74HC4066 PDF

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
74HC/HCT4066
Quad bilateral switches
Product specification 1998 Nov 10
Supersedes data of 1998 Oct 02
File under Integrated Circuits, IC06
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4066
FEATURES The 74HC/HCT4066 have four independent analog

switches. Each switch has two input/output terminals (nY,
• Very low “ON” resistance:
nZ) and an active HIGH enable input (nE). When nE is
50 Ω (typ.) at VCC = 4.5 V
LOW the belonging analog switch is turned off.
45 Ω (typ.) at VCC = 6.0 V
35 Ω (typ.) at VCC = 9.0 V The “4066” is pin compatible with the “4016” but exhibits a
• Output capability: non-standard much lower “ON” resistance. In addition, the “ON”
resistance is relatively constant over the full input signal
• ICC category: SSI. range.
GENERAL DESCRIPTION
The 74HC/HCT4066 are high-speed Si-gate CMOS
devices and are pin compatible with the “4066” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL PARAMETER CONDITIONS UNIT
HC HCT
tPZH/ tPZL turn-on time nE to Vos CL = 15 pF; RL = 1 kΩ; VCC = 5 V 11 12 ns
tPHZ/ tPLZ turn-off time nE to Vos 13 16 ns
CI input capacitance 3.5 3.5 pF
CPD power dissipation capacitance per switch notes 1 and 2 11 12 pF
CS max. switch capacitance 8 8 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
a) PD = CPD × VCC2 × fi + ∑ {(CL + CS) × VCC2 × fo} where:
b) fi = input frequency in MHz
c) fo = output frequency in MHz
d) ∑ {(CL + CS) × VCC2 × fo} = sum of outputs
e) CL = output load capacitance in pF
f) CS = maximum switch capacitance in pF
g) VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
1998 Nov 10 2
ORDERING INFORMATION
TYPE PACKAGE
NUMBER NAME DESCRIPTION VERSION
74HC4066 DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HC4066 SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HC4066 SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
74HC4066 TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
74HCT4066 DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT4066 SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HCT4066 SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
74HCT4066 TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION

1, 4, 8, 11 1Y to 4Y independent inputs/outputs
2, 3, 9, 10 1Z to 4Z independent inputs/outputs
7 GND ground (0 V)
13, 5, 6, 12 1E to 4E enable inputs (active HIGH)
14 VCC positive supply voltage
handbook, halfpage handbook, halfpage

1Y 1 14 VCC 1Y 1
13 1E
1Z 2
1Z 2 13 1E
2Y 4
2Z 3 12 4E 5 2E
2Z 3
2Y 4 4066 11 4Y
3Y 8
6 3E
2E 5 10 4Z 3Z 9
3E 6 9 3Z 4Y 11
12 4E
4Z 10
GND 7 8 3Y
MGR254
MGR253
Fig.1 Pin configuration. Fig.2 Logic symbol.
1998 Nov 10 3
handbook, halfpage 1 2 handbook, halfpage 1 2

1 1
13 # 13 #
X1
4 3
4 3
1 1
5 #
5 #
X1
8 9
6 # 8 9
1 1
11 10 6 #
X1
12 #
11 10
1 1
MGR255
12 #
X1
MGR256
a. b.
Fig.3 IEC logic symbol.
FUNCTION TABLE
INPUT NE SWITCH
L off
H on
Note
1. H = HIGH voltage level; L = LOW voltage level.
handbook, halfpage13 1 5 4 6 8 12 11
1E 1Y 2E 2Y 3E 3Y 4E 4Y
handbook, halfpage nY
1Z 2Z 3Z 4Z
2 3 9 10
MGR257 nE
VCC VCC
GND nZ MGR258
Fig.4 Functional diagram. Fig.5 Schematic diagram (one switch).
1998 Nov 10 4
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134) Voltages are referenced to GND
(GND = 0 V)
SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS
VCC DC supply voltage −0.5 +11.0 V
±IIK DC digital input diode current 20 mA for VI < − 0.5 V or VI > VCC + 0.5 V
±ISK DC switch diode current 20 mA for VS < − 0.5 V or VS > VCC + 0.5 V
±IIS DC switch current 25 mA for −0.5 V < VS < VCC + 0.5 V
±ICC; DC VCC or GND current 50 mA
±IGND
Tstg storage temperature range −65 +150 °C
Ptot power dissipation per package for temperature range: −40 to +125 °C
74HC/HCT
plastic DIL 750 mW above +70 °C: derate linearly with 12 mW/K
plastic mini-pack (SO) 500 mW above +70 °C: derate linearly with 8 mW/K
PS power dissipation per switch 100 mW
Note
1. To avoid drawing VCC current out of terminal nZ, when switch current flows in terminal nY, the voltage drop across
the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current will flow
out of terminal nY. In this case there is no limit for the voltage drop across the switch, but the voltages at nY and nZ
may not exceed VCC or GND.
RECOMMENDED OPERATING CONDITIONS
74HC 74HCT
SYMBOL PARAMETER UNIT CONDITIONS
min. typ. max. min. typ. max.
VCC DC supply voltage 2.0 5.0 10.0 4.5 5.0 5.5 V
VI DC input voltage range GND VCC GND VCC V
VS DC switch voltage range GND VCC GND VCC V
Tamb operating ambient −40 +85 −40 +85 °C see DC and AC
temperature range CHARACTERISTICS
Tamb operating ambient −40 +125 −40 +125 °C
temperature range
tr, tf input rise and fall times 6.0 1000 6.0 500 ns VCC = 2.0 V
500 VCC = 4.5 V
400 VCC = 6.0 V
250 VCC = 10.0 V
1998 Nov 10 5
DC CHARACTERISTICS FOR 74HC/HCT

For 74HC: VCC = 2.0, 4.5, 6.0 and 9.0 V; For 74HCT: VCC = 4.5 V
Tamb (°C) TEST CONDITIONS

74HC/HCT
SYMBOL PARAMETER UNIT V IS
+25 −40 to +85 −40 to +125 CC
VIS VI
(V) (µA)
min. typ. max. min. max. min. max.
RON ON-resistance (peak) − − − − Ω 2.0 100 VCC VIH
54 95 118 142 Ω 4.5 1000 to or
GND VIL
42 84 105 126 Ω 6.0 1000
32 70 88 105 Ω 9.0 1000
RON ON-resistance (rail) 80 − − − Ω 2.0 100 GND VIH
35 75 95 115 Ω 4.5 1000 or
VIL
27 65 82 100 Ω 6.0 1000
20 55 70 85 Ω 9.0 1000
RON ON-resistance (rail) 100 − − − Ω 2.0 100 VCC VIH
42 80 106 128 Ω 4.5 1000 or
VIL
35 75 94 113 Ω 6.0 1000
27 60 78 95 Ω 9.0 1000
∆RON maximum variation of − Ω 2.0 VCC VIH
ON-resistance between 5 Ω 4.5 to or
any two channels GND VIL
4 Ω 6.0
3 Ω 9.0
Note
1. At supply voltages approaching 2 V, the analog switch ON-resistance becomes extremely non-linear. Therefore it is
recommended that these devices be used to transmit digital signals only, when using these supply voltages.
1998 Nov 10 6
dbook, full pagewidth

HIGH
(from enable inputs)
V
nY
nZ
Vis = 0 to VCC − GND Iis
GND
MGR259
Fig.6 Test circuit for measuring ON-resistance (RON).
handbook, full pagewidth LOW

nY nZ
VI = VCC or GND A A VO = GND or VCC
GND
MGR260
Fig.7 Test circuit for measuring OFF-state current.
handbook, full pagewidth HIGH

nY nZ
VI = VCC or GND A A VO (open circuit)
GND
MGR261
Fig.8 Test circuit for measuring ON-state current.
1998 Nov 10 7
MGR262
60
handbook, halfpage
RON
(Ω) VCC = 4.5 V
50
6V
40
9V
30
20
10
0 1.8 3.6 5.4 7.2 9
Vis (V)
Fig.9 Typical ON-resistance (RON) as a function of input voltage (Vis) for Vis = 0 to VCC.
1998 Nov 10 8
DC CHARACTERISTICS FOR 74HC

Voltage are referenced to GND (ground = 0 V)
74HC
SYMBOL PARAMETER −40 to UNIT V VI OTHER
+25 −40 to +85 CC
+125 (V)
min. typ. max. min. max. min. max
VIH HIGH-level input 1.5 1.2 1.5 1.5 V 2.0
voltage 3.15 2.4 3.15 3.15 4.5
4.2 3.2 4.2 4.2 6.0
6.3 4.7 6.3 6.3 9.0
VIL LOW-level input 0.8 0.50 0.50 0.50 V 2.0
voltage 2.1 1.35 1.35 1.35 4.5
2.8 1.80 1.80 1.80 6.0
4.3 2.70 2.70 2.70 9.0
±II input leakage 0.1 1.0 1.0 µA 6.0 VCC
current 0.2 2.0 2.0 10.0 or
GND
±IS analog switch 0.1 1.0 1.0 µA 10.0 VIH VS = VCC − GND
OFF-state or (see Fig.7)
current per VIL
channel
ON-state current or (see Fig.8)
VIL
ICC quiescent 2.0 20.0 40.0 µA 6.0 VCC Vis = GND or
supply current 4.0 40.0 80.0 10.0 or VCC;
GND Vos = VCC or
GND
1998 Nov 10 9
AC CHARACTERISTICS FOR 74HC

GND = 0 V; tr = tf = 6 ns; CL = 50 pF

74HC
SYMBOL PARAMETER UNIT V OTHER
+25 −40 to +85 −40 to +125 CC
(V)
tPHL/tPLH propagation delay 8 60 75 90 ns 2.0 RL = ∞;
Vis to Vos 3 12 15 18 4.5 CL = 50 pF
(see Fig.18)
2 10 13 15 6.0
2 8 10 12 9.0
tPZH/tPZL turn-on time 36 100 125 150 ns 2.0 RL = 1 kΩ;
nE to Vos 13 20 25 30 4.5 CL = 50 pF
(see Figs 19
10 17 21 26 6.0
and 20)
8 13 16 20 9.0
tPHZ/tPLZ turn-off time 44 150 190 225 ns 2.0 RL = 1 kΩ;
nE to Vos 16 30 38 45 4.5 CL = 50 pF
(see Figs 19
13 26 33 38 6.0
and 20)
16 24 16 20 9.0
1998 Nov 10 10
DC CHARACTERISTICS FOR 74HCT

Voltages are referenced to GND (ground = 0 V)
74HCT
SYMBOL PARAMETER UNIT V
+25 −40 to +85 −40 to +125 CC
VI OTHER
(V)
VIH HIGH-level 2.0 1.6 2.0 2.0 V 4.5
input voltage to
5.5
VIL LOW-level 1.2 0.8 0.8 0.8 V 4.5
input voltage to
5.5
±II input leakage 0.1 1.0 1.0 µA 5.5 VCC
current or
GND
OFF-state or (see Fig.7)
current per VIL
channel
ON-state or (see Fig.8)
current VIL
ICC quiescent 2.0 20.0 40.0 µA 4.5 VCC Vis = GND or
supply current to or VCC; Vos = VCC or
5.5 GND GND
∆ICC additional 100 360 450 490 µA 4.5 VCC − other inputs at
quiescent to 2.1 V VCC or GND
supply current 5.5
per input pin
for unit load
coefficient is 1
(note 1)
Note
1. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given here. To determine ∆ICC per input,
multiply this value by the unit load coefficient shown in the table below.
Table 1
INPUT UNIT LOAD COEFFICIENT
nE 1.00
1998 Nov 10 11
AC CHARACTERISTICS FOR 74HCT

GND = 0 V; tr = tf = 6 ns

74HCT
SYMBOL PARAMETER UNIT V OTHER
+25 −40 to +85 −40 to +125 CC
(V)
tPHL/tPLH propagation 3 12 15 18 ns 4.5 RL = ∞; CL = 50 pF
delay Vis to Vos (see Fig.18)
tPZH/tPZL turn-on time 12 24 30 36 ns 4.5 RL = 1 kΩ; CL = 50 pF
nE to Vos (see Figs 19 and 20)
tPHZ/tPLZ turn-off time 20 35 44 53 ns 4.5 RL = 1 kΩ; CL = 50 pF
nE to Vos (see Figs 19 and 20)
ADDITIONAL AC CHARACTERISTICS FOR 74HC/HCT

Recommended conditions and typical values GND = 0 V; tr = tf = 6 ns
VCC VIS(p−p)
SYMBOL PARAMETER TYP. UNIT CONDITIONS
(V) (V)
sine wave distortion f = 1 kHz 0.04 % 4.5 4.0 RL = 10 kΩ; CL = 50 pF
0.02 % 9.0 8.0 (see Fig.16)
sine wave distortion f = 10 kHz 0.12 % 4.5 4.0 RL = 10 kΩ; CL = 50 pF
0.06 % 9.0 8.0 (see Fig.16)
switch “OFF” signal feed-through −50 dB 4.5 note 3 RL = 600 Ω; CL = 50 pF;
−50 dB 9.0 f = 1 MHz (see Figs 10 and 17)
crosstalk between any two −60 dB 4.5 note 3 RL = 600 Ω; CL = 50 pF;
switches −60 dB 9.0 f = 1 MHz (see Fig.12)
V(p−p) crosstalk voltage between enable 110 mV 4.5 RL = 600 Ω; CL = 50 pF;
or address input to any switch 220 mV 9.0 f = 1 MHz (nE, square wave
(peak-to-peak value) between VCC and GND,
tr = tf = 6 ns) (see Fig.14)
fmax minimum frequency response 180 MHz 4.5 note 4 RL = 50 Ω; CL = 10 pF
(−3 dB) 200 MHz 9.0 (see Figs 11 and 15)
CS maximum switch capacitance 8 pF
Notes
1. Vis is the input voltage at nY or nZ terminal, whichever is assigned as an input.
2. Vos is the output voltage at nY or nZ terminal, whichever is assigned as an output.
3. Adjust input voltage Vis is 0 dBM level (0 dBM = 1 mW into 600 Ω).
4. Adjust input voltage Vis is 0 dBM level at Vos for 1 MHz (0 dBM = 1 mW into 50 Ω).
1998 Nov 10 12
MGR263
0
handbook, full pagewidth
(dB)
−20
−40
−60
−80
−100
10 102 103 104 105 106
f (kHz)
Test conditions: VCC = 4.5 V; GND = 0 V; RL = 50 Ω; Rsource = 1 kΩ.
Fig.10 Typical switch “OFF” signal feed-through as a function of frequency.
MGR264
5
handbook, full pagewidth
(dB)
−5
10 102 103 104 105 106
f (kHz)
Test conditions: VCC = 4.5 V; GND = 0 V; RL = 50 Ω; Rsource = 1 kΩ.
Fig.11 Typical frequency response.
1998 Nov 10 13
handbook, full pagewidth VCC
2RL
0.1 µF
nY/nZ nZ/nY
Vi
RL
2RL CL
channel
GND
ON
MGM265
Fig.12 Test circuit for measuring crosstalk between any two switches; channel ON condition.
handbook, full pagewidth VCC VCC
2RL 2RL
nY/nZ nZ/nY
Vos
2RL 2RL CL dB
channel
OFF
GND
MGR266
Fig.13 Test circuit for measuring crosstalk between any two switches; channel OFF condition.
The crosstalk is defined as follows

handbook, full pagewidth VCC nE VCC
(oscilloscope output): VCC
2RL GND 2RL
fpage nY/nZ nZ/nY
D.U.T. Vos
V(p-p)
2RL 2RL CL oscilloscope
MGR267
GND
MGR268
Fig.14 Test circuit for measuring crosstalk between control and any switch.
1998 Nov 10 14
2RL
0.1 µF
nY/nZ nZ/nY
Vis Vos
sine-wave
2RL CL dB
channel
GND
ON
MGR269
Adjust input voltage to obtain 0 dBM at Vos when fin = 1 MHz. After set-up frequency of fin is increased to obtain a reading of −3 dB at Vos.
Fig.15 Test circuit for measuring minimum frequency response.
2RL
10 µF
nY/nZ nZ/nY
fin = 1 kHz Vis Vos
sine-wave
DISTORTION
2RL CL
METER
channel
ON GND
MGR270
Fig.16 Test circuit for measuring sine wave distortion.
2RL
0.1 µF
nY/nZ nZ/nY
Vis Vos
2RL CL dB
channel
GND
OFF
MGR271
Fig.17 Test circuit for measuring switch “OFF” signal feed-through.
1998 Nov 10 15
AC WAVEFORMS
handbook, full pagewidth tr tf

VCC
90%
Vis 50%
10%
GND
Vos 50%
tPLH tPHL
MGR272
(1) HC: VM = 50%; VI = GND to VCC; HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.18 Waveforms showing the input (Vis) to output (Vos) propagation delays.
tf tr
90 %
nE INPUT V M (1)
10 %
t PLZ t PZL
OUTPUT
LOW - to - OFF 50 %
OFF - to - LOW
10 %
t PHZ t PZH
90 %
OUTPUT
HIGH - to - OFF 50 %
OFF - to - HIGH
outputs outputs outputs

MGA846 enabled disabled enabled
Fig.19 Waveforms showing the turn-on and turn-off times.
TEST CIRCUIT AND WAVEFORMS
handbook, full pagewidth VCC Vis VCC
VI VO RL switch
PULSE
D.U.T. open
GENERATOR
RT CL
GND
MGR273
Fig.20 Test circuit for measuring AC performance.
1998 Nov 10 16
Table 2 Conditions
TEST SWITCH VIS

tPZH GND VCC
tPZL VCC GND
tPHZ GND VCC
tPLZ VCC GND
others open pulse
Table 3 Definitions for Figs 20 and 21:

SYMBOL DEFINITION
CL load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values)
RT termination resistance should be equal to the output impedance ZO of the pulse generator
tr tf = 6 ns, when measuring fmax, there is no constraint on tr, tf with 50% duty factor
handbook, full pagewidth tW

AMPLITUDE
90%
NEGATIVE
VM
INPUT PULSE
10%
0V
tTHL (tf) tTLH (tr)
tTLH (tr) tTHL (tf)
AMPLITUDE
90%
POSITIVE
VM
INPUT PULSE
10%
0V
tW MGR274
Fig.21 Input pulse definitions.
Table 4
tr; tf
FAMILY AMPLITUDE VM fmax;
OTHER
PULSE WIDTH
74HC VCC 50% < 2 ns 6 ns
74HCT 3.0 V 1.3 V < 2 ns 6 ns
1998 Nov 10 17
PACKAGE OUTLINES
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
D ME
seating plane
A2 A
L A1
c
Z e w M
b1
(e 1)
b
14 8 MH
pin 1 index
E
1 7
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A A1 A2
b b1 c D (1) E (1) e e1 L ME MH w Z (1)
max. min. max. max.
1.73 0.53 0.36 19.50 6.48 3.60 8.25 10.0
mm 4.2 0.51 3.2 2.54 7.62 0.254 2.2
1.13 0.38 0.23 18.55 6.20 3.05 7.80 8.3
0.068 0.021 0.014 0.77 0.26 0.14 0.32 0.39
inches 0.17 0.020 0.13 0.10 0.30 0.01 0.087
0.044 0.015 0.009 0.73 0.24 0.12 0.31 0.33
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION
92-11-17
SOT27-1 050G04 MO-001AA
95-03-11
1998 Nov 10 18
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
D E A
X
y HE v M A
14 8
Q
A2
(A 3) A
A1
pin 1 index
θ
Lp
1 7 L
e w M detail X
bp
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 o
0.10 1.25 0.36 0.19 8.55 3.8 5.8 0.4 0.6 0.3 8
0.010 0.057 0.019 0.0100 0.35 0.16 0.244 0.039 0.028 0.028 0o
inches 0.069 0.01 0.050 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.34 0.15 0.228 0.016 0.024 0.012
Note

ISSUE DATE
95-01-23
SOT108-1 076E06S MS-012AB
97-05-22
1998 Nov 10 19
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
D E A
X
c
y HE v M A
14 8
Q
A2 A
A1 (A 3)
pin 1 index
θ
Lp
L
1 7 detail X
w M
e bp
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.
o
0.21 1.80 0.38 0.20 6.4 5.4 7.9 1.03 0.9 1.4 8
mm 2.0 0.25 0.65 1.25 0.2 0.13 0.1
0.05 1.65 0.25 0.09 6.0 5.2 7.6 0.63 0.7 0.9 0o
Note

ISSUE DATE
95-02-04
SOT337-1 MO-150AB
96-01-18
1998 Nov 10 20
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
D E A
X
y HE v M A
14 8
Q
A2 (A 3)
A
A1
pin 1 index
θ
Lp
L
1 7
detail X
w M
e bp
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ
max.
o
0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.72 8
mm 1.10 0.25 0.65 1.0 0.2 0.13 0.1
0.05 0.80 0.19 0.1 4.9 4.3 6.2 0.50 0.3 0.38 0o
Notes
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

ISSUE DATE
94-07-12
SOT402-1 MO-153
95-04-04
1998 Nov 10 21
SOLDERING Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the
Introduction
packages should preferable be kept below 230 °C.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in WAVE SOLDERING
our “Data Handbook IC26; Integrated Circuit Packages”
Conventional single wave soldering is not recommended
(document order number 9398 652 90011).
for surface mount devices (SMDs) or printed-circuit boards
There is no soldering method that is ideal for all IC with a high component density, as solder bridging and
packages. Wave soldering is often preferred when non-wetting can present major problems.
through-hole and surface mount components are mixed on
To overcome these problems the double-wave soldering
one printed-circuit board. However, wave soldering is not
method was specifically developed.
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations If wave soldering is used the following conditions must be
reflow soldering is often used. observed for optimal results:
• Use a double-wave soldering method comprising a
Through-hole mount packages turbulent wave with high upward pressure followed by a
SOLDERING BY DIPPING OR BY SOLDER WAVE smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact – larger than or equal to 1.27 mm, the footprint
with the joints for more than 5 seconds. The total contact longitudinal axis is preferred to be parallel to the
time of successive solder waves must not exceed transport direction of the printed-circuit board;
5 seconds. – smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
The device may be mounted up to the seating plane, but
printed-circuit board.
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg(max)). If the The footprint must incorporate solder thieves at the
printed-circuit board has been pre-heated, forced cooling downstream end.
may be necessary immediately after soldering to keep the • For packages with leads on four sides, the footprint must
temperature within the permissible limit. be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
MANUAL SOLDERING solder thieves downstream and at the side corners.
Apply the soldering iron (24 V or less) to the lead(s) of the During placement and before soldering, the package must
package, either below the seating plane or not more than be fixed with a droplet of adhesive. The adhesive can be
2 mm above it. If the temperature of the soldering iron bit applied by screen printing, pin transfer or syringe
is less than 300 °C it may remain in contact for up to dispensing. The package can be soldered after the
10 seconds. If the bit temperature is between adhesive is cured.
300 and 400 °C, contact may be up to 5 seconds.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
Surface mount packages
of corrosive residues in most applications.
REFLOW SOLDERING
MANUAL SOLDERING
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied Fix the component by first soldering two
to the printed-circuit board by screen printing, stencilling or diagonally-opposite end leads. Use a low voltage (24 V or
pressure-syringe dispensing before package placement. less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
Several methods exist for reflowing; for example,
300 °C.
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary When using a dedicated tool, all other leads can be
between 100 and 200 seconds depending on heating soldered in one operation within 2 to 5 seconds between
method. 270 and 320 °C.
1998 Nov 10 22
Suitability of IC packages for wave, reflow and dipping soldering methods
SOLDERING METHOD
MOUNTING PACKAGE
WAVE REFLOW(1) DIPPING
Through-hole mount DBS, DIP, HDIP, SDIP, SIL suitable(2) − suitable
Surface mount HLQFP, HSQFP, HSOP, SMS not suitable(3) suitable −
PLCC(4), SO suitable suitable −
LQFP, QFP, TQFP not recommended(4)(5) suitable −
SQFP not suitable suitable −
SSOP, TSSOP, VSO not recommended(6) suitable −
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Nov 10 23
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© Philips Electronics N.V. 1998 SCA60

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands 245106/00/03/pp24 Date of release: 1998 Nov 10 Document order number: 9397 750 04779
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.

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INTEGRATED CIRCUITS

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

Quad bilateral switches 74HC/HCT4066

FEATURES The 74HC/HCT4066 have four independent analog

QUICK REFERENCE DATA

Quad bilateral switches 74HC/HCT4066

PIN NO. SYMBOL NAME AND FUNCTION

handbook, halfpage handbook, halfpage

Fig.1 Pin configuration. Fig.2 Logic symbol.

Quad bilateral switches 74HC/HCT4066

handbook, halfpage 1 2 handbook, halfpage 1 2

Fig.3 IEC logic symbol.

Fig.4 Functional diagram. Fig.5 Schematic diagram (one switch).

Quad bilateral switches 74HC/HCT4066

RECOMMENDED OPERATING CONDITIONS

Quad bilateral switches 74HC/HCT4066

DC CHARACTERISTICS FOR 74HC/HCT

Tamb (°C) TEST CONDITIONS

Quad bilateral switches 74HC/HCT4066

dbook, full pagewidth

Vis = 0 to VCC − GND Iis

Fig.6 Test circuit for measuring ON-resistance (RON).

handbook, full pagewidth LOW

Fig.7 Test circuit for measuring OFF-state current.

handbook, full pagewidth HIGH

Fig.8 Test circuit for measuring ON-state current.

Quad bilateral switches 74HC/HCT4066

Quad bilateral switches 74HC/HCT4066

DC CHARACTERISTICS FOR 74HC

Quad bilateral switches 74HC/HCT4066

AC CHARACTERISTICS FOR 74HC

Tamb (°C) TEST CONDITIONS

Quad bilateral switches 74HC/HCT4066

DC CHARACTERISTICS FOR 74HCT

Quad bilateral switches 74HC/HCT4066

AC CHARACTERISTICS FOR 74HCT

Tamb (°C) TEST CONDITIONS

ADDITIONAL AC CHARACTERISTICS FOR 74HC/HCT

Quad bilateral switches 74HC/HCT4066

Test conditions: VCC = 4.5 V; GND = 0 V; RL = 50 Ω; Rsource = 1 kΩ.

Fig.10 Typical switch “OFF” signal feed-through as a function of frequency.

Test conditions: VCC = 4.5 V; GND = 0 V; RL = 50 Ω; Rsource = 1 kΩ.

Fig.11 Typical frequency response.

Quad bilateral switches 74HC/HCT4066

handbook, full pagewidth VCC

handbook, full pagewidth VCC VCC

The crosstalk is defined as follows

Quad bilateral switches 74HC/HCT4066

handbook, full pagewidth VCC

Fig.15 Test circuit for measuring minimum frequency response.

handbook, full pagewidth VCC

Fig.16 Test circuit for measuring sine wave distortion.

handbook, full pagewidth VCC

Fig.17 Test circuit for measuring switch “OFF” signal feed-through.

Quad bilateral switches 74HC/HCT4066

handbook, full pagewidth tr tf

(1) HC: VM = 50%; VI = GND to VCC; HCT: VM = 1.3 V; VI = GND to 3 V.

outputs outputs outputs

Fig.19 Waveforms showing the turn-on and turn-off times.