Lecture 7: ARM Arithmetic and Bitwise Instructions
Lecture 7: ARM Arithmetic and Bitwise Instructions
Lecture 7: ARM Arithmetic and Bitwise Instructions
Instructions
B. 0 to 255
What is a likely range for immediates in
the immediate addressing mode
A. 0 to (232-1)
§ Example:
§ in C: a = b * c;
§ in ARM:
let b be r2; let c be r3; and let a be r0 and r1 (since it may be up to 64 bits)
MUL r0, r2, r3 ; b*c only 32 bits stored
Note: Often, we only care about the lower half of the product.
§ 64-bit multiply instructions offer both signed and unsigned versions
§ For these instruction there are 2 destination registers
B. Instructions
C. Numbers
D. Strings
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Logical Operations operate on
A. Bits
B. Instructions
C. Numbers
D. Strings
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Logical Operators
v In
general, can define them to accept >2 inputs,
but in the case of ARM assembly, both of these
accept exactly 2 inputs and produce 1 output
v Again, rigid syntax, simpler hardware
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Logical Operators
v Truth Table: standard table listing all possible
combinations of inputs and resultant output for each
v Truth Table for AND, OR and XOR
A AND (NOT B)
A B A AND B A OR B A XOR B A BIC B
0 0 0 0 0 0
0 1 0 1 1 0
1 0 0 1 1 1
1 1 1 1 0 0
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Bitwise Logic Instruction Syntax
v Syntax of Instructions:
1 2, 3, 4
where:
1) instruction by name
2) operand getting result (“destination”)
3) 1st operand for operation (“source1”)
4) 2nd operand for operation (“source2”)
v Syntax is rigid (for the most part):
v 1operator, 3 operands
v Why? Keep Hardware simple via regularity
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Bitwise Logic Operations
v Bitwise AND in Assembly
v Example: AND r0,r1,r2 (in ARM)
Equivalent to: r0 = r1 & r2 (in C)
v Bitwise OR in Assembly
v Example: ORR r3, r4, r5 (in ARM)
Equivalent to: r3 = r4 | r5 (in C)
v Bitwise XOR in Assembly
v Example: EOR r0,r1,r2 (in ARM)
Equivalent to: r0 = r1 ^ r2 (in C)
v Bitwise Clear in Assembly
v Example: BIC r3, r4, r5 (in ARM)
Equivalent to: r3 = r4 & (!r5) (in C)
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Bit wise operations
r0: 01101001
r1: 11000111
__________
ORR r3, r0,r1; r3: 11101111
AND r3,r0,r1; r3: 01000001
EOR r3,r0,r1; r3: 10101110
BIC r3, r0, r1; r3: 00101000
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Uses for Logical Operators
v Note that ANDing a bit with 0 produces a 0 at the
output while ANDing a bit with 1 produces the
original bit.
v This can be used to create a mask.
v Example:
1011 0110 1010 0100 0011 1101 1001 1010
mask: 0000 0000 0000 0000 0000 1111 1111 1111
v The result of ANDing these:
0000 0000 0000 0000 0000 1101 1001 1010
mask last 12 bits
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Uses for Logical Operators
v Similarly,note that ORing a bit with 1
produces a 1 at the output while ORing a bit
with 0 produces the original bit.
v This can be used to force certain bits of a
string to 1s.
v Forexample, 0x12345678 OR 0x0000FFF
results in 0x1234FFFF (e.g. the high-order 16
bits are untouched, while the low-order 16 bits
are forced to 1s).
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Invert bits 0-2 of x
A. x AND 00000111
B. x OR 00000111
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Invert bits 0-2 of x
A. x AND 00000111
B. x OR 00000111
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Uses for Logical Operators
v Finally,note that BICing a bit with 1 resets
the bit (sets to 0) at the output while BICing
a bit with 0 produces the original bit.
v This can be used to force certain bits of a
string to 0s.
v Forexample, 0x12345678 OR 0x0000FFFF
results in 0x12340000 (e.g. the high-order 16
bits are untouched, while the low-order 16 bits
are forced to 0s).
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Find the 1's complement of x
A. x XOR 00000000
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Find the 1's complement of x
A. x XOR 00000000
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Assignment Instructions
v Assignment in Assembly
v Example: MOV r0,r1 (in ARM)
Equivalent to: a = b (in C)
where ARM registers r0, r1 are associated with C
variables a & b
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Assignment Instructions
v MVN – Move Negative – moves one’s
complement of the operand into the register.
v Assignment in Assembly
v Example: MVN r0,#0 (in ARM)
Equivalent to: a = -1 (in C)
where ARM registers r0 are associated with C
variables a
Since ~0x00000000 == 0xFFFFFFFF
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Conclusion
§ In ARM Assembly Language:
§ Registers replace C variables
§ One Instruction (simple operation) per line
§ Simpler is Better
§ Smaller is Faster
§ Instructions so far:
§ ADD, SUB, MUL, MULA, [U|S]MULL, [U|
S]MLAL
§ Registers:
§ Places for general variables: r0-r12