Foxconn 748a01 Rev A

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5 4 3 2 1

Foxconn Precision Co.Inc.


Date:2004/03/ 01
D
748A01 D

PAGE INDEX
01. Index Page 25. SIS964-PCI, IDE, MUTIOL
02 . Topology 26. SIS964-LPC /MII/GPIO
0 3. Reset Map 27. SIS964-USB , SATA
04. Clock Dist ribution 28. SIS964-PO WER
05. Power Deli very Map 29. PCI 1&2.S CH
06. C PU-1 30. PCI 3&4.S CH
C 07. C PU-2 31 . PCI5.SCH C

08. C PU-3 32. VT6307


09. ISL6563 V CCP 33. USB Header & 1394 Port
10. ISL6563 V CCP 3 4. LAN POWER
11. 748-1(Host /AGP) 35. RTL8110S/R TL8100C
12. 748-2 Mem ory 36. LAN & USB PORT
13. 748-3 MuTI OL/Other 37. IDE.SCH
14. 748-4 Pow er 38. AC97 CODEC .SCH
15. 2.5V_DDR & 1.25V_VTT 39 . AC97 I/O
B 16. SB1.8V & SB 3V & 5V_DUAL 40. ITE8705 B

17. 1D8V_VCC & VDDQ 41. Keyboard M ouse.SCH


18. Hardware T rap* 42. FAN HW Mon itor
19. Main Clock Generator 43. BIOS/FLOP PY
20. Clock Buffe r-1(3DDR/MIX) 44. COM/PRT P ORT
21. DDR/MIX DI MM1,2 45. Power BTN/R TC Batt.SCH
22. DDR/MIX DI MM3 46. Power Conn ector
23. SSTL-2 Term ination Res 47. GPIO Sett ing
24. AGP.SCH 48. Change li st
A A

TECHNOLOGY COPR.
Title
Index
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 1 of 48
5 4 3 2 1
5 4 3 2 1

AMD K7

D D

Host Bus

DDR SDRAM
AGP SLOT CHANNEL A
SiS748
CHANNEL B

PCI Slot 1 Gigabit LAN

MuTIOL 1G
C
RJ45 C

PCI Slot 2
LAN PHY
PCI Slot 3
AC'97 Audio I/O
PCI Slot 4
Audio Codec
PCI Slot 5
SiS964 SATA1,2
ATA 66/100/133
IDE 1
KEYBOARD PS/2
IDE 2 /MOUSE
Back Panel Front Panel
B B

USB 0
LPC Bus USB 4
USB 1 USB 5
FAN 1 USB 2 USB 6
Media
FAN CONTROL USB 3 USB 7
Interface
FAN 2 VOLTAGE MONITOR
FAN 3 LPC Super I/O TEMPERATURE MONITOR
ISA Bus
ISA ROM

A A

IR PARALLEL FLOPPY
TECHNOLOGY COPR.
Title
Topology
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 2 of 48
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

TECHNOLOGY COPR.
Title
Reset Map
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 3 of 48
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

TECHNOLOGY COPR.
Title
Clock Distribution
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 4 of 48
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

TECHNOLOGY COPR.
Title
Power Delivery Map
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 5 of 48
5 4 3 2 1
8 7 6 5 4 3 2 1
L1 L2
SDATAINCLKJ[0..3] L0603 4.7nH L0603 4.7nH
11 SDATAINCLKJ[0..3] ADINCLKJ 1 2 1 2 SADDINCLKJ SADDINCLKJ 11
SDATAOUTCLKJ[0..3]
11 SDATAOUTCLKJ[0..3] 10/10 BC1
SADDINJ[2..14]
11 SADDINJ[2..14] THERMDA
THERMDA 40,42
* 2.7pF
50V, NPO, +/-0.25pF
SADDOUTJ[2..14] C0603
11 SADDOUTJ[2..14]
SDATAJ[0..63]
THERMDC
THERMDC 42
4.7nH
11 SDATAJ[0..63]

D D

AC31

AD30
AA31
W31

AD8
G11
G13
G19
G21
G27
G29
G31

Q31
H10
H28
H30
H32

N31

U31
K30

S31

Y31
F30

L31
J31

W7
H6
H8

U7
VCCP

K8

S7

Y5
F8
U1A

J5
SDATAJ0 AA35 AJ33 ADINCLKJ

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
SDATAJ1 SYSDATA#0 SYSADDINCLK# R1 680 +/-5%
W37 SYSDATA#1
SDATAJ2 W35 AJ29 SADDINJ0
SDATAJ3 SYSDATA#2 SYSADDIN#0 SADDINJ1
Y35 SYSDATA#3 SYSADDIN#1 AL29
SDATAJ4 U35 AG33 SADDINJ2
SDATAJ5 SYSDATA#4 SYSADDIN#2 SADDINJ3 R2 680 +/-5%
U33 SYSDATA#5 SYSADDIN#3 AJ37
SDATAJ6 S37 AL35 SADDINJ4
SDATAJ7 SYSDATA#6 SYSADDIN#4 SADDINJ5
S33 SYSDATA#7 SYSADDIN#5 AE33
SDATAJ8 AA33 AJ35 SADDINJ6
SDATAJ9 SYSDATA#8 SYSADDIN#6 SADDINJ7
AE37 SYSDATA#9 SYSADDIN#7 AG37
SDATAJ10 AC33 AL33 SADDINJ8
SDATAJ11 SYSDATA#10 SYSADDIN#8 SADDINJ9
AC37 SYSDATA#11 SYSADDIN#9 AN37
SDATAJ12
SDATAJ13
SDATAJ14
Y37
AA37
AC35
SYSDATA#12
SYSDATA#13
SOCKETA-1 SYSADDIN#10
SYSADDIN#11
AL37
AG35
AN29
SADDINJ10
SADDINJ11
SADDINJ12
SDATAJ15 SYSDATA#14 SYSADDIN#12 SADDINJ13
S35 SYSDATA#15 SYSADDIN#13 AN35
SDATAJ16 Q37 AN31 SADDINJ14
SDATAJ17 SYSDATA#16 SYSADDIN#14
Q35 SYSDATA#17
SDATAJ18 N37
SDATAJ19 SYSDATA#18 SADDOUTCLKJ
J33 SYSDATA#19 SYSADDOUTCLK# E3 SADDOUTCLKJ 11
SDATAJ20 G33
SDATAJ21 SYSDATA#20
G37 SYSDATA#21 SYSADDOUT#0 J1
SDATAJ22 E37 VID[4:0] VCC_CORE VID[4:0] VCC_CORE J3
SDATAJ23 SYSDATA#22 SYSADDOUT#1 SADDOUTJ2
G35 SYSDATA#23 SYSADDOUT#2 C7
SDATAJ24 Q33 A7 SADDOUTJ3
SDATAJ25 SYSDATA#24 00000 1.850 10000 1.450 SYSADDOUT#3 SADDOUTJ4
N33 SYSDATA#25 SYSADDOUT#4 E5
C SDATAJ26
SDATAJ27
L33
N35
SYSDATA#26 00001 1.825 10001 1.425 SYSADDOUT#5 A5
E7
SADDOUTJ5
SADDOUTJ6 C
SDATAJ28 SYSDATA#27 SYSADDOUT#6 SADDOUTJ7
L37 SYSDATA#28 SYSADDOUT#7 C1
SDATAJ29 J37 00010 1.800 10010 1.400 C5 SADDOUTJ8
SDATAJ30 SYSDATA#29 SYSADDOUT#8 SADDOUTJ9
A37 SYSDATA#30 SYSADDOUT#9 C3
SDATAJ31 E35 00011 1.775 10011 1.375 G1 SADDOUTJ10
SDATAJ32 SYSDATA#31 SYSADDOUT#10 SADDOUTJ11
E31 SYSDATA#32 SYSADDOUT#11 E1
SDATAJ33 E29 00100 1.750 10100 1.350 A3 SADDOUTJ12
SDATAJ34 SYSDATA#33 SYSADDOUT#12 SADDOUTJ13
A27 SYSDATA#34 SYSADDOUT#13 G5
SDATAJ35 A25 00101 1.725 10101 1.325 G3 SADDOUTJ14
SDATAJ36 SYSDATA#35 SYSADDOUT#14
E21 SYSDATA#36
SDATAJ37 C23 00110 1.700 10110 1.300
SDATAJ38 SYSDATA#37 DAINCLKJ0
C27 SYSDATA#38 SYSDATAINCLK#0 W33
SDATAJ39 A23 00111 1.675 10111 1.275 J35 DAINCLKJ1
SDATAJ40 SYSDATA#39 SYSDATAINCLK#1 DAINCLKJ2
A35 SYSDATA#40 SYSDATAINCLK#2 E27
SDATAJ41 C35 01000 1.650 11000 1.250 E15 DAINCLKJ3
SDATAJ42 SYSDATA#41 SYSDATAINCLK#3
C33 SYSDATA#42
SDATAJ43 C31 01001 1.625 11001 1.225
SDATAJ44 SYSDATA#43 SDATAOUTCLKJ0 VCCP VCCP
A29 SYSDATA#44 SYSDATAOUTCLK#0 AE35
SDATAJ45 C29 01010 1.600 11010 1.200 C37 SDATAOUTCLKJ1
SDATAJ46 SYSDATA#45 SYSDATAOUTCLK#1 SDATAOUTCLKJ2
E23 SYSDATA#46 SYSDATAOUTCLK#2 A33
SDATAJ47 C25 01011 1.575 11011 1.175 C11 SDATAOUTCLKJ3
SDATAJ48 SYSDATA#47 SYSDATAOUTCLK#3 R3 R4
E17 SYSDATA#48
SDATAJ49 E13 01100 1.550 11100 1.150 U37 60.4 60.4
SDATAJ50 SYSDATA#49 SYSCHECK#0 +/-1% +/-1%
E11 SYSDATA#50 SYSCHECK#1 Y33
SDATAJ51 C15 01101 1.525 11101 1.125 L35 R0603 R0603
SDATAJ52 SYSDATA#51 SYSCHECK#2
E9 SYSDATA#52 SYSCHECK#3 E33
SDATAJ53 A13 01110 1.500 11110 1.100 E25 R5
SDATAJ54 SYSDATA#53 SYSCHECK#4 301
C9 SYSDATA#54 SYSCHECK#5 A31
SDATAJ55 A9 01111 1.475 11111 NO CPU C13 600 0.1uF +/-1%
B SDATAJ56 C21
SYSDATA#55
SYSDATA#56
SYSCHECK#6
SYSCHECK#7 A19 R0603 B
SDATAJ57 A21 BC2
SDATAJ58 SYSDATA#57 680pF
E19 SYSDATA#58 RSTCLK# AL19
SDATAJ59 C19 AL17 50V, NPO, +/-5%
CK_133M_CPUJ 19

* *
SDATAJ60 SYSDATA#59 CLKIN# BC3
C0603
C17 SYSDATA#60
SDATAJ61 A11 AN19 680pF
SDATAJ62 SYSDATA#61 RSTCLK 50V, NPO, +/-5%
A17 SYSDATA#62 CLKIN AN17 CK_133M_CPU 19
SDATAJ63 A15 C0603
SYSDATA#63
AN33 SDATAINVALJ
SDATAIN_VALID# SDATAINVALJ 11
SDATAOUT_VALID# AL31
NC35
NC36
NC37
NC38
NC39
NC40
NC41
NC42
NC43
NC44
NC45
NC46
NC47
NC48
NC49
NC50
NC51
NC52
NC53
NC54
NC55

NC57
NC58
NC59
NC60
NC61
NC62
NC63
NC64
NC65
NC66
NC67
NC68

SYSFILLVALID# AJ31

SOCKETA R6 R7
AE31
AF6
AF8
AF10
AF28
AF30
AF32
AG5
AG19
AG21
AG23
AG25
AH8
AH30
AJ7
AJ9

AK8
AJ11
AJ15
AJ17
AJ19
AJ27

AL7
AL9
AL11
AL25
AL27
AM8
AN7
AN9
AN11
AN25
AN27

270 270
+/-5% +/-5%
R0603 R0603

FSB_Sense[1]
FSB1
Close to S748 FSB1 19,26

L3 L4 L5 L6
L0603 10nH L0603 10nH L0603 10nH L0603 10nH
DAINCLKJ0 1 2 M_DAINCLKJ0 1 2 SDATAINCLKJ0 DAINCLKJ21 2 1 2 SDATAINCLKJ2
BC4 BC5

A * 4.7pF
50V, NPO, +/-0.25pF * 4.7pF
50V, NPO, +/-0.25pF A
10nH C0603 C0603

L7 L8 L9
L0603 10nH L0603 10nH L0603 10nH L10 L0603 10nH
DAINCLKJ1 1 2 M_DAINCLKJ1 1 2 SDATAINCLKJ1 DAINCLKJ31 2 M_DAINCLKJ3 1 2 SDATAINCLKJ3 TECHNOLOGY COPR.
BC6 BC7
* 4.7pF
50V, NPO, +/-0.25pF *
4.7pF
50V, NPO, +/-0.25pF
Title
CPU-1
C0603 C0603
Document Number R ev

748A01 A
Date: Sunday, September 05, 2004 Sheet 6 of 48
8 7 6 5 4 3 2 1
FSB_Sense[0]

FSB0
FSB0 19,26
VCCP VCCP VCCP VCCP

AG15
AG17
AG27
AG29
AG31
VCCP

AG7
AG9
G15
G17
G23
G25

AA7
G7
G9

Q7
N7
R8 R9 R10 R11

Y7
*After Model 6,VCC_Z/VSS_Z is NC 100 100 100 100
R12 0 AC7 AN3 NMI +/-5% +/-5% +/-5% +/-5%

KEY1
KEY2
KEY3
KEY4
KEY5
KEY6
KEY7
KEY8
KEY9
KEY10
KEY11
KEY12
KEY13
KEY14
KEY15
KEY16
KEY17
VCC_Z NMI NMI 26
DUMMY AN5 SMIJ R0603 R0603 R0603 R0603
SMI# SMIJ 26
BC8 AE1 A20MJ
* A20M# A20MJ 26
0.1uF AG1 FERR PLLBYPASSCLKJ PLLBYPASSCLK K7CLKOUT K7CLKOUTJ
DUMMY FERR INTR
INTR AL1 INTR 26
D R13 0 AE7
DUMMY VSS_Z INIT# AJ3
AJ1
INITJ
IGNNEJ
INITJ 26
R14
100
R15
100
R16
100
R17
100
D
IGNNE# IGNNEJ 26
AC1 STPCLKJ +/-5% +/-5% +/-5% +/-5%
STPCLK# STPCLKJ 26
AL3 FLUSHJ R0603 R0603 R0603 R0603
TRSTJ FLUSH#
U3 TRST#
U5 TDO
TDI U1
TCK TDI CONNECT
Q1 TCK CONNECT AL23 CONNECT 11
TMS Q3 AN23 P ROCRDY
TMS PROCRDY PROCRDY 11
AJ21 CLKFWDRST
CLKFWDRESET CLKFWDRST 11
AA1 3D3V_SYS 3D3V_SYS 3D3V_SYS
DBREQJ DBRDY
AA3 DBREQ#
N5 PICD1
PIC#1 PICD1 26
SCANCLK1 S1 N3 PICD0 R18 R19 R20
SCANCLK1 PIC#0 PICD0 26
SCANCLK2 S5 N1 PICCLK0 330 330 330
SCANCLK2 PICCLK PICCLK0 19
SCANSHIFTEN Q5 +/-5% +/-5% +/-5%
SCANINTEVAL SCANSHIFTEN R0603 R0603 R0603
S3 SCANINTEVAL
AL21 K7CLKOUT
K7CLKOUT K7CLKOUTJ PICD0 PICD1 PICCLK0
K7CLKOUT# AN21
PLLTESTJ AC3 PLLTEST# 15MIL R21 R22 R23
PLLMON1 AN13 AG13 COREFBJ 1K 1K 1K
PLLMON2 PLLMON1 COREFB- COREFB +/-5% +/-5% +/-5%
AL13 PLLMON2 COREFB+ AG11 COREFB 9
R0603 R0603 R0603

PLLBYPASSJ AJ25 W1 FI D0
PLLBYPASS# FID0 FI D1
FID1 W3
PLLBYPASSCLKJ AL15 Y1 FI D2
PLLBYPASSCLK PLLBYPASSCLK# FID2 FI D3
AN15 PLLBYPASSCLK FID3 Y3
C VCCA
FID[0..3] 18 C
AJ23 L1 VID0 VCCP
VCCA VID0 VID0 9
L3 VID1
VID1 VID1 9
SOCKETA-2 VID2
VID3
L5
L7
J7
VID2
VID3
VID4
VID2
VID3
9
9
R25
VID4 VID4 9
ZP AE5 150
ZP +/-5%Change Component
ZN AC5 AH6 R0603
ZN AMDPIN
ANALOG AJ13
600 have vccp pull up
VREFSYS W5 VREFSYS FERRJ 26
AE3 PWRGOOD
*After Model 6,SYSVERFMODE is NC PWROK PWRGOOD 46
SYSVREFMODE AA5 AG3 CPURSTJ

C
SYSVREFMODE RESET# CPURSTJ 11
VCCP
VCCP FERR B Q1
MMBT3904
U1B

E
SOCKETA DBREQJ R28 510
PLLTESTJ R29 510
R27
100 RN1 510

BC9
+/-1%
R0603
TRSTJ
TDI
*
1
3
2
4
* 0.1uF
25V, Y5V, +80%/-20%
VREFSYS TCK
TMS
5
7
6
8
C0603 BC10 BC11
B R30
* 0.33uF/NC
* 47nF CIS B
100 PLLMON1 R31 56
+/-1% C0603 C0603 RN2
R0603 PLLMON2 R33 56
270

PLLBYPASSJ R35 680


SCANCLK2
SCANINTEVAL
*
1
3
2
4
SCANCLK1 5 6
SCANSHIFTEN 7 8
ZN R38 40.2

RN62 680 ZP R32 56


SMIJ
INITJ
*
1
3
2
4 SYSVREFMODE R34 270 DUMMY
FLUSHJ 5 6
NMI 7 8 VREFMODE=Low=No voltage scaling

RN63 8P4R0603

3D3V_SYS A individual power


INTR
IGNNEJ
*
1
3
+/-5% 2
4 COREFBJ R36 10K
A20MJ
plane, Isolate withVCCA STPCLKJ
5
7
6
8
digital power.
U2 AME8800 680 8P4R0603
3 2 R47 10 +/-5%
V_IN V_OUT K7_PLL_PGD 46 600 NC
+/-5% CPURSTJ R49 100
BC14 R0603
GND

39pF
1

* BC12 BC13
10uF * BC15* * *
BC17
39pF
COREFB R50 10K

A 1uF C0805 10nF 39pF BC16 50V, NPO, +/-5% A


1

C0603

TECHNOLOGY COPR.
JP18 Title
2 1 SocketA-2
SHORT Document Number R ev

748A01 A
Date: Sunday, September 05, 2004 Sheet 7 of 48
8 7 6 5 4 3 2 1
VCCP

U1C

AB30 AB2 High Frequency Decoupling Capacitors


VCC_CORE1 VSS1
AB32 VCC_CORE2 VSS2 AB4
AB34 VCC_CORE3 VSS3 AB6
AB36 AB8 VCCP
VCC_CORE4 VSS4
AD2 VCC_CORE5 VSS5 AD32
AD4 VCC_CORE6 VSS6 AD34
AD6 VCC_CORE7 VSS7 AD36
AF14 VCC_CORE8 VSS8 AF12
D AF18
AF22
VCC_CORE9 VSS9 AF16
AF2
D
VCC_CORE10 VSS10 BC18 4.7uF BC19 4.7uF BC20 10uF
AF26 VCC_CORE11 VSS11 AF20
AF34 AF24

*
VCC_CORE12 VSS12 C1206 C1206 C1206
AF36 VCC_CORE13 VSS13 AF4
AH10 VCC_CORE14 VSS14 AH12
AH14 AH16 BC21 4.7uF BC22 4.7uF/NC BC23 10uF
VCC_CORE15 VSS15
AH18 AH20

*
VCC_CORE16 VSS16 C1206 C1206 C1206
AH2 VCC_CORE17 VSS17 AH24
AH22 VCC_CORE18 VSS18 AH28
AH26 AH32 BC24 4.7uF/NC BC25 4.7uF/NC BC26 10uF/NC
VCC_CORE19 VSS19
AH4 AH34

*
VCC_CORE20 VSS20 C1206 C1206 C1206
AJ5 VCC_CORE21 VSS21 AH36
AK10 VCC_CORE22 VSS22 AK12
AK14 AK16 BC27 4.7uF BC28 4.7uF/NC BC29 10uFNC
VCC_CORE23 VSS23
AK18 AK2

*
VCC_CORE24 VSS24 C1206 C1206 C1206
AK22 VCC_CORE25 VSS25 AK20
AK26 VCC_CORE26 VSS26 AK24
AK30 VCC_CORE27 VSS27 AK28
AK34 VCC_CORE28 VSS28 AK32
AK36 VCC_CORE29 VSS29 AK4
AL5 AK6 CPR# CPR#(AK6): CPU_PRESENCE#
VCC_CORE30 VSS30 is connected to VSS on the High Frequency Decoupling Capacitors
AM10 VCC_CORE31 VSS31 AM12
AM14 AM16 processor package. If
VCC_CORE32 VSS32 pulled-up on the
AM18 VCC_CORE33 VSS33 AM20 motherboard, CPU_PRESENCE#
AM2 AM24 VCCP
VCC_CORE34 VSS34 may be used to detect the
AM22 VCC_CORE35 VSS35 AM28 presence or absence of a
AM26 VCC_CORE36 VSS36 AM32 processor.
AM30 VCC_CORE37 VSS37 AM36
C AM34
B12
VCC_CORE38 VSS38 AM4
AM6
C
VCC_CORE39 VSS39
B16 VCC_CORE40 VSS40 B10
B20 B14 BC30 0.22uF BC31 0.22uF/NC BC32 0.22uF/nc BC33 0.22uF/NC

*
VCC_CORE41 VSS41

SOCKETA-3
B24 VCC_CORE42 VSS42 B18
B28 VCC_CORE43 VSS43 B2
B32 VCC_CORE44 VSS44 B22
B36 B26 BC34 0.22uF BC35 0.22uF/NC BC36 0.22uF/NC BC37 0.22uF/NC

*
VCC_CORE45 VSS45
B4 VCC_CORE46 VSS46 B30
B8 VCC_CORE47 VSS47 B34
D12 VCC_CORE48 VSS48 B6
D16 D10 BC38 0.22uF BC39 0.22uF/NC BC40 0.22uF/NC BC41 0.22uF/NC

*
VCC_CORE49 VSS49
D2 VCC_CORE50 VSS50 D14
D20 VCC_CORE51 VSS51 D18
D24 VCC_CORE52 VSS52 D22
D28 D26 BC42 0.22uF BC43 0.22uF/NC BC44 0.22uF/NC BC45 0.22uF/NC

*
VCC_CORE53 VSS53
D32 VCC_CORE54 VSS54 D30
D4 VCC_CORE55 VSS55 D34
D8 VCC_CORE56 VSS56 D36
F12 D6 BC46 0.22uF BC47 0.22uF/NC BC48 0.22uF/NC BC49 0.22uF/NC

*
VCC_CORE57 VSS57
F16 VCC_CORE58 VSS58 F10
F20 VCC_CORE59 VSS59 F14
F24 VCC_CORE60 VSS60 F18
F28 F2 BC50 0.22uF BC51 0.22uF/NC

*
VCC_CORE61 VSS61
F32 VCC_CORE62 VSS62 F22
F34 VCC_CORE63 VSS63 F26
F36 VCC_CORE64 VSS64 F4
H12 VCC_CORE65 VSS65 F6
H16 VCC_CORE66 VSS66 H14
H2 H18
B H20
VCC_CORE67
VCC_CORE68
VSS67
VSS68 H22 B
H24 VCC_CORE69 VSS69 H26
H4 VCC_CORE70 VSS70 H34
K32 VCC_CORE71 VSS71 H36
K34 VCC_CORE72 VSS72 K2
K36 VCC_CORE73 VSS73 K4
M2 VCC_CORE74 VSS74 K6
M4 VCC_CORE75 VSS75 M30
M6 VCC_CORE76 VSS76 M32
M8 VCC_CORE77 VSS77 M34
P30 VCC_CORE78 VSS78 M36
P32 VCC_CORE79 VSS79 P2
P34 VCC_CORE80 VSS80 P4
P36 VCC_CORE81 VSS81 P6
R2 VCC_CORE82 VSS82 P8
R4 VCC_CORE83 VSS83 R30
R6 VCC_CORE84 VSS84 R32
R8 VCC_CORE85 VSS85 R34
T30 VCC_CORE86 VSS86 R36
T32 VCC_CORE87 VSS87 T2
T34 VCC_CORE88 VSS88 T4
T36 VCC_CORE89 VSS89 T6
V2 VCC_CORE90 VSS90 T8
V4 VCC_CORE91 VSS91 V30
V6 VCC_CORE92 VSS92 V32
V8 VCC_CORE93 VSS93 V34
X30 VCC_CORE94 VSS94 V36
X32 VCC_CORE95 VSS95 X2
X34 X4
A X36
VCC_CORE96
VCC_CORE97
VSS96
VSS97 X6 A
Z2 VCC_CORE98 VSS98 X8
Z4 VCC_CORE99 VSS99 Z30
Z6 VCC_CORE100 VSS100 Z32
Z8 VCC_CORE101 VSS101 Z34
VSS102 Z36 TECHNOLOGY COPR.
SOCKETA Title
SocketA-3
Document Number R ev

748A01 A
Date: Sunday, September 05, 2004 Sheet 8 of 48
5 4 3 2 1

ISL6563CR FOR K7 POWER D

3D3V_SYS 5V_SYS 5V_SYS VIN


Choke COIL 0.7uH
L11

*
R51
5V_SYS VIN
2 EC1 EC2 EC3
+/-5% BC834 * 1500uF * 1500uF * 1500uF
R0603
* 10uF/NC
6.3V, X5R, +/-20%
16V,+/-20%
CE50D100H300
16V,+/-20%
CE50D100H300
16V,+/-20%
CE50D100H300

2
4
6
8
BC68 BC69 C1206
R52
1K
RN3
1K
BC853
0.1uF * 10uF
*
C1206 * 10uF
C1206
BC854
0.1uF * *
BC70
10uF
+/-5% 6.3V, X5R, +/-20%

D
R0603 C1206
5V_SYS * AOD412 Q2

16
1
3
5
7

8
U3
22 19 R53 1 R0805 G

VCC

PVCC
7 VID4 VID4 UGATE1
C 23 +/-5% Choke COIL 0.7uH C
7 VID3 VID3
R536 24 L12

*
7 VID2

S
2K/NC VID2
7 VID1 1 VID1 PHASE1 18 VCCP
+/-5% 2

D
7 VID0 VID0
R0603 3 DACSEL/VID5
BC71
* AOD412 Q3
PWMOK 10 0.1uF R55
46 PWMOK SSEND R54 0 G 2.2
LGATE1 17

1
R537 R56 21 R0805 +/-5% EC4 EC5 EC6
5V_SYS ENLL
3.3K/NC BC72 +/-5% R0805

S
+/-5% R57 0.1uF_NC 10nF R1151 2200uF 6.3V 2200uF 6.3V 2200uF 6.3V/NC

2
R0603 10K 10K/NC * R58 2K BC73 VIN
5 20
*

R0603 +/-5% COMP BOOT1 * BC74


+/-5% R0603 BC75 0.1uF_NC 2.2 10nF
R59
*

6 11 BC76 BC77

D
7 COREFB FB BOOT2

1K 5V_SYS
R60 150K_NC 9 OFS
R1152 2.2
* AOD412 *
Q4
10uF
6.3V, X5R, +/-20%
0.1uF C1206
R0603 R62 12 1 G
+/-5% 10K UGATE2 Choke COIL 0.7uH
+/-5% R61 L13

*
S
R0603 13
R63 PHASE2

D
5V_SYS 7 ISEN AOD412 Q5
R64
R65
10K 2.2
B LGATE2 15 G B

1
R0603 4 +/-5% EC8 EC9
GND

+/-5% VRM10 R0805


14

S
PGND 0 2200uF 6.3V 2200uF 6.3V

2
ISL6563CR R0805
25

+/-5% * BC78
10nF
JP17
2 1
Seperated from GND Pad
SHORT
BOTTOM PAD
CONNECT TO GND

A A

TECHNOLOGY COPR.
Title
VCCP
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 9 of 48
5 4 3 2 1
5 4 3 2 1

D D

H4 H5 H6 H7 H8 H9
Mounting Hole Mounting Hole Mounting Hole Mounting Hole Mounting Hole Mounting Hole
mh40x80_8 mh40x80_8 mh40x80_8 mh40x80_8 mh40x80_8 mh40x80_8
H1 H2 H3

6
5

6
5

6
5

6
5

6
5

6
5
FMARK FMARK FMARK
FD40 FD40 FD40 7 4 7 4 7 4 7 4 7 4 7 4
8 3 8 3 8 3 8 3 8 3 8 3
9 2 9 2 9 2 9 2 9 2 9 2

1
C C

B B

A A

TECHNOLOGY COPR.
Title
VRD DRIVER
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 10 of 48
5 4 3 2 1
8
3D3V_SYS Place near the 748 chip. 7 6 SDATAJ[0..63] 5 4 3 2 1
6 SDATAJ[0..63] AAD[0..31]
SDATAJ[0..63] AAD[0..31] 24
CPUCLKAVDD
BC80 BC81 SBAJ[0..7]
SBAJ[0..7] 24
* 0.1uF
* 10nF
25V, Y5V, +80%/-20% AC-BE[0..3]
AC-BE[0..3] 24
C0603 C0603

S2KCOMPND

S2KCOMPPD
CPUCLKAVSS ST[0..2]
ST[0..2] 24

SDATAJ10
SDATAJ11
SDATAJ12
SDATAJ13
SDATAJ14
SDATAJ15
SDATAJ16
SDATAJ17
SDATAJ18
SDATAJ19
SDATAJ20
SDATAJ21
SDATAJ22
SDATAJ23
SDATAJ24
SDATAJ25
SDATAJ26
SDATAJ27
SDATAJ28
SDATAJ29
SDATAJ30
SDATAJ31
SDATAJ32
SDATAJ33
SDATAJ34
SDATAJ35
SDATAJ36
SDATAJ37
SDATAJ38
SDATAJ39
SDATAJ40
SDATAJ41
SDATAJ42
SDATAJ43
SDATAJ44
SDATAJ45
SDATAJ46
SDATAJ47
SDATAJ48
SDATAJ49
SDATAJ50
SDATAJ51
SDATAJ52
SDATAJ53
SDATAJ54
SDATAJ55
SDATAJ56
SDATAJ57
SDATAJ58
SDATAJ59
SDATAJ60
SDATAJ61
SDATAJ62
SDATAJ63
SDATAJ0
SDATAJ1
SDATAJ2
SDATAJ3
SDATAJ4
SDATAJ5
SDATAJ6
SDATAJ7
SDATAJ8
SDATAJ9
ADSTBF[0..1]
ADSTBF[0..1] 24
3D3V_SYS
ADSTBS[0..1]
ADSTBS[0..1] 24
C PUPHYAVDD
BC83 BC84
D * 0.1uF
* 10nF D

M26

M24
G24

G26

G29
G27
D17

C25

D25
C26

C27

D23

C24
D26

D24

D27
D29

C29
C28

H25

H27

N26
R25
R26

R27

N27
N24
N25
N28

R29
N29
R24
E18

E24

A27

A25

B25

B27

E26

E28
E29

K25

K27

P27

P25
F24

F23

F22

F26

F29
F27

F25

T26

T24
T29
L24

L28
L25
L27

L26
J25

J24
J26

J27
J29
J28
25V, Y5V, +80%/-20%
JP3 C0603 C0603
2 1 CPUPHYAVSS

S2KCOMPND

S2KCOMPPD

SDATA#0
SDATA#1
SDATA#2
SDATA#3
SDATA#4
SDATA#5
SDATA#6
SDATA#7
SDATA#8
SDATA#9
SDATA#10
SDATA#11
SDATA#12
SDATA#13
SDATA#14
SDATA#15
SDATA#16
SDATA#17
SDATA#18
SDATA#19
SDATA#20
SDATA#21
SDATA#22
SDATA#23
SDATA#24
SDATA#25
SDATA#26
SDATA#27
SDATA#28
SDATA#29
SDATA#30
SDATA#31
SDATA#32
SDATA#33
SDATA#34
SDATA#35
SDATA#36
SDATA#37
SDATA#38
SDATA#39
SDATA#40
SDATA#41
SDATA#42
SDATA#43
SDATA#44
SDATA#45
SDATA#46
SDATA#47
SDATA#48
SDATA#49
SDATA#50
SDATA#51
SDATA#52
SDATA#53
SDATA#54
SDATA#55
SDATA#56
SDATA#57
SDATA#58
SDATA#59
SDATA#60
SDATA#61
SDATA#62
SDATA#63
SHORT VDDREFA M27
VSSREFA VDDREFA
M29 VSSREFA AGP3.0 = 50 ohm
VDDREFB A23
VSSREFB VDDREFB VDDQ
C23 VSSREFB R68
HSTLVREFA L29 B7 AC-BE3 AGPRCOMN 49.9
HSTLVREFB HSTLVREFA AC/BE3# AC-BE2 +/-1%
B23 HSTLVREFB AC/BE2# C5
C3 AC-BE1 R0603
AC/BE1# AC-BE0
19 CK_133M_S748 W29 CPUCLK AC/BE0# H5

SDATAINVALJ E20 D15 R69


6 SDATAINVALJ SDATAINVAL# AREQ# AREQ 24
CPURSTJ D18 E16 AGPRCOMP 43.2
7 CPURSTJ CPURST# AGNT# AGNT 24
P ROCRDY D19 F6 +/-1%
AFRAME 24
7
7
7

6
PROCRDY
CONNECT
CLKFWDRST

SADDINCLKJ
6 SADDOUTCLKJ
CONNECT
CLKFWDRST

SADDINCLKJ
SADDOUTCLKJ
C19
F18

A22
U29
PROCRDY
CONNECT
CLKFWDRST

SADDINCLK#
SADDOUTCLK#
HOST AFRAME#
AIRDY#
ATRDY#
ADEVSEL#
ASERR#
ASTOP#
A4
E5
D6
B4
A3
AIRDY
ATRDY
ADEVSEL
ASERR
ASTOP
24
24
24
24
24
R0603

SDATAINCLKJ0 A26 B2
SDATAINCLK#0 APAR# APAR 24
SDATAINCLKJ1 E27
SDATAINCLKJ2 SDATAINCLK#1
K29 SDATAINCLK#2 RBF# C14 RBF 24
SDATAINCLKJ3 P29 B13
SDATAINCLK#3 WBF# W BF 24
C 6 SDATAINCLKJ[0..3] SDATAOUTCLKJ0 A24 C15 GCDETJ C
SDATAOUTCLK#0 GC_DET#/AGP8XDET# GCDETJ 24
SDATAOUTCLKJ1 G28 A13 DBI_HI
SDATAOUTCLK#1 PIPE#/DBI_HI DBI_HI 24
SDATAOUTCLKJ2 H29 D13 DBI_LOW
SDATAOUTCLK#2 DBI_LO DBI_LOW 24
SDATAOUTCLKJ3 R28 SDATAOUTCLK#3
6 SDATAOUTCLKJ[0..3] SB_STBF A12 SBSTBF 24
SADDINJ2 F21 B11
SADDIN#2 SB_STBS SBSTBS 24
SADDINJ3 D21
Put near 748 chip SADDINJ4 SADDIN#3 ADSTBF0

748-1
B21 SADDIN#4 AD_STBF0 E1
VCCP SADDINJ5 E22 F2 ADSTBS0
SADDINJ6 SADDIN#5 AD_STBS0
F20 SADDIN#6
SADDINJ7 D22 B8 ADSTBF1
R70 SADDINJ8 SADDIN#7 AD_STBF1 ADSTBS1
C20 SADDIN#8 AD_STBS1 A7
62 SADDINJ9 C21
+/-1% SADDINJ10 SADDIN#9 AGPCLK0
D20 SADDIN#10 AGPCLK C16 CK_66M_S748 19
R0603 SADDINJ11 C22
SADDINJ12 SADDIN#11 AGPRCOMP
A20 SADDIN#12 AGPRCOMP J3
CK_133M_S748 SADDINJ13 A21 J1 AGPRCOMN
SADDINJ14 SADDIN#13 AGPRCOMN A1XAVDD
F19 SADDIN#14 A1XAVDD A16
B16 A1XAVSS
SADDOUTJ2 A1XAVSS
6 SADDINJ[2..14] U24 SADDOUT#2
SADDOUTJ3 T27 B15 A4XAVDD
SADDOUT#3 A4XAVDD
* BC859 SADDOUTJ4 W24 SADDOUT#4 A4XAVSS A15 A4XAVSS
3.3pF/NC SADDOUTJ5
SADDOUTJ6
SADDOUTJ7
SADDOUTJ8
SADDOUTJ9
SADDOUTJ10
U25
U27
W26
U28
V25
W27
SADDOUT#5
SADDOUT#6
SADDOUT#7
SADDOUT#8
SADDOUT#9
AGP AGPVREF

AGPVSSREF
H1

J2
AVREFGC 24

3D3V_SYS
SADDOUTJ11 SADDOUT#10
V27
B SADDOUTJ12 U26
SADDOUT#11
SADDOUT#12
B
SADDOUTJ13 Y25 A1XAVDD
SADDOUTJ14 SADDOUT#13
V29 SADDOUT#14
6 SADDOUTJ[2..14] CPUCLKAVDD BC85 BC86
Y26 CPUAVDD
CPUCLKAVSS Y27 CPUAVSS
* 0.1uF
* 10nF

C0603 C0603
C PUPHYAVDD B19 CPUPHYAVDD JP4
AAD10
AAD11
AAD12
AAD13
AAD14
AAD15
AAD16
AAD17
AAD18
AAD19
AAD20
AAD21
AAD22
AAD23
AAD24
AAD25
AAD26
AAD27
AAD28
AAD29
AAD30
AAD31
AAD0
AAD1
AAD2
AAD3
AAD4
AAD5
AAD6
AAD7
AAD8
AAD9

Place near the 748 chip.


SBA7
SBA6
SBA5
SBA4
SBA3
SBA2
SBA1
SBA0

CPUPHYAVSS A19 A1XAVSS 2 1


CPUPHYAVSS
ST0
ST1
ST2

VCCP SHORT
R73
E11
F12
C11
A10
C12
D12
E13
F14

F15
A14
E14

H2
J6
G1
H4
J4
G3
F3
G4
E2
E4
D2
G6
F5
D3
C1
D4
D7
B5
E7
F8
A6
C6
E8
F9
C8
D9
E10
C9
F11
A9
B10
D10
33 S2KCOMPND U4A
+/-5% 748 3D3V_SYS
R0603
AAD10
AAD11
AAD12
AAD13
AAD14
AAD15
AAD16
AAD17
AAD18
AAD19
AAD20
AAD21
AAD22
AAD23
AAD24
AAD25
AAD26
AAD27
AAD28
AAD29
AAD30
AAD31
SBAJ7
SBAJ6
SBAJ5
SBAJ4
SBAJ3
SBAJ2
SBAJ1
SBAJ0

R74
AAD0
AAD1
AAD2
AAD3
AAD4
AAD5
AAD6
AAD7
AAD8
AAD9
ST0
ST1
ST2

33 S2KCOMPPD A4XAVDD
+/-5%
R0603
BC88 BC89
VCCP VCCP
* 0.1uF
* 10nF

C0603 C0603

BC91 R76 BC92 JP5


R77
100 * 10nF/NC 100
+/-1% * 10nF/NC A4XAVSS 2 1

A +/-1% C0603 15 mil


trace
R0603 C0603 15 mil
trace
SHORT A
R0603
HSTLVREFA HSTLVREFB 1D8V_VCCNB 1D8V_VCCNB

BC95 R80 BC97 VDDREFB VDDREFA TECHNOLOGY COPR.


R81
100 * 10nF 100
+/-1% * 10nF BC100
*
0.1uF
*
BC101
10nF/NC
BC103
*
0.1uF
*
BC104
10nF/NC Title
+/-1% C0603 R0603 C0603 HOST & AGP
R0603 JP8 C0603 C0603 JP9 C0603 C0603
2 1 2 1 2 1 VSSREFB 2 1 VSSREFA Document Number R ev

JP6 JP7 SHORT SHORT 748A01 A


SHORT SHORT Date: Sunday, September 05, 2004 Sheet 11 of 48
8 7 6 5 4 3 2 1
MD[0..63] MAA[0..14]
MD[0..63] 21,22,23 MAA[0..14] 21,22,23
DQM[0..7]
DQM[0..7] 21,22,23
DQS[0..7] CSAJ[0..5]
DQS[0..7] 21,22,23 CSAJ[0..5] 21,22,23

U4B 10 mil wire

MD0 AD25 AE13 MAA0


MD1 MD0 MAA0 MAA1
AH28 MD1 MAA1 AJ14
MD2 AD24 AH14 MAA2
MD2 MAA2
D MD3
MD4
AH26
AF27
MD3 MAA3 AE14
AD15
MAA3
MAA4
D
MD5 MD4 MAA4 MAA5
AG25 MD5 MAA5 AD18
MD6 AF26 AJ18 MAA6
MD7 MD6 MAA6 MAA7
AG27 MD7 MAA7 AF18
DQM0 AJ26 AG18 MAA8
DQS0 DQM0 MAA8 MAA9
AJ27 CSB#0/DQS0 MAA9 AH19
MD8 AE25 AF14 MAA10
MD9 MD8 MAA10 MAA11
AE23 MD9 MAA11 AE10
MD10 AG24 AD13 MAA12
MD11 MD10 MAA12 MAA13
AH23 MD11 MAA13 AG19
MD12 AF24 AD19 MAA14
MD13 MD12 MAA14
AH25 MD13 MAA15 AF23
MD14 AE22
MD15 MD14 MWAJ
AD21 MD15 RAMRWA# AF9
DQM1 AD22 AG9 RASAJ
DQS1 DQM1 SRASA# CASAJ
AJ24 CSB#1/DQS1 SCASA# AJ9
MD16 AH22
MD17 MD16
AG22 MD17 Reserved AE17
MD18 AF20
MD19 MD18
AH20 MD19
MD20 AE20
MD21 MD20 RASAJ
AF21 MD21 RASAJ 21,22,23
MD22 AE19
MD23 MD22 MWAJ
AJ20 MD23 MWAJ 21,22,23
DQM2 AG21
DQS2 DQM2 CASAJ
AJ21 CSB#2/DQS2 CASAJ 21,22,23
MD24 AE16
MD25 MD24
AH17 MD25
C MD26
MD27
AF15
AJ15
MD26 C
MD28 MD27
AF17
MD29
MD30
MD31
AD16
AG15
AH16
MD28
MD29
MD30
MD31
748-2
DQM3 AG16
DQS3 DQM3
AJ17 CSB#3/DQS3
MD32 AJ12
MD33 MD32
AF12 MD33
MD34 AG10
MD35 MD34 CSAJ0
AF11 MD35 CS0# AD9
MD36 AG12 AD10 CSAJ1
MD37 MD36 CS1# CSAJ2
AD12 MD37 CS2# AJ8
MD38 AE11 AE8 CSAJ3
MD39 MD38 CS3# CSAJ4
AH10 MD39 CS4# AF8
DQM4 AH11 AH8 CSAJ5
DQS4 DQM4 CS5#
AJ11 CSB#4/DQS4
MD40 AJ6
MD41 MD40
AF6 MD41
MD42 AE7 AJ23 DDRVREFA
MD43 MD42 DDRVREFA DDRVREFB
AH4 MD43 DDRVREFB AJ3
MD44 AH7
MD45 MD44 DLLAVDD
AG7 MD45 DLLAVDD AA29
MD46 AG6 AA28 DLLAVSS
MD47 MD46 DLLAVSS
AF5 MD47
DQM5 AJ5 2D5V_DDR
DQS5 DQM5
AH5 CSB#5/DQS5 SDRCLKI AG13
MD48 AD7 DDRCOMN R83 40.2 +/-1%
MD49 MD48 FWDSDCLKO DDRCOMP R84 40.2 +/-1%
AE5 AH13
B MD50 AE4
MD49
MD50
FWDSDCLKO B
MD51 AF2
MD52 MD51 DDRAVDD
AG4 MD52 DDRAVDD Y29
MD53 AF3 Y28 DDRAVSS
MD54 MD53 DDRAVSS
AG3 MD54
MD55 AD6
DQM6 MD55 CKE0
AH2 DQM6 CKE0 AA6 CKE0 21
DQS6 AG1 AB6 CKE1
CSB#6/DQS6 CKE1 CKE1 21
MD56 AC2 AA5 CKE2
MD56 CKE2 CKE2 21
MD57 AE1 AA3 CKE3
MD57 CKE3 CKE3 21
MD58 AB3 AB4 CKE4
MD58 CKE4 CKE4 22
MD59 AD3 AA4 CKE5
MD59 CKE5 CKE5 22
MD60 AE2
MD61 MD60
AC6 MD61 S3AUXSW# Y6
MD62 AD5
MD63 MD62
AC4 MD63
DQM7 AB5 AB2 DDRCOMP
DQS7 DQM7 DDRCOMP DDRCOMN Put near 748 chip.
AD1 CSB#7/DQS7 DDRCOMN AB1
FWDSDCLKO R86 22 R0603
SDCLKO_DDR 20
+/-5%
748
2D5V_DDR 2D5V_DDR
BC105
* 10pF
50V, NPO, +/-5%
BC106 BC107 R87 C0603
* 0.1uF/NC R88
150 * 0.1uF/NC 150
+/-1% 3D3V_SYS 3D3V_SYS
C0603 +/-1% C0603 R0603
A R0603 A
DDRVREFA DDRVREFB DDRAVDD DLLAVDD
( 10-mil trace ) ( 10-mil trace )
25-mil clearance BC108 25-mil clearance BC109 R91 BC110 BC111 BC113 BC114
or shielded by or shielded by
VSS trace and
VDD trace
* 0.1uF R92
150 VSS trace and
VDD trace
* 0.1uF 150
+/-1% * 0.1uF
* 10nF
* 0.1uF
* 10nF
TECHNOLOGY COPR.
C0603 +/-1% C0603 R0603 C0603 C0603 C0603 C0603
R0603 Title
DDRAVSS DLLAVSS 748-MEM
Document Number R ev

748A01 A
Date: Sunday, September 05, 2004 Sheet 12 of 48
8 7 6 5 4 3 2 1
NB Hardware Trap Table

A0/A1 ON/1 OFF/0 Default

CPUDLLENN CPUCLK SDCLK PLL/DLL Circuit Enable DISABLE ENABLE OFF

TMODE0 MuTIOL ( ASL ) DBI Mode DISABLE ENABLE OFF

TMODE1 MuTIOL ( ASL ) initialize Mode Packet Series OFF


D The differences between U4C TMODE2 P748 Debug Mode Selection ENABLE DISABLE OFF
D
the traces of MuTIOL 748
Strobes and Data should TRAP4 MuTIOL type (verision 1 , 2) Ver. 1 Ver. 2 OFF
be smaller than 0.05"
ZCLK0 W1
19 ZCLK0 ZCLK
ZSTB0 U1 B18 TMODE0
25 ZSTB0 ZSTBJ0 ZSTB0 TESTMODE0 TMODE1
25 ZSTBJ0 V2 ZSTB0# TESTMODE1 A18
F17 TMODE2
ZSTB1 TESTMODE2
25 ZSTB1 P2 ZSTB1
ZSTBJ1 R1 E17 TRAP0
25 ZSTBJ1 ZSTB1# TRAP0 TRAP0 18
C17 TRAP1
TRAP1 TRAP1 18
B17 TRAP2 3D3V_SYS
TRAP2 18
Z1XAVDD
Z1XAVSS
Y2
Y1
Z1XAVDD
Z1XAVSS 748-3 TRAP2
TRAP3
TRAP4
A17
F16
TRAP3
TRAP4
TRAP3 18

Z4XAVDD AA1 D16 ENTEST R1160 0


Z4XAVSS Z4XAVDD ENTEST DLLENJ R1145
AA2 Z4XAVSS DLLEN# C18
4.7K/NC
DUMMY 3D3V_SB +/-5%
ZCMPJN W2 Y4 DRAM_SEL R94 0 R0603
ZCMP_N DRAM_SEL
PCIRST# W5 PCIRSTJ2 25,37
ZCMPJP W4 ZCMP_P MuTIOL DLLENJ
Y5 PWRGD_NB
PWROK PWRGD_NB 46
ZVREF W3 ZVREF
Y3
C AUXOK BC116
AUXOK 26,45
C
25 ZUREQ
ZUREQ
ZDREQ
W6
V3
ZUREQ * 1uF
*
BC117
1uF

ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZAD16
25 ZDREQ ZDREQ C0603

ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
dummy C0603
dummy
V4
T2
U5
T5
U3
T4
R3
T6
P6
P1
R5
P4
N2
N5
N3
N6
V6
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14

ZAD16
ZAD15
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
The differences between NB Hardware Trap
the traces of MuTIOL
Strobes and Data should
be smaller than 0.05"
PULL LOW 3D3V_SYS

ZAD[0..16]
25 ZAD[0..16]
RN75
TMODE0
TMODE1
*
1
3
2
4
TMODE2 5 6
TRAP4 7 8

4.7K DUMMY
R1144 4.7K DUMMY

B B
NB Hardware Trap has internal pull-low in SiS748 chip
for DRAM_SEL,CPUDLLENN,TMODE0,TMODE1,TMODE2 signals.

Place near 748 chip.

1D8V_VCCNB
R95
56 ZCMPJN
+/-5%
FB52
3D3V_SYS 3D3V_SYS R96 BC118 R0603

2 1 Z4XAVDD Z1XAVDD
150
+/-1% * 0.1uF

BC833 BC121 BC120 BC123 BC124 R0603 C0603


*
10uF
FB L0603 47 Ohm
* 0.1uF
* 10nF
* 10nF
* 0.1uF
ZVREF
C1206 JP14 C0603 C0603 JP15 C0603 C0603
A 2 1 Z4XAVSS 2 1 Z1XAVSS R98 BC126 A
SHORT SHORT
49.9
+/-1% * 0.1uF

R0603 C0603
JP16 R99 TECHNOLOGY COPR.
2 1 56 ZCMPJP
+/-5% Title
SHORT R0603 MuTIOL
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 13 of 48
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2
1D8V_VCCNB 1
BC127 10uF C1206

* * * * *
3D3V_SYS VCCP
BC128 1uF/NC
BC130
10uF C1206

* * * * *
VDDQ BC131 0.1uF BC132 1uF

N4

R4
R6
U4
U6
VDDQ U4E BC134 1uF/NC

P5

V5

* *
U4D VDDQ
BC129
1D8V_VCCNB A5 BC135 0.1uF BC136 0.1uF/NC

VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
10uF C1206 VSSQ BC138 0.1uF
H8 A8
* * * * * *

VDDQ VSSQ
D BC133
H9
J8
VDDQ VDDZ T10
R11
K1
K2
VDDQ VSSQ A11
B3 BC139 0.1uF
D
10uF/NC C1206 VDDQ VDDZ VDDQ VSSQ BC141 0.1uF/NC
VDDZ R10 K3 VDDQ VSSQ B6
K10 VDDQ VDDZ P11 K4 VDDQ VSSQ B9
BC137 1uF/NC K11 P10 2D5V_DDR K5 B12 2D5V_DDR
VDDQ VDDZ VDDQ VSSQ BC143 0.1uF
K13 VDDQ IVDD W20 K6 VDDQ VSSQ B14
K14 VDDQ L1 VDDQ VSSQ C2
BC140 1uF L10 T11 L2 C4
VDDQ VDDM VDDQ VSSQ
L11 VDDQ VDDM U10 L3 VDDQ VSSQ C7
L12 U11 L4 C10 BC145 1uF/NC
BC142 0.1uF VDDQ VDDM VDDQ VSSQ
L13 U19 L5 C13

* * * * * * * *
VDDQ VDDM VDDQ VSSQ BC146 10uF VCCP
L14 VDDQ VDDM U20 L6 VDDQ VSSQ D1
L15 V10 M1 D5 BC147 1uF/NC C1206 BC149 10uF/NC

*
BC144 0.1uF/NC VDDQ VDDM VDDQ VSSQ C1206
M10 V11 M2 D8

*
VDDQ VDDM VDDQ VSSQ 10uF/NC
M11 VDDQ VDDM V19 M3 VDDQ VSSQ D11
N11 W10 M4 D14 BC150 0.1uF/NC BC148 C1206

*
VDDQ VDDM VDDQ VSSQ BC152 1uF/NC
VDDM W11 M5 VDDQ VSSQ E3

748-4
W12 M6 E6

* * * *
VDDM VDDQ VSSQ BC153 0.1uF/NC
VDDM W13 VSSQ E9
W14 E12 BC155 0.1uF
VDDM VSSQ
VDDM W15 VSSQ E15
W16 1D8V_VCCNB F1 BC156 1uF
VDDM VSSQ BC157 0.1uF/NC
VDDM W17 VSSQ F4
1D8V_VCCNB

K12
K15
K16
IVDD
IVDD
VDDM
VDDM
VDDM
VDDM
W18
W19
Y10
Y13
Y14
N1
P3
R2
T1
T3
VDDZ
VDDZ
VDDZ
VDDZ
748-5 VSSQ
VSSQ
VSSQ
VSSQ
F7
F10
F13
G2
G5
BC158

BC160
1uF

0.1uF
BC159 0.1uF

IVDD VDDM VDDZ VSSQ


K18 IVDD VDDM Y16 U2 VDDZ VSSQ H3
C K20 IVDD VDDM Y17
Y20
V1 VDDZ VSSQ H6
J5 BC161 0.1uF C
VDDM VSSQ
L20 IVDD VDDM AA8
2D5V_DDR AC1
VSSM
M20 IVDD VSSM AC3
Power(inside)

VDDM AA22 VSSM AC5


N10 IVDD VDDM AB8 Y24 VDDM VSSM AD2
VDDM AB9 AA24 VDDM VSSM AD4
VDDM AB21 AA25 VDDM VSSM AD8
AB22 AA26 AD11 Place these capacitors under 748 solder side.
VDDM VDDM VSSM
AA27 VDDM VSSM AD14
W9 AB24 AD17 2D5V_DDR
PVDDM VDDM VSSM VDDQ
PVDDM Y11 AB25 VDDM VSSM AD20
AB26 VDDM VSSM AD23
AA13 AB27 AE3 BC164 0.1uF-BOT BC163 0.1uF-BOT
PVDDM VDDM VSSM
V20 AA17 AB28 AE6

*
IVDD PVDDM VDDM VSSM BC165
AB29 VDDM VSSM AE9
Y12 P12 AC24 AE12 0.1uF-BOT

*
IVDD VSSM VDDM VSSM
Y15 IVDD VSSM P13 AC25 VDDM VSSM AE15
Y18 IVDD VSSM P14 AC26 VDDM VSSM AE18
Y19 P15 AC27 AE21 VDDQ BC166 0.1uF-BOT
IVDD VSSM VDDM VSSM
P16 AC28
. Power AE24 BC170 0.1uF-BOT

*
VSSM VDDM VSSM
R12 AC29 AF1

*
VSSM VDDM VSSM
VSSM R13 AD26 VDDM VSSM AF4
VSSM R14 AD27 VDDM VSSM AF7

VCCP
AB13
AB17
IVDD
IVDD
VSSM
VSSM
VSSM
R15
R16
T12
T13
AD28
AD29
AE26
AE27
VDDM
VDDM
VDDM
(outside) VSSM
VSSM
VSSM
AF10
AF13
AF16
AF19
VSSM VDDM VSSM 1D8V_VCCNB
H21 T14 AE28 AF22
B H22
S2KOVDD
S2KOVDD
VSSM
VSSM T15 AE29
VDDM
VDDM
VSSM
VSSM AF25 B
VSSM T16 AF28 VDDM VSSM AG2
U12 AF29 AG5 BC172 0.1uF-BOT
VSSM VDDM VSSM
J22 U13 AG29 AG8

*
S2KOVDD VSSM VDDM VSSM
K17 S2KOVDD VSSM U14 VSSM AG11
K19 U15 AG14 BC174 0.1uF-BOT

*
S2KOVDD VSSM VSSM
L16 S2KOVDD VSSM U16 VSSM AG17
L17 U17 VCCP AG20 BC176 0.1uF-BOT

*
S2KOVDD VSSM VSSM
L18 S2KOVDD VSSM U18 VSSM AG23
L19 V12 B20 AG26 BC178

*
S2KOVDD VSSM S2KOVDD VSSM 0.1uF-BOT
M19 S2KOVDD VSSM V13 B22 S2KOVDD VSSM AG28
N19 S2KOVDD VSSM V14 B24 S2KOVDD VSSM AH3
N20 S2KOVDD VSSM V15 B26 S2KOVDD VSSM AH6
P19 S2KOVDD VSSM V16 B28 S2KOVDD VSSM AH9
P20 V17 D28 AH12 VCCP
S2KOVDD VSSM S2KOVDD VSSM
R19 S2KOVDD VSSM V18 F28 S2KOVDD VSSM AH15
R20 S2KOVDD H28 S2KOVDD VSSM AH18
T19 M12 K28 AH21 BC180 0.1uF-BOT
3D3V_SYS S2KOVDD VSSQ S2KOVDD VSSM
T20 M13 M28 AH24

*
S2KOVDD VSSQ S2KOVDD VSSM
VSSQ M14 P28 S2KOVDD VSSM AH27
1D8V_SB H16 M15 T28 AJ4 BC182 0.1uF-BOT

*
VDD3.3 VSSQ S2KOVDD VSSM
J16 VDD3.3 VSSQ N12 V28 S2KOVDD VSSM AJ7
3D3V_SB N13 W28 AJ10 BC184 0.1uF-BOT

**
VSSQ S2KOVDD VSSM
T9 AUX1.8 VSSQ N14 VSSM AJ13
N15 AJ16 BC186 0.1uF-BOT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ VSSM
U9 AUX3.3 VSSM AJ19
BC673 BC188 AJ22
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSM
* 10uF
* 10nF 748 AJ25
T18
T17
R18
R17
P18
P17
N18
N17
N16
M18
M17
M16

VSSM
A C1206 C0603 748 A
E19
E21
E23
E25
G25
H24
H26
K24
K26
M25
P24
P26
T25
V24
V26
W25

TECHNOLOGY COPR.
Title
748-POWER
Document Number R ev

748A01 A
Date: Sunday, September 05, 2004 Sheet 14 of 48
5 4 3 2 1

3D3V_SYS

12V_SYS
3D3V_SB
BC778 EC78
* 0.1uF
25V, Y5V, +80%/-20%
1000uF*
C0603 6.3V, +/-20%
R1132
270 CE35D80H200
+/-1%

D
D R0603 U26A 3D3V_SB D

4
Q54
3 3D3V_SYS
+
1 G
2 SDU3055L2
-
R1135

S
LM324 R1133 169

11
R1134 1K +/-1% BC779

D
1K R0603 U26B
* 0.1uF

4
+/-1% R0603 +/-5% Q50 25V, Y5V, +80%/-20%
R0603 2D5V_DDR 5 C0603
+
7 G
EC79 EC14 EC15 EC68 2.598 6 SDU3055L2
-
1000uF * * 1000uF* * 1000uF/NC

S
1000uF 6.3V, +/-20% LM324 R522 1K

11
6.3V, +/-20% 6.3V, +/-20% 6.3V, +/-20% CE35D80H200 R1136
205 R0603 1D8V_VCCSB
CE35D80H200 CE35D80H200 CE35D80H200 +/-1%
R0603
BC678 EC59
* 0.1uF
25V, Y5V, +80%/-20%
* 1000uF
6.3V, +/-20%
C0603 CE35D80H200

1.8V--SB
C C

3D3V_SB
1D5V_AGP POWER FOR NB/AGP
3D3V_SYS

R1137
340 EC60
+/-1% * 1000uF/NC
D

R0603 U26C 6.3V, +/-20%


4

Q51 CE35D80H200
10 +
8 G
9 SDU3055L2 3D3V_SB 3D3V_SYS
-
R526
S

LM324
11

R1138
301 VDDQ
+/-1% R1139 EC58
1K
R0603
R0603
150
+/-1%
* 1000uF
6.3V, +/-20%

D
+/-5% BC679 EC61 R0603 U26D CE35D80H200

4
B
* 0.1uF * 1000uF
6.3V, +/-20% 12
Q55
B
+
CE35D80H200 14 G
13 SDU3055L2
-

S
R1140 1K

11
R1141 LM324
205 R0603 1D8V_VCCNB
+/-1%
R0603
BC780 EC80
* 0.1uF
25V, Y5V, +80%/-20%
* 1000uF
6.3V, +/-20%
2D5V_DDR 3D3V_SYS C0603 CE35D80H200

1.9V--NB

U6 BC190
1 VIN VCNTL
VCNTL
8
7
* 0.1uF
25V, Y5V, +80%/-20%
1

BC191 R109 6 C0603


1K VCNTL
VCNTL 5
1uF/NC
2

VOUT 4 DDR_VTT
2

A 3 2 EC17 EC18 BC192 A


REFEN GND
* 470uF * 470uF/NC
* 0.1uF
1

BC193 R110 RT9173 6.3V, +/-20% 6.3V, +/-20% 25V, Y5V, +80%/-20%
* 0.1uF/NC
25V, Y5V, +80%/-20%
CE25D60H110 CE25D60H110 C0603

C0603 TECHNOLOGY COPR.


1K
2

Title
2.5V_DDR & 1.25_VTT
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 15 of 48
5 4 3 2 1
5 4 3 2 1

SB1.8V
D Vref=1.25V D
3D3V_SB 1D8V_SB

1
U7 + R111
Vin

4 Vout

ADJ
AME1117 750
BC194 Vref +/-1% BC195
* 10uF
10V, Y5V, +80%/-20% -
R0603
*
EC21
470uF * 0.1uF
25V, Y5V, +80%/-20%
4

C1206 6.3V, +/-20% C0603


CE25D60H110

R113
330
+/-1%
R0603

C C

5V_SB U36 AIC1086CE/NC 3D3V_SB


3 VIN VOUT 2
1 ADJ

ADJ

SB3.3V
5V_SB Vref=1.25V 3D3V_SB

B B
3

U8 + R112
Vin

4 Vout

ADJ

EC19 BC196 AME1117 196 EC20 BC197


* 22uF
50V, +/-20% * 10uF/NC Vref +/-1%
R0603
* 470uF
6.3V, +/-20% * 0.1uF/NC
25V, Y5V, +80%/-20%
CE20D50H110 C1206 - CE25D60H110 C0603
4

ADJ

R114
330
+/-1%
R0603

A A

TECHNOLOGY COPR.
Title
SB1.8V & SB3V & 5V_DUAL
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 16 of 48
5 4 3 2 1
5 4 3 2 1

CNR1
B1 RESERVED RESERVED A1
3D3V_SYS B2 A2
RESERVED RESERVED
B3 RESERVED GND A3
B4 GND RESERVED A4
ATTACH R1166 FOR NO CNR SKU B5 A5
RESERVED RESERVED
B6 RESERVED GND A6
B7 GND LAN_TXD2 A7
D B8 LAN_TXD1 LAN_TXD0 A8 D
3D3V_SYS -12V_SYS 5V_SB B9 A9
R1166 LAN_RSTSYNC GND
R1165 0/NC B10 A10 12V_SYS 3D3V_SB 5V_SYS
1K GND LAN_CLK
B11 LAN_RXD2 LAN_RXD1 A11
+/-5% R1167 B12 A12
R0603 10K LAN_RXD0 RESERVED
B13 GND USB+ A13
+/-5% D22 B14 A14
R0603 AC_RESETJ RESERVED GND
1 2 B15 +5VDUAL USB- A15
B16 USB_OC# +12V A16
1N4148W B17 A17
GND GND
CODEC_RSTJ 38 B18 -12V +3.3VDUAL A18
B19 +3.3VD +5VD A19
J9

C
3 3
2 PRI_DNJ B Q56 B20 A20
2 MMBT3904 GND GND
1 1 B21 EE_DOUT EE_DIN A21
B22 A22
E
EE_SHCLK EE_CS SMA1
HEADER_1X3 B23 A23
SMA0 GND SMB_A1 SMA2
B24 SMB_A0 SMB_A2 A24
19,20,21,22,26 SMB_CLK_MAIN B25 SMB_SCL SMB_SDA A25 SMB_DATA_MAIN 19,20,21,22,26
PRI_DNJ B26 A26
PRIMARY_DN# AC97_RESET# AC_RESETJ 26
B27 GND AC97_SD_IN2 A27 SDATI2 26
26,38 SYNC B28 AC97_SYNC AC97_SD_IN1 A28 SDATI1 26
26,38 SDATO B29 AC97_SD_OUT AC97_SD_IN0 A29 SDATI0 26,38
26,38 BIT_CLK B30 AC97_BITCLK GND A30

CNR
C C
R1170 R1172 R1173
10K R1171 10K 10K/NC

10K/NC
2-3 ENABLE CNR AUDIO

1-2 ENABLE PRIMARY AUDIO

5V_SYS

R1175 R1176
R1174 10K 10K
10K

SMA0
B SMA1 B
SMA2

R1177

10K/NC

A A

TECHNOLOGY COPR.
Title
EMPTY
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 17 of 48
5 4 3 2 1
8 7 6 5 4 3 2 1

D D

GPIO4 26

GPIO3 26 internal pull-low


0 1 Default (30~50K Ohm)
GPIO1 26
SPKR( LPC addr mapping) disable enable R409 un-stuff yes
GPIO0 26
SDATO( Trap mode) ROM PCI AD R410 un-stuff yes
C GPIO7 26
C
OC4-( SB debug mode) enable disable R411 un-stuff NO

SYNC( PCICLK PLL) enable disable NONE yes


2
4
6
8

RN76 R1157
0/NC
0/NC +/-5%
3D3V_SYS R0603
*
1
3
5
7

FID[0..3]
FID[0..3] 7

2D5V_DDR
3D3V_SB
2
4
6
8

RN70 max 2.625v


10K
8P4R0603 R152
10K
+/-5%
*

+/-5%
1
3
5
7

R0603
2
4
6
8

B RN71
NB Hardware Trap has internal pull-low in SiS748 chip FOR TRAP[0..3].
B
680
D

8P4R0603
Q22 (FID3) (FID2) (FID1) (FID0)
+/-5%
*1
3
5
7

G 11.0 0 0 0 0
RN72 2N7002 11.5 0 0 0 1
13 TRAP0
TRAP0
*
1 2 12.0 0 0 1 0
S

TRAP1 3 4 F ID0 12.5 0 0 1 1


13 TRAP1 5.0 0 1 0 0
TRAP2 5 6
13 TRAP2 5.5 0 1 0 1
TRAP3 7 8
D

13 TRAP3 6.0 0 1 1 0
1K Q23 6.5 0 1 1 1
+/-5% 7.0 1 0 0 0
8P4R0603 G 7.5 1 0 0 1
2N7002 8.0 1 0 1 0
8.5 1 0 1 1
S

F ID1 9.0 1 1 0 0
9.5 1 1 0 1
10.0 1 1 1 0
D

10.5 1 1 1 1
Q24

G
2N7002
S

F ID2
A A
D

Q25
TECHNOLOGY COPR.
G
2N7002 Title
Hardware Trap
S

F ID3
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 18 of 48
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3D3V_SYS

Main Clock Generator

2
2D5V_DDR
FB5
FB L0805 60 Ohm

1
2

U11 Damping Resistors


FB6 ICS952703 Place near to the
FB L0805 60 Ohm Clock Outputs
D CLK_3V 1 SATA FOR SRC
D
1

BC215 BC216 BC217 VDDREF


11 VDDZ
CLK_2.5V * 0.1uF
* 0.1uF
* 0.1uF 13
19
VDDPCI
VDDPCI_1
SRCCLKT
SRCCLKC
43
42
R161
R162
22
22
CK_100M_SATA 27
CK_100M_SATAJ 27
C0603 C0603 C0603 28
BC220 BC221 BC222 AVDD48 R1161 R1162
29 VDDAGP

*
BC686 BC225
10uF
* 0.1uF * 0.1uF
* 0.1uF
* 0.1uF
CPUCLK_0T 38 R163 10 CPUCLK0
CK_133M_CPU 6
49.9
+/-1%
49.9
+/-1%
16V, X5R, +/-10% C0603 C0603 C0603 37 R164 10 CPUCLK-0 R0603 R0603
CPUCLK_0C CK_133M_CPUJ 6
C1206 C0603 5 40 R165 0 748CCLK
GNDREF CPUCLK_1T CK_133M_S748 11
8 GNDZ
18 GNDPCI
24 47 R166 10 PICCLK0 CPU
GNDPCI_1 IOAPIC1 PICCLK0 7
25 46 R167 10 PICCLK1
GND48 IOAPIC0 PICCLK1 26 SB
32 GNDAGP
31 R168 22 AGPCLK0
AGPCLK0 CK_66M_S748 11
30 R169 22 AGPCLK1
AGPCLK1 CK_66M_AGP 24
44 9 R170 22 ZCLK0
VDDSRC ZCLK0 ZCLK0 13 *
10 R171 22 ZCLK1 NB&SB BC856
ZCLK1 ZCLK1 25
BC230 BC231 CLK_2.5V 48 10pF
VDDAPIC
* 0.1uF
* 0.1uF
39 GNDCPU
*FS2/PCICLK_F0
*FS3/PCICLK_F1
14
15
FS2
FS3
RN64 7
5
8
6
CK_33M_SIO 40
CK_33M_1394 32
C0603
DUMMY
C0603 C0603 45 16 3 4
GNDAPIC PCICLK0 CK_33M_PCI5 31
41 GNDSRC PCICLK1 17 1 * 2 CK_33M_PCI2 29
PCICLK2 20 7 8 CK_33M_PCI1 29
21 33 8P4R0603 5 6
*(PCI_STOP#)PCICLK3 CK_33M_PCI3 30
22 33 3 4
C 34 IREF
*(CPU_STOP#)PCICLK4
*(PD#)PCICLK5 23 1 * 2
CK_33M_PCI4
CK_33M_S964
30
25
C
R180 +/-5% RN65
475 2 FS0 R181 33 OSCI
**FS0/REF0 CK_14M_S964 26
+/-1% 3 FS1 R182 33 VOSCI
**FS1/REF1 CK_14M_AUDIO 38
R0603 4 R183 33/NC REFCLK2
R53 SATA FOR SRC **Mode/REF2
27 R187 22 USB12M
12_48MHz/SEL12_48#MHz* CK_12M_USB 27
26 R185 22 SIO48M
24_48MHz/SEL24_48#MHz**~ CK_48M_SIO 40
* BC860
10pF
12 SMB_CLK_MAIN C0603
SCLK SMB_CLK_MAIN 17,20,21,22,26
3D3V_SYS 33 SMB_DATA_MAIN
SDATA SMB_DATA_MAIN 17,20,21,22,26 DUMMY
FB7
2 1 36 VDDA R1164
FB L0805 60 Ohm BC245 BC246 3D3V_SYS
* 0.1uF
* 1nF
25V, NPO, +/-5% R186
Frequency Selection
R188
10K
C0603 C0603 10K 10K
+/-5% +/-5% +/-5% REFCLK2 BC684 10pFC0603 DUMMY

*
35 R0603 R0603 R0603
GNDA DUMMY DUMMY DUMMY

X1

X2
B B
6

7
3D3V_SYS FS1

BC861
R190
10K * 22pF
50V, NPO, +/-5% FSB_Sense[1] FSB_Sense[0] Bus Frequency
+/-5% C0603 1 2
R0603 1 0 RESERVED
7,26 FSB0
FSB0 R191 10K FS3 X1 1 1 133 MHz
XTAL-14.318MHz
BC247 BC248 0 1 166 MHz
SB--GPIO 1
J8 33pF
50V,NPO,+/-5% * * 33pF
50V,NPO,+/-5% 0 0 200 MHz
2 C0603 C0603

Header_1X2

3D3V_SYS

3D3V_SYS
FS3 FS2 FS1 FS0 CPU SRC ZCLK AGP PCI
R189 0 0 0 1 200.01 100.00 133.34 66.67 33.33
10K
R193 +/-5% 1 0 0 1 166.65 100.00 133.32 66.66 33.33
10K R0603
+/-5% FS0 1 1 0 1 133.34 100.00 133.34 66.67 33.33
R0603
FSB1 R197 10K FS2 R192 0 1 0 1 100.00 100.00 133.34 66.67 33.33
A 6,26 FSB1
10K A
+/-5%
SB--GPIO R0603
DUMMY
TECHNOLOGY COPR.
Title
CLK 952703
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 19 of 48
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Clock Buffer ( FOR 3 DDR SDRAM DIMMS )

1. Cypress CY28351C
D 2.
3.
ICS 93735
Hitachi CDCV851
DDRCLK[0..8]
DDRCLK[0..8] 21,22 D
4. Phaselink 102-08 DDRCLKJ[0..8]
5. Realtek RTM 680-648 DDRCLKJ[0..8] 21,22

CBVDD

U34
ICS 93705

CBVDD 15 VDDI2C
4 VDD
2D5V_DDR 11 VDD
21 VDD
28 By-Pass Capacitors
VDD Place near to the Clock Buffer
34 VDD
2

38 VDD
FB50 45 3 DDRCLK3
VDD CLK0 DDRCLK6
FB L0805 60 Ohm CLK1 5
10 DDRCLK2 DDRCLK8 BC751 10pFC0603 DUMMY
1

*
CLK2 DDRCLK5
CLK3 20
16 22 DDRCLK8 DDRCLK5 BC752 10pFC0603 DUMMY

*
BC754 BC755 AVDD CLK4 DDRCLK0
CLK5 46
* 0.1uF
* 10nF 44 DDRCLK4 DDRCLK2 BC753 10pFC0603 DUMMY

*
25V, Y5V, +80%/-20% CLK6 DDRCLK1
CLK7 39
C0603 C0603 29 DDRCLK7 DDRCLK6 BC756 10pFC0603 DUMMY
C C

*
CLK8
17 AGND CLK9 27
DDRCLK3 BC757 10pFC0603 DUMMY

*
SMB_CLK_MAIN 12 2 DDRCLKJ3
17,19,21,22,26 SMB_CLK_MAIN SCLK CLK#0
SMB_DATA_MAIN 37 6 DDRCLKJ6 DDRCLK0 BC758 10pFC0603 DUMMY
17,19,21,22,26 SMB_DATA_MAIN

*
SDATA CLK#1 DDRCLKJ2
CLK#2 9
SDCLKO_DDR 13 19 DDRCLKJ5 DDRCLK7 BC759 10pFC0603 DUMMY
12 SDCLKO_DDR

*
CLK_IN CLK#3 DDRCLKJ8
CLK#4 23
47 DDRCLKJ0 DDRCLK4 BC760 10pFC0603 DUMMY

*
CLK#5 DDRCLKJ4
CLK#6 43
40 DDRCLKJ1 DDRCLK1 BC761 10pFC0603 DUMMY

*
CLK#7 DDRCLKJ7
CLK#8 30
CLK#9 26
14 CLK_IN#
33 BFB_OUT R1131 22 FB_OUT
FB_OUT FB_OUT
35 FB_IN FB_OUT# 32
DDRCLKJ8 BC762 10pFC0603
10pFDUMMY

*
DDRCLKJ5 BC763 10pFC0603 DUMMY

*
DDRCLKJ2 BC764 C0603 DUMMY

*
36 DDRCLKJ6 BC765 10pFC0603 DUMMY

*
FB_IN#
DDRCLKJ3 BC766 10pFC0603 DUMMY

*
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DDRCLKJ0 BC767 10pFC0603 DUMMY

*
B DDRCLKJ7 BC768 10pFC0603 DUMMY
B
1
7
8
18
24
25
31
41
42
48

*
DDRCLKJ4 BC769 10pFC0603 DUMMY

*
DDRCLKJ1 BC770 10pFC0603 DUMMY

*
FB_OUT BC771 27pFC0603

*
FB51
2D5V_DDR

2 1 CBVDD
BC772

FB L0805 60 Ohm * 10nF


*
BC774
0.1uF
25V, Y5V, +80%/-20%
C0603
C0603

BC775 BC776 BC777


* 10nF
* 0.1uF
* 0.1uF

C0603 C0603 C0603

A A

TECHNOLOGY COPR.
Title
Clock Buffer
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 20 of 48
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
2D5V_DDR
D DRVREF 2D5V_DDR
DDRVREF 22
D DRVREF

108
120
148
168

184
DIMM1

38
46
70
85

82

108
120
148
168

184
7

1
DDR_DIMM DIMM2

38
46
70
85

82
MD[0..63] 12,22,23

1
DDR_DIMM

VDDSPD/VCC3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDID

VREF/NC

VDDSPD/VCC3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDID

VREF/NC
15 2 MD0
VDDQ DQ0 MD1 MD0
22 VDDQ DQ1 4 15 VDDQ DQ0 2
30 6 MD2 22 4 MD1
VDDQ DQ2 MD3 VDDQ DQ1 MD2
54 VDDQ DQ3 8 30 VDDQ DQ2 6
MD4 MD3
D 62
77
VDDQ
VDDQ
DQ4
DQ5
94
95 MD5
54
62
VDDQ
VDDQ
DQ3
DQ4
8
94 MD4 D
96 98 MD6 77 95 MD5
VDDQ VDD VDDQ VDDID DQ6 MD7 VDDQ DQ5 MD6
104 VDDQ DQ7 99 96 VDDQ DQ6 98
112 3.3V 3.3V OPEN 104 VDD VDDQ VDDID 99 MD7
VDDQ 3.3V 2.5V VSS MD8 VDDQ 3.3V 3.3V OPEN DQ7
128 VDDQ DQ8 12 112 VDDQ
136 2.5V 2.5V OPEN 13 MD9 128 3.3V 2.5V VSS 12 MD8
VDDQ 2.5V 1.8V VSS DQ9 MD10 VDDQ 2.5V 2.5V OPEN DQ8 MD9
143 VDDQ DQ10 19 136 VDDQ DQ9 13
156 1.8V 1.8V OPEN 20 MD11 143 2.5V 1.8V VSS 19 MD10
VDDQ DQ11 MD12 VDDQ 1.8V 1.8V OPEN DQ10 MD11
164 VDDQ DQ12 105 156 VDDQ DQ11 20
172 106 MD13 164 105 MD12
VDDQ DQ13 MD14 VDDQ DQ12 MD13
180 VDDQ DQ14 109 172 VDDQ DQ13 106
110 MD15 180 109 MD14
12,22,23 MAA[0..14] DQ15 VDDQ DQ14 MD15
DQ15 110
MAA0 48 23 MD16
MAA1 A0 DQ16 MD17 MAA0 MD16
43 A1 DQ17 24 48 A0 DQ16 23
MAA2 41 28 MD18 MAA1 43 24 MD17

PIN 92
MAA3 A2 DQ18 MD19 MAA2 A1 DQ17 MD18
130 31 41 28

PIN 92
A3 DQ19 A2 DQ18

PIN 184
MAA4 37 114 MD20 MAA3 130 31 MD19
A4 DQ20 A3 DQ19

PIN 184
MAA5 32 117 MD21 MAA4 37 114 MD20
MAA6 A5 DQ21 MD22 MAA5 A4 DQ20 MD21
125 A6 DQ22 121 32 A5 DQ21 117
MAA7 29 123 MD23 MAA6 125 121 MD22
MAA8 A7 DQ23 MAA7 A6 DQ22 MD23
122 A8 29 A7 DQ23 123
MAA9 27 33 MD24 MAA8 122
MAA10 A9 DQ24 MD25 MAA9 A8 MD24
141 A10 DQ25 35 27 A9 DQ24 33
MAA13 118 39 MD26 MAA10 141 35 MD25
MAA14 A11 DQ26 MD27 MAA13 A10 DQ25 MD26
115 NC/A12 DQ27 40 118 A11 DQ26 39
167 126 MD28 MAA14 115 40 MD27
NC/A13 DQ28 MD29 NC/A12 DQ27 MD28
DQ29 127 167 NC/A13 DQ28 126
MAA11 59 131 MD30 127 MD29
MAA12 BA0 DQ30 MD31 MAA11 DQ29 MD30
C 12,22,23 DQM[0..7] 52
113
BA1
NC/BA2
DQ31 133
MAA12
59
52
BA0
BA1
DQ30
DQ31
131
133 MD31 C
53 MD32 113
DQM0 DQ32 MD33 NC/BA2 MD32
97 55 53
PIN 53
DQM1 DQMB0 DQ33 MD34 DQM0 DQ32 MD33
107 57 97 55

PIN 53
DQMB1 DQ34 DQMB0 DQ33

PIN 145
DQM2 119 60 MD35 DQM1 107 57 MD34
DQMB2 DQ35 DQMB1 DQ34

PIN 145
DQM3 129 146 MD36 DQM2 119 60 MD35
DQM4 DQMB3 DQ36 MD37 DQM3 DQMB2 DQ35 MD36
149 147 129 146
PIN 52

2D5V_DDR DQM5 DQMB4 DQ37 MD38 DQM4 DQMB3 DQ36 MD37


159 150 149 147

PIN 52
DQMB5 DQ38 2D5V_DDR DQMB4 DQ37
PIN 144

DQM6 169 151 MD39 DQM5 159 150 MD38


DQMB6 DQ39 DQMB5 DQ38

PIN 144
DQM7 177 DQM6 169 151 MD39
R225 8.2K DQMB7 MD40 DQM7 DQMB6 DQ39
140 DQMB8 DQ40 61 177 DQMB7
64 MD41 R226 8.2K 140 61 MD40
CSAJ0 DQ41 MD42 DQMB8 DQ40 MD41
12,23 CSAJ0 157 CS0 DQ42 68 DQ41 64
CSAJ1 158 69 MD43 CSAJ2 157 68 MD42
12,23 CSAJ1 CS1 DQ43 12,23 CSAJ2 CS0 DQ42
71 153 MD44 CSAJ3 158 69 MD43
NC/CS2 DQ44 12,23 CSAJ3 CS1 DQ43
163 155 MD45 71 153 MD44
NC/CS3 DQ45 MD46 NC/CS2 DQ44 MD45
DQ46 161 163 NC/CS3 DQ45 155
RASAJ 154 162 MD47 161 MD46
CASAJ RAS DQ47 RASAJ DQ46 MD47
65 CAS 12,22,23 RASAJ 154 RAS DQ47 162
MWAJ 63 CASAJ 65
12,22,23 DQS[0..7] WE 12,22,23 CASAJ CAS
72 MD48 MWAJ 63
DQ48 12,22,23 MWAJ WE
DQS0 5 73 MD49 72 MD48
DQS1 DQS0 DQ49 MD50 DQS0 DQ48 MD49
14 DQS1 DQ50 79 5 DQS0 DQ49 73
DQS2 25 80 MD51 DQS1 14 79 MD50
DQS3 DQS2 DQ51 MD52 DQS2 DQS1 DQ50 MD51
36 DQS3 DQ52 165 25 DQS2 DQ51 80
DQS4 56 166 MD53 DQS3 36 165 MD52
DQS5 DQS4 DQ53 MD54 DQS4 DQS3 DQ52 MD53
67 DQS5 DQ54 170 56 DQS4 DQ53 166
DQS6 78 171 MD55 DQS5 67 170 MD54
DQS7 DQS6 DQ55 DQS6 DQS5 DQ54 MD55
86 DQS7 78 DQS6 DQ55 171
MD56 DQS7
B 47 DQS8 DQ56
DQ57
83
84 MD57
86
47
DQS7
DQS8 DQ56 83 MD56 B
87 MD58 84 MD57
FRONT PIN 1

CKE0 DQ58 MD59 DQ57 MD58


21 88 87

FRONT PIN 1
12 CKE0
PIN 93

CKE1 CKE0 DQ59 MD60 CKE2 DQ58 MD59


111 174 21 88
BACK

12 CKE1 12 CKE2

PIN 93
CKE1 VOLTAGE KEY DQ60 MD61 CKE3 CKE0 DQ59 MD60
175 111 174

BACK
DQ61 12 CKE3 CKE1 DQ60
DDRCLK1 16 178 MD62 VOLTAGE KEY 175 MD61
20 DDRCLK1 CK0/(NC) DQ62 DQ61
DDRCLKJ1 17 179 MD63 DDRCLK4 16 178 MD62
20 DDRCLKJ1 CK0/(NC) DQ63 20 DDRCLK4 CK0/(NC) DQ62
DDRCLKJ4 17 179 MD63
20 DDRCLKJ4 CK0/(NC) DQ63
DDRCLK0 137
20 DDRCLK0 CK1(CK0)
DDRCLKJ0 138 44 DDRCLK3 137
20 DDRCLKJ0 CK1(CK0) CB0 20 DDRCLK3 CK1(CK0)
45 DDRCLKJ3 138 44
CB1 20 DDRCLKJ3 CK1(CK0) CB0
DDRCLK2 76 49 45
20 DDRCLK2 CK2/(NC) CB2 CB1
DDRCLKJ2 75 51 DDRCLK5 76 49
20 DDRCLKJ2 CK2/(NC) CB3 20 DDRCLK5 CK2/(NC) CB2
134 DDRCLKJ5 75 51
CB4 20 DDRCLKJ5 CK2/(NC) CB3
VDDQ= 2.5V 1.8V 3.3V 135 134
CB5 VDDQ= 2.5V 1.8V 3.3V CB4
CB6 142 CB5 135
FRONT VIEW 144 142
CB7 FRONT VIEW CB6
181 SA0 CB7 144
182 9 2D5V_DDR R227 8.2K 181
SA1 NC SA0
183 SA2 NC/ (RESET) 10 182 SA1 NC 9
NC 101 183 SA2 NC/ (RESET) 10
SMB_CLK_MAIN 92 102 101
17,19,20,22,26 SMB_CLK_MAIN SCL NC NC
SMB_DATA_MAIN 91 103 92 102
17,19,20,22,26 SMB_DATA_MAIN SDA NC/ (FETEN) 17,19,20,22,26 SMB_CLK_MAIN SCL NC
WP 90 173 91 103
WP NC 17,19,20,22,26 SMB_DATA_MAIN SDA NC/ (FETEN)
WP 90 173
22 WP WP NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A A
3
11
18
26
34
42
50
58
66
74
81
89
93
100
116
124
132
139
145
152
160
176

3
11
18
26
34
42
50
58
66
74
81
89
93
100
116
124
132
139
145
152
160
176
TECHNOLOGY COPR.
Title
DDR Slot 1 / 2
Document Number R ev

748A01 A
Date: Sunday, September 05, 2004 Sheet 21 of 48

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

OK
2D5V_DDR
DDRVREF
DDRVREF 21

108
120
148
168

184
DIMM3

38
46
70
85

82
7

1
DDR_DIMM
MD[0..63] 12,21,23 DDRVREF GEN. & DECOUPLING

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDID

VREF/NC
VDDSPD/VCC3
D 15
22
VDDQ DQ0 2
4
MD0
MD1
D
VDDQ DQ1 MD2
30 VDDQ DQ2 6
54 8 MD3 2D5V_DDR
VDDQ DQ3 MD4
62 VDDQ DQ4 94
77 95 MD5
VDDQ DQ5 MD6
96 VDDQ DQ6 98
104 VDD VDDQ VDDID 99 MD7 R228 BC288 BC289 BC290 BC291
VDDQ DQ7
112
128
VDDQ
VDDQ
3.3V
3.3V
3.3V
2.5V
OPEN
VSS
DQ8 12 MD8
75
+/-5% * 10nF
* 10nF
* 10nF
* 10nF

136 2.5V 2.5V OPEN 13 MD9 R0603 C0603 C0603 C0603 C0603
VDDQ 2.5V 1.8V VSS DQ9 MD10
143 VDDQ DQ10 19
156 1.8V 1.8V OPEN 20 MD11 DDRVREF
VDDQ DQ11 DDRVREF 21
164 105 MD12
VDDQ DQ12 MD13 BC292 BC293 BC294 BC295
172 VDDQ DQ13 106

12,21,23 MAA[0..14]
180 VDDQ DQ14
DQ15
109
110
MD14
MD15
R229
75 * 10nF
* 10nF
* 10nF
* 10nF

+/-5% C0603 C0603 C0603 C0603


MAA0 48 23 MD16 R0603
MAA1 A0 DQ16 MD17
43 A1 DQ17 24
MAA2 41 28 MD18

PIN 92
MAA3 A2 DQ18 MD19 close to close to close to close to
130 A3 DQ19 31
resistor DIMM1 VREF DIMM2 VREF DIMM3 VREF

PIN 184
MAA4 37 114 MD20
MAA5 A4 DQ20 MD21 divider pin pin pin
32 A5 DQ21 117
MAA6 125 121 MD22
MAA7 A6 DQ22 MD23
29 A7 DQ23 123
MAA8 122
MAA9 A8 MD24
27 A9 DQ24 33
MAA10 141 35 MD25
A10 DQ25
C MAA13
MAA14
118
115
A11 DQ26 39
40
MD26
MD27 C
NC/A12 DQ27 MD28
167 NC/A13 DQ28 126
127 MD29
MAA11 DQ29 MD30
59 BA0 DQ30 131
MAA12 52 133 MD31
12,21,23 DQM[0..7] BA1 DQ31
113 NC/BA2
53 MD32
DQM0 DQ32 MD33 DIMM DECOUPLING
97 55
PIN 53

DQM1 DQMB0 DQ33 MD34


107 DQMB1 DQ34 57
PIN 145

DQM2 119 60 MD35


DQM3 DQMB2 DQ35 MD36
129 DQMB3 DQ36 146
DQM4 149 147 MD37
PIN 52

2D5V_DDR DQM5 DQMB4 DQ37 MD38


159 DQMB5 DQ38 150
PIN 144

DQM6 169 151 MD39 2D5V_DDR


DQM7 DQMB6 DQ39
177 DQMB7
R1063 8.2K 140 61 MD40
DQMB8 DQ40 MD41
DQ41 64 BC296
CSAJ4 157 68 MD42 BC297
12,23 CSAJ4 CS0 DQ42
CSAJ5 158 69 MD43 0.1uF 0.1uF BC298 0.1uF
12,23 CSAJ5

*
CS1 DQ43 MD44
71 NC/CS2 DQ44 153
163 155 MD45
NC/CS3 DQ45 MD46
DQ46 161
RASAJ 154 162 MD47 BC299 0.1uF/NC BC300 0.1uF/NC BC301 0.1uF/NC
12,21,23 RASAJ RAS DQ47
CASAJ 65
12,21,23 CASAJ

*
MWAJ CAS
12,21,23 MWAJ 63 WE
72 MD48
12,21,23 DQS[0..7] DQS0 DQ48 MD49
5 DQS0 DQ49 73
DQS1 14 79 MD50 BC302 0.1uF/NC 0.1uF/NC BC304 0.1uF/NC
DQS2 DQS1 DQ50 MD51 BC303
25 80
B B

*
DQS3 DQS2 DQ51 MD52
36 DQS3 DQ52 165
DQS4 56 166 MD53
DQS5 DQS4 DQ53 MD54
67 DQS5 DQ54 170
DQS6 78 171 MD55 BC305 BC306 0.1uF BC307 0.1uF
DQS7 DQS6 DQ55 0.1uF
86

*
DQS7 MD56
47 DQS8 DQ56 83
84 MD57
DQ57 MD58
87
FRONT PIN 1

CKE4 DQ58 MD59 BC308 0.1uF/NC BC309 0.1uF/NC BC310 0.1uF/NC


12 CKE4 21 88
PIN 93

CKE5 CKE0 DQ59 MD60


111 174
BACK

12 CKE5

*
CKE1 VOLTAGE KEY DQ60 MD61
DQ61 175
DDRCLK7 16 178 MD62
20 DDRCLK7 CK0/(NC) DQ62
DDRCLKJ7 17 179 MD63
20 DDRCLKJ7 CK0/(NC) DQ63 BC312 0.1uF/NC BC313 0.1uF/NC
DDRCLK6 137 BC311 0.1uF/NC
20 DDRCLK6

*
DDRCLKJ6 CK1(CK0)
20 DDRCLKJ6 138 CK1(CK0) CB0 44
CB1 45
DDRCLK8 76 49
20 DDRCLK8 CK2/(NC) CB2
DDRCLKJ8 75 51
20 DDRCLKJ8 CK2/(NC) CB3
CB4 134
VDDQ= 2.5V 1.8V 3.3V 135
CB5
CB6 142
FRONT VIEW 144
CB7
181 SA0
2D5V_DDR R1064 8.2K 182 9
SA1 NC
183 SA2 NC/ (RESET) 10
NC 101
SMB_CLK_MAIN 92 102
17,19,20,21,26 SMB_CLK_MAIN SCL NC
SMB_DATA_MAIN 91 103
A
17,19,20,21,26 SMB_DATA_MAIN
21 WP
WP 90
SDA
WP
NC/ (FETEN)
NC 173 A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

TECHNOLOGY COPR.
3
11
18
26
34
42
50
58
66
74
81
89
93
100
116
124
132
139
145
152
160
176

Title
DDR SLOT3
Document Number R ev

748A01 A
Date: Sunday, September 05, 2004 Sheet 22 of 48
8 7 6 5 4 3 2 1
RASAJ
12,21,22 RASAJ MWAJ
12,21,22 MWAJ CASAJ
12,21,22 CASAJ SSTL-2 Termination Resistors
MD[0..63] (Note: The termination resistors are only for DDR application)
MD[0..63] 12,21,22 MAA[0..14]
DQM[0..7]
DQM[0..7] 12,21,22 DDR
OK CSAJ[0..5]
MAA[0..14]

CSAJ[0..5]
12,21,22

12,21,22
DQS[0..7] Rs Rtt
DQS[0..7] 12,21,22 MD/DQM(/DQS) SSTL-2 10/0 33/47
MA/Control SSTL-2 10/0 22/33
CS SSTL-2 10/0 22/33
D CKE LV-CMOS/OD 2.5V
D

DECOUPLING CAPACITOR FOR SSTL-2 END TERMIANTION VTT ISLAND


Pullup resistance can reswap by layout result. 0603 Package placed within 350mils of VTT Termination R-packs
DDR_VTT
DDR_VTT

DUMMY ONE HALF DEPEND ON LAYOUT


RN6 33 RN7 33
MD12
MD8
2
4
* 1
3
MD27
MD31
2
4
* 1
3
MD3 6 5 MD26 6 5
MD7 8 7 MD30 8 7 BC314 BC315 BC316 0.1uF BC317 0.1uF
RN8 33 RN9 33 0.1uF 0.1uF

*
MD6
MD2
2
4
* 13 MD37
MD33
2
4
* 13
DQM0 6 5 MD36 6 5
DQS0 8 7 MD32 8 7 BC318 0.1uF/NC BC319 0.1uF/NC BC320 0.1uF/NC BC321 0.1uF
RN10 33 RN11 33

*
MD1
MD5
2
4
* 13 MD38
MD34
2
4
* 13
MD4 6 5 DQM4 6 5
MD0 8 7 DQS4 8 7 BC322 0.1uF/NC BC323 0.1uF BC324 0.1uF/NC BC325 0.1uF
RN12 33 RN13 33

*
C DQM1
DQS1
2
4
* 13 MD44
MD40
2
4
* 13 C
MD13 6 5 MD35 6 5
MD9 8 7 MD39 8 7 BC326 0.1uF/NC BC327 0.1uF/NC BC328 0.1uF BC329 0.1uF
RN14 33

*
MD11
MD10
2
4
* 13 MD45
MD41
R233
R234
33
33
MD15 6 5 MD59 R235 33
MD14 8 7 MD63 R236 33
RN15 33 RN16 33
DQS2
MD21
2
4
* 13 MD46
MD42
2
4
* 13
MD17 6 5 DQM5 6 5
MD16 8 7 DQS5 8 7 BC330 0.1uF BC331 0.1uF BC333 0.1uF
RN17 33 RN18 33 BC332 0.1uF

*
MD22 2
4
* 1
3
MD52
MD48
2
4
* 1
3
MD18 6 5 MD47 6 5
DQM2 8 7 MD43 8 7 BC334 0.1uF BC335 0.1uF/NC BC336 0.1uF BC337 0.1uF
RN19 33 RN20 33

*
MD25
MD29
2
4
* 13 DQS6
DQM6
2
4
* 13
MD28 6 5 MD53 6 5
MD24 8 7 MD49 8 7 BC338 0.1uF/NC BC339 0.1uF BC340 0.1uF/NC BC341 0.1uF
RN21 33

*
DQM3
DQS3
R237
R238
33
33
MD51
MD55
2
4
* 1
3
MD19 R239 33 MD50 6 5
MD23 R240 33 MD54 8 7 BC342 0.1uF/NC BC343 0.1uF/NC BC344 0.1uF/NC BC345 0.1uF/NC
MD20 R241 33
B B

*
Pullup resistance can reswap by layout result.

DDR_VTT DDR_VTT

RN22 33
MD57
MD61
2
4
* 13 MAA14
MAA13
R242
R243
33
33
MD56 6 5 MAA9 R244 33
MD60 8 7 MAA7 R245 33
RN23 33 MAA8 R246 33
MD58
MD62
2
4
* 13 MAA5
MAA6
R247
R248
33
33
DQS7 6 5 MAA4 R249 33
DQM7 8 7 MAA3 R250 33
RN24 47 MAA2 R251 33
CSAJ3
CSAJ5
2
4
* 13 MAA1
MAA0
R252
R253
33
33
CSAJ2 6 5 MAA10 R254 33
CSAJ4 8 7 MAA12 R255 33
MAA11 R256 33
CSAJ0 R257 47 RASAJ R258 33
CSAJ1 R259 47 MWAJ R260 33
A CASAJ R261 33 A

TECHNOLOGY COPR.
Title
DDR Termination Res
Document Number R ev

748A01 A
Date: Sunday, September 05, 2004 Sheet 23 of 48
8 7 6 5 4 3 2 1
SBAJ[0..7]
11 SBAJ[0..7]
ST[0..2] 5V_SYS 12V_SYS
NOTE: This AGP slot support
11 ST[0..2]
AC-BE[0..3]
both AGP3.0 display card GCDET- on card GCDET- AVREFCG APERR
11 AC-BE[0..3]
AAD[0..31]
VDDQ and SiS301 video bridge
3D3V_SB GND 0V 0.35V 0V
11

11
AAD[0..31]

ADSTBF[0..1]
ADSTBF[0..1]
OK card.
3D3V_SYS OPEN 1.47V 0.75V 1.5V
ADSTBS[0..1] VDDQ 3D3V_SYS
11 ADSTBS[0..1]

D D
AGP1
B1 OVRCNT# +12V A1
B2 +5V TYPEDET# A2
B3 A3 GCDETJ
+5V GC_AGP8X_DET GCDETJ 11
B4 USB+ USB- A4
B5 GND GND A5
INTJB B6 A6 INTJA
25,29,30,31 INTJB INTB# INTA# INTJA 25,29,30,31
CK_66M_AGP B7 A7 PCIRSTJ0
19 CK_66M_AGP CLK RST# PCIRSTJ0 25,29,30,31,40
AREQ B8 A8 AGNT
11 AREQ REQ# GNT# AGNT 11
B9 VCC3.3 VCC3.3 A9
ST0 B10 A10 ST1
ST2 ST0 ST1
B11 ST2 MB_AGP8X_DET A11
RBF B12 A12 DBI_HI
11 RBF RBF# PIPE# DBI_HI 11
B13 GND GND A13
B14 A14 WBF
11 DBI_LOW RESERVEDB14 WBF# WBF 11
SBAJ0 B15 A15 SBAJ1
SBA0 SBA1
B16 VCC3.3 VCC3.3 A16
SBAJ2 B17 A17 SBAJ3
SBSTBF SBA2 SBA3 SBSTBS
11 SBSTBF B18 SB_STB SB_STB# A18 SBSTBS 11 close to AGP SLOT
B19 GND GND A19
SBAJ4 B20 A20 SBAJ5
SBAJ6 SBA4 SBA5 SBAJ7 3D3V_SYS 5V_SYS VDDQ
B21 SBA6 SBA7 A21
B22 DBI_LO DBI_HI A22
B23 GND GND A23
B24 VCC3_AUX RESERVEDA24 A24
B25 A25
C AAD31 B26
VCC3.3
AD31
VCC3.3
AD30 A26 AAD30 R262 C
AAD29 B27 A27 AAD28 124
AD29 AD28 R263 R264
B28 VCC3.3 VCC3.3 A28 R0603
AAD27 B29 A29 AAD26 10K 10K
AAD25 B30
AD27 AD26
A30 AAD24 +/-5% +/-5% R265 54.9 +/-1% AVREFCG
AD25 AD24 R0603 R0603
B31 GND GND A31
ADSTBF1 B32 A32 ADSTBS1

D
AAD23 AD_STB1 AD_STB1# AC-BE3 R266
B33 AD23 C/BE3# A33
B34 A34 Q26 124 BC362
VDDQ VDDQ
AAD21
AAD19
B35
B36
AD21
AD19
AD22
AD20
A35
A36
AAD22
AAD20 G
*
R0603
+/-1%
10nF

B37 A37 2N7002 C0603

C
AAD17 GND GND AAD18 4.3K
B38 A38

S
AC-BE2 AD17 AD18 AAD16 GCDETJ R267 Q27
B39 C/BE#2 AD16 A39 B
B40 A40 MMBT3904
A IRDY VDDQ VDDQ AFRAME
B41 A41 AFRAME 11

E
11 AIRDY IRDY# FRAME#

VDDQ

B46 A46 ATRDY


11 ADEVSEL DEVEL# TRDY# ATRDY 11
B47 A47 ASTOP R268
VDDQ STOP# ASTOP 11
APERR B48 A48 PMEJ 8.2K
PERR# PME# PMEJ 26,29,30,31,40
B49 A49 +/-5%
GND GND APAR R0603
11 ASERR B50 SERR# PAR A50 APAR 11
AC-BE1 B51 A51 AAD15 APERR
C/BE1# AD15
B52 A52

D
VDDQ VDDQ
B AAD14
AAD12
B53
B54
AD14 AD13 A53
A54
AAD13
AAD11 Q28
B
AD12 AD11
B55 GND GND A55
AAD10 B56 A56 AAD9 G
AAD8 AD10 AD9 AC-BE0 2N7002
B57 AD8 C/BE0# A57
B58 A58

S
ADSTBF0 VDDQ VDDQ ADSTBS0
B59 AD_STB0 AD_STB0# A59
AAD7 B60 A60 AAD6 R269
AD7 AD6 1K
B61 GND GND A61
AAD5 B62 A62 AAD4 +/-5%
AAD3 AD5 AD4 AAD2 R0603
B63 AD3 AD2 A63
B64 VDDQ VDDQ A64
AAD1 B65 A65 AAD0
AVREFCG AD1 AD0
B66 VREF_CG VREF_GC A66 AVREFGC 11
1
2
3

BC363
AGP_SLOT
* 0.1uF
1
2
3

AGP CONNECTOR DECOUPLING C0603 close to


748
put CAP close to AGP slot each POWER PIN

VDDQ 3D3V_SYS

12V_SYS 5V_SYS
A BC364 BC365 BC366 BC367 BC368 BC369 BC370 BC371 BC372 BC373 BC374 BC375 A
* 10nF
* 10nF
* 10nF
* 10nF/NC
* 10nF/NC
* 10nF/NC
* 10nF
* 10nF
* 10nF
* 10nF/NC
* 10nF/NC
* 10nF/NC
*
BC376
10nF
*
BC377
10nF
C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603
C0603 C0603 TECHNOLOGY COPR.
Title
AGP
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 24 of 48
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1D8V_VCCSB

OK
BC378 BC379
* 10nF
* 0.1uF

U14A C0603 C0603

IDEAVDD W1
PREQJ4 F1 W2
31 PREQJ4 PREQ4# IDEAVSS
PREQJ3 F2
30 PREQJ3 PREQ3#
PREQJ2 I CHRDYA
D 30
29
PREQJ2
PREQJ1
PREQJ1
F3
F4
PREQ2#
PREQ1#
ICHRDYA
IDREQA
AE15
AD14 IDEREQA
ICHRDYA
IDEREQA
37
37
D
PREQJ0 E1 AC15 IDEIRQA
29 PREQJ0 PREQ0# IIRQA IDEIRQA 37
AE16 CBLIDA
CBLIDA CBLIDA 37
PGNTJ4 H4
31 PGNTJ4 PGNT4#
PGNTJ3 G1 AF15 IDEIORJA
30 PGNTJ3 PGNT3# IIORA# IDEIORJA 37
PGNTJ2 G2 AC14 IDEIOWJA
30 PGNTJ2 PGNT2# IIOWA# IDEIOWJA 37
PGNTJ1 G3 AD15 IDACKJA
29 PGNTJ1 PGNT1# IDACKA# IDACKJA 37
PGNTJ0 G4
29 PGNTJ0 PGNT0#
AE22 I CHRDYB
ICHRDYB ICHRDYB 37
INTJA F5 AD21 IDEREQB
24,29,30,31 INTJA INTA# IDREQB IDEREQB 37
INTJB E4 AC22 IDEIRQB
24,29,30,31 INTJB INTB# IIRQB IDEIRQB 37
INTJC E3 AE23 CBLIDB
29,30,31 INTJC INTC# CBLIDB CBLIDB 37
3D3V_SYS INTJD E2
29,30,31,32 INTJD INTD# IDEIORJB
IIORB# AF22 IDEIORJB 37
FRAMEJ M1 AC21 IDEIOWJB
29,30,31,32 FRAMEJ FRAME# IIOWB# IDEIOWJB 37
IR D YJ N4 AD22 IDACKJB
29,30,31,32 IRDYJ IRDY# IDACKB# IDACKJB 37
R271 TR DYJ N3
4.7K 29,30,31,32 TRDYJ STOPJ TRDY# IDESAA2
29,30,31,32 STOPJ P4 STOP# IDSAA2 AC16
+/-5% AF16 IDESAA1
R0603 SERRJ IDSAA1 IDESAA0
29,30,31,32 SERRJ P3 SERR# IDSAA0 AD16
DUMMY PAR P2
29,30,31,32 PAR PAR
PCIRSTJ

DEVSELJ N2 AE17 IDECSJA1


29,30,31,32 DEVSELJ DEVSEL# IDECSA1# IDESAA[0..2] 37
PLOCKJ N1 AF17 IDECSJA0
29,30,31 PLOCKJ PLOCK# IDECSA0#

I
CK_33M_S964 W3 AF24 IDESAB2
19 CK_33M_S964 PCICLK IDSAB2 IDECSJA[0..1] 37
R272 33 PCIRSTJ B3 AF23 IDESAB1
24,29,30,31,40 PCIRSTJ0 R273 33 PCIRST# IDSAB1 IDESAB0
32 PCIRSTJ1 IDSAB0 AD23
R274 33
13,37 PCIRSTJ2 C/BEJ3 IDECSJB1
K3 C/BE3# IDECSB1# AF25 IDESAB[0..2] 37

D
C/BEJ2 IDECSJB0
C C/BEJ1
M2
P1
C/BE2#
C/BE1#
IDECSB0# AE24
C
C/BEJ0 U4 C/BE0# IDECSJB[0..1] 37
AF14 IDEDA0
AD0 IDA0 IDEDA1
W4 AD0 IDA1 AD13
29,30,31,32 C/BEJ[0..3]

I
AD1 IDEDA2

E
V1 AD1 IDA2 AF13
AD2 V2 AD12 IDEDA3
AD3 AD2 IDA3 IDEDA4
V3 AD3 IDA4 AF12
AD4 V4 AD11 IDEDA5
AD5 AD4 IDA5 IDEDA6
U1 AD5 IDA6 AF11
1D8V_VCCSB AD6 U2 AF10 IDEDA7
AD7 AD6 IDA7 IDEDA8
U3 AD7 IDA8 AE10
AD8 T1 AE11 IDEDA9
AD9 AD8 IDA9 IDEDA10
T2 AD9 IDA10 AC11
AD10 T3 AE12 IDEDA11
AD11 AD10 IDA11 IDEDA12
T4 AD11 IDA12 AC12
R275 BC380 AD12 R1 AE13 IDEDA13
150 AD12 IDA13
+/-1% * 0.1uF AD13
AD14
R2
R3
AD13
AD14
IDA14
IDA15
AC13
AE14
IDEDA14
IDEDA15
R0603 C0603 AD15 R4
AD16 AD15 IDEDB0
M3 AD16 IDB0 AF21 IDEDA[0..15] 37
SZVREF AD17 M4 AD20 IDEDB1
BC381 AD18 AD17 IDB1 IDEDB2
L1 AD18 IDB2 AF20
R276
49.9 * 0.1uF AD19
AD20
L2
L3
AD19
AD20
IDB3
IDB4
AD19
AF19
IDEDB3
IDEDB4
+/-1% C0603 AD21 L4 AD18 IDEDB5
R0603 AD22 AD21 IDB5 IDEDB6
K1 AD22 IDB6 AF18
AD23 K2 AD17 IDEDB7
AD24 AD23 IDB7 IDEDB8
K4 AD24 IDB8 AC17
AD25 J1 AE18 IDEDB9
AD26 AD25 IDB9 IDEDB10
B AD27
J2
J3
AD26
AD27 M U T I O L IDB10
IDB11
AC18
AE19 IDEDB11 B
AD28 J4 AC19 IDEDB12
AD29 AD28 IDB12 IDEDB13
H1 AD29 IDB13 AE20
AD30 IDEDB14
Z1XAVDD

Z4XAVDD

H2 AC20
Z1XAVSS

Z4XAVSS
ZCMP_N

AD30 IDB14
ZCMP_P
ZSTB0#

ZSTB1#

AD31 IDEDB15
ZUREQ
ZDREQ

H3 AE21
ZVREF
ZSTB0

ZSTB1

ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZAD16
AD31 IDB15
ZCLK

ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
29,30,31,32 AD[0..31] IDEDB[0..15] 37
SiS964
AC26
AB26
V24
W26
R25
T26
Y24
Y23
AA24
AA25

AB25
Y22
AA23
AA26

W24
W25
V22
V23
V26
U22
U25
U24
T22
U26
T23
R22
T24
R24
R26
P22
Y26
ZCLK1 3D3V_SYS
19 ZCLK1
13 ZSTB0
13 ZSTBJ0 RN25
13 ZSTB1
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZAD16
INTJB
* 13
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9

13 ZSTBJ1 2
INTJA 4
13 ZUREQ INTJC
13 ZDREQ 6 5
SZCMP_N INTJD 8 7
SZCMP_P
SZ1XAVDD 8.2K
SZ1XAVSS +/-5%
SZ4XAVDD 8P4R0603
SZ4XAVSS
SZVREF ZAD[0..16]
ZAD[0..16] 13

Analog Power supplies of Transzip function for 96X Chip. 1D8V_VCCSB

1D8V_VCCSB 1D8V_VCCSB R278 56 SZCMP_N

A SZ1XAVDD SZ4XAVDD BC383 BC384 A


BC386 BC387 BC389 BC390
* 0.1uF
* 10nF
* 0.1uF
* 10nF * 0.1uF
* 10nF

C0603 C0603
C0603 C0603 C0603 C0603
SZ1XAVSS SZ4XAVSS R281 56 SZCMP_P TECHNOLOGY COPR.
Title
PCI IDE MUTIOL
Document Number R ev

748A01 A
Date: Sunday, September 05, 2004 Sheet 25 of 48

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U14B
RN60 33 Put closed to 964 CHIP
STXEN 1
STXD0 3
* 2+/-5%
4
TXEN
TXD0
OSC25MHO

INITJ AB23 D7 OSC25MHI STXD1 5 6 TXD1 10M


7 INITJ A20MJ INIT# OSC25MHI STXD2 7 TXD2 OSC25MHI R1097 1
7 A20MJ AD26 A20M# 8 2

CPU_S
SMIJ AE25 C7 OSC25MHO
7 SMIJ INTR SMI# OSC25MHO
7 INTR AC24 INTR
NMI AD25 D10 TXCLK 1 2 X8
7 NMI NMI TXCLK TXCLK 35
IG NNEJ AD24 RN61 BC717 BC718
7 IGNNEJ IGNNE#

1
VCCP FERRJ E10 STXEN TXEN 33 15pF
7 FERRJ STPCLKJ
AE26 FERR# TXEN TXEN 35
SMDIO
* 2+/-5% MDIO
* XTAL-25MHz

D 7 STPCLKJ CPUSLPJ
AB22
AC23
STPCLK#
E11 STXD0 TXD0
TXD0 35
SMDC
1
3 4 MDC C0603 20pF D

2
CPUSLP# TXD0 STXD3 TXD3
5 6
TXD1 D12 STXD1 TXD1
TXD1 35 7 8 50V, NPO, +/-5%
R284 4.7K/NC
CPUSLPJ AF26 C12 STXD2 TXD2
19 PICCLK1 APICCK/LDTREQ# TXD2 TXD2 35

APIC
7 PICD0 AC25 APICD0/THERM2#
7 PICD1 AB24 APICD1/GPIOFF# TXD3 E13 STXD3 TXD3
TXD3 35

40 LAD[0..3]
RXCLK C13 RXCLK RXCLK 35
1D8V_SB

M
R1159 4.7K LAD0 AC4
LAD1 LAD0
AC3 LAD1 RXDV A12 RXDV RXDV 35
MIIAVDD

L P C
LAD2 AE1 BC392 BC393
LAD2

I
LAD3 A13 RXER
AF1 LAD3 RXER RXER 35 * 0.1uF
* 10nF
25V, Y5V, +80%/-20%
LFRAMEJ AD3 B12 RXD0 C0603 C0603
40 LFRAMEJ LFRAME# RXD0 RXD0 35

I
LDRQJ AE2 MIIAVSS
40 LDRQJ SIRQ LDRQ# Analog power of MII
40 SIRQ AF2 SIRQ RXD1 A11 RXD1 RXD1 35

RXD2 B11 RXD2 RXD2 35

RXD3 C11 RXD3 RXD3 35 Put closed to 96X CHIP


SDATI0 E6
17,38 SDATI0 SDATI1 AC_SDIN0 COL OSC32KHI
17 SDATI1 B4 AC_SDIN1 COL B14 COL 35

AC97
SDATO AB3 C15 CRS OSC32KHO R285 10M
17,38 SDATO AC_SDOUT CRS CRS 35
SYNC AC1
17,38 SYNC AC_SYNC SMDC MDC
MDC C9 MDC 35
AC_RESETJ
C 17
17,38
AC_RESETJ
BIT_CLK
BIT_CLK
B5
AC2
AC_RESET#
AC_BIT_CLK MDIO E9 SMDIO MDIO
MDIO 35
C
X4 XTAL-32.768kHz 20PF
B7 MIIAVDD BC395 1 2
MIIAVDD 15pF
A6 MIIAVSS 50V, NPO, +/-5% * *
BC396
22pF

4
OSC32KHI MIIAVSS C0603 50V, NPO, +/-5%
C2 OSC32KHI C0603
OSC32KHO C1 OSC32KHO
GPIO0/SPDIF Y3 GPIO0 18
BATOK D4
45 BATOK BATOK

R T C
46 PWRGD_SB D2 PWROK GPIO1/LDRQ1# AE3 GPIO1 18
BC397 RTCVDD Y4 THERMJ
GPIO2/THERM# THERMJ 40 NEED NOT to place
* 0.1uF
25V, Y5V, +80%/-20% C3 RTCVDD GPIO3/EXTSMI# AA1 GPIO3 18
close to 96X
RN8SMDA
3D3V_SYS
C0603
D3 AA2 RN26 4.7K/NC +/-5%
RTCVSS GPIO4/CLKRUN# GPIO4 18
LAD0 7 8
AA3 PREQJ5 LAD1 5 6
GPIO5/PREQ5# PREQJ5 32
LAD2 3 4
AA4 PGNTJ5 LAD3 1 * 2

G P I O
GPIO6/PGNT5# PGNTJ5 32
CK_14M_S964 AD2 A4 GPIO7
19 CK_14M_S964 OSCI GPIO7 GPIO7 18
SENTEST D1 LDRQJ R288 4.7K DUMMY
SPKR ENTEST R ING
38,45 SPKR AD1 SPK GPIO8/RING C6 RING 44
SIRQ R289 4.7K DUMMY
ACPI/OTHERS

C5 SDATI2
GPIO9/AC_SDIN2 SDATI2 17 SENTEST R290 0
C4 3D3V_SB
PWRBTNJ GPIO10/AC_SDIN3
B 45 PWRBTNJ
24,29,30,31,40 PMEJ
PMEJ
D5
A7
PWRBTN#
PME# GPIO11/OSC25M/STP_PCI# F6 GPIO11
FSB0 7,19
B
PSONJ D8
46 PSONJ PSON# GPIO12 PMEJ R292 4.7K
GPIO12/CPUSTP# E5 FSB1 6,19 GPIO pins pull down
AB2 SMB_CLK_MAIN NEED NOT to place
GPIO19 SMB_CLK_MAIN 17,19,20,21,22 close to 96X
AB1 SMB_DATA_MAIN R ING R1163 4.7K DUMMY
GPIO20 SMB_DATA_MAIN 17,19,20,21,22
S1LED_GREEN B6 3D3V_SYS
45 S1LED_GREEN AUXOK ACPILED
A3 AUXOK
13,45 AUXOK BC398 THERMJ R293 4.7K DUMMY
* 0.1uF
25V, Y5V, +80%/-20% NC30 D15

C0603 E14
NC31

NC32 C14
R294 4.7K/NC B2 GPIO13
NC33 A14
3D3V_SB R295 4.7K/NC A5 GPIO14
NC34 D13
KBDAT B8 SMB_DATA_MAIN R296 4.7K
41 KBDAT GPIO15/KBDAT
K B C

NC35 C10
KBCLK A8 SMB_CLK_MAIN R300 4.7K
41 KBCLK GPIO16/KBCLK
NC36 A10
PMDAT C8
41 PMDAT GPIO17/PMDAT
NC37 B9
41 PMCLK D6 GPIO18/PMCLK
NC38 A9

A SiS963, 964 GPIO 0~7 SiS963, 964 GPIO 9,10 A


internal pull up internal pull down
Place near to 96X
SDATI0 R305 4.7K DUMMY SiS964
BIT_CLK TECHNOLOGY COPR.
SDATI1 R306 4.7K DUMMY BC399

SDATI2 R307 4.7K DUMMY * 15pF


50V, NPO, +/-5%
Title
964-LPC/MII/GPIO
C0603
GPIO7 R308 4.7K DUMMY Document Number R ev

748A01 A
Date: Sunday, September 05, 2004 Sheet 26 of 48

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OK 1D8V_SB

U14C
UV0+ G26 USBCMPAVDD1.8
33 UV0+ UV0- UV0+ OSC12MHI
33 UV0- G25 UV0- OSC12MHI E25 CK_12M_USB 19
UV1+ H24 BC401 BC402
33 UV1+ UV1+
33
36
UV1-
UV2+
UV1-
UV2+
H23
C21
UV1-
UV2+
OSC12MHO E26 OSC12MHO
* 10nF
* 1uF

UV2- D21 A24 USBREF R309 127 C0603 C0603


36 UV2- UV3+ UV2- USBREF USBCMPAVSS1.8
36 UV3+ A22 UV3+
UV3- B22 F24 USBPVDD1.8
36 UV3- UV4+ UV3- USBPVDD18 USBPVSS1.8
33 UV4+ C19 UV4+ USBPVSS18 F23
UV4- D19
33 UV4- UV4-
D 33 UV5+
UV5+
UV5-
A20
B20
UV5+ USBCMPAVDD18 A25
B24
USBCMPAVDD1.8
USBCMPAVSS1.8 1D8V_SB
D
33 UV5- UV6+ UV5- USBCMPAVSS18
33 UV6+ C17 UV6+
UV6- D17 D23 USBCMPAVDD3.3
33
33
33
UV6-
UV7+
UV7-
UV7+
UV7-
A18
B18
UV6-
UV7+
UV7-
USB USBCMPAVDD33
USBCMPAVSS33 C23 USBCMPAVSS3.3 USBPVDD1.8

BC404 BC405
5V_SB
R1142
C26
C24
OC0#
OC1# IVDD_AUX G21 IVDD_AUX * 10nF
* 1uF

D26 H21 IVDD_AUX C0603 C0603


OC2# IVDD_AUX USBPVSS1.8
D25 OC3#
D24 3D3V_SB
OC4#
10K E24 OC5#
E23 OC6# UVDD33 G16
R0603 F22 G18
1D8V_SB FB13 +/-5% OC7# UVDD33 BC406 BC407 1D8V_SB
UVDD33 H20

1 2
E18
E20
UVDD18
UVDD18
* 10nF
* 1uF

BC408 BC409 E22 C0603 C0603 IVDD_AUX


UVDD18
FB L0805 300 Ohm * 10nF
* 0.1uF F17
F18
UVDD18
UVDD18 *
BC411
10nF BC412
C0603 C0603 F19
F20
UVDD18
UVDD18
C0603 * 1uF

F21 C0603
UVDD18
G22 UVDD18
1D8V_VCCSBFB15 H22 UVDD18 STX1P
TX1+ AD7
1 2 AA6 AC7 STX1N
BC413 BC414 AVDDSATA TX1- SRX1P
AA7 AVDDSATA RX1+ AF6
C FB L0805 300 Ohm * 10nF
* 0.1uF AA8
AA9
AVDDSATA
AVDDSATA
RX1-
TX2+
AE6
AD9
SRX1N
STX2P
3D3V_SB
C
C0603 C0603 AA10 AC9 STX2N
AB6
AVDDSATA
AVDDSATA SATA TX2-
RX2+
RX2-
AF8
AE8
SRX2P
SRX2N
USBCMPAVDD3.3

SATARXAVDD AF3 BC415 BC416


SATARXAVDD
SATARXAVSS AD4 SATARXAVSS
GPIO21/EESK A16 GPIO21 * 10nF
* 1uF

SATATXAVDD Y2 A15 GPIO22 C0603 C0603


SATATXAVSS SATATXAVDD GPIO22/EEDI GPIO23 USBCMPAVSS3.3
Y1 SATATXAVSS GPIO23/EEDO B16
B15 GPIO24
SATACMPAVDD GPIO24/EECS
AB5 SATACMPAVDD
SATACMPAVSS AD5 A26 IPB_OUT0
SATACMPAVSS IPB_OUT0/PLLENN
B25 IPB_OUT1 1D8V_VCCSB
R311 IPB_OUT1/ZCLKSEL
SATACMPAVSS 374 AC5
+/-1% REXT SATARXAVDD
R0603 AB4 SATALED
HDACT SATALED 37 BC419 BC420
19 CK_100M_SATAJ AE4 CLK25MI 3D3V_SB
* 10nF
* 1uF

AF4 B26 R312 4.7K DUMMY C0603 C0603


19 CK_100M_SATA CLK25MO TRAP0 SATARXAVSS
C25 R313 4.7K DUMMY
TRAP1
R314 R315
SiS964 22 22 CHECK
+/-5% +/-5%
3D3V_SB R0603 R0603 1D8V_VCCSB
B B
2

SATATXAVDD
4.7K 3D3V_SB
BC422 BC423
R299
U35 * 10nF
* 1uF
10V, Y5V, +80%/-20%
1

GPIO24 1 8 C0603 C0603


GPIO21 CS VCC SATATXAVSS
2 SK NC 7
GPIO22 3 6
GPIO23 DI ORG 3D3V_SB
CN1 4 DO GND 5

1
2 STX1P AT93C46 CHECK 1D8V_VCCSB
8 3 STX1N
4 IPB_OUT0 R317 4.7K DUMMY
9 5 SRX1N SATACMPAVDD
6 SRX1P
7 BC425 BC426

SATA
IPB_OUT1 R318 4.7K DUMMY
* 10nF
* 1uF
10V, Y5V, +80%/-20%
C0603 C0603
IPB_OUT0 pull up: MuTIOL clock PLL disable SATACMPAVSS
IPB_OUT1 pull up: MuTIOL V1.0, default V2.0
CN2 OSC12MHI
1
2 STX2P OSC12MHO
R319
8 3 STX2N 10M/NC
4
A 9 5 SRX2N
SRX2P
A
6
7
X3 0 1 Default internal pull-low
1 2 (30~50K Ohm)
SATA
TECHNOLOGY COPR.
XTAL-12MHz/NC SPKR( LPC addr mapping) disable enable 0 Yes
2

Title
BC427 BC428 SDATO( Trap from) ROM PCI AD 0 Yes
SIS748-USB, SATA
20pF/NC 20pF/NC
1

OC45-( SB debug mode) enable disable 1 No Document Number Rev


USBPVSS1.8
748A01 A
Date: Sunday, September 05, 2004 Sheet 27 of 48

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1D8V_VCCSB U14D

L10
P26
P21
VDDZ
VDDZ
VSS
VSS
VSS
L11
L12
OK
R21 VDDZ VSS M10
T25 VDDZ VSS M11
V25 VDDZ VSS M12
V21 N10 3D3V_SYS
VDDZ VSS
W21 VDDZ VSS N11
Y25 VDDZ VSS N12
Y21 VDDZ VSS N13
D VSS N14
N15
BC430 10uF/NC 1D8V_VCCSB 1D8V_SB
BC429
D

*
VSS C1206 1uF
M21 IVDD VSS N16
N21 P10

*
IVDD VSS BC432 10uF BC431 C0603
T21 IVDD VSS P11
U21 P12 10uF

*
IVDD VSS C1206 BC433
AB18 P13

*
IVDD VSS C1206 0.1uF/NC
AB16 IVDD VSS P14
AB14 R10 BC435 0.1uF/NC

*
IVDD VSS BC434 C0603
AB11 R11

*
IVDD VSS C0603 1uF/NC
AA5 IVDD VSS R12
Y5 R13 BC437

*
IVDD VSS 0.1uF/NC C0603
T5 IVDD VSS R14
R5 T10

*
IVDD VSS C0603 BC436
L5 IVDD VSS T13
G5 T14 0.1uF/NC
3D3V_SYS IVDD VSS BC438 0.1uF
U10

*
VSS C0603
U13

*
VSS C0603
L21 PVDD VSS U14
AA21 U15 BC439
PVDD VSS BC441 0.1uF/NC VCCP
AB19 PVDD
AB13 P15 0.1uF BC440

*
PVDD VSSZ C0603 1uF
U5 P16

*
PVDD VSSZ C0603
M5 R15

*
PVDD VSSZ BC442 C0603
H5 PVDD VSSZ R16
T15 0.1uF
VSSZ BC444 0.1uF BC443
K21 T16

*
OVDD VSSZ C0603 0.1uF/NC
J21 U16
C C

*
OVDD VSSZ C0603
AB20

*
OVDD C0603
AB17 OVDD USBVSS F25
AB15 OVDD USBVSS F26
AB12 OVDD USBVSS G23
AB10 OVDD USBVSS G24
W5 OVDD USBVSS H25
V5 H26
P5
N5
OVDD
OVDD
OVDD
Power USBVSS
USBVSS
USBVSS
J23
J24
K5 OVDD USBVSS A23
J5 OVDD USBVSS B23
VCCP C22
USBVSS
USBVSS D22
AA22 VTT USBVSS A21 Put in Bottom side of 964
AB21 B21 1D8V_VCCSB
VTT USBVSS
USBVSS E21
1D8V_SB C20
USBVSS 3D3V_SB
USBVSS D20
F9 IVDD_AUX USBVSS A19
F12 IVDD_AUX USBVSS B19
3D3V_SB F15 E19
IVDD_AUX USBVSS BC7811
USBVSS C18 2 0.10uF/B/NC
B10 D18 BC7821 2 0.10uF/B/NC
OVDD_AUX USBVSS
B13 OVDD_AUX USBVSS A17
BC447 BC448 E7 B17 VCCP
OVDD_AUX USBVSS
* 10nF
* 0.1uF E12
E15
OVDD_AUX
OVDD_AUX
USBVSS
USBVSS
E17
C16 BC7831 2 0.10uF/B/NC BC7841 2 0.10uF/B/NC
B C0603 C0603 F10
F11
OVDD_AUX USBVSS D16 B
OVDD_AUX 3D3V_SYS BC785
F13 OVDD_AUX USBVSS L13 1 2 0.10uF/B/NC
F7 OVDD_AUX USBVSS L14
G20 L15 BC7861 2 0.10uF/B/NC
OVDD_AUX USBVSS
E8 PVDD_AUX USBVSS L16
F14 PVDD_AUX USBVSS M13
USBVSS M14
M15 BC7871 2 0.10uF/B/NC BC7881 2 0.10uF/B/NC
USBVSS
USBVSS M16

W22 NC1 AVSSSATA AD10


P25 NC2 AVSSSATA AC10
P24 AF9 BC7891 2 0.10uF/B/NC
NC3 AVSSSATA
P23 NC4 AVSSSATA AE9
N26 AB9 1D8V_SB
NC5 AVSSSATA
N25 NC6 AVSSSATA AD8
N24 AC8 BC7901 2 0.10uF/B/NC
NC7 AVSSSATA
N23 NC8 AVSSSATA AB8
N22 NC9 AVSSSATA AF7
M26 AE7 BC7911 2 0.10uF/B/NC
NC10 AVSSSATA
M25 NC11 AVSSSATA AB7
M24 NC12 AVSSSATA AD6
M23 NC13 AVSSSATA AC6
M22 NC14 AVSSSATA AF5
L26 NC15 AVSSSATA AE5
L25 NC16 AVSSSATA T11
L24 T12
A L23
NC17
NC18
AVSSSATA
AVSSSATA U11 A
VSSZ
VSSZ
VSSZ
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29

L22 U12
VSS
VSS
VSS

NC19 AVSSSATA

SiS964 TECHNOLOGY COPR.


K26
K25
K24
K23
J26
J25
J22
K22
F16
E16

D9
D11
D14
R23
U23
W23

Title
964 POWER
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 28 of 48
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C/BEJ[0..3]
25,30,31,32 C/BEJ[0..3] AD[0..31] PCI Slot 1 & 2
25,30,31,32 AD[0..31]
OK
24,25,30,31,40 PCIRSTJ0 5V_SYS 5V_SYS 5V_SYS 5V_SYS

-12V_SYS 12V_SYS -12V_SYS 12V_SYS


3D3V_SYS 3D3V_SYS 3D3V_SYS
3D3V_SYS

PCI_SLOT J1
D B1 -12V TRST# A1 PCI_SLOT J2 D
B2 TCK +12V A2 B1 -12V TRST# A1
B3 GND1 TMS A3 B2 TCK +12V A2
B4 TDO TDI A4 B3 GND1 TMS A3
B5 +5V1 +5V2 A5 B4 TDO TDI A4
B6 A6 INTJA B5 A5
+5V3 INTA# INTJA 24,25,30,31 +5V1 +5V2
INTJB B7 A7 INTJC B6 A6 INTJB
24,25,30,31 INTJB INTB# INTC# INTJC 25,30,31 +5V3 INTA#
INTJD B8 A8 INTJC B7 A7 INTJD
25,30,31,32 INTJD INTD# +5V4 INTJA INTB# INTC#
B9 PRSNT1# RSV1 A9 B8 INTD# +5V4 A8
B10 A10 3D3V_SB B9 A9 3D3V_SB
RSV2 +5V5 PRSNT1# RSV1
B11 PRSNT2# RSV3 A11 B10 RSV2 +5V5 A10
B12 GND2 GND3 A12 B11 PRSNT2# RSV3 A11
B13 GND4 GND5 A13 B12 GND2 GND3 A12
B14 RSV4 SB3V A14 B13 GND4 GND5 A13
B15 A15 PCIRSTJ0 B14 A14
CK_33M_PCI1 GND6 RESET# RSV4 SB3V PCIRSTJ0
19 CK_33M_PCI1 B16 CLK +5V6 A16 B15 GND6 RESET# A15
B17 A17 PGNTJ0 CK_33M_PCI2 B16 A16
GND7 GNT# PGNTJ0 25 19 CK_33M_PCI2 CLK +5V6
PREQJ0 B18 A18 B17 A17 PGNTJ1
25 PREQJ0 REQ# GND8 GND7 GNT# PGNTJ1 25
B19 A19 PMEJ PREQJ1 B18 A18
+5V7 PCI_PME# PMEJ 24,26,30,31,40 25 PREQJ1 REQ# GND8
AD31 B20 A20 AD30 B19 A19 PMEJ
AD29 AD(31) AD(30) AD31 +5V7 PCI_PME# AD30
B21 AD(29) +3.3V1 A21 B20 AD(31) AD(30) A20
B22 A22 AD28 AD29 B21 A21
AD27 GND9 AD(28) AD26 AD(29) +3.3V1 AD28
B23 AD(27) AD(26) A23 B22 GND9 AD(28) A22
AD25 B24 A24 AD27 B23 A23 AD26
AD(25) GND10 AD24 AD25 AD(27) AD(26)
B25 +3.3V2 AD(24) A25 B24 AD(25) GND10 A24
C/BEJ3 B26 A26 R320 100 AD18 B25 A25 AD24
AD23 C/BE#(3) IDSEL C/BEJ3 +3.3V2 AD(24) R321 100 AD19
B27 AD(23) +3.3V3 A27 B26 C/BE#(3) IDSEL A26
B28 A28 AD22 AD23 B27 A27
AD21 GND11 AD(22) AD20 AD(23) +3.3V3 AD22
B29 AD(21) AD(20) A29 B28 GND11 AD(22) A28
AD19 AD21 AD20
C B30
B31
AD(19)
+3.3V4
GND12
AD(18)
A30
A31 AD18 AD19
B29
B30
AD(21)
AD(19)
AD(20)
GND12
A29
A30 C
AD17 B32 A32 AD16 B31 A31 AD18
C/BEJ2 AD(17) AD(16) AD17 +3.3V4 AD(18) AD16
B33 C/BE#(2) +3.3V5 A33 B32 AD(17) AD(16) A32
B34 A34 FRAMEJ C/BEJ2 B33 A33
GND13 FRAME# FRAMEJ 25,30,31,32 C/BE#(2) +3.3V5
IRDYJ B35 A35 B34 A34 FRAMEJ
25,30,31,32 IRDYJ IRDY# GND14 TRDYJ IRDYJ GND13 FRAME#
B36 +3.3V6 TRDY# A36 TRDYJ 25,30,31,32 B35 IRDY# GND14 A35
DEVSELJ B37 A37 B36 A36 TRDYJ
25,30,31,32 DEVSELJ DEVSEL# GND15 STOPJ DEVSELJ +3.3V6 TRDY#
B38 GND16 STOP# A38 STOPJ 25,30,31,32 B37 DEVSEL# GND15 A37
PLOCKJ B39 A39 B38 A38 STOPJ
25,30,31 PLOCKJ PERRJ LOCK# +3.3V7 SDONE1 PLOCKJ GND16 STOP#
30,31,32 PERRJ B40 PERR# SDONE A40 B39 LOCK# +3.3V7 A39
B41 A41 SBOJ1 PERRJ B40 A40 SDONE2
SERRJ +3.3V8 SBO# PERR# SDONE SBOJ2
25,30,31,32 SERRJ B42 SERR# GND17 A42 B41 +3.3V8 SBO# A41
B43 A43 PAR SERRJ B42 A42
+3.3V9 PAR PAR 25,30,31,32 SERR# GND17
C/BEJ1 B44 A44 AD15 B43 A43 PAR
AD14 C/BE#(1) AD(15) C/BEJ1 +3.3V9 PAR AD15
B45 AD(14) +3.3V10 A45 B44 C/BE#(1) AD(15) A44
B46 A46 AD13 AD14 B45 A45
AD12 GND18 AD(13) AD11 AD(14) +3.3V10 AD13
B47 AD(12) AD(11) A47 B46 GND18 AD(13) A46
AD10 B48 A48 AD12 B47 A47 AD11
AD(10) GND19 AD9 AD10 AD(12) AD(11)
B49 GND20 AD(9) A49 B48 AD(10) GND19 A48
A50 B50 B49 A49 AD9
A50 B50 GND20 AD(9)
A51 A51 B51 B51 A50 A50 B50 B50
AD8 B52 A52 C/BEJ0 A51 B51
AD7 AD(8) C/BE#(0) AD8 A51 B51 C/BEJ0
B53 AD(7) +3.3V11 A53 B52 AD(8) C/BE#(0) A52
B54 A54 AD6 AD7 B53 A53
AD5 +3.3V12 AD(6) AD4 AD(7) +3.3V11 AD6
B55 AD(5) AD(4) A55 B54 +3.3V12 AD(6) A54
AD3 B56 A56 AD5 B55 A55 AD4
AD(3) GND21 AD2 AD3 AD(5) AD(4)
B57 GND22 AD(2) A57 B56 AD(3) GND21 A56
AD1 B58 A58 AD0 B57 A57 AD2
AD(1) AD(0) AD1 GND22 AD(2) AD0
B59 +5V8 +5V9 A59 B58 AD(1) AD(0) A58
PACK64J1 PREQ64J1
B B60
B61
ACK64#
+5V10
REQ64#
+5V11
A60
A61 PACK64J2
B59
B60
+5V8
ACK64#
+5V9
REQ64#
A59
A60 PREQ64J2 B
B62 A62 B61 A61
X1
X2

+5V12 +5V13 +5V10 +5V11


B62 A62

X1
X2
+5V12 +5V13
X1
X2

X1
X2
5V_SYS 5V_SYS 5V_SYS
RN27 RN28

A SERRJ
PERRJ
2
4
* 13 DEVSELJ
TRDYJ
2
4
* 13 PREQJ0 R322 2.7KDUMMY
A
PLOCKJ 6 5 IRDYJ 6 5 PREQJ1 R323 2.7KDUMMY
STOPJ 8 7 FRAMEJ 8 7

4.7K 2.7K
TECHNOLOGY COPR.
RN30DUMMY RN67
SDONE2
SBOJ2
2
4
* 1
3
PREQ64J2
PACK64J2
2
4
* 13 Title
PCI 1, 2
SDONE1 6 5 PACK64J1 6 5
SBOJ1 8 7 PREQ64J1 8 7 Document Number Rev

4.7K 2.7K 748A01 A


Date: Sunday, September 05, 2004 Sheet 29 of 48
8 7 6 5 4 3 2 1

OK
C /BEJ[0..3]
25,29,31,32 C/BEJ[0..3] AD[0..31] PCI Slot 1 & 2
25,29,31,32 AD[0..31]

24,25,29,31,40 PCIRSTJ0 5V_SYS 5V_SYS 5V_SYS 5V_SYS

D -12V_SYS
3D3V_SYS
12V_SYS
3D3V_SYS
-12V_SYS 12V_SYS
3D3V_SYS
D
3D3V_SYS

PCI_SLOT J3
B1 A1 PCI_SLOT J4
-12V TRST#
B2 TCK +12V A2 B1 -12V TRST# A1
B3 GND1 TMS A3 B2 TCK +12V A2
B4 TDO TDI A4 B3 GND1 TMS A3
B5 +5V1 +5V2 A5 B4 TDO TDI A4
B6 A6 IN TJC B5 A5
+5V3 INTA# INTJC 25,29,31 +5V1 +5V2
IN TJD B7 A7 INTJA B6 A6 IN TJD
25,29,31,32 INTJD INTB# INTC# INTJA 24,25,29,31 +5V3 INTA#
INTJB B8 A8 INTJA B7 A7 INTJB
24,25,29,31 INTJB INTD# +5V4 IN TJC INTB# INTC#
B9 PRSNT1# RSV1 A9 B8 INTD# +5V4 A8
B10 A10 3D3V_SB B9 A9 3D3V_SB
RSV2 +5V5 PRSNT1# RSV1
B11 PRSNT2# RSV3 A11 B10 RSV2 +5V5 A10
B12 GND2 GND3 A12 B11 PRSNT2# RSV3 A11
B13 GND4 GND5 A13 B12 GND2 GND3 A12
B14 RSV4 SB3V A14 B13 GND4 GND5 A13
B15 A15 PCIRSTJ0 B14 A14
CK_33M_PCI3 GND6 RESET# RSV4 SB3V PCIRSTJ0
19 CK_33M_PCI3 B16 CLK +5V6 A16 B15 GND6 RESET# A15
B17 A17 PGNTJ2 CK_33M_PCI4 B16 A16
GND7 GNT# PGNTJ2 25 19 CK_33M_PCI4 CLK +5V6
PREQJ2 B18 A18 B17 A17 PGNTJ3
25 PREQJ2 REQ# GND8 GND7 GNT# PGNTJ3 25
B19 A19 PMEJ PREQJ3 B18 A18
+5V7 PCI_PME# PMEJ 24,26,29,31,40 25 PREQJ3 REQ# GND8
AD31 B20 A20 AD30 B19 A19 PMEJ
AD29 AD(31) AD(30) AD31 +5V7 PCI_PME# AD30
B21 AD(29) +3.3V1 A21 B20 AD(31) AD(30) A20
B22 A22 AD28 AD29 B21 A21
AD27 GND9 AD(28) AD26 AD(29) +3.3V1 AD28
B23 AD(27) AD(26) A23 B22 GND9 AD(28) A22
AD25 B24 A24 AD27 B23 A23 AD26
AD(25) GND10 AD24 AD25 AD(27) AD(26)
B25 +3.3V2 AD(24) A25 B24 AD(25) GND10 A24
C/BEJ3 B26 A26 R328 100 AD20 B25 A25 AD24
AD23 C/BE#(3) IDSEL C/BEJ3 +3.3V2 AD(24) R329 100 AD21
B27 AD(23) +3.3V3 A27 B26 C/BE#(3) IDSEL A26
B28 A28 AD22 AD23 B27 A27
AD21 GND11 AD(22) AD20 AD(23) +3.3V3 AD22
B29 AD(21) AD(20) A29 B28 GND11 AD(22) A28
AD19 B30 A30 AD21 B29 A29 AD20
AD(19) GND12 AD18 AD19 AD(21) AD(20)
B31 +3.3V4 AD(18) A31 B30 AD(19) GND12 A30
AD17 B32 A32 AD16 B31 A31 AD18
C/BEJ2 AD(17) AD(16) AD17 +3.3V4 AD(18) AD16
B33 A33 B32 A32
C IRDYJ
B34
B35
C/BE#(2)
GND13
+3.3V5
FRAME# A34
A35
FRAMEJ
FRAMEJ 25,29,31,32
C/BEJ2 B33
B34
AD(17)
C/BE#(2)
AD(16)
+3.3V5 A33
A34 FRAMEJ
C
25,29,31,32 IRDYJ IRDY# GND14 TR DYJ IRDYJ GND13 FRAME#
B36 +3.3V6 TRDY# A36 TRDYJ 25,29,31,32 B35 IRDY# GND14 A35
DEVSELJ B37 A37 B36 A36 TR DYJ
25,29,31,32 DEVSELJ DEVSEL# GND15 STOPJ DEVSELJ +3.3V6 TRDY#
B38 GND16 STOP# A38 STOPJ 25,29,31,32 B37 DEVSEL# GND15 A37
PLOCKJ B39 A39 B38 A38 STOPJ
25,29,31 PLOCKJ PER RJ LOCK# +3.3V7 SDONE3 PLOCKJ GND16 STOP#
29,31,32 PERRJ B40 PERR# SDONE A40 B39 LOCK# +3.3V7 A39
B41 A41 SBOJ3 PER RJ B40 A40 SDONE4
SER RJ +3.3V8 SBO# PERR# SDONE SBOJ4
25,29,31,32 SERRJ B42 SERR# GND17 A42 B41 +3.3V8 SBO# A41
B43 A43 PAR SER RJ B42 A42
+3.3V9 PAR PAR 25,29,31,32 SERR# GND17
C/BEJ1 B44 A44 AD15 B43 A43 PAR
AD14 C/BE#(1) AD(15) C/BEJ1 +3.3V9 PAR AD15
B45 AD(14) +3.3V10 A45 B44 C/BE#(1) AD(15) A44
B46 A46 AD13 AD14 B45 A45
AD12 GND18 AD(13) AD11 AD(14) +3.3V10 AD13
B47 AD(12) AD(11) A47 B46 GND18 AD(13) A46
AD10 B48 A48 AD12 B47 A47 AD11
AD(10) GND19 A D9 AD10 AD(12) AD(11)
B49 GND20 AD(9) A49 B48 AD(10) GND19 A48
A50 B50 B49 A49 A D9
A50 B50 GND20 AD(9)
A51 A51 B51 B51 A50 A50 B50 B50
A D8 B52 A52 C/BEJ0 A51 B51
A D7 AD(8) C/BE#(0) A D8 A51 B51 C/BEJ0
B53 AD(7) +3.3V11 A53 B52 AD(8) C/BE#(0) A52
B54 A54 A D6 A D7 B53 A53
A D5 +3.3V12 AD(6) A D4 AD(7) +3.3V11 A D6
B55 AD(5) AD(4) A55 B54 +3.3V12 AD(6) A54
A D3 B56 A56 A D5 B55 A55 A D4
AD(3) GND21 A D2 A D3 AD(5) AD(4)
B57 GND22 AD(2) A57 B56 AD(3) GND21 A56
A D1 B58 A58 A D0 B57 A57 A D2
AD(1) AD(0) A D1 GND22 AD(2) A D0
B59 +5V8 +5V9 A59 B58 AD(1) AD(0) A58
PACK64J3 B60 A60 PREQ64J3 B59 A59
ACK64# REQ64# PACK64J4 +5V8 +5V9 PREQ64J4
B61 +5V10 +5V11 A61 B60 ACK64# REQ64# A60
B62 A62 B61 A61
X1
X2

+5V12 +5V13 +5V10 +5V11


B62 A62

X1
X2
+5V12 +5V13
X1
X2

X1
X2
B B

5V_SYS

5V_SYS PREQJ2 R330 2.7KDUMMY


RN31
SDONE4
SBOJ4
2
4
* 13 PREQJ3 R331 2.7KDUMMY

SDONE3 6 5
SBOJ3 8 7

2.7K

RN68
PREQ64J4
PACK64J4
2
4
* 13
PACK64J3 6 5
PREQ64J3 8 7
A 2.7K
A

TECHNOLOGY COPR.
Title
Index

Confidential Document.Do Not Reproduce Without Foxconn Authorization. Document Number


748A01
Rev
A
Date: Sunday, September 05, 2004 Sheet 30 of 48

8 7 6 5 4 3 2 1
5 4 3 2 1

C/BEJ[0..3]
25,29,30,32 C/BEJ[0..3] AD[0..31]
25,29,30,32 AD[0..31]

5V_SYS 5V_SYS

-12V_SYS 12V_SYS
OK
D 3D3V_SYS 3D3V_SYS D

PCI_SLOT J5
B1 -12V TRST# A1
B2 TCK +12V A2
B3 GND1 TMS A3
B4 TDO TDI A4
B5 +5V1 +5V2 A5
B6 A6 INTJA
+5V3 INTA# INTJA 24,25,29,30
INTJB B7 A7 INTJC
24,25,29,30 INTJB INTB# INTC# INTJC 25,29,30
INTJD B8 A8
25,29,30,32 INTJD INTD# +5V4
B9 PRSNT1# RSV1 A9
B10 A10 3D3V_SB
RSV2 +5V5
B11 PRSNT2# RSV3 A11
B12 GND2 GND3 A12
B13 GND4 GND5 A13
B14 RSV4 SB3V A14
B15 A15 PCIRSTJ
GND6 RESET# PCIRSTJ0 24,25,29,30,40
CK_33M_PCI5 B16 A16
19 CK_33M_PCI5 CLK +5V6 PGNTJ4
B17 GND7 GNT# A17 PGNTJ4 25
PREQJ4 B18 A18
25 PREQJ4 REQ# GND8 PMEJ
B19 +5V7 PCI_PME# A19 PMEJ 24,26,29,30,40
AD31 B20 A20 AD30
AD29 AD(31) AD(30)
B21 AD(29) +3.3V1 A21
B22 A22 AD28
AD27 GND9 AD(28) AD26
B23 AD(27) AD(26) A23
C AD25 B24 A24 C
AD(25) GND10 AD24
B25 +3.3V2 AD(24) A25
C/BEJ3 B26 A26 R336 100 AD22
AD23 C/BE#(3) IDSEL
B27 AD(23) +3.3V3 A27
B28 A28 AD22
AD21 GND11 AD(22) AD20
B29 AD(21) AD(20) A29
AD19 B30 A30
AD(19) GND12 AD18
B31 +3.3V4 AD(18) A31
AD17 B32 A32 AD16
C/BEJ2 AD(17) AD(16)
B33 C/BE#(2) +3.3V5 A33
B34 A34 FRAMEJ 5V_SYS 5V_SYS
GND13 FRAME# FRAMEJ 25,29,30,32
I RDYJ B35 A35
25,29,30,32 IRDYJ IRDY# GND14 T RDYJ PREQJ4 R337 2.7K DUMMY
B36 +3.3V6 TRDY# A36 TRDYJ 25,29,30,32
DEVSELJ B37 A37
25,29,30,32 DEVSELJ DEVSEL# GND15 STOPJ
B38 GND16 STOP# A38 STOPJ 25,29,30,32
PLOCKJ B39 A39
25,29,30 PLOCKJ PERRJ LOCK# +3.3V7 SDONE5 RN66
29,30,32 PERRJ B40 PERR# SDONE A40

SERRJ
B41
B42
+3.3V8 SBO# A41
A42
SBOJ5 PREQ64J5
PACK64J5
*
1
3
2
4
25,29,30,32 SERRJ SERR# GND17 PAR SBOJ5
B43 +3.3V9 PAR A43 PAR 25,29,30,32 5 6
C/BEJ1 B44 A44 AD15 SDONE5 7 8
AD14 C/BE#(1) AD(15)
B45 AD(14) +3.3V10 A45
B46 A46 AD13 2.7K
AD12 GND18 AD(13) AD11 +/-5%
B47 AD(12) AD(11) A47
AD10 B48 A48 8P4R0603
AD(10) GND19 AD9
B49 GND20 AD(9) A49
A50 A50 B50 B50
B A51 A51 B51 B51 B
AD8 B52 A52 C/BEJ0
AD7 AD(8) C/BE#(0)
B53 AD(7) +3.3V11 A53
B54 A54 AD6
AD5 +3.3V12 AD(6) AD4
B55 AD(5) AD(4) A55
AD3 B56 A56
AD(3) GND21 AD2
B57 GND22 AD(2) A57
AD1 B58 A58 AD0
AD(1) AD(0)
B59 +5V8 +5V9 A59
PACK64J5 B60 A60 PREQ64J5
ACK64# REQ64#
B61 +5V10 +5V11 A61
B62 A62
X1
X2

+5V12 +5V13
X1
X2

A A

TECHNOLOGY COPR.
Title
Index
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 31 of 48
5 4 3 2 1
5 4 3 2 1

3D3V_1394 FB44 1 2 FB L0805 30 Ohm


3D3V_SYS

BC719 BC720 BC721

1
0.10uF 0.10uF 0.10uF
FB45 C0603 C0603 C0603
FB L0805 30 Ohm 5V_SYS

2
2
R1178
0/nc
BC724 BC725 BC726 BC727 BC728 BC729 BC730 BC731 BC732 R1179 +/-5%

99
17
27
32
43
57
67
72

75
88
91
1

1
0.10uF 0.10uF 0.10uF 0.10uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0 R0603 U27
C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603

VDDA
VDDA
VDDA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
BC734

2
D D
70 93 22pF

*
PCI_VIOS XI C0603

1
50V, NPO, +/-5%
A D0 69 X9
A D1 PCI_AD0
68 PCI_AD1 XTAL-24.576MHz
A D2 65 R1098 BC735

2
A D3 PCI_AD2 22pF
64 94

*
A D4 PCI_AD3 XO C0603
63 PCI_AD4
A D5 61 95 330 BC736 1 2 0.10uF 50V, NPO, +/-5%
A D6 PCI_AD5 RESET# 25V,Y5V,+80%/-20%
60 PCI_AD6
3D3V_SYS 3D3V_1394 A D7 59
A D8 PCI_AD7 R1099
BC737 56 PCI_AD8
A D9 55 90
AD10 PCI_AD9 R1
1 2 54 PCI_AD10 510K
AD11 53 R1100
AD12 PCI_AD11 2.49K R0603
0.10uF 51 PCI_AD12
AD13 50 +/-1% +/-5%
C0603 AD14 PCI_AD13 R0603
49 PCI_AD14
AD15 48 89
AD16 PCI_AD15 R0
35 PCI_AD16
AD17 34 86 TPBIAS0
AD18 PCI_AD17 TPBIAS0 TPA0
31 PCI_AD18 TPA0+ 85 TPA0 39
AD19 30 84 TPA0J
AD[0..31] PCI_AD19 TPA0- TPA0J 39
AD20 29 83 TPB0
25,29,30,31 AD[0..31] PCI_AD20 TPB0+ TPB0 39
AD21 28 82 TPB0J
PCI_AD21 TPB0- TPB0J 39
AD22 26 81 TPBIAS1
AD23 PCI_AD22 TPBIAS1 TPA1
AD24
25
21
PCI_AD23 FW322-100 TPA1+ 80
79 TPA1J
TPA1 39
PCI_AD24 TPA1- TPA1J 39
AD25 20 78 TPB1
PCI_AD25 TPB1+ TPB1 39
AD26 19 77 TPB1J
PCI_AD26 TPB1- TPB1J 39
AD27 18
AD28 PCI_AD27
16 PCI_AD28
AD29 15
AD30 PCI_AD29
14 PCI_AD30
AD31 13 PCI_AD31 402K
C/BE-0 58 73 R1153 BPWR
25,29,30,31 C/BEJ0 PCI_CBE0# CPS
C C/BE-1 47 C
25,29,30,31 C/BEJ1 PCI_CBE1#
C/BE-2 36
25,29,30,31 C/BEJ2 PCI_CBE2#
C/BE-3 23
25,29,30,31 C/BEJ3 PCI_CBE3#
PAR 46
25,29,30,31 PAR PCI_PAR
FRAMEJ 37 71 R1103 10K
25,29,30,31 FRAMEJ PCI_FRAME# PC2
IRDYJ 39
25,29,30,31 IRDYJ PCI_IRDY#
TR DYJ 40
25,29,30,31 TRDYJ PCI_TRDY#
DEVSELJ 41
25,29,30,31 DEVSELJ PCI_DEVSEL#
STOPJ 42 1
25,29,30,31 STOPJ PCI_STOP# CARDBUSN
AD24 R1106 100 IDSEL 24 PCI_IDSEL
REQ5_1J 9
26 PREQJ5 PCI_REQ#
GNT5_1J 8
26 PGNTJ5 PCI_GNT#
PER RJ 44 5 R1109 10K
29,30,31 PERRJ PCI_PERR# TEST0
SER RJ 45 2 R1110 10K
25,29,30,31 SERRJ PCI_SERR# TEST1
96 R1102 10K
PTEST R1112 10K
19 CK_33M_1394 11 PCI_PCLK SE 98
97 R1101 10K
SM

25 PCIRSTJ1 PCIRSTJ 7 3D3V_1394


INT-D PCI_PRST#
25,29,30,31 INTJD 6 PCI_INTA#

1
10 4 BC738
PCI_PME# ROM_AD 0.10uF
3 R1113 R1114 R1111

2
ROM_CLK
10K 10K

VSSA
VSSA
VSSA
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
330 U33
8 VCC A0 1
7 2

100
12
22
33
38
52
62
66

74
87
92
76
S CL WP/NC A1
6 SCL A2/NC 3
SDA 5 4
SDA VSS/GND
AT24C02N-2.7V

B B

R1117 56.2
TPB0 R1118 56.2
TPB1

R1120 56.2 R1121 56.2


TPBIAS0 TPA0 R1122 56.2 TPB0J R1123 56.2
TPBIAS1 TPA1 TPB1J
R1126
R1125 56.2
TPA0J R1128 56.2 R1127
TPA1J
4.99K +/-1% 4.99K +/-1%

BC740 220pF C0603


BC741 0.33uF BC742 220pF C0603
* 50V, NPO, +/-5%
*

A BC743 0.33uF C0805 50V, NPO, +/-5% A


*

C0805 16V, X7R, +/-10%


16V, X7R, +/-10%

TECHNOLOGY COPR.
Title
IEE1394
Document Number Rev

748A01 A
Date: Sunday, September 05, 2004 Sheet 32 of 48
5 4 3 2 1
5 4 3 2 1

Rear Dual USB Connector


5V_SYS

D D

EC45
* 1000uF/NC

12
9
6.3V, +/-20%
CE35D80H200 USB
USBX2
1

BOTTOM
2

TOP
UV0- 6
27 UV0-
UV0+ 7
27 UV0+
8
UV1-
27 UV1-
C UV1+ C

10

11
27 UV1+

USB Header2 5V_SYS

USB Header1 5V_SYS

*
EC47
1000uF/NC
6.3V, +/-20%
CE35D80H200

B SVCC2 B

CN4
SVCC1 1 2
27 UV4- 3 4 UV5- 27
27 UV4+ 5 6 UV5+ 27
CN5 7 8
X 10
1 2 BC511

1
3 4 0.10uF
27 UV6- UV7- 27 HEADER_2X5_9
5 6 C0603
27 UV6+ UV7+ 27
7 8

2
BC512 X 10
1

0.10uF
C0603
HEADER_2X5_9
2

A A

TECHNOLOGY COPR.
Title
USB Header & USB Port
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 33 of 48
5 4 3 2 1
8 7 6 5 4 3 2 1

VIN
5V_SYS VCCP

D BC841 BC857 BC858


BC839
0.1uF
BC840
0.1uF
D
BC842 BC843 BC844 BC845 BC847 BC848 BC849
* 0.1uF
*0.1uF
*0.1uF * *
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
* * * * * * *

5V_SB
3D3V_SYS -12V_SYS

BC850
BC851 BC852 0.1uF
* 0.1uF
* 0.1uF *

C C

B B

A A

TECHNOLOGY COPR.
Title
EMPTY
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 34 of 48
8 7 6 5 4 3 2 1
5 4 3 2 1

FB L0805 120 Ohm

36 PWFBOUT PWFBOUT 1 2 PWFBIN

3D3V_SB
3D3V_SB * BC824
0.1uF L48 * BC825
0.1uF
Place L2, C17, C18, C19 as close to each power pin C0603 C0603
D as possible. D

R1093
5.1K Place C14, C15, L1 close to PWFBOUT and place C16
R0603 U31
close to PWFBIN.
+/-5%
MDC 25 32 PWFBOUT
26 MDC MDC PWFBOUT
MDIO 26 36 AVDD33
26 MDIO MDIO AVDD33
TXD0 6
26 TXD0 TXD0
TXD1 5 BC826
26 TXD1 TXD1
26
26
TXD2
TXD3
TXD2
TXD3
4
3
TXD2
TXD3
AGND
AGND
29
35
* 0.1uF
25V, Y5V, +80%/-20%
TXEN 2 C0603
26 TXEN TXEN
TXCLK 7
26 TXCLK TXC
RXDV 22
26 RXDV RXDV
RXD0 21 27
26 RXD0 RXD0 NC1
RXD1 20
26 RXD1 RXD1
RXD2 19
26
26
RXD2
RXD3
RXD3
RXCLK
18
RXD2
RXD3
RTL8201BL LRDP
26 RXCLK 16 RXC TPRX+ 31 LRDP 36
COL 1 30 L RDN LRDN 36
26 COL COL TPRX-
CRS 23
26 CRS CRS
RXER 24
26 RXER RXER/FXEN
46 33 LTDN LTDN 36
X1 TPTX- LTDP
X7 47 X2 TPTX+ 34 LTDP 36
C C
1 2 LED0/PHYAD0 9 R1094
BC827 BC828 LED1/PHYAD1 LED0/PHYAD0 6.2K 8201 5.9K
10 LED1/PHYAD1 RTSET 28
22pF
C0603 * XTAL-25MHz * 22pF
C0603
LED2/PHYAD2
LED3/PHYAD3
12
13
LED2/PHYAD2
LED3/PHYAD3
ISOLATE
RPTR
43
40
+/-5%
R0603

3D3V_SB
LED4/PHYAD4 15 LED4/PHYAD4 SPEED 39
38
*
1
3
2
4
PWFBIN DUPLEX
8 PWFBIN ANE 37 5 6
14 DVDD33 LDPS 41 7 8 3D3V_SB
48 DVDD33 MII/SNIB/RTT3 44
42 RN57
RESETB +/-5%
11 DGND0
17 8P4R0603
BC829 BC830 DGND1 5.1K
45 DGND2
0.1uF
C0603* * 0.1uF
C0603 IP101

* 13
5
7
+/-5%
8P4R0603
3D3V_SB R1095 5.1K/NC
U17/pin14 U17/pin48 R0603 +/-5% 5.1K
RN58
* BC831
0.1uF

2
4
6
8
C0603 3D3V_SB

Hardwire Configuration network:


B 1. This configuration shows B
Enable: Auto negotiation, Full duplex, 100Mbps,
RN59 Link Down Power Saving, MII interface
36 LED3/PHYAD3
LED3/PHYAD3
LED4/PHYAD4
*
1
3
2
4
36 LED0/PHYAD0
LED0/PHYAD0 R1096 3D3V_SB Disable: Isolate, Repeater mode
2. These senven configuration pins could be connected to VDD
LED2/PHYAD2 5 6 5.1K/NC R0603 +/-5%
36 LED2/PHYAD2 LED1/PHYAD1 or GND directly.
7 8

5.1K This schematic sets PHY address to 00001b.


+/-5% You could set PHY address from 00001b to 11111b.
8P4R0603 But the LED polarity must matchs the respective
PHYAD setting. Refer to datasheet's detailed
description.

LED0 LED1 LED2 LED3 LED4


Link Dupx 10Act 100Act COL
A A

TECHNOLOGY COPR.
Title
RTL8110S/RTL8100C
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 35 of 48
5 4 3 2 1
5 4 3 2 1

5V_SYS

D D

3D3V_SB

R1091
35 PWFBOUT 510/NC
BC713 +/-5%
* 10nF R0603

C0603
* BC714
0.1uF USB_LAN1
D19

C0603 9 1
RJ45-1 LED2/PHYAD2 35
GigaLAN R1092
10 17 510/NC 3
RJ45-2 DYA +/-5%
C L47 YEL GRN C
11 18 R0603 2
RJ45-3 DGA LED3/PHYAD3 35
35 LTDN LTDN 3 14
LTDP TD- TX-
35 LTDP 1 TD+ TX+ 16 14 RJ45-6
35 LRDP LRDP 6 11 20
RD+ RX+ GC LED0/PHYAD0 35 BAT54C/NC
35 LRDN L RDN 8 9 12
RD- RX- RJ45-4 GRN
GA 19
7 CTD CTX 10 13 RJ45-5
2 TDT TCMT 15 CGND5 25
15 RJ45-7 CGND6 26
4 NC_4 NC_13 13 CGND7 27
5 NC_5 NC_12 12 16 RJ45-8 CGND8 28

SVCC3 5
XFMR 350uH VCC2
2
4
6
8
6 D2- Up USB
RN55
R1143 75 7 D2+ CGND3 23
* 13
5
7

+/-5% 3D3V_SB 8 24
8P4R0603 GND2 CGND4
8P4R0603 +/-5%
*

SVCC4 1
1
3
5
7

51 VCC1
RN56 0/NC 2 D1- Down USB
R0603 3 21
2
4
6
8

+/-5% D1+ CGND1


4 GND1 CGND2 22

BC715
0.1uF
* * BC716
BC832
1.5nF
USBX2_RJ45 10/100 Mbit LAN

B C0603 0.1uF B
C0603

Close to USB connector

27 UV2-

27 UV2+

27 UV3-

27 UV3+

A A

TECHNOLOGY COPR.
Title
LAN & USB PORT
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 36 of 48
5 4 3 2 1
8 7 6 5 4 3 2 1
IDERSTJ

IDEDA7 R398 5.6K

IDEDA[0..15]
25 IDEDA[0..15]
CN6
1 2
IDEDA7 3 4 IDEDA8
D IDEDA6
IDEDA5
5
7
6
8
IDEDA9
IDEDA10
D
IDEDA4 9 10 IDEDA11
IDEDA3 11 12 IDEDA12
IDEDA2 13 14 IDEDA13
IDEDA1 15 16 IDEDA14
IDEDA0 17 18 IDEDA15
19 X
IDEREQA 21 22
25 IDEREQA IDEIOWJA
25 IDEIOWJA 23 24
IDEIORJA 25 26
25 IDEIORJA ICHRD YA
25 ICHRDYA 27 28
IDACKJA 29 30
25 IDACKJA IDEIRQA
25 IDEIRQA 31 32
IDESAA1 33 34 CBLIDA
CBLIDA 25
IDESAA0 35 36 IDESAA2
IDECSJA0 37 38 IDECSJA1
39 40

CONN40 (IDE2)

25 IDESAA[0..2]

D6
25 IDECSJA[0..1]
HDDLED 1 2
C 45 HDDLED C
1N4148W
25 IDESAB[0..2]
D7
1 2 SATALED
SATALED 27 25 IDECSJB[0..1]
3D3V_SYS 5V_SYS
1N4148W
IDEDB[0..15]
25 IDEDB[0..15]
R402 R403
4.7K 4.7K
+/-5% +/-5%
R0603 R0603
IDERSTJ
C

IDEDB7 R404 5.6K


B Q33
MMBT3904
C

R405 4.7KB Q34


13,25 PCIRSTJ2 MMBT3904 CN7
IDEDB8? Page35 1 2
E

IDEDB7 3 4 IDEDB8
IDEDB6 5 6 IDEDB9
IDEDB5 7 8 IDEDB10
IDEDB4 9 10 IDEDB11
B IDEDB3
IDEDB2
11
13
12
14
IDEDB12
IDEDB13
B
IDEDB1 15 16 IDEDB14
IDEDB0 17 18 IDEDB15
19 X
IDEREQB IDEREQB 21 22
25 IDEREQB IDEIOWJB IDEIOWJB
25 IDEIOWJB 23 24
IDEIORJB IDEIORJB 25 26
25 IDEIORJB ICHRD YB MICHRDYB
25 ICHRDYB 27 28
IDACKJB IDACKJB 29 30
25 IDACKJB IDEIRQB IDEIRQB
25 IDEIRQB 31 32
IDESAB1 33 34 CBLIDB
CBLIDB 25
IDESAB0 35 36 IDESAB2
IDECSJB0 37 38 IDECSJB1
39 40

CONN40 (IDE1)

D8
HDDLED 1 2
45 HDDLED
1N4148W

A A

TECHNOLOGY COPR.
Title
IDE
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 37 of 48
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LINE_IN_L
LINE IN
* BC792 R1066
FB43 5V_SYS AUDIO1C 100pF/NC 22K
C0603 R0603
VCC5A 1 2 32
3D3V_SYS 12V_SYS 50V, NPO, +/-5% +/-5%
33
+/-25% FB L0805 60 Ohm U29 LM78L05/NC 40 34 R1067 10K JD2
1 R0603 +/-5%
BC794 BC795 OUT IN 3 35

* 0.1uF
* 0.1uF
* BC796
* BC797 EC81 JACK_AUDX3 Vertical * BC793

GND
1
C0603 C0603 0.1uF
C0603
0.1uF
C0603
22uF/nc
16V, +/-20% * BC798
0.1uF/NC * BC799
1uF/NC
3.3uF

D CE20D50H110 C0603 C0603


C0805
D

2
10V, Y5V, +80%/-20%
L INE_IN_R

25
38
1
9
U30 R1068
22K

DVdd1
DVdd2
AVdd1
AVdd2
* BC800 R0603
100pF/NC +/-5%
3 XTL_OUT C0603
XTL-IN 2
19 CK_14M_AUDIO XTL_IN 50V, NPO, +/-5%
CE25D60H110
11 35 EC71 100uF 16V, +/-20% LINE_OUT_L
17 CODEC_RSTJ RESET# FRONT_OUT_L

* **
BIT_CLK 6 36 EC72 100uF 16V, +/-20% LINE_OUT_R
17,26 BIT_CLK S Y NC BIT_CLK FRONT_OUT_R CE25D60H110
17,26 SYNC 10 SYNC MONO_OUT 37
SDATI0 8 33
17,26 SDATI0 SDATO SDATA_IN NC_33 BC801 1uF C0603 F_MIC
17,26 SDATO 5 SDATA_OUT Front-MIC1 34
SURR-OUT-L 39
*

NC_40 40
22pF/NC PC_BEEP VREFOUT
BC802
12
13
PC_BEEP ALC655 SURR-OUT-R 41
43
PHONE CEN-OUT
14 AUX_L LFE-OUT 44
15 45 JD0
JD2 AUX_R JD0(GPIO0) R1069 R1070
16 JD2 XTLSEL 46
JD1 17 4.7K 4.7K
CD_L BC803 1uF C0603 JD1 VREFOUT
18 28 R0603 R0603
*******

CD_GNDBC804 1uF C0603 CD_L VREFOUT


19 CD_GND VREF 27 +/-5% +/-5%
CD _R BC805 1uF C0603 20 29 10K R1071 JD0
MIC1 BC806 1uF C0805 CD_R AFILT1 +/-5% R0603 MIC1
21 MIC1 AFILT2 30
MIC2 BC807 1uF C0805 22 31
LINE_IN_L BC808 1uF C0603 MIC2 VRDA BC814 R1072
L INE_IN_R BC809
23 LINE_IN_L Front-MIC2 32 MIC IN *
1uF C0603 24
* *
BC811 BC812
* BC813
* 4.7uF
* BC815 5.6K BC810

NC_49
LINE_IN_R

DVss1
DVss2
AVss1
AVss2
47 1uF 1nF 1nF 10uF/NC R0603 AUDIO1A 3.3uF
SPDIF_OUT SPDIFI(EAPD) C0603 C0603 C0603 C0805 C1206 +/-5%
48 SPDIFO C0805
1
ALC655 2
4
7
26
42
49
37 3
36 4
5 MIC2
C BC816 C
EMI
0/NC
JACK_AUDX3 Vertical
* 100pF/NC
50V, NPO, +/-5%
R1074 R0603 +/-5% C0603
BC817

R1077 0 R0603 +/-5% * 100pF/NC


50V, NPO, +/-5%
R1075
22K
R1076
22K
C0603 R0603 R0603
*
50 mil wide trace
etched on the PCB +/-5% +/-5%
BC837 0.1uF

PC_BEEP BC818 1uF R1078 10K


SPKR 26,45
*

C0603 +/-5% R0603


BC819 R1081
* 100pF/NC 1K R1079 LINE OUT
C0603 +/-1% 100 CN20
R0603 R0603 RCA JD1 R1082 10K
BC707
+/-5% 10nF RCA3 R0603 +/-5%
SPDIF_OUT 25V, Y5V, +80%/-20%
2 1
*

*
R1080 200
R0603 +/-5%

C0603 * BC820
3

BC836 VCC5A 3.3uF


* 100pF
50V, NPO, +/-5%
C0805
10V, Y5V, +80%/-20%
C0603 JACK_AUDX3 Vertical
FRONT_OUT_R
SPDIF OUT 25

1
24 38
FB53 23 39
FB L0603 47 Ohm FRONT_OUT_L 22

B B
2
AUDIO1B

* BC855
1uF R1084 R1085 R1086
BC821
* *
C0603 10K 22K 22K BC822
+/-5% R0603 R0603 100pF/NC
R0603 100pF/NC C0603 C0603
+/-5% +/-5%
50V, NPO, +/-5%
F_MIC

VCC5A
F_AUDIO
1 2
3 4
LINE_OUT_R 5 6 FRONT_OUT_R
CD IN LINE_OUT_L
7
9
X
10 FRONT_OUT_L

JST-CON4-2-Black Header_2X5_8 BC823


CD_L
5
1
2 CD_GND * 0.1uF
25V, Y5V, +80%/-20%
3 C0603
4 CD _R

CD_IN

A A

TECHNOLOGY COPR.
Title
AC97 CODEC
Document Number Rev
748A01 A
Date: Sunday, September 05, 2004 Sheet 38 of 48

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D20

BPWR 2 1
12V_SYS
D BC745
EC74
B320B D

1
0.10uF
C0603
* 470uF/NC
16V, +/-20%
CE35D80H200

2
BC746
1 2 0.10uFC0603
FB46
1 2

FB L0805 60 Ohm

2 1
SHD3

TPB0_L 1394GND 1394VCC


4 1394D0+ 1394D0- 3 TPB0J 32
6 1394D1+ 1394D1- 5
8 SHD2 SHD1 7

CN17
1394 CONN

C TPA0J 32 C

TPA0 32

TPB0 32

D21
2 1 12V_SYS

B320B

BC747 EC76
1

0.10uF * 470uF/NC
B C0603 16V, +/-20%
CE35D80H200
B
2

CN18
TPA1J_L
TPA1J 32
1 2 TPA1_L
TPA1 32
3 4
5 6 TPB1J_L
TPB1J 32
7 8
X 10

TPB1_L
TPB1 32
HEADER_2X5_9_Shield

BC7491 2 0.10uF

FB48
1 2
A A
FB L0805 60 Ohm

TECHNOLOGY COPR.
Title
1394 I/O
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 39 of 48
8 7 6 5 4 3 2 1
5 4 3 2 1
3D3V_SB

5V_SB 5V_SYS 5V_SYS


VBAT
BC598 BC599
* 4.7uF
*0.1uF/NC
10V, Y5V, +80%/-20%
*
BC600
0.1uF
*
BC601
0.1uF
*
BC602
0.1uF/NC
POWER ON TRAPS

C0805 C0603
C0603 C0603 C0603

D 5V_SYS
D
U22 PRPD[0..7]

76

77

35
99
PRPD[0..7] 44

4
VBAT

VCCH

VCC
VCC
VCC
118 116 PRPD7
44 DCDJ1 DCD1# PD7 PRPD6
44 RIJ1 119 RI1# PD6 115
120 114 PRPD5
44 CTSJ1 DTRJ1 CTS1# PD5 PRPD4 RN69
44 DTRJ1 121 DTR1#/JP1 PD4 113
44 RTSJ1
RTSJ1 122
123
RTS1#/JP2 PD3 112
111
PRPD3
PRPD2
DTRJ2
TD1
*
1
3
2
4
44 DSRJ1 TD1 DSR1# PD2 PRPD1 RTSJ1
44 TD1 124 SOUT1/JP3 PD1 110 Print Port 5 6
125 109 PRPD0 DTRJ1 7 8
44 RD1 SIN1 PD0
108 PSTB# 2.2K
STB# PSTBJ 44
126 107 PAFD# +/-5%
DCD2# AFD# PAFDJ 44
PRERR# 8P4R0603
COM 127
128
RI2#
CTS2#
ERR#
INIT#
106
105 PINIT#
PRERRJ
PINITJ
44
44
DTRJ2 1 104 PSLIN#
DTR2#/JP4 SLIN# PSLINJ 44
2 103 PACK#
RTS2# ACK# PACKJ 44
3 102 PBUSY
DSR2# BUSY PBUSY 44
TD2 5 101 PE
SOUT2/JP5 PE PE 44
6 100 R446 22 PSLCT
SIN2 SLCT PSLCT 44

F D0 7 98 VIN0
C 43 FD[0..7]
F D1 8
FD0/GP10
FD1/GP11
VIN0
VIN1 97
VIN0 42
C
F D2 9 96 VIN1
FD2/GP12 VIN2 VIN1 42
F D3 10 95 VIN2
FD3/GP13 VIN3 VIN2 42 1.If use LPC ROM, pull down S4 ~ S7
F D4 11 94
FD4/GP14 VIN4 VIN3 42
F D5 12 93 and pull down S8 with 2.2Kohm. TD2 R448 2.2K/NC
F D6 FD5/GP15 VIN5
13 FD6/GP16 VIN6 92
F D7 14 91 2.If use Legacy 2MB flash rom, pull high
FD7/GP17 VIN7 S4 ~ S7 and pull down S8 with 2.2Kohm.
FA0 16 90 SIOVREF R449 2.2K
43 FA[0..17] FA0/GP20 VREF SIOVREF 42
FA1 17 3.If use Legacy 4MB flash rom, pull high
FA2 FA1/GP21 S4 ~ S7 and pull high S8 with 2.2Kohm.
18 FA2/GP22
FA3 19 91 TMPIN3
FA4 FA3/GP23
ISA FA5
20
21
FA4/GP24
FA5/GP25 TMPIN1 89 TMPIN1 6,42
FA6 22 88 TMPIN2 42
FA7
FA8
FA9
23
24
25
FA6/GP26
FA7/GP27
FA8/GP30
FA9/GP31
ITE8705 TMPIN2
TMPIN3 87

FA10 26
FA11 FA10/GP32 87 COPEN
27 FA11/GP33 CIRRX/GP67 85
FA12 28 84 ITE8705 POWER ON TRAP
FA13 FA12/GP34 CIRTX/GP66
29 FA13/GP35
FA14 30 S8
FA15 FA14/GP36 IRRX
31 FA15/GP37 IRRX/GP65 83
FA16 32 82 IRTX 1-2 : 4M FLASH ROM ENABLE
FA17 FA16/GP50 IRTX/GP64 (PIN 75 IS FA18)
33 FA17/GP51

B 43 FRDJ 34
47
FRD#/GP52
81
2-3 : PIN 75 IS FAN_TAC3
B
43 FCSJ FCS#/GP53 PME#/GP63 PMEJ 24,26,29,30,31
43 FWEJ 48 FWE#/GP54

80
19 CK_33M_SIO 42 PCICLK
FAN_CTL3/GP62
FAN_CTL2/GP61 79 IR CONNECTOR
78 5V_SYS
26 LAD[0..3] FAN_CTL1/GP60
LAD0 38
LAD1 LAD0 IR
CN8
LPC LAD2
39
40
LAD1
LAD2 G/FA18/FAN_TAC3 75 FA18 43 1
LAD3 41 74 PN74
LAD3 GP56/FAN_TAC2 FAN_TAC2 42
73 IRRX
GP55/FAN_TAC1 FAN_TAC1 42 3
LDRQJ 36
26 LDRQJ SIRQ LDRQ# IRTX 4
26 SIRQ 37 SERIRQ 5
24,25,29,30,31 PCIRSTJ0 45 LRESET#
46 72 HEADER_1X5_2/NC
26 LFRAMEJ LFRAME# DSKCHG# DSKCHGJ 43
WPT# 71 WPJ 43
INDEX# 70 INDEXJ 43
CK_48M_SIO 44 69
19 CK_48M_SIO CLKIN TRK0# TRK0J 43
RDATA# 68 RDATAJ 43
WGATE# 66 WGATEJ 43
49 JSACX/GP40 HDSEL# 65 HEADJ 43
26 THERMJ 50 JSACY/GP41 STEP# 64 STEPJ 43

45 SIOSPKR
51
52
JSAB1/GP42
JSAB2/GP43
DIR#
WDATA#
63
62
DIRJ
WDJ
43
43
FLOPPY
61
A 53 JSBCX/GP44
DRVB#
DRVA# 60
DSBJ
DSAJ
43
43
A
54 JSBCY/GP45 MTRB# 59 MOBJ 43
GNDD1
GNDD2
GNDD3

55 JSBB1/GP46 MTRA# 58 MOAJ 43


GNDA

56 57
GND

JSBB2/GP47 DENSEL# RWCJ 43


TECHNOLOGY COPR.
ITE8705 Title
86

43

15
117
67

ITE8705GX
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 40 of 48
5 4 3 2 1
8 7 6 5 4 3 2 1

D D
5V_SB
5V_SB

8
6
4
2
RN35
10K
8P4R0603

*
+/-5%

7
5
3
1
KBDAT XKBDAT
26 KBDAT
CONNECTOR VIEW TOP VIEW

KBCLK XKBCLK
26 KBCLK 12 11
C BC604 BC605 BC606 12 11 . . C
* 56pF/NC
* 56pF/NC
* 0.1uF/NC . .

13

14

15
5
3
1

2
4
6
50V, NPO, +/-5% 25V, Y5V, +80%/-20% . . . .
C0603 C0603 C0603 CN9 10 9
PS2-KBMS-2 . . 10 8 7 9

8 7 6 5
. . . .

DOWN
. . . .

4 2 1 3

UP
6 5
. .

4 3

16

11
9
7
8
10
12

17
. .

2 1
. .

PMDAT XPMDAT
26 PMDAT

PMCLK XPMCLK
26 PMCLK NOTE:
B BC607 BC608 SIS IS NOT RESPONSIBLE FOR
B
* 56pF/NC
* 56pF/NC
50V, NPO, +/-5%
ANY ERRORS OR OMISSIONS IN
THESE SCHEMATICS. THIS IS
C0603 C0603 BC609 AN EXAMPLE ONLY.
* 0.1uF/NC
25V, Y5V, +80%/-20%
C0603

A A

TECHNOLOGY COPR.
Title
Keyboard Mouse
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 41 of 48
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Voltage Monitor FAN Input and Output

VCCP 3D3V_SYS 5V_SYS 12V_SYS

D D
R456 R457 R458 R459
10K 10K 6.8K 30K
+/-5% +/-5% +/-5% +/-5%
R0603 R0603 R0603 R0603
12V_SYS
Fan Header 1
12V_SYS For CPU

40 VIN0 CN10

40 VIN1 3 4
40 VIN2 2
R464 1
40 VIN3

2
4.7K
+/-5% D17
R0603 1N4148W/NC CONN3(FAN3P)

R468 22

1
R465 R466 R467 40 FAN_TAC2
10K 10K 10K R527 BC610
+/-5%
R0603
+/-5%
R0603
+/-5%
R0603
10K
+/-5% * 0.1uF
25V, Y5V, +80%/-20%
DUMMY R0603 C0603
DUMMY

C C

CHECK FAN PCB FOOTPRINT

12V_SYS
12V_SYS

check footprint
B CN11 B
Temperature Monitor 3 4

2
R474 2
4.7K D18 1
Choosing method of measuring temperature by either thermistor or diode +/-5% 1N4148W/NC
R0603
CONN3(FAN3P)

1
R528 22
40 FAN_TAC1
40 SIOVREF BC616

BC615 R475 R477


R529
10K * 0.1uF
25V, Y5V, +80%/-20%
* 0.1uF/NC 10K
+/-1%
30K
+/-1%
+/-5%
R0603
C0603
DUMMY
C0603 R0603 R0603

40 TMPIN2

6,40 TMPIN1 THERMDA 6,40

*
* BC617
T
0.1uF/NC
RT1
10K
*
BC619
3.3nF
C0603 +/-1% 16V, NPO, +/-5%
R0603 C0603
A JP19 A
2 1 THERMDC 6
SHORT
TECHNOLOGY COPR.
Title
For CPU
FAN HW Monitor
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 42 of 48
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BIOSVCC
3D3V_SYS 5V_SYS

D ISA INTERFACE ROM R480 R481 F D3 8 7 RN37 * BC680


D
0/NC 0 F D2 6 5 4.7K 0.1uF
+/-5% +/-5% F D1 4 3 +/-5%
R0603 R0603 F D0 2 *
1 8P4R0603

FD[0..7]
40 FD[0..7] FA[0..17]

BIOSVCC
40 FA[0..17]

U23 F D7 8 7 RN38
32 13 F D0 F D6 6 5 4.7K
FA0 VCC O0 F D1 F D5 +/-5%
12 A0 O1 14 4 3
FA1 11 15 F D2 F D4 2 *
1 8P4R0603
FA2 A1 O2 F D3
10 A2 O3 17
FA3 9 18 F D4
FA4 A3 O4 F D5
8 A4 O5 19
FA5 7 20 F D6
FA6 A5 O6 F D7
6 A6 O7 21
FA7 5
FA8 A7
27 A8
FA9 26
BIOSVCC FA10 23
A9
FA11 A10
25 A11
FA12 4
FA13 A12
28 A13
R482 FA14 29
8.2K FA15 A14
3 A15
+/-5% FA16 2
C R0603 FA17 30
A16
A17
C
FCSJ 22
FAN_TAC3 FR DJ CE
24 OE
R484 0 1
40 FA18 DUMMY R485 330 VPP
40 FWEJ 31 PGM
16 GND
PLCC-32-SKT

FCSJ
40 FCSJ FR DJ
40 FRDJ

5V_SYS

B 2
B
4
6
8
R486
330 RN39
FDC +/-5% 330
R0603 8P4R0603
+/-5%
*1
3
5
7

CN13
1 1 2 2 RWCJ 40
3 3 4 4
5 5 6 6
7 7 8 8 INDEXJ 40
9 9 10 10 MOAJ 40
11 11 12 12 DSBJ 40
13 13 14 14 DSAJ 40
15 15 16 16 MOBJ 40
17 17 18 18 DIRJ 40
19 19 20 20 STEPJ 40
21 21 22 22 WDJ 40
23 23 24 24 WGATEJ 40
25 25 26 26 TRK0J 40
27 27 28 28 WPJ 40
29 29 30 30 RDATAJ 40
31 31 32 32 HEADJ 40
33 34
A 33 34 DSKCHGJ 40
A
CONN34 (FDD)

TECHNOLOGY COPR.
Title
Index
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 43 of 48
8 7 6 5 4 3 2 1
A B C D E

5V_SYS CN14

PSLCT 13
PRPD[0..7] 25
40 PRPD[0..7] RN40 33 PE 12

2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8

1
PRPD3
PRPD2
*
1
3
2
4
RN41 RN42 RN43
RN44 R487 PBUSY
24
11
PRPD1 5 6 23
PRPD0 7 8 2.7K 2.7K PACKJ 10
4 22 4

2
*

*
P_D7 9

1
3
5
7

1
3
5
7

1
3
5
7

1
3
5
7
2.7K 2.7K 2.7K PERRJ 21
+/-5% +/-5% +/-5% AFDJ P_D6 8 26
RN45 8P4R0603 8P4R0603 8P4R0603 INIT 20 27
40 PSTBJ *
1
3
2
4
SLINJ P_D5 7
19
28
40 PAFDJ STRBJ P_D4
40 PINITJ 5 6 6
7 8 P_D0 18
40 PSLINJ P_D1 P_D3 5
33 P_D2 SLINJ 17
+/-5% P_D3 P_D2 4
8P4R0603 P_D4 INIT 16
RN46 P_D5 P_D1 3
PRPD7
PRPD6
1
3
* 2
4
P_D6
P_D7
PERRJ
P_D0
15
2
PRPD5 5 6 AFDJ 14
PRPD4 7 8 STRBJ 1

33
+/-5% PRNT25-M

BC620

BC621

BC622

BC623

BC624

BC625

BC626

BC627

BC628

BC629

BC630

BC631

BC632

BC633

BC634

BC635

BC636
8P4R0603 PRINT PORT
40 PRERRJ

1
220pF/NC

220pF/NC

220pF/NC

220pF/NC

220pF/NC

220pF/NC

220pF/NC

220pF/NC

220pF/NC

220pF/NC

220pF/NC

220pF/NC

220pF/NC

220pF/NC

220pF/NC

220pF/NC

220pF/NC
PACKJ D11

2
40 PACKJ PBUSY XRIJ1
40 PBUSY 1 2
3 PPE 3
40 PE PSLCT 1N4148W
40 PSLCT

5V_SYS 12V_SYS

BC637 COM1 BC638 R488


0.1uF/NC 0.1uF/NC 560K
* 25V, Y5V, +80%/-20% * 25V, Y5V, +80%/-20% +/-5%
C0603 C0603 COM1 R0603
U24 10
20 VCC V+ 1
19 ROUT1 2 RIN11 1 RING
40 DCDJ1 RIN1 26 RING
18 ROUT2 3 RIN21 6 R489
40 DSRJ1 RIN2
17 ROUT3 4 RIN31 2 220K
40 RD1 RIN3 C0603
40
40
RTSJ1
TD1
16 DIN1
15 DIN2
DOUT1
DOUT2
5
6
DOUT11
DOUT21
7
3
* +/-5%
R0603
14 ROUT4 7 RIN41 8 BY EXPERIENCED 100pF
40 CTSJ1 RIN4 BC639
13 DIN3 8 DOUT31 4
40 DTRJ1 DOUT3
12 ROUT5 9 XRIJ1 9 DUMMY
40 RIJ1 RIN5
11 GND V- 10 5

GD75232 BC640 BC641 BC642 BC643 BC644 BC645 BC646 BC647 BC648 11
2

2
0.1uF/NC 47pF 47pF 47pF 47pF 47pF 47pF 47pF 47pF
* 25V, Y5V, +80%/-20% COM_PORT_9
C0603
1

1
2 2

-12V_SYS
DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY

NEAR CONN

1 1

TECHNOLOGY COPR.
Title
COM/PRT PORT
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 44 of 48
A B C D E
8 7 6 5 4 3 2 1

3D3V_SB

3D3V_SYS

5V_SYS R1154 5V_SYS


R1155 330
330 +/-5%
+/-5% R0603
D R1156
330
R0603
R490
D
+/-5% 220
R0603 +/-5%
R0603

J7
FP1 SPK 1 1
HD_LED+ 1 2 PLED+ 3
HD_LEDJ 3 G_LED R495 33 3
37 HDDLED 4 4 4
5 6 PWRBTNJ 26
7 8 Header_1X4_2
46 RSTSWJ
9 X D13

1
BC662 BC663 2

C
Header_2X5_10 Shield 26,38 SPKR BC661
0.1uF/NC 0.1uF B 3
* 0.1uF
2

2
Q39 25V, Y5V, +80%/-20%
1 MMBT3904 C0603

E
40 SIOSPKR

BAT54C

C C

R496 220 G_LED


26 S1LED_GREEN

3D3V_SB

D14
2 1
RTC 1N4148W/NC

NOTE!
R497 1K AUXOK
AUXOK 13,26
1.The RTCVDD is 3V
3D3V_SB
2.Decoupling capacitor must be close to 96X RTCVDD pin.

1
R498 EC56
100K 22uF
B 3.RTC circuit must strictly follow SiS's recommended design +/-5%
B

2
R0603 CE20D50H110
SiS is not responsible for RTC problems from foreign designs.
RTCVDD

D15

2
D16
3 2 1

1 1N4148W/NC
CN15
3 3 R499 10K
BAT54C 2 2 BATOK 26
BC664 1 1
BAT * 1uF
10V, Y5V, +80%/-20%
HEADER_1X3

C0603 2-3: NORMAL


1K BC665 BC666 BC667
R500
1-2: Clear CMOS
* 1uF
* 15nF/NC
25V, Y5V, +80%/-20% *10uF
10V, Y5V, +80%/-20%
C0603 C0603 C1206
1

CN16
A A
Battery holder
2

TECHNOLOGY COPR.
Decoupling Capacitor
Place close to 96X Title
Power BTN/RTC Batt
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 45 of 48
8 7 6 5 4 3 2 1
5 4 3 2 1

5V_SB 5V_SYS -12V_SYS 3D3V_SYS 3D3V_SYS 5V_SYS 5V_SB 12V_SYS 5V_SYS

D D

1
BC668
R501 0.1uF/NC
8.2K 25V, Y5V, +80%/-20%

2
+/-5% C0603 The circuit generates PWRGOOD signal
R0603 PWR1 R119
11 3.3V* 1 8.2K to CPU, Be sure that the rising time of 5V_SB VCCP
3.3V* +/-5%
12 -12V 3.3V* 2 CPU PWRGOOD must be short than
13 COM 3 R0603
14 PS-ON
COM
4 200ns and delay > 3ms after Vcc_core R502
26 PSONJ 5V
15 COM COM 5 stable. 4.7K R505
16 COM 6 +/-5% 100
5V R0603 +/-5%
17 COM COM 7
18 -5V 8 ATX_PWOK R0603
PW-OK TO CPU
19 5V 5VSB 9
BC835 20 5V 10

21
12V
* 10uF/NC PWRGOOD
PWRGOOD 7
1

1
6.3V, X5R, +/-20% BC669 ATX Power 2X10 BC670 BC671

21
C1206 0.1uF/NC 0.1uF/NC

D
0.1uF/NC PWMOK
2

2
C0603 C0603 C0603 9 PWMOK Q43
BC672
R507
5.6K
G
*270pF
2N7002 50V, NPO, +/-10%
R1158 +/-5% C0603

S
1K/NC R0603
VCCP DUMMY Q44
C +/-5% MMBT3904/NC C
R0603 R508 BC674
3K/NC
+/-5% * 1uF/NC

R0603 C0603
Increase PWRGOOD signal
R1148 rising speed for avoid CPU
can't weakup from S3/S4/S5 3D3V_SYS
state issue.

0
R0603 R530
+/-5% 100
+/-5%
5V_SB 3D3V_SYS R1149 R0603
R510 0
20K/NC Q45 +/-5%
7 K7_PLL_PGD +/-5% MMBT3904/NC R0603 PWRGOODMB
R511 R512 R0603 R513 BC675
4.7K/NC 100/NC 10K/NC
* 47nF/NC

D
+/-5% +/-5% +/-5% 25V, Y5V, +80%/-20%
R0603 R0603 TO south-bridge R0603 C0603 Q52
BC681
PWRGD_SB 26 G
*270pF
2N7002 50V, NPO, +/-10%
D

R514 C0603

S
Q46 51K/NC
B +/-5% R515 B
G R0603 10
RSTSWJ 45
2N7002/NC +/-5%
R0603 ATX_PWOK
C

R516 ATX_PWOK
PWRGOODMB 4.7K/NC B Q47 R517
+/-5% MMBT3904/NC 4.7K
R0603 BC676 +/-5%
E

* 0.1uF
25V, Y5V, +80%/-20%
3D3V_SYS R0603
Q48
C0603 MMBT3904
DUMMY R518 R519 BC677
100/NC
+/-5% TO north-bridge
10K
+/-5% * 0.1uF
25V, Y5V, +80%/-20%
R0603 R0603 C0603
DUMMY
PWRGD_NB 13
D

R520
Q49 51K/NC
+/-5%
G R0603
2N7002/NC
S

A A
R1150

TECHNOLOGY COPR.
0
R0603 Title
+/-5% Power Connector
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 46 of 48
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

TECHNOLOGY COPR.
Title
GPIO Setting
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 47 of 48
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

TECHNOLOGY COPR.
Title
Change List
Document Number Re v

748A01 A
Date: Sunday, September 05, 2004 Sheet 48 of 48
5 4 3 2 1

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