Er63419 Rev101 140628
Er63419 Rev101 140628
Er63419 Rev101 140628
R63419
16,777,216–Color, 1600RGB x 2560 -Dot Graphics Liquid
Crystal Controller Driver for TFT Panel
Rev.1.01
June 28, 2014
Description .......................................................................................................... 9
Features ............................................................................................................... 9
Reset .................................................................................................................... 32
(1) Command Default Values .................................................................................................................................... 32
(2) Initial States of Input/Output Pins and Output Pins ............................................................................................. 32
Description
The R63419 is liquid crystal controller driver LSI for TFT panel sized 1600RGB x 2560-dot at
maximum. For high-speed data transfer, the R63419 supports MIPI DSI (4 lanes) with 2 ports as
system interface to microcomputer.
The R63419 incorporates step-up and voltage follower circuits to generate drive voltage required for
TFT liquid crystal panel and a dynamic backlight control function to control backlight brightness
depending on image data, reducing power consumption at the backlight with the slightest influence on
image quality.
Other features include a power management function, making the R63419 best suitable for small-and-
mid-sized portable devices with color graphics display such as digital mobile phones, Smartphone,
Tablet PC, and photo frames.
Features
Single chip driver for 16, 777, 216-color TFT 1600RGB x 2560-dot graphics (with power supply
circuits and supporting LTPS panel )
Resolution: 1600RGB x 2560 dots, 1536RGB x 2560dots,1440RGB x 2560dots
Command set (Compliant with MIPI DCS Version 1.01.00) *DCS: Display Command Set
System interface
– MIPI DSI : 4 data lanes and 1 clock lane with 2 ports
MIPI DSI: Version 1.01.00r11 21-Feb-2008 (Video Mode supported)
MIPI D-PHY: Version 1.00.00 14-May-2009
Video image display interface (see Note 1)
- MIPI DSI TE-reporting
Direct compressed data input
- Video through mode : 1/2 or 1/3 data compressed data input
- Command mode : 1/3 data compressed data input (see Note.3)
Abundant color display and drawing functions
– 16,777,216-color display
– Partial display function
– Digital Gamma Adjustment for RGB separate gamma correction function
– Color Enhancement with skin tone correction function
– Sunlight Readability Enhancement function
– Local area Auto Contrast Optimization
Low-power consumption architecture (allowing direct input of interface I/O power supply)
– Deep standby mode
– Input power supply voltage:
Interface and logic power supply: IOVCC
Analog power supply:,VSP,VSN
MIPI D-PHY power supply: DPHYVCC
Note1: Connect these power supplies to other power supplies on the FPC when they are set at the same
electrical potential as other power supplies. For voltage, see DC Characteristics in Electrical
Characteristics.
Note2: The voltage of this terminal should not exceed DPHYVCC.
Term Definition
RSP LCD Driver: an RSP product to be used according to its data sheet
(1) Unit which data is written to data should be written to Frame memory in unit of 2 lines
If writing to Frame memory stops halfway, the wirte data is not reflected in Frame memory.
(3) To keep the write speed at 1Gbps/lane, the range of SC and EC of the window address needs to be
set as following table.
Table 3 Range of window address (SC, EC) at write speed of 1Gbps/lane horizontal resolution
(5) If writing to Frame memory is started by the 2Ch command during Sleep In state, the internal OSC
starts operating.
To stop the internal OSC after the end of writing to Frame memory, wait 200us and then execute
the Sleep In command via DSI.
Block Diagram
LEDPWM GNDRF
Command GND
Register (CDR) Parameter Address Image processing IP AGND
Register Counter
(PR)
CABC, CE, SRE, ACO
DUMMYR1-2
IOVCC DUMMY
IOVCCRF NV
IM2-IM0 Memory
CSX
DCX System Data
WRX/SCL Interface compress
circuit
Source Driver
DOUT
Latch circuit
Latch circuit
Latch circuit
Frame
Write Data Memory
TE Register S1-S2400
TE2 (WDR)
RESX 4,096,000
bytes
DPHYVCC
DPHYGND
VDDLP_A/B
CLKP/N_A/B MIPI-DSI
DATA0P/N_A/B 4 lane
DATA1P/N_A/B
Gamma calculation
circuit
PNSLV
Timing Generator
DBIST
VSOUT
HSOUT Touch panel
sync. output
Panel Interface circuit
EXCK
(for LTPS)
OSC
SOUT1-32
Internal reference
Voltage generator
Internal logic
power supply
regulator
VDD
PCLK
VREF
TESTE
VREFC
HSYNC
DB7-1
VREFM
TS1-0
TEST1-4,6
VDDTEST
VSP
VSN
VGLP
VSNRF
VGHP
VCL
VGL
VPLVL
VNLVL
VGH
VCOM
C21P/C21M
VSPRF
C31P/C31M
VCI
Figure 1
Block Function
The RSP LCD driver supports MIPI DSI Command Mode, MIPI DSI Video Mode. The RSP LCD
driver also supports TE synchronization signal as display interface for video mode.
Table 4
Number of available
IM2 IM1 IM0 Interface Used pin
colors
0 0 0 Setting disabled - -
0 0 1 Setting disabled - -
0 1 0 Setting disabled - -
0 1 1 Setting disabled - -
1 0 0 Setting disabled - -
1 0 1 Setting disabled - -
DATA0P/N_A/B,
DATA1P/N_A/B,
1 1 0 MIPI DSI 262,144/16,777,216
DATA2P/N_A/B,
DATA3P/N_A/B
1 1 1 Setting disabled - -
When MIPI DSI command mode is selected, display data is written in synchronization with a start of
the frame period by TE-reporting function. This enables updating image data without flicker on the
panel.
Data written in MIPI DSI video mode is directly output as display data without being written to internal
GRAM.
(3)Frame memory
R63419 incorporates the frame memory that has a capacity of 4,096,000 bytes, which can store pattern
data of 1600RGB x 2560 graphics display at the maximum using. Send display data in units of 4 pixels
because of data compression.
The grayscale voltage generating circuit generates liquid crystal drive voltage according to the
grayscale setting value in the gamma correction registers. RGB separate gamma correction setting
enables maximum 16,777,216-color display.
The LCD drive power supply circuit generates voltage levels to drive the liquid crystal panel.
(6)Timing Generator
The timing generator is used to generate timing signals for operating internal circuits.
(7)Oscillator (OSC)
The LCD driver circuit has the 2400-channels source driver (S1-S2400). When 1600RGB pixels of
data are input, the display pattern data is latched. The voltage is output from the source driver
according to the latched data.
The panel interface circuit generates and outputs the interface signals (SOUTn) to the TFT panel.
The internal logic power supply regulator generates power supply for the internal logic circuit.
(11)Image processing IP
The backlight control circuit(CABC) adjusts backlight brightness according to the histogram of image
to reduce power consumption at the backlight. Brightness of the backlight and display data is adjusted.
The color enhancement control circuit (CE) enhances the saturation of the image displays on the liquid
crystal panel and displays image with color enhanced.
The sunlight readability control circuit (SRE) enhances the image data to make it easier to read under
strong sunlight.
(12)NVM
The RSP LCD driver supports NVM that stores manufacturer command setting values.
The RSP LCD driver can output the synchronization signals to capture touch sensing signal for touch
panel controller. To use these signals, touch panel controller can capture touch sensing signal while
avoiding display changing noise.
Pin Function
Table 5 External Power Supply Pins
Signal I/O Connect to Function Connection
when signal
is unused
IOVCC I Power supply Power supply to interface pins. Power supply
IOVCC < 0.3V (When power is turned off.) Stabilizing
Stabilizing
capacitor capacitor
IOVCCRF I Power supply Connect to IOVCC on the FPC to prevent noise in case of COG. Power supply
DPHYVCC I Power supply Power supply to MIPI DSI D-PHY Power supply
Connect to IOVCC on the FPC when DPHYVCC is set at the same Stabilizing
Stabilizing
electrical potential as IOVCC. capacitor
capacitor
GND I Power supply GND for internal logic and interface pins. GND=0V. Power supply
GNDRF I Power supply Connect to GND on the FPC to prevent noise in case of COG. Power supply
AGND I Power supply Analog GND (logic regulator and LCD power supply circuit). AGND = Power supply
0V. Connect to GND on the FPC to prevent noise in case of COG.
AGNDRF I Power supply Connect to AGND on the FPC to prevent noise in case of COG Power supply
VSP I Power supply Power supply analog circuit Power supply
Stabilizing Stabilizing
capacitor capacitor
VSPRF I Power supply Connect to VSP on the FPC to prevent noise in case of COG Power supply
VSN I Power supply Power supply analog circuit Power supply
Stabilizing Stabilizing
capacitor capacitor
VSNRF I Power supply Connect to VSN on the FPC to prevent noise in case of COG Power supply
DPHYGND I Power supply GND for MIPI DSI D-PHY Connect to GND on the FPC to prevent Power supply
noise in case of COG.
RESX I Host Processor Reset pin. The RSP LCD driver is initialized when RESX is Low. Host
or external RC Make sure to execute power-on reset when turning power supply on. Processor or
circuit external RC
circuit
TE O Host processor Tearing effect output signal. Open
By register settings, it can be used as a verify signal for NVM write.
Leave it open when not in use.
Table 13 Clock External Application Control pin (Amplitude: IOVCC - GND) (Test mode)
Signal I/O Connect to Function Connection
when signal
is unused
External clock input pin. The internal clock and the external
EXCK I Host Processor GND
supply clock can be switched by register control.
Table 15 DSI select port number select pin (Amplitude: IOVCC - GND)
Signal I/O Connect to Function
0 0 0 0 DATA3N DATA3P DATA2N DATA2P CLKN CLKP DATA1N DATA1P DATA0N DATA0P DATA0P DATA0N DATA1P DATA1N CLKP CLKN DATA2P DATA2N DATA3P DATA3N
0 0 0 1 DATA3N DATA3P DATA0N DATA0P CLKN CLKP DATA1N DATA1P DATA2N DATA2P DATA2P DATA2N DATA1P DATA1N CLKP CLKN DATA0P DATA0N DATA3P DATA3N
0 0 1 0 DATA0N DATA0P DATA1N DATA1P CLKN CLKP DATA2N DATA2P DATA3N DATA3P DATA3P DATA3N DATA2P DATA2N CLKP CLKN DATA1P DATA1N DATA0P DATA0N
0 0 1 1 DATA2N DATA2P DATA1N DATA1P CLKN CLKP DATA0N DATA0P DATA3N DATA3P DATA3P DATA3N DATA0P DATA0N CLKP CLKN DATA1P DATA1N DATA2P DATA2N
0 1 0 0 DATA3P DATA3N DATA2P DATA2N CLKP CLKN DATA1P DATA1N DATA0P DATA0N DATA0N DATA0P DATA1N DATA1P CLKN CLKP DATA2N DATA2P DATA3N DATA3P
0 1 0 1 DATA3P DATA3N DATA0P DATA0N CLKP CLKN DATA1P DATA1N DATA2P DATA2N DATA2N DATA2P DATA1N DATA1P CLKN CLKP DATA0N DATA0P DATA3N DATA3P
0 1 1 0 DATA0P DATA0N DATA1P DATA1N CLKP CLKN DATA2P DATA2N DATA3P DATA3N DATA3N DATA3P DATA2N DATA2P CLKN CLKP DATA1N DATA1P DATA0N DATA0P
0 1 1 1 DATA2P DATA2N DATA1P DATA1N CLKP CLKN DATA0P DATA0N DATA3P DATA3N DATA3N DATA3P DATA0N DATA0P CLKN CLKP DATA1N DATA1P DATA2N DATA2P
1 0 0 0 DATA3N DATA3P DATA2N DATA2P CLKN CLKP DATA1N DATA1P DATA0N DATA0P DATA3N DATA3P DATA2N DATA2P CLKN CLKP DATA1N DATA1P DATA0N DATA0P
1 0 0 1 DATA3N DATA3P DATA0N DATA0P CLKN CLKP DATA1N DATA1P DATA2N DATA2P DATA3N DATA3P DATA0N DATA0P CLKN CLKP DATA1N DATA1P DATA2N DATA2P
1 0 1 0 DATA0N DATA0P DATA1N DATA1P CLKN CLKP DATA2N DATA2P DATA3N DATA3P DATA0N DATA0P DATA1N DATA1P CLKN CLKP DATA2N DATA2P DATA3N DATA3P
1 0 1 1 DATA2N DATA2P DATA1N DATA1P CLKN CLKP DATA0N DATA0P DATA3N DATA3P DATA2N DATA2P DATA1N DATA1P CLKN CLKP DATA0N DATA0P DATA3N DATA3P
1 1 0 0 DATA3P DATA3N DATA2P DATA2N CLKP CLKN DATA1P DATA1N DATA0P DATA0N DATA3P DATA3N DATA2P DATA2N CLKP CLKN DATA1P DATA1N DATA0P DATA0N
1 1 0 1 DATA3P DATA3N DATA0P DATA0N CLKP CLKN DATA1P DATA1N DATA2P DATA2N DATA3P DATA3N DATA0P DATA0N CLKP CLKN DATA1P DATA1N DATA2P DATA2N
1 1 1 0 DATA0P DATA0N DATA1P DATA1N CLKP CLKN DATA2P DATA2N DATA3P DATA3N DATA0P DATA0N DATA1P DATA1N CLKP CLKN DATA2P DATA2N DATA3P DATA3N
1 1 1 1 DATA2P DATA2N DATA1P DATA1N CLKP CLKN DATA0P DATA0N DATA3P DATA3N DATA2P DATA2N DATA1P DATA1N CLKP CLKN DATA0P DATA0N DATA3P DATA3N
Table 18 The test free running mode Control pin (Amplitude: IOVCC - GND)
Signal I/O Connect to Function Connection
when signal
is unused
Enables the Test Image Generation function
High On
VSYNC I Open or GND Test pins. Fix to GND or leave open. Open or GND
HSYNC I Open or GND Test pins. Fix to GND or leave open. Open or GND
PCLK I Open or GND Test pins. Fix to GND or leave open. Open or GND
DE I Open or GND Test pins. Fix to GND or leave open. Open or GND
DB7-1 I Open or GND Test pins. Fix to GND or leave open. Open or GND
TS1-0 O Open Test pin. Leave open. Open
Open or Test pin. Fix to AGND or leave open. To leave open, do not pull Open or
VPP1 I
AGND out ITO wiring. AGND
DUMMY1-422 O Open Dummy pins. Leave open. Open
Alignment Mark
Chip thickness: 170 um (typ.)
Au bump height: 15 um
Alignment mark
15um
30um
120um 30um
Y-size
30um
Alignment
Mark Area 15um
120um
Alignment Mark Area X-size
Bump View
(0,0)
IO side
BUMP
Bump View
Chip
Figure 2
IOVCC
DPHYVCC (8)
(5)
IOVCCRF
VDDLP_A VDD
(1) (4)
VDDLP_B
(2)
VCOM
VCI (7)
(6)
VCL
(3)
R63419
C21P
(11)
C21M
VGH
(14)
VSP
(10)
VGHP
(16)
C31P
(12)
C31M
VGLP
VSN (17)
(9)
VGL
(13)
(15)
Figure 3
2.2µF (B characteristics) 6V (5) DPHYVCC, (6) VCI, (7) VCOM, (8) IOVCC,
2.2µF (B characteristics) 25V (13) VGL, (14) VGH, (16) VGHP, (17) VGLP
VGH/VGHP ( 5V to 13.0V )
Charge pump
VCI( ~ 3.0V )
DPHYVCC
Source(Posi)
VDDLP ( 1.2V )
VCOM(-2V~2V)
IOVCC
VDD ( 1.2V )
Panel I/F
GND ( 0V )
Source(Nega)
VCL ( ~ -3.0V ) Regulator
Regulator
Charge pump
(VSP-VPLVL)≧0.3V
(VSN-VNLVL)≦-0.3V
(VSP-VCI2) ≧ 0.2V
(VSP-VCI3) ≧ 0.2V
R63419 can be operated by supplying VSP and VSN power supply directly.
a)Power On Sequence
90% 90%
IOVCC
DPHYVCC thVSP
tsVSP
90%
tRW1
50% tPOFF2 50%
VSP 10% 10%
tPON2
tPON1 tPOFF1
10% 10%
VSN 50% 50%
90%
tRW1 VIH
RESX VIL
tRT
RSP LCD
driver status Reset Initial condition
IOVCC
DPHYVCC
90%
tRW1
VSP 50%
tPOFF2 50%
10% 10%
tPON2
tPON1
VSN 10%
50%
50%
90%
tRW1 VIH
RESX tRW2
VIL VIL
tRT
RSP LCD
driver status DSTB Reset Initial condition
Notes: 1. Make sure that the following relationships are power supply sequence.
Reset
The RSP LCD driver is initialized by reset input. During the reset period, the RSP LCD driver is set to
its internal initial setting and no command is accepted from the processor. The source driver unit and
the power supply circuit unit are also reset to the respective initial states when reset signal is input to
the RSP LCD driver.
The initial states of commands are shown in the “register map” table. See “register map” The command
setting is initialized to the default value when hardware reset is executed.
A table below shows initial states of input/output pins and output pins after reset.
Table 22 Initial States of Input/Output Pins and Output Pins after Reset
External power supply IOVCC DPHYVCC VSP VSN
P1 P801
2560
1600RGB
R63419
Slave Master
Host
MIPI MIPI
R63419 has PNSLV pin that can select the execution DSI port of User and Manufacture Command.
When PNSLV is connected to GND, PortA is assigned to Master port that is valid to the execution of
command, and when connected to IOVCC, PortB is assigned to Master port. The host processor need
to control via PortA or PortB assigned to Master port function selected by PNSLV pin.
R63419 can select Sn output direction by D6 (36h), SS1 (C1h) and PNSLV pin. LCM needs to
consider the relationship with Panel position and Display. The relationship between Sn output and
D6/SS1/PNSLV is shown below.
Display
Host
Display
S2400 S1201 S1200 S1 S2400 S1201 S1200 S1 S2400 S1201 S1200 S1 S2400 S1201 S1200 S1
RSP LCD Driver RSP LCD Driver RSP LCD Driver RSP LCD Driver
PortB PortA PortB PortA PortB PortA PortB PortA
Master Slave Master Slave Slave Master Slave Master
Slot0 Slot1 Slot0 Slot1 Slot1 Slot0 Slot1 Slot0
Host
Display
Host
Electrical Characteristics
Notes: 1. The DC/AC electrical characteristics of bare die and wafer are guaranteed at +85C.
(2) DC Characteristics
Table 27
Item Symbol Unit Test condition Min. Typ. Max. Note
Vo1 mV V0~V63,V192~V255 - - 35 6
Output voltage dispersion
Vo2 mV V64~V191 - - 15 6
Average output variance ⊿V⊿ mV - -35 - +35 7
Notes: 1. The DC/AC electrical characteristics of bare die and wafer are guaranteed at +85C.
2. The following figures illustrate the configurations of input, I/O, and output pins.
Figure 8
Table 29
Item Symbol Unit Test condition Min. Typ. Max.
Table 30
Item Symbol Unit Test condition Min. Typ. Max.
Oscillation clock fosc MHz IOVCC = 1.8V 53.2 56.0 58.8
Table 31
Item Symbol Unit Test condition Min. Max.
Reset low-level width1 tRW1 us Power supply on 1000 -
Reset low-level width2 tRW2 us Operation 1000 -
Reset time (Sleep IN) tRT1 ms - - 3
Reset time (Sleep OUT) tRT2 ms - - 3
Noise reject width tRESNR us - - 1
Table 32
Item Symbol Unit Test condition Min. Typ. Max Note
IOVCC=1.8V, , Ta=25℃,
VSP=5.60V, VSN=-5.60V,
reached voltage: defined grayscale
Load resistance R
Test Point
Source Pin
Load capacitance C
Table 33
Item Symbol Unit Test condition Min. Typ. Max. Note
Table 34
Item Symbol Unit Test condition Min. Typ. Max. Note
IOVCC=1.65V~ 1.95V
DSICLK Frequency fDSICLK MHz 100 - 500 4
DPHYVCC=1.65V~ 1.95V
IOVCC=1.65V~ 1.95V
DSICLK Cycle time tCLKP ns 1 - 10
DPHYVCC=1.65V~ 1.95V
IOVCC=1.65V~ 1.95V
DSI Data Transfer Rate tDSIR Mbps 200 - 1000 4
DPHYVCC=1.65V~ 1.95V
IOVCC=1.65V~ 1.95V
UI 0.15 - - 6
DPHYVCC=1.65V~ 1,95V
Data to Clock Setup Time tSETUP
IOVCC=1.65V~ 1.95V
ns 0.15 - - 5,6
DPHYVCC=1.65V~ 1.95V
IOVCC=1.65V~ 1.95V
UI 0.15 - - 6
DPHYVCC=1.65V~ 1.95V
Clock to Data Hold Time tHOLD
IOVCC=1.65V~ 1.95V
ns 0.15 - - 5,6
DPHYVCC=1.65V~ 1.95V
Notes: 4. When fDSICLK<125MHz, change auto load NV setting so that it is compliant with THS-PREPARE+THS-ZERO
spec.
5. Minimum tSETUP/tHOLD Time is 0.15UI. This value may change according to DSI transfer rate.
6. tSETUP/tHOLD Time is measured without HS-TX Jitter.
Table 35
Test
Item Symbol Unit Min Typ Max Notes
condition
CLK
D0p/D0n
Capture
LP-11 LP-01 LP-00 1ST Data Bit TEOT LP-11
THS-TRAIL THS-EXIT
TCLK-POST TEOT
VIH(min)
VIL(max)
VIH(min)
VIL(max)
Figure 15 Switching the Clock Lane between Clock Transmission and LP Mode
Command List
Table 36 User Command
Command (C) MIPI DCS
Operational Number Of RSP LCD driver
Command /Read (R) Type 1 Note
Code (Hex) Parameter Implementation
/Write(W) Requirement
00h nop C 0 Yes Yes
01h soft_reset C 0 Yes Yes
Read_Display_Idetificat
04h R 15 No Yes
ion_Infomation
Read_Number_of_the_
05h R 1 No Yes
Errors_on_DSI
06h get_red_channel R 1 Yes Yes
07h get_green_channel R 1 Yes Yes
08h get_blue_channel R 1 Yes Yes
Yes
0Ah get_power_mode R 1 Yes
(Bit 6/5/4/3/2 only)
Yes
0Bh get_address_mode R 1 Yes
(Bit 7/6/4/3/0 only)
0Ch get_pixel_format R 1 Yes Yes
0Dh get_display_mode R 1 Yes Yes
Yes
0Eh get_signal_mode R 1 Yes
(Bit 7/6/0 only)
Bit 7/6: Yes
0Fh get_diagnostic_result R 1 Yes (Bit 6 only)
Bit 5/4: Optional
10h enter_sleep_mode C 0 Yes Yes
11h exit_sleep_mode C 0 Yes Yes
12h enter_partial_mode C 0 Yes Yes
13h enter_normal_mode C 0 Yes Yes
20h exit_invert_mode C 0 Yes No
21h enter_invert_mode C 0 Yes No
22h set_all_pixels_off C 0 No Yes
23h set_all_pixels_on C 0 No Yes
26h set_gamma_curve W 1 Yes Yes
28h set_display_off C 0 Yes Yes
29h set_display_on C 0 Yes Yes
2Ah set_column_address W 4 No Yes
2Bh set_page_address W 4 No Yes
2Ch write_memory_start W Variable No Yes
2Dh write_LUT W Variable Optional No
2Eh read_memory_start R Variable No No
30h set_partial_area W 4 Yes Yes
33h set_scroll_area W 6 No No
34h set_tear_off C 0 No Yes
35h set_tear_on W 1 No Yes
Yes
36h set_address_mode W 1 Yes
(Bit 7/6/4/3/0 only)
37h set_scroll_start W 2 No No
Command Accessibility
In the default status, only User Commands and Manufacturer Command Access Protect (MCAP)
register can be accessed. Other commands are recognized as “nop”.
Manufacturer Commands except the MCAP register are accessible by releasing Access Protect. See
Command the description of the MCAP register for details.
Manufacturer Command
B0h Yes Yes Yes Yes Yes
Access Protect
B1h Low Power Mode Control No No No No Yes
B3h Interface Setting Yes Yes Yes Yes Yes
B4h Interface ID Setting Yes Yes Yes Yes Yes
Read Checksum and ECC
B5h Yes Yes Yes Yes Yes
Error Count
B6h DSI Control Yes Yes Yes Yes Yes
Checksum and ECC Error
B7h Yes Yes Yes Yes Yes
Count Reset
B8h Backlight Control (1) (GUI) Yes Yes Yes Yes Yes
B9h Backlight Control (2) (Still) Yes Yes Yes Yes Yes
BAh Backlight Control (3) (Movie) Yes Yes Yes Yes Yes
SRE Control 1 (SRE=1
BBh Yes Yes Yes Yes Yes
Weak setting)
SRE Control 2 (SRE=2
BCh Yes Yes Yes Yes Yes
Middle setting)
SRE Control 3 (SRE=3
BDh Yes Yes Yes Yes Yes
Strong setting)
BEh Test Register No No No No No
BFh Device code Read Yes Yes Yes Yes Yes
C0h Slew rate adjustment Yes Yes Yes Yes Yes
C1h Display Setting 1 Yes Yes Yes Yes Yes
C2h Display Setting 2 Yes Yes Yes Yes Yes
C3h TPC Sync. Control Yes Yes Yes Yes Yes
C4h Source Timing Setting Yes Yes Yes Yes Yes
C5h Real Time scaling Yes Yes Yes Yes Yes
C6h LTPS Timing Setting Yes Yes Yes Yes Yes
C7h Gamma Setting Yes Yes Yes Yes Yes
C8h Digital Gamma Setting Yes Yes Yes Yes Yes
C9h Test Register No No No No No
CAh Color enhancement Yes Yes Yes Yes Yes
CBh Panel PIN Control Yes Yes Yes Yes Yes
CCh Panel Interface Control Yes Yes Yes Yes Yes
CDh Test Register No No No No No
CEh Backlight Control (4) Yes Yes Yes Yes Yes
Power Setting
D0h Yes Yes Yes Yes Yes
(Charge Pump Setting)
D1h Test Register No No No No No
D2h Power Setting for Common Yes Yes Yes Yes Yes
D3h Test Register Yes Yes Yes Yes Yes
D4h Test Register Yes Yes Yes Yes Yes
D5h VCOM Setting Yes Yes Yes Yes Yes
D6h Test Register No No No No No
D7h Test Register No No No No No
D8h Test Register No No No No No
D9h Test Register No No No No No
E5h Test Image Generator Yes Yes Yes Yes Yes
E6h NVM Access control Yes Yes Yes Yes Yes
E7h Set_DDB write control Yes Yes Yes Yes Yes
E8h NVM load control Yes Yes Yes Yes Yes
E9h Test Register No No No No No
Compression Method
EAh No No No No No
supported
EBh Compression Method No No No No No
ECh Test Register No No No No No
EDh Test Register No No No No No
EEh Test Register No No No No No
EFh Test Register No No No No No
F0h Test Register No No No No No
F1h Test Register No No No No No
F3h Test Register No No No No No
F4h Test Register No No No No No
F9h Test Register No No No No No
FAh Test Register No No No No No
FBh Test Register No No No No No
FCh Test Register No No No No No
FDh Test Register No No No No No
FEh Test Register No No No No No
User Command
nop: 00h
00h nop
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 0 0 0 0 0 0 00h
Parameter None
Description This command is an empty command. It has no effect on the display module.
X = Don’t care
Restriction -
Flow chart -
soft_reset: 01h
01h soft_reset
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 0 0 0 0 0 1 01h
Parameter None
Description When the Software Reset command is written, it causes a software reset. It resets the commands and
parameters to their S/W Reset default values. (See “Default Modes and Values”)
X = Don’t care
Restriction If a soft_reset is sent when the display module is not in Sleep Mode, the host processor needs wait time
before sending an exit_sleep_mode command. (Please refer to the Appendix for maritime.)
soft_reset shall not be sent during exit_sleep_mode sequence.
No new command setting is allowed until the RSP LCD driver enters the Sleep Mode.
See “State Transition Diagram” for the sequence to enter Sleep Mode.
If a soft_reset is sent when the display module is in Sleep Mode, data in NVM are read. No new command
setting is inhibited when data are read (3 ms).
Flow chart
Read_Display_Idetification_Information: 04h
04h Read_Display_Idetification_Infomation
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 0 0 0 1 0 0 04h
Dummy
1 1 X X X X X X X X xxh
parameter
1st ID1 ID1 ID1 ID1 ID1 ID1 ID1 ID1
1 1 XXh
parameter [15] [14] [13] [12] [11] [10] [9] [8]
2nd ID1 ID1 ID1 ID1 ID1 ID1 ID ID1
1 1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
3rd ID2 ID2 ID2 ID2 ID2 ID2 ID2 ID2
1 1 XXh
parameter [15] [14] [13] [12] [11] [10] [9] [8]
4th ID2 ID2 ID2 ID2 ID2 ID2 ID2 ID2
1 1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
5th ID3 ID3 ID3 ID3 ID3 ID3 ID3 ID3
1 1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
6th ID4 ID4 ID4 ID4 ID4 ID4 ID4 ID4
1 1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
7th - 14th
1 1 X X X X X X X X XXh
parameter
15th
1 1 1 1 1 1 1 1 1 1 FFh
parameter
Description ID1[15:0]
ID2[15:0]
ID3[7:0]
ID4[7:0]
04h Read_Display_Idetification_Infomation
Flow chart
Read_Display_Idetification_Information Legend
Host
Command
RSP LCD driver
Dummy Read Parameter
Display
1st parameter ID1[15:8]
(MS byte of Supplier ID) Action
Mode
2nd parameter ID1[7:0]
(LS byte of Supplier ID) Sequential
transfer
Note : When this command is read via DSI, dummy read operation is not preformed.
05h Read_Number_of_the_Errors_on_DSI
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 0 0 0 1 0 1 05h
Dummy
1 1 X X X X X X X X XXh
parameter
1st
1 1 P7 P6 P5 P4 P3 P2 P1 P0 XXh
parameter
Description This command returns an error count when DSI is used.
P[6:0] indicates an error count. When a count overflows, P[7] is set to 1.
When P[7:0] is 0, D0 (0Eh of get_signal_mode) is set to 0.
When this command is read via DSI, P[7:0] is cleared. When this command is read via interface except
DSI, P[7:0] is not cleared.
X = Don’t care
Restriction -
Flow chart
Note : When this command is read via DSI, dummy read operation is not preformed.
get_red_channel: 06h
06h get_red_channel
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 0 0 0 1 1 0 06h
Dummy
1 1 X X X X X X X X XXh
parameter
1st
1 1 R7 R6 R5 R4 R3 R2 R1 R0 XXh
parameter
Description The display module returns the red component value of the first pixel in the active frame.
This command is only valid for Type 2 and Type 3 display modules.
R7 is the MSB and R0 is the LSB.
Only the relevant bits are used according to the pixel format; unused bits are set to ‘0’
18bit format D7 D6 D5 D4 D3 D2 D1 D0
0 0 R5 R4 R3 R2 R1 R0
24bit format D7 D6 D5 D4 D3 D2 D1 D0
R7 R6 R5 R4 R3 R2 R1 R0
Restriction If using compression data transfer, this command does not support.
Flow chart
get_green_channel: 07h
07h get_green_channel
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 0 0 0 1 1 1 07h
Dummy
1 1 X X X X X X X X XXh
parameter
1st
1 1 G7 G6 G5 G4 G3 G2 G1 G0 XXh
parameter
Description The display module returns the green component value of the first pixel in the active frame.
This command is only valid for Type 2 and Type 3 display modules.
G7 is the MSB and G0 is the LSB.
Only the relevant bits are used according to the pixel format; unused bits are set to ‘0’
•18 bit format: G5 is MSB and G0 is LSB. G7 and G6 are set to ‘0’.
• 24 bit format: G7 is MSB and G0 is LSB. All bits are used.
18bit format D7 D6 D5 D4 D3 D2 D1 D0
0 0 G5 G4 G3 G2 G1 G0
24bit format D7 D6 D5 D4 D3 D2 D1 D0
G7 G6 G5 G4 G3 G2 G1 G0
Restriction If using compression data transfer, this command does not support.
Flow chart
get_blue_channel: 08h
08h get_blue_channel
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 0 0 1 0 0 0 08h
Dummy
1 1 X X X X X X X X XXh
parameter
1st
1 1 B7 B6 B5 B4 B3 B2 B1 B0 XXh
parameter
Description The display module returns the blue component value of the first pixel in the active frame.
This command is only valid for Type 2 and Type 3 display modules.
B7 is the MSB and B0 is the LSB.
Only the relevant bits are used according to the pixel format; unused bits are set to ‘0’
18bit format D7 D6 D5 D4 D3 D2 D1 D0
0 0 B5 B4 B3 B2 B1 B0
24bit format D7 D6 D5 D4 D3 D2 D1 D0
B7 B6 B5 B4 B3 B2 B1 B0
Restriction If using compression data transfer, this command does not support.
Flow chart
get_power_mode: 0Ah
0Ah get_power_mode
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 0 0 1 0 1 0 0Ah
Dummy
1 1 X X X X X X X X XXh
parameter
1st IDM PTL SLP NOR DSP
1 1 0 0 0 XXh
parameter ON ON OUT ON ON
Description The display module returns the current power mode as listed below.
Bit Description Comment Command list symbol
D7 Reserved Set to ‘0’. -
D6 Idle Mode On/Off IDMON
D5 Partial Mode On/Off PTLON
D4 Sleep Mode On/Off SLPOUT
D3 Display Normal Mode On/Off NORON
D2 Display On/Off DSPON
D1 Reserved Set to ‘0’. -
D0 Reserved Set to ‘0’. -
Bit D7 – Reserved
This bit is not applicable. Set to ‘0’. (Not supported)
IDMON
PTLON
SLPOUT
0Ah get_power_mode
Description
NORON
DSPON
Bit D1 – Reserved
This bit is not applicable. Set to ‘0’. (Not supported)
Bit D0 – Reserved
This bit is not applicable. Set to ‘0’. (Not supported)
X = Don’t care
Restriction -
Flow chart
Note : When this command is read via DSI, dummy read operation is not preformed.
get_address_mode: 0Bh
0Bh get_address_mode
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 0 0 1 0 1 1 0Bh
Dummy
0 1 X X X X X X X X XXh
parameter
1st
1 1 B7 B6 0 B4 B3 0 0 B0 XXh
parameter
Description For B4, B3 and B0, please refer to the Appendix for each mode.
Bit Description Comment Command list
symbol
D7 Page Address Order B7
D6 Column Address Order B6
D5 Page/column Order Set to ‘0’ -
D4 Line Address Order B4
D3 RGB/BGR Order B3
D2 Display Data Latch Order Set to ‘0’. -
D1 Reserved Set to ‘0’. -
D0 Switching between common outputs and frame memory B0
Note : B4, B3 and B0 depand on each Panel Interface mode. See the appendix of each mode.
0Bh get_address_mode
Description
Bit D3 – RGB/BGR Order
For bit D3, see “set_address_mode (36h)” and the appendix data sheet.
Bit D1 – Reserved
This bit is not applicable. Set to ’0’. (Not supported)
X = Don’t care
Restriction -
Flow Chart
Note : When this command is read via DSI, dummy read operation is not preformed.
get_pixel_format: 0Ch
0Ch get_pixel_format
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 0 0 1 1 0 0 0Ch
Dummy
1 1 X X X X X X X X XXh
parameter
1st
1 1 0 D6 D5 D4 0 D2 D2 D0 XXh
parameter
Description This command indicates the current status of the display as described in the table below. This command
setting depends on set_pixel_format (3Ah).
Bit Description Comment
D7 Set to ’0’.
D6 DPI Pixel Format D6
D5 (RGB Interface Color Format) D5
D4 D4
D3 Set to ’0’.
D2 DBI Pixel Format D2
D1 (Control Interface Color Format) D1
D0 D0
Bits D[6:4] – DPI Pixel Format (DSI Video Mode Control Interface Color Format Selection)
Bits D[2:1] – DBI Pixel Format (Control Interface and DSI Command Mode ColorFormat
Selection)
Bits D7 and D3
This bit is not applicable. Set to ‘0’.
0Ch get_pixel_format
Flow chart
Note : When this command is read via DSI, dummy read operation is not preformed.
get_display_mode: 0Dh
0Dh get_display_mode
DCX RDX WRX DB23-8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 X 0 0 0 0 1 1 0 1 0Dh
Dummy
1 1 X X X X X X X X X XXh
parameter
1st
1 1 X 0 0 0 D4 D3 D2 D1 D0 XXh
parameter
Description The display module returns the current status of the display as described in the table below.
Command list
Bit Description Comment
symbol
D7 Vertical Scrolling Status Set to ‘0’.
D6 Horizontal Scrolling Status Set to ‘0’.
D5 Inversion On/Off Set to ‘0’.
D4 All Pixels On
D3 All Pixels Off
D2 Gamma Curve Selection D2
D1 Gamma Curve Selection D1
D0 Gamma Curve Selection D0
X = Don’t care
Restriction -
0Dh get_display_mode
Flow chart
Note : When this command is read via DSI, dummy read operation is not preformed.
get_signal_mode: 0Eh
0Eh get_signal_mode
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 0 0 1 1 1 0 0Eh
Dummy
1 1 X X X X X X X X xxh
parameter
RDD
1st
1 1 TEON TELOM 0 0 0 0 0 SM_ xxh
parameter
D0
Description The display module returns the current status of the display as described in the table below.
Command list
Bit Description Comment
symbol
D7 Tearing Effect Line On/Off TEON
D6 Tearing Effect Line Output Mode TELOM
D5 Reserved Set to ‘0’. -
D4 Reserved Set to ‘0’. -
D3 Reserved Set to ‘0’. -
D2 Reserved Set to ‘0’. -
D1 Reserved Set to ‘0’. -
D0 Errors on DSI RDDSM_D0
X = Don’t care
Restriction -
0Eh get_signal_mode
Flow chart
Note : When this command is read via DSI, dummy read operation is not preformed.
get_diagnostic_result: 0Fh
0Fh get_diagnostic_result
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 0 0 1 1 1 1 0F
Dummy
0 1 X X X X X X X X XXh
parameter
1st 0 1 0 FUNCD 0 0 0 0 0 0 XXh
parameter
Command list
Bit Description Comment
symbol
D7 Register Loading Detection Set to ‘0’. -
D6 Functionality Detection FUNCD
D5 Chip Attachment Detection Set to ‘0’. -
D4 Display Glass Break Detection Set to ‘0’. -
D3 Reserved Set to ‘0’. -
D2 Reserved Set to ‘0’. -
D1 Reserved Set to ‘0’. -
D0 Reserved Set to ‘0’. -
The display module returns the self-diagnostic results following the exit_sleep_mode (11h) as shown in the
table above.
FUNCD
Reserved. Set to 0.
X = Don’t care
Restriction -
0Fh get_diagnostic_result
Flow chart
Note : When this command is read via DSI, dummy read operation is not preformed.
enter_sleep_mode: 10h
10h enter_sleep_mode
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 0 1 0 0 0 0 10h
Parameter None
Description This command causes the LCD module to enter the Sleep mode. In this mode, the DC/DC converter, internal
oscillator and panel scanning stop.
See “State Transition Diagram” for each stage of transition.
X = Don’t care
Restriction This command has no effect when the module is already in Sleep mode. Sleep mode can be exited only
when the exit_sleep_mode (11h) is transmitted.
Sending a new command is prohibited while the RSP LCD driver performs either display off sequence or
power off sequence.
Flow chart
exit_sleep_mode: 11h
11h exit_sleep_mode
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 0 1 0 0 0 1 11h
Parameter None
Description This command causes the display module to exit Sleep mode. The DC/DC converter, internal oscillator,
and panel scanning start.
See “State Transition Diagram” for each stage of transition.
X = Don’t care
Restriction This command shall not cause any visual effect on display device when the display module is not in Sleep
mode.
No new command setting is allowed during power on sequence. Operation may continue due to power on
sequence setting. The host processor needs waittime. (Please refer to the Appendix for waittime.) Do not
send any command either in this case.
The host processor needs waittime after sending an enter_sleep_mode command before sending an
exit_sleep_mode command. (Please refer to the Appendix for waittime.)
The display runs the self-diagnostic function after this command is received.
Flow chart
enter_partial_mode: 12h
12h enter_partial_mode
DCX RDX WRX DB23-8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 X 0 0 0 1 0 0 1 0 12h
Parameter None
Description This command causes the display module to enter the Partial Display Mode. In this mode, LEDPWM and
RGB switch signal for panel stop except display area to achieve low power.
The Partial Display Mode window is described by the set_partial_area command (30h). To leave Partial
Display Mode, the enter_normal_mode (13h) should be written.
X = Don’t care
Note: When a command breaks in the middle of frame period in Normal mode, the command is enabled
from the next frame period.
Restriction This command has no effect when the module is already in Partial mode.
Flow chart See “set_partial_area (30h)”.
enter_normal_mode: 13h
13h enter_normal_mode
DCX RDX WRX DB23-8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 X 0 0 0 1 0 0 1 1 13h
Parameter None
Description This command causes the display module to enter the Normal mode. Normal Mode means Partial mode is
off.
X = Don’t care
Note: When a command breaks in the middle of frame period in Partial mode, that command becomes valid
from the next frame period.
Restriction This command has no effect when Normal mode is already active.
Flow chart See the description of command set_partial_area (30h) when using this command.
set_all_pixels_off: 22h
22h set_all_pixels_off
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 1 0 0 0 1 0 22h
Parameter None
Description This command turns the display panel black in “Sleep Out” mode and a status of the “Display On/Off” register
can be “on“ or “off”.
This command makes no change of contents of frame memory.
This command does not change any other status.
(Example)
Host Processor Display Device
Restriction Setting parameters except the above ones is disabled. A selected gamma curve is not changed until a correct
value is set.
Flow chart
Normal display Legend
Command
set_all_pixels_off Parameter
Display
Black display
Action
Mode
Sequential
transter
set_all_pixels_on: 23h
23h set_all_pixels_on
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 1 0 0 0 1 1 23h
Parameter None
Description This command turns the display panel white in “Sleep Out” mode and a status of the “Display On/Off” register
can be “on“ or “off”.
This command makes no change of contents of frame memory.
This command does not change any other status.
(Example)
Host Processor Display Device
Restriction Setting parameters except the above ones is disabled. A selected gamma curve is not changed until a correct
value is set.
Flow chart
Normal display Legend
Command
set_all_pixels_off Parameter
Display
White display
Action
Mode
Sequential
transter
set_gamma_curve: 26h
26h set_gamma_curve
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 1 0 0 1 1 0 26h
GC GC GC GC GC GC GC GC
Parameter 1 1 XXh
[7] [6] [5] [4] [3] [2] [1] [0]
Description This command selects a gamma curve set beforehand. A gamma curve is selected from four curves according
to image data.
GC[7:0] parameter Selection
1 GC[0] Gamma Curve 1
- GC[7:1] Reserved (Set to”0”)
X=Don’t care
Restriction Setting parameters except the above ones is disabled. A selected gamma curve is not changed until a correct
value is set.
Flow chart
set_display_off: 28h
28h set_display_off
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 1 0 1 0 0 0 28h
Parameter None
Description This command causes the display module to stop displaying image data on the display device.
X = Don’t care
Restriction This command has no effect when the display panel is already off.
Flow chart
set_display_on: 29h
29h set_display_on
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 1 0 1 0 0 1 29h
Parameter None
Description This command causes the display module to start displaying the image data on the display device
X = Don’t care
Restriction This command has no effect when the display panel is already on.
Flow chart
set_column_address: 2Ah
2Ah set_column_address
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 1 0 1 0 1 0 2Ah
1st SC
1 1 0 0 0 0 0 SC[9] SC[8] XXh
parameter [10]
2nd
1 1 SC[7] SC[6] SC[5] SC[4] SC[3] SC[2] SC[1] SC[0] XXh
parameter
3rd EC
1 1 0 0 0 0 0 EC[9] EC[8] XXh
parameter [10]
4th
1 1 EC[7] EC[6] EC[5] EC[4] EC[3] EC[2] EC[1] EC[0] XXh
parameter
Description SC[n:0]
EC[n:0]
This command defines the column extent of the frame memory accessed by the host processor. The
values of SC[n:0] and EC[n:0] are referred when write_memory_start (2Ch) commands are written. No
status bits are changed.
X=Don’t care
Restriction 1.SC [n:0] must be equal to or less than EC[n:0].
2. Set the parameters as follows.
SC[n:0] = 8n ( n = 0, 1, 2, ・・・)
EC[n:0] = 8m - 1 ( m = 1, 2, 3, ・・・)
EC - SC : Refer “Restriction in Using R63419”.
3. The parameters are disregarded in following cases.
SC[n:0] or EC[n:0] > (Column_Address_Max)h
4. The host processor must wait more 15us between the end of write data transfer and this command
5. There is the restriction about EC/SC setting in case of using 2port data transfer.
Refer “Restriction of R63419”.
For the number of bits (n) supported in SC[n:0] and EC[n:0], See “Term Definition.”
X = Don’t care
2Ah set_column_address
Flow chart
set_page_address: 2Bh
2Bh set_page_address
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 1 0 1 0 1 1 2Bh
st
1 SP SP
1 1 0 0 0 0 SP[9] SP[8] XXh
parameter [11] [10]
2nd
1 1 SP[7] SP[6] SP[5] SP[4] SP[3] SP[2] SP[1] SP[0] XXh
parameter
3rd EP EP
1 1 0 0 0 0 EP[9] EP[8] XXh
parameter [11] [10]
4th
1 1 EP[7] EP[6] EP[5] EP[4] EP[3] EP[2] EP[1] EP[0] XXh
parameter
Description SP[n:0]
EP[n:0]
This command defines the page extent of the frame memory accessed by the host processor. The values of
SP[n:0] and EP[n:0] are referred when write_memory_start (2Ch) are written. No status bits are changed.
X=Don’t care
Restriction SP [n:0] must be equal to or less than EP[n:0].
Note: Set the parameters as follows.
SP[n:0] or EP[n:0] > (Row_Address_Max)h
SP[n:0] = 2n (n=0,1,2,…)
EP[n:0] = 2m-1 (m=1,2,3,…)
EP – SP ≧ 2lines
For the number of bits (n) supported in SP[n:0] and EP[n:0], See “Term Definition.”
X = Don’t care
The host processor must wait more 15us between the end of write data transfer and this command.
D7/D0 and D6/D1 flips all display area regardless any window address setting.
2Bh set_page_address
Flow chart
write_memory_start: 2Ch
2Ch write_memory_start
DCX RDX WRX DB23-8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 X 0 0 1 0 1 1 0 0 2Ch
st
1 D1 D1 D1 D1 D1 D1 D1 D1 D1 000h
1 1
pixel data [23:8] [7] [6] [5] [4] [3] [2] [1] [0] …3Fh
Dx Dx Dx Dx Dx Dx Dx Dx Dx 000h
: 1 1
[23:8] [7] [6] [5] [4] [3] [2] [1] [0] …3Fh
Nth Dn Dn Dn Dn Dn Dn Dn Dn Dn 000h
1 1
pixel data [23:8] [7] [6] [5] [4] [3] [2] [1] [0] …3Fh
Description This command transfers image data from the host processor to the display module’s frame memory.
No status bits are changed.
If this command is received, the column and page registers are set to the Start Column (SC) and Start Page
(SP) respectively.
If Frame Memory Access and Interface setting (B3h) WEM = 0:
If the number of pixels in transfer data exceed (EC-SC+1)*(EP-SP+1), the extra pixels are ignored.
If Frame Memory Access and Interface setting (B3h) WEM = 1
When the number of pixels in transfer data exceed (EC-SC+1)*(EP-SP+1), the column register and the page
register are set to the Start Column and Start Page respectively. Then subsequent data are written to the
frame memory. Sending any other command will stop writing to the frame memory.
See “Data Format” for each interface write data format.
X=Don’t care.
Restriction In all color modes, there are no restrictions on the length of parameters.
If data is not transferred in units of multiple of 4, the extra data is regarded as invalid.
The host processor must wait more 40 ByteClock between register setting and this command.
Data lane should send Null packet , Nop command or LP-11 during the wait period.
Note: fByteClock = (1/4) * fDSICLK. fByteClock = frequency of ByteClock.
Flow chart
set_partial_area: 30h
30h set_partial_area
DCX RDX WRX DB23-8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 X 0 0 1 1 0 0 0 0 30h
1st SR SR 000h
1 1 X X X 0 0 SR[9] SR[8]
parameter [11] [10] …
2nd XXX
1 1 X SR[7] SR[6] SR[5] SR[4] SR[3] SR[2] SR[1] SR[0] h
parameter
3rd ER ER 000h
1 1 X X X 0 0 ER[9] ER[8]
parameter [11] [10] …
4th XXX
1 1 X ER[7] ER[6] ER[5] ER[4] ER[3] ER[2] ER[1] ER[0] h
parameter
Description
This command defines the partial mode’s display area. There are 2 parameters associated with this
command, the first defines the Start Row (SR) and the second the End Row (ER), as illustrated in the figures
below. SR and ER refer to the Frame Memory Line Pointer.
30h set_partial_area
Description
When End Row is Start Row, a partial area is a 1-row area. X = Don’t care
Restriction SR[n:0] and ER[n:0] must not be greater than a value set by NL. The bits other than SR[n:0] and ER[n:0] are
“Don’t care”. This function cannot be used in MIPI DPI, MIPI DSI Video mode, and Active Refresh mode, in
which display data is written to RAM without using frame memory. For the number of bits (n) supported in
SR[n:0] and ER[n:0], See “Term Definition.”
Flow chart
set_tear_off: 34h
34h set_tear_off
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 1 1 0 1 0 0 34h
Parameter None
Description This command turns off the Tearing Effect output signal from the TE signal line.
X = Don’t care
Restriction This command has no effect when Tearing Effect output is already off.
Flow chart
set_tear_on: 35h
35h set_tear_on
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 1 1 0 1 0 1 35h
st
1 TELO
1 1 X X X X X X X XXh
parameter M
Description This command turns on the display module’s Tearing Effect output signal on the TE signal line. Changing
B4 (Line Refresh Order of set_address_mode (36h)) does not change this output. The Tearing Effect Line
On has one parameter, TELOM, which describes the Tearing Effect Output Line mode. See “TE Pin Output
Signal” for detail.
set_address_mode: 36h
36h set_address_mode
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 1 1 0 1 1 0 36h
st
1
1 1 B7 B6 0 B4 B3 0 0 B0 XXh
parameter
Description For B7(Video mode), B3 and B0, please see the appendix for each mode.
Bit Description Comment Symbol
D7 Page Address Order B7
D6 Column Address Order B6
D5 Page/Column Addressing Order Set to “0” -
D4 Display Device Line Refresh Order B4
D3 RGB/BGR Order B3
D2 Display Data Latch Data Order Set to “0” -
D1 Flip Horizontal Set to “0” -
D0 Flip Vertical B0
Note : This function is same as B0. See description of UDS(manufacture command :C1h).
SP SP SP SP
B7=0
EP EP EP EP
SC EC SC EC SC EC EC SC
36h set_address_mode
Description
Bit D5 – Page/Column Addressing Order
This bit is not applicable. Set to ‘0’. (Not supported)
X = Don’t care
36h set_address_mode
Restriction Display flips vertical by setting D7 or D0.
D0
0 1
0 Normal display Flip vertical
D7
1 Flip vertical Flip vertical
D7/D0 flips all display area regardless any window address setting.
Flow chart
exit_idle_mode: 38h
38h exit_idle_mode
DCX RDX WRX DB23-8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 ↑ x 0 0 1 1 1 0 0 0 38h
Parameter None
Description This command causes the display module to exit Idle mode. LCD can display up to maximum 16,777,216
colors.
X = Don’t care
Restriction This command has no effect when the display module is not in Idle mode.
Flow chart
enter_idle_mode: 39h
39h enter_idle_mode
DCX RDX WRX DB23-8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 X 0 0 1 1 1 0 0 1 39h
Parameter None
Description This command causes the display modules to enter Idle mode.
In the idle mode, color expression is reduced. Eight color depth data are displayed using MSB of each R, G,
and B color components in the frame memory.
And frequency of RCLK changes for idle mode. Refer “Reference Clock Generating Function “for detail.
39h enter_idle_mode
Flow chart
set_pixel_format: 3Ah
3Ah set_pixel_format
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 0 1 1 1 0 1 0 3Ah
st
1
1 1 0 D6 D5 D4 0 D2 D1 D0 XXh
parameter
Description This command is used to define the format of RGB picture data, which are to be transferred via the interface.
The formats are shown in the following table.
Bit D[6:4] – DPI Pixel Format (Video Mode Control Interface Color Format Selection)
Bit D[2:0] – DBI Pixel Format (Control Interface and DSI Command Mode Color Format
Selection)
Bits D7 and D3
This bit is not applicable. Set to ‘0’. (Not supported)
3Ah set_pixel_format
Flow chart
write_memory_continue: 3Ch
3Ch write_memory_continue
DCX RDX WRX DB23-8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 X 0 0 1 1 1 1 0 0 3Ch
000h
1st D1 D1 D1 D1 D1 D1 D1 D1 D1
1 1 ...
pixel data [23:8] [7] [6] [5] [4] [3] [2] [1] [0]
FFFh
000h
Dx Dx Dx Dx Dx Dx Dx Dx Dx
: 1 1 ...
[23:8] [7] [6] [5] [4] [3] [2] [1] [0]
FFFh
000h
Nth Dn Dn Dn Dn Dn Dn Dn Dn Dn
1 1 ...
pixel data [23:8] [7] [6] [5] [4] [3] [2] [1] [0]
FFFh
Description This command transfers image data from the host processor to the display module’s frame memory
continuing from the pixel location following the previous write_memory_continue or write_memory_start
command.
Frame Memory Access and Interface setting (B3h): WEM = 0
If the number of pixels in the transfer data exceed (EC-SC+1)*(EP-SP+1), the extra pixels are ignored.
Frame Memory Access and Interface setting (B3h): WEM = 1
When the number of pixels in the transfer data exceed (EC-SC+1)*(EP-SP+1), the column register and the
page register are reset to the Start Column/Start Page positions, and the subsequent data are written to the
frame memory.
X=Don’t care
Restriction If write_memory_continue command is executed without setting set_column_address (2Ah),
set_page_address (2Bh), and set_address_mode (36h), there is no guarantee that data are correctly written
to the frame memory. If data is not transferred in units of multiple of 4, the extra data is regarded as invalid.
The host processor must wait more 40 ByteClock between register setting and this command.
Data lane should send Null packet , Nop command or LP-11 during the wait period.
Note: fByteClock = (1/4) * fDSICLK. fByteClock = frequency of ByteClock.
Flow chart
set_tear_scanline:44h
44h set_tear_scanline
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 1 0 0 0 1 0 0 44h
1st STS STS STS STS
1 1 0 0 0 0 0Xh
parameter [11] [10] [9] [8]
2nd STS STS STS STS STS STS STS STS
1 1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
Description This command turns on the display module’s Tearing Effect output signal on the TE signal line when the
display module reaches line N defined by STS [n:0].
TE line is unaffected by change in B4 bit of set_address_mode command.
See figure in “TE Pin Output Signal”.
X = Don’t care.
Restriction The command takes affect on the frame following the current frame. Therefore, if the TE signal is already
ON, TE signal is output according to the old set_tear_on and set_tear_scanline commands until the end of
currently scanned frame.
Setting is disabled when TELOM=1 of set_tear_on (35h).
Make sure that STS [n:0] ≤ NL (number of line) + 1.
For the number of bits (n) supported in STS[n:0], See “Term Definition.”
Flow chart
Write_Display_Brightness: 51h
51h Write_Display_Brigtness
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 1 0 1 0 0 0 1 51h
st
1 DBV DBV DBV DBV DBV DBV DBV DBV
1 1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
Description This command is used to adjust the amount of LED light.
DBV
When the amount of LED light is adjusted externally, PWM signal's width is selected by setting DBV
register. This register setting is enabled when CABC function is off.
DBV[7:0] Amount of light
8’h00 None (0%)
8’h01 1/255
8’h02 2/255
8’h03 3/255
: :
8’hFE 254/255
8’hFF 255/255 (100%)
X = Don’t care
Restriction
Flow chart
Read_Display_Brightness_Value: 52h
52h Read_Display_Brightness_Value
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 1 0 1 0 0 1 0 52h
Dummy
1 1 X X X X X X X X XXh
parameter
RD_D RD_D RD_D RD_D RD_D RD_D RD_D RD_D
1st
1 1 BV BV BV BV BV BV BV BV XXh
parameter
[7] [6] [5] [4] [3] [2] [1] [0]
RD_D RD_D RD_D RD_D
2nd
1 1 BV_L BV_L BV_L BV_L 0 0 0 0 XXh
parameter
[3] [2] [1] [0]
Description This command returns the current brightness value.
RD_DBV[7:0], RD_DBV_L[3:0]
This register returns the brightness data of the LED that is the source of the current LEDPWM signal, whether
the CABC function is on or off.
X = Don’t care
Restriction In Sleep Mode On, this register setting value is disabled.
Flow chart
Note : When this command is read via DSI, dummy read operation is not preformed.
Write_Control_Display: 53h
53h Write_Control_Display
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 1 0 1 0 0 1 1 53h
st
1 BCTR
1 1 X X X DD BL X X XXh
parameter L
Description This command is used to control the CABC function. Set each register only in Sleep Mode On. Do not
change the setting during operation.
BCTRL
The register is used to enable LEDPWM pin output. Set to 0 in a system configuration without the
LEDPWM pin. Set to 1 in a system configuration with the LEDPWM pin.
DD
This register is used to enable / disable PWM's dimming function. The register is used to control change in
brightness (change in PWM signal) when DBV register is rewritten or LEDPWM pin is turned on. This bit is
applied to DBV register setting and not to brightness change by the CABC function.
DD Dimming function Brightness change
0 Off Changes immediately.
1 On Changes about PWM_DIV
setting.
BL
This register controls on/off of the LEDPWM signal output. Note that LEDPWM is off in sleep mode
regardless of BL value.
BL LEDPWM signal output
0 Off
1 On
X = Don’t care
Restriction
Flow chart
Read_Control_Value_Display: 54h
54h Read_Control_Value_Display
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 1 0 1 0 1 0 0 54h
Dummy
1 1 X X X X X X X X XXh
parameter
1st
1 1 X X BCTRL X DD BL X X XXh
parameter
Description This command indicates the current status of the CABC function set by write_control_display (53h) as
follows.
BCTRL
This register controls on/off of the LEDPWM signal output.
Note that LEDPWM is off in sleep mode regardless of BL value.
DD
This register is used to enable / disable LEDPWM's dimming function.
DD Dimming function Brightness change
0 Off Changes immediately.
1 On Changes about PWM_DIV setting.
BL
The register is used to enable LEDPWM pin output.
BL LEDPWM signal output
0 Off system configuration without the LEDPWM pin.
1 On system configuration with the LEDPWM pin.
X = Don’t care
Restriction
Flow chart
Note : When this command is read via DSI, dummy read operation is not preformed.
Write_Content_Adaptive_Brightness_Control: 55h
55h Write_Content_Adaptive_Brightness_Control
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 1 0 1 0 1 0 1 55h
st
1 LOCAL SRE
1 1 SRE[1] SRE[0] X X C[1] C[0] XXh
parameter _ON _ON
Description This command is used to control the CABC and the SRE function. Set each register only in Sleep Mode
On. Do not change the setting during operation.
C[1:0]
The CABC function adjusts backlight brightness dynamically and processes image. This register can select
one mode from three according to image data.
C[1] C[0] Function
0 0 Off
0 1 User interface image
1 0 Still image
1 1 Video image
SRE_ON
This register is used to enable / disable the SRE function.
SRE_ON SRE function
0 Off
1 On
SRE[1:0]
This register can select one mode from three setting.
SRE[1] SRE[0] Function
0 0 User Setting
0 1 Weak setting
1 0 Middle setting
1 1 Strong setting
LOCAL_ON
This register is used to enable / disable the Local Area ACO function.
LOCAL_ON Local Area ACO function
0 Off
1 On
X = Don’t care
Restriction -
Flow chart
Read_Content_Adaptive_Brightness_Control: 56h
56h Read_Content_Adaptive_Brightness_Control
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 1 0 1 0 1 1 0 56h
Dummy
1 1 X X X X X X X X XXh
parameter
1st LOCA SRE_ SRE SRE
1 1 X X C[1] C[0] XXh
parameter L_ON ON [1] [0]
Description This command indicates the current mode set by write_content_adaptive_brightness_control (55h) as
follows.
C[1:0]
The CABC function adjusts backlight brightness dynamically and processes image. This register can select
one mode from three according to image data.
C[1] C[0] Function
0 0 Off
0 1 User interface image
1 0 Still image
1 1 Video image
SRE_ON
This register is used to enable / disable the SRE function.
SRE_ON SRE function
0 Off
1 On
SRE[1:0]
This register can select one mode from three setting.
SRE[1] SRE[0] Function
0 0 User Setting
0 1 Weak setting
1 0 Middle setting
1 1 Strong setting
LOCAL_ON
This register is used to enable / disable the Local Area ACO function.
LOCAL_ON Local Area ACO function
0 Off
1 On
X = Don’t care
Restriction -
Flow chart
Note : When this command is read via DSI, dummy read operation is not preformed.
Write_CABC_Minimum_Brightness: 5Eh
5Eh Write_CABC_Minimum_Brightness
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 1 0 1 1 1 1 0 5Eh
st
1 CMB CMB CMB CMB CMB CMB CMB CMB
1 1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
Description This command is used to adjust the brightness of the CABC function.
CMB
When the CABC function is used, minimum brightness data is set by setting CMB register. This register
setting value is enabled when the CABC function is on.
CMB[7:0] Amount of light
8’h00 None (0%)
8’h01 1/255
8’h02 2/255
8’h03 3/255
: :
8’hFE 254/255
8’hFF 255/255 (100%)
X = Don’t care
Restriction
Flow chart
Read_CABC_Minimum_Brightness: 5Fh
5Fh Read_CABC_Minimum_Brightness
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 ↑ 0 1 0 1 1 1 1 1 5Fh
Dummy
1 1 X X X X X X X X XXh
parameter
1st CMB CMB CMB CMB CMB CMB CMB CMB
1 1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
2nd
1 1 0 0 0 0 0 0 0 0 XXh
parameter
Description This command returns the current minimum brightness value of the CABC function.
CMB
This register returns the minimum brightness data of the CABC function.
X = Don’t care
Restriction -
Flow chart
Note : When this command is read via DSI, dummy read operation is not preformed.
Read_Automatic_Brightness_Control_Self_Diagnostic_Result: 68h
68h Read_Automatic_Brightness_Control_Self_Diagnostic_Result
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 0 1 1 0 1 0 0 0 68h
Dummy
1 1 X X X X X X X X XXh
parameter
1st 1 1 0 FUNCD 0 0 0 0 0 0 XXh
parameter
Command list
Bit Description Comment
symbol
D7 Register Loading Detection Set to ‘0’. -
D6 Functionality Detection FUNCD
D5 Chip Attachment Detection Set to ‘0’. -
D4 Display Glass Break Detection Set to ‘0’. -
D3 Reserved Set to ‘0’. -
D2 Reserved Set to ‘0’. -
D1 Reserved Set to ‘0’. -
D0 Reserved Set to ‘0’. -
The display module returns the self-diagnostic results following the exit_sleep_mode (11h) as shown in the
table above.
FUNCD
Reserved. Set to 0.
X = Don’t care
Restriction -
68h Read_Automatic_Brightness_Control_Self_Diagnostic_Result
Legend
read_automatic_
Command
brightness_control_
self_diagnostic_result Parameter
Host
Sequential
transfer
Note : When this command is read via DSI, dummy read operation is not preformed.
read_Black/White_Low_Bit: 70h
70h read_Black/White_Low_Bit
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 ↑ 0 1 1 1 0 0 0 0 70h
Dummy
1 1 X X X X X X X X XXh
parameter
1st Bkx Bkx Bky Bky Wx Wx Wy Wy
1 1 XXh
parameter [1] [0] [1] [0] [1] [0] [1] [0]
Description This command returns the lowest bits of black and white color characteristics.
Black : Bkx and Bky
White : Wx and Wy
X = Don’t care
Note : When this command is read via DSI, dummy read operation is not performed.
Restriction -
read_Bkx: 71h
71h read_Bkx
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 ↑ 0 1 1 1 0 0 0 1 71h
Dummy
1 1 X X X X X X X X XXh
parameter
1st Bkx Bkx Bkx Bkx Bkx Bkx Bkx Bkx
1 1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Bkx[9:2] of black color characteristics.
X = Don’t care
Note : When this command is read via DSI, dummy read operation is not performed.
Restriction -
read_Bky: 72h
72h read_Bky
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 ↑ 0 1 1 1 0 0 1 0 72h
Dummy
1 1 X X X X X X X X XXh
parameter
1st Bky Bky Bky Bky Bky Bky Bky Bky
1 1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Bky[9:2] of black color characteristics.
X = Don’t care
Note : When this command is read via DSI, dummy read operation is not performed.
Restriction -
read_Wx: 73h
73h read_Wx
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 ↑ 0 1 1 1 0 0 1 1 73h
Dummy
1 1 X X X X X X X X XXh
parameter
1st Wx Wx Wx Wx Wx Wx Wx Wx
1 1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Wx[9:2] of white color characteristics.
X = Don’t care
Note : When this command is read via DSI, dummy read operation is not performed.
Restriction -
read_Wy: 74h
74h read_Wy
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 ↑ 0 1 1 1 0 1 0 0 74h
Dummy
1 1 X X X X X X X X XXh
parameter
1st Wy Wy Wy Wy Wy Wy Wy Wy
1 1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Wy[9:2] of white color characteristics.
X = Don’t care
Note : When this command is read via DSI, dummy read operation is not performed.
Restriction -
read_Red/Green_Low_Bit: 75h
75h read_Red/Green_Low_Bit
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 ↑ 0 1 1 1 0 1 0 1 75h
Dummy
1 1 X X X X X X X X XXh
parameter
1st Rx Rx Ry Ry Gx Gx Gy Gy
1 1 XXh
parameter [1] [0] [1] [0] [1] [0] [1] [0]
Description This command returns the lowest bits of red and green color characteristics.
Red : Rx and Ry
Green : Gx and Gy
X = Don’t care
Note : When this command is read via DSI, dummy read operation is not performed.
Restriction -
read_Rx: 76h
76h read_Rx
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 ↑ 0 1 1 1 0 1 1 0 76h
Dummy
1 1 X X X X X X X X XXh
parameter
1st Rx Rx Rx Rx Rx Rx Rx Rx
1 1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Rx[9:2] of red color characteristics.
X = Don’t care
Note : When this command is read via DSI, dummy read operation is not performed.
Restriction -
read_Ry: 77h
77h read_Ry
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 ↑ 0 1 1 1 0 1 1 1 77h
Dummy
1 1 X X X X X X X X XXh
parameter
1st Ry Ry Ry Ry Ry Ry Ry Ry
1 1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Ry[9:2] of red color characteristics.
X = Don’t care
Note : When this command is read via DSI, dummy read operation is not performed.
Restriction -
read_Gx: 78h
78h read_Gx
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 ↑ 0 1 1 1 1 0 0 0 78h
Dummy
1 1 X X X X X X X X XXh
parameter
1st Gx Gx Gx Gx Gx Gx Gx Gx
1 1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Gx[9:2] of green color characteristics.
X = Don’t care
Note : When this command is read via DSI, dummy read operation is not performed.
Restriction -
read_Gy: 79h
79h read_Gy
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 ↑ 0 1 1 1 1 0 0 1 79h
Dummy
1 1 X X X X X X X X XXh
parameter
1st Gy Gy Gy Gy Gy Gy Gy Gy
1 1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Gy[9:2] of green color characteristics.
X = Don’t care
Note : When this command is read via DSI, dummy read operation is not performed.
Restriction -
read_Blue/Acolor_Low_Bit: 7Ah
7Ah read_Blue/Acolor_Low_Bit
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 ↑ 0 1 1 1 1 1 0 0 7Ah
Dummy
1 1 X X X X X X X X XXh
parameter
1st Bx Bx By By Ax Ax Ay Ay
1 1 XXh
parameter [1] [0] [1] [0] [1] [0] [1] [0]
Description This command returns the lowest bits of blue and A color characteristics.
Blue : Bx and By
A : Ax and Ay
X = Don’t care
Note : When this command is read via DSI, dummy read operation is not performed.
Restriction -
read_Bx: 7Bh
7Bh read_Bx
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 ↑ 0 1 1 1 1 0 1 1 7Bh
Dummy
1 1 X X X X X X X X XXh
parameter
1st Bx Bx Bx Bx Bx Bx Bx Bx
1 1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Bx[9:2] of blue color characteristics.
X = Don’t care
Note : When this command is read via DSI, dummy read operation is not performed.
Restriction -
read_By: 7Ch
7Ch read_By
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 ↑ 0 1 1 1 1 1 0 0 7Ch
Dummy
1 1 X X X X X X X X XXh
parameter
1st By By By By By By By By
1 1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the By[9:2] of blue color characteristics.
X = Don’t care
Note : When this command is read via DSI, dummy read operation is not performed.
Restriction -
read_Ax: 7Dh
7Dh read_Ax
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 ↑ 0 1 1 1 1 1 0 1 7Dh
Dummy
1 1 X X X X X X X X XXh
parameter
1st Ax Ax Ax Ax Ax Ax Ax Ax
1 1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Ax[9:2] of A color characteristics.
X = Don’t care
Note : When this command is read via DSI, dummy read operation is not performed.
Restriction -
read_Ay: 7Eh
7Eh read_Ay
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 ↑ 0 1 1 1 1 1 1 0 7Eh
Dummy
1 1 X X X X X X X X XXh
parameter
1st Ay Ay Ay Ay Ay Ay Ay Ay
1 1 XXh
parameter [9] [8] [7] [6] [5] [4] [3] [2]
Description This command returns the Ay[9:2] of A color characteristics.
X = Don’t care
Note : When this command is read via DSI, dummy read operation is not performed.
Restriction -
read_DDB_start: A1h
A1h read_DDB_start
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 1 0 1 0 0 0 0 1 A1h
Dummy
1 1 X X X X X X X X xxh
parameter
1st ID1 ID1 ID1 ID1 ID1 ID1 ID1 ID1
1 1 XXh
parameter [15] [14] [13] [12] [11] [10] [9] [8]
2nd ID1 ID1 ID1 ID1 ID1 ID1 ID1 ID1
1 1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
3rd ID2 ID2 ID2 ID2 ID2 ID2 ID2 ID2
1 1 XXh
parameter [15] [14] [13] [12] [11] [10] [9] [8]
4th ID2 ID2 ID2 ID2 ID2 ID2 ID2 ID2
1 1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
5th ID3 ID3 ID3 ID3 ID3 ID3 ID3 ID3
1 1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
6th ID4 ID4 ID4 ID4 ID4 ID4 ID4 ID4
1 1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
7th - 14th
1 1 X X X X X X X X XXh
parameter
15th
1 1 1 1 1 1 1 1 1 1 FFh
parameter
Description ID1[15:0]
ID2[15:0]
ID3[7:0]
ID4[7:0]
A1h read_DDB_start
read_DDB_start Legend
Host Command
RSP LCD driver
Dummy Read Parameter
Display
1st parameter ID1[15:8]
(MS byte of Supplier ID) Action
Mode
2nd parameter ID1[7:0]
(LS byte of Supplier ID)
Sequential
transfer
Note : When this command is read via DSI dummy read operation is not preformed.
read_DDB_continue: A8h
A8h read_DDB_continue
DCX RDX WRX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
Command 0 1 1 0 1 0 1 0 0 0 A8h
Dummy
1 1 X X X X X X X X xxh
parameter
1st DDB0 DDB0 DDB0 DDB0 DDB0 DDB0 DDB0 DDB0
1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
DDBx DDBx DDBx DDBx DDBx DDBx DDBx DDBx
: 1 XXh
[7] [6] [5] [4] [3] [2] [1] [0]
Nth
1 1 1 1 1 1 1 1 1 1 FFh
parameter
Description This command continues read operation from the position where the operation is halted by
read_DDB_continue or read_DDB_start. For the position that information is returned, see read_DDB_start
(A1h).
X=Don’t care
Restriction To fix the position that information is returned, execute read_DDB_start command and parameter read
operation at least once before read_DDB_continue command is executed. If they are not executed, the
value returned by read_DDB_continue command is invalid.
[When MIPI DSI is selected]
To fix the position that information is returned, execute read_DDB_start command at least once and
parameter read operation at least once before read_DDB_continue command is executed. Otherwise, data
read with a read_DDB_continue command is undefined.
Note: When this command is read via DSI , dummy read operation is not performed.
A8h read_DDB_continue
read_DDB_start Legend
Host
Command
RSP LCD driver
Parameter
Dummy Read
Display
Sequential
transfer
Note : When this command is read via DSI, dummy read operation is not preformed.
read_ID1: DAh
DAh read_ID1
DC RD WR
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
X X X
Command 0 1 1 1 0 1 1 0 1 0 DAh
Dummy
1 1 X X X X X X X X XXh
parameter
1st RD ID1 RD ID1 RD ID1 RD ID1 RD ID1 RD ID1 RD ID1 RD ID1
1 1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
Description RDID1[7:0]
read_ID2: DBh
DBh read_ID2
DC RD WR
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
X X X
Command 0 1 1 1 0 1 1 0 1 1 DBh
Dummy
1 1 X X X X X X X X XXh
parameter
1st RD ID2 RD ID2 RD ID2 RD ID2 RD ID2 RD ID2 RD ID2 RD ID2
1 1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
Description RDID2[7:0]
read_ID3: DCh
DCh read_ID3
DC RD WR
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
X X X
Command 0 1 1 1 0 1 1 1 0 0 DCh
Dummy
1 1 X X X X X X X X XXh
parameter
1st RD ID3 RD ID3 RD ID3 RD ID3 RD ID3 RD ID3 RD ID3 RD ID3
1 1 XXh
parameter [7] [6] [5] [4] [3] [2] [1] [0]
Description RDID3[7:0]
idlemode_BL_control: E1h
E1h idlemode_BL_control
DC RD WR
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
X X X
Command 0 1 1 1 1 0 0 0 0 1 E1h
IDLE_
IDLE_
1st MODE_
BL 1 0 0 PWM_ 0 0 0 0 XXh
parameter BL_
EN
EN
Description The content of the register idlemode_BL_control will define the functionality of the transmissive LCD display backlight
behavior in idle mode which is enabled by enter_idle_mode command. In this mode, the backlight power consumption
will be reduced.
Bit D5 – IDLE_PWM_EN
This bit is not applicable. Set to ‘0’. (Not supported)
Bit D0 – IDLE_MODE_BL_EN
This bit is not applicable. Set to ‘0’. (Not supported)
X = Don’t care
Restriction -
read_idlemode_BL_control: E2h
E2h read_idlemode_BL_control
DC RD WR
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex
X X X
Command 0 1 1 1 1 0 0 0 0 1 E2h
Dummy
1 1 X X X X X X X X XXh
parameter
IDLE_
IDLE_
1st MODE_
BL 1 0 0 PWM_ 0 0 0 0 XXh
parameter BL_
EN
EN
Description This command returns the current state of the register idlemode_BL_control.
Bit D5 – IDLE_PWM_EN
If entering idle_mode, this bit is ’1’.
Bit D0 – IDLE_MODE_BL_EN
This bit is not applicable. Set to ’0’. (Not supported)
X = Don’t care
Note : When this command is read via DSI, dummy read operation is not preformed.
Restriction -
Manufacturer Command
MCAP
Description
This register controls access protect of MCS(Manufacturer command Set).
Function Table
MCAP
Command 3
0 1 2 4 other
(default)
Restriction
The all MCS read data in Access Protect On (“No”, “Fixed” in above function table) is “0”.
(Excluding Device Code Read(ALMIDx)).
DSTB
Description
This register controls Deep Standby mode.
Function Table
DSTB Deep Standby mode
0 off
1 on
Restriction
・In enter_sleep_mode only, DSTB can set to 1.
・If read data of BFh/5th parameter is 00h, this command is not supported. Please use RESX=L to
enter deep standby mode..
RM, DM
Description
These registers control display interface.
Function Table
Display control
Display Display data
RM DM Input data Display CABC
interface mode path VSYNC HSYNC
Clock PWM
Command
‘h0 Command RAM->Source Register Register OSC OSC
mode
‘h0 Video through
‘h1 Video Video->Source DSI DSI OSC OSC
mode
‘h2-‘h7 Setting inhibit
‘h0-2 Setting inhibit
Video RAM
‘h1 Video Video->Source DSI DSI OSC OSC
capture mode
‘h1 ‘h2 Setting inhibit
Video to RAM
‘h3 Video RAM->Source DSI Register OSC OSC
mode
‘h4-7 Setting inhibit
Video Video
mode mode
Video Video
mode mode
Restriction
When DM register is changed, please follow a display mode change sequence.
Please input display clock of each interface before sending exit_sleep_mode command.
When using Video to RAM mode, keep following restriction.
Frame rate > BP+NL+FP
V2CRM
Description
This register controls video data capture operation at last frame when display interface is switched
from video mode to command mode by DM register. Refer to “Display mode” for detail.
Function Table
V2CRM Video capture at last frame
‘h0 Disable
‘h1 Enable
Restriction -
WEM
Description
This register controls addressing when memory access reaches to end of window address.
Function Table
Restriction
The host processor must wait more 15us between the end of write data transfer and this command.
TEI
Description
This register controls interval of TE output frame.
Please adjust the value fitted pixel data refresh rate and data transfer rate.
Function Table
TEI Interval of TE signal output
‘h0 Every frame
‘h1 2 frame
‘h2 Setting inhibit
‘h3 4 frame
‘h4 Setting inhibit
‘h5 6 frame
‘h6 Setting inhibit
‘h7 Setting inhibit
Restriction -
EPF
Description
This register controls data format of 18bpp(R,G,B)→24bpp(r,g,b) expansion when data are stored
to internal memory(24bpp).
Function Table
< 24bpp Frame Memory >
set_pixel_format = 18bpp
EPF 18bpp(R,G,B)→24bpp(r,g,b) set_pixel_format = 24bpp
expansion
Set “0” to lower bit
r[7:0]={ R[5:0], 2’h0 }
g[7:0]={ G[5:0], 2’h0 }
’h0 b[7:0]={ B[5:0], 2’h0 }
Exception :
R[5:0], G[5:0],B[5:0]=6’h3F
→ r[7:0],g[7:0],b[7:0]=8’hFF
Set “1” to lower bit r[7:0] = { R[7:0] }
r[7:0]={ R[5:0], 2’h3 } g[7:0] = { G[7:0] }
g[7:0]={ G[5:0], 2’h3 } b[7:0] = { B[7:0] }
’h1 b[7:0]={ B[5:0], 2’h3 }
Exception :
R[5:0], G[5:0],B[5:0]=6’h00
→ r[7:0],g[7:0],b[7:0]=8’h00
Set upper bit data to lower bit
r[7:0]={ R[5:0], R[5:4] }
’h2
g[7:0]={ G[5:0], G[5:4] }
b[7:0]={ B[5:0], B[5:4] }
’h3-7 Setting inhibit Setting inhibit
Restriction -
EPFV
Description
This register controls data format of 18bpp(R,G,B)→24bpp(r,g,b) expansion in video mode.
Function Table
< 24bpp Gray Scale(video mode) >
set_pixel_format = 18bpp
EPFV set_pixel_format = 24bpp
18bpp(R,G,B)→24bpp(r,g,b) expansion
Set “0” to lower bit
r[7:0]={ R[5:0], 2’h0 }
g[7:0]={ G[5:0], 2’h0 }
’h0 b[7:0]={ B[5:0], 2’h0 }
Exception :
R[5:0], G[5:0],B[5:0]=6’h3F
→ r[7:0],g[7:0],b[7:0]=8’hFF
Set “1” to lower bit
r[7:0] = { R[7:0] }
r[7:0]={ R[5:0], 2’h3 }
g[7:0] = { G[7:0] }
g[7:0]={ G[5:0], 2’h3 }
b[7:0] = { B[7:0] }
’h1 b[7:0]={ B[5:0], 2’h3 }
Exception :
R[5:0], G[5:0],B[5:0]=6’h00
→ r[7:0],g[7:0],b[7:0]=8’h00
Set upper bit data to lower bit
r[7:0]={ R[5:0], R[5:4] }
’h2
g[7:0]={ G[5:0], G[5:4] }
b[7:0]={ B[5:0], B[5:4] }
’h3-7 Setting inhibit Setting inhibit
Restriction -
DSIVCA
Description
This register controls DSI virtual channel of PortA setting.
The corresponding packets to DSIVCA[1:0] are acceptable.
Function Table
DSIVCA Configuration
‘h0 VC=00
‘h1 VC=01
‘h2 VC=10
‘h3 VC=11
Restriction
Initial value(without writing to NVM) is “0”.
If changing DSIVCA value, please use excluding DSI PortA I/F and write the setting to NVM.
DSIVCB
Description
This register controls DSI virtual channel of PortB setting.
The corresponding packets to DSIVCB[1:0] are acceptable.
Function Table
DSIVCB Configuration
‘h0 VC=00
‘h1 VC=01
‘h2 VC=10
‘h3 VC=11
Restriction
Initial value(without writing to NVM) is “0”.
If changing DSIVCB value, please use excluding DSI PortB I/F and write the setting to NVM.
DSICSOUTA
Description
The value of Checksum Error count is read out.
Checksum Error count is count up when Checksum Error occurs at receiving DSI Long Packet
This register is cleared to 0 after read out and soft reset. (only operating DSI PortA I/F)
Function Table -
Restriction
The clear operation at DSICSOUTA read out is executed only selected DSI PortA I/F.
Other I/F can read this register’s value. (Zero value is returned in case of using other I/F.)
DSICSOUTB
Description
The value of Checksum Error count is read out.
Checksum Error count is count up when Checksum Error occurs at receiving DSI Long Packet
This register is cleared to 0 after read out and soft reset. (only operating DSI PortB I/F)
Function Table -
Restriction
The clear operation at DSICSOUTB read out is executed only selected DSI PortB I/F.
Other I/F can read this register’s value. (Zero value is returned in case of using other I/F.)
DSIECPA
Description
The value of single ECC Error count is read out. Single bit ECC Error count is count up when 1bit
ECC Error occurs at receiving、DSI Packet Header.
This register is clear to 0 after read out and soft reset. (only operating DSI PortA I/F)
Function Table -
Restriction
The clear operation at DSIECPA read out is executed only selected DSI PortA I/F.
Other I/F cannot read this register’s value.(Zero value is kept in case of using other I/F.)
DSIECPB
Description
The value of single ECC Error count is read out. Single bit ECC Error count is count up when 1bit
ECC Error occurs at receiving、DSI Packet Header.
This register is clear to 0 after read out and soft reset. (only operating DSI PortB I/F)
Function Table -
Restriction
The clear operation at DSIECPB read out is executed only selected DSI PortB I/F.
Other I/F cannot read this register’s value.(Zero value is kept in case of using other I/F.)
DSIECEA
Description
The value of Multi bits ECC Error count is read out. Multi bits ECC Error count is count up when
2bit or more ECC Error occurs at receiving、DSI Packet Header.
This register is clear to 0 after read out and soft reset. (only operating DSI PortA I/F)
Function Table -
Restriction
The clear operation at DSIECEA read out is executed only selected DSI PortA I/F.
Other I/F cannot read this register’s value.(Zero value is kept in case of using other I/F.)
DSIECEB
Description
The value of Multi bits ECC Error count is read out. Multi bits ECC Error count is count up when
2bit or more ECC Error occurs at receiving、DSI Packet Header.
This register is clear to 0 after read out and soft reset. (only operating DSI PortB I/F)
Function Table -
Restriction
The clear operation at DSIECEB read out is executed only selected DSI PortB I/F.
Other I/F cannot read this register’s value.(Zero value is kept in case of using other me /F.)
DSITXDIV
Description
This register controls the DSICLK dividing ratio for LP mode data transmission.
In case of stopping DSICLK, internal OSC is selected for data transmission clock instead of
DSICLK. Refer “Electrical characteristics” about OSC frequency.
Function Table
DSITXDIV DSICLK dividing ratio
’b00 fDSICLK/8
‘b01 fDSICLK/16
‘b10 fDSICLK/24 (default)
’b11 fDSICLK/32
Configuration of DSITXDIV
Host to DriverIC DriverIC to Host
fTXCLK
Status of Clock Lane Bit Rate fDSICLK Setting of DSITXDIV Bit rate
(=1/TLPTX)
[Mbps] [MHz] (example) [Mbps]
[MHz]
Active ’b11
1000 500 15.63 7.81
950 475 ’b10 19.79 9.90
900 450 18.75 9.38
850 425 17.71 8.85
800 400 16.67 8.33
750 375 15.63 7.81
700 350 14.58 7.29
650 325 13.54 6.77
600 300 ’b01 18.75 9.38
550 275 17.19 8.59
500 250 15.63 7.81
450 225 14.06 7.03
400 200 12.50 6.25
350 175 10.94 5.47
300 150 ’b00 18.75 9.38
250 125 15.63 7.81
200 100 12.50 6.25
Inactive - - -
fOSCCLK/4 fTXCLK/2
(Stop)
Restriction -
DSI_THSSET
Description
This register controls MIPI-DSI DPHY operating frequency.
Please set the suitable value for tHS-PREPARE and tHS-PREPARE+tHS-ZERO.
Function Table
DSI DPHY operating frequency
DSI_THSSET
Min Max
‘h0 100Mbps 180Mbps
‘h1 180Mbps 280Mbps
‘h2 280Mbps 420Mbps
‘h3 420Mbps 590Mbps
‘h4 590Mbps 740Mbps
‘h5 740Mbps 1000Mbps
‘h6 Reserved Reserved
‘h7 Reserved Reserved
Restriction -
ERR_CNT_RST
Description
This register resets a DSI error count.
Function Table
ERR_CNT_RST DSI Error count
0 Not clear
1 0 clear
Restriction
After resetting an error count by ERR_CNT_RST=1, it returns to ERR_CNT_RST=0.
ALMID0
Description
Upper 8bit of Supplier ID can read by accessing this register.
Function Table
D7 D6 D5 D4 D3 D2 D1 D0 HEX
ALMID0 ALMID0 ALMID0 ALMID0 ALMID0 ALMID0 ALMID0 ALMID0
parameter
[7] [6] [5] [4] [3] [2] [1] [0]
Register
0 0 0 0 0 0 0 1 01h
init
Restriction
ALMID0 can be reading at all MCAP protect level.
ALMID1
Description
Lower 8bit of Supplier ID can read by accessing this register.
Function Table
D7 D6 D5 D4 D3 D2 D1 D0 HEX
parameter ALMID1 ALMID1 ALMID1 ALMID1 ALMID1 ALMID1 ALMID1 ALMID1
[7] [6] [5] [4] [3] [2] [1] [0]
Register 0 0 1 0 0 0 1 0 22h
init
Restriction
ALMID1 can be reading at all MCAP protect level.
ALMID2
Description
Upper 8bit of IC part number can read by accessing this register.
Function Table
D7 D6 D5 D4 D3 D2 D1 D0 HEX
ALMID2 ALMID2 ALMID2 ALMID2 ALMID2 ALMID2 ALMID2 ALMID2
parameter
[7] [6] [5] [4] [3] [2] [1] [0]
Register
0 0 1 1 0 1 0 0 34h
init
Restriction
ALMID2 can be reading at all MCAP protect level.
ALMID3
Description
Lower 8bit of IC part number can read by accessing this register.
Function Table
D7 D6 D5 D4 D3 D2 D1 D0 HEX
ALMID3 ALMID3 ALMID3 ALMID3 ALMID3 ALMID3 ALMID3 ALMID3
parameter
[7] [6] [5] [4] [3] [2] [1] [0]
Register
0 0 0 1 1 0 0 1 19h
init
Restriction
ALMID3 can be reading at all MCAP protect level.
SOUTTR1/2/3/4/5/6, SOUTTF1/2/3/4/5/6
Description
These registers set s Driving ability(Tr/Tf)
SOUTTR1, SOUTTF1: sets a Driving ability(Tr/Tf) SOUT14,15,16
SOUTTR2, SOUTTF2: sets a Driving ability(Tr/Tf) SOUT17,18,19
SOUTTR3, SOUTTF3: sets a Driving ability(Tr/Tf) SOUT1,2,3,4,5,6,7,8
SOUTTR4, SOUTTF4: sets a Driving ability(Tr/Tf) SOUT25,26,27,28,29,30,31,32
SOUTTR5, SOUTTF5: sets a Driving ability(Tr/Tf) SOUT9,10,11,12,13
SOUTTR6, SOUTTF6: sets a Driving ability(Tr/Tf) SOUT20,21,22,23,24
Function Table
Driving
SOUTTR1/2/3/4/5/6 SOUTTF1/2/3/4/5/6 Driving ability(Tf)
ability(Tr)
‘h00 100% ‘h0 100%
‘h01 67% ‘h1 67%
‘h02 33% ‘h2 33%
‘h03 17% ‘h3 17%
SOUTTR1/2/3/4/5/6
SOUTTR1/2 SOUTTF1/2/3/4/5/6
SOUTTF1/2
100% 100%
67% 67%
33% 33%
17% 17%
26th
1 ↑ ↑ 0 DSPODR5[2] DSPODR5[1] DSPODR5[0] 0 DSPODR4[2] DSPODR4[1] DSPODR4[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
27th
1 ↑ ↑ 0 DSPODR7[2] DSPODR7[1] DSPODR7[0] 0 DSPODR6[2] DSPODR6[1] DSPODR6[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
28th
1 ↑ ↑ 0 0 SPCON[1] SPCON[0] 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
29th
1 ↑ ↑ 0 BLGCK BLPSW[1] BLPSW[0] 0 0 1 0 xx
parameter
Register init - - - 0 0 0 0 0 0 1 0 02
30th
1 ↑ ↑ FDBS_SW[2] FDBS_SW[1] FDBS_SW[0] 0 0 FDBS[2] FDBS[1] FDBS[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
31th
1 ↑ ↑ HIZ_CANCEL 0 1 BLSOUT1[4] BLSOUT1[3] BLSOUT1[2] BLSOUT1[1] BLSOUT1[0] xx
parameter
Register init - - - 0 0 1 0 0 0 0 0 20
32th
1 ↑ ↑ 0 0 0 0 BLSOUT2[3] BLSOUT2[2] BLSOUT2[1] BLSOUT2[0] xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
33th
1 ↑ ↑ 0 0 0 0 0 0 0 0 xx
parameter
Register init - - - 0 0 0 0 0 0 0 0 00
34th
1 ↑ ↑ 0 0 0 0 0 0 0 1 xx
parameter
Register init - - - 0 0 0 0 0 0 0 1 01
35th
1 ↑ ↑ ABSI[1] ABSI[0] 0 1 0 0 0 1 xx
parameter
Register init - - - 0 0 0 1 0 0 0 1 11
SS1
Description
This register controls output shift direction of source driver.
Register’s value reflects when data are written to line buffer.
Function Table
Source output direction
SS1 BGR1=0 BGR1=1
S1→Sn S1→Sn
0
“R”,”G”,”B” “B”,”G”,”R”
Sn→S1 Sn→S1
1
“R”,”G”,”B” “B”,”G”,”R”
Restriction About relationship between 36h command, SS1 command and PNSLV pin,
refer to “System Configuration for Dual MIPI-DSI Ports”.
BGR1
Description
This register controls data order when display data are written to line buffer.
Please set the suitable value of color filter.
Function Table
BGR1 Order of RGB data when data are written to line buffer
0 (R) (G) (B) → (R) (G) (B)
1 (R) (G) (B) → (B) (G) (R)
Restriction -
REV
Description
This register controls source output level of display period in Normal/Partial/Idle mode.
And this register defines the relation of display data and source level.
Function Table
<Column/Dot inversion>
Source output level in display period
REV Image Data
Positive polarity Negative polarity
24’h000000 V255P V255N
0 : : :
24’hFFFFFF V0P V0N
24’h000000 V0P V0N
1 : : :
24’hFFFFFF V255P V255N
Restriction -
PTLREV
Description
This register controls source output level of non-display period.
Function Table
<Column/Dot inversion>
Source output level of non-display period Source Amp. operation in
PTLREV
Positive polarity Negative polarity non-display period
0 VP255 VN255 ON
1 VP0 VN0 ON
Restriction -
BLREV, BLS
Description
This register controls source output level of blank period in Normal/Partial mode.
Function Table
<Column/Dot inversion>
Source output level of blank period Source Amp. operation in blank
BLREV BLS
Positive polarity Negative polarity period
0 0 V255P V255N ON
1 GND GND OFF
1 0 V0P V0N ON
1 HiZ HiZ OFF
Restriction -
HRE1
Description
This register controls assignment of source output.
According to this register setting, display operation mode is defined.
Function Table
Panel resolution control
Assignment of Source pins Output level of
(=CABC resolution)
HRE1 non-assigend
source pins
X(HRE) Y(NL) 2MUX 3MUX
S[1:800],
‘h0 1600RGB 2560 S[1:2400] -
S[1601:2400]
S[1:1080], S[1:720],
‘h1 1440RGB 2560 GND
S[1321:2400] S[1681:2400]
S[1:1152], S[1:768],
‘h2 1536RGB 2560 Random data
S[1249:2400] S[1633:2400]
Restriction
This register is setted in sleep in mode. Please do not change in sleep out mode.
Please set set_column_address and set_page_address again after releasing HWRESET, releasing
DSTB, changing HRE1.
UDS
Description
This register controls scan direction of vertical.
Function Table
Restriction -
ABSI
Description
This register controls avoiding initial-noisy-pattern lights up.
Only when it’s a mode using RAM, this command becomes effective.
Function Table
ABSI Operation
Initial-noisy-pattern display
‘h0 When establishing the DISPON command before the SLPOUT command, the
DISPON command becomes effective automatically after power-on sequence. In
this case initial-noisy-pattern lights up, if RAM data are not written.
Black image display
‘h1 In case of using this setting, black image data is written to GRAM during power-on
sequence. If any image data are written to GRAM before exit_sleep_mode
command, display starts using this data after set_display_on command.
Written data display
‘h2 The DISPON command does not become effective until 1 frame data are written.
In case of using this setting, be sure to write data for 1frame. If not doing this
operation, display does not start to display wrote data.
‘h3 Setting inhibit
Restriction -
PNSET
Description
This register sets a dot inversion method.
Details are described in a paragraph “LINEINV”, please refer it.
Function Table
PNSET Method
‘h0 Spatial configuration mode 1
‘h1 Spatial configuration mode 2
Restriction
This register setting is not usable at the time of 1-line, 3-line, over 14-line and Column inversion.
MUX3EN
Description
This register sets the number of MUX.
Using source pins in 2MUX/3MUX are described in a paragraph “HRE1”, please refer it.
Function Table
MUX3EN MUX mode
‘h0 2MUX
‘h1 3MUX
Restriction
-
LINEINV
Description
This register sets a dot inversion method.
Function Table
LINEINV Method
‘h0 1-line inversion drive
‘h1 2-line inversion drive
‘h2 3-line inversion drive
‘h3 4-line inversion drive
‘h4 6-line inversion drive
‘h5 8-line inversion drive
‘h6 10-line inversion drive
‘h7 12-line inversion drive
‘h8 14-line inversion drive
‘h9 16-line inversion drive
‘hA 24-line inversion drive
‘hB 32-line inversion drive
‘hC 48-line inversion drive
‘hD 64-line inversion drive
‘hE Setting inhibited
‘hF Column inversion
3-line inversion drive [spatial configuration mode1] (LINEINV =’h2, PNSET=Don’t care
Line↓ + - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
Line↓ + - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
- + - + - + - + + - + - + - + -
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
+ - + - + - + - - + - + - + - +
Column inversion
Restriction -
NL
Description
This register controls the number of lines to drive panel.
Function Table
NL Number of lines [line]
‘hA00 2560 lines
Restriction
The host processor must wait more 15us between the end of write data transfer and this command.
BP
Description
This register controls the number of line of back porch.
Function Table
BP Number of line of back porch[line]
n<2 Setting inhibit
‘h2 2 lines
‘h3 3 lines
: :
n n lines
: :
‘h1F 31 lines
Restriction
Setting of BP is different from VBP if using compression data transfer. Refer to “Compression data
transfer”.
Please do not change this register in displaying.
Please refer to Appendix data sheet for detail of setting.
FP
Description
This register controls the number of lines of front porch.
Function Table
FP Number of lines of front porch [line]
n<2 Setting inhibit
‘h2 2 lines
‘h3 3 lines
: :
n n lines
: :
‘h1F 31 lines
Restriction
Please do not change this register in displaying.
Please refer to Appendix data sheet for detail of setting.
FP2
Description
This register controls the number of lines of front porch during idle mode (entering by 39h
command).
Function Table
FP2 Number of lines of front porch [line]
n<2 Setting inhibit
‘h2 2 lines
‘h3 3 lines
: :
n n lines
: :
‘h1F 31 lines
Restriction
Please do not change this register in displaying.
Please refer to Appendix data sheet for detail of setting.
TPSYNEN
Description
This register set to enable VSOUT, HSOUT output.
Function Table
TPSYNEN VSOUT, HSOUT output
‘h0 OFF (Fixed Low)
‘h1 ON (Active)
Restriction -
HSOM
Description
This register set the HSOUT output timing.
Refer to “Synchronization signal Output for touch panel controller” for details.
Function Table
HSOUT output period
HSOM
Back porch Display period Front porch
(BP) (NL) (FP)
‘h0 Output Output Output
‘h1 Fixed low Output Fixed Low
‘h2 Output Fixed low Output
‘h3 Setting inhibited
Restriction -
VSOD
Description
This register set the VSOUT output timing.
Refer to “Synchronization signal Output for touch panel controller” for details.
Function Table
VSOD VSOUT output timing
‘h0 0 line (First line of back porch)
‘h1 +1 line
‘h2 +2 line
‘h3 +3 line
Restriction -
HSOD
Description
This register set the HSOUT output timing
Function Table
HSOD HSOUT output timing
‘h0 0clk
‘h1 1clk
‘h2 2clk
: :
n n clk
: :
‘h7F 127clk
(1clk=1RCLK)
Restriction -
HSOHW
Description
This register set the high period of HSOUT.
Function Table
HSOHW HSOUT high period
‘h0 0clk
‘h1 1clk
‘h2 2clk
: :
n n clk
: :
‘hFF 255 clk
(1clk=1RCLK)
Restriction -
DIV
Description
These registers sets the OSC divide ratio of RCLK.
Please refer the paragraph “Internal Reference Clock Generating Function”.
Function Table
Restriction -
EQWx
Description
These registers set the horizontal period of pre-charge, equalize operation.
Function Table
EQW3-19 Period
‘h00 0clk
‘h01 1clk
‘h02 2clk
‘h03 3clk
: :
‘hFh 15 clk
(1clk = 1RCLK)
SOUTn EQ
SOUTn timing
EQW3 EQW10 EQW5 EQW11
EQW6 EQW12 EQW7 EQW13
EQW8 EQW14 EQW9 EQW15
EQW16 EQW18 EQW17 EQW19
VGH
SOUTn
VSP
GND
VSN
VGL
<rise> <fall>
Restriction -
SNTx
Description
These registers set s source output delay.
Function Table
(1clk = 1RCLK)
Restriction -
RTSON
Description
This register controls on/off of the Real time Scaling function.
Function Table
RTSON Real Time Scaling
0 Real Time Scaling Off
1 Real Time Scaling On
Restriction
ON/OFF switching of Real time scaling function is possible in Command mode only.
RTSRAM
Description
This register selects input data size.
Function Table
RTSRAM Input data size
0 ×1
1 × 1/4
Restriction
The host processor must wait more 15us between the end of write data transfer and this command.
Description
The output timing of each panel control signal is set.
STx : Sets the Rising or Falling position of the SOUT signal.
SWx : Sets the High or Low period of the SOUT signal.
PSWTx : Sets the Rising or Falling position of the SOUT signal.
PWWx : Sets the High or Low period of the SOUT signal.
PSWGx : Sets the Non-overlap period of the SOUT signal
Function Table
(1clk = 1RCLK)
Restriction -
RTN0
Description
Sets 1H (line) period.
See Appendix for detail of panel control signal timing.
Function Table
Restriction -
RTN2
Description
Sets 1H (line) period.
See Appendix for detail of panel control signal timing during idle mode(entering by 39h command).
Function Table
Restriction -
28th
1 ↑ ↑ 0 VGMN12[6] VGMN12[5] VGMN12[4] VGMN12[3] VGMN12[2] VGMN12[1] VGMN12[0] xx
parameter
Register init - - - 0 1 0 1 0 1 1 1 57
29th
1 ↑ ↑ 0 VGMN13[6] VGMN13[5] VGMN13[4] VGMN13[3] VGMN13[2] VGMN13[1] VGMN13[0] xx
parameter
Register init - - - 0 1 0 1 1 1 1 1 5F
30th
1 ↑ ↑ 0 VGMN14[6] VGMN14[5] VGMN14[4] VGMN14[3] VGMN14[2] VGMN14[1] VGMN14[0] xx
parameter
Register init - - - 0 1 1 0 0 1 1 1 67
VGMPn, VGMNn
Description
This registers are applied to source pins.
See “Gamma Correction Function” for detailed description of the parameters.
Function Table -
Restriction -
GAMADJ
Description
This register is independent gamma adjustment enable On/Off
Refer to the Application Note for Digital Gamma Function.
Function Table
GAMADJ Gamma adjustment
0 Off
1 On
Restriction -
Description
These registers are used to set brightness and contrast
Function Table
Adjustment registers Function
BR0_R,BR1_R Adjustment for Red Brightness and Contrast
BR0_G, BR1_G Adjustment for Green Brightness and Contrast
BR0_B, BR1_B Adjustment for Blue Brightness and Contrast
Restriction -
Description
These registers are used to set gamma curve
Function Table
Adjustment registers Function
GAM0_R, GAM1_R, GAM2_R Adjustment for Red gamma curve
GAM0_G, GAM1_G, GAM2_G Adjustment for Green gamma curve
GAM0_B, GAM1_B, GAM2_B Adjustment for Blue gamma curve
Restriction -
Description
These registers are used to fine adjustment of gamma curve
Function Table
Adjustment registers Function
TILT0_R, TILT1_R Fine adjustment for Red gamma curve
TILT0_G, TILT1_G Fine adjustment for Green gamma curve
TILT0_B, TILT1_B Fine adjustment for Blue gamma curve
Restriction -
CE_ON, PPEN2
Description
These registers cotnrol CE on/off.
Function Table
CE_ON PPEN2 CE
0 0 Disable
0 1 Setting inihibit
1 0 Setting inhibit
1 1 Enable
SOUTENx SOUTPLx
Description
As for SOUTPLx, the control output polarity of SOUT1-n is set up.
SOUTENx controls output enable of SOUT1-n.
Function Table
Command
SOUTx output
SOUTENx SOUTPLx
‘h0 Fix Low
‘h0
‘h1 Fix High
‘h0 Operate(normal)
‘h1
‘h1 Operate(inversion)
Restriction
SOUTABSPLEN SOUTABSPLx
Description
These registers control the porarity of SOUT1-x during abnormal power off sequence.
Function Table
Restriction -
LIM
Description
This register controls Panel Interface Mode.
Please select suitable setting for each panel according to Panel Interface Specification.
Function Table
LIM LCD Panel interface Mode
Restriction
LIM is defined by the Panel Specification. Please refer to the Appendix data sheet.
DC2
Description
This register controls divide ration of boost clock frequency for VGH.
Function Table
Restriction
This command will control when power on/off sequence..
BT2
Description
This register controls boost ratio of VGH.
Function Table
Boost ratio
BT2
VGH boost ratio
’h0 VCI2×2
’h1 VCI2×2-VSN
Restriction
This command will control when power on/off sequence.
DC3
Description
This register controls divide ration of boost clock frequency for VGL.
Function Table
Restriction -
BT3
Description
This register controls boost ratio of VGL.
Function Table
Boost ratio
BT3
VGL boost ratio
’h0 VSN-VCI3
’h1 VSN×2-VCI3
Restriction
This command will control when power on/off sequence.
VLM2
Description
This register controls output level of VGH.
Recommended voltage: (voltage set by BT2) – (voltage set by VLM2) ≦ 2V
Function Table
Restriction -
VLM3
Description
This register controls output voltage level of VGL.
Recommended voltage: (voltage set by BT3) - (voltage set by VLM3) ≧ -2V
Function Table
Restriction -
VC2
Description
This register controls output voltage of VCI2 regulator. VCI2 is internal voltage for generating VGH.
Function Table
Restriction
This command will control when power on/off sequence.
VC3
Description
This register controls output voltage of VCI3 regulator. VCI3 is internal volgtage for generating VGL.
Function Table
VCI3 regulator output VCI3 regulator output
VC3 VC3
voltage voltage
‘h0 2.4V ‘h8 4.0V
‘h1 2.6V ‘h9 4.2V
‘h2 2.8V ‘hA 4.4V
‘h3 3.0V ‘hB 4.6V
‘h4 3.2V ‘hC 4.8V
‘h5 3.4V ‘hD 5.0V
‘h6 3.6V ‘hE 5.2V
‘h7 3.8V ‘hF 5.4V
Restriction
This command will control when power on/off sequence.
VPL
Description
This register controls output voltage of positive gray scale reference level.
Function Table
VPL VPLVL [V] VPL VPLVL [V] VPL VPLVL [V] VPL VPLVL [V]
'h00 'h20 3.725 'h40 4.525 'h60 5.325
'h01 'h21 3.750 'h41 4.550 'h61 5.350
'h02 'h22 3.775 'h42 4.575 'h62 5.375
'h03 'h23 3.800 'h43 4.600 'h63 5.400
'h04 'h24 3.825 'h44 4.625 'h64 5.425
'h05 'h25 3.850 'h45 4.650 'h65 5.450
'h06 'h26 3.875 'h46 4.675 'h66 5.475
'h07 'h27 3.900 'h47 4.700 'h67 5.500
'h08 'h28 3.925 'h48 4.725 'h68 5.525
Setting
'h09 inhibited 'h29 3.950 'h49 4.750 'h69 5.550
'h0A 'h2A 3.975 'h4A 4.775 'h6A 5.575
'h0B 'h2B 4.000 'h4B 4.800 'h6B 5.600
'h0C 'h2C 4.025 'h4C 4.825 'h6C 5.625
'h0D 'h2D 4.050 'h4D 4.850 'h6D 5.650
'h0E 'h2E 4.075 'h4E 4.875 'h6E 5.675
'h0F 'h2F 4.100 'h4F 4.900 'h6F 5.700
'h10 'h30 4.125 'h50 4.925 'h70 5.725
'h11 'h31 4.150 'h51 4.950 'h71 5.750
'h12 'h32 4.175 'h52 4.975 'h72 5.775
'h13 'h33 4.200 'h53 5.000 'h73 5.800
'h14 'h34 4.225 'h54 5.025 'h74 5.825
'h15 'h35 4.250 'h55 5.050 'h75 5.850
'h16 'h36 4.275 'h56 5.075 'h76 5.875
'h17 3.500 'h37 4.300 'h57 5.100 'h77 5.900
'h18 3.525 'h38 4.325 'h58 5.125 'h78 5.925
'h19 3.550 'h39 4.350 'h59 5.150 'h79 5.950
'h1A 3.575 'h3A 4.375 'h5A 5.175 'h7A 5.975
'h1B 3.600 'h3B 4.400 'h5B 5.200 'h7B 6.000
'h1C 3.625 'h3C 4.425 'h5C 5.225 'h7C
'h1D 3.650 'h3D 4.450 'h5D 5.250 'h7D Setting
'h1E 3.675 'h3E 4.475 'h5E 5.275 'h7E inhibited
'h1F 3.700 'h3F 4.500 'h5F 5.300 'h7F
VNL
Description
This register controls output voltage of negative gray scale reference level.
Function Table
VNL VNLVL [V] VNL VNLVL [V] VNL VNLVL [V] VNL VNLVL [V]
'h00 'h20 -3.725 'h40 -4.525 'h60 -5.325
'h01 'h21 -3.750 'h41 -4.550 'h61 -5.350
'h02 'h22 -3.775 'h42 -4.575 'h62 -5.375
'h03 'h23 -3.800 'h43 -4.600 'h63 -5.400
'h04 'h24 -3.825 'h44 -4.625 'h64 -5.425
'h05 'h25 -3.850 'h45 -4.650 'h65 -5.450
'h06 'h26 -3.875 'h46 -4.675 'h66 -5.475
'h07 'h27 -3.900 'h47 -4.700 'h67 -5.500
'h08 'h28 -3.925 'h48 -4.725 'h68 -5.525
'h09 'h29 -3.950 'h49 -4.750 'h69 -5.550
'h0A Setting 'h2A -3.975 'h4A -4.775 'h6A -5.575
'h0B inhibited 'h2B -4.000 'h4B -4.800 'h6B -5.600
'h0C 'h2C -4.025 'h4C -4.825 'h6C -5.625
'h0D 'h2D -4.050 'h4D -4.850 'h6D -5.650
'h0E 'h2E -4.075 'h4E -4.875 'h6E -5.675
'h0F 'h2F -4.100 'h4F -4.900 'h6F -5.700
'h10 'h30 -4.125 'h50 -4.925 'h70 -5.725
'h11 'h31 -4.150 'h51 -4.950 'h71 -5.750
'h12 'h32 -4.175 'h52 -4.975 'h72 -5.775
'h13 'h33 -4.200 'h53 -5.000 'h73 -5.800
'h14 'h34 -4.225 'h54 -5.025 'h74 -5.825
'h15 'h35 -4.250 'h55 -5.050 'h75 -5.850
'h16 'h36 -4.275 'h56 -5.075 'h76 -5.875
'h17 -3.500 'h37 -4.300 'h57 -5.100 'h77 -5.900
'h18 -3.525 'h38 -4.325 'h58 -5.125 'h78 -5.925
'h19 -3.550 'h39 -4.350 'h59 -5.150 'h79 -5.950
'h1A -3.575 'h3A -4.375 'h5A -5.175 'h7A -5.975
'h1B -3.600 'h3B -4.400 'h5B -5.200 'h7B -6.000
'h1C -3.625 'h3C -4.425 'h5C -5.225 'h7C
'h1D -3.650 'h3D -4.450 'h5D -5.250 'h7D Setting
'h1E -3.675 'h3E -4.475 'h5E -5.275 'h7E inhibited
'h1F -3.700 'h3F -4.500 'h5F -5.300 'h7F
APAN
Description
This register controls reference current of Source amp, Gamma circuit and reference voltage circuit
for negative polarity.
In case of lower current setting, there is the potential to affect the display quality. In case of higher
current setting, there is the potential to increase IC current. If changing this register, check the
display quality and current consumption.
Function Table
Restriction -
APAP
Description
This register controls reference current of Source amp, Gamma circuit and reference voltage circuit
for positive polality.
In case of lower current setting, there is the potential to affect the display quality. In case of higher
current setting, there is the potential to increase IC current. If changing this register, check the
display quality and current consumption.
Function Table
Restriction -
VBTS
Description
When the value of VSP is lower than the value of VBTS, it changes to Abnormal Sequence.
Function Table
Detection level
VBTS
of VSP [V]
’h0 4.74
’h1 5.10
’h2 4.02
’h3 4.42
Restriction -
WCVDC
Description
This register controls access to VCOM adjustment register (VDC).
Please use this register in case of VCOM adjustment.
Function Table
WCVDC Operation
Restriction -
WCVDCB
Description
This register controls access to VCOM adjustment register (VDCB).
Please use this register in case of adjustment.
Function Table
WCVDCB Operation
Restriction -
VDC
Description
This register controls VCOM output level. VDC is effective on forward scan.
Function Table
(Continued)
(Continued)
(continued)
(Continued)
(Continued)
(Continued)
Restriction
Make sure that voltage level is (-2.0 ~ +2.0)V in setting.
VDCB
Description
This register controls VCOM output level. VDCB is effective on backward scan.
Function Table
VDCB VCOM VDCB VCOM VDCB VCOM VDCB VCOM
'h0 'h20 'h40 'h60 x 0.3727
'h1 'h21 'h41 'h61 x 0.3735
'h2 'h22 'h42 'h62 x 0.3742
'h3 'h23 'h43 Setting 'h63 x 0.3750
'h4 'h24 'h44 inhibited 'h64 x 0.3758
'h5 'h25 'h45 'h65 x 0.3765
'h6 'h26 'h46 'h66 x 0.3773
'h7 'h27 'h47 'h67 x 0.3780
'h8 'h28 'h48 x 0.3545 'h68 x 0.3788
'h9 'h29 'h49 x 0.3553 'h69 x 0.3795
'hA 'h2A 'h4A x 0.3561 'h6A x 0.3803
'hB 'h2B 'h4B x 0.3568 'h6B x 0.3811
'hC 'h2C 'h4C x 0.3576 'h6C x 0.3818
'hD 'h2D 'h4D x 0.3583 'h6D x 0.3826
'hE 'h2E 'h4E x 0.3591 'h6E x 0.3833
'hF Setting 'h2F Setting 'h4F x 0.3598 'h6F x 0.3841
'h10 inhibited 'h30 inhibited 'h50 x 0.3606 'h70 x 0.3848
'h11 'h31 'h51 x 0.3614 'h71 x 0.3856
'h12 'h32 'h52 x 0.3621 'h72 x 0.3864
'h13 'h33 'h53 x 0.3629 'h73 x 0.3871
'h14 'h34 'h54 x 0.3636 'h74 x 0.3879
'h15 'h35 'h55 x 0.3644 'h75 x 0.3886
'h16 'h36 'h56 x 0.3652 'h76 x 0.3894
'h17 'h37 'h57 x 0.3659 'h77 x 0.3902
'h18 'h38 'h58 x 0.3667 'h78 x 0.3909
'h19 'h39 'h59 x 0.3674 'h79 x 0.3917
'h1A 'h3A 'h5A x 0.3682 'h7A x 0.3924
'h1B 'h3B 'h5B x 0.3689 'h7B x 0.3932
'h1C 'h3C 'h5C x 0.3697 'h7C x 0.3939
'h1D 'h3D 'h5D x 0.3705 'h7D x 0.3947
'h1E 'h3E 'h5E x 0.3712 'h7E x 0.3955
'h1F 'h3F 'h5F x 0.3720 'h7F x 0.3962
(Continued)
(Continued)
(Continued)
(Continued)
(Continued)
(Continued)
Restriction
Make sure that voltage level is (-2.0 ~ +2.0)V in setting.
TIGON
Description
This IC supports the test free-running mode function. When TIGON is set to “1”, this IC operates in
synchronization with the internal oscillation clock.
Enables the Test Image Generation function.
Function Table
0 Off
1 On
Restriction
・In Built-in TCON Display Mode ( DM = ‘h0 ) only, TIGON can set to 1.
・In PNSLV='h1 (Master=portB), set C1h3rd paremeter to C0h.
TIGCYC
Description
TIGCYC can change the display cycle of the selected image.
Function Table
Restriction -
TIP
Description
Setting each of the TIP[15:0] registers to 1 allows images to be displayed in the free-running mode.
The following are the relationships between the registers and display images.
Function Table
Register Display image
TIP[0] Middle Gray 127
TIP[1] Horizontal grayscale
TIP[2] Vertical grayscale
TIP[3] White 255
TIP[4] Red 255
TIP[5] Green 255
TIP[6] Blue 255
TIP[7] Black
TIP[8] SMEAR (a white window against a dark background)
TIP[9] Color bar
TIP[10] DCF (aligned dot check)
TIP[11] 2Pixel V-Stripe
Restriction
Display image TIP[1], TIP[2] , and TIP[9],[10],[11] may be repeated in a screen according to the size.
The central white window size in display image TIP[8] varies according to the display image size.
Power supply on
VSP/VSN
IOVCC Exit Sleep mode
Command:11h
Set_Display_On
Command 29h
Power on reset
(Hard ware reset)
Wait for
more than 3ms R63419 free running
Sleep in State
VSP/VSN
Set Test Image Generator Command IOVCC
Command:E5h
1st Parameter: TIGCYC[1:0],TIGON=1
2nd Parameter: TIP[11:8] GND
3rd Parameter: TIP[7:0]
Command:B3h
1st Parameter: 00h DM=0h
2)case of DBIST
Power supply on
VSP/VSN
IOVCC
DBIST=High(IOVCC)
GND
Power on reset
(Hard ware reset)
Wait for
more than 3ms DBIST=Low(GND)
Sleep in State
Wait more
than 120ms
Manufacturer Command Access
Protect off
Power supply off
MCAP=3’b100
VSP/VSN
IOVCC
A setup is unnecessary
when NVM has a setup.
Command:B3h
1st Parameter: 00h DM=0h
NVMAEN
Description
This register controls NVM accessibility. Refer to "NVM Control" for detail.
Function Table
NVMAEN NV Memory Access
0 Disable
1 Enable
Restriction -
TEM
Description
This register controls output data from TE.
Function Table
TEM TE output TE output control
sleep_mode_on
TE output is fixed low.
‘h0 Tearing Effect sleep_mode_off
set_tear_on : TE output is enabled.
set_tear_off : TE output is fixed low.
NVM automatically write data verification
result (=VERIFLGWR & VERIFLGER)
‘h1 TE output is always enabled.
TE = 0 Verification result is NG
TE = 1 Verification result is OK
Restriction -
NVMFTT
Description
This register controls NVM re-write sequence.
If NVMAEN=1 & NVMFTT=1, NVM start re-write(erase and write) sequence.
Function Table
NVMFTT NV Memory re-write & Verify operation
0→1 Sequence start
(1→0) Return to “0” when sequence finish
Restriction -
NVMVFFLGER
Description
NVM execute erase verify operation after NVM erase operation, and return write verify result.
(Erase operation is executed 1st step of NVM re-write sequence.)
This register is read-only, and cannot write data.
Function Table
NVMVFFLGER NV Memory Erase Verification Result
0 Fail
1 Pass
Restriction -
NVMVFFLGWR
Description
NVM execute write verify operation after NVM write operation, and return write verify result.
(Write operation is executed following erase operation.)
This register is read-only, and cannot write data.
Function Table
NVMVFFLGWR NVM Write Verification Result
0 Fail
1 Pass
Restriction -
WCDDB
Description
This register controls accessibility of A1h: read_DDB_start register
Function Table
WCDDB Notes
0 DDB access is disable. *Please set WCDDB=0 except NVM writing
1 DDB access is enable. *Data setted DDB register are written to NVM.
If writing the data to A1h to NVM, WCDDB=1, and send A1h command and whole parameters before
starting NVM writing (NVMFTT=1). If finishing to write A1h, turn WCDDB from 1 to 0.
Please refer “NVM Write Sequence” for detail.
Restriction -
WCDDBCOL
Description
This register controls accessibility of 70h – 7Eh registers.
Function Table
WCDDBCOL Notes
1 7xh access is enable. *Data setted 7xh register are written to NVM.
If writing the data to 7xh to NVM, WCDDBCOM=1, and send 70h command – 7Eh command before
starting NVM writing(NVMFTT=1) . If finishing to write 7xh, turn WCDDB from 1 to 0.
Please refer “NVM Write Sequence” for detail.
Restriction -
WCRDID
Description
This register controls accessibility of DAh, DBh, DCh registers.
Function Table
WCRDID Notes
1 DAh-DCh access is enable. *Data setted DAh-DCh register are written to NVM.
If writing the data to DAh-DCh to NVM, WCRDID=1, and send DAh command – DCh command
before starting NVM writing(NVMFTT=1) . If finishing to write DAh-DCh, turn WCDDB from 1 to 0.
Please refer “NVM Write Sequence” for detail.
Restriction -
NVMLD
Description
These registers set commands used to load data from NVM during each sequence.
Function Table
NVMLD[x] Operation
NVMLD[1] B8h, B9h, BAh, BBh, BCh, BDh CABC, SRE, SRE
Test register,
NVMLD[5] CDh, D6h-D9h, E5h, ECh-EFh, FBh
Test image generator,
Restriction -
NVMWECNT
Description
These registers count the times of NVM erase/write.
Function Table
Restriction
When NVM erase/write operation finish normally, this counter counts up.
If NVM erase/write operation finish abnormally, this counter cannot count correctly.
COMP_ENTRY_NUM
Description
This register indicates the number of compression method which Driver IC is supported.
Function Table
Restriction
Description
In order to check the support compression ID of Driver IC have the compression method ID register.
These registers are ID register. These registers consist compression method and compression
method version for each Video mode and Command mode.
Application processor should check the compression method the Driver IC is supported.
Function Table
bit Description
0: No compression
2: 1/2 compression
[7:5] Compression ratio
3: 1/3 compression
Other: inhibit
[4:2] Compression IP version -
0: Not supported
[1] Support Video mode
1: Supported
0 :Not supported
[0] Support Command mode
1 :Supported
Restriction
COMPV_METHOD
Description
This register is for setting of compression method in Video mode.
Function Table
bit Description
0: No compression
[7] Compression enable
1: Compression
[6:3] Reserved -
0: No compression
2: 1/2 compression
[2:0] Compression Ratio
3: 1/3 compression
Other: inhibit
Restriction
-
COMPC_METHOD
Description
This register is for setting of compression method in Command mode.
Function Table
bit Description
0: No compression
[7] Compression enable
1: Compression
[6:3] Reserved -
0: No compression
[2:0] Compression Ratio 3: 1/3 compression
Other: inhibit
Restriction
-
Description
This register necessary to set when changing the state Realtime Scaling On to Off.
Function Table
RTSOFC Real Time Scaling off contorol
0 It is impossible to turn off Realtime Scaling function.
1 It is possible to turn off Realtime Scaling function.
Restriction
-
Note: For the number of lanes and the data rate, see “Block Function” and “Electrical
Characteristics.”
When MIPI DSI is selected, CSX is used only to exit deep standby (DSTB) mode.
When deep standby mode is exited by RESX, CSX is not required. a
Figure 19 Switching the Clock Lane between Clock Transmission and Low Power Mode 1
Figure 20 Switching the Clock Lane between Clock Transmission and Low Power Mode 2
Figure 21 Switching the Clock Lane between Clock Transmission and Low Power Mode 3
TCLK-POST TEOT
VIH(min)
VIL(max)
VIH(min)
VIL(max)
Figure 22 Switching the Clock Lane between Clock Transmission and Low Power Mode 4
The data lanes and clock lane should be in the LP-11 state during power-on, HWRESET, and soft_reset
sequences.
2) Escape Mode
Figure 24
R63419 supports TE Report function. Only master port defined by PNSLV pin supports TE Report.
Procedures are as follows:
Figure 25
Figure 27
In LP-11 state, multiple Short Packets (SPa) and Long Packets (LPa) can be received between SoT and
EoT.
The RSP LCD driver supports Virtual Channel(VC). The data of VC is setting by 2bits, and refer data
of DSIVCA[1:0]/DSIVCB[1:0]. The data of DSIVCA[1:0]/DSIVCB[1:0] are stored to NVM.
If Data Type undefined in the MIPI DSI specification is received, the subsequent data cannot be
received. Transmit data again after checking that the RSP LCD driver is in LP-11 state by Error Report.
If Data Type unsupported in the RSP LCD driver is received, it is regarded as NOP, and the result is
not reflected on the Error Report.
Table 53
Data Identification (DI)
Virtual Channel (VC) Data Type (DT)
B7 (0) B6 (0) B5 B4 B3 B2 B1 B0
00h-01h Reserved - -
03h-07h Reserved - -
09h-10h Reserved - -
13h-18h Reserved - -
1Bh Reserved - -
1Dh-20h Reserved - -
23h-28h Reserved - -
29h-3Fh Reserved - -
Word Count (WC) = 2 bytes: The number of packet data on Long Packet (0 to 65,535 bytes)
ECC detects 1-bit errors or multiple-bit errors in each Packet Header. ECC is performed on the
following:
Figure 28 24bpp Pixel Data Format on the Long Packet (3Ah: set_pixel_format D2-0 = 111)
Figure 29 18bpp Pixel Data Format on the Long Packet (3Ah: set_pixel_format D2-0 = 110)
In the Long Packet, Packet Footer is added after Packet Data. Packet footer includes CRC calculated
from Packet Data as checksum.
Table 56
RSP LCD driver
Bit Description Note
Implementation
0 SoT Error No
1 SoT Sync Error No
2 EoT Sync Error No
3 Escape Mode Entry Command Error Yes 1
4 Low-Power Transmit Sync Error Yes 1
5 HS Receive Timeout Error No
6 False Control Error No
7 Reserved -
8 ECC Error, single-bit (detected, and corrected) Yes
9 ECC Error, multi-bit (detected, not corrected) Yes
10 Checksum Error (Long packet only) Yes
11 DSI Data Type Not Recognized Yes
12 DSI VC ID Invalid Yes
13 Invalid Transmission Length No
14 Reserved -
15 DSI Protocol Violation No
Note: Detail error report condition is defined by RSP LCD driver (based on MIPI description).
The following tables show available data type of each command (DCS and MCS).
DCS Data 05’h 15’h 39’h 13’h 23’h 29’h 14’h 24’h 06’h 37’h
Type
Command/Parameter Packet Short Short Long Short Short Long Short Short Short Short
DCS DCS DCS DCS Generic Generic Generic Generic Generic DCS Set
para no 1 1 para 2 para - 1 para 2 para no max.
para para para return
packet
size
DCS Data 05’h 15’h 39’h 13’h 23’h 29’h 14’h 24’h 06’h 37’h
Type
Command/Parameter Packet Short Short Long Short Short Long Short Short Short Short
DCS DCS DCS DCS Generic Generic Generic Generic Generic DCS Set
para no 1 1 para 2 para - 1 para 2 para no max.
para para para return
packet
size
Note: When each data type packet is sent, it is necessary to write all parameters of each DCS and MCS.
Note1: maximum return packet size ≧ 2
MCS Data 05’h 15’h 39’h 13’h 23’h 29’h 14’h 24’h 06’h 37’h
Type
Command/Parameter Packet Short Short Long Short Short Long Short Short Short Short
MCS DCS DCS DCS Generic Generic Generic Generic Generic DCS Set
para no 1 1 para 2 para - 1 para 2 para no max.
para para para return
packet
size
The RSP LCD driver supports Video Mode for moving pictures. There are three formats of
transmission packet sequences. The RSP LCD driver supports two of these formats. See the following
table.
Table 60
Transmission packet sequence in video mode RSP LCD driver implementation
Non-burst mode with sync pulses Not supported
Non-burst mode with sync events Supported
Burst mode Supported
Figure 30
VSYNC
D[23:0]
VBL Vadr(NL)
DE
VP(1frame)
BP+1 VFP-1
Source Output
HSYNC
V B H B H B H B RGB B H B RGB B H B H B H B V B
S P S P S P S P data P S P data P S P S P S P S P
Key :
VS : Vsync Start(DT=01h),HS : Hsync Start(DT=21h),BP : Blanking Packet(DT=09h)
RGB data : RGB data(DT=3Rh),DT : Data type
Figure 31
Figure 32
line line
BP FP BP FP
Video data
display
display
Video data
α: Time the pixel data is transferred to PortB precedes time the pixel data is transferred to the PortA.
β: Time the pixel data is transferred to PortB is behind time the pixel data is transferred to the PortA.
45ByteClock(min) 100ByteClock(min)
Hadr(RGB Data)
Pixel Data of Master Port 45ByteClock α β (100ByteClock)
(600ByteClock)
45ByteClock
α 100ByteClock
Hadr(RGB Data)
Pixel Data of Slave Port 45ByteClock α β (100ByteClock)
(600ByteClock)
(delay against Master)
Figure 33
* frame freq. 60 Hz
Vertical Sync
*X 1440 RGB
*Y 2560 line VS
invisible image
* VS+VBP 8 line
8
Horizontal
Byte clock 9.1 ns
Sync
Figure 34
...
Pixel 1
1 byte 2 bytes 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte
6b 6b 6b 6b 6b 6b 6b 6b 6b
Virtual Channel ID
Data Type
1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 2 bytes
6b 6b 6b 6b 6b 6b 6b 6b 6b
... Checksum
Variable Size Payload (Last Three Pixels Packed in Nine Bytes) Packet Footer
Figure 35 18-Bit Format Long Packet (loosely packed) Data Type 10 1110 (2Eh)
...
Pixel 1
1 byte 2 bytes 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte
8b 8b 8b 8b 8b 8b 8b 8b 8b
Virtual Channel ID
Data Type
1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 2 bytes
8b 8b 8b 8b 8b 8b 8b 8b 8b
... Checksum
Variable Size Payload (Last Three Pixels Packed in Nine Bytes) Packet Footer
In the Long Packet, Packet Footer is added after Packet Data. Packet footer includes CRC calculated
from Packet Data as checksum.
The Low-Power receiver and a separate contention detector shall be used in a bi-directional data Lane
to monitor the line voltage on each low-power signal. The low-power receiver shall be used to detect an
LP high fault when the LP transmitter is driving high and the pin voltage is less than V IL. The
contention detector shall be used to detect an LP low fault when the LP transmitter is driving low and
the pin voltage is greater than VIHCD. An LP low fault shall not be detected when the pin voltage is less
than VILCD.
The LP-CD threshold voltages (VILCD and VIHCD) are shown along with the normal signaling voltages
as below.
After contention has been detected, the protocol shall take proper measures to resolve the situation.
Display Mode
As shown below, input display clock via each interface before issuing exit_sleep_mode.
≧4frame
Figure 38
RSP LCD driver can switching display interface between Command mode and Video mode using
“Video Through mode” with V2CRM or “Video to RAM mode” without display off. Details are
following.
In case of using RSP compression I/F, V2CRM does not support. If switching display interface
between Command mode and Video mode without display off, use “Video to RAM mode”.
Command mode
DM='h0
RM='h0
Command mode
DM='h0
RM='h0
Figure 39
If switch Video Through mode to Command mode by DM, Continue video input at least 2frames.
DM=1->0
≧2frame
Video Input
Host Frame 1 Frame2 ・・・ Frame N-1 Frame N Frame N+1 Frame N+2
Figure 40
Operation
Chart
data write data write data write data write
TE
Display mode Command mode Video through mode Video capture mode Command mode
DM='h1 DM='h0
V2CRM=0 V2CRM=1
274
Overlap frame Overlap frame
Figure 41
Host to Driver
Frame Momory
Display
Specification
R63419
TE
DM='h3 DM='h0
RM=1 RM=0
Overlap frame
275
Overlap frame
Figure 42
Host to Driver
Frame Momory
Display
Specification
R63419 Specification
Frame Memory
The frame memory retains image data obtained from (panel resolution the number of colors (bpp)).
In this mode, a content of the frame memory within an area where column pointer is 0000h to
(Column_Address_Max)h and page pointer is 0000h to (Row_Address_Max)h is displayed.
Figure 43
The figure below illustrates data stream from the host processor.
Figure 44
The data is written in the order shown in the above figure. The frame memory in this driver employs
an image compression store method. Image is compressed in units of four pixels. To write data to the
frame memory, transfer the image data in units of consecutive addresses. Determine a data transfer start
position settings by set_column_address (2Ah).
Table 66
When column counter value is larger than ”End Column” and page Entry Mode(B3h)
STOP STOP
counter value is larger than “End Page” WEM=0
DIV
Reference
clock(RCLK)
OSC clock1
Internal (Ex.)(fOSC/4)/DIV Display timing
1/4 Divider
oscillation clock fOSC/4 contorol circuit
(*1) 1/1
OSC clock2
1/2 Step-up circuit
fOSC/2
If entering 39h(Idle_mode_entry), the setting of DIV is ‘h11. Then, RCLK= (fOSC/4)/4, and if normal
mode frame rate is 60fps, idle mode frame rate is 15fps. Send pixel data to match this slow frame rate.
It is possible to set a low frame frequency for saving power consumption when displaying a still picture
and set a high frame frequency when displaying video image.
Relationship between the Liquid Crystal Drive Duty and the Frame Frequency
The relationship between the liquid crystal drive duty and the frame frequency is calculated from the
following equation. The frame frequency can be changed by setting frame frequency adjustment
parameters (the number of clocks per 1 line period (RTN0)).
RCLK
FrameFrequency [ Hz]
RTN 0 ( NL FP 0 BP )
14MHz
f FRM 60 Hz
91clocks (2560 8 8)
In the conditions described here, the frame frequency can be changed as follows by setting RTN0.
(NL = 2560 lines, BP = 8 lines, FP = 8 lines, and fosc = 56 MHz (typ.)).
Table 67
TEON
TELOM
(represents status of TE pin output
(35h1st parameter)
35h command)
0 * GND
1 0 TE (Mode1)
1 1 Setting inhibited
Tearing Effect signal mode is defined by TELOM (D0 in parameter of set_tear_on (35h)).
1H(RTN)
Figure 45
Self-Diagnostic Function
The RSP LCD driver supports the self-diagnostic functions. Set get_diagnostic_result (0Fh) 1st
parameter’s D6 bit according to the following flow chart.
Checks VPLVL
voltage level
Through histogram analysis of brightness of image data, the brightness of backlight and image
processing coefficient is calculated so that image data is optimized. Backlight power is reduced
without changing display image.
The RSP LCD driver can use Auto Contrast Optimization function and Content Adaptive Brightness
Control function at the same time.
Notes: 1. The CABC and SRE setting are enabled by 55h user command.
(write_content_adaptive_brightness_control).
2. The effects of CABC and SRE function on power efficiency and display quality depend on
image data and the setting. Check display quality on the panel.
System Configuration
The LEDPWM signal connects to the LED driver IC. The LED driver IC is controlled entirely via the
RSP LCD driver.
Overview
The RSP LCD driver supports a color enhancement function, which enhances saturation by calculating
image data. This function enhances the saturation of the image displayed on the liquid crystal panel and
displays image with color enhanced.
The function enhances color and makes pixel colors more vivid.
Saturation enhancement
Figure 49
When the saturation enhancement coefficients of the input image are 1.0 or more, the display
image with color enhanced is generated.
M Y
Input image colors
B G
Figure 50
See the saturation diagram right above. The colors of the input image are enhanced. (The polygon
showing the colors of the input image is enlarged)
When the saturation enhancement coefficients of red, yellow, green, cyan, blue, and magenta are
set independently. Here the saturation enhancement coefficients of only red and yellow are set.
M Y
Enhanced colors
B G
Unenhanced colors C
Figure 51
See the saturation diagram right above. Green, cyan, blue, and magenta are not enhanced. The colors
mixed with red or yellow and the mixed colors of red and yellow are enhanced.
- The skin color independent adjustment function displays natural skin color.
No skin color adjustment areas are set. Skin color adjustment areas are set.
- To adjust the skin color after saturation enhancement, this function adjusts the skin hues independently from the
other hues.
Conventional ACO was generated image on one tone curve in one frame. In this case, bright image can
be more bright, dark image can be darker. So contrast is high, but degradation of bright and dark
gradation occurs. On the other hands, Local Area ACO can change the curve for each location. So
degradation does not occur.
The RSP LCD driver can use Auto Contrast Optimization function and Content Adaptive Brightness
Control function at the same time.
The function can reduce the power consumption, EMI noise and space of a system by setting the
amount of data transfer from a host to 1/2 or 1/3.
Compression data transfer function is enabled, and compression rate can be selected by
COMPV_METHOD/COMPC_METHOD registers.
Features:
When the transfer error occurs, the impact of the image changes is small.
In 1/2 compression mode, 4pixels (Horizontal 4pixels x Vertical 1pixels) are packed into 1/2 size
compressed block.
In 1/3 compression mode, 8pixels (Horizontal 4pixels x Vertical 2pixels) are packed into 1/3 size
compressed block.
RSP compression data transfer can use existing DSI packet structure. And it is possible to apply both of
Video mode and Command mode.
The following figure describes explanation of each element for compressed data transfer.
In setting of Set column address (0x2A) and Set page address (0x2B), please set the address of display
image in conventional way. RSP compression technology can realize Partial / Window update with
only little restrictions of memory access in 1/2 compression mode and 1/3 compression mode.
The 1/2 compression data is made only from a one-line pixel data, since 1/2 compression unit consists
of horizontal 4 pixels.
It is transferred in an every line period same as Non compression data. (The Non compression data is
transferred in an every line period.)
The 1/3 compression data is made only from 2-lines pixel data, since 1/3 compression unit consists of
horizontal 4 pixels x vertical 2 pixels.
It is divided into a Left half image data part and a Right half image data part, and they are transferred in
each of an even line period and an odd line period.
By using compression data transfer, LCM can reduce port number or data transfer rate. The relation of
data transfer rate, port number and compression mode is below. R63419 just support following
combination.
(6)BP setting
By using compression data transfer, setting of BP is different from VBP at each compression rate.
Table 69 BP setting
No compression VBP = BP
1/2 compression VBP = BP – 1
1/3 compression VBP = BP - 2
The function can reduce the power consumption of a system by setting the amount of data transfer from
a host to 1/4.
Real time scaling function is enabled by the RTSON, the RTSRAM register.
ON/OFF switching of Real time scaling function is possible in Command mode only.
If change the state Realtime Scaling On to Off, It necessary to set to 20h the 1st parameter of F1h
Maximum DSI data transfer rate (tDSIR) of real time scaling is tDSIR/(2 x port number).
Ex) tDSIR=1Gbps
BP register needs to set even number. Please set (VS+VBP) to (BP register x 1/2).
Real time scaling function cannot be used in combination with interlace mode.
The odd line inversion cannot use in this mode. (Available mode: 2line, 4line,…. Column)
Operation
Chart data write
data write data write data write
TE
(4) Display Interface switching diagram-1
DM='h1 DM='h0
V2CRM=0 V2CRM=1
299
DSI data
DSI_Bit_Rate
taransfer rate Max. 1000Mbps
Host to Driver
Frame Momory
Display
Specification
R63419 Specification
Internal HSYNC is extended twice using RTN register at Realtime Scaling Mode.
Internal Data Transmission occurs each line(Internal_H1 and Internal_H2).
So, the following restrictions are needed in order to secure data transfer time.
Internal_H1
RTN ≧80RCLK
Internal_H2
Table 69-2 Example of 60Hz display setting at Realtime Scaling and Video Through Mode.
Port HRE1 tDSIR HS+HBP Hadr HFP RTN fFRM
1600RGB 480Mbps 22 800 450 5Ah 60.37Hz
2port 1440RGB 440Mbps 20 720 418 5Ah 60.33Hz
1536RGB 464Mbps 21 768 438 5Ah 60.29Hz
1600RGB 884Mbps 40 1600 782 5Ah 60.34Hz
1port 1440RGB 804Mbps 36 1440 716 5Ah 60.38Hz
1536RGB 852Mbps 38 1536 756 5Ah 60.34Hz
It is possible to shorten HBP according to tDSIR. (tDSIR/1000 * HBP)
The above-mentioned table is calculated as VS+VBP=4 , Vadr = 1280, VFP=4.
These signals are consist of vertical synchronization signal: VSOUT and horizontal synchronization
signal: HSOUT. The level of output voltage is IOVCC to GND. Each signal can adjust output timing
for internal synchronization signal. The high level width of VSOUT is 1 line, and the high level width
is adjustable.
Enable/disable of these signals is controlled by TPSYNEN register. VSOUT is outputted always, but
HSOUT is outputted during displaying only.
VSOUT is outputted that internal VSYNC is starting point. VSOUT output timing can adjust by VSOD
register. Unit is 1H.
HSOUT is outputted that internal source output timing is starting point. HSOUT output timing can
adjust by HSOD register. And HSOUT high level width can adjust by HSOHW register.
Internal VSYNC
1H
Internal HSYNC
Source
SNTx
1H
VSOUT
VSOD=’h1
HSOD
HSOUT
HSOHW
1H
HSOD
HSOHW
Figure 71
The state transition of the RSP LCD driver (display modes) compliant with MIPI DCS is as follows:
Figure 72
Notes: 1. A specified sequence is executed during each state transition. For details, see the description
of each sequence.
2. Do not transit to states not defined.
3. Turn on Peripheral Command Packet and Shutdown Peripheral Command Packet is
supported in only DSI Video mode.
(2-b) HWRESET sequence (RESX= Low ->High) Deep stand by Sleep mode on
Sleep out
(3) exit_sleep_mode sequence 11h:exit_sleep_mode Sleep mode on
Display off
Sleep mode off Sleep mode off
(3-a) 11h:exit_sleep_mode
Display off/on Display off/on
Turn on Peripheral Command
DSI : Data Type=0x32
Power off
Power on
Sleep_mode off
Set display on 29h
Note : Wait 1 frame(max.)
Power off
Power off
Figure 73
HWRESET (RESX=Low)
Figure 74
The following figure shows a gamma correction circuit. Two ends of the 168-step ladder resistors for
positive grayscale are connected to VPLVL and VGS. Those for negative grayscale are connected to
VGS (GND) and VNLVL.
Vx0, Vx4, Vx8, Vx15, Vx31, Vx55, Vx79, Vx127.5 Vx176, Vx200, Vx224, Vx240, Vx247, Vx251,
and Vx255 are grayscale reference levels. The reference levels can be adjusted by register. Voltage
between VPLVL and VGS (GND), and voltage between VGS (GND) and VNLVL is divided by ladder
resistors. The divided voltage is selected by selectors, and then, grayscale reference levels are output.
For other grayscale levels, see “Grayscale Voltage Calculation Formula.” The amplifiers for the
selectors are divided into three kinds: ones for R dots, ones for G dots, and ones for B dots.
Note: Vx0 to Vx255 mean positive grayscale voltages VP0 to VP255 and negative grayscale voltages
VN0 to VN255
VPLVL
Grayscale reference
level for positive
AMP. polarity
VP0
Positive
polarity VP4
VP8
1R VP15
1R VP31
1R VP55
VP79
Selector
127R 128 to 1
VP127.5
VP176
168R
VP200
VP224
VP240
Selector
1R 127R 128 to 1
VP247
VP251
1R
VP255
VGS(GND)
Negative VN255
polarity
VN251
1R VN247
1R VN240
VN224
VN200
168R VN79
VN55
VN31
VN15
1R Selector
VN8
128 to 1 VN4
1R 127R
VN0
1R
AMP. Grayscale reference
level for negative
polarity
VNLVL
Figure 75
A table below shows grayscale reference levels to be adjusted. Each reference level is set by a 7-bit
gamma correction register that generates a grayscale reference level. Each of the gamma correction
registers for positive polarity and negative polarity consists of 7-bit registers (total: 105 bits).
Table 72
Gamma correction register
Grayscale reference level
Positive polarity Negative polarity
Vx0 VGMP0[6:0] VGMN0[6:0]
Vx4 VGMP1[6:0] VGMN1[6:0]
Vx8 VGMP2[6:0] VGMN2[6:0]
Vx15 VGMP3[6:0] VGMN3[6:0]
Vx31 VGMP4[6:0] VGMN4[6:0]
Vx55 VGMP5[6:0] VGMN5[6:0]
Vx79 VGMP6[6:0] VGMN6[6:0]
Vx127.5 VGMP7[6:0] VGMN7[6:0]
Vx176 VGMP8[6:0] VGMN8[6:0]
Vx200 VGMP9[6:0] VGMN9[6:0]
Vx224 VGMP10[6:0] VGMN10[6:0]
Vx240 VGMP11[6:0] VGMN11[6:0]
Vx247 VGMP12[6:0] VGMN12[6:0]
Vx251 VGMP13[6:0] VGMN13[6:0]
Vx255 VGMP14[6:0] VGMN14[6:0]
Tables below shows relationships between values set in gamma correction registers and voltage.
Table 73
Register Value Voltage
Table 74
Register Value Voltage
Table 75
Grayscale Grayscale
Calculation formula Calculation formula
voltage voltage
V0 See Table 72 – Table 74. V32 (V31*3+V35)/4
V1 (V0-V4)*18/26+V4 V33 (V31*2+V35*2)/4
V2 (V0-V4)*11/26+V4 V34 (V31+V35*3)/4
V3 (V0-V4)*5/26+V4 V35 (V31-V55)*13.5/16.5+V55
V4 See Table 72 – Table 74. V36 (V35*3+V39)/4
V5 (V4-V8)*10/14+V8 V37 (V35*2+V39*2)/4
V6 (V4-V8)*6/14+V8 V38 (V35+V39*3)/4
V7 (V4-V8)*3/14+V8 V39 (V31-V55)*10.5/16.5+V55
V8 See Table 72 – Table 74. V40 (V39*3+V43)/4
V9 (V8-V15)*13/16+V15 V41 (V39*2+V43*2)/4
V10 (V8-V15)*10/16+V15 V42 (V39+V43*3)/4
V11 (V8-V15)*8/16+V15 V43 (V31-V55)*7.5/16.5+V55
V12 (V8-V15)*6/16+V15 V44 (V43*3+V47)/4
V13 (V8-V15)*4/16+V15 V45 (V43*2+V47*2)/4
V14 (V8-V15)*2/16+V15 V46 (V43+V47*3)/4
V15 See Table 72 – Table 74. V47 (V31-V55)*5/16.5+V55
V16 (V15*3+V19)/4 V48 (V47*3+V51)/4
V17 (V15*2+V19*2)/4 V49 (V47*2+V51*2)/4
V18 (V15+V19*3)/4 V50 (V47+V51*3)/4
V19 (V15-V31)*12/17+V31 V51 (V31-V55)*2.5/16.5+V55
V20 (V19*3+V23)/4 V52 (V51*3+V55)/4
V21 (V19*2+V23*2)/4 V53 (V51*2+V55*2)/4
V22 (V19+V23*3)/4 V54 (V51+V55*3)/4
V23 (V15-V31)*7/17+V31 V55 See Table 72 – Table 74
V24 (V23*3+V27)/4 V56 (V55*3+V59)/4
V25 (V23*2+V27*2)/4 V57 (V55*2+V59*2)/4
V26 (V23+V27*3)/4 V58 (V55+V59*3)/4
V27 (V15-V31)*3/17+V31 V59 (V55-V79)*8.5/10.5+V79
V28 (V27*3+V31)/4 V60 (V59*3+V63)/4
V29 (V27*2+V31*2)/4 V61 (V59*2+V63*2)/4
V30 (V27+V31*3)/4 V62 (V59+V63*3)/4
V31 See Table 72 – Table 74. V63 (V55-V79)*6.5/10.5+V79
Table 76
Grayscale Grayscale
Calculation formula Calculation formula
voltage voltage
V64 (V63*3+V67)/4 V96 (V95*3+V99)/4
V65 (V63*2+V67*2)/4 V97 (V95*2+V99*2)/4
V66 (V63+V67*3)/4 V98 (V95+V99*3)/4
V67 (V55-V79)*4.5/10.5+V79 V99 (V79-V127.5)*7.125/12.125+V127.5
V68 (V67*3+V71)/4 V100 (V99*3+V103)/4
V69 (V67*2+V71*2)/4 V101 (V99*2+V103*2)/4
V70 (V67+V71*3)/4 V102 (V99+V103*3)/4
V71 (V55-V79)*3/10.5+V79 V103 (V79-V127.5)*6.125/12.125+V127.5
V72 (V71*3+V75)/4 V104 (V103*3+V107)/4
V73 (V71*2+V75*2)/4 V105 (V103*2+V107*2)/4
V74 (V71+V75*3)/4 V106 (V103+V107*3)/4
V75 (V55-V79)*1.5/10.5+V79 V107 (V79-V127.5)*5.125/12.125+V127.5
V76 (V75*3+V79)/4 V108 (V107*3+V111)/4
V77 (V75*2+V79*2)/4 V109 (V107*2+V111*2)/4
V78 (V75+V79*3)/4 V110 (V107+V111*3)/4
V79 See Table 72 – Table 74. V111 (V79-V127.5)*4.125/12.125+V127.5
V80 (V79*3+V83)/4 V112 (V111*3+V115)/4
V81 (V79*2+V83*2)/4 V113 (V111*2+V115*2)/4
V82 (V79+V83*3)/4 V114 (V111+V115*3)/4
V83 (V79-V127.5)*11.125/12.125+V127.5 V115 (V79-V127.5)*3.125/12.125+V127.5
V84 (V83*3+V87)/4 V116 (V115*3+V119)/4
V85 (V83*2+V87*2)/4 V117 (V115*2+V119*2)/4
V86 (V83+V87*3)/4 V118 (V115+V119*3)/4
V87 (V79-V127.5)*10.125/12.125+V127.5 V119 (V79-V127.5)*2.125/12.125+V127.5
V88 (V87*3+V91)/4 V120 (V119*3+V123)/4
V89 (V87*2+V91*2)/4 V121 (V119*2+V123*2)/4
V90 (V87+V91*3)/4 V122 (V119+V123*3)/4
V91 (V79-V127.5)*9.125/12.125+V127.5 V123 (V79-V127.5)*1.125/12.125+V127.5
V92 (V91*3+V95)/4 V124 (V123*3+V127)/4
V93 (V91*2+V95*2)/4 V125 (V123*2+V127*2)/4
V94 (V91+V95*3)/4 V126 (V123+V127*3)/4
V95 (V79-V127.5)*8.125/12.125+V127.5 V127 (V79-V127.5)*0.125/12.125+V127.5
Table 77
Grayscale Grayscale
Calculation formula Calculation formula
voltage voltage
V128 (V127.5-176)*12/12.125+V176 V160 (V127.5-176)*4/12.125+V176
V129 (V128*3+V132)/4 V161 (V160*3+V164)/4
V130 (V128*2+V132*2)/4 V162 (V160*2+V164*2)/4
V131 (V128+V132*3)/4 V163 (V160+V164*3)/4
V132 (V127.5-176)*11/12.125+V176 V164 (V127.5-176)*3/12.125+V176
V133 (V132*3+V136)/4 V165 (V164*3+V168)/4
V134 (V132*2+V136*2)/4 V166 (V164*2+V168*2)/4
V135 (V132+V136*3)/4 V167 (V164+V168*3)/4
V136 (V127.5-176)*10/12.125+V176 V168 (V127.5-176)*2/12.125+V176
V137 (V136*3+V140)/4 V169 (V168*3+V172)/4
V138 (V136*2+V140*2)/4 V170 (V168*2+V172*2)/4
V139 (V136+V140*3)/4 V171 (V168+V172*3)/4
V140 (V127.5-176)*9/12.125+V176 V172 (V127.5-176)*1/12.125+V176
V141 (V140*3+V144)/4 V173 (V172*3+V176)/4
V142 (V140*2+V144*2)/4 V174 (V172*2+V176*2)/4
V143 (V140+V144*3)/4 V175 (V172+V176*3)/4
V144 (V127.5-176)*8/12.125+V176 V176 See Table 72 – Table 74.
V145 (V144*3+V148)/4 V177 (V176*3+V180)/4
V146 (V144*2+V148*2)/4 V178 (V176*2+V180*2)/4
V147 (V144+V148*3)/4 V179 (V176+V180*3)/4
V148 (V127.5-176)*7/12.125+V176 V180 (V176-V200)*9/10.5+V200
V149 (V148*3+V152)/4 V181 (V180*3+V184)/4
V150 (V148*2+V152*2)/4 V182 (V180*2+V184*2)/4
V151 (V148+V152*3)/4 V183 (V180+V184*3)/4
V152 (V127.5-176)*6/12.125+V176 V184 (V176-V200)*7.5/10.5+V200
V153 (V152*3+V156)/4 V185 (V184*3+V188)/4
V154 (V152*2+V156*2)/4 V186 (V184*2+V188*2)/4
V155 (V152+V156*3)/4 V187 (V184+V188*3)/4
V156 (V127.5-176)*5/12.125+V176 V188 (V176-V200)*6/10.5+V200
V157 (V156*3+V160)/4 V189 (V188*3+V192)/4
V158 (V156*2+V160*2)/4 V190 (V188*2+V192*2)/4
V159 (V156+V160*3)/4 V191 (V188+V192*3)/4
Table 78
Grayscale Grayscale
Calculation formula Calculation formula
voltage voltage
V192 (V176-V200)*4/10.5+V200 V224 See tables 114 and 115.
V193 (V192*3+V196)/4 V225 (V224*3+V228)/4
V194 (V192*2+V196*2)/4 V226 (V224*2+V228*2)/4
V195 (V192+V196*3)/4 V227 (V224+V228*3)/4
V196 (V176-V200)*2/10.5+V200 V228 (V224-V240)*14/17+V240
V197 (V197*3+V200)/4 V229 (V228*3+V232)/4
V198 (V197*2+V200*2)/4 V230 (V228*2+V232*2)/4
V199 (V197+V200*3)/4 V231 (V228+V232*3)/4
V200 See Table 72 – Table 74 V232 (V224-V240)*10/17+V240
V201 (V200*3+V204)/4 V233 (V232*3+V236)/4
V202 (V200*2+V204*2)/4 V234 (V232*2+V236*2)/4
V203 (V200+V204*3)/4 V235 (V232+V236*3)/4
V204 (V200-V224)*14/16.5+V200 V236 (V224-V240)*5/17+V240
V205 (V204*3+V208)/4 V237 (V236*3+V240)/4
V206 (V204*2+V208*2)/4 V238 (V236*2+V240*2)/4
V207 (V204+V208*3)/4 V239 (V236+V240*3)/4
V208 (V200-V224)*11.5/16.5+V200 V240 See Table 72 – Table 74.
V209 (V208*3+V212)/4 V241 (V240-V247)*14/16+V247
V210 (V208*2+V212*2)/4 V242 (V240-V247)*12/16+V247
V211 (V208+V212*3)/4 V243 (V240-V247)*10/16+V247
V212 (V200-V224)*9/16.5+V200 V244 (V240-V247)*8/16+V247
V213 (V212*3+V216)/4 V245 (V240-V247)*6/16+V247
V214 (V212*2+V216*2)/4 V246 (V240-V247)*3/16+V247
V215 (V212+V216*3)/4 V247 See Table 72 – Table 74.
V216 (V200-V224)*6/16.5+V200 V248 (V247-V251)*11/14+V251
V217 (V216*3+V220)/4 V249 (V247-V251)*8/14+V251
V218 (V216*2+V220*2)/4 V250 (V247-V251)*4/14+V251
V219 (V216+V220*3)/4 V251 See Table 72 – Table 74.
V220 (V200-V224)*3/16.5+V200 V252 (V251-V255)*21/26+V255
V221 (V220*3+V224)/4 V253 (V251-V255)*15/26+V255
V222 (V220*2+V224*2)/4 V254 (V251-V255)*8/26+V255
V223 (V220+V224*3)/4 V255 See Table 72 – Table 74.
V55P
V127.5P
V200P
V200N
V127.5N
V55N
Figure 76
Notes: 1. Vx0, Vx4, Vx8, Vx15, Vx31, Vx55, Vx79, Vx127.5, Vx176, Vx200, Vx224, Vx240, Vx247,
Vx251, Vx255 are “reference levels” set by gamma correction registers.
2. Set gamma correction registers to satisfy the following relationship: |Vx0| > |Vx4| > |Vx8| >
|Vx15| > |Vx31| > |Vx55| > |Vx79| >|Vx127.5|> |Vx176| > |Vx200| > |Vx224| > |Vx240| >
|Vx247| > |Vx251| > |Vx255|
3. Set gamma correction registers to satisfy the following relationship: V255P 0.2V. V255N
-0.2V.
NVM Control
The RSP LCD driver incorporates NVM.
16 bits are for Supplier Elective Data (read by read_DDB_start command (A1h))
Manufacturer Command is stored (For the Manufacturer Command stored in NVM, see
“Command Stored in NVM”)
To write, read and erase data from/to the NVM, follow the sequence below. Data on the NVM is
loaded to internal registers automatically when the sequences are performed. NVMLD register
determines whether to update data loaded from NVM to each register.
Power On sequence
HW RESET sequence
exit_sleep_mode command
soft_reset sequence
Data stored in the NVM is retained permanently even if power supply is turned off.
Table 80
Operation Power supply voltage Time Temperature
VSP 5.00 ~ 6.00V
Write/Erase
VSN -5.00 ~ -6.00V 1.7s or more
(External VSP/VSN +10C ~ +40C
DPHYVCC 1.65 ~ 1.95V after NVMFTT = 1
supply)
IOVCC 1.65~ 1.95V
Note: NVM data rewrite (erase-write) operation should be performed up to 40 times per address.
VGHP/VGLP (power supply for panel) and SOUT are GND during NVM data rewrite
operation.
The register values of User/Manufacturer Commands supposed to be stored in NVM are written to
NVM. When “1” is written to an address, the bit of the address is set to “1”. If the data is erased from
the bit, the bit is returned to ”0”. The bit to which data is not written should be set to “0”.
Note4
Power supply on
VSP,VSN NVM Load Control
IOVCC, DHPYVCC Read Verify Status
Command:D6h
Command: E6h
1st Parameter: 01h NVMVFFLGER
GND 0 : Fail (Note1) 1 : Pass
Exit Sleep mode
NVMVFFLGWR
Command:11h
0 : Fail 1 : Pass
Wait for
TE Output Status (TEM=1)
more than 120ms
The result of verification is outputted from
TE output.
Power on reset VCOM NVM Write Data Set TE = 1 : Pass
(Hard ware reset) Command: D5h TE = 0 : Fail
WCVDC=1, WCVDCB=1
Set_Display_On
Wait for
Command 29h
more than 3ms
Adjust VDC & VDCB value
Sleep in State NVM Access Protect On
Manufacture Command Access Disable Set_Display_Off Command: E6h
(Protect ON) Command 28h NVMAEN=0
NVM Access Disable NVMFTT=0
(Protect ON) Enter Sleep mode TEM=0
Command:10h
Manufacturer Command Access
Protect off Wait more
MCAP=3’b100 than 120ms
NVM Write Data Set (initial Setting) NVM Access Protect Off
Verify output Setting and Write Start
Manufacturer Command Command: E6h
NVMAEN=1
NVMFTT=1
TEM=1
Figure 77
Abnormal Sequence
When the externally applied voltage level drops or the low level of RESX is detected during Sleep
mode off, executes the abnormal sequence and enters Sleep mode on.
Interface
RESX=Low during Display Operation.
RESX
DSP
Internal clock
OSC
Power Supply
IOVCC GND
DPHYVCC GND
VSP GND
VSN GND
(internal detection signal)
Output Voltage
VCI GND
VDD GND
VGH GND
GND
VGL
VCL GND
VPLVL GND
VNLVL GND
GND
VCOMDC
VCOM
Notes: 1. If verify operation to verify whether data is erased fails before write operation, write operation is not performed.
2. If power is turned on when data has not been written, data set to “0” is loaded from NVM.
Set the defaults of all the commands at “Initial Setting” after power is turned on. Then, write the data to NVM.
3. To change the number of lanes when data is written to NVM via DSI, execute this sequence after changing the number
of lanes.
4. When VCOM is not adjusted by VDC, this sequence is unnecessary.
Revision Record
176 Add restriction : NL : need wait time between data transfer and NL
180 Error correction ; delete EQW1, EQW2
181 Erro correction EQW3,6,8,9 -> EQW3,6,8,16 EQW5,7,9,16 -> EQW5,7,9,17
196 Add description SOUTABSPLx, SOUTABSPLEN
281 Add description : Can use CABC and ACO at same time
287 Add description of Local Area ACO
0.04 2014/01/31 11 Error correction : DPHYVCC voltage range
144 Add restriction : not support DSTB command in case of BFh/5th para = 00h
194 Error correction : CE on/off setting Disable <-> Enable
202 Add specification :
Recommended voltage: (voltage set by BT2) – (voltage set by VLM2) ≦ 2V
247 Error correction: Delete “CS x6” because CSX is test pin.
260 Error correction : A1h’s write type 15h, 39h= yes (because of using this command to
write data and read data)
0.2 2014.06.03 37 Error correction : rigih side figure Top -> Bottom
39,40,41 Specification change : remove “TBD”
40 Add specification : Icin4/5 1600RGB(HRE1=3’h0)