X1500 Iot Application Processor: Data Sheet

X1500
IoT Application Processor

Data Sheet
Release Date: Feb. 8, 2017

X1500 IoT Application Processor
Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
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CONTENTS
CONTENTS
1 Overview .......................................................................................... 1
1.1 Block Diagram ......................................................................................................................... 1
1.2 Features .................................................................................................................................. 1
1.2.1 CPU Core ........................................................................................................................ 1
1.2.2 Image Core ...................................................................................................................... 2
1.2.3 Display/Camera/Audio ..................................................................................................... 2
1.2.4 Memory Interface ............................................................................................................ 3
1.2.5 System Functions ............................................................................................................ 3
1.2.6 Peripherals ...................................................................................................................... 5
1.2.7 Bootrom ........................................................................................................................... 7
2 Pinout Information ............................................................................ 8

2.1 Pin Map ................................................................................................................................... 8
2.2 Pin Descriptions .................................................................................................................... 10
2.2.1 GPIO Group A ............................................................................................................... 10
2.2.2 GPIO Group B ................................................................................................................ 11
2.2.3 GPIO Group C ............................................................................................................... 12
2.2.4 GPIO Group D ............................................................................................................... 13
2.3 X1500 FUNCTION PIN DESCRIPTION ............................................................................... 13
2.4 X1500 FUNCTION DESCRIPTION ...................................................................................... 16
3 Electrical Specifications .................................................................. 19

3.1 Absolute Maximum Ratings .................................................................................................. 19
3.2 Recommended operating conditions .................................................................................... 20
3.3 DC Specifications .................................................................................................................. 21
3.4 Power On, Reset and BOOT ................................................................................................ 23
3.4.1 Power-On Timing........................................................................................................... 23
3.4.2 Reset procedure ............................................................................................................ 25
3.4.3 BOOT ............................................................................................................................ 26
4 Packaging Information .................................................................... 28

4.1 Overview ............................................................................................................................... 28
4.2 X1500 Device Dimensions .................................................................................................... 28
4.3 Solder Ball Materials ............................................................................................................. 29
4.4 Moisture Sensitivity Level ..................................................................................................... 29
5 PCB Mounting Guidelines............................................................... 30

5.1 RoHS compliance ................................................................................................................. 30
5.2 Reflow profile ........................................................................................................................ 30
i
X1500 IoT Application Processor Data Sheet
TABLES
TABLES
Table 2-1 GPIO Group A Pinmux(30) .................................................................................................. 10
Table 2-2 GPIO Group B Pinmux(15) .................................................................................................. 11
Table 2-3 GPIO Group C Pinmux(8) .................................................................................................... 12
Table 2-4 GPIO Group D Pinmux(6) .................................................................................................... 13
Table 2-5 X1500 function pin description ............................................................................................. 13
Table 2-6 X1500 Function Description ................................................................................................. 16
Table 3-1 Absolute Maximum Ratings ................................................................................................. 19
Table 3-2 Recommended operating conditions for power supplies ..................................................... 20
Table 3-3 Recommended operating conditions for VDDMEM supplied pins ....................................... 20
Table 3-4 Recommended operating conditions for VDDIO/VDDIO_5T/VDDRTC supplied pins ........ 20
Table 3-5 Recommended operating conditions for others ................................................................... 20
Table 3-6 DC characteristics for VREFMEM ............................................................................................. 21
Table 3-7 DC characteristics for VDDmem supplied pins in LPDDR application ................................ 21
Table 3-8 DC characteristics for VDDIO/VDDIO_5T/VDDRTC supplied pins for 1.8V application ..... 21
Table 3-9 DC characteristics for VDDIO/VDDIO_5T/VDDRTC supplied pins for 2.5V application ..... 22
Table 3-10 DC characteristics for VDDIO/VDDIO_5T/VDDRTC supplied pins for 3.3V application ... 22
Table 3-11 Power-On Timing Parameters ........................................................................................... 23
Table 3-12 Boot Configuration of X1500 ........................................................................................... 26
i
FIGURES
FIGURES
Figure 1-1 X1500 Diagram ..................................................................................................................... 1
Figure 2-1 X1500 pin to ball assignment ............................................................................................... 9
Figure 3-1 Power-On Timing Diagram ................................................................................................. 25
Figure 3-2 Boot flow diagram of X1500 ............................................................................................... 27
Figure 4-1 X1500 package outline drawing ......................................................................................... 29
i
Overview
1 Overview
X1500 is a low power consumption, high performance and high integrated application processor, the
application is focus on IoT devices. And it can match the requirements of many other embedded
products.
NAME SIP LPDDR
X1500 32MB
1.1 Block Diagram
Figure 1-1 X1500 Diagram
1.2 Features
1.2.1 CPU Core

®
 MIPS-Based XBurst cores (up to 1.0GHz)
®
 MIPS-Based XBurst CPU
®
– XBurst RISC instruction set
®
– XBurst SIMD instruction set
®
– XBurst FPU instruction set supporting both single and double floating point format
which are IEEE754 compatible
1
Overview
®
– XBurst 9-stage pipeline micro-architecture
 MMU
– 32-entry joint-TLB
– 4 entry Instruction TLB
– 4 entry data TLB
 L1 Cache
– 16KB instruction cache
– 16KB data cache
 Hardware debug support
 16KB tight coupled memory
 L2 Cache
– 128KB unify cache
 The XBurst® processor system supports little endian only
1.2.2 Image Core

 Hardware JPEG encoder
– Baseline ISO/IEC 10918-1 JPEG compliant
– 8-bit pixel depth support
– Support for YUY2 ([Y0,U0,Y1,V0]) color
– Up to four programmable Quantization tables
– Fully programmable Huffman tables
– Image size up to 2M pixels
1.2.3 Display/Camera/Audio
 Camera interface module
– Input image size up to 2M pixels
– Integrated DMA
– Supported data format: YCbCr 4:2:2
– Supports ITU656 (YCbCr 4:2:2) input
– Configurable VSYNC and HSYNC signals: active high/low
– Configurable PCLK: active edge rising/falling
– PCLK max. 80MHz
– Configurable output order
 Low power DMIC Controller
– 16 bits data interface and 20bit precision internal controller.
– SNR: 90dB, THD: -90dB @ FS -20dB
– Linear high pass filter include. Attenuation: -2.9dB@100Hz, -22dB@27Hz. -36dB@10Hz
– Low power voice trigger when waiting to start talking.
– 1 to 4 channel MIC support.
– Support voice data pre-fetch when trigger enable and the data interface disable, but do
not increase the power dissipation.
2
Overview
– Sample rate supported: 8k, 16k.

– Support low power mode
1.2.4 Memory Interface

 DDR Controller
– Support LPDDR, DDR2, DDR3
– 16 bit data width
– Support size up to 1GB (1 chip select, 3-bit Bank,15-bit Row, 11-bit Column,)
– Asynchornize to system bus and each port.
– Support clock-stop mode
– Support auto self-refresh mode
– Support power-down mode and deep-power-down mode
– Programmable DDR timing parameters
– Programmable DDR row and column address width and order
 32MB SIP LPDDR
 Serial nand/nor flash interface(SFC)

– SPI protocol support: Standard, Dual, Quad SPI
– Standard I/O data transfer up to 80Mbits/s
– Dual I/O data transfer up to 160Mbits/s
– Quad I/O data transfer up to 240Mbits/s
– transmit-only or receive-only operation
– MSB always be first in intra transfer of one byte. Least Significant Byte first for inter
transfer of data bytes, and Most Significant Byte first for inter transfer of command or
address bytes.
– one device select
– Configurable sampling point for reception
– Configurable timing parameters: tSLCH, tCHSH and tSHSL
– Configurable flash address wide are supported
– 7 transfer formats: Standard SPI, Dual-Output/Dual-Input SPI, Quad-Output/Quad-Input
SPI, Dual-I/O SPI, Quad-I/O SPI, Full Dual-I/O SPI, Full Quad-I/O SPI
– two data transfer mode: slave mode and DMA mode
– Configurable 6 phases for software flow
1.2.5 System Functions

 Clock generation and power management
– On-chip oscillator circuit (support 24MHz, 26MHz)
– Two phase-locked loops (PLL) with programmable multiplier
– CCLK, HHCLK, H2CLK, PCLK, H0CLK, DDR_CLK frequency can be changed
separately for software by setting registers
– Functional-unit clock gating
3
Overview
– Supply block power shut down
 Timer and counter unit with PWM output and/or input edge counter
– Provide 5 channels, all can generate PWM, two of them have input signal transition edge
counter
– 16-bit A counter and 16-bit B counter with auto-reload function every channel
– Support interrupt generation when the A counter underflows
– Three clock sources: RTCLK (real time clock), EXCLK (external clock input), PCLK (APB
Bus clock) selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected
 OS timer
– One channel
– 32-bit counter and 32-bit compare register
– Support interrupt generation when the counter matches the compare register
– Three clock sources: RTCLK (real time clock), EXCLK (external clock input), PCLK (APB
Bus clock) selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected
 Interrupt controller
– Total 64 interrupt sources
– Each interrupt source can be independently enabled
– Priority mechanism to indicate highest priority interrupt
– All the registers are accessed by CPU and PDMA
– Unmasked interrupts can wake up the chip in sleep mode
– Another set of source, mask and pending registers to serve for PDMA
 Watchdog timer
– Generates WDT reset
– A 16-bit Data register and a 16-bit counter
– Counter clock uses the input clock selected by software
 PCLK, EXTAL and RTCCLK can be used as the clock for counter
 The division ratio of the clock can be set to 1, 4, 16, 64, 256 and 1024 by software
 PDMA Controller
– Support up to 8 independent DMA channels
– Descriptor or No-Descriptor Transfer mode
®
– A simple Xburst -1 CPU supports smart transfer mode controlled by programmable
firmware
– Transfer data units: 1-byte, 2-byte, 4-byte, 16-byte, 32-byte, 64-byte, 128-byte
24
– Transfer number of data unit: 1 ~ 2 -1
– Independent source and destination port width: 8-bit, 16-bit, 32-bit
– Fixed three priorities of channel groups: 0~3, highest; 4~11: mid; 12~31: lowest
– An extra INTC IRQ can be bound to one programmable DMA channel
4
Overview
 RTC (Real Time Clock)

– Need external 32768Hz oscillator for 32KHz clock generation.
– RTCLK selectable from the oscillator or from the divided clock of EXCLK, so that 32k
crystal can be absent if the hibernating mode is not needed
– 32-bits second counter
– Programmable and adjustable counter to generate accurate 1 Hz clock
– Alarm interrupt, 1Hz interrupt
– Stand alone power supply, work in hibernating mode
– Power down controller
– Alarm wakeup
– External pin wakeup with up to 2s glitch filter
1.2.6 Peripherals
 General-Purpose I/O ports
– Each port can be configured as an input, an output or an alternate function port
– Each port can be configured as an interrupt source of low/high level or rising/falling edge
triggering. Every interrupt source can be masked independently
– Each port has an internal pull-up or pull-down resistor connected. The pull-up/down
resistor can be disabled
– GPIO output 4 interrupts, 1 for every group, to INTC
 Three I2C Controller (I2C0, I2C1, I2C2)

– Two-wire I2C serial interface – consists of a serial data line (SDA) and a serial clock
(SCL)
– Two speeds
 Standard mode (100 Kb/s)
 Fast mode (400 Kb/s)
– Device clock is identical with pclk
– Programmable SCL generator
– Master or slave I2C operation
– 7-bit addressing/10-bit addressing
– -level transmit and receive FIFOs
– Interrupt operation
– The number of devices that you can connect to the same I2C-bus is limited only by the
maximum bus capacitance of 400pF
 One Synchronous serial interfaces (SSI0)

– 3 protocols support: National’s Microwire, TI’s SSP, and Motorola’s SPI
– Full-duplex or transmit-only or receive-only operation
– Programmable transfer order: MSB first or LSB first
– Configurable normal transfer mode or Interval transfer mode
– Programmable clock phase and polarity for Motorola’s SSI format
5
Overview
– Two slave select signal (SSI0_CE0_ / SSI0_CE1_) supporting up to 2 slave devices

– Back-to-back character transmission/reception mode
– Loop back mode for testing
– Data transfer up to 30Mbits/s
 Three UARTs (UART0, UART1, UART2)

– Full-duplex operation
– 5-, 6-, 7- or 8-bit characters with optional no parity or even or odd parity and with 1, 1½,
or 2 stop bits
– Independently controlled transmit, receive (data ready or timeout), line status interrupts
– Internal diagnostic capability Loopback control and break, parity, overrun and
framing-error is provided
– Separate DMA requests for transmit and receive data services in FIFO mode
– Supports modem flow control by software or hardware
– Slow infrared asynchronous interface that conforms to IrDA specification
 One MMC/SD/SDIO controllers

– Fully compatible with the MMC System Specification version 4.5
– Support SD Specification 3.0
– Support SD I/O Specification 1.0 with 1 command channel and 4 data channels
– Consumer Electronics Advanced Transport Architecture (CE-ATA – version 1.1)
– Maximum data rate is 50Mbps
– Both support MMC data width 1bit ,4bit
– Built-in programmable frequency divider for MMC/SD bus
– Built-in Special Descriptor DMA
– Mask-able hardware interrupt for SDIO interrupt, internal status and FIFO status
– Multi-SD function support including multiple I/O and combined I/O and memory
– IRQ supported enable card to interrupt MMC/SD controller
– Single or multi block access to the card including erase operation
– Stream access to the MMC card
– Supports SDIO read wait, interrupt detection during 1-bit or 4-bit access
– Supports CE-ATA digital protocol commands
– Support Command Completion Signal and interrupt to CPU
– Command Completion Signal disable feature
– The maximum block length is 4096bytes
 USB 2.0 OTG interface

– Complies with the USB 2.0 standard for high-speed (480 Mbps) functions and with the
On-The-Go supplement to the USB 2.0 specification
– Operates either as the function controller of a high- /full-speed USB peripheral or as the
host/peripheral in point-to-point or multi-point communications with other USB functions
– Supports Session Request Protocol (SRP) and Host Negotiation Protocol (HNP)
– UTMI+ Level 3 Transceiver Interface
6
Overview
– Soft connect/disconnect
– 8 endpoints in device mode, 16 channels for host mode.
– Dedicate FIFO
– Supports control, interrupt, ISO and bulk transfer
 OTP Slave Interface

– Total 1Kb.
1.2.7 Bootrom
16KB Boot ROM memory
7
Pinout Information
2 Pinout Information
2.1 Pin Map
The X1500 pin to ball assignment is shown in Figure 2-1.
8
Pinout Information
X1500 Ball Assignment Ver1.1

BGA109, 8mm X 8mm X 1.2mm, 0.65pitch, top view
0 1 2 3 4 5 6 7 8 9 10 11 12
SFC_HOLD_
UART0_TX UART0_CT SFC_CE_SSI0_ SFC_WP_SSI0_ CIM_D1_PA
A D_PC11 S_PC12 CE0_PA27
SSI0_GPC_P
CE1_PA30 ZQ VREF0 CIM_D3_PA16
18
CIM_D5_PA14 CIM_D4_PA15 CIM_D7_PA12
A31
UART0_RX UART0_RT SFC_CLK_SSI0 SFC_DR_SSI SFC_DT_SSI0_ CIM_D2_PA CIM_VSYN_PA1
B D_PC10 S_PC13 _CLK_PA26 0_DR_PA28 DT_PA29 17
CIM_D0_PA19 CIM_D6_PA13 0
DMIC0_IN_ CIM_HSYN_PA0
C PB22
AVDEFUSE CIM_MCLK_PA11
9
MSC0_CMD_
I2C0_SDA_ I2C0_SCK_
D PB24 PB23
VDDMEM VDDMEM VDDMEM VSS CIM_PCLK_PA08 SSI0_CE0_PA
25
MSC0_CLK_S
PWM0_PC2 PWM4_PC2 MSC0_D0_SSI
E 5 4 VSS VSS VDDMEM VDDMEM VSS VSS 0_DR_PA23
SI0_CLK_PA2
4
I2C1_SDA_ I2C1_SCK_
MSC0_D2_SSI MSC0_D1_SS
F PWM2_PC2 PWM1_PC2 VSS VSS VDD VDD 0_CE1_PA21 I0_DT_PA22
7 6
BOOT_SEL BOOT_SEL UART1_TXD_PA0 MSC0_D3_SS
G 0_PB28 1_PB29 VSS VSS VDD VDD 5 I0_GPC_PA20
UART2_RXD_ UART2_TXD_
UART1_RXD_PA0
H UART1_RTS_ UART1_CTS_ VSS VSS VSS VDDIO VDDIO VDD 4
I2C1_SDA_PA01
PD05 PD04
SSI0_DR_U SSI0_DT_U
UART2_RXD_PA0 UART2_TXD_PA
J ART1_TXD_ ART1_RXD VSS VSS VDDIO_5V VDDIO OTG_VBUS 2 03
PD03 _PD02
SSI0_CLK_I SSI0_CE0_I
K 2C2_SCK_P 2C2_SDA_P VSSRTC PLL_AVSS AVSOTG OTG_ID PWM3_PB06 I2C1_SCK_PA00
D00 D01
I2S_MCLK_ I2S_BCLK_ I2S_LRCLK_PB DRV_VBUS_P EXCLK_

L PB00 PB01 02
WKUP_PB31 PPRST_ RTCLK PWRON B25
OTG_DM AVDOTG25
O
I2S_DI_PB0 I2S_DO_PB DMIC1_IN_PB0 DMIC_CLK_P OTG_TXR_RK
M 3 04 5 B21
LDOOUT XRTCLK VDDRTC PLL_AVDD EXCLK_I L
OTG_DP AVDOTG
Figure 2-1 X1500 pin to ball assignment
9
Pinout Information
2.2 Pin Descriptions
2.2.1 GPIO Group A

Table 2-1 GPIO Group A Pinmux(30)
Ball Pull Driven Slewrate Extra

Ball Name In/Out Pull Schmitt GPIO Func0 Func1 Func2 Power
No. Default Strength limitate Func
K12 I2C1_SCK_PA00 IO PU Enable 8mA No GPA[0] I2C1_SCK WKUP VDDIO

H12 I2C1_SDA_PA01 IO PU Enable 8mA No GPA[1] I2C1_SDA WKUP VDDIO
J11 UART2_RXD_PA02 IO PU Enable 8mA No GPA[2] UART2_RXD WKUP VDDIO
J12 UART2_TXD_PA03 IO PU Enable 8mA No GPA[3] UART2_TXD WKUP VDDIO
H11 UART1_RXD_PA04 IO PU Enable 8mA No GPA[4] UART1_RXD WKUP VDDIO
G11 UART1_TXD_PA05 IO PU Enable 8mA No GPA[5] UART1_TXD WKUP VDDIO
D11 CIM_PCLK_PA08 IO PU Enable 8mA No GPA[8] CIM_PCLK WKUP VDDIO
C12 CIM_HSYN_PA09 IO PU Enable 8mA No GPA[9] CIM_HSYN WKUP VDDIO
B12 CIM_VSYN_PA10 IO PU Enable 8mA No GPA[10] CIM_VSYN WKUP VDDIO
C11 CIM_MCLK_PA11 IO PU Enable 8mA No GPA[11] CIM_MCLK WKUP VDDIO
A12 CIM_D7_PA12 IO PU Enable 8mA No GPA[12] CIM_D7 WKUP VDDIO
B11 CIM_D6_PA13 IO PU Enable 8mA No GPA[13] CIM_D6 WKUP VDDIO
10
Pinout Information

G12 MSC0_D3_SSI0_GPC_PA20 IO PU Enable 8mA No GPA[20] MSC0_D3 SSI0_GPC WKUP VDDIO
F11 MSC0_D2_SSI0_CE1_PA21 IO PU Enable 8mA No GPA[21] MSC0_D2 SSI0_CE1 WKUP VDDIO
F12 MSC0_D1_SSI0_DT_PA22 IO PU Enable 8mA No GPA[22] MSC0_D1 SSI0_DT WKUP VDDIO
E11 MSC0_D0_SSI0_DR_PA23 IO PU Enable 8mA No GPA[23] MSC0_D0 SSI0_DR WKUP VDDIO
E12 MSC0_CLK_SSI0_CLK_PA24 IO PU Enable 8mA No GPA[24] MSC0_CLK SSI0_CLK WKUP VDDIO
D12 MSC0_CMD_SSI0_CE0_PA25 IO PU Enable 8mA No GPA[25] MSC0_CMD SSI0_CE0 WKUP VDDIO
B3 SFC_CLK_SSI0_CLK_PA26 IO PU Enable 8mA No GPA[26] SFC_CLK SSI0_CLK WKUP VDDIO
A3 SFC_CE_SSI0_CE0_PA27 IO PU Enable 8mA No GPA[27] SFC_CE SSI0_CE0 WKUP VDDIO
B4 SFC_DR_SSI0_DR_PA28 IO PU Enable 8mA No GPA[28] SFC_DR SSI0_DR WKUP VDDIO
B5 SFC_DT_SSI0_DT_PA29 IO PU Enable 8mA No GPA[29] SFC_DT SSI0_DT WKUP VDDIO
A5 SFC_WP_SSI0_CE1_PA30 IO PU Enable 8mA No GPA[30] SFC_WP SSI0_CE1 WKUP VDDIO
A4 SFC_HOLD_SSI0_GPC_PA31 IO PU Enable 8mA No GPA[31] SFC_HOLD SSI0_GPC WKUP VDDIO
2.2.2 GPIO Group B

Table 2-2 GPIO Group B Pinmux(15)

L1 I2S_MCLK_PB00 IO PU Enable 8mA No GPB[0] I2S_MCLK WKUP VDDIO
L2 I2S_BCLK_PB01 IO PU Enable 8mA No GPB[1] I2S_BCLK WKUP VDDIO
L3 I2S_LRCLK_PB02 IO PU Enable 8mA No GPB[2] I2S_LRCLK WKUP VDDIO
M1 I2S_DI_PB03 IO PU Enable 8mA No GPB[3] I2S_DI WKUP VDDIO
M2 I2S_DO_PB04 IO PU Enable 8mA No GPB[4] I2S_DO WKUP VDDIO
M3 DMIC1_IN_PB05 IO PU Enable 8mA No GPB[5] DMIC1_IN WKUP VDDIO
11
Pinout Information
K11 PWM3_PB06 IO PU Enable 8mA No GPB[6] PWM3 WKUP VDDIO

M4 DMIC_CLK_PB21 IO PU Enable 8mA No GPB[21] DMIC_CLK WKUP VDDIO
C1 DMIC0_IN_PB22 IO PU Enable 8mA No GPB[22] DMIC0_IN WKUP VDDIO
D2 I2C0_SCK_PB23 IO PU Enable 8mA No GPB[23] I2C0_SCK WKUP VDDIO
D1 I2C0_SDA_PB24 IO PU Enable 8mA No GPB[24] I2C0_SDA WKUP VDDIO
L8 DRV_VBUS_PB25 IO PD Enable 8mA No GPB[25] DRV_VBUS WKUP VDDIO
G1 BOOT_SEL0_PB28 IO PU Disable 8mA No GPB[28] BOOT_SEL0 WKUP VDDIO
G2 BOOT_SEL1_PB29 IO PU Disable 8mA No GPB[29] BOOT_SEL1 WKUP VDDIO
L4 WKUP_PB31 IO PU Enable 8mA Yes GPB[31] WKUP WKUP VDDRTC
2.2.3 GPIO Group C

Table 2-3 GPIO Group C Pinmux(8)

B1 UART0_RXD_PC10 IO PU Enable 8mA No GPC[10] UART0_RXD WKUP VDDIO
A1 UART0_TXD_PC11 IO PU Enable 8mA No GPC[11] UART0_TXD WKUP VDDIO
A2 UART0_CTS_PC12 IO PU Enable 8mA No GPC[12] UART0_CTS WKUP VDDIO
B2 UART0_RTS_PC13 IO PU Enable 8mA No GPC[13] UART0_RTS WKUP VDDIO
E2 PWM4_PC24 IO PU Enable 8mA No GPC[24] PWM4 WKUP VDDIO
E1 PWM0_PC25 IO PD Enable 8mA No GPC[25] PWM0 WKUP VDDIO
F2 I2C1_SCK_PWM1_PC26 IO PU Enable 8mA No GPC[26] I2C1_SCK PWM1 WKUP VDDIO
F1 I2C1_SDA_PWM2_PC27 IO PU Enable 8mA No GPC[27] I2C1_SDA PWM2 WKUP VDDIO
12
Pinout Information
2.2.4 GPIO Group D

Table 2-4 GPIO Group D Pinmux(6)
Ball In/ Pull Driven Slewrate Extra

Ball Name Pull Schmitt GPIO Func0 Func1 Func2 Power
No. Out Default Strength limitate Func
K1 SSI0_CLK_I2C2_SCK_PD00 IO PU Enable 8mA No 5V GPD[0] SSI0_CLK I2C2_SCK WKUP VDDIO_5T
K2 SSI0_CE0_I2C2_SDA_PD01 IO PU Enable 8mA No 5V GPD[1] SSI0_CE0 I2C2_SDA WKUP VDDIO_5T
J2 SSI0_DT_UART1_RXD_PD02 IO PU Enable 8mA No 5V GPD[2] SSI0_DT UART1_RXD WKUP VDDIO_5T
J1 SSI0_DR_UART1_TXD_PD03 IO PU Enable 8mA No 5V GPD[3] SSI0_DR UART1_TXD WKUP VDDIO_5T
H2 UART2_TXD_UART1_CTS_PD04 IO PU Enable 8mA No 5V GPD[4] UART2_TXD UART1_CTS WKUP VDDIO_5T
H1 UART2_RXD_UART1_RTS_PD05 IO PU Enable 8mA No 5V GPD[5] UART2_RXD UART1_RTS WKUP VDDIO_5T
2.3 X1500 FUNCTION PIN DESCRIPTION

Table 2-5 X1500 function pin description
Ball No. Pin Names IO Power Pin Description
Memory
A6 ZQ DDR PHY ZQ calibration resistor
A7 VREF0 DDR PHY VREF
Power and Ground
D5 VDDMEM P - IO digital power for DRAM 1.8V
13
Pinout Information
E6 VDDMEM P - IO digital power for DRAM 1.8V

E7 VDDMEM P - IO digital power for DRAM 1.8V
H7 VDDIO P - IO digital power for none DRAM 1.8~3.3V
H8 VDDIO P - IO digital power for none DRAM 1.8~3.3V
J8 VDDIO P - IO digital power for none DRAM 1.8~3.3V
J7 VDDIO_5T P - IO digital power for none DRAM (5V tolerant)
D8 VSS P - Core digital gound for none DRAM and CORE digital ground, 0V
E4 VSS P - Core digital gound for none DRAM and CORE digital ground, 0V
F4 VSS P - Core digital gound for none DRAM and CORE digital ground, 0V
F5 VSS P - Core digital gound for none DRAM and CORE digital ground, 0V
G4 VSS P - Core digital gound for none DRAM and CORE digital ground, 0V
G5 VSS P - Core digital gound for none DRAM and CORE digital ground, 0V
H4 VSS P - Core digital gound for none DRAM and CORE digital ground, 0V
J5 VSS P - Core digital gound for none DRAM and CORE digital ground, 0V
J6 VSS P - Core digital gound for none DRAM and CORE digital ground, 0V
F8 VDD P - CORE digital power, 1.2V
F9 VDD P - CORE digital power, 1.2V
G8 VDD P - CORE digital power, 1.2V
G9 VDD P - CORE digital power, 1.2V
H9 VDD P - CORE digital power, 1.2V
USB OTG
14
Pinout Information
M11 USB_DP0(OTG_DP) AIO AVDOTG USB OTG data plus

L11 USB_DM0(OTG_DM) AIO AVDOTG USB OTG data minus
USB 5-V power supply pin for USB OTG. An external charge pump must provide
J10 USB_VBUS(OTG_VBUS) AIO 5V
power to this pin
USB mini-receptacle identifier. It differentiates a mini-A from a mini-B plug. If this
K10 USB_ID(OTG_ID) AI AVDOTG25
signal is not used, internal resistance pulls the signal’s voltage level to AVDUSB25.
Transmitter resister tune. It connects to an external resistor of 43.2Ω with 1%
M10 OTG_TXR_RKL AIO AVDOTG25
tolerance to analog ground, that adjusts the USB 2.0 high-speed source impedance
M12 AVDOTG P - USB analog power.3.3V
K9 AVSOTG P - USB analog ground.
L12 AVDOTG25 P - USB OTG analog power, 2.5V
EFUSE
C2 AVDEFUSE P AVEFUSE EFUSE programming power, 0V/2.5V
CPM
M9 EXCLK_XI(EXCLK_I) AI VDDIO OSC input.
L9 EXCLK_XO(EXCLK_O) AO VDDIO OSC output.
M8 PLL_AVDD P - PLL analog power, 1.2V
K8 PLL_AVSS P - PLL analog ground
RTC
L6 RTCLK AI VDDRTC OSC input or 32768Hz clock input
L7 PWRON O VDDRTC Power on/off control of main power
L5 PPRST_ I VDDRTC RTC power on reset and RESET-KEY reset input
M5 LDOOUT P - capacitor pin for RTC LDO need a 1nF decoupling capacitor to ground
K7 VSSRTC P - RTC ground
VDDRTC: 3.3V power for RTC and hibernating mode controlling that never power
M7 VDDRTC P -
down(normally you can use 1.8V instead to reduce power consumption)
15
Pinout Information
2.4 X1500 FUNCTION DESCRIPTION

Table 2-6 X1500 Function Description
Signal Name In/Out Description
CIM(Camera Interface)
CIM_PCLK Input CIM pixel clock input
CIM_HSYN Input CIM line horizonal sync input
CIM_VSYN Input CIM vertical sync input
CIM_MCLK Output CIM master clock output
CIM_D7 Input CIM data input bit 7
I2S
I2S_MCLK Output I2S master clock out
I2S_BCLK Bidirection I2S bit clock
I2S_LRCLK Bidirection I2S LR clock
I2S_DI Input I2S data input
I2S_DO Output I2S data output
DMIC
DMIC0_IN Input Digital MIC data input(Front/Back channel)
DMIC1_IN Input Digital MIC data input(Left/Right channel)
16
Pinout Information
DMIC_CLK Output Digital MIC clock output

SFC
SFC_CLK Output Serial Flash clock output
SFC_CE_ Output Serial Flash chip enable
SFC_DR Bidirection Serial Flash data input
SFC_DT Bidirection Serial Flash data output
SFC_WP Bidirection Serial Flash write protect signal
SFC_HOLD Bidirection Serial Flash hold signal
PWM
PWMn Bidirection PWM output or pulse input channel n
I2C
I2Cn_SCK Bidirection I2C n serial clock
I2Cn_SDA Bidirection I2C n serial data
SSI
SSIn_CLK Output SSI n clock output
SSIn_CE0_ Output SSI n chip enable 0
SSIn_CE1_ Output SSI n chip enable 1
SSIn_GPC Output SSI n general-purpose control signal
SSIn_DT Output SSI n data output
SSIn_DR Input SSI n data input
UART
UARTn_RXD Input UART n receiving data
UARTn_TXD Output UART n transmitting data
UARTn_CTS_ Input UART Clear to send control
UARTn_RTS_ Output UART Request to send control
MSC
17
Pinout Information
MSCn_D3 Bidirection MSC(MMC/SD) n data bit 3

MSCn_CLK Output MSC(MMC/SD) n clock output
MSCn_CMD Bidirection MSC(MMC/SD) n command
USB 2.0 OTG
DRV_VBUS Output USB OTG VBUS driver control signal
NOTES:
1 The meaning of phases in IO cell characteristics are:
a Bi-dir, Single-end: bi-direction and single-ended DDR IO are used.
b Output, Single-end: output and single-ended DDR IO are used.
c Output, Differential: output and differential signal DDR IO are used.
d Bi-dir, Differential: bi-direction and differential signal DDR IO are used.
e 4mA, 8mA, 16mA out: The IO cell’s output driving strength is about 4mA,8mA,16mA.
4/8mA means the IO cell's output driving strength is selected and can be set as 4mA or 8mA.
2/4mA means the IO cell's output driving strength is selected and can be set as 2mA or 4mA.
f Pull-up: The IO cell contains a pull-up resistor.
g Pull-down: The IO cell contains a pull-down resistor.
h Pullup-pe: The IO cell contains a pull-up resistor and the pull-up resistor can be enabled or disabled by setting corresponding register.
i Pulldown-pe: The IO cell contains a pull-down resistor and the pull-down resistor can be enabled or disabled by setting corresponding register.
j rst-pe: these pins are initialed (during reset and after reset) to IO internal pull (up or down) enabled. Otherwise, the pins are initialed to pull
disabled
k Schmitt: The IO cell is Schmitt trig input.
l ~SL: The IO cell do not limited slew rate.
2 All GPIO shared pins are reset to GPIO input
18
Electrical Specifications
3 Electrical Specifications
3.1 Absolute Maximum Ratings
The absolute maximum ratings for the processors are listed in Table 3-1. Do not exceed these
parameters or the part may be damaged permanently. Operation at absolute maximum ratings is not
guaranteed.
Table 3-1 Absolute Maximum Ratings
Parameter Min Max Unit

Storage Temperature -65 150 C
Operation Temperature -40 85 C
VDDMEM power supplies voltage -0.5 1.98 V
VDDIO power supplies voltage -0.5 3.6 V
VDDIO_5T power supplies voltage -0.5 3.6 V
VDD core power supplies voltage -0.2 1.32 V
PLLAVDD power supplies voltage -0.2 1.32 V
AVDEFUSE power supplies voltage -0.5 2.75 V
VDDRTC power supplies voltage -0.5 3.63 V
AVDOTG25 power supplies voltage -0.5 2.75 V
AVDOTG power supplies voltage -0.5 3.63 V
Input voltage to VDDMEM supplied non-supply pins -0.3 1.98 V
Input voltage to VDDIO_5T supplied non-supply pins with 5V
-0.5 5.5 V
tolerance
Input voltage to VDDIO supplied non-supply pins without 5V tolerance -0.5 3.6 V
Input voltage to VDDRTC supplied non-supply pins -0.5 3.6 V
Input voltage to AVDOTG25 supplied non-supply pins -0.5 2.75 V
Input voltage to AVDOTG supplied non-supply pins -0.5 3.63 V
Output voltage from VDDMEM supplied non-supply pins -0.5 1.98 V
Output voltage from VDDIO supplied non-supply pins -0.5 3.6 V
Output voltage from VDDIO_5T supplied non-supply pins -0.5 3.6 V
Output voltage from VDDRTC supplied non-supply pins -0.5 3.6 V
Output voltage from AVDOTG25 supplied non-supply pins -0.5 2.75 V
Output voltage from AVDOTG supplied non-supply pins -0.5 3.6 V
Maximum ESD stress voltage, Human Body Model; Any pin to any
supply pin, either polarity, or Any pin to all non-supply pins together, 2000 V
either polarity. Three stresses maximum.
19
3.2 Recommended operating conditions

Table 3-2 Recommended operating conditions for power supplies
Symbol Description Min Typical Max Unit

VDDMEM voltage for LPDDR 1.65 1.8 1.95 V
VDDMEM voltage for SSTL18 (DDR2) 1.7 1.8 1.9 V
VMEM
VDDMEM voltage for DDR3 1.425 1.5 1.575 V
VDDMEM voltage for DDR3L 1.28 1.35 1.45 V
VIO(1.8V) VDDIO voltage, use as 1.8V 1.62 1.8 1.98 V
VIO5(1.8V) VDDIO_5T voltage, use as 1.8V 1.62 1.8 1.98 V
VCORE VDD core voltage 1.08 1.2 1.32 V
VPLL12 PLLAVDD voltage 1.08 1.25 1.32 V
VEFUSE AVDEFUSE voltage 2.25 2.5 2.75 V
VRTC33 VDDRTC voltage 1.8 1.8 3.63 V
VUSB25 AVDOTG25 voltage 2.25 2.5 2.75 V
VUSB33 AVDOTG voltage 3.0 3.3 3.6 V
Table 3-3 Recommended operating conditions for VDDMEM supplied pins
Symbol Parameter Min Typical Max Unit

VI18 Input voltage for LPDDR applications 0 1.8 1.9 V
VO18 Output voltage for LPDDR applications 0 1.8 1.9 V
Table 3-4 Recommended operating conditions for VDDIO/VDDIO_5T/VDDRTC supplied pins

VIH18 Input high voltage for 1.8V I/O application 1.17 1.8 3.6 V
VIL18 Input low voltage for 1.8V I/O application –0.3 0 0.63 V
VIH25 Input high voltage for 2.5V I/O application 1.7 2.5 3.6 V
VIH33 Input high voltage for 3.3V I/O application 2 3.3 3.6 V
Table 3-5 Recommended operating conditions for others
Symbol Description Min Typical Max Unit

TA Ambient temperature –40 85 C
20
3.3 DC Specifications
The DC characteristics for each pin include input-sense levels and output-drive levels and currents.
These parameters can be used to determine maximum DC loading, and also to determine maximum
transition times for a given load. All DC specification values are valid for the entire temperature range
of the device.
Table 3-6 DC characteristics for VREFMEM

VREFM Reference voltage supply 0.49 0.5 0.51 VMEM
Table 3-7 DC characteristics for VDDmem supplied pins in LPDDR application

VIH(DC) Input logic threshold High 0.7* VMEM VMEM+0.3 V
VIL(DC) Input logic threshold Low VMEM-0.3 0.3* VMEM V
VIH(AC) AC Input logic High 0.8* VMEM VMEM+0.3 V
VIL(AC) AC Input logic Low VMEM-0.3 0.2* VMEM V
VOH DC output logic High 0.9*VMEM V
(IOH=-0.1mA)
VOL DC output logic Low 0.1 *VMEM V
(IOL=0.1mA)
ILL Input leakage current 0.01 6.45 uA
IMEM VMEM quiescent current 0.02 15.03 uA
Table 3-8 DC characteristics for VDDIO/VDDIO_5T/VDDRTC supplied pins for 1.8V application

VT Threshold point 0.79 0.86 0.94 V
VT+ Schmitt trig low to high threshold point 0.95 1.06 1.16 V
VT– Schmitt trig high to low threshold point 0.58 0.69 0.79 V
VTPU Threshold point with pull-up resistor enabled 0.79 0.86 0.94 V
VTPD Threshold point with pull-down resistor enabled 0.79 0.86 0.94 V
Schmitt trig low to high threshold point with pull-up
VTPU+ 0.95 1.06 1.16 V
resistor enabled
Schmitt trig high to low threshold point with pull-down
VTPU– 0.58 0.68 0.78 V
resistor enabled
Schmitt trig low to high threshold point with pull-down
VTPD+ 0.96 1.07 1.17 V
resistor enabled
Schmitt trig high to low threshold point with pull-up
VTPD– 0.59 0.69 0.79 V
resistor enabled
IL Input Leakage Current @ VI=1.8V or 0V ±10 μA
IOZ Tri-State output leakage current @ VI=1.8V or 0V ±10 μA
21
RPU Pull-up Resistor 66 114 211 kΩ

RPD Pull-down Resistor 58 103 204 kΩ
VOL Output low voltage 0.45 V
VOH Output high voltage 1.35 V
8mA 5.3 9.8 15.8 mA
IOL Low level output current @ VOL(max)
16mA 10.8 19.7 31.8 mA
8mA 3.3 8.3 16.6 mA
IOH High level output current @ VOH(min)
16mA 6.6 16.5 33.2 mA

VTPU+ 1.27 1.39 1.48 V
resistor enabled
VTPU– 0.85 0.97 1.08 V
resistor enabled
VTPD+ 1.27 1.41 1.50 V
resistor enabled
VTPD– 0.88 0.99 1.10 V
resistor enabled
8mA 11.6 19.4 28.4 mA
16mA 23.3 39.1 57.2 mA
8mA 9.3 19.4 34.6 mA
16mA 18.6 38.7 69.2 mA

22
VTPU+ 1.62 1.75 1.89 V
resistor enabled
VTPU– 1.16 1.28 1.43 V
resistor enabled
VTPD+ 1.64 1.77 1.91 V
resistor enabled
VTPD– 1.19 1.31 1.45 V
resistor enabled
8mA 10.0 15.2 20.2 mA
16mA 20.2 30.6 40.6 mA
8mA 13.9 28.0 48.2 mA
16mA 27.8 56.0 96.3 mA
3.4 Power On, Reset and BOOT
3.4.1 Power-On Timing

The external voltage regulator and other power-on devices must provide the X1500 processor with a
specific sequence of power and resets to ensure proper operation. Figure 3-1shows this sequence
and Table 3-11 gives the timing parameters. Following are the name of the power.
 VDDRTC: VDDRTC
 VDD: all 1.25V power supplies, include VDDCORE, PLLAVDD
 VDDIO: all other digital IO, include DDR power supplies: VDDMEM, VDDIO, VDDIO_5T
 AVD: all other analog power supplies: AVDOTG25, AVDOTG
 AVDEFUSE
Table 3-11 Power-On Timing Parameters
Symbol Parameter Min Max Unit

[1]
tR_VDDRTC VDDRTC rise time 0 5 ms
[1]
tR_VDDIO VDDIO rise time 0 5 ms
23
Delay between VDD arriving 50% (or 90%) to VDDIO

tD_VDDIO 0 – ms
arriving 50% (or 90%)
[1]
tR_VDD VDD rise time 0 5 ms
Delay between VDDRTC arriving 50% (or 90%) to VDD
tD_VDD 0 1 ms
arriving 50% (or 90%)
[1]
tR_AVD AVD rise time 0 5 ms
tD_AVD Delay between VDDIO arriving 90% to AVD arriving 90% 0 1 ms
[3] [2]
tD_PPRST_ Delay between AVD stable and PPRST_ de-asserted TBD – ms
Delay between PPRST_ finished and E-fuse programming
tD_AVDEFUSE 0 – ms
power apply
NOTES:
1 The power rise time is defined as 10% to 90%.
2 The PPRST_ must be kept at least 100us. After PPRST_ is deasserted, the corresponding
chip reset will be extended at least 40ms.
3 It must make sure the EXCLK is stable and all power(except AVDEFUSE) is stable.
24
tR_VDDRTC
VDDRTC
tD_VDD
tD_VDD
tR_VDD
VDD
tD_VDDIO
tD_VDDIO
tR_VDDIO
VDDIO
tD_AVD
tR_AVD
AVD
tD_PPRST_
PPRST_
tD_AVDEFUSE
AVDEFUSE
Figure 3-1 Power-On Timing Diagram
3.4.2 Reset procedure

There 3 reset sources: 1 PPRST_ pin reset; 2 WDT timeout reset; and 3 hibernating reset when exiting
hibernating mode. After reset, program start from boot.
1 PPRST_ pin reset.

This reset is trigged when PPRST_ pin is put to logic 0. It happens in power on RTC power
and RESET-KEY pressed to reset the chip from unknown dead state. The reset end time is
about 1M EXCLK cycles after rising edge of PPRST_.
2 WDT reset.
This reset happens in case of WDT timeout. The reset keeps for about a few RTCLK cycles.
3 Hibernating reset.
This reset happens in case of wakeup the main power from power down. The reset keeps for
about 1ms ~ 125ms programable, plus 1M EXCLK cycles, start after WKUP_ signal is
recognized.
After reset, all GPIO shared pins are put to GPIO input function and most of their internal pull-up/down
resistor are set to on, see “2.5 Pin Descriptions” for details. The PWRON is output 1. The oscillators
25
are on. The USB 2.0 OTG PHY, the audio CODEC DAC/ADC put in suspend mode.
3.4.3 BOOT
The boot sequence of the X1500 is controlled by boot_sel [1:0] pin values. The following table lists
them:
Table 3-12 Boot Configuration of X1500
boot_sel[1] boot_sel[0] Boot configuration

1 1 Boot from SFC0
0 1 Boot from MSC0
1 0 Boot from USB 2.0 device
X: means "Don't Care"
The boot procedure is showed in the following flow chart:
After reset, the boot program on the internal boot ROM executes as follows:
1 Disable all interrupts and read boot_sel[2:0] to determine the boot method.
2 If it is boot from MMC/SD card at MSC0, its function pins MSC0_D0, MSC0_CLK,
MSC0_CMD are initialized, the boot program loads the 12KB code from MMC/SD card to
tcsm and jump to it. Only one data bus which is MSC0_D0 is used. The clock EXTCLK/128 is
used initially. When reading data, the clock EXTCLK/4 is used.
3 If it is boot from USB, a block of code will be received through USB cable connected with host
PC and be stored in tcsm. Then branch to this area in tcsm.
4 If it is boot from SPI nor/nand at SFC, its function pins SFC_CLK,SFC_CE,SFC_DR,SFC_DT,
SFC_WP, SFC_HOLD are initialized, the boot program loads the 12KB code from
MMC/SD card to tcsm and jump to it.
26
Figure 3-2 Boot flow diagram of X1500
27
Packaging Information
4 Packaging Information
4.1 Overview
X1500 processor is offered in 109-pin BGA package, which is 8mm X 8mm X 1.2mm, 12 x 12 matrix
ball grid array and 0.65mm ball pitch, show in Figure 4-1.
4.2 X1500 Device Dimensions
28
Packaging Information
Figure 4-1 X1500 package outline drawing
Notes:
1. BALL PAD OPENING: 0.270mm；
2. PRIMARY DATUM C AND SEATING PLANE ARE THE SOLDER BALLS；
3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER,PARALLEL
TO PRIMARY DATUM C；
4. SPECIAL CHARACTERISTICS C CLASS: bbb,ddd；
5. THE PATTERN OF PIN 1 FIDUCIAL IS FOR REFERENCE ONLY；
6. BAN TO USE THE LEVEL 1 ENVIRONMENT-RELATED SUBSTANCES OF JCET
PRESCRIBING；
7. ALL UNITS ARE IN MILLIMETER；
4.3 Solder Ball Materials

Both the top (joint) and bottom solder ball materials of X1500 are SAC105.
4.4 Moisture Sensitivity Level

X1500 package moisture sensitivity is level 3.
29
PCB Mounting Guidelines
5 PCB Mounting Guidelines

5.1 RoHS compliance
TBD.
5.2 Reflow profile

X1500 package is lead-free. It’s reflow profile follows the IPC/JEDEC lead-free reflow profile as
contained in J-STD-020C.
30

X1500 Iot Application Processor: Data Sheet

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X1500 Iot Application Processor: Data Sheet

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X1500

IoT Application Processor

Release Date: Feb. 8, 2017

Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.

Ingenic Semiconductor Co., Ltd.

Ingenic Headquarters, East Bldg. 14, Courtyard #10,

2 Pinout Information ............................................................................ 8

3 Electrical Specifications .................................................................. 19

4 Packaging Information .................................................................... 28

5 PCB Mounting Guidelines............................................................... 30

1.1 Block Diagram

Figure 1-1 X1500 Diagram

1.2.1 CPU Core

1.2.2 Image Core

– Sample rate supported: 8k, 16k.

1.2.4 Memory Interface

 32MB SIP LPDDR

 Serial nand/nor flash interface(SFC)

1.2.5 System Functions

– Supply block power shut down

 RTC (Real Time Clock)

 Three I2C Controller (I2C0, I2C1, I2C2)

 One Synchronous serial interfaces (SSI0)

– Two slave select signal (SSI0_CE0_ / SSI0_CE1_) supporting up to 2 slave devices

 Three UARTs (UART0, UART1, UART2)

 One MMC/SD/SDIO controllers

 USB 2.0 OTG interface

 OTP Slave Interface

X1500 Ball Assignment Ver1.1

I2S_MCLK_ I2S_BCLK_ I2S_LRCLK_PB DRV_VBUS_P EXCLK_

Figure 2-1 X1500 pin to ball assignment

2.2 Pin Descriptions

2.2.1 GPIO Group A

Ball Pull Driven Slewrate Extra

K12 I2C1_SCK_PA00 IO PU Enable 8mA No GPA[0] I2C1_SCK WKUP VDDIO

B10 CIM_D0_PA19 IO PU Enable 8mA No GPA[19] CIM_D0 WKUP VDDIO

2.2.2 GPIO Group B

Ball Pull Driven Slewrate Extra

K11 PWM3_PB06 IO PU Enable 8mA No GPB[6] PWM3 WKUP VDDIO

2.2.3 GPIO Group C

Ball Pull Driven Slewrate Extra

2.2.4 GPIO Group D

Ball In/ Pull Driven Slewrate Extra

2.3 X1500 FUNCTION PIN DESCRIPTION

Ball No. Pin Names IO Power Pin Description

E6 VDDMEM P - IO digital power for DRAM 1.8V

M11 USB_DP0(OTG_DP) AIO AVDOTG USB OTG data plus

2.4 X1500 FUNCTION DESCRIPTION

Signal Name In/Out Description

DMIC_CLK Output Digital MIC clock output

MSCn_D3 Bidirection MSC(MMC/SD) n data bit 3

Table 3-1 Absolute Maximum Ratings

Parameter Min Max Unit

3.2 Recommended operating conditions

Symbol Description Min Typical Max Unit

Table 3-3 Recommended operating conditions for VDDMEM supplied pins

Symbol Parameter Min Typical Max Unit

Table 3-4 Recommended operating conditions for VDDIO/VDDIO_5T/VDDRTC supplied pins

Symbol Parameter Min Typical Max Unit