MC14066B

Quad Analog Switch/Quad

Multiplexer
The MC14066B consists of four independent switches capable of
controlling either digital or analog signals. This quad bilateral switch
is useful in signal gating, chopper, modulator, demodulator and
CMOS logic implementation. http://onsemi.com
The MC14066B is designed to be pin−for−pin compatible with the
MC14016B, but has much lower ON resistance. Input voltage swings MARKING
DIAGRAMS
as large as the full supply voltage can be controlled via each
14
independent control input.
PDIP−14
P SUFFIX MC14066BCP
Features AWLYYWWG
CASE 646
• Triple Diode Protection on All Control Inputs 1
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Linearized Transfer Characteristics 14
SOIC−14
• Low Noise − 12 nV/√Cycle, f ≥ 1.0 kHz typical D SUFFIX
14066BG
AWLYWW
• Pin−for−Pin Replacement for CD4016, CD4016, MC14016B CASE 751A
• For Lower RON, Use The HC4066 High−Speed CMOS Device 1
• Pb−Free Packages are Available 14
14
MAXIMUM RATINGS (Voltages Referenced to VSS) 066B
TSSOP−14
Symbol Parameter Value Unit DT SUFFIX ALYW
CASE 948G 
VDD DC Supply Voltage Range −0.5 to +18.0 V
Vin, Vout Input or Output Voltage Range −0.5 to VDD + 0.5 V 1
(DC or Transient)
Iin Input Current (DC or Transient) ± 10 mA 14
per Control Pin SOEIAJ−14
F SUFFIX MC14066B
ISW Switch Through Current ± 25 mA ALYWG
CASE 965
PD Power Dissipation, per Package 500 mW
(Note 1) 1
TA Ambient Temperature Range −55 to +125 °C
A = Assembly Location
Tstg Storage Temperature Range −65 to +150 °C WL, L = Wafer Lot
TL Lead Temperature 260 °C YY, Y = Year
(8−Second Soldering) WW, W = Work Week
G or  = Pb−Free Package
Stresses exceeding Maximum Ratings may damage the device. Maximum (Note: Microdot may be in either location)
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: ORDERING INFORMATION
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.

© Semiconductor Components Industries, LLC, 2006 1 Publication Order Number:

October, 2006 − Rev. 7 MC14066B/D
 MC14066B

PIN ASSIGNMENT

IN 1 1 14 VDD
OUT 1 2 13 CONTROL 1
OUT 2 3 12 CONTROL 4
IN 2 4 11 IN 4
CONTROL 2 5 10 OUT 4
CONTROL 3 6 9 OUT 3
VSS 7 8 IN 3

BLOCK DIAGRAM LOGIC DIAGRAM AND TRUTH TABLE

13 (1/4 OF DEVICE SHOWN)
CONTROL 1 2
1 OUT 1
IN/OUT OUT/IN
IN 1
5
CONTROL 2 3 CONTROL
4 OUT 2
IN 2 Control Switch Logic Diagram Restrictions
6 0 = VSS OFF VSS ≤ Vin ≤ VDD
CONTROL 3
9 1 = VDD ON
VSS ≤ Vout ≤ VDD
8 OUT 3
IN 3
12
CONTROL 4 10
11 OUT 4
IN 4 VDD = PIN 14
VSS = PIN 7

CIRCUIT SCHEMATIC
(1/4 OF CIRCUIT SHOWN)

VDD VDD VDD

VSS

VDD
VDD VDD VDD

CMOS
INPUT 300
W
VSS VSS

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2
 MC14066B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ELECTRICAL CHARACTERISTICS

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎ
ÎÎÎ
− 55C 25C 125C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎ
ÎÎÎ
Characteristic Symbol VDD Test Conditions Min Max Min Typ (2) Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
Power Supply Voltage VDD — 3.0 18 3.0 − 18 3.0 18 V
Range

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Quiescent Current Per
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
IDD
ÎÎ 5.0 Control Inputs: − 0.25 − 0.005 0.25 − 7.5 mA

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Package

ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ 10 Vin = VSS or VDD, − 0.5 − 0.010 0.5 − 15

ÎÎÎÎÎÎÎ
ÎÎ ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
15 Switch I/O: VSS v VI/O − 1.0 − 0.015 1.0 − 30
v VDD, and

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎ DVswitch v 500 mV (3)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current
ÎÎ
ID(AV) 5.0 TA = 25C only The
(0.07 mA/kHz) f + IDD
mA

ÎÎÎÎÎÎÎ
ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
(Dynamic Plus Quiescent, 10 channel component,
Typical (0.20 mA/kHz) f + IDD
Per Package 15 (Vin – Vout)/Ron, is

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
(0.36 mA/kHz) f + IDD
not included.)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
CONTROL INPUTS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
Low−Level Input Voltage
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
VIL
ÎÎ 5.0 Ron = per spec, − 1.5 − 2.25 1.5 − 1.5 V

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ ÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎ
10 Ioff = per spec − 3.0 − 4.50 3.0 − 3.0
15 − 4.0 − 6.75 4.0 − 4.0

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
High−Level Input Voltage
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
VIH
ÎÎ 5.0 Ron = per spec, 3.5 − 3.5 2.75 − 3.5 − V

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎ ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎ
10
15
Ioff = per spec 7.0
11
−
−
7.0
11
5.50
8.25
−
−
7.0
11
−
−

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
Input Leakage Current Iin 15 Vin = 0 or VDD − ± 0.1 − ±0.00001 ± 0.1 − ± 1.0 mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
Input Capacitance Cin − − − − 5.0 7.5 − − pF

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
SWITCHES IN AND OUT (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
Recommended Peak−to− VI/O − Channel On or Off 0 VDD 0 − VDD 0 VDD Vp–p
Peak Voltage Into or Out

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
of the Switch

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
Recommended Static or DVswitch − Channel On 0 600 0 − 600 0 300 mV

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
Dynamic Voltage Across
the Switch (3) (Figure 1)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Output Offset Voltage
ÎÎÎ
ÎÎÎÎÎÎ
VOO
ÎÎ − Vin = 0 V, No Load − − − 10 − − − mV

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ON Resistance

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
Ron
ÎÎ 5.0 DVswitch v 500 mV (3), − 800 − 250 1050 − 1200 W

ÎÎÎÎÎÎÎ
ÎÎ ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
10 Vin = VIL or VIH − 400 − 120 500 − 520
15 (Control), and Vin = − 220 − 80 280 − 300

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎ 0 to VDD (Switch)

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
Any Two Channels ÎÎÎ
DON Resistance Between

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
in the Same Package
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
DRon
ÎÎ
ÎÎÎÎÎÎ
ÎÎ
5.0
10
15
−
−
−
70
50
45
−
−
−
25
10
10
70
50
45
−
−
−
135
95
65
W

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Off−Channel Leakage

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
Ioff

ÎÎ
15

ÎÎÎÎÎÎÎ
Vin = VIL or VIH

ÎÎÎ
−

ÎÎÎÎÎ
−

ÎÎÎÎ
± 0.05

ÎÎÎÎÎÎ
−

ÎÎÎ
± 1000

ÎÎ
±100 ±100 nA
Current (Figure 6) (Control) Channel to

ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎ ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
Channel or Any One
Channel

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Capacitance, Switch I/O
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
CI/O − Switch Off − − − 10 15 − − pF

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Capacitance, Feedthrough
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
CI/O − − − − 0.47 − − − pF

ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎ
(Switch Off)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ −
2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
3. For voltage drops across the switch (DVswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.)

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 MC14066B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ELECTRICAL CHARACTERISTICS (Note 4) (CL = 50 pF, TA = 25C unless otherwise noted.)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
VDD
Vdc Typ (5)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic

ÎÎÎÎ
Symbol

ÎÎÎÎ
ÎÎÎÎ
Min

ÎÎÎÎ
ÎÎÎÎ
Max

ÎÎÎ
Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Times VSS = 0 Vdc

ÎÎÎÎ
tPLH, tPHL

ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ns
Input to Output (RL = 10 kW)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.17 ns/pF) CL + 15.5 ns 5.0 − 20 40
tPLH, tPHL = (0.08 ns/pF) CL + 6.0 ns 10 − 10 20

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, tPHL = (0.06 ns/pF) CL + 4.0 ns 15 − 7.0 15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Control to Output (RL = 1 kW) (Figure 2)

ÎÎÎÎ
Output “1” to High Impedance

ÎÎÎ
tPHZ
5.0
10
−
−
40
35
80
70
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ 15 − 30 60

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Output “0” to High Impedance

ÎÎÎ
tPLZ 5.0
10
15
−
−
−
40
35
30
80
70
60
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
High Impedance to Output “1”

ÎÎÎÎÎÎÎÎÎÎÎ
tPZH 5.0
10
−
−
60
20
120
40
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
15 − 15 30

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
High Impedance to Output “0” tPZL 5.0 − 60 120 ns
10 − 20 40

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Second Harmonic Distortion
ÎÎÎÎ
ÎÎÎ
ÎÎÎ VSS = – 5 Vdc −
15
5.0
−
−
15
0.1
30
− %

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,
RL = 10 kW, f = 1.0 kHz)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Bandwidth (Switch ON) (Figure 3)

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
VSS = – 5 Vdc
(RL = 1 kW, 20 Log (Vout/Vin) = − 3 dB, CL = 50 pF,
− 5.0 − 65 − MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Vin = 5 Vp−p)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Feedthrough Attenuation (Switch OFF) VSS = – 5 Vdc − 5.0 − – 50 − dB
(Vin = 5 Vp−p, RL = 1 kW, fin = 1.0 MHz) (Figure 3)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Channel Separation (Figure 4)
ÎÎÎ VSS = – 5 Vdc − 5.0 − – 50 − dB

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
(Vin = 5 Vp−p, RL = 1 kW, fin = 8.0 MHz)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
(Switch A ON, Switch B OFF)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Crosstalk, Control Input to Signal Output (Figure 5) mVp−p
VSS = – 5 Vdc − 5.0 − 300 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
(R1 = 1 kW, RL = 10 kW, Control tTLH = tTHL = 20 ns)
4. The formulas given are for the typical characteristics only at 25C.
5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

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 MC14066B

ORDERING INFORMATION
Device Package Shipping †
MC14066BCP PDIP−14
MC14066BCPG PDIP−14 25 Units / Rail
(Pb−Free)
MC14066BD SOIC−14
MC14066BDG SOIC−14 55 Units / Rail
(Pb−Free)
MC14066BDR2 SOIC−14
MC14066BDR2G SOIC−14
(Pb−Free)
2500 / Tape & Reel
MC14066BDTR2 TSSOP−14*
MC14066BDTR2G TSSOP−14*
MC14066BF SOEIAJ−14
MC14066BFG SOEIAJ−14 50 Units / Rail
(Pb−Free)
MC14066BFEL SOEIAJ−14
MC14066BFELG SOEIAJ−14 2000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.

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 MC14066B

TEST CIRCUITS

Vout
VC
RL CL
ON SWITCH
Vin Vx
CONTROL 20 ns
SECTION VDD
90%
OF IC VC 50%
10%
tPZH VSS
tPHZ
LOAD 90%
V Vout Vin = VDD
10%
tPZL tPLZ Vx = VSS
90%
Vout Vin = VSS
SOURCE 10% Vx = VDD

Figure 1. DV Across Switch Figure 2. Turn−On Delay Time Test Circuit

and Waveforms

VDD − VSS
VC = VDD FOR BANDWIDTH TEST 2
VC = VSS FOR FEEDTHROUGH TEST

VDD − VSS Vin

2
RL CL
VDD
Vin Vout

RL CL

VC
RL CL
VSS
VDD VSS

Figure 3. Bandwidth and Figure 4. Channel Separation

Feedthrough Attenuation

OFF CHANNEL UNDER TEST

VDD
Vin
A
Vout VSS
1k CONTROL
RL CL = 50 pF SECTION
10 k OF IC
VSS

VC = −5.0 V TO +5.0 V SWING VDD

Figure 5. Crosstalk, Figure 6. Off Channel Leakage

Control to Output

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 MC14066B

VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k

1 kW
VDD RANGE X−Y
PLOTTER
VSS

Figure 7. Channel Resistance (RON) Test Circuit

TYPICAL RESISTANCE CHARACTERISTICS

350 350

300 300
R ON , ON" RESISTANCE (OHMS)

R ON , ON" RESISTANCE (OHMS)

250 250

200 200

150 150 TA = 125°C

TA = 125°C
100 100 25°C
25°C
−55 °C −55 °C
50 50

0 0
−10 −8.0 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 10 −10 −8.0 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS)

Figure 8. VDD = 7.5 V, VSS = − 7.5 V Figure 9. VDD = 5.0 V, VSS = − 5.0 V

700 350
TA = 25°C
600 300
RON , ON" RESISTANCE (OHMS)
RON , ON" RESISTANCE (OHMS)

500 250 VDD = 2.5 V

400 200

300 150
TA = 125°C 5.0 V
200 100
25°C 7.5 V

100 −55 °C 50

0 0
−10 −8.0 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 10 −10 −8.0 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS)

Figure 10. VDD = 2.5 V, VSS = − 2.5 V Figure 11. Comparison at 25°C, VDD = − VSS

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 MC14066B

APPLICATIONS INFORMATION

Figure A illustrates use of the Analog Switch. The V DD and/or below V SS are anticipated on the analog
0−to−5 V digital control signal is used to directly control a channels, external diodes (Dx) are recommended as shown
5 V peak−to−peak analog signal. in Figure B. These diodes should be small signal types able
The digital control logic levels are determined by V DD to absorb the maximum anticipated current surges during
and VSS. The VDD voltage is the logic high voltage, the VSS clipping.
voltage is logic low. For the example, V DD = + 5 V = logic The absolute maximum potential difference between
high at the control inputs; VSS = GND = 0 V = logic low. V DD and V SS is 18 V. Most parameters are specified up to
The maximum analog signal level is determined by VDD 15 V which is the recommended maximum difference
and VSS. The analog voltage must not swing higher than between V DD and V SS.
V DD or lower than V SS.
The example shows a 5 V peak−to−peak signal which
allows no margin at either peak. If voltage transients above

+5 V

VDD VSS

+5.0 V

5 Vp−p SWITCH
ANALOG SIGNAL IN SWITCH 5 Vp−p
+ 2.5 V
+5 V OUT ANALOG SIGNAL

GND
EXTERNAL 0−TO−5 V DIGITAL MC14066B
CMOS
CONTROL SIGNALS
DIGITAL
CIRCUITRY

Figure A. Application Example

VDD VDD

DX DX

SWITCH SWITCH
IN OUT
DX DX

VSS VSS

Figure B. External Germanium or Schottky Clipping Diodes

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 MC14066B

PACKAGE DIMENSIONS

PDIP−14
CASE 646−06
ISSUE P

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14 8 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 7 5. ROUNDED CORNERS OPTIONAL.

INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
F L C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
N C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
−T− J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
SEATING L 0.290 0.310 7.37 7.87
PLANE
K J M −−− 10  −−− 10 
H G D 14 PL N 0.015 0.039 0.38 1.01
M
0.13 (0.005) M

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 MC14066B

PACKAGE DIMENSIONS

SOIC−14
CASE 751A−03
ISSUE H

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−A− 2. CONTROLLING DIMENSION: MILLIMETER.
14 8 3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B− 5. DIMENSION D DOES NOT INCLUDE
P 7 PL DAMBAR PROTRUSION. ALLOWABLE
0.25 (0.010) M B M DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
1 7 CONDITION.

G MILLIMETERS INCHES
R X 45  F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
−T− F 0.40 1.25 0.016 0.049
K M J
SEATING D 14 PL G 1.27 BSC 0.050 BSC
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

SOLDERING FOOTPRINT*
7X
7.04 14X
1.52
1
14X
0.58

1.27
PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 MC14066B

PACKAGE DIMENSIONS

TSSOP−14
CASE 948G−01
ISSUE B

14X K REF NOTES:

1. DIMENSIONING AND TOLERANCING PER
0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
N EXCEED 0.15 (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE
2X L/2 INTERLEAD FLASH OR PROTRUSION.
M INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE
−U− N DAMBAR PROTRUSION. ALLOWABLE
PIN 1 DAMBAR PROTRUSION SHALL BE 0.08
IDENT. F (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
1 7 CONDITION.
DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
0.15 (0.006) T U S
A K DETERMINED AT DATUM PLANE −W−.

ÉÉÉ
ÇÇÇ
−V− K1 MILLIMETERS INCHES
DIM MIN MAX MIN MAX

ÇÇÇ
ÉÉÉ
A 4.90 5.10 0.193 0.200
J J1 B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
SECTION N−N F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
−W− J 0.09 0.20 0.004 0.008
C J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
0.10 (0.004) K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
−T− SEATING D G H DETAIL E M 0 8 0 8
PLANE

SOLDERING FOOTPRINT*

7.06

0.65
PITCH

14X 14X
0.36
1.26
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 MC14066B

PACKAGE DIMENSIONS

SOEIAJ−14
CASE 965−01
ISSUE A

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
14 8 LE MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
Q1 (0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
E HE M REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
1 7 L TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DETAIL P DAMBAR CANNOT BE LOCATED ON THE LOWER
Z RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
D TO BE 0.46 ( 0.018).

VIEW P MILLIMETERS INCHES

e A DIM MIN MAX MIN MAX
A −−− 2.05 −−− 0.081
c A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.10 0.20 0.004 0.008
D 9.90 10.50 0.390 0.413
b A1 E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
0.13 (0.005) M 0.10 (0.004) HE 7.40 8.20 0.291 0.323
0.50 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0 10  0 10 
Q1 0.70 0.90 0.028 0.035
Z −−− 1.42 −−− 0.056

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
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12