Universidad Autónoma "Tomás Frías" Facultad de Ingeniería Tecnológica
Universidad Autónoma "Tomás Frías" Facultad de Ingeniería Tecnológica
Universidad Autónoma "Tomás Frías" Facultad de Ingeniería Tecnológica
LABORATORIO # 4
PRE INFORME
PROCEDIMIENTO DE DISEÑO.-
ck ck1
DivFrec1 B
[0:3]m1,m2 [0:3]BCD [0:6]seg
MUX C
RELOJ h1,h2 D
rst [0:3]ho1,ho2
pul2 acumuladorh
rst [0:3]mi2,mi1
Acumulador1
pul1
h2 h1: m2 m1
2 3: 5 9
Pul2 = h++
Pul1= m++
Código en Verilog
reg [12:0] x;
initial x = 0;
reg [20:0] x;
initial x = 0;
initial
begin
h2 = 0;
h1 = 0;
//m2 = 0;
//m1 = 0;
end
else
begin
if(pul2 == 1)
begin
if(h1 == 9)
begin
h1 = 0;
h2 = h2 + 1;
end
else
begin
h1 = h1+1;
end
endmodule
initial
begin
// h2 = 0;
// h1 = 0;
m2 = 0;
m1 = 0;
end
else
begin
if(pul1 == 1)
begin
m1 = m1 + 1;
if(m1 == 10)
begin
m1 = 0;
m2= m2 + 1;
if(m2==6)
begin
m1 = 0;
m2 = 0;
end
end
end
end
end
endmodule
reg [0:1]S;
assign Z = S;
initial S = 3;
module reloj1(ck, ho2, ho1, mi2, mi1, r, h2, h1, m2, m1, buz);
input ck, r;
input [0:3] ho2, ho1, mi2, mi1;
output buz;
output [0:3] m1, m2, h1, h2;
initial
begin
m1 = 0;
m2 = 0;
h1 = 0;
h2 = 0;
buz = 0;
end
else
begin
h2 = ho2;
h1 = ho1;
m2 = mi2;
m1 = mi1;
buz = 0;
end
end
endmodule
always @(Z)
begin
case(Z)
0: sel = 8'b10000000;
1: sel = 8'b01000000;
2: sel = 8'b00100000;
3: sel = 8'b00010000;
endcase
end
endmodule
reg [0:6] X;
assign seg = X;
always @(BCD)
begin
case(BCD)
0: X = 7'b1111110;
1: X = 7'b0110000;
2: X = 7'b1101101;
3: X = 7'b1111001;
4: X = 7'b0110011;
5: X = 7'b1011011;
6: X = 7'b1011111;
7: X = 7'b1110000;
8: X = 7'b1111111;
9: X = 7'b1111011;
default X = 7'b0000000;
endcase
end
endmodule
wire [0:3] h1, h2, m1, m2, BCD, ho2, ho1, mi2, mi1;
wire [0:1] Z;
wire ck1, ck2, x;