Beginning FPGA Programming - Partie75

Chapter 16 ■ Up in Lights: How to Drive LED Segment Displays
Table 16-1. FPGA pins mapping to 7 Segment display
J5 Pin Number 7 Segment Display Pin FPGA Port Name Function

5 7 GPIO_05 Segment A
6 6 GPIO_06 Segment B
7 4 GPIO_07 Segment C
8 2 GPIO_08 Segment D
9 1 GPIO_09 Segment E
10 9 GPIO_10 Segment F
13 10 GPIO_11 Segment G
12 3 and 8 N/A Ground
Figure 16-5 shows our setup for the connections of the 7 segment display. We are using 5k ohm resistor
for our setup. You can use a smaller resistor value which will give you brighter LEDs. This is because the
smaller the resistor value, the more current can pass though the 7 segment LEDs. When the FPGA GPIO pins
drive high, the LEDs on the 7 segment will light up.
Figure 16-5. Connection between 7 segment display and Be Micro MAX 10
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If you power up the BeMicro MAX10 FPGA, the 7 segment display may partially light up. It is because
any non-programed pin from FPGA may have lower than the 2.5V voltage come out from the pin. The next
section will create the VHDL design to actually driving it.
16.3 Designing the 7 segment display counter

We are going to design a 7 segment counter in the FPGA. We need to have two sections for this counter. The
first is a simple counter and the second is decoding the counter value to display on the 7 segment display
which is human readable. Table 16-2 shows the port list for the 7 segments display counter. It has a 29.5 MHz
clock and reset inputs, counter update input ports, current value report output and 7 segment display output
ports. Figure 16-6 shows the first section of the VHDL design: Libraries, entity with port list and architecture
with the name arch.
Table 16-2. seven_segment_counter.vhd port list
Name Type Function

sys_clock std_logic 29.5MHz clock
sys_rst Std_logic Active Low reset (logic 0 is reset)
data_in Std_logic_vector(7 downto 0) Updated counter value
current_value Std_logic_vector(7 downto 0) Current counter value output
segments_a2g Std_logic_vector(0 to 6) 7 segment display: A to G LEDs outputs
Figure 16-6. seven_segment_counter entity and architecture signal section
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16.3.1 Simple counter design section

Since we have one 7 segment display, the counter will only allow us to count 0 to 9. The simple counter will
count from 0 to 9 and then start from 0 again. We should slowly increment the counter value such that we
can see the update one by one. This counter should provide an interface for updating the current value such
that the counter value can start from any value we select.
1.
Data input process for update the current counter value
2.
One second internal counter for slowly updating the 7 segment display counter
3.
4 bit counter with value from 0 to 9 and loading input port
16.3.1.1 Data input process

This process is synchronous to sys_clock which is 29.5MHz. It will update the data_in_reg value when
data_valid is equal to ‘1’. It is a simple 8 bit register. Figure 16-7 shows this data input registers process. The
default value of the data_in_reg after power on is 0xFF such that the 7 segment display counter will start to
count automatically.
Figure 16-7. data input process
16.3.1.2 One second counter

This is a counter with a max value equal to 29.5M such that we can count one second duration. The binary
value of 29.5M has 25 bits. We need to have a counter ( second_count ) with the same number of bit to
counter one second. This counter starts from 0 and counter all the way up to 29499999. It will generate a tick
( second_tick ) when it is equal to 29.5M - 1, which is one second when the counter is clocked by 29.5MHz.
Figure 16-8 shows this one second counter design process.
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Figure 16-8. One second counter
16.3.1.3 4 Bit Counter with value from 0 to 9

This is a counter with a max value much less than the last one. It only counts from 0 to 9. This counter
is controlled by the input value (data_in_reg). The counter will start increment by one when the data_
in_reg value is bigger than 9. If the data_in_reg value is smaller or equal to 9, then the counter value
(counter_0to9) will be updated by the data_in_reg value and freeze which means the counter will not
incremented. Figure 16-9 shows the design of this 4 bit counter (counter_0to9)
Figure 16-9. 4 bits counter with load
373
In line 74, we use unsigned(data_in_reg) to convert the std_logic_vector to an unsigned value such
that we can compare it with 9.
16.3.2 7 segment decoder section

The output from the simple counter is a binary number. We need to translate the 4 bit binary number to 7 bit
segment display LEDs output. In this design we are using a common cathode LED which means we need to
output '1' to make the LED on. We can use a simple case statement in VHDL to map these 4 bit binary inputs
to 7 bit segment outputs.
16.3.2.1 Case statement for 7 Segment decoder

This decoder is a pure combinational logic design which uses case statements. This is a good example of
how to use a case statement as part of combinational logic. Counter_0to9 is the case inputs. We only need to
decode the value between 0 to 9. The 7 segment display will NOT output anything when the counter_0to9
value are not equal to valid range (0 ~ 9) which is in the case statement “others”(Figure 16-10 line 103).
Remember to add the counter_0to9 to the sensitive list. Line 107 and 108 connect the counter_0to9 value
externally. This example shows you how to create combinational logic without any logic gate design. All of
the logic gates are created by the Altera tools.
Figure 16-10. 7 Segment decoder case statements
16.3.3 End of the counter design

Each VHDL module design has entity (line 6 to 19) and architecture (line 21 to 110). Figure 16-3e shows the
last three line of VHDL code. The lower four bits of current_vlaue is connected to the counter_0to9 (the 4
bit counter) and the upper four bits are all set to zero. This current_value is an output port of the 7 segment
display counter module. The port value will be used to report the value back to Raspberry Pi (when it sends a
read back command) and output to drive the one board LEDs.
The last line (line 110) in the Figure 16-11 is the end of the counter design. It defines the end of the
architecture: arch.
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Chapter 16 ■ Up in Lights: How to Drive LED Segment Displays

Table 16-1. FPGA pins mapping to 7 Segment display

J5 Pin Number 7 Segment Display Pin FPGA Port Name Function

Figure 16-5. Connection between 7 segment display and Be Micro MAX 10

16.3 Designing the 7 segment display counter

Table 16-2. seven_segment_counter.vhd port list

Name Type Function

Figure 16-6. seven_segment_counter entity and architecture signal section

16.3.1 Simple counter design section

16.3.1.1 Data input process

Figure 16-7. data input process

16.3.1.2 One second counter

Figure 16-8. One second counter

16.3.1.3 4 Bit Counter with value from 0 to 9

Figure 16-9. 4 bits counter with load

16.3.2 7 segment decoder section

16.3.2.1 Case statement for 7 Segment decoder

Figure 16-10. 7 Segment decoder case statements

16.3.3 End of the counter design

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16.3 Designing the 7 segment display counter

16.3.1 Simple counter design section

16.3.1.1 Data input process

16.3.1.2 One second counter

16.3.1.3 4 Bit Counter with value from 0 to 9

16.3.2 7 segment decoder section

16.3.2.1 Case statement for 7 Segment decoder

16.3.3 End of the counter design