Design of An Open-Source SATA Core: July 2015
Design of An Open-Source SATA Core: July 2015
Design of An Open-Source SATA Core: July 2015
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For some applications, it may be desirable to store the acquired data for later analysis.
However, the amount of data would quickly exceed the RAM storage capacity, so it is necessary
to store the data on a dedicated storage device such as a hard drive. To do so, one of the
industry-standard hard drive interfaces must be used. Thus, SATA seems to be a suitable
choice, since it features high throughput for storage, as shown in Table 1.
SATA Overview
Serial ATA is a peripheral interface created in 2003 to replace Parallel ATA, also
known as IDE. Hard drive speeds were getting faster, and would soon outpace the
capabilities of the older standard—the fastest PATA speed achieved was 133MB/s, while
SATA began at 150MB/s and was designed with future performance in mind [2]. Also,
newer silicon technologies used lower voltages than PATA's 5V minimum. The ribbon
cables used for PATA were also a problem; they were wide and blocked air flow, had a
short maximum length restriction, and required many pins and signal lines [2].
SATA has a number of features that make it superior to Parallel ATA. The
signaling voltages are low and the cables and connectors are very small. SATA has
outpaced hard drive performance, so the interface is not a bottleneck in a system. It also
has a number of new features, including hot-plug support.
SATA is a point-to-point architecture, where each SATA link contains only two
devices: a SATA host (typically a computer) and the storage device. If a system requires
multiple storage devices, each SATA link is maintained separately. This simplifies the
protocol and allows each storage device to utilize the full capabilities of the bus
simultaneously, unlike in the PATA architecture where the bus is shared.
To ease the transition to the new standard, SATA maintains backward
compatibility with PATA. To do this, the Host Bus Adapter (HBA) maintains a set of
shadow registers that mimic the registers used by PATA. The disk also maintains a set of
these registers. When a register value is changed, the register set is sent across the serial
line to keep both sets of registers synchronized. This allows for the software drivers to be
agnostic about the interface being used.
SATA uses a layered architecture, depicted in Figure 3.The highest layer is the Application
Layer, which represents the software using the SATA device. Below that is the Command
Layer, which triggers series of Transport Layer actions to implement a PATA command. Next
is the Transport Layer, which handles creating and formatting Frame Information Structures
(FISes), and the valid sequences of FISes. Beneath that is the Link Layer, which encodes the
FISes, handles control signals, and checks for FIS integrity. The lowest layer is the Physical
Layer, which handles the transmission and reception of the actual electrical signal and
maintains alignment. It also takes care of establishing the link, using what is known as Out-of-
band (OOB) signaling.
Each layer provides services to the layer above it. This allows for each layer to “abstract away”
the details of the layers below it and simplify the design process. The layers will be discussed
in more depth shortly.
Notes on Terminology
When discussing SATA, there are multiple words that can refer to the same thing, and words
could have different meanings in other contexts. To avoid ambiguity, in this document, we will
try to be consistent in the use and meaning of the following terms.
Dword: Although this term is typically used in the context of a particular processor or processor
family, here it refers to 32 bits of data, or 4 bytes. This is consistent with other SATA literature.
However, note that a Dword is encoded as 40 bits while on the line. Despite the size change,
this is still referred to as a “Dword” because the encoded data is never manipulated directly, and
once decoded, will again be 32 bits.
Core, Host Bus Adapter (HBA): This refers to the SATA design being presented in this work.
That is, the hardware that interfaces with a disk and handles the SATA protocol.
Host: This refers to the system that is interfacing with the disk, and includes the HBA. An
example of a host would be a PC, or the SSD board. Since the SATA protocol is asymmetric,
“Host” can also refer to the host's side of the protocol.
Disk, device: This refers to the hard drive with which we are communicating. Although disk is
unambiguous, device could refer to any number of things. In this work, “device” refers to the
hard disk, unless context indicates otherwise.
Frame Information Structure (FIS): A Frame Information Structure, or FIS, is a single data
payload that is sent over the SATA link. These are analogous to “packets” in network
terminology. There are multiple types of FISes, and all of them are wrapped by Start of Frame
(SOF) and End of Frame (EOF) primitives. The protocol defines valid sequences of FISes for
data transfer. One or more of these FISes will be Data FISes, that actually contain the data to
be read or written. The maximum size of a single FIS is 8KB.
SATA Details
Physical Layer
The physical layer is the lowest layer of the SATA protocol stack. It handles the electrical signal
being sent across the cable. The physical layer also handles some other important aspects, such
as resets and speed negotiation.
SATA uses low-voltage differential signaling (LVDS). Instead of sending 1's and 0's relative to a
common ground, the data being sent is based on the difference in voltage between two conductors
sending data. In other words, there is a TX+ and a TX- signal. A logic 1 corresponds to a high
TX+ and a low TX-; and vice versa for a logic 0. SATA uses a ±125mV voltage swing.
This scheme was chosen for multiple reasons. For one, it improves resistance to noise. A
source of interference will likely affect both conductors in the same way, since they are parallel
to each other. However, a change in voltage on both conductors does not change the difference
between them, so the signal will still be easily recovered. Low- voltage differential signaling also
reduces electromagnetic interference (EMI), and the lower signaling voltages means that less
power is used.
Out-of-Band Signaling
As stated earlier, the physical layer is also responsible for link initialization and resets. But how
can a host and a device communicate to initialize the link if they don't have a link with which to
communicate? The scheme that SATA uses is called out-of-band (or OOB) signaling.
Under this scheme, it is assumed that the host and the device can detect the presence or
absence of a signal, even if they cannot yet decode that signal. OOB signals are essentially
that—whether or not an in-band signal is there. By driving TX+ and TX- to the same common
voltage (so not a logic 1 or a logic 0), one party can transmit an OOB “lack of signal.”
Link initialization is performed by sending a sequence of OOB primitives, which are defined
patterns of signal/no-signal. There are three defined primitives: COMRESET, COMINIT, and
COMWAKE. Each primitive consists of six “bursts” of a present signal, with idle time in between.
The times of each burst are defined in terms of “Generation 1 Unit Intervals” (U), which is the
time to send 1 bit at the SATA I rate of 1.5Gb/s.
Table 2 shows the definitions of the primitives. There are also fairly loose tolerances defined for
each signal. Note also that COMRESET and COMINIT have the same definition—the only
difference is that COMRESET is sent by the host, and COMINIT is sent by the device.
OOB Signal Burst Length Inter-burst Idle Time
COMRESET 106ns (160U) 320ns (480U)
COMINIT 106ns 320ns
COMWAKE 106ns 106ns
Table 2: OOB Primitive Definitions
The COMRESET signal, sent by the host, is used to reset the link. Following a COMRESET, the
OOB initialization sequence is performed again. COMRESET can also be sent repeatedly to
hold the link in a reset state.
The OOB Sequence
The initialization state machine for the host follows this sequence to establish communications
with the disk. This sequence is illustrated in Figure 4.
First, a COMRESET is sent. The host then waits for a COMINIT from the device.
If no COMINIT is received, the host can send more COMRESETs until it receives one, and
assume that no device is connected until it does. After receiving COMINIT, the host is given
time to optionally calibrate its receiver and transmitter. For example, it may be necessary to
adjust signal parameters or termination impedances. The host then sends a COMWAKE to the
device, and expects the same in return. After this, the host waits to receive an ALIGN primitive
(an in-band signal which will be explained shortly).
Meanwhile, it sends a “dial-tone” to the device: an alternating pattern of 1's and 0's. This was
intended as a cost-saving feature, so that disks with cheap oscillators could instead use the dial-
tone as a reference clock for locking.
8b/10b Encoding
The Physical Layer also handles encoding the data before sending it. The scheme used in
SATA is 8b/10b encoding, which is also used in PCI Express, USB 3.0, and many other high
speed protocols. 8b/10b Encoding has a number of properties that make it useful for this
purpose.
One primary function of 8b/10b encoding is clock recovery. Under this scheme, there are never
more than five ones or zeros in a row. In other words, there are many bit transitions in the data
stream. This allows the receiver to recover the clock using a PLL or by oversampling the data.
This is important for serial data, as otherwise a stream of 12 ones in a row, for example, could
be interpreted as 11 or 13 ones instead.
The encoding of data maps each byte to a 10-bit character, instead of an 8-bit one.
Only 10-bit characters that have enough transitions are used. Also, the scheme tries to maintain
DC Balance, and uses the 10-bit patterns with an equal number of ones and zeros. However,
there are not enough of these to accommodate the 256 possible values of a byte, so also those
patterns with 6 zeros and 4 ones (or vice versa) are used.
The encoder keeps track of the running disparity to maintain DC Balance. The running disparity
changes each time an uneven pattern is sent. For example, if a 10-bit character with 6 zeros and
4 ones was just sent, the running disparity is now negative.
The next character therefore must have positive disparity (4 zeros and 6 ones) or neutral disparity
(5 and 5). Thus, many of the bytes actually have two encodings—one positive and the other
negative. The current running disparity determines which encoded value to use. Running disparity
also acts as a means to detect transmission errors.
In SATA, the comma is used as part of the ALIGN primitive. Link Layer primitives, which will be
discussed shortly, are 4 bytes long and always begin with a K character. The ALIGN is the only
one to contain the comma, K28.5. That is why it is used as part of the link initialization
procedure, so that byte boundaries can be determined before attempting to send data.
The SATA protocol also specifies that at least two ALIGNs must be sent every 256 Dwords, and
they must be sent in pairs. This happens even when data is being sent. This ensures that the
byte boundary is not lost, and both the host and the disk must send these ALIGNs. It also acts
as a way to manage small frequency differences between the sender and receiver. For
example, if the sender's clock is running a bit faster than the receiver's, the receiver's buffer may
eventually overflow. Since ALIGNs are sent periodically and they are not data-important, they
can be dropped to prevent this from occurring.
Spread-Spectrum Clocking
To further reduce EMI, the SATA specification requires that a receiver be able to lock to a
bitstream that uses spread-spectrum clocking (SSC). SSC is a scheme where-in the line rate
does not stay constant, but varies slightly over time. This spreads the emissions over a wider
frequency range. The transceivers on the Virtex-4 are able to receive SSC signals, but does not
use it when transmitting.
Link Layer
The link layer is the next layer and is directly above the physical layer. This layer is responsible
for encapsulating data payloads and manages the protocol for sending and receiving them. A
data payload that is sent is called a Frame Information Structure (FIS). The link layer also
provides some other services for ensuring data integrity, handling flow control, and reducing
EMI.
The host and the disk each have their own transmit pair in a SATA cable, and theoretically data
could be sent in both directions simultaneously. However, this does not occur. Instead, the
receiver sends “backchannel” information to the sender that indicates the status of the transfer
in progress. For instance, if an error were to be detected mid- transmission, such as a disparity
error, the receiver could notify the sender of this.
The link layer uses a set of defined Link Layer Primitives to perform these functions. Primitives
are each 4 Dwords long and start with the control character K28.3 (except for ALIGN, as
discussed above). The following table lists most of the defined primitives and their value in
hexadecimal before encoding. The usage of these will be discussed in more detail.
SOF 0x3737B57C
R_IP 0x5555B57C
HOLD 0xD5D5AA7C
HOLD_ACK 0x9595AA7C
EOF 0xD5D5B57C
WTRM 0x5858B57C
R_OK 0x3535B57C
R_ERR 0x5656B57C
CONT 0x9999AA7C
SATA Conclusion
Overall, SATA is a very suitable protocol for the mass storage design. It allows for high speed
storage compatible with almost any hard drive or SSD available on the market. Also, it is a very
robust protocol, making it suitable for use pretty much everywhere. Each and every frame has a
CRC to protect against bit errors. Low-voltage differential signaling adds noise immunity and
decreases power consumed. There are also numerous methods employed to reduce EMI.
Resources
[1] “Serial ATA: Meeting Storage Needs Today and Tomorrow”. SATA-IO.
http://www.serialata.org/documents/SATA-Rev-30-Presentation.pdf, Jun 2009.
[2] K. Grimsrud and H. Smith, Serial ATA Storage Architecture and Applications.
Hillsboro, OR: Intel Press, 2003.
[3] D. Anderson, SATA Storage Technology. Colorado Springs, CO: Mindshare Press, 2007.
[4] “Serial ATA I/II Host Controller (SATA_HI).” ASICS World Services.
http://www.xilinx.com/publications/3rd_party/products/ASICSWS_SATA_H1.p df, May 2008.
* Mr. Nikola Zlatanov spent over 20 years working in the Capital Semiconductor Equipment Industry. His work at Gasonics, Novellus,
Lam and KLA-Tencor involved progressing electrical engineering and management roles in disruptive technologies. Nikola received his
Undergraduate degree in Electrical Engineering and Computer Systems from Technical University, Sofia, Bulgaria and completed a
Graduate Program in Engineering Management at Santa Clara University. He is currently consulting for Fortune 500 companies as well
as Startup ventures in Silicon Valley, California.