Spruh73q PDF

AM335x and AMIC110 Sitara™ Processors
Technical Reference Manual
Literature Number: SPRUH73Q

October 2011 – Revised December 2019
Contents
Preface ..................................................................................................................................... 173

1 Introduction ..................................................................................................................... 174
1.1 AM335x Family ............................................................................................................ 174
1.1.1 Device Features.................................................................................................. 174
1.1.2 Device Identification ............................................................................................. 174
1.2 Silicon Revision Functional Differences and Enhancements ....................................................... 174
1.2.1 Added RTC Alarm Wakeup for DeepSleep Modes.......................................................... 174
1.2.2 Changed BOOTP Identifier ..................................................................................... 174
1.2.3 Changed Product String in USB Descriptor .................................................................. 175
1.2.4 Added DPLL Power Switch Control and Status Registers ................................................. 175
1.2.5 Added Control for CORE SRAM LDO Retention Mode..................................................... 175
1.2.6 Added Pin Mux Options for GPMC_A9 to Facilitate RMII Pin Muxing .................................... 175
1.2.7 Changed Polarity of Input Signal nNMI (Pin EXTINTn) ..................................................... 175
1.2.8 Changed Default Value of ncin and pcin Bits in vtp_ctrl Register ......................................... 176
1.2.9 Changed Default Value of RGMII Mode to No Internal Delay ............................................. 176
1.2.10 Changed Default Value of RMII Clock Source .............................................................. 176
1.2.11 Changed the Method of Determining Speed of Operation During EMAC Boot ........................ 176
1.2.12 Added EFUSE_SMA Register for Help Identifying Different Device Variants .......................... 176
2 Memory Map .................................................................................................................... 177
2.1 ARM Cortex-A8 Memory Map ........................................................................................... 177
3 ARM MPU Subsystem ....................................................................................................... 186
3.1 ARM Cortex-A8 MPU Subsystem ...................................................................................... 187
3.1.1 Features ........................................................................................................... 188
3.1.2 MPU Subsystem Integration.................................................................................... 188
3.1.3 MPU Subsystem Clock and Reset Distribution .............................................................. 189
3.1.4 ARM Subchip ..................................................................................................... 192
3.1.5 Interrupt Controller ............................................................................................... 193
3.1.6 Power Management ............................................................................................. 194
3.1.7 ARM Programming Model ...................................................................................... 196
4 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-
ICSS) ............................................................................................................................... 198
4.1 Introduction ................................................................................................................ 199
4.1.1 Features ........................................................................................................... 200
4.2 Integration.................................................................................................................. 201
4.2.1 PRU-ICSS Connectivity Attributes ............................................................................. 202
4.2.2 PRU-ICSS Clock and Reset Management ................................................................... 202
4.2.3 PRU-ICSS Pin List ............................................................................................... 203
4.2.4 PRU-ICSS Internal Pinmux ..................................................................................... 204
4.3 PRU-ICSS Memory Map Overview ..................................................................................... 206
4.3.1 Local Memory Map .............................................................................................. 206
4.3.2 Global Memory Map ............................................................................................. 207
4.4 Functional Description.................................................................................................... 208
4.4.1 PRU Cores........................................................................................................ 208
4.4.2 Interrupt Controller (INTC) ...................................................................................... 225
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4.4.3 Industrial Ethernet Peripheral (IEP) ........................................................................... 233

4.4.4 Universal Asynchronous Receiver/Transmitter (UART) .................................................... 241
4.4.5 ECAP .............................................................................................................. 254
4.4.6 MII_RT ............................................................................................................ 254
4.4.7 MDIO .............................................................................................................. 273
4.5 Registers ................................................................................................................... 274
4.5.1 PRU_ICSS_PRU_CTRL Registers ............................................................................ 274
4.5.2 PRU_ICSS_PRU_DEBUG Registers ......................................................................... 284
4.5.3 PRU_ICSS_INTC Registers .................................................................................... 349
4.5.4 PRU_ICSS_IEP Registers ...................................................................................... 413
4.5.5 PRU_ICSS_UART Registers ................................................................................... 464
4.5.6 PRU_ICSS_ECAP Registers ................................................................................... 483
4.5.7 PRU_ICSS_MII_RT Registers ................................................................................. 483
4.5.8 PRU_ICSS_MDIO Registers ................................................................................... 503
4.5.9 PRU_ICSS_CFG Registers .................................................................................... 503
5 Graphics Accelerator (SGX) ............................................................................................... 522
5.0.10 POWERVR SGX Main Features .............................................................................. 523
5.0.11 SGX 3D Features ............................................................................................... 524
5.0.12 Universal Scalable Shader Engine (USSE) – Key Features .............................................. 525
5.0.13 Unsupported Features ......................................................................................... 525
5.1 Integration.................................................................................................................. 526
5.1.1 SGX530 Connectivity Attributes ............................................................................... 526
5.1.2 SGX530 Clock and Reset Management ...................................................................... 526
5.1.3 SGX530 Pin List ................................................................................................. 527
5.2.1 SGX Block Diagram ............................................................................................. 528
5.2.2 SGX Elements Description ..................................................................................... 528
6 Interrupts ......................................................................................................................... 530
6.1.1 Interrupt Processing ............................................................................................ 532
6.1.2 Register Protection .............................................................................................. 533
6.1.3 Module Power Saving ........................................................................................... 533
6.1.4 Error Handling .................................................................................................... 533
6.1.5 Interrupt Handling ................................................................................................ 533
6.2 Basic Programming Model............................................................................................... 534
6.2.1 Initialization Sequence .......................................................................................... 534
6.2.2 INTC Processing Sequence .................................................................................... 534
6.2.3 INTC Preemptive Processing Sequence ..................................................................... 538
6.2.4 Interrupt Preemption ............................................................................................. 542
6.2.5 ARM A8 INTC Spurious Interrupt Handling .................................................................. 542
6.3 ARM Cortex-A8 Interrupts ............................................................................................... 543
6.4 Crypto DMA Events ...................................................................................................... 547
6.5 PWM Events ............................................................................................................... 549
6.6 Interrupt Controller Registers............................................................................................ 550
6.6.1 INTC Registers ................................................................................................... 550
7 Memory Subsystem .......................................................................................................... 596
7.1 GPMC ...................................................................................................................... 597
7.1.1 Introduction ....................................................................................................... 597
7.1.2 Integration......................................................................................................... 600
7.1.3 GPMC High-Level Programming Model Overview .......................................................... 681
7.1.4 Use Cases ........................................................................................................ 692
7.1.5 GPMC Registers ................................................................................................. 702
7.2 OCMC-RAM ............................................................................................................... 900
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7.2.1 Introduction ....................................................................................................... 900

7.2.2 Integration......................................................................................................... 901
7.3 EMIF ........................................................................................................................ 902
7.3.1 Introduction ....................................................................................................... 902
7.3.2 Integration......................................................................................................... 904
7.3.3 Functional Description........................................................................................... 906
7.3.4 Use Cases ........................................................................................................ 928
7.3.5 EMIF4D Registers ............................................................................................... 928
7.3.6 DDR2/3/mDDR PHY Registers ................................................................................ 972
7.4 ELM ......................................................................................................................... 982
7.4.1 Introduction ....................................................................................................... 982
7.4.2 Integration......................................................................................................... 983
7.4.3 Functional Description........................................................................................... 984
7.4.4 Basic Programming Model...................................................................................... 987
7.4.5 ELM Registers.................................................................................................... 992
8 Power, Reset, and Clock Management (PRCM) ................................................................... 1197
8.1 Power, Reset, and Clock Management .............................................................................. 1198
8.1.1 Introduction ..................................................................................................... 1198
8.1.2 Device Power-Management Architecture Building Blocks ............................................... 1198
8.1.3 Clock Management ............................................................................................ 1198
8.1.4 Power Management ........................................................................................... 1204
8.1.5 PRCM Module Overview ..................................................................................... 1215
8.1.6 Clock Generation and Management ......................................................................... 1217
8.1.7 Reset Management ............................................................................................ 1237
8.1.8 Power-Up/Down Sequence ................................................................................... 1248
8.1.9 IO State .......................................................................................................... 1249
8.1.10 Voltage and Power Domains ................................................................................ 1249
8.1.11 Device Modules and Power Management Attributes List ............................................... 1250
8.1.12 Clock Module Registers ...................................................................................... 1253
8.1.13 Power Management Registers .............................................................................. 1407
9 Control Module ............................................................................................................... 1448
9.1 Introduction ............................................................................................................... 1449
9.2 Functional Description .................................................................................................. 1449
9.2.1 Control Module Initialization................................................................................... 1449
9.2.2 Pad Control Registers ......................................................................................... 1449
9.2.3 EDMA Event Multiplexing ..................................................................................... 1451
9.2.4 Device Control and Status .................................................................................... 1451
9.2.5 DDR PHY........................................................................................................ 1457
9.3 Registers ................................................................................................................. 1458
9.3.1 CONTROL_MODULE Registers ............................................................................. 1458
10 Interconnects ................................................................................................................. 1561
10.1 Introduction ............................................................................................................... 1562
10.1.1 Terminology .................................................................................................... 1562
10.1.2 L3 Interconnect ................................................................................................ 1562
10.1.3 L4 Interconnect ................................................................................................ 1565
11 Enhanced Direct Memory Access (EDMA) .......................................................................... 1566
11.1 Introduction ............................................................................................................... 1567
11.1.1 EDMA3 Controller Block Diagram .......................................................................... 1567
11.1.2 Third-Party Channel Controller (TPCC) Overview ........................................................ 1568
11.1.3 Third-Party Transfer Controller (TPTC) Overview ........................................................ 1570
11.2 Integration ................................................................................................................ 1571
11.2.1 Third-Party Channel Controller (TPCC) Integration ...................................................... 1571

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11.2.2 Third-Party Transfer Controller (TPTC) Integration ....................................................... 1572

11.3.1 Functional Overview .......................................................................................... 1574
11.3.2 Types of EDMA3 Transfers .................................................................................. 1577
11.3.3 Parameter RAM (PaRAM) ................................................................................... 1579
11.3.4 Initiating a DMA Transfer ..................................................................................... 1591
11.3.5 Completion of a DMA Transfer .............................................................................. 1594
11.3.6 Event, Channel, and PaRAM Mapping ..................................................................... 1595
11.3.7 EDMA3 Channel Controller Regions ....................................................................... 1597
11.3.8 Chaining EDMA3 Channels .................................................................................. 1600
11.3.9 EDMA3 Interrupts ............................................................................................. 1600
11.3.10 Memory Protection .......................................................................................... 1607
11.3.11 Event Queues ................................................................................................ 1611
11.3.12 EDMA3 Transfer Controller (EDMA3TC) ................................................................. 1613
11.3.13 Event Dataflow ............................................................................................... 1616
11.3.14 EDMA3 Prioritization ........................................................................................ 1616
11.3.15 EDMA3 Operating Frequency (Clock Control) ........................................................... 1617
11.3.16 Reset Considerations ....................................................................................... 1617
11.3.17 Power Management ......................................................................................... 1617
11.3.18 Emulation Considerations .................................................................................. 1617
11.3.19 EDMA Transfer Examples .................................................................................. 1619
11.3.20 EDMA Events ................................................................................................ 1635
11.4 EDMA3 Registers ....................................................................................................... 1638
11.4.1 EDMA3CC Registers ......................................................................................... 1638
11.4.2 EDMA3TC Registers .......................................................................................... 1773
11.5 Appendix A ............................................................................................................... 1826
11.5.1 Debug Checklist ............................................................................................... 1826
11.5.2 Miscellaneous Programming/Debug Tips .................................................................. 1827
11.5.3 Setting Up a Transfer ......................................................................................... 1829
12 Touchscreen Controller ................................................................................................... 1831
12.1 Introduction ............................................................................................................... 1832
12.1.1 TSC_ADC Features ........................................................................................... 1832
12.1.2 Unsupported TSC_ADC_SS Features ..................................................................... 1832
12.2 Integration ................................................................................................................ 1833
12.2.1 TSC_ADC Connectivity Attributes .......................................................................... 1833
12.2.2 TSC_ADC Clock and Reset Management ................................................................. 1834
12.2.3 TSC_ADC Pin List ............................................................................................ 1834
12.3.1 Hardware-Synchronized or Software-Enabled ............................................................ 1835
12.3.2 Open Delay and Sample Delay ............................................................................. 1835
12.3.3 Averaging of Samples (1, 2, 4, 8, and 16) ................................................................. 1835
12.3.4 One-Shot (Single) or Continuous Mode ................................................................... 1835
12.3.5 Interrupts ....................................................................................................... 1835
12.3.6 DMA Requests ................................................................................................ 1836
12.3.7 Analog Front End (AFE) Functional Block Diagram ..................................................... 1836
12.4 Operational Modes ...................................................................................................... 1838
12.4.1 PenCtrl and PenIRQ .......................................................................................... 1839
12.5 Touchscreen Controller Registers .................................................................................... 1842
12.5.1 TSC_ADC_SS Registers ..................................................................................... 1842
13 LCD Controller ................................................................................................................ 1924
13.1 Introduction ............................................................................................................... 1925
13.1.1 Purpose of the Peripheral .................................................................................... 1925
13.1.2 Features ........................................................................................................ 1926

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13.2 Integration ................................................................................................................ 1927

13.2.1 LCD Controller Connectivity Attributes ..................................................................... 1927
13.2.2 LCD Controller Clock and Reset Management............................................................ 1928
13.2.3 LCD Controller Pin List ....................................................................................... 1928
13.3.1 Clocking ........................................................................................................ 1929
13.3.2 LCD External I/O Signals..................................................................................... 1931
13.3.3 Pin Mapping and Color Assignments ....................................................................... 1931
13.3.4 DMA Engine ................................................................................................... 1932
13.3.5 LIDD Controller ................................................................................................ 1933
13.3.6 Raster Controller .............................................................................................. 1939
13.3.7 Interrupt Conditions ........................................................................................... 1953
13.3.8 DMA ............................................................................................................. 1955
13.3.9 Power Management .......................................................................................... 1955
13.4 Programming Model .................................................................................................... 1956
13.4.1 LCD Character Displays ...................................................................................... 1956
13.4.2 Active Matrix Displays ........................................................................................ 1959
13.4.3 System Interaction ............................................................................................ 1959
13.4.4 Palette Lookup ................................................................................................. 1959
13.4.5 Test Logic ...................................................................................................... 1961
13.4.6 Disable and Software Reset Sequence .................................................................... 1961
13.4.7 Precedence Order for Determining Frame Buffer Type .................................................. 1962
13.5 Registers ................................................................................................................. 1963
13.5.1 LCD Registers ................................................................................................. 1963
14 Ethernet Subsystem ........................................................................................................ 2000
14.1 Introduction ............................................................................................................... 2001
14.1.1 Features ........................................................................................................ 2001
14.1.2 Unsupported Features ........................................................................................ 2002
14.2 Integration ................................................................................................................ 2003
14.2.1 Ethernet Switch Connectivity Attributes .................................................................... 2004
14.2.2 Ethernet Switch Clock and Reset Management .......................................................... 2005
14.2.3 Ethernet Switch Pin List ...................................................................................... 2006
14.2.4 Ethernet Switch RMII Clocking Details ..................................................................... 2006
14.2.5 GMII Interface Signal Connections and Descriptions .................................................... 2007
14.2.6 RMII Signal Connections and Descriptions ................................................................ 2009
14.2.7 RGMII Signal Connections and Descriptions .............................................................. 2011
14.3.1 CPSW_3G Subsystem ....................................................................................... 2013
14.3.2 CPSW_3G...................................................................................................... 2018
14.3.3 Ethernet Mac Sliver (CPGMAC_SL) ....................................................................... 2061
14.3.4 Command IDLE ............................................................................................... 2063
14.3.5 RMII Interface .................................................................................................. 2063
14.3.6 RGMII Interface ................................................................................................ 2064
14.3.7 Common Platform Time Sync (CPTS) ..................................................................... 2065
14.3.8 MDIO ............................................................................................................ 2070
14.4 Software Operation ..................................................................................................... 2073
14.4.1 Transmit Operation............................................................................................ 2073
14.4.2 Receive Operation ............................................................................................ 2075
14.4.3 Initializing the MDIO Module ................................................................................. 2076
14.4.4 Writing Data to a PHY Register ............................................................................. 2076
14.4.5 Reading Data from a PHY Register ........................................................................ 2077
14.4.6 Initialization and Configuration of CPSW .................................................................. 2077
14.5 Ethernet Subsystem Registers ........................................................................................ 2078

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14.5.1 CPSW_ALE Registers ........................................................................................ 2078

14.5.2 CPSW_CPDMA Registers ................................................................................... 2093
14.5.3 CPSW_CPTS Registers ...................................................................................... 2148
14.5.4 CPSW_STATS Registers .................................................................................... 2161
14.5.5 CPDMA_STATERAM Registers............................................................................. 2161
14.5.6 CPSW_PORT Registers ..................................................................................... 2195
14.5.7 CPSW_SL Registers .......................................................................................... 2250
14.5.8 CPSW_SS Registers ......................................................................................... 2264
14.5.9 CPSW_WR Registers ........................................................................................ 2277
14.5.10 MDIO Registers .............................................................................................. 2313
15 Pulse-Width Modulation Subsystem (PWMSS) .................................................................... 2324
15.1 Pulse-Width Modulation Subsystem (PWMSS) ..................................................................... 2325
15.1.1 Introduction ..................................................................................................... 2325
15.1.2 Integration ...................................................................................................... 2327
15.1.3 PWMSS Registers ............................................................................................ 2329
15.2 Enhanced PWM (ePWM) Module ..................................................................................... 2334
15.2.1 Introduction ..................................................................................................... 2334
15.2.2 Functional Description ........................................................................................ 2338
15.2.3 Use Cases ..................................................................................................... 2409
15.2.4 EPWM Registers .............................................................................................. 2433
15.3 Enhanced Capture (eCAP) Module ................................................................................... 2469
15.3.1 Introduction ..................................................................................................... 2469
15.3.3 Use Cases ..................................................................................................... 2479
15.3.4 Registers ....................................................................................................... 2495
15.4 Enhanced Quadrature Encoder Pulse (eQEP) Module ............................................................ 2511
15.4.1 Introduction ..................................................................................................... 2511
15.4.3 EQEP Registers ............................................................................................... 2532
16 Universal Serial Bus (USB) ............................................................................................... 2559
16.0.4 Acronyms, Abbreviations, and Definitions ................................................................. 2560
16.0.5 Unsupported USB OTG and PHY Features ............................................................... 2562
16.1 Integration ................................................................................................................ 2563
16.1.1 USB Connectivity Attributes ................................................................................. 2563
16.1.2 USB Clock and Reset Management ........................................................................ 2564
16.1.3 USB Pin List ................................................................................................... 2564
16.1.4 USB GPIO Details............................................................................................. 2564
16.1.5 USB Unbonded PHY Pads................................................................................... 2565
16.2.1 VBUS Voltage Sourcing Control ............................................................................ 2566
16.2.2 Pullup/PullDown Resistors ................................................................................... 2566
16.2.3 Role Assuming Method ....................................................................................... 2567
16.2.4 Clock, PLL, and PHY Initialization .......................................................................... 2567
16.2.5 Indexed and Non-Indexed Register Spaces ............................................................... 2567
16.2.6 Dynamic FIFO Sizing ......................................................................................... 2567
16.2.7 USB Controller Host and Peripheral Modes Operation .................................................. 2568
16.2.8 Protocol Description(s) ....................................................................................... 2570
16.2.9 Communications Port Programming Interface (CPPI) 4.1 DMA ........................................ 2603
16.2.10 USB 2.0 Test Modes ........................................................................................ 2627
16.3 Supported Use Cases .................................................................................................. 2629
16.4 USB Registers ........................................................................................................... 2630
16.4.1 USBSS Registers ............................................................................................. 2630
16.4.2 USB0_CTRL Registers ....................................................................................... 2675

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16.4.3 USB1_CTRL Registers ....................................................................................... 2725

16.4.4 USB2PHY Registers .......................................................................................... 2773
16.4.5 CPPI_DMA Registers ......................................................................................... 2798
16.4.6 CPPI_DMA_SCHEDULER Registers....................................................................... 2954
16.4.7 QUEUE_MGR Registers ..................................................................................... 2957
17 Interprocessor Communication......................................................................................... 4108
17.1 Mailbox ................................................................................................................... 4109
17.1.1 Introduction ..................................................................................................... 4109
17.1.2 Programming Guide .......................................................................................... 4115
17.1.3 MAILBOX Registers .......................................................................................... 4118
17.2 Spinlock................................................................................................................... 4179
17.2.1 SPINLOCK Registers ......................................................................................... 4179
18 Multimedia Card (MMC) .................................................................................................... 4217
18.1 Introduction ............................................................................................................... 4218
18.1.1 MMCHS Features ............................................................................................. 4218
18.1.2 Unsupported MMCHS Features ............................................................................. 4218
18.2 Integration ................................................................................................................ 4219
18.2.1 MMCHS Connectivity Attributes ............................................................................. 4220
18.2.2 MMCHS Clock and Reset Management ................................................................... 4221
18.2.3 MMCHS Pin List ............................................................................................... 4221
18.3.1 MMC/SD/SDIO Functional Modes .......................................................................... 4223
18.3.2 Resets .......................................................................................................... 4229
18.3.4 Interrupt Requests ............................................................................................ 4233
18.3.5 DMA Modes ................................................................................................... 4235
18.3.6 Mode Selection ................................................................................................ 4238
18.3.7 Buffer Management ........................................................................................... 4238
18.3.8 Transfer Process .............................................................................................. 4241
18.3.9 Transfer or Command Status and Error Reporting ....................................................... 4242
18.3.10 Auto Command 12 Timings ................................................................................ 4247
18.3.11 Transfer Stop ................................................................................................. 4249
18.3.12 Output Signals Generation ................................................................................. 4250
18.3.13 Card Boot Mode Management ............................................................................. 4252
18.3.14 CE-ATA Command Completion Disable Management ................................................. 4254
18.3.15 Test Registers ................................................................................................ 4254
18.3.16 MMC/SD/SDIO Hardware Status Features .............................................................. 4255
18.4 Low-Level Programming Models ...................................................................................... 4256
18.4.1 Surrounding Modules Global Initialization ................................................................. 4256
18.4.2 MMC/SD/SDIO Controller Initialization Flow .............................................................. 4256
18.4.3 Operational Modes Configuration ........................................................................... 4259
18.5 Multimedia Card Registers ............................................................................................. 4261
18.5.1 MULTIMEDIA_CARD Registers ............................................................................. 4261
19 Universal Asynchronous Receiver/Transmitter (UART) ........................................................ 4318
19.1 Introduction ............................................................................................................... 4319
19.1.1 UART Mode Features ........................................................................................ 4319
19.1.2 IrDA Mode Features .......................................................................................... 4319
19.1.3 CIR Mode Features ........................................................................................... 4319
19.1.4 Unsupported UART Features ................................................................................ 4319
19.2 Integration ................................................................................................................ 4321
19.2.1 UART Connectivity Attributes ................................................................................ 4321
19.2.2 UART Clock and Reset Management ...................................................................... 4322
19.2.3 UART Pin List .................................................................................................. 4324

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19.3.1 Block Diagram ................................................................................................. 4325
19.3.2 Clock Configuration ........................................................................................... 4326
19.3.3 Software Reset ................................................................................................ 4326
19.3.5 Interrupt Requests ............................................................................................ 4328
19.3.6 FIFO Management ............................................................................................ 4331
19.3.7 Mode Selection ................................................................................................ 4339
19.3.8 Protocol Formatting ........................................................................................... 4345
19.4 UART/IrDA/CIR Basic Programming Model ......................................................................... 4368
19.4.1 UART Programming Model .................................................................................. 4368
19.4.2 IrDA Programming Model .................................................................................... 4374
19.5 UART Registers ......................................................................................................... 4377
19.5.1 UART Registers ............................................................................................... 4377
20 Timers ........................................................................................................................... 4435
20.1 DMTimer .................................................................................................................. 4436
20.1.1 Introduction ..................................................................................................... 4436
20.1.2 Integration ...................................................................................................... 4438
20.1.4 Use Cases ..................................................................................................... 4451
20.1.5 TIMER Registers .............................................................................................. 4451
20.2 DMTimer 1ms ............................................................................................................ 4470
20.2.1 Introduction ..................................................................................................... 4470
20.2.2 Integration ...................................................................................................... 4472
20.2.4 DMTIMER_1MS Registers ................................................................................... 4482
20.3 RTC_SS .................................................................................................................. 4506
20.3.1 Introduction ..................................................................................................... 4506
20.3.2 Integration ...................................................................................................... 4507
20.3.4 Use Cases ..................................................................................................... 4517
20.3.5 RTC Registers ................................................................................................. 4517
20.4 WATCHDOG ............................................................................................................. 4555
20.4.1 Introduction ..................................................................................................... 4555
20.4.2 Integration ...................................................................................................... 4556
20.4.4 Watchdog Registers .......................................................................................... 4565
21 I2C ................................................................................................................................ 4583
21.1 Introduction ............................................................................................................... 4584
21.1.1 I2C Features ................................................................................................... 4584
21.1.2 Unsupported I2C Features ................................................................................... 4584
21.2 Integration ................................................................................................................ 4585
21.2.1 I2C Connectivity Attributes ................................................................................... 4585
21.2.2 I2C Clock and Reset Management ......................................................................... 4586
21.2.3 I2C Pin List ..................................................................................................... 4586
21.3.1 Functional Block Diagram .................................................................................... 4587
21.3.2 I2C Master/Slave Contoller Signals ......................................................................... 4587
21.3.3 I2C Reset ....................................................................................................... 4588
21.3.4 Data Validity ................................................................................................... 4589
21.3.5 START & STOP Conditions.................................................................................. 4590
21.3.6 I2C Operation .................................................................................................. 4590
21.3.7 Arbitration ...................................................................................................... 4592

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21.3.8 I2C Clock Generation and I2C Clock Synchronization ................................................... 4592
21.3.9 Prescaler (SCLK/ICLK) ....................................................................................... 4593
21.3.10 Noise Filter ................................................................................................... 4593
21.3.11 I2C Interrupts ................................................................................................. 4593
21.3.12 DMA Events .................................................................................................. 4594
21.3.13 Interrupt and DMA Events .................................................................................. 4594
21.3.14 FIFO Management .......................................................................................... 4594
21.3.15 How to Program I2C......................................................................................... 4599
21.3.16 I2C Behavior During Emulation ............................................................................ 4600
21.4 I2C Registers ............................................................................................................ 4601
21.4.1 I2C Registers .................................................................................................. 4601
22 Multichannel Audio Serial Port (McASP) ............................................................................ 4652
22.1 Introduction ............................................................................................................... 4653
22.1.2 Features ........................................................................................................ 4653
22.1.3 Protocols Supported ......................................................................................... 4654
22.1.4 Unsupported McASP Features .............................................................................. 4654
22.2 Integration ................................................................................................................ 4655
22.2.1 McASP Connectivity Attributes .............................................................................. 4655
22.2.2 McASP Clock and Reset Management .................................................................... 4656
22.2.3 McASP Pin List ................................................................................................ 4656
22.3.1 Overview ....................................................................................................... 4657
22.3.2 Functional Block Diagram .................................................................................... 4658
22.3.3 Industry Standard Compliance Statement ................................................................. 4661
22.3.4 Definition of Terms ............................................................................................ 4665
22.3.5 Clock and Frame Sync Generators ......................................................................... 4667
22.3.6 Signal Descriptions............................................................................................ 4671
22.3.7 Pin Multiplexing ................................................................................................ 4671
22.3.8 Transfer Modes ................................................................................................ 4672
22.3.9 General Architecture .......................................................................................... 4679
22.3.10 Operation ..................................................................................................... 4683
22.3.11 Reset Considerations ....................................................................................... 4700
22.3.12 Setup and Initialization ...................................................................................... 4700
22.3.13 Interrupts ...................................................................................................... 4705
22.3.14 EDMA Event Support ....................................................................................... 4707
22.3.15 Power Management ......................................................................................... 4709
22.3.16 Emulation Considerations .................................................................................. 4709
22.4 Registers ................................................................................................................. 4710
22.4.1 MCASP Registers ............................................................................................. 4710
23 Controller Area Network (CAN) ......................................................................................... 4772
23.1 Introduction ............................................................................................................... 4773
23.1.1 DCAN Features ................................................................................................ 4773
23.1.2 Unsupported DCAN Features ............................................................................... 4773
23.2 Integration ................................................................................................................ 4774
23.2.1 DCAN Connectivity Attributes ............................................................................... 4774
23.2.2 DCAN Clock and Reset Management ...................................................................... 4775
23.2.3 DCAN Pin List ................................................................................................. 4775
23.3.1 CAN Core ...................................................................................................... 4776
23.3.2 Message Handler ............................................................................................. 4777
23.3.3 Message RAM ................................................................................................. 4777
23.3.4 Message RAM Interface ...................................................................................... 4777

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23.3.5 Registers and Message Object Access .................................................................... 4777

23.3.6 Module Interface............................................................................................... 4777
23.3.7 Dual Clock Source ............................................................................................ 4777
23.3.8 CAN Operation ................................................................................................ 4778
23.3.9 Dual Clock Source ............................................................................................ 4784
23.3.10 Interrupt Functionality ....................................................................................... 4785
23.3.11 Local Power-Down Mode ................................................................................... 4787
23.3.12 Parity Check Mechanism ................................................................................... 4789
23.3.13 Debug/Suspend Mode ...................................................................................... 4790
23.3.14 Configuration of Message Objects ........................................................................ 4790
23.3.15 Message Handling ........................................................................................... 4793
23.3.16 CAN Bit Timing ............................................................................................... 4798
23.3.17 Message Interface Register Sets .......................................................................... 4806
23.3.18 Message RAM ............................................................................................... 4808
23.3.19 GIO Support .................................................................................................. 4813
23.4 Registers ................................................................................................................. 4814
23.4.1 DCAN Registers ............................................................................................... 4814
24 Multichannel Serial Port Interface (McSPI).......................................................................... 4885
24.1 Introduction ............................................................................................................... 4886
24.1.1 McSPI Features ............................................................................................... 4886
24.1.2 Unsupported McSPI Features ............................................................................... 4886
24.2 Integration ................................................................................................................ 4887
24.2.1 McSPI Connectivity Attributes ............................................................................... 4888
24.2.2 McSPI Clock and Reset Management ..................................................................... 4888
24.2.3 McSPI Pin List ................................................................................................. 4888
24.3.1 SPI Transmission ............................................................................................. 4889
24.3.2 Master Mode .................................................................................................. 4896
24.3.3 Slave Mode .................................................................................................... 4913
24.3.4 Interrupts ....................................................................................................... 4917
24.3.5 DMA Requests ................................................................................................ 4918
24.3.6 Emulation Mode .............................................................................................. 4919
24.3.7 Power Saving Management ................................................................................. 4920
24.3.8 System Test Mode ........................................................................................... 4921
24.3.9 Reset ........................................................................................................... 4921
24.3.10 Access to Data Registers .................................................................................. 4922
24.3.11 Programming Aid ........................................................................................... 4922
24.3.12 Interrupt and DMA Events ................................................................................. 4923
24.4 McSPI Registers ......................................................................................................... 4923
24.4.1 SPI Registers .................................................................................................. 4923
25 General-Purpose Input/Output .......................................................................................... 4976
25.1 Introduction ............................................................................................................... 4977
25.1.2 GPIO Features ................................................................................................ 4977
25.1.3 Unsupported GPIO Features ................................................................................ 4977
25.2 Integration ................................................................................................................ 4978
25.2.1 GPIO Connectivity Attributes ................................................................................ 4978
25.2.2 GPIO Clock and Reset Management ....................................................................... 4979
25.2.3 GPIO Pin List .................................................................................................. 4980
25.3.1 Operating Modes .............................................................................................. 4981
25.3.2 Clocking and Reset Strategy ................................................................................ 4981
25.3.3 Interrupt and Wake-up Features ............................................................................ 4982

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25.3.4 General-Purpose Interface Basic Programming Model .................................................. 4985

25.4 GPIO Registers .......................................................................................................... 4990
25.4.1 GPIO Registers ................................................................................................ 4990
26 Initialization .................................................................................................................... 5017
26.1.1 Device Types .................................................................................................. 5018
26.1.2 Architecture .................................................................................................... 5018
26.1.3 Functionality.................................................................................................... 5019
26.1.4 Memory Map ................................................................................................... 5021
26.1.5 Start-up and Configuration ................................................................................... 5025
26.1.6 Booting.......................................................................................................... 5028
26.1.7 Fast External Booting ......................................................................................... 5037
26.1.8 Memory Booting ............................................................................................... 5039
26.1.9 Peripheral Booting ............................................................................................ 5068
26.1.10 Image Format ................................................................................................ 5075
26.1.11 Table of Contents ............................................................................................ 5077
26.1.12 Authentication and Code Execution ....................................................................... 5078
26.1.13 Wakeup ....................................................................................................... 5079
26.1.14 Tracing ........................................................................................................ 5081
27 Debug Subsystem ........................................................................................................... 5084
27.1.1 Debug Resource Manager (DRM) .......................................................................... 5085
27.1.2 Debug Ports .................................................................................................... 5085
27.2 Registers ................................................................................................................. 5088
27.2.1 Debug Resource Manager (DebugSS_DRM) Registers ................................................. 5088
A Glossary ........................................................................................................................ 5090
Revision History — Version Q ................................................................................................... 5110
Revision History — Version P .................................................................................................... 5112
Revision History — Version O ................................................................................................... 5113
Revision History — Version N.................................................................................................... 5114
Revision History — Version M ................................................................................................... 5115
Revision History — Version L .................................................................................................... 5116
B Revision History ............................................................................................................. 5117

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List of Figures
3-1. Microprocessor Unit (MPU) Subsystem ............................................................................... 187
3-2. Microprocessor Unit (MPU) Subsystem Signal Interface ............................................................ 189
3-3. MPU Subsystem Clocking Scheme .................................................................................... 190
3-4. Reset Scheme of the MPU Subsystem ................................................................................ 191
3-5. MPU Subsystem Power Domain Overview............................................................................ 194
4-1. PRU-ICSS Block Diagram ............................................................................................... 199
4-2. PRU-ICSS Integration .................................................................................................... 201
4-3. PRU-ICSS Internal Signal Muxing: pin_mux_sel[0] .................................................................. 204
4-5. PRU Block Diagram ...................................................................................................... 209
4-6. PRU Module Interface .................................................................................................... 211
4-7. Event Interface Mapping (R31) ......................................................................................... 212
4-8. PRU R31 (GPI) Direct Input Mode Block Diagram ................................................................... 215
4-9. PRU R31 (GPI) 16-Bit Parallel Capture Mode Block Diagram...................................................... 215
4-10. PRU R31 (GPI) 28-Bit Shift In Mode ................................................................................... 216
4-11. PRU R30 (GPO) Direct Output Mode Block Diagram ............................................................... 218
4-12. PRU R30 (GPO) Shift Out Mode Block Diagram ..................................................................... 219
4-13. Integration of the PRU and MPY/MAC ................................................................................. 220
4-14. Multiply-Only Mode Functional Diagram ............................................................................... 221
4-15. Multiply and Accumulate Mode Functional Diagram ................................................................. 222
4-16. Integration of PRU and Scratch Pad ................................................................................... 223
4-17. Interrupt Controller Block Diagram ..................................................................................... 226
4-18. Flow of System Events to Host ......................................................................................... 229
4-19. Industrial Ethernet Peripheral Block Diagram ......................................................................... 233
4-20. Sync Signal Generation Mode .......................................................................................... 236
4-21. Examples of the Dependent Mode of SYNC1 ........................................................................ 237
4-22. IEP DIGIO Data In ........................................................................................................ 239
4-23. IEP DIGIO Data Out ...................................................................................................... 240
4-24. UART Block Diagram..................................................................................................... 242
4-25. UART Clock Generation Diagram ...................................................................................... 243
4-26. Relationships Between Data Bit, BCLK, and UART Input Clock ................................................... 244
4-27. UART Protocol Formats.................................................................................................. 246
4-28. UART Interface Using Autoflow Diagram .............................................................................. 249
4-29. Autoflow Functional Timing Waveforms for UARTn_RTS .......................................................... 250
4-30. Autoflow Functional Timing Waveforms for UARTn_CTS .......................................................... 250
4-31. UART Interrupt Request Enable Paths ................................................................................ 252
4-32. MII_RT Block Diagram ................................................................................................... 255
4-33. Auto-forward ............................................................................................................... 255
4-34. Auto-forward with PRU Snoop .......................................................................................... 256
4-35. 8- or 16-bit Processing with On-the-Fly Modifications ............................................................... 256
4-36. 32-byte Double Buffer or Ping-Pong Processing .................................................................... 256
4-37. Data Nibble Structure .................................................................................................... 257
4-38. PRU R30, R31 Operations .............................................................................................. 257
4-39. Reading and Writing FIFO Data ........................................................................................ 258
4-40. RX Data Latch ............................................................................................................. 259
4-41. Start of Frame Detection ................................................................................................. 260
4-42. CRC Error Detection ..................................................................................................... 260
SPRUH73Q – October 2011 – Revised December 2019 List of Figures 13

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4-43. RX Error Detection........................................................................................................ 260

4-44. Error Detection Window with Running Counter ....................................................................... 261
4-45. RX L1 to PRU Interface .................................................................................................. 261
4-46. MII RX Data to PRU R31 (R) and RX FIFO ........................................................................... 262
4-47. RX L2 to PRU Interface .................................................................................................. 265
4-48. Data and Status Register Dependency ................................................................................ 265
4-49. PRU to TX L1 Interface .................................................................................................. 268
4-50. PRU to TX MII Interface ................................................................................................. 268
4-51. TX Mask Mode ............................................................................................................ 269
4-52. RX L1 to TX L1 Interface ................................................................................................ 269
4-53. MII Receive Multiplexer .................................................................................................. 272
4-54. MII Transmit Multiplexer ................................................................................................. 272
4-55. Scratch Pad Mode ........................................................................................................ 272
4-56. CTRL Register ............................................................................................................ 275
4-57. STS Register .............................................................................................................. 277
4-58. WAKEUP_EN Register .................................................................................................. 278
4-59. CYCLE Register .......................................................................................................... 279
4-60. STALL Register ........................................................................................................... 280
4-61. CTBIR0 Register .......................................................................................................... 281
4-62. CTBIR1 Register .......................................................................................................... 282
4-63. CTPPR0 Register ......................................................................................................... 283
4-64. CTPPR1 Register ......................................................................................................... 284
4-65. GPREG0 Register ........................................................................................................ 286
4-66. GPREG1 Register ........................................................................................................ 287
4-67. GPREG2 Register ........................................................................................................ 288
4-68. GPREG3 Register ........................................................................................................ 289
4-69. GPREG4 Register ........................................................................................................ 290
4-70. GPREG5 Register ........................................................................................................ 291
4-71. GPREG6 Register ........................................................................................................ 292
4-72. GPREG7 Register ........................................................................................................ 293
4-73. GPREG8 Register ........................................................................................................ 294
4-74. GPREG9 Register ........................................................................................................ 295
4-75. GPREG10 Register ....................................................................................................... 296
4-76. GPREG11 Register ....................................................................................................... 297
4-77. GPREG12 Register ....................................................................................................... 298
4-78. GPREG13 Register ....................................................................................................... 299
4-79. GPREG14 Register ....................................................................................................... 300
4-80. GPREG15 Register ....................................................................................................... 301
4-81. GPREG16 Register ....................................................................................................... 302
4-82. GPREG17 Register ....................................................................................................... 303
4-83. GPREG18 Register ....................................................................................................... 304
4-84. GPREG19 Register ....................................................................................................... 305
4-85. GPREG20 Register ....................................................................................................... 306
4-86. GPREG21 Register ....................................................................................................... 307
4-87. GPREG22 Register ....................................................................................................... 308
4-88. GPREG23 Register ....................................................................................................... 309
4-89. GPREG24 Register ....................................................................................................... 310
4-90. GPREG25 Register ....................................................................................................... 311
4-91. GPREG26 Register ....................................................................................................... 312
14 List of Figures SPRUH73Q – October 2011 – Revised December 2019

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4-92. GPREG27 Register ....................................................................................................... 313

4-93. GPREG28 Register ....................................................................................................... 314
4-94. GPREG29 Register ....................................................................................................... 315
4-95. GPREG30 Register ....................................................................................................... 316
4-96. GPREG31 Register ....................................................................................................... 317
4-97. CT_REG0 Register ....................................................................................................... 318
4-98. CT_REG1 Register ....................................................................................................... 319
4-99. CT_REG2 Register ....................................................................................................... 320
4-100. CT_REG3 Register ....................................................................................................... 321
4-101. CT_REG4 Register ....................................................................................................... 322
4-102. CT_REG5 Register ....................................................................................................... 323
4-103. CT_REG6 Register ....................................................................................................... 324
4-104. CT_REG7 Register ....................................................................................................... 325
4-105. CT_REG8 Register ....................................................................................................... 326
4-106. CT_REG9 Register ....................................................................................................... 327
4-107. CT_REG10 Register ..................................................................................................... 328
4-108. CT_REG11 Register ..................................................................................................... 329
4-109. CT_REG12 Register ..................................................................................................... 330
4-110. CT_REG13 Register ..................................................................................................... 331
4-111. CT_REG14 Register ..................................................................................................... 332
4-112. CT_REG15 Register ..................................................................................................... 333
4-113. CT_REG16 Register ..................................................................................................... 334
4-114. CT_REG17 Register ..................................................................................................... 335
4-115. CT_REG18 Register ..................................................................................................... 336
4-116. CT_REG19 Register ..................................................................................................... 337
4-117. CT_REG20 Register ..................................................................................................... 338
4-118. CT_REG21 Register ..................................................................................................... 339
4-119. CT_REG22 Register ..................................................................................................... 340
4-120. CT_REG23 Register ..................................................................................................... 341
4-121. CT_REG24 Register ..................................................................................................... 342
4-122. CT_REG25 Register ..................................................................................................... 343
4-123. CT_REG26 Register ..................................................................................................... 344
4-124. CT_REG27 Register ..................................................................................................... 345
4-125. CT_REG28 Register ..................................................................................................... 346
4-126. CT_REG29 Register ..................................................................................................... 347
4-127. CT_REG30 Register ..................................................................................................... 348
4-128. CT_REG31 Register ..................................................................................................... 349
4-129. REVID Register ........................................................................................................... 351
4-130. CR Register................................................................................................................ 352
4-131. GER Register.............................................................................................................. 353
4-132. GNLR Register ............................................................................................................ 354
4-133. SISR Register ............................................................................................................. 355
4-134. SICR Register ............................................................................................................. 356
4-135. EISR Register ............................................................................................................. 357
4-136. EICR Register ............................................................................................................. 358
4-137. HIEISR Register .......................................................................................................... 359
4-138. HIDISR Register .......................................................................................................... 360
4-139. GPIR Register ............................................................................................................. 361
4-140. SRSR0 Register .......................................................................................................... 362

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4-141. SRSR1 Register .......................................................................................................... 363

4-142. SECR0 Register .......................................................................................................... 364
4-143. SECR1 Register .......................................................................................................... 365
4-144. ESR0 Register ............................................................................................................ 366
4-145. ESR1 Register ............................................................................................................ 367
4-146. ECR0 Register ............................................................................................................ 368
4-147. ECR1 Register ............................................................................................................ 369
4-148. CMR0 Register ............................................................................................................ 370
4-149. CMR1 Register ............................................................................................................ 371
4-150. CMR2 Register ............................................................................................................ 372
4-151. CMR3 Register ............................................................................................................ 373
4-152. CMR4 Register ............................................................................................................ 374
4-153. CMR5 Register ............................................................................................................ 375
4-154. CMR6 Register ............................................................................................................ 376
4-155. CMR7 Register ............................................................................................................ 377
4-156. CMR8 Register ............................................................................................................ 378
4-157. CMR9 Register ............................................................................................................ 379
4-158. CMR10 Register .......................................................................................................... 380
4-159. CMR11 Register .......................................................................................................... 381
4-160. CMR12 Register .......................................................................................................... 382
4-161. CMR13 Register .......................................................................................................... 383
4-162. CMR14 Register .......................................................................................................... 384
4-163. CMR15 Register .......................................................................................................... 385
4-164. HMR0 Register ............................................................................................................ 386
4-165. HMR1 Register ............................................................................................................ 387
4-166. HMR2 Register ............................................................................................................ 388
4-167. HIPIR0 Register ........................................................................................................... 389
4-168. HIPIR1 Register ........................................................................................................... 390
4-169. HIPIR2 Register ........................................................................................................... 391
4-170. HIPIR3 Register ........................................................................................................... 392
4-171. HIPIR4 Register ........................................................................................................... 393
4-172. HIPIR5 Register ........................................................................................................... 394
4-173. HIPIR6 Register ........................................................................................................... 395
4-174. HIPIR7 Register ........................................................................................................... 396
4-175. HIPIR8 Register ........................................................................................................... 397
4-176. HIPIR9 Register ........................................................................................................... 398
4-177. SIPR0 Register ............................................................................................................ 399
4-178. SIPR1 Register ............................................................................................................ 400
4-179. SITR0 Register ............................................................................................................ 401
4-180. SITR1 Register ............................................................................................................ 402
4-181. HINLR0 Register .......................................................................................................... 403
4-182. HINLR1 Register .......................................................................................................... 404
4-183. HINLR2 Register .......................................................................................................... 405
4-184. HINLR3 Register .......................................................................................................... 406
4-185. HINLR4 Register .......................................................................................................... 407
4-186. HINLR5 Register .......................................................................................................... 408
4-187. HINLR6 Register .......................................................................................................... 409
4-188. HINLR7 Register .......................................................................................................... 410
4-189. HINLR8 Register .......................................................................................................... 411

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4-190. HINLR9 Register .......................................................................................................... 412

4-191. HIER Register ............................................................................................................. 413
4-192. IEP_TMR_GLB_CFG Register .......................................................................................... 415
4-193. IEP_TMR_GLB_STS Register .......................................................................................... 416
4-194. IEP_TMR_COMPEN Register .......................................................................................... 417
4-195. IEP_TMR_CNT Register ................................................................................................. 418
4-196. IEP_TMR_CAP_CFG Register ......................................................................................... 419
4-197. IEP_TMR_CAP_STS Register .......................................................................................... 421
4-198. IEP_TMR_CAPR0 Register ............................................................................................. 422
4-205. IEP_TMR_CAPF6 Register.............................................................................................. 429
4-207. IEP_TMR_CAPF7 Register.............................................................................................. 431
4-208. IEP_TMR_CMP_CFG Register ......................................................................................... 432
4-209. IEP_TMR_CMP_STS Register ......................................................................................... 433
4-210. IEP_TMR_CMP0 Register ............................................................................................... 434
4-218. IEP_TMR_RXIPG0 Register ............................................................................................ 442
4-219. IEP_TMR_RXIPG1 Register ............................................................................................ 443
4-220. IEP_SYNC_CTRL Register.............................................................................................. 444
4-221. IEP_SYNC_FIRST_STAT Register .................................................................................... 446
4-222. IEP_SYNC0_STAT Register ............................................................................................ 447
4-223. IEP_SYNC1_STAT Register ............................................................................................ 448
4-224. IEP_SYNC_PWIDTH Register .......................................................................................... 449
4-225. IEP_SYNC0_PERIOD Register ......................................................................................... 450
4-226. IEP_SYNC1_DELAY Register .......................................................................................... 451
4-227. IEP_SYNC_START Register ............................................................................................ 452
4-228. IEP_WD_PREDIV Register.............................................................................................. 453
4-229. IEP_PDI_WD_TIM Register ............................................................................................. 454
4-230. IEP_PD_WD_TIM Register .............................................................................................. 455
4-231. IEP_WD_STATUS Register ............................................................................................. 456
4-232. IEP_WD_EXP_CNT Register ........................................................................................... 457
4-233. IEP_WD_CTRL Register................................................................................................. 458
4-234. IEP_DIGIO_CTRL Register ............................................................................................. 459
4-235. IEP_DIGIO_DATA_IN Register ......................................................................................... 460
4-236. IEP_DIGIO_DATA_IN_RAW Register ................................................................................. 461
4-237. IEP_DIGIO_DATA_OUT Register ...................................................................................... 462
4-238. IEP_DIGIO_DATA_OUT_EN Register ................................................................................. 463

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4-239. IEP_DIGIO_EXP Register ............................................................................................... 464

4-240. Receiver Buffer Register (RBR) ........................................................................................ 466
4-241. Transmitter Holding Register (THR) .................................................................................... 467
4-242. Interrupt Enable Register (IER) ......................................................................................... 468
4-243. Interrupt Identification Register (IIR) ................................................................................... 469
4-244. FIFO Control Register (FCR) ............................................................................................ 471
4-245. Line Control Register (LCR) ............................................................................................. 472
4-246. Modem Control Register (MCR) ........................................................................................ 474
4-247. Line Status Register (LSR) .............................................................................................. 475
4-248. Modem Status Register (MSR) ......................................................................................... 478
4-249. Scratch Pad Register (SCR) ............................................................................................ 479
4-250. Divisor LSB Latch (DLL) ................................................................................................. 480
4-251. Divisor MSB Latch (DLH) ................................................................................................ 480
4-252. Revision Identification Register 1 (REVID1) .......................................................................... 481
4-253. Revision Identification Register 2 (REVID2) .......................................................................... 481
4-254. Power and Emulation Management Register (PWREMU_MGMT) ................................................ 482
4-255. Mode Definition Register (MDR) ........................................................................................ 483
4-256. RXCFG0 Register ........................................................................................................ 484
4-257. RXCFG1 Register ........................................................................................................ 486
4-258. TXCFG0 Register ......................................................................................................... 488
4-259. TXCFG1 Register ......................................................................................................... 490
4-260. TXCRC0 Register ......................................................................................................... 492
4-261. TXCRC1 Register ......................................................................................................... 493
4-262. TXIPG0 Register .......................................................................................................... 494
4-263. TXIPG1 Register .......................................................................................................... 495
4-264. PRS0 Register ............................................................................................................ 496
4-265. PRS1 Register ............................................................................................................ 497
4-266. RXFRMS0 Register....................................................................................................... 498
4-267. RXFRMS1 Register....................................................................................................... 499
4-268. RXPCNT0 Register ....................................................................................................... 500
4-269. RXPCNT1 Register ....................................................................................................... 501
4-270. RXERR0 Register ........................................................................................................ 502
4-271. RXERR1 Register ........................................................................................................ 503
4-272. REVID Register ........................................................................................................... 505
4-273. SYSCFG Register ........................................................................................................ 506
4-274. GPCFG0 Register ........................................................................................................ 507
4-275. GPCFG1 Register ........................................................................................................ 509
4-276. CGR Register ............................................................................................................. 511
4-277. ISRP Register ............................................................................................................. 513
4-278. ISP Register ............................................................................................................... 514
4-279. IESP Register ............................................................................................................. 515
4-280. IECP Register ............................................................................................................. 516
4-281. PMAO Register ........................................................................................................... 517
4-282. MII_RT Register........................................................................................................... 518
4-283. IEPCLK Register .......................................................................................................... 519
4-284. SPP Register .............................................................................................................. 520
4-285. PIN_MX Register ......................................................................................................... 521
5-1. SGX Block Diagram ...................................................................................................... 528
6-1. Interrupt Controller Block Diagram ..................................................................................... 531

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6-2. IRQ/FIQ Processing Sequence ......................................................................................... 537

6-3. Nested IRQ/FIQ Processing Sequence ............................................................................... 541
6-4. INTC_REVISION Register ............................................................................................... 552
6-5. INTC_SYSCONFIG Register ............................................................................................ 553
6-6. INTC_SYSSTATUS Register............................................................................................ 554
6-7. INTC_SIR_IRQ Register ................................................................................................. 555
6-8. INTC_SIR_FIQ Register ................................................................................................. 556
6-9. INTC_CONTROL Register .............................................................................................. 557
6-10. INTC_PROTECTION Register .......................................................................................... 558
6-11. INTC_IDLE Register ...................................................................................................... 559
6-12. INTC_IRQ_PRIORITY Register......................................................................................... 560
6-13. INTC_FIQ_PRIORITY Register ......................................................................................... 561
6-14. INTC_THRESHOLD Register ........................................................................................... 562
6-15. INTC_ITR0 Register ...................................................................................................... 563
6-16. INTC_MIR0 Register ..................................................................................................... 564
6-17. INTC_MIR_CLEAR0 Register ........................................................................................... 565
6-18. INTC_MIR_SET0 Register .............................................................................................. 566
6-19. INTC_ISR_SET0 Register ............................................................................................... 567
6-20. INTC_ISR_CLEAR0 Register ........................................................................................... 568
6-21. INTC_PENDING_IRQ0 Register........................................................................................ 569
6-22. INTC_PENDING_FIQ0 Register ........................................................................................ 570
6-47. INTC_ILR_0 to INTC_ILR_127 Register............................................................................... 595
7-1. GPMC Block Diagram .................................................................................................... 599
7-2. GPMC Integration ......................................................................................................... 600
7-3. GPMC to 16-Bit Address/Data-Multiplexed Memory ................................................................. 604

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7-4. GPMC to 16-Bit Non-multiplexed Memory ............................................................................ 605

7-5. GPMC to 8-Bit NAND Device ........................................................................................... 605
7-6. Chip-Select Address Mapping and Decoding Mask .................................................................. 610
7-7. Wait Behavior During an Asynchronous Single Read Access (GPMCFCLKDivider = 1) ....................... 613
7-8. Wait Behavior During a Synchronous Read Burst Access .......................................................... 615
7-9. Read to Read for an Address-Data Multiplexed Device, On Different CS, Without Bus Turnaround (CS0n
Attached to Fast Device)................................................................................................. 617
7-10. Read to Read / Write for an Address-Data Multiplexed Device, On Different CS, With Bus Turnaround .... 617
7-11. Read to Read / Write for a Address-Data or AAD-Multiplexed Device, On Same CS, With Bus
Turnaround ................................................................................................................ 618
7-12. Asynchronous Single Read Operation on an Address/Data Multiplexed Device ................................. 627
7-13. Two Asynchronous Single Read Accesses on an Address/Data Multiplexed Device (32-Bit Read Split
Into 2 × 16-Bit Read) ..................................................................................................... 628
7-14. Asynchronous Single Write on an Address/Data-Multiplexed Device ............................................. 629
7-15. Asynchronous Single-Read on an AAD-Multiplexed Device ........................................................ 630
7-16. Asynchronous Single Write on an AAD-Multiplexed Device ........................................................ 632
7-17. Synchronous Single Read (GPMCFCLKDIVIDER = 0) .............................................................. 634
7-18. Synchronous Single Read (GPMCFCLKDIVIDER = 1) .............................................................. 635
7-19. Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 0) ................................................... 637
7-20. Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 1) ................................................... 638
7-21. Synchronous Single Write on an Address/Data-Multiplexed Device ............................................... 639
7-22. Synchronous Multiple Write (Burst Write) in Address/Data-Multiplexed Mode ................................... 640
7-23. Synchronous Multiple Write (Burst Write) in Address/Address/Data-Multiplexed Mode......................... 641
7-24. Asynchronous Single Read on an Address/Data-Nonmultiplexed Device ........................................ 643
7-25. Asynchronous Single Write on an Address/Data-Nonmultiplexed Device ........................................ 644
7-26. Asynchronous Multiple (Page Mode) Read ........................................................................... 645
7-27. NAND Command Latch Cycle .......................................................................................... 650
7-28. NAND Address Latch Cycle ............................................................................................. 651
7-29. NAND Data Read Cycle ................................................................................................. 652
7-30. NAND Data Write Cycle ................................................................................................. 653
7-31. Hamming Code Accumulation Algorithm (1 of 2) ..................................................................... 657
7-32. Hamming Code Accumulation Algorithm (2 of 2) ..................................................................... 658
7-33. ECC Computation for a 256-Byte Data Stream (Read or Write) ................................................... 658
7-34. ECC Computation for a 512-Byte Data Stream (Read or Write) ................................................... 659
7-35. 128 Word16 ECC Computation ......................................................................................... 660
7-36. 256 Word16 ECC Computation ......................................................................................... 660
7-37. Manual Mode Sequence and Mapping ................................................................................ 665
7-38. NAND Page Mapping and ECC: Per-Sector Schemes .............................................................. 670
7-39. NAND Page Mapping and ECC: Pooled Spare Schemes........................................................... 671
7-40. NAND Page Mapping and ECC: Per-Sector Schemes, with Separate ECC ..................................... 672
7-41. Programming Model Top-Level Diagram .............................................................................. 682
7-42. NOR Interfacing Timing Parameters Diagram ........................................................................ 689
7-43. GPMC Connection to an External NOR Flash Memory ............................................................. 693
7-44. Synchronous Burst Read Access (Timing Parameters in Clock Cycles) .......................................... 695
7-45. Asynchronous Single Read Access (Timing Parameters in Clock Cycles) ....................................... 697
7-46. Asynchronous Single Write Access (Timing Parameters in Clock Cycles) ....................................... 699
7-47. GPMC_REVISION Register ............................................................................................. 707
7-48. GPMC_SYSCONFIG Register .......................................................................................... 708
7-49. GPMC_SYSSTATUS Register .......................................................................................... 709
7-50. GPMC_IRQSTATUS Register .......................................................................................... 710

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7-51. GPMC_IRQENABLE Register .......................................................................................... 711

7-52. GPMC_TIMEOUT_CONTROL Register ............................................................................... 712
7-53. GPMC_ERR_ADDRESS Register...................................................................................... 713
7-54. GPMC_ERR_TYPE Register............................................................................................ 714
7-55. GPMC_CONFIG Register ............................................................................................... 715
7-56. GPMC_STATUS Register ............................................................................................... 716
7-57. GPMC_CONFIG1_0 Register ........................................................................................... 717
7-64. GPMC_NAND_COMMAND_0 Register ............................................................................... 728
7-65. GPMC_NAND_ADDRESS_0 Register ................................................................................. 729
7-66. GPMC_NAND_DATA_0 Register ...................................................................................... 730

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7-127. GPMC_PREFETCH_CONFIG1 Register .............................................................................. 815
7-128. GPMC_PREFETCH_CONFIG2 Register .............................................................................. 817
7-129. GPMC_PREFETCH_CONTROL Register............................................................................. 818
7-130. GPMC_PREFETCH_STATUS Register ............................................................................... 819
7-131. GPMC_ECC_CONFIG Register ........................................................................................ 820
7-132. GPMC_ECC_CONTROL Register ..................................................................................... 822
7-133. GPMC_ECC_SIZE_CONFIG Register ................................................................................. 823
7-134. GPMC_ECC1_RESULT Register ...................................................................................... 825
7-143. GPMC_BCH_RESULT0_0 Register ................................................................................... 843

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7-175. GPMC_BCH_SWDATA Register ....................................................................................... 875

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7-200. OCMC RAM Integration .................................................................................................. 901
7-201. DDR2/3/mDDR Memory Controller Signals ........................................................................... 906
7-202. DDR2/3/mDDR Subsystem Block Diagram ........................................................................... 908
7-203. DDR2/3/mDDR Memory Controller FIFO Block Diagram ........................................................... 909
7-204. EMIF_MOD_ID_REV Register .......................................................................................... 930
7-205. STATUS Register ......................................................................................................... 931
7-206. SDRAM_CONFIG Register .............................................................................................. 932
7-207. SDRAM_CONFIG_2 Register ........................................................................................... 934
7-208. SDRAM_REF_CTRL Register .......................................................................................... 935
7-209. SDRAM_REF_CTRL_SHDW Register ................................................................................ 936
7-210. SDRAM_TIM_1 Register................................................................................................. 937
7-211. SDRAM_TIM_1_SHDW Register ....................................................................................... 938
7-216. PWR_MGMT_CTRL Register ........................................................................................... 943
7-217. PWR_MGMT_CTRL_SHDW Register ................................................................................. 945
7-218. OCP_CONFIG Register.................................................................................................. 946
7-219. OCP_CFG_VAL_1 Register ............................................................................................. 947
7-220. OCP_CFG_VAL_2 Register ............................................................................................. 948
7-221. PERF_CNT_1 Register .................................................................................................. 949
7-222. PERF_CNT_2 Register .................................................................................................. 950
7-223. PERF_CNT_CFG Register .............................................................................................. 951
7-224. PERF_CNT_SEL Register............................................................................................... 952
7-225. PERF_CNT_TIM Register ............................................................................................... 953
7-226. READ_IDLE_CTRL Register ............................................................................................ 954
7-227. READ_IDLE_CTRL_SHDW Register .................................................................................. 955
7-228. IRQSTATUS_RAW_SYS Register ..................................................................................... 956
7-229. IRQSTATUS_SYS Register ............................................................................................. 957
7-230. IRQENABLE_SET_SYS Register ...................................................................................... 958
7-231. IRQENABLE_CLR_SYS Register ...................................................................................... 959
7-232. ZQ_CONFIG Register .................................................................................................... 960
7-233. Read-Write Leveling Ramp Window Register......................................................................... 961
7-234. Read-Write Leveling Ramp Control Register ......................................................................... 962
7-235. Read-Write Leveling Control Register ................................................................................. 963
7-236. DDR_PHY_CTRL_1 Register ........................................................................................... 964
7-237. DDR_PHY_CTRL_1_SHDW Register ................................................................................. 966
7-238. Priority to Class of Service Mapping Register ........................................................................ 968
7-239. Connection ID to Class of Service 1 Mapping Register ............................................................. 969
7-240. Connection ID to Class of Service 2 Mapping Register ............................................................. 970
7-241. Read Write Execution Threshold Register ............................................................................ 971
7-242. DDR PHY Command 0/1/2 Address/Command Slave Ratio Register
(CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0) .................................................................. 974
7-243. DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register
(CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0) ........................................................................ 974
7-244. DDR PHY Command 0/1/2 Invert Clockout Selection Register(
CMD0/1/2_REG_PHY_INVERT_CLKOUT_0) ....................................................................... 975

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7-245. DDR PHY Data Macro 0/1 Read DQS Slave Ratio Register
(DATA0/1_REG_PHY_RD_DQS_SLAVE_RATIO_0))............................................................... 975
7-246. DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0) ...................................................................... 976
7-247. DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_WRLVL_INIT_MODE_0) ..................................................................... 977
7-248. DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0) .................................................................... 977
7-249. DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_GATELVL_INIT_MODE_0) .................................................................. 978
7-250. DDR PHY Data Macro 0/1 DQS Gate Slave Ratio
Register(DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) ..................................................... 978
7-251. DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0) ............................................................. 979
7-252. DDR PHY Data Macro 0/1 Delay Selection Register (DATA0/1_REG_PHY_USE_RANK0_DELAYS) ....... 980
7-253. DDR PHY Data 0/1 DLL Lock Difference Register (DATA0/1_REG_PHY_DLL_LOCK_DIFF_0) ............. 980
7-254. Offset value from DQS to DQ for Data Macro Register (DATA0/DATA1 _REG_PHY_DQ_OFFSET_0) ..... 981
7-255. ELM Integration ........................................................................................................... 983
7-256. ELM_REVISION Register ............................................................................................... 997
7-257. ELM_SYSCONFIG Register ............................................................................................ 998
7-258. ELM_SYSSTATUS Register ............................................................................................ 999
7-259. ELM_IRQSTATUS Register ........................................................................................... 1000
7-260. ELM_IRQENABLE Register ........................................................................................... 1002
7-261. ELM_LOCATION_CONFIG Register ................................................................................. 1003
7-262. ELM_PAGE_CTRL Register ........................................................................................... 1004
7-263. ELM_SYNDROME_FRAGMENT_0_0 Register ..................................................................... 1005

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7-319. ELM_LOCATION_STATUS_0 Register .............................................................................. 1061
7-320. ELM_ERROR_LOCATION_0_0 Register ............................................................................ 1062
7-330. ELM_ERROR_LOCATION_10_0 Register .......................................................................... 1072

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8-1. Functional and Interface Clocks ....................................................................................... 1198
8-2. Generic Clock Domain .................................................................................................. 1203
8-3. Clock Domain State Transitions ....................................................................................... 1203
8-4. Generic Power Domain Architecture.................................................................................. 1205
8-5. High Level System View for RTC-only Mode ........................................................................ 1210
8-6. System Level View of Power Management of Cortex A8 MPU and Cortex M3 ................................ 1213
8-7. IPC Mechanism .......................................................................................................... 1214
8-8. ADPLLS .................................................................................................................. 1218
8-9. Basic Structure of the ADPLLLJ ....................................................................................... 1220
8-10. Effect of the SSC in Frequency ....................................................................................... 1222
8-11. Effect of the SSC in the Time Domain................................................................................ 1223
8-12. Peak Reduction Caused by Spreading ............................................................................... 1223
8-13. Core PLL ................................................................................................................. 1226
8-14. Peripheral PLL Structure ............................................................................................... 1229
8-15. MPU Subsystem PLL Structure ....................................................................................... 1231
8-16. Display PLL Structure................................................................................................... 1232
8-17. DDR PLL Structure...................................................................................................... 1233
8-18. CLKOUT Signals ........................................................................................................ 1234
8-19. Watchdog Timer Clock Selection ..................................................................................... 1234
8-20. Watchdog and Secure Timer Clock Selection (For Secure Devices only) ....................................... 1235
8-21. Timer Clock Selection .................................................................................................. 1236
8-22. RTC, VTP, and Debounce Clock Selection .......................................................................... 1237
8-23. PORz...................................................................................................................... 1239
8-24. External Buffer for nRESETIN_OUT .................................................................................. 1239
8-25. External System Reset ................................................................................................. 1241
8-26. Warm Reset Sequence (External Warm Reset Source) ........................................................... 1242
8-27. Warm Reset Sequence (Internal Warm Reset Source) ............................................................ 1242
8-28. CM_PER_L4LS_CLKSTCTRL Register .............................................................................. 1255
8-29. CM_PER_L3S_CLKSTCTRL Register ............................................................................... 1257
8-30. CM_PER_L3_CLKSTCTRL Register ................................................................................. 1258

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8-31. CM_PER_CPGMAC0_CLKCTRL Register .......................................................................... 1259

8-32. CM_PER_LCDC_CLKCTRL Register ................................................................................ 1260
8-33. CM_PER_USB0_CLKCTRL Register ................................................................................ 1261
8-34. CM_PER_TPTC0_CLKCTRL Register ............................................................................... 1262
8-35. CM_PER_EMIF_CLKCTRL Register ................................................................................. 1263
8-36. CM_PER_OCMCRAM_CLKCTRL Register ......................................................................... 1264
8-37. CM_PER_GPMC_CLKCTRL Register ............................................................................... 1265
8-38. CM_PER_MCASP0_CLKCTRL Register ............................................................................ 1266
8-39. CM_PER_UART5_CLKCTRL Register............................................................................... 1267
8-40. CM_PER_MMC0_CLKCTRL Register ............................................................................... 1268
8-41. CM_PER_ELM_CLKCTRL Register .................................................................................. 1269
8-42. CM_PER_I2C2_CLKCTRL Register .................................................................................. 1270
8-43. CM_PER_I2C1_CLKCTRL Register .................................................................................. 1271
8-44. CM_PER_SPI0_CLKCTRL Register.................................................................................. 1272
8-45. CM_PER_SPI1_CLKCTRL Register.................................................................................. 1273
8-46. CM_PER_L4LS_CLKCTRL Register ................................................................................. 1274
8-47. CM_PER_MCASP1_CLKCTRL Register ............................................................................ 1275
8-52. CM_PER_TIMER7_CLKCTRL Register ............................................................................. 1280
8-56. CM_PER_GPIO1_CLKCTRL Register ............................................................................... 1284
8-59. CM_PER_TPCC_CLKCTRL Register ................................................................................ 1287
8-60. CM_PER_DCAN0_CLKCTRL Register .............................................................................. 1288
8-61. CM_PER_DCAN1_CLKCTRL Register .............................................................................. 1289
8-62. CM_PER_EPWMSS1_CLKCTRL Register .......................................................................... 1290
8-65. CM_PER_L3_INSTR_CLKCTRL Register ........................................................................... 1293
8-66. CM_PER_L3_CLKCTRL Register .................................................................................... 1294
8-67. CM_PER_IEEE5000_CLKCTRL Register ........................................................................... 1295
8-68. CM_PER_PRU_ICSS_CLKCTRL Register .......................................................................... 1296
8-75. CM_PER_SPINLOCK_CLKCTRL Register .......................................................................... 1303
8-76. CM_PER_MAILBOX0_CLKCTRL Register .......................................................................... 1304
8-77. CM_PER_L4HS_CLKSTCTRL Register ............................................................................. 1305
8-78. CM_PER_L4HS_CLKCTRL Register ................................................................................. 1306
8-79. CM_PER_OCPWP_L3_CLKSTCTRL Register ..................................................................... 1307

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8-80. CM_PER_OCPWP_CLKCTRL Register ............................................................................. 1308

8-81. CM_PER_PRU_ICSS_CLKSTCTRL Register ...................................................................... 1309
8-82. CM_PER_CPSW_CLKSTCTRL Register ............................................................................ 1310
8-83. CM_PER_LCDC_CLKSTCTRL Register............................................................................. 1311
8-84. CM_PER_CLKDIV32K_CLKCTRL Register ......................................................................... 1312
8-85. CM_PER_CLK_24MHZ_CLKSTCTRL Register .................................................................... 1313
8-86. CM_WKUP_CLKSTCTRL Register ................................................................................... 1316
8-87. CM_WKUP_CONTROL_CLKCTRL Register ........................................................................ 1318
8-88. CM_WKUP_GPIO0_CLKCTRL Register............................................................................. 1319
8-89. CM_WKUP_L4WKUP_CLKCTRL Register .......................................................................... 1320
8-90. CM_WKUP_TIMER0_CLKCTRL Register ........................................................................... 1321
8-91. CM_WKUP_DEBUGSS_CLKCTRL Register ........................................................................ 1322
8-92. CM_L3_AON_CLKSTCTRL Register ................................................................................. 1324
8-93. CM_AUTOIDLE_DPLL_MPU Register ............................................................................... 1325
8-94. CM_IDLEST_DPLL_MPU Register ................................................................................... 1326
8-95. CM_SSC_DELTAMSTEP_DPLL_MPU Register ................................................................... 1327
8-96. CM-SSC_MODFREQDIV_DPLL_MPU Register .................................................................... 1328
8-97. CM_CLKSEL_DPLL_MPU Register .................................................................................. 1329
8-98. CM_AUTOIDLE_DPLL_DDR Register ............................................................................... 1330
8-99. CM_IDLEST_DPLL_DDR Register ................................................................................... 1331
8-100. CM_SSC_DELTAMSTEP_DPLL_DDR Register.................................................................... 1332
8-101. CM_SSC_MODFREQDIV_DPLL_DDR Register ................................................................... 1333
8-102. CM_CLKSEL_DPLL_DDR Register .................................................................................. 1334
8-103. CM_AUTOIDLE_DPLL_DISP Register ............................................................................... 1335
8-104. CM_IDLEST_DPLL_DISP Register ................................................................................... 1336
8-105. CM_SSC_DELTAMSTEP_DPLL_DISP Register ................................................................... 1337
8-106. CM_SSC_MODFREQDIV_DPLL_DISP Register ................................................................... 1338
8-107. CM_CLKSEL_DPLL_DISP Register .................................................................................. 1339
8-108. CM_AUTOIDLE_DPLL_CORE Register ............................................................................. 1340
8-109. CM_IDLEST_DPLL_CORE Register ................................................................................. 1341
8-110. CM_SSC_DELTAMSTEP_DPLL_CORE Register .................................................................. 1342
8-111. CM_SSC_MODFREQDIV_DPLL_CORE Register ................................................................. 1343
8-112. CM_CLKSEL_DPLL_CORE Register ................................................................................ 1344
8-113. CM_AUTOIDLE_DPLL_PER Register ............................................................................... 1345
8-114. CM_IDLEST_DPLL_PER Register ................................................................................... 1346
8-115. CM_SSC_DELTAMSTEP_DPLL_PER Register .................................................................... 1347
8-116. CM_SSC_MODFREQDIV_DPLL_PER Register.................................................................... 1348
8-117. CM_CLKDCOLDO_DPLL_PER Register ............................................................................ 1349
8-118. CM_DIV_M4_DPLL_CORE Register ................................................................................. 1350
8-120. CM_CLKMODE_DPLL_MPU Register ............................................................................... 1352
8-121. CM_CLKMODE_DPLL_PER Register................................................................................ 1354
8-122. CM_CLKMODE_DPLL_CORE Register ............................................................................. 1355
8-123. CM_CLKMODE_DPLL_DDR Register ............................................................................... 1357
8-124. CM_CLKMODE_DPLL_DISP Register ............................................................................... 1359
8-125. CM_CLKSEL_DPLL_PERIPH Register .............................................................................. 1361
8-126. CM_DIV_M2_DPLL_DDR Register ................................................................................... 1362
8-127. CM_DIV_M2_DPLL_DISP Register .................................................................................. 1363
8-128. CM_DIV_M2_DPLL_MPU Register ................................................................................... 1364

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8-129. CM_DIV_M2_DPLL_PER Register ................................................................................... 1365

8-130. CM_WKUP_WKUP_M3_CLKCTRL Register ....................................................................... 1366
8-131. CM_WKUP_UART0_CLKCTRL Register ............................................................................ 1367
8-132. CM_WKUP_I2C0_CLKCTRL Register ............................................................................... 1368
8-133. CM_WKUP_ADC_TSC_CLKCTRL Register ........................................................................ 1369
8-134. CM_WKUP_SMARTREFLEX0_CLKCTRL Register ............................................................... 1370
8-135. CM_WKUP_TIMER1_CLKCTRL Register ........................................................................... 1371
8-136. CM_WKUP_SMARTREFLEX1_CLKCTRL Register ............................................................... 1372
8-137. CM_L4_WKUP_AON_CLKSTCTRL Register ....................................................................... 1373
8-138. CM_WKUP_WDT1_CLKCTRL Register ............................................................................. 1374
8-140. CLKSEL_TIMER7_CLK Register ..................................................................................... 1377
8-144. CM_MAC_CLKSEL Register .......................................................................................... 1381
8-147. CM_CPTS_RFT_CLKSEL Register .................................................................................. 1384
8-148. CLKSEL_TIMER1MS_CLK Register ................................................................................. 1385
8-149. CLKSEL_GFX_FCLK Register ........................................................................................ 1386
8-150. CLKSEL_PRU_ICSS_OCP_CLK Register .......................................................................... 1387
8-151. CLKSEL_LCDC_PIXEL_CLK Register ............................................................................... 1388
8-152. CLKSEL_WDT1_CLK Register ........................................................................................ 1389
8-153. CLKSEL_GPIO0_DBCLK Register ................................................................................... 1390
8-154. CM_MPU_CLKSTCTRL Register ..................................................................................... 1391
8-155. CM_MPU_MPU_CLKCTRL Register ................................................................................. 1392
8-156. CM_CLKOUT_CTRL Register ......................................................................................... 1394
8-157. CM_RTC_RTC_CLKCTRL Register .................................................................................. 1396
8-158. CM_RTC_CLKSTCTRL Register ..................................................................................... 1397
8-159. CM_GFX_L3_CLKSTCTRL Register ................................................................................. 1399
8-160. CM_GFX_GFX_CLKCTRL Register .................................................................................. 1400
8-161. CM_GFX_L4LS_GFX_CLKSTCTRL Register....................................................................... 1401
8-162. CM_GFX_MMUCFG_CLKCTRL Register ........................................................................... 1402
8-163. CM_GFX_MMUDATA_CLKCTRL Register .......................................................................... 1403
8-164. CM_CEFUSE_CLKSTCTRL Register ................................................................................ 1405
8-165. CM_CEFUSE_CEFUSE_CLKCTRL Register ....................................................................... 1406
8-166. REVISION_PRM Register.............................................................................................. 1408
8-167. PRM_IRQSTATUS_MPU Register ................................................................................... 1409
8-168. PRM_IRQENABLE_MPU Register ................................................................................... 1410
8-169. PRM_IRQSTATUS_M3 Register ...................................................................................... 1411
8-170. PRM_IRQENABLE_M3 Register ...................................................................................... 1412
8-171. RM_PER_RSTCTRL Register ......................................................................................... 1414
8-172. PM_PER_PWRSTST Register ........................................................................................ 1415
8-173. PM_PER_PWRSTCTRL Register..................................................................................... 1417
8-174. RM_WKUP_RSTCTRL Register ...................................................................................... 1419
8-175. PM_WKUP_PWRSTCTRL Register .................................................................................. 1420
8-176. PM_WKUP_PWRSTST Register...................................................................................... 1421
8-177. RM_WKUP_RSTST Register .......................................................................................... 1422

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8-178. PM_MPU_PWRSTCTRL Register .................................................................................... 1424

8-179. PM_MPU_PWRSTST Register ........................................................................................ 1426
8-180. RM_MPU_RSTST Register ............................................................................................ 1427
8-181. PRM_RSTCTRL Register .............................................................................................. 1429
8-182. PRM_RSTTIME Register............................................................................................... 1430
8-183. PRM_RSTST Register.................................................................................................. 1431
8-184. PRM_SRAM_COUNT Register........................................................................................ 1432
8-185. PRM_LDO_SRAM_CORE_SETUP Register ........................................................................ 1433
8-186. PRM_LDO_SRAM_CORE_CTRL Register .......................................................................... 1435
8-187. PRM_LDO_SRAM_MPU_SETUP Register.......................................................................... 1436
8-188. PRM_LDO_SRAM_MPU_CTRL Register............................................................................ 1438
8-189. PM_RTC_PWRSTCTRL Register..................................................................................... 1439
8-190. PM_RTC_PWRSTST Register ........................................................................................ 1440
8-191. PM_GFX_PWRSTCTRL Register..................................................................................... 1442
8-192. RM_GFX_RSTCTRL Register ......................................................................................... 1443
8-193. PM_GFX_PWRSTST Register ........................................................................................ 1444
8-194. RM_GFX_RSTST Register ............................................................................................ 1445
8-195. PM_CEFUSE_PWRSTCTRL Register ............................................................................... 1446
8-196. PM_CEFUSE_PWRSTST Register ................................................................................... 1447
9-1. USB Charger Detection ................................................................................................ 1453
9-2. control_revision Register ............................................................................................... 1463
9-3. control_hwinfo Register................................................................................................. 1464
9-4. control_sysconfig Register ............................................................................................. 1465
9-5. control_status Register ................................................................................................. 1466
9-6. control_emif_sdram_config Register.................................................................................. 1467
9-7. core_sldo_ctrl Register ................................................................................................. 1469
9-8. mpu_sldo_ctrl Register ................................................................................................. 1470
9-9. clk32kdivratio_ctrl Register ............................................................................................ 1471
9-10. bandgap_ctrl Register .................................................................................................. 1472
9-11. bandgap_trim Register ................................................................................................. 1473
9-12. pll_clkinpulow_ctrl Register ............................................................................................ 1474
9-13. mosc_ctrl Register ...................................................................................................... 1475
9-14. deepsleep_ctrl Register ................................................................................................ 1476
9-15. dpll_pwr_sw_status Register .......................................................................................... 1477
9-16. device_id Register....................................................................................................... 1478
9-17. dev_feature Register .................................................................................................... 1479
9-18. init_priority_0 Register .................................................................................................. 1480
9-19. init_priority_1 Register .................................................................................................. 1481
9-20. tptc_cfg Register ........................................................................................................ 1482
9-21. usb_ctrl0 Register ....................................................................................................... 1483
9-22. usb_sts0 Register ....................................................................................................... 1485
9-23. usb_ctrl1 Register ....................................................................................................... 1486
9-24. usb_sts1 Register ....................................................................................................... 1488
9-25. mac_id0_lo Register .................................................................................................... 1489
9-26. mac_id0_hi Register .................................................................................................... 1490
9-27. mac_id1_lo Register .................................................................................................... 1491
9-28. mac_id1_hi Register .................................................................................................... 1492
9-29. dcan_raminit Register .................................................................................................. 1493
9-30. usb_wkup_ctrl Register ................................................................................................. 1494

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9-31. gmii_sel Register ........................................................................................................ 1495

9-32. pwmss_ctrl Register .................................................................................................... 1496
9-33. mreqprio_0 Register .................................................................................................... 1497
9-34. mreqprio_1 Register .................................................................................................... 1498
9-35. hw_event_sel_grp1 Register........................................................................................... 1499
9-39. smrt_ctrl Register........................................................................................................ 1503
9-40. mpuss_hw_debug_sel Register ....................................................................................... 1504
9-41. mpuss_hw_dbg_info Register ......................................................................................... 1505
9-42. vdd_mpu_opp_050 Register ........................................................................................... 1506
9-45. vdd_mpu_opp_turbo Register ......................................................................................... 1509
9-46. vdd_core_opp_050 Register ........................................................................................... 1510
9-47. vdd_core_opp_100 Register ........................................................................................... 1511
9-48. bb_scale Register ....................................................................................................... 1512
9-49. usb_vid_pid Register.................................................................................................... 1513
9-50. efuse_sma Register ..................................................................................................... 1514
9-51. conf_<module>_<pin> Register ....................................................................................... 1515
9-52. cqdetect_status Register ............................................................................................... 1516
9-53. ddr_io_ctrl Register ..................................................................................................... 1517
9-54. vtp_ctrl Register ......................................................................................................... 1518
9-55. vref_ctrl Register ........................................................................................................ 1519
9-56. tpcc_evt_mux_0_3 Register ........................................................................................... 1520
9-57. tpcc_evt_mux_4_7 Register ........................................................................................... 1521
9-58. tpcc_evt_mux_8_11 Register .......................................................................................... 1522
9-59. tpcc_evt_mux_12_15 Register ........................................................................................ 1523
9-72. timer_evt_capt Register ................................................................................................ 1536
9-73. ecap_evt_capt Register ................................................................................................ 1537
9-74. adc_evt_capt Register .................................................................................................. 1538
9-75. reset_iso Register ....................................................................................................... 1539
9-76. dpll_pwr_sw_ctrl Register .............................................................................................. 1540
9-77. ddr_cke_ctrl Register ................................................................................................... 1542
9-78. sma2 Register ........................................................................................................... 1543
9-79. m3_txev_eoi Register ................................................................................................... 1544

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9-80. ipc_msg_reg0 Register ................................................................................................. 1545

9-88. ddr_cmd0_ioctrl Register ............................................................................................... 1553
9-91. ddr_data0_ioctrl Register............................................................................................... 1557
9-92. ddr_data1_ioctrl Register............................................................................................... 1559
10-1. L3 Topology .............................................................................................................. 1563
10-2. L4 Topology .............................................................................................................. 1565
11-1. EDMA3 Controller Block Diagram..................................................................................... 1567
11-2. EDMA3 Channel Controller (EDMA3CC) Block Diagram .......................................................... 1575
11-3. EDMA3 Transfer Controller (EDMA3TC) Block Diagram .......................................................... 1576
11-4. Definition of ACNT, BCNT, and CCNT .............................................................................. 1577
11-5. A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3).................................................... 1578
11-6. AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) .................................................. 1579
11-7. PaRAM Set ............................................................................................................... 1581
11-8. Channel Options Parameter (OPT) ................................................................................... 1583
11-9. Linked Transfer .......................................................................................................... 1590
11-10. Link-to-Self Transfer .................................................................................................... 1591
11-11. DMA Channel and QDMA Channel to PaRAM Mapping........................................................... 1596
11-12. QDMA Channel to PaRAM Mapping ................................................................................. 1597
11-13. Shadow Region Registers ............................................................................................. 1598
11-14. Interrupt Diagram ........................................................................................................ 1603
11-15. Error Interrupt Operation ............................................................................................... 1606
11-16. PaRAM Set Content for Proxy Memory Protection Example ...................................................... 1610
11-17. Channel Options Parameter (OPT) Example ........................................................................ 1610
11-18. Proxy Memory Protection Example ................................................................................... 1611
11-19. EDMA3 Prioritization .................................................................................................... 1618
11-20. Block Move Example ................................................................................................... 1619
11-21. Block Move Example PaRAM Configuration......................................................................... 1619
11-22. Subframe Extraction Example ......................................................................................... 1620
11-23. Subframe Extraction Example PaRAM Configuration .............................................................. 1620
11-24. Data Sorting Example .................................................................................................. 1621
11-25. Data Sorting Example PaRAM Configuration ....................................................................... 1622
11-26. Servicing Incoming McASP Data Example .......................................................................... 1623
11-27. Servicing Incoming McASP Data Example PaRAM Configuration ............................................... 1623
11-28. Servicing Peripheral Burst Example .................................................................................. 1624
11-29. Servicing Peripheral Burst Example PaRAM Configuration ....................................................... 1625
11-30. Servicing Continuous McASP Data Example ........................................................................ 1626
11-31. Servicing Continuous McASP Data Example PaRAM Configuration ............................................. 1627
11-32. Servicing Continuous McASP Data Example Reload PaRAM Configuration ................................... 1627
11-33. Ping-Pong Buffering for McASP Data Example .................................................................... 1630
11-34. Ping-Pong Buffering for McASP Example PaRAM Configuration................................................. 1630

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11-35. Ping-Pong Buffering for McASP Example Pong PaRAM Configuration ......................................... 1631
11-36. Ping-Pong Buffering for McASP Example Ping PaRAM Configuration .......................................... 1632
11-37. Intermediate Transfer Completion Chaining Example .............................................................. 1633
11-38. Single Large Block Transfer Example ................................................................................ 1634
11-39. Smaller Packet Data Transfers Example............................................................................. 1634
11-40. PID Register ............................................................................................................. 1641
11-41. CCCFG Register ........................................................................................................ 1642
11-42. SYSCONFIG Register .................................................................................................. 1644
11-43. DCHMAP_0 to DCHMAP_63 Register ............................................................................... 1645
11-44. QCHMAP_0 to QCHMAP_7 Register ................................................................................ 1646
11-45. DMAQNUM_0 to DMAQNUM_7 Register............................................................................ 1647
11-46. QDMAQNUM Register.................................................................................................. 1652
11-47. QUEPRI Register........................................................................................................ 1655
11-48. EMR Register ............................................................................................................ 1656
11-49. EMRH Register .......................................................................................................... 1657
11-50. EMCR Register .......................................................................................................... 1658
11-51. EMCRH Register ........................................................................................................ 1659
11-52. QEMR Register .......................................................................................................... 1660
11-53. QEMCR Register ........................................................................................................ 1661
11-54. CCERR Register ........................................................................................................ 1662
11-55. CCERRCLR Register ................................................................................................... 1663
11-56. EEVAL Register ......................................................................................................... 1664
11-57. DRAE0 Register ......................................................................................................... 1665
11-58. DRAEH0 Register ....................................................................................................... 1666
11-59. DRAE1 Register ......................................................................................................... 1667
11-60. DRAEH1 Register ....................................................................................................... 1668
11-61. DRAE2 Register ......................................................................................................... 1669
11-62. DRAEH2 Register ....................................................................................................... 1670
11-63. DRAE3 Register ......................................................................................................... 1671
11-64. DRAEH3 Register ....................................................................................................... 1672
11-65. DRAE4 Register ......................................................................................................... 1673
11-66. DRAEH4 Register ....................................................................................................... 1674
11-67. DRAE5 Register ......................................................................................................... 1675
11-68. DRAEH5 Register ....................................................................................................... 1676
11-69. DRAE6 Register ......................................................................................................... 1677
11-70. DRAEH6 Register ....................................................................................................... 1678
11-71. DRAE7 Register ......................................................................................................... 1679
11-72. DRAEH7 Register ....................................................................................................... 1680
11-73. QRAE_0 to QRAE_7 Register ......................................................................................... 1681
11-74. Q0E0 Register ........................................................................................................... 1682
11-75. Q0E1 Register ........................................................................................................... 1683
11-76. Q0E2 Register ........................................................................................................... 1684
11-77. Q0E3 Register ........................................................................................................... 1685
11-78. Q0E4 Register ........................................................................................................... 1686
11-79. Q0E5 Register ........................................................................................................... 1687
11-80. Q0E6 Register ........................................................................................................... 1688
11-81. Q0E7 Register ........................................................................................................... 1689
11-82. Q0E8 Register ........................................................................................................... 1690
11-83. Q0E9 Register ........................................................................................................... 1691

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11-84. Q0E10 Register.......................................................................................................... 1692

11-85. Q0E11 Register.......................................................................................................... 1693
11-86. Q0E12 Register.......................................................................................................... 1694
11-87. Q0E13 Register.......................................................................................................... 1695
11-88. Q0E14 Register.......................................................................................................... 1696
11-89. Q0E15 Register.......................................................................................................... 1697
11-90. Q1E0 Register ........................................................................................................... 1698
11-91. Q1E1 Register ........................................................................................................... 1699
11-92. Q1E2 Register ........................................................................................................... 1700
11-93. Q1E3 Register ........................................................................................................... 1701
11-94. Q1E4 Register ........................................................................................................... 1702
11-95. Q1E5 Register ........................................................................................................... 1703
11-96. Q1E6 Register ........................................................................................................... 1704
11-97. Q1E7 Register ........................................................................................................... 1705
11-98. Q1E8 Register ........................................................................................................... 1706
11-99. Q1E9 Register ........................................................................................................... 1707
11-100. Q1E10 Register ........................................................................................................ 1708
11-101. Q1E11 Register ........................................................................................................ 1709
11-102. Q1E12 Register ........................................................................................................ 1710
11-103. Q1E13 Register ........................................................................................................ 1711
11-104. Q1E14 Register ........................................................................................................ 1712
11-105. Q1E15 Register ........................................................................................................ 1713
11-106. Q2E0 Register .......................................................................................................... 1714
11-107. Q2E1 Register .......................................................................................................... 1715
11-108. Q2E2 Register .......................................................................................................... 1716
11-109. Q2E3 Register .......................................................................................................... 1717
11-110. Q2E4 Register .......................................................................................................... 1718
11-111. Q2E5 Register .......................................................................................................... 1719
11-112. Q2E6 Register .......................................................................................................... 1720
11-113. Q2E7 Register .......................................................................................................... 1721
11-114. Q2E8 Register .......................................................................................................... 1722
11-115. Q2E9 Register .......................................................................................................... 1723
11-116. Q2E10 Register ........................................................................................................ 1724
11-117. Q2E11 Register ........................................................................................................ 1725
11-118. Q2E12 Register ........................................................................................................ 1726
11-119. Q2E13 Register ........................................................................................................ 1727
11-120. Q2E14 Register ........................................................................................................ 1728
11-121. Q2E15 Register ........................................................................................................ 1729
11-122. QSTAT_0 to QSTAT_2 Register ..................................................................................... 1730
11-123. QWMTHRA Register .................................................................................................. 1731
11-124. CCSTAT Register ...................................................................................................... 1732
11-125. MPFAR Register ....................................................................................................... 1734
11-126. MPFSR Register ....................................................................................................... 1735
11-127. MPFCR Register ....................................................................................................... 1736
11-128. MPPAG Register ....................................................................................................... 1737
11-129. MPPA_0 to MPPA_7 Register ....................................................................................... 1738
11-130. ER Register ............................................................................................................. 1739
11-131. ERH Register ........................................................................................................... 1740
11-132. ECR Register ........................................................................................................... 1741

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11-133. ECRH Register ......................................................................................................... 1742

11-134. ESR Register ........................................................................................................... 1743
11-135. ESRH Register ......................................................................................................... 1744
11-136. CER Register ........................................................................................................... 1745
11-137. CERH Register ......................................................................................................... 1746
11-138. EER Register ........................................................................................................... 1747
11-139. EERH Register ......................................................................................................... 1748
11-140. EECR Register ......................................................................................................... 1749
11-141. EECRH Register ....................................................................................................... 1750
11-142. EESR Register ......................................................................................................... 1751
11-143. EESRH Register ....................................................................................................... 1752
11-144. SER Register ........................................................................................................... 1753
11-145. SERH Register ......................................................................................................... 1754
11-146. SECR Register ......................................................................................................... 1755
11-147. SECRH Register ....................................................................................................... 1756
11-148. IER Register ............................................................................................................ 1757
11-149. IERH Register .......................................................................................................... 1758
11-150. IECR Register .......................................................................................................... 1759
11-151. IECRH Register ........................................................................................................ 1760
11-152. IESR Register .......................................................................................................... 1761
11-153. IESRH Register ........................................................................................................ 1762
11-154. IPR Register ............................................................................................................ 1763
11-155. IPRH Register .......................................................................................................... 1764
11-156. ICR Register ............................................................................................................ 1765
11-157. ICRH Register .......................................................................................................... 1766
11-158. IEVAL Register ......................................................................................................... 1767
11-159. QER Register ........................................................................................................... 1768
11-160. QEER Register ......................................................................................................... 1769
11-161. QEECR Register ....................................................................................................... 1770
11-162. QEESR Register ....................................................................................................... 1771
11-163. QSER Register ......................................................................................................... 1772
11-164. QSECR Register ....................................................................................................... 1773
11-165. PID Register ............................................................................................................ 1775
11-166. TCCFG Register ....................................................................................................... 1776
11-167. SYSCONFIG Register ................................................................................................. 1777
11-168. TCSTAT Register ...................................................................................................... 1778
11-169. ERRSTAT Register .................................................................................................... 1780
11-170. ERREN Register ....................................................................................................... 1781
11-171. ERRCLR Register ..................................................................................................... 1782
11-172. ERRDET Register ..................................................................................................... 1783
11-173. ERRCMD Register ..................................................................................................... 1784
11-174. RDRATE Register ..................................................................................................... 1785
11-175. SAOPT Register ....................................................................................................... 1786
11-176. SASRC Register ....................................................................................................... 1788
11-177. SACNT Register ....................................................................................................... 1789
11-178. SADST Register........................................................................................................ 1790
11-179. SABIDX Register ....................................................................................................... 1791
11-180. SAMPPRXY Register.................................................................................................. 1792
11-181. SACNTRLD Register .................................................................................................. 1793

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11-182. SASRCBREF Register ................................................................................................ 1794

11-183. SADSTBREF Register ................................................................................................ 1795
11-184. DFCNTRLD Register .................................................................................................. 1796
11-185. DFSRCBREF Register ................................................................................................ 1797
11-186. DFDSTBREF Register ................................................................................................ 1798
11-187. DFOPT0 Register ...................................................................................................... 1799
11-188. DFSRC0 Register ...................................................................................................... 1801
11-189. DFCNT0 Register ...................................................................................................... 1802
11-190. DFDST0 Register ...................................................................................................... 1803
11-191. DFBIDX0 Register ..................................................................................................... 1804
11-192. DFMPPRXY0 Register ................................................................................................ 1805
11-193. DFOPT1 Register ...................................................................................................... 1806
11-194. DFSRC1 Register ...................................................................................................... 1808
11-195. DFCNT1 Register ...................................................................................................... 1809
11-196. DFDST1 Register ...................................................................................................... 1810
11-197. DFBIDX1 Register ..................................................................................................... 1811
11-199. DFOPT2 Register ...................................................................................................... 1813
11-200. DFSRC2 Register ...................................................................................................... 1815
11-201. DFCNT2 Register ...................................................................................................... 1816
11-202. DFDST2 Register ...................................................................................................... 1817
11-203. DFBIDX2 Register ..................................................................................................... 1818
11-205. DFOPT3 Register ...................................................................................................... 1820
11-206. DFSRC3 Register ...................................................................................................... 1822
11-207. DFCNT3 Register ...................................................................................................... 1823
11-208. DFDST3 Register ...................................................................................................... 1824
11-209. DFBIDX3 Register ..................................................................................................... 1825
12-1. TSC_ADC Integration ................................................................................................... 1833
12-2. Functional Block Diagram .............................................................................................. 1837
12-3. Sequencer FSM ......................................................................................................... 1840
12-4. Example Timing Diagram for Sequencer............................................................................. 1841
12-5. REVISION Register ..................................................................................................... 1844
12-7. IRQSTATUS_RAW Register ........................................................................................... 1846
12-8. IRQSTATUS Register .................................................................................................. 1848
12-9. IRQENABLE_SET Register ............................................................................................ 1850
12-10. IRQENABLE_CLR Register............................................................................................ 1852
12-11. IRQWAKEUP Register ................................................................................................. 1854
12-12. DMAENABLE_SET Register........................................................................................... 1855
12-13. DMAENABLE_CLR Register .......................................................................................... 1856
12-14. CTRL Register ........................................................................................................... 1857
12-15. ADCSTAT Register ..................................................................................................... 1858
12-16. ADCRANGE Register ................................................................................................... 1859
12-17. ADC_CLKDIV Register ................................................................................................. 1860
12-18. ADC_MISC Register .................................................................................................... 1861
12-19. STEPENABLE Register ................................................................................................ 1862
12-20. IDLECONFIG Register ................................................................................................. 1863

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12-21. TS_CHARGE_STEPCONFIG Register .............................................................................. 1865

12-22. TS_CHARGE_DELAY Register ....................................................................................... 1867
12-23. STEPCONFIG1 Register ............................................................................................... 1868
12-24. STEPDELAY1 Register................................................................................................. 1870
12-41. STEPCONFIG10 Register ............................................................................................. 1895
12-42. STEPDELAY10 Register ............................................................................................... 1897
12-55. FIFO0COUNT Register ................................................................................................. 1916
12-56. FIFO0THRESHOLD Register .......................................................................................... 1917
12-57. DMA0REQ Register..................................................................................................... 1918
12-58. FIFO1COUNT Register ................................................................................................. 1919
12-59. FIFO1THRESHOLD Register .......................................................................................... 1920
12-60. DMA1REQ Register..................................................................................................... 1921
12-61. FIFO0DATA Register ................................................................................................... 1922
12-62. FIFO1DATA Register ................................................................................................... 1923
13-1. LCD Controller ........................................................................................................... 1925
13-2. LCD Controller Integration ............................................................................................. 1927
13-3. Input and Output Clocks ................................................................................................ 1929
13-4. LIDD Mode HD44780 Write Timing Diagram ........................................................................ 1935
13-5. LIDD Mode HD44780 Read Timing Diagram ........................................................................ 1935
13-6. LIDD Mode 6800 Write Timing Diagram ............................................................................. 1936
13-7. LIDD Mode 6800 Read Timing Diagram ............................................................................. 1937

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13-8. LIDD Mode 6800 Status Timing Diagram ............................................................................ 1937

13-9. LIDD Mode 8080 Write Timing Diagram ............................................................................. 1937
13-10. LIDD Mode 8080 Read Timing Diagram ............................................................................. 1938
13-11. LIDD Mode 8080 Status Timing Diagram ............................................................................ 1938
13-12. Logical Data Path for Raster Controller .............................................................................. 1940
13-13. Frame Buffer Structure ................................................................................................. 1941
13-14. 16-Entry Palette/Buffer Format (1, 2, 4, 12, 16 BPP)............................................................... 1943
13-15. 256-Entry Palette/Buffer Format (8 BPP) ............................................................................ 1944
13-16. 16-BPP Data Memory Organization (TFT Mode Only)—Little Endian ........................................... 1944
13-17. 12-BPP Data Memory Organization—Little Endian ................................................................. 1945
13-18. 8-BPP Data Memory Organization ................................................................................... 1945
13-19. 4-BPP Data Memory Organization .................................................................................... 1945
13-22. Monochrome and Color Output........................................................................................ 1948
13-23. Example of Subpicture.................................................................................................. 1949
13-24. Subpicture HOLS Bit .................................................................................................... 1949
13-25. Raster Mode Display Format .......................................................................................... 1950
13-26. Raster Mode Passive (STN) Timing Diagram ....................................................................... 1951
13-27. Raster Mode Active (TFT) Timing Diagram .......................................................................... 1952
13-28. Palette Lookup Examples .............................................................................................. 1960
13-29. PID Register ............................................................................................................. 1964
13-30. CTRL Register ........................................................................................................... 1965
13-31. LIDD_CTRL Register ................................................................................................... 1966
13-32. LIDD_CS0_CONF Register ............................................................................................ 1968
13-33. LIDD_CS0_ADDR Register ............................................................................................ 1969
13-34. LIDD_CS0_DATA Register ............................................................................................ 1970
13-35. LIDD_CS1_CONF Register ............................................................................................ 1971
13-36. LIDD_CS1_ADDR Register ............................................................................................ 1972
13-37. LIDD_CS1_DATA Register ............................................................................................ 1973
13-38. RASTER_CTRL Register .............................................................................................. 1974
13-39. RASTER_TIMING_0 Register ......................................................................................... 1977
13-42. RASTER_SUBPANEL Register ....................................................................................... 1981
13-43. RASTER_SUBPANEL2 Register...................................................................................... 1982
13-44. LCDDMA_CTRL Register .............................................................................................. 1983
13-45. LCDDMA_FB0_BASE Register ....................................................................................... 1985
13-46. LCDDMA_FB0_CEILING Register .................................................................................... 1986
13-47. LCDDMA_FB1_BASE Register ....................................................................................... 1987
13-48. LCDDMA_FB1_CEILING Register .................................................................................... 1988
13-53. IRQENABLE_CLEAR Register ........................................................................................ 1996
13-54. CLKC_ENABLE Register............................................................................................... 1998
13-55. CLKC_RESET Register ................................................................................................ 1999
14-1. Ethernet Switch Integration ............................................................................................ 2003

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14-2. Ethernet Switch RMII Clock Detail .................................................................................... 2007

14-3. MII Interface Connections .............................................................................................. 2008
14-4. RMII Interface Connections ............................................................................................ 2010
14-5. RGMII Interface Connections .......................................................................................... 2011
14-6. CPSW_3G Block Diagram ............................................................................................. 2019
14-7. Tx Buffer Descriptor Format ........................................................................................... 2024
14-8. Rx Buffer Descriptor Format ........................................................................................... 2027
14-9. VLAN Header Encapsulation Word ................................................................................... 2031
14-10. CPTS Block Diagram ................................................................................................... 2065
14-11. Event FIFO Misalignment Condition .................................................................................. 2067
14-12. HW1/4_TSP_PUSH Connection ...................................................................................... 2068
14-13. Port TX State RAM Entry............................................................................................... 2074
14-14. Port RX DMA State ..................................................................................................... 2075
14-15. IDVER Register .......................................................................................................... 2079
14-16. CONTROL Register ..................................................................................................... 2080
14-17. PRESCALE Register.................................................................................................... 2082
14-18. UNKNOWN_VLAN Register ........................................................................................... 2083
14-19. TBLCTL Register ........................................................................................................ 2084
14-20. TBLW2 Register ......................................................................................................... 2085
14-21. TBLW1 Register ......................................................................................................... 2086
14-22. TBLW0 Register ......................................................................................................... 2087
14-23. PORTCTL0 Register .................................................................................................... 2088
14-29. TX_IDVER Register ..................................................................................................... 2096
14-30. TX_CONTROL Register ................................................................................................ 2097
14-31. TX_TEARDOWN Register ............................................................................................. 2098
14-32. RX_IDVER Register .................................................................................................... 2099
14-33. RX_CONTROL Register ............................................................................................... 2100
14-34. RX_TEARDOWN Register ............................................................................................. 2101
14-35. CPDMA_SOFT_RESET Register ..................................................................................... 2102
14-36. DMACONTROL Register ............................................................................................... 2103
14-37. DMASTATUS Register ................................................................................................. 2105
14-38. RX_BUFFER_OFFSET Register ...................................................................................... 2107
14-39. EMCONTROL Register ................................................................................................. 2108
14-40. TX_PRI0_RATE Register .............................................................................................. 2109
14-48. TX_INTSTAT_RAW Register .......................................................................................... 2117
14-49. TX_INTSTAT_MASKED Register ..................................................................................... 2118
14-50. TX_INTMASK_SET Register .......................................................................................... 2119

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14-51. TX_INTMASK_CLEAR Register ...................................................................................... 2120

14-52. CPDMA_IN_VECTOR Register ....................................................................................... 2121
14-53. CPDMA_EOI_VECTOR Register ..................................................................................... 2122
14-54. RX_INTSTAT_RAW Register .......................................................................................... 2123
14-55. RX_INTSTAT_MASKED Register..................................................................................... 2124
14-56. RX_INTMASK_SET Register .......................................................................................... 2125
14-57. RX_INTMASK_CLEAR Register ...................................................................................... 2127
14-58. DMA_INTSTAT_RAW Register ....................................................................................... 2129
14-59. DMA_INTSTAT_MASKED Register .................................................................................. 2130
14-60. DMA_INTMASK_SET Register ........................................................................................ 2131
14-61. DMA_INTMASK_CLEAR Register .................................................................................... 2132
14-62. RX0_PENDTHRESH Register......................................................................................... 2133
14-70. RX0_FREEBUFFER Register ......................................................................................... 2141
14-78. CPTS_IDVER Register ................................................................................................. 2150
14-79. CPTS_CONTROL Register ............................................................................................ 2151
14-80. CPTS_TS_PUSH Register ............................................................................................. 2152
14-81. CPTS_TS_LOAD_VAL Register ...................................................................................... 2153
14-82. CPTS_TS_LOAD_EN Register ........................................................................................ 2154
14-83. CPTS_INTSTAT_RAW Register ...................................................................................... 2155
14-84. CPTS_INTSTAT_MASKED Register ................................................................................. 2156
14-85. CPTS_INT_ENABLE Register ......................................................................................... 2157
14-86. CPTS_EVENT_POP Register ......................................................................................... 2158
14-87. CPTS_EVENT_LOW Register......................................................................................... 2159
14-88. CPTS_EVENT_HIGH Register ........................................................................................ 2160
14-89. TX0_HDP Register ...................................................................................................... 2164
14-90. TX1_HDP Register ...................................................................................................... 2165
14-91. TX2_HDP Register ...................................................................................................... 2166
14-92. TX3_HDP Register ...................................................................................................... 2167
14-93. TX4_HDP Register ...................................................................................................... 2168
14-94. TX5_HDP Register ...................................................................................................... 2169
14-95. TX6_HDP Register ...................................................................................................... 2170
14-96. TX7_HDP Register ...................................................................................................... 2171
14-97. RX0_HDP Register ..................................................................................................... 2172
14-98. RX1_HDP Register ..................................................................................................... 2173
14-99. RX2_HDP Register ..................................................................................................... 2174

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14-100. RX3_HDP Register .................................................................................................... 2175

14-101. RX4_HDP Register .................................................................................................... 2176
14-102. RX5_HDP Register .................................................................................................... 2177
14-103. RX6_HDP Register .................................................................................................... 2178
14-104. RX7_HDP Register .................................................................................................... 2179
14-105. TX0_CP Register ...................................................................................................... 2180
14-106. TX1_CP Register ...................................................................................................... 2181
14-107. TX2_CP Register ...................................................................................................... 2182
14-108. TX3_CP Register ...................................................................................................... 2183
14-109. TX4_CP Register ...................................................................................................... 2184
14-110. TX5_CP Register ...................................................................................................... 2185
14-111. TX6_CP Register ...................................................................................................... 2186
14-112. TX7_CP Register ...................................................................................................... 2187
14-113. RX0_CP Register ...................................................................................................... 2188
14-114. RX1_CP Register ...................................................................................................... 2189
14-115. RX2_CP Register ...................................................................................................... 2190
14-116. RX3_CP Register ...................................................................................................... 2191
14-117. RX4_CP Register ...................................................................................................... 2192
14-118. RX5_CP Register ...................................................................................................... 2193
14-119. RX6_CP Register ...................................................................................................... 2194
14-120. RX7_CP Register ...................................................................................................... 2195
14-121. P0_CONTROL Register............................................................................................... 2197
14-122. P0_MAX_BLKS Register ............................................................................................. 2198
14-123. P0_BLK_CNT Register ................................................................................................ 2199
14-124. P0_TX_IN_CTL Register ............................................................................................. 2200
14-125. P0_PORT_VLAN Register ............................................................................................ 2201
14-126. P0_TX_PRI_MAP Register ........................................................................................... 2202
14-127. P0_CPDMA_TX_PRI_MAP Register ................................................................................ 2203
14-128. P0_CPDMA_RX_CH_MAP Register ................................................................................ 2204
14-129. P0_RX_DSCP_PRI_MAP0 Register ................................................................................ 2205
14-143. P1_TS_SEQ_MTYPE Register ...................................................................................... 2220
14-144. P1_SA_LO Register ................................................................................................... 2221
14-145. P1_SA_HI Register .................................................................................................... 2222
14-146. P1_SEND_PERCENT Register ...................................................................................... 2223

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14-161. P2_TS_SEQ_MTYPE Register ...................................................................................... 2239
14-162. P2_SA_LO Register ................................................................................................... 2240
14-163. P2_SA_HI Register .................................................................................................... 2241
14-164. P2_SEND_PERCENT Register ...................................................................................... 2242
14-173. IDVER Register ........................................................................................................ 2252
14-174. MACCONTROL Register ............................................................................................. 2253
14-175. MACSTATUS Register ................................................................................................ 2256
14-176. SOFT_RESET Register ............................................................................................... 2257
14-177. RX_MAXLEN Register ................................................................................................ 2258
14-178. BOFFTEST Register .................................................................................................. 2259
14-179. RX_PAUSE Register .................................................................................................. 2260
14-180. TX_PAUSE Register .................................................................................................. 2261
14-181. EMCONTROL Register ............................................................................................... 2262
14-182. RX_PRI_MAP Register ............................................................................................... 2263
14-183. TX_GAP Register ...................................................................................................... 2264
14-184. ID_VER Register ....................................................................................................... 2265
14-185. CONTROL Register ................................................................................................... 2266
14-187. STAT_PORT_EN Register ........................................................................................... 2268
14-188. PTYPE Register ........................................................................................................ 2269
14-189. SOFT_IDLE Register .................................................................................................. 2270
14-190. THRU_RATE Register ................................................................................................ 2271
14-191. GAP_THRESH Register .............................................................................................. 2272
14-192. TX_START_WDS Register ........................................................................................... 2273
14-193. FLOW_CONTROL Register .......................................................................................... 2274
14-194. VLAN_LTYPE Register ............................................................................................... 2275
14-195. TS_LTYPE Register ................................................................................................... 2276
14-196. DLR_LTYPE Register ................................................................................................. 2277
14-197. IDVER Register ........................................................................................................ 2279

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14-199. CONTROL Register ................................................................................................... 2281
14-200. INT_CONTROL Register ............................................................................................. 2282
14-201. C0_RX_THRESH_EN Register ...................................................................................... 2283
14-202. C0_RX_EN Register ................................................................................................... 2284
14-203. C0_TX_EN Register ................................................................................................... 2285
14-204. C0_MISC_EN Register ................................................................................................ 2286
14-206. C1_RX_EN Register ................................................................................................... 2288
14-207. C1_TX_EN Register ................................................................................................... 2289
14-210. C2_RX_EN Register ................................................................................................... 2292
14-211. C2_TX_EN Register ................................................................................................... 2293
14-213. C0_RX_THRESH_STAT Register ................................................................................... 2295
14-214. C0_RX_STAT Register ............................................................................................... 2296
14-215. C0_TX_STAT Register ................................................................................................ 2297
14-216. C0_MISC_STAT Register ............................................................................................ 2298
14-225. C0_RX_IMAX Register ................................................................................................ 2307
14-226. C0_TX_IMAX Register ................................................................................................ 2308
14-231. RGMII_CTL Register .................................................................................................. 2313
14-232. MDIO Version Register (MDIOVER) ................................................................................ 2314
14-233. MDIO Control Register (MDIOCONTROL) ......................................................................... 2315
14-234. PHY Acknowledge Status Register (MDIOALIVE) ................................................................ 2316
14-235. PHY Link Status Register (MDIOLINK) ............................................................................. 2316
14-236. MDIO Link Status Change Interrupt Register (MDIOLINKINTRAW) ............................................ 2317
14-237. MDIO Link Status Change Interrupt Register (Masked Value) (MDIOLINKINTMASKED) ................... 2317
14-238. MDIO User Command Complete Interrupt Register (Raw Value) (MDIOUSERINTRAW) ................... 2318
14-239. MDIO User Command Complete Interrupt Register (Masked Value) (MDIOUSERINTMASKED) .......... 2318
14-240. MDIO User Command Complete Interrupt Mask Set Register (MDIOUSERINTMASKSET) ................ 2319
14-241. MDIO User Command Complete Interrupt Mask Clear Register (MDIOUSERINTMASKCLR) ............. 2319
14-242. MDIO User Access Register 0 (MDIOUSERACCESS0) ......................................................... 2320
14-243. MDIO User PHY Select Register 0 (MDIOUSERPHYSEL0) ..................................................... 2321
14-244. MDIO User Access Register 1 (MDIOUSERACCESS1) ......................................................... 2322
14-245. MDIO User PHY Select Register 1 (MDIOUSERPHYSEL1) ..................................................... 2323
15-1. PWMSS Integration ..................................................................................................... 2327

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15-2. PWMSS Synchronization............................................................................................... 2328

15-3. IDVER Register .......................................................................................................... 2330
15-5. CLKCONFIG Register .................................................................................................. 2332
15-6. CLKSTATUS Register .................................................................................................. 2333
15-7. Multiple ePWM Modules................................................................................................ 2335
15-8. Submodules and Signal Connections for an ePWM Module ...................................................... 2336
15-9. ePWM Submodules and Critical Internal Signal Interconnects ................................................... 2337
15-10. Time-Base Submodule Block Diagram ............................................................................... 2341
15-11. Time-Base Submodule Signals and Registers ...................................................................... 2343
15-12. Time-Base Frequency and Period .................................................................................... 2345
15-13. Time-Base Counter Synchronization Scheme 1 .................................................................... 2346
15-14. Time-Base Up-Count Mode Waveforms ............................................................................. 2348
15-15. Time-Base Down-Count Mode Waveforms .......................................................................... 2349
15-16. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down on Synchronization Event ... 2349
15-17. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up on Synchronization Event ....... 2350
15-18. Counter-Compare Submodule ......................................................................................... 2351
15-19. Counter-Compare Submodule Signals and Registers.............................................................. 2351
15-20. Counter-Compare Event Waveforms in Up-Count Mode .......................................................... 2354
15-21. Counter-Compare Events in Down-Count Mode .................................................................... 2354
15-22. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down on
Synchronization Event ................................................................................................. 2355
15-23. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up on Synchronization
Event ..................................................................................................................... 2355
15-24. Action-Qualifier Submodule ............................................................................................ 2356
15-25. Action-Qualifier Submodule Inputs and Outputs .................................................................... 2357
15-26. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs ......................................... 2358
15-27. Up-Down-Count Mode Symmetrical Waveform ..................................................................... 2361
15-28. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High ................................................................................................. 2362
15-29. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low ................................................................................................. 2364
15-30. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA ........... 2366
15-31. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low ................................................................................................ 2368
15-32. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary .......................................................................................... 2370
15-33. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low ........................................................................................................................ 2372
15-34. Dead-Band Generator Submodule .................................................................................... 2374
15-35. Configuration Options for the Dead-Band Generator Submodule ................................................ 2375
15-36. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%).................................................. 2377
15-37. PWM-Chopper Submodule ............................................................................................ 2378
15-38. PWM-Chopper Submodule Signals and Registers ................................................................. 2379
15-39. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only ............................... 2380
15-40. PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses ...... 2380
15-41. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses ..................................................................................................................... 2381
15-42. Trip-Zone Submodule ................................................................................................... 2382
15-43. Trip-Zone Submodule Mode Control Logic .......................................................................... 2385
15-44. Trip-Zone Submodule Interrupt Logic................................................................................. 2385

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15-45. Event-Trigger Submodule .............................................................................................. 2386

15-46. Event-Trigger Submodule Inter-Connectivity to Interrupt Controller .............................................. 2387
15-47. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs....................................... 2387
15-48. Event-Trigger Interrupt Generator ..................................................................................... 2389
15-49. HRPWM System Interface ............................................................................................. 2390
15-50. Resolution Calculations for Conventionally Generated PWM ..................................................... 2391
15-51. Operating Logic Using MEP ........................................................................................... 2392
15-52. Required PWM Waveform for a Requested Duty = 40.5% ........................................................ 2394
15-53. Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz .............................. 2396
15-54. High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz .............................. 2396
15-55. Simplified ePWM Module............................................................................................... 2409
15-56. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave ..................................... 2410
15-57. Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 .................................................. 2411
15-58. Buck Waveforms for (Note: Only three bucks shown here) ....................................................... 2412
15-59. Control of Four Buck Stages. (Note: FPWM2 = N × FPWM1) ........................................................... 2414
15-60. Buck Waveforms for (Note: FPWM2 = FPWM1))........................................................................... 2415
15-61. Control of Two Half-H Bridge Stages (FPWM2 = N × FPWM1) .......................................................... 2417
15-62. Half-H Bridge Waveforms for (Note: Here FPWM2 = FPWM1 ) .......................................................... 2418
15-63. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control ............................. 2420
15-64. 3-Phase Inverter Waveforms for (Only One Inverter Shown) ..................................................... 2421
15-65. Configuring Two PWM Modules for Phase Control ................................................................. 2424
15-66. Timing Waveforms Associated With Phase Control Between 2 Modules ....................................... 2425
15-67. Control of a 3-Phase Interleaved DC/DC Converter ................................................................ 2426
15-68. 3-Phase Interleaved DC/DC Converter Waveforms for ........................................................... 2427
15-69. Controlling a Full-H Bridge Stage (FPWM2 = FPWM1) ................................................................... 2430
15-70. ZVS Full-H Bridge Waveforms ........................................................................................ 2431
15-71. TBCTL Register ......................................................................................................... 2434
15-72. TBSTS Register ......................................................................................................... 2436
15-73. TBPHSHR Register ..................................................................................................... 2437
15-74. TBPHS Register ......................................................................................................... 2438
15-75. TBCNT Register ......................................................................................................... 2439
15-76. TBPRD Register ......................................................................................................... 2440
15-77. CMPCTL Register ....................................................................................................... 2441
15-78. CMPAHR Register ...................................................................................................... 2443
15-79. CMPA Register .......................................................................................................... 2444
15-80. CMPB Register .......................................................................................................... 2445
15-81. AQCTLA Register ....................................................................................................... 2446
15-82. AQCTLB Register ....................................................................................................... 2448
15-83. AQSFRC Register ....................................................................................................... 2450
15-84. AQCSFRC Register ..................................................................................................... 2451
15-85. DBCTL Register ......................................................................................................... 2452
15-86. DBRED Register ........................................................................................................ 2454
15-87. DBFED Register ......................................................................................................... 2455
15-88. TZSEL Register.......................................................................................................... 2456
15-89. TZCTL Register.......................................................................................................... 2457
15-90. TZEINT Register ........................................................................................................ 2458
15-91. TZFLG Register ......................................................................................................... 2459
15-92. TZCLR Register ......................................................................................................... 2460
15-93. TZFRC Register ......................................................................................................... 2461

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15-94. ETSEL Register ......................................................................................................... 2462

15-95. ETPS Register ........................................................................................................... 2463
15-96. ETFLG Register ......................................................................................................... 2464
15-97. ETCLR Register ......................................................................................................... 2465
15-98. ETFRC Register ......................................................................................................... 2466
15-99. PCCTL Register ......................................................................................................... 2467
15-100. HRCNFG Register ..................................................................................................... 2468
15-101. Multiple eCAP Modules ............................................................................................... 2470
15-102. Capture and APWM Modes of Operation .......................................................................... 2471
15-103. Capture Function Diagram ........................................................................................... 2472
15-104. Event Prescale Control ................................................................................................ 2473
15-105. Prescale Function Waveforms ....................................................................................... 2473
15-106. Continuous/One-shot Block Diagram ............................................................................... 2474
15-107. Counter and Synchronization Block Diagram ..................................................................... 2475
15-108. Interrupts in eCAP Module............................................................................................ 2477
15-109. PWM Waveform Details Of APWM Mode Operation ............................................................. 2478
15-110. Capture Sequence for Absolute Time-Stamp, Rising Edge Detect ............................................ 2480
15-111. Capture Sequence for Absolute Time-Stamp, Rising and Falling Edge Detect .............................. 2482
15-112. Capture Sequence for Delta Mode Time-Stamp, Rising Edge Detect ......................................... 2484
15-113. Capture Sequence for Delta Mode Time-Stamp, Rising and Falling Edge Detect ........................... 2486
15-114. PWM Waveform Details of APWM Mode Operation ............................................................. 2488
15-115. Multichannel PWM Example Using 4 eCAP Modules ............................................................ 2490
15-116. Multiphase (channel) Interleaved PWM Example Using 3 eCAP Modules .................................... 2493
15-117. TSCTR Register........................................................................................................ 2496
15-118. CTRPHS Register ..................................................................................................... 2497
15-119. CAP1 Register ......................................................................................................... 2498
15-120. CAP2 Register ......................................................................................................... 2499
15-121. CAP3 Register ......................................................................................................... 2500
15-122. CAP4 Register ......................................................................................................... 2501
15-123. ECCTL1 Register ...................................................................................................... 2502
15-124. ECCTL2 Register ...................................................................................................... 2504
15-125. ECEINT Register ....................................................................................................... 2506
15-126. ECFLG Register........................................................................................................ 2507
15-127. ECCLR Register ....................................................................................................... 2508
15-128. ECFRC Register ....................................................................................................... 2509
15-129. REVID Register ........................................................................................................ 2510
15-130. Optical Encoder Disk ................................................................................................. 2511
15-131. QEP Encoder Output Signal for Forward/Reverse Movement ................................................... 2512
15-132. Index Pulse Example ................................................................................................. 2512
15-133. Functional Block Diagram of the eQEP Peripheral ............................................................... 2515
15-134. Functional Block Diagram of Decoder Unit ......................................................................... 2516
15-135. Quadrature Decoder State Machine ................................................................................ 2518
15-136. Quadrature-clock and Direction Decoding ......................................................................... 2518
15-137. Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or F9Fh) ............. 2520
15-138. Position Counter Underflow/Overflow (QPOSMAX = 4) ........................................................ 2521
15-139. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1) .............................................. 2523
15-140. Strobe Event Latch (QEPCTL[SEL] = 1) ........................................................................... 2524
15-141. eQEP Position-compare Unit ........................................................................................ 2525
15-142. eQEP Position-compare Event Generation Points ................................................................ 2526

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15-143. eQEP Position-compare Sync Output Pulse Stretcher........................................................... 2526

15-144. eQEP Edge Capture Unit ............................................................................................ 2528
15-145. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010) ............................... 2528
15-146. eQEP Edge Capture Unit - Timing Details ......................................................................... 2529
15-147. eQEP Watchdog Timer ............................................................................................... 2530
15-148. eQEP Unit Time Base ................................................................................................ 2531
15-149. EQEP Interrupt Generation .......................................................................................... 2531
15-150. QPOSCNT Register ................................................................................................... 2533
15-151. QPOSINIT Register .................................................................................................... 2534
15-152. QPOSMAX Register ................................................................................................... 2535
15-153. QPOSCMP Register ................................................................................................... 2536
15-154. QPOSILAT Register ................................................................................................... 2537
15-155. QPOSSLAT Register .................................................................................................. 2538
15-156. QPOSLAT Register .................................................................................................... 2539
15-157. QUTMR Register ....................................................................................................... 2540
15-158. QUPRD Register ....................................................................................................... 2541
15-159. QWDTMR Register .................................................................................................... 2542
15-160. QWDPRD Register .................................................................................................... 2543
15-161. QDECCTL Register .................................................................................................... 2544
15-162. QEPCTL Register ...................................................................................................... 2545
15-163. QCAPCTL Register .................................................................................................... 2547
15-164. QPOSCTL Register .................................................................................................... 2548
15-165. QEINT Register ........................................................................................................ 2549
15-166. QFLG Register ......................................................................................................... 2550
15-167. QCLR Register ......................................................................................................... 2551
15-168. QFRC Register ......................................................................................................... 2552
15-169. QEPSTS Register...................................................................................................... 2553
15-170. QCTMR Register ....................................................................................................... 2554
15-171. QCPRD Register ....................................................................................................... 2555
15-172. QCTMRLAT Register .................................................................................................. 2556
15-173. QCPRDLAT Register .................................................................................................. 2557
15-174. REVID Register ........................................................................................................ 2558
16-1. USB Integration .......................................................................................................... 2563
16-2. USB GPIO Integration .................................................................................................. 2565
16-3. CPU Actions at Transfer Phases ...................................................................................... 2573
16-4. Sequence of Transfer ................................................................................................... 2574
16-5. Flow Chart of Setup Stage of a Control Transfer in Peripheral Mode ............................................ 2576
16-6. Flow Chart of Transmit Data Stage of a Control Transfer in Peripheral Mode .................................. 2577
16-7. Flow Chart of Receive Data Stage of a Control Transfer in Peripheral Mode .................................. 2578
16-8. Flow Chart of Setup Stage of a Control Transfer in Host Mode .................................................. 2589
16-9. Flow Chart of Data Stage (IN Data Phase) of a Control Transfer in Host Mode ............................... 2590
16-10. Flow Chart of Data Stage (OUT Data Phase) of a Control Transfer in Host Mode ............................ 2592
16-11. Flow Chart of Status Stage of Zero Data Request or Write Request of a Control Transfer in Host Mode .. 2593
16-12. Chart of Status Stage of a Read Request of a Control Transfer in Host Mode ................................. 2595
16-13. Packet Descriptor Layout............................................................................................... 2605
16-14. Buffer Descriptor (BD) Layout ......................................................................................... 2608
16-15. Teardown Descriptor Layout ........................................................................................... 2610
16-16. Relationship Between Memory Regions and Linking RAM ........................................................ 2615
16-17. High-level Transmit and Receive Data Transfer Example ......................................................... 2620

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16-18. Transmit Descriptors and Queue Status Configuration ............................................................ 2622

16-19. Transmit USB Data Flow Example (Initialization) ................................................................... 2623
16-20. Receive Buffer Descriptors and Queue Status Configuration ..................................................... 2625
16-21. Receive USB Data Flow Example (Initialization) .................................................................... 2626
16-22. REVREG Register....................................................................................................... 2632
16-24. IRQSTATRAW Register ................................................................................................ 2634
16-25. IRQSTAT Register ...................................................................................................... 2635
16-26. IRQENABLER Register................................................................................................. 2636
16-27. IRQCLEARR Register .................................................................................................. 2637
16-28. IRQDMATHOLDTX00 Register........................................................................................ 2638
16-32. IRQDMATHOLDRX00 Register ....................................................................................... 2642
16-44. IRQDMAENABLE0 Register ........................................................................................... 2654
16-45. IRQDMAENABLE1 Register ........................................................................................... 2656
16-46. IRQFRAMETHOLDTX00 Register .................................................................................... 2658
16-50. IRQFRAMETHOLDRX00 Register .................................................................................... 2662
16-62. IRQFRAMEENABLE0 Register........................................................................................ 2674
16-63. IRQFRAMEENABLE1 Register........................................................................................ 2675
16-64. USB0REV Register ..................................................................................................... 2677
16-65. USB0CTRL Register .................................................................................................... 2678
16-66. USB0STAT Register .................................................................................................... 2680

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16-67. USB0IRQMSTAT Register ............................................................................................. 2681

16-68. USB0IRQSTATRAW0 Register ....................................................................................... 2682
16-69. USB0IRQSTATRAW1 Register ....................................................................................... 2684
16-70. USB0IRQSTAT0 Register .............................................................................................. 2686
16-71. USB0IRQSTAT1 Register .............................................................................................. 2688
16-72. USB0IRQENABLESET0 Register ..................................................................................... 2690
16-73. USB0IRQENABLESET1 Register ..................................................................................... 2692
16-74. USB0IRQENABLECLR0 Register..................................................................................... 2694
16-75. USB0IRQENABLECLR1 Register..................................................................................... 2696
16-76. USB0TXMODE Register ............................................................................................... 2698
16-77. USB0RXMODE Register ............................................................................................... 2700
16-78. USB0GENRNDISEP1 Register........................................................................................ 2704
16-87. USB0GENRNDISEP10 Register ...................................................................................... 2713
16-93. USB0AUTOREQ Register.............................................................................................. 2719
16-94. USB0SRPFIXTIME Register ........................................................................................... 2721
16-95. USB0_TDOWN Register ............................................................................................... 2722
16-96. USB0UTMI Register .................................................................................................... 2723
16-97. USB0MGCUTMILB Register ........................................................................................... 2724
16-98. USB0MODE Register ................................................................................................... 2725
16-99. USB1REV Register ..................................................................................................... 2727
16-100. USB1CTRL Register .................................................................................................. 2728
16-101. USB1STAT Register ................................................................................................... 2730
16-102. USB1IRQMSTAT Register............................................................................................ 2731
16-103. USB1IRQSTATRAW0 Register ...................................................................................... 2732
16-104. USB1IRQSTATRAW1 Register ...................................................................................... 2734
16-105. USB1IRQSTAT0 Register ............................................................................................ 2736
16-106. USB1IRQSTAT1 Register ............................................................................................ 2738
16-107. USB1IRQENABLESET0 Register ................................................................................... 2740
16-108. USB1IRQENABLESET1 Register ................................................................................... 2742
16-109. USB1IRQENABLECLR0 Register ................................................................................... 2744
16-110. USB1IRQENABLECLR1 Register ................................................................................... 2746
16-111. USB1TXMODE Register .............................................................................................. 2748
16-112. USB1RXMODE Register .............................................................................................. 2750

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16-122. USB1GENRNDISEP10 Register ..................................................................................... 2761
16-128. USB1AUTOREQ Register ............................................................................................ 2767
16-129. USB1SRPFIXTIME Register ......................................................................................... 2769
16-130. USB1TDOWN Register ............................................................................................... 2770
16-131. USB1UTMI Register ................................................................................................... 2771
16-132. USB1UTMILB Register ................................................................................................ 2772
16-133. USB1MODE Register ................................................................................................. 2773
16-134. Termination_control Register ......................................................................................... 2775
16-135. RX_CALIB Register ................................................................................................... 2776
16-136. DLLHS_2 Register ..................................................................................................... 2778
16-137. RX_TEST_2 Register ................................................................................................. 2779
16-138. CHRG_DET Register .................................................................................................. 2780
16-139. PWR_CNTL Register .................................................................................................. 2782
16-140. UTMI_INTERFACE_CNTL_1 Register .............................................................................. 2783
16-141. UTMI_INTERFACE_CNTL_2 Register .............................................................................. 2784
16-142. BIST Register........................................................................................................... 2786
16-143. BIST_CRC Register ................................................................................................... 2787
16-144. CDR_BIST2 Register .................................................................................................. 2788
16-145. GPIO Register .......................................................................................................... 2789
16-146. DLLHS Register ........................................................................................................ 2790
16-147. USB2PHYCM_CONFIG Register .................................................................................... 2792
16-148. AD_INTERFACE_REG1 Register ................................................................................... 2793
16-151. ANA_CONFIG2 Register ............................................................................................. 2798
16-152. DMAREVID Register .................................................................................................. 2802
16-153. TDFDQ Register ....................................................................................................... 2803
16-154. DMAEMU Register..................................................................................................... 2804
16-155. TXGCR0 Register ...................................................................................................... 2805
16-156. RXGCR0 Register ..................................................................................................... 2806
16-157. RXHPCRA0 Register .................................................................................................. 2808
16-158. RXHPCRB0 Register .................................................................................................. 2809
16-159. TXGCR1 Register ...................................................................................................... 2810
16-160. RXGCR1 Register ..................................................................................................... 2811
16-163. TXGCR2 Register ...................................................................................................... 2815
16-164. RXGCR2 Register ..................................................................................................... 2816

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16-167. TXGCR3 Register ...................................................................................................... 2820
16-168. RXGCR3 Register ..................................................................................................... 2821
16-171. TXGCR4 Register ...................................................................................................... 2825
16-172. RXGCR4 Register ..................................................................................................... 2826
16-175. TXGCR5 Register ...................................................................................................... 2830
16-176. RXGCR5 Register ..................................................................................................... 2831
16-179. TXGCR6 Register ...................................................................................................... 2835
16-180. RXGCR6 Register ..................................................................................................... 2836
16-183. TXGCR7 Register ...................................................................................................... 2840
16-184. RXGCR7 Register ..................................................................................................... 2841
16-187. TXGCR8 Register ...................................................................................................... 2845
16-188. RXGCR8 Register ..................................................................................................... 2846
16-191. TXGCR9 Register ...................................................................................................... 2850
16-192. RXGCR9 Register ..................................................................................................... 2851
16-195. TXGCR10 Register .................................................................................................... 2855
16-196. RXGCR10 Register .................................................................................................... 2856
16-197. RXHPCRA10 Register ................................................................................................ 2858
16-198. RXHPCRB10 Register ................................................................................................ 2859
16-199. TXGCR11 Register .................................................................................................... 2860
16-200. RXGCR11 Register .................................................................................................... 2861
16-203. TXGCR12 Register .................................................................................................... 2865
16-204. RXGCR12 Register .................................................................................................... 2866
16-207. TXGCR13 Register .................................................................................................... 2870
16-208. RXGCR13 Register .................................................................................................... 2871
16-211. TXGCR14 Register .................................................................................................... 2875
16-212. RXGCR14 Register .................................................................................................... 2876

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16-215. TXGCR15 Register .................................................................................................... 2880
16-216. RXGCR15 Register .................................................................................................... 2881
16-219. TXGCR16 Register .................................................................................................... 2885
16-220. RXGCR16 Register .................................................................................................... 2886
16-223. TXGCR17 Register .................................................................................................... 2890
16-224. RXGCR17 Register .................................................................................................... 2891
16-227. TXGCR18 Register .................................................................................................... 2895
16-228. RXGCR18 Register .................................................................................................... 2896
16-231. TXGCR19 Register .................................................................................................... 2900
16-232. RXGCR19 Register .................................................................................................... 2901
16-235. TXGCR20 Register .................................................................................................... 2905
16-236. RXGCR20 Register .................................................................................................... 2906
16-239. TXGCR21 Register .................................................................................................... 2910
16-240. RXGCR21 Register .................................................................................................... 2911
16-243. TXGCR22 Register .................................................................................................... 2915
16-244. RXGCR22 Register .................................................................................................... 2916
16-247. TXGCR23 Register .................................................................................................... 2920
16-248. RXGCR23 Register .................................................................................................... 2921
16-251. TXGCR24 Register .................................................................................................... 2925
16-252. RXGCR24 Register .................................................................................................... 2926
16-255. TXGCR25 Register .................................................................................................... 2930
16-256. RXGCR25 Register .................................................................................................... 2931
16-259. TXGCR26 Register .................................................................................................... 2935
16-260. RXGCR26 Register .................................................................................................... 2936

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16-263. TXGCR27 Register .................................................................................................... 2940

16-264. RXGCR27 Register .................................................................................................... 2941
16-267. TXGCR28 Register .................................................................................................... 2945
16-268. RXGCR28 Register .................................................................................................... 2946
16-271. TXGCR29 Register .................................................................................................... 2950
16-272. RXGCR29 Register .................................................................................................... 2951
16-275. DMA_SCHED_CTRL Register ....................................................................................... 2955
16-276. WORD_0 to WORD_63 Register .................................................................................... 2956
16-277. QMGRREVID Register ................................................................................................ 2982
16-278. QMGRRST Register ................................................................................................... 2983
16-279. FDBSC0 Register ...................................................................................................... 2984
16-280. FDBSC1 Register ...................................................................................................... 2985
16-281. FDBSC2 Register ...................................................................................................... 2986
16-282. FDBSC3 Register ...................................................................................................... 2987
16-283. FDBSC4 Register ...................................................................................................... 2988
16-284. FDBSC5 Register ...................................................................................................... 2989
16-285. FDBSC6 Register ...................................................................................................... 2990
16-286. FDBSC7 Register ...................................................................................................... 2991
16-287. LRAM0BASE Register ................................................................................................ 2992
16-288. LRAM0SIZE Register.................................................................................................. 2993
16-289. LRAM1BASE Register ................................................................................................ 2994
16-290. PEND0 Register........................................................................................................ 2995
16-291. PEND1 Register........................................................................................................ 2996
16-292. PEND2 Register........................................................................................................ 2997
16-293. PEND3 Register........................................................................................................ 2998
16-294. PEND4 Register........................................................................................................ 2999
16-295. QMEMRBASE0 Register ............................................................................................. 3000
16-296. QMEMCTRL0 Register ................................................................................................ 3001
16-311. QUEUE_0_A Register ................................................................................................. 3016

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16-312. QUEUE_0_B Register ................................................................................................. 3017

16-313. QUEUE_0_C Register ................................................................................................ 3018
16-314. QUEUE_0_D Register ................................................................................................ 3019
16-315. QUEUE_1_A Register ................................................................................................. 3020
16-316. QUEUE_1_B Register ................................................................................................. 3021
16-317. QUEUE_1_C Register ................................................................................................ 3022
16-318. QUEUE_1_D Register ................................................................................................ 3023
16-319. QUEUE_2_A Register ................................................................................................. 3024
16-320. QUEUE_2_B Register ................................................................................................. 3025
16-321. QUEUE_2_C Register ................................................................................................ 3026
16-322. QUEUE_2_D Register ................................................................................................ 3027
16-323. QUEUE_3_A Register ................................................................................................. 3028
16-324. QUEUE_3_B Register ................................................................................................. 3029
16-325. QUEUE_3_C Register ................................................................................................ 3030
16-326. QUEUE_3_D Register ................................................................................................ 3031
16-327. QUEUE_4_A Register ................................................................................................. 3032
16-328. QUEUE_4_B Register ................................................................................................. 3033
16-329. QUEUE_4_C Register ................................................................................................ 3034
16-330. QUEUE_4_D Register ................................................................................................ 3035
16-331. QUEUE_5_A Register ................................................................................................. 3036
16-332. QUEUE_5_B Register ................................................................................................. 3037
16-333. QUEUE_5_C Register ................................................................................................ 3038
16-334. QUEUE_5_D Register ................................................................................................ 3039
16-335. QUEUE_6_A Register ................................................................................................. 3040
16-336. QUEUE_6_B Register ................................................................................................. 3041
16-337. QUEUE_6_C Register ................................................................................................ 3042
16-338. QUEUE_6_D Register ................................................................................................ 3043
16-339. QUEUE_7_A Register ................................................................................................. 3044
16-340. QUEUE_7_B Register ................................................................................................. 3045
16-341. QUEUE_7_C Register ................................................................................................ 3046
16-342. QUEUE_7_D Register ................................................................................................ 3047
16-343. QUEUE_8_A Register ................................................................................................. 3048
16-344. QUEUE_8_B Register ................................................................................................. 3049
16-345. QUEUE_8_C Register ................................................................................................ 3050
16-346. QUEUE_8_D Register ................................................................................................ 3051
16-347. QUEUE_9_A Register ................................................................................................. 3052
16-348. QUEUE_9_B Register ................................................................................................. 3053
16-349. QUEUE_9_C Register ................................................................................................ 3054
16-350. QUEUE_9_D Register ................................................................................................ 3055
16-351. QUEUE_10_A Register ............................................................................................... 3056
16-352. QUEUE_10_B Register ............................................................................................... 3057
16-353. QUEUE_10_C Register ............................................................................................... 3058
16-354. QUEUE_10_D Register ............................................................................................... 3059
16-355. QUEUE_11_A Register ............................................................................................... 3060
16-356. QUEUE_11_B Register ............................................................................................... 3061
16-357. QUEUE_11_C Register ............................................................................................... 3062
16-358. QUEUE_11_D Register ............................................................................................... 3063
16-359. QUEUE_12_A Register ............................................................................................... 3064
16-360. QUEUE_12_B Register ............................................................................................... 3065

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16-361. QUEUE_12_C Register ............................................................................................... 3066

16-362. QUEUE_12_D Register ............................................................................................... 3067
16-363. QUEUE_13_A Register ............................................................................................... 3068
16-364. QUEUE_13_B Register ............................................................................................... 3069
16-365. QUEUE_13_C Register ............................................................................................... 3070
16-366. QUEUE_13_D Register ............................................................................................... 3071
16-367. QUEUE_14_A Register ............................................................................................... 3072
16-368. QUEUE_14_B Register ............................................................................................... 3073
16-369. QUEUE_14_C Register ............................................................................................... 3074
16-370. QUEUE_14_D Register ............................................................................................... 3075
16-371. QUEUE_15_A Register ............................................................................................... 3076
16-372. QUEUE_15_B Register ............................................................................................... 3077
16-373. QUEUE_15_C Register ............................................................................................... 3078
16-374. QUEUE_15_D Register ............................................................................................... 3079
16-375. QUEUE_16_A Register ............................................................................................... 3080
16-376. QUEUE_16_B Register ............................................................................................... 3081
16-377. QUEUE_16_C Register ............................................................................................... 3082
16-378. QUEUE_16_D Register ............................................................................................... 3083
16-379. QUEUE_17_A Register ............................................................................................... 3084
16-380. QUEUE_17_B Register ............................................................................................... 3085
16-381. QUEUE_17_C Register ............................................................................................... 3086
16-382. QUEUE_17_D Register ............................................................................................... 3087
16-383. QUEUE_18_A Register ............................................................................................... 3088
16-384. QUEUE_18_B Register ............................................................................................... 3089
16-385. QUEUE_18_C Register ............................................................................................... 3090
16-386. QUEUE_18_D Register ............................................................................................... 3091
16-387. QUEUE_19_A Register ............................................................................................... 3092
16-388. QUEUE_19_B Register ............................................................................................... 3093
16-389. QUEUE_19_C Register ............................................................................................... 3094
16-390. QUEUE_19_D Register ............................................................................................... 3095
16-391. QUEUE_20_A Register ............................................................................................... 3096
16-392. QUEUE_20_B Register ............................................................................................... 3097
16-393. QUEUE_20_C Register ............................................................................................... 3098
16-394. QUEUE_20_D Register ............................................................................................... 3099
16-395. QUEUE_21_A Register ............................................................................................... 3100
16-396. QUEUE_21_B Register ............................................................................................... 3101
16-397. QUEUE_21_C Register ............................................................................................... 3102
16-398. QUEUE_21_D Register ............................................................................................... 3103
16-399. QUEUE_22_A Register ............................................................................................... 3104
16-400. QUEUE_22_B Register ............................................................................................... 3105
16-401. QUEUE_22_C Register ............................................................................................... 3106
16-402. QUEUE_22_D Register ............................................................................................... 3107
16-403. QUEUE_23_A Register ............................................................................................... 3108
16-404. QUEUE_23_B Register ............................................................................................... 3109
16-405. QUEUE_23_C Register ............................................................................................... 3110
16-406. QUEUE_23_D Register ............................................................................................... 3111
16-407. QUEUE_24_A Register ............................................................................................... 3112
16-408. QUEUE_24_B Register ............................................................................................... 3113
16-409. QUEUE_24_C Register ............................................................................................... 3114

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16-410. QUEUE_24_D Register ............................................................................................... 3115

16-411. QUEUE_25_A Register ............................................................................................... 3116
16-412. QUEUE_25_B Register ............................................................................................... 3117
16-413. QUEUE_25_C Register ............................................................................................... 3118
16-414. QUEUE_25_D Register ............................................................................................... 3119
16-415. QUEUE_26_A Register ............................................................................................... 3120
16-416. QUEUE_26_B Register ............................................................................................... 3121
16-417. QUEUE_26_C Register ............................................................................................... 3122
16-418. QUEUE_26_D Register ............................................................................................... 3123
16-419. QUEUE_27_A Register ............................................................................................... 3124
16-420. QUEUE_27_B Register ............................................................................................... 3125
16-421. QUEUE_27_C Register ............................................................................................... 3126
16-422. QUEUE_27_D Register ............................................................................................... 3127
16-423. QUEUE_28_A Register ............................................................................................... 3128
16-424. QUEUE_28_B Register ............................................................................................... 3129
16-425. QUEUE_28_C Register ............................................................................................... 3130
16-426. QUEUE_28_D Register ............................................................................................... 3131
16-427. QUEUE_29_A Register ............................................................................................... 3132
16-428. QUEUE_29_B Register ............................................................................................... 3133
16-429. QUEUE_29_C Register ............................................................................................... 3134
16-430. QUEUE_29_D Register ............................................................................................... 3135
16-431. QUEUE_30_A Register ............................................................................................... 3136
16-432. QUEUE_30_B Register ............................................................................................... 3137
16-433. QUEUE_30_C Register ............................................................................................... 3138
16-434. QUEUE_30_D Register ............................................................................................... 3139
16-435. QUEUE_31_A Register ............................................................................................... 3140
16-436. QUEUE_31_B Register ............................................................................................... 3141
16-437. QUEUE_31_C Register ............................................................................................... 3142
16-438. QUEUE_31_D Register ............................................................................................... 3143
16-439. QUEUE_32_A Register ............................................................................................... 3144
16-440. QUEUE_32_B Register ............................................................................................... 3145
16-441. QUEUE_32_C Register ............................................................................................... 3146
16-442. QUEUE_32_D Register ............................................................................................... 3147
16-443. QUEUE_33_A Register ............................................................................................... 3148
16-444. QUEUE_33_B Register ............................................................................................... 3149
16-445. QUEUE_33_C Register ............................................................................................... 3150
16-446. QUEUE_33_D Register ............................................................................................... 3151
16-447. QUEUE_34_A Register ............................................................................................... 3152
16-448. QUEUE_34_B Register ............................................................................................... 3153
16-449. QUEUE_34_C Register ............................................................................................... 3154
16-450. QUEUE_34_D Register ............................................................................................... 3155
16-451. QUEUE_35_A Register ............................................................................................... 3156
16-452. QUEUE_35_B Register ............................................................................................... 3157
16-453. QUEUE_35_C Register ............................................................................................... 3158
16-454. QUEUE_35_D Register ............................................................................................... 3159
16-455. QUEUE_36_A Register ............................................................................................... 3160
16-456. QUEUE_36_B Register ............................................................................................... 3161
16-457. QUEUE_36_C Register ............................................................................................... 3162
16-458. QUEUE_36_D Register ............................................................................................... 3163

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16-459. QUEUE_37_A Register ............................................................................................... 3164

16-460. QUEUE_37_B Register ............................................................................................... 3165
16-461. QUEUE_37_C Register ............................................................................................... 3166
16-462. QUEUE_37_D Register ............................................................................................... 3167
16-463. QUEUE_38_A Register ............................................................................................... 3168
16-464. QUEUE_38_B Register ............................................................................................... 3169
16-465. QUEUE_38_C Register ............................................................................................... 3170
16-466. QUEUE_38_D Register ............................................................................................... 3171
16-467. QUEUE_39_A Register ............................................................................................... 3172
16-468. QUEUE_39_B Register ............................................................................................... 3173
16-469. QUEUE_39_C Register ............................................................................................... 3174
16-470. QUEUE_39_D Register ............................................................................................... 3175
16-471. QUEUE_40_A Register ............................................................................................... 3176
16-472. QUEUE_40_B Register ............................................................................................... 3177
16-473. QUEUE_40_C Register ............................................................................................... 3178
16-474. QUEUE_40_D Register ............................................................................................... 3179
16-475. QUEUE_41_A Register ............................................................................................... 3180
16-476. QUEUE_41_B Register ............................................................................................... 3181
16-477. QUEUE_41_C Register ............................................................................................... 3182
16-478. QUEUE_41_D Register ............................................................................................... 3183
16-479. QUEUE_42_A Register ............................................................................................... 3184
16-480. QUEUE_42_B Register ............................................................................................... 3185
16-481. QUEUE_42_C Register ............................................................................................... 3186
16-482. QUEUE_42_D Register ............................................................................................... 3187
16-483. QUEUE_43_A Register ............................................................................................... 3188
16-484. QUEUE_43_B Register ............................................................................................... 3189
16-485. QUEUE_43_C Register ............................................................................................... 3190
16-486. QUEUE_43_D Register ............................................................................................... 3191
16-487. QUEUE_44_A Register ............................................................................................... 3192
16-488. QUEUE_44_B Register ............................................................................................... 3193
16-489. QUEUE_44_C Register ............................................................................................... 3194
16-490. QUEUE_44_D Register ............................................................................................... 3195
16-491. QUEUE_45_A Register ............................................................................................... 3196
16-492. QUEUE_45_B Register ............................................................................................... 3197
16-493. QUEUE_45_C Register ............................................................................................... 3198
16-494. QUEUE_45_D Register ............................................................................................... 3199
16-495. QUEUE_46_A Register ............................................................................................... 3200
16-496. QUEUE_46_B Register ............................................................................................... 3201
16-497. QUEUE_46_C Register ............................................................................................... 3202
16-498. QUEUE_46_D Register ............................................................................................... 3203
16-499. QUEUE_47_A Register ............................................................................................... 3204
16-500. QUEUE_47_B Register ............................................................................................... 3205
16-501. QUEUE_47_C Register ............................................................................................... 3206
16-502. QUEUE_47_D Register ............................................................................................... 3207
16-503. QUEUE_48_A Register ............................................................................................... 3208
16-504. QUEUE_48_B Register ............................................................................................... 3209
16-505. QUEUE_48_C Register ............................................................................................... 3210
16-506. QUEUE_48_D Register ............................................................................................... 3211
16-507. QUEUE_49_A Register ............................................................................................... 3212

www.ti.com
16-508. QUEUE_49_B Register ............................................................................................... 3213

16-509. QUEUE_49_C Register ............................................................................................... 3214
16-510. QUEUE_49_D Register ............................................................................................... 3215
16-511. QUEUE_50_A Register ............................................................................................... 3216
16-512. QUEUE_50_B Register ............................................................................................... 3217
16-513. QUEUE_50_C Register ............................................................................................... 3218
16-514. QUEUE_50_D Register ............................................................................................... 3219
16-515. QUEUE_51_A Register ............................................................................................... 3220
16-516. QUEUE_51_B Register ............................................................................................... 3221
16-517. QUEUE_51_C Register ............................................................................................... 3222
16-518. QUEUE_51_D Register ............................................................................................... 3223
16-519. QUEUE_52_A Register ............................................................................................... 3224
16-520. QUEUE_52_B Register ............................................................................................... 3225
16-521. QUEUE_52_C Register ............................................................................................... 3226
16-522. QUEUE_52_D Register ............................................................................................... 3227
16-523. QUEUE_53_A Register ............................................................................................... 3228
16-524. QUEUE_53_B Register ............................................................................................... 3229
16-525. QUEUE_53_C Register ............................................................................................... 3230
16-526. QUEUE_53_D Register ............................................................................................... 3231
16-527. QUEUE_54_A Register ............................................................................................... 3232
16-528. QUEUE_54_B Register ............................................................................................... 3233
16-529. QUEUE_54_C Register ............................................................................................... 3234
16-530. QUEUE_54_D Register ............................................................................................... 3235
16-531. QUEUE_55_A Register ............................................................................................... 3236
16-532. QUEUE_55_B Register ............................................................................................... 3237
16-533. QUEUE_55_C Register ............................................................................................... 3238
16-534. QUEUE_55_D Register ............................................................................................... 3239
16-535. QUEUE_56_A Register ............................................................................................... 3240
16-536. QUEUE_56_B Register ............................................................................................... 3241
16-537. QUEUE_56_C Register ............................................................................................... 3242
16-538. QUEUE_56_D Register ............................................................................................... 3243
16-539. QUEUE_57_A Register ............................................................................................... 3244
16-540. QUEUE_57_B Register ............................................................................................... 3245
16-541. QUEUE_57_C Register ............................................................................................... 3246
16-542. QUEUE_57_D Register ............................................................................................... 3247
16-543. QUEUE_58_A Register ............................................................................................... 3248
16-544. QUEUE_58_B Register ............................................................................................... 3249
16-545. QUEUE_58_C Register ............................................................................................... 3250
16-546. QUEUE_58_D Register ............................................................................................... 3251
16-547. QUEUE_59_A Register ............................................................................................... 3252
16-548. QUEUE_59_B Register ............................................................................................... 3253
16-549. QUEUE_59_C Register ............................................................................................... 3254
16-550. QUEUE_59_D Register ............................................................................................... 3255
16-551. QUEUE_60_A Register ............................................................................................... 3256
16-552. QUEUE_60_B Register ............................................................................................... 3257
16-553. QUEUE_60_C Register ............................................................................................... 3258
16-554. QUEUE_60_D Register ............................................................................................... 3259
16-555. QUEUE_61_A Register ............................................................................................... 3260
16-556. QUEUE_61_B Register ............................................................................................... 3261

www.ti.com
16-557. QUEUE_61_C Register ............................................................................................... 3262

16-558. QUEUE_61_D Register ............................................................................................... 3263
16-559. QUEUE_62_A Register ............................................................................................... 3264
16-560. QUEUE_62_B Register ............................................................................................... 3265
16-561. QUEUE_62_C Register ............................................................................................... 3266
16-562. QUEUE_62_D Register ............................................................................................... 3267
16-563. QUEUE_63_A Register ............................................................................................... 3268
16-564. QUEUE_63_B Register ............................................................................................... 3269
16-565. QUEUE_63_C Register ............................................................................................... 3270
16-566. QUEUE_63_D Register ............................................................................................... 3271
16-567. QUEUE_64_A Register ............................................................................................... 3272
16-568. QUEUE_64_B Register ............................................................................................... 3273
16-569. QUEUE_64_C Register ............................................................................................... 3274
16-570. QUEUE_64_D Register ............................................................................................... 3275
16-571. QUEUE_65_A Register ............................................................................................... 3276
16-572. QUEUE_65_B Register ............................................................................................... 3277
16-573. QUEUE_65_C Register ............................................................................................... 3278
16-574. QUEUE_65_D Register ............................................................................................... 3279
16-575. QUEUE_66_A Register ............................................................................................... 3280
16-576. QUEUE_66_B Register ............................................................................................... 3281
16-577. QUEUE_66_C Register ............................................................................................... 3282
16-578. QUEUE_66_D Register ............................................................................................... 3283
16-579. QUEUE_67_A Register ............................................................................................... 3284
16-580. QUEUE_67_B Register ............................................................................................... 3285
16-581. QUEUE_67_C Register ............................................................................................... 3286
16-582. QUEUE_67_D Register ............................................................................................... 3287
16-583. QUEUE_68_A Register ............................................................................................... 3288
16-584. QUEUE_68_B Register ............................................................................................... 3289
16-585. QUEUE_68_C Register ............................................................................................... 3290
16-586. QUEUE_68_D Register ............................................................................................... 3291
16-587. QUEUE_69_A Register ............................................................................................... 3292
16-588. QUEUE_69_B Register ............................................................................................... 3293
16-589. QUEUE_69_C Register ............................................................................................... 3294
16-590. QUEUE_69_D Register ............................................................................................... 3295
16-591. QUEUE_70_A Register ............................................................................................... 3296
16-592. QUEUE_70_B Register ............................................................................................... 3297
16-593. QUEUE_70_C Register ............................................................................................... 3298
16-594. QUEUE_70_D Register ............................................................................................... 3299
16-595. QUEUE_71_A Register ............................................................................................... 3300
16-596. QUEUE_71_B Register ............................................................................................... 3301
16-597. QUEUE_71_C Register ............................................................................................... 3302
16-598. QUEUE_71_D Register ............................................................................................... 3303
16-599. QUEUE_72_A Register ............................................................................................... 3304
16-600. QUEUE_72_B Register ............................................................................................... 3305
16-601. QUEUE_72_C Register ............................................................................................... 3306
16-602. QUEUE_72_D Register ............................................................................................... 3307
16-603. QUEUE_73_A Register ............................................................................................... 3308
16-604. QUEUE_73_B Register ............................................................................................... 3309
16-605. QUEUE_73_C Register ............................................................................................... 3310

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16-606. QUEUE_73_D Register ............................................................................................... 3311

16-607. QUEUE_74_A Register ............................................................................................... 3312
16-608. QUEUE_74_B Register ............................................................................................... 3313
16-609. QUEUE_74_C Register ............................................................................................... 3314
16-610. QUEUE_74_D Register ............................................................................................... 3315
16-611. QUEUE_75_A Register ............................................................................................... 3316
16-612. QUEUE_75_B Register ............................................................................................... 3317
16-613. QUEUE_75_C Register ............................................................................................... 3318
16-614. QUEUE_75_D Register ............................................................................................... 3319
16-615. QUEUE_76_A Register ............................................................................................... 3320
16-616. QUEUE_76_B Register ............................................................................................... 3321
16-617. QUEUE_76_C Register ............................................................................................... 3322
16-618. QUEUE_76_D Register ............................................................................................... 3323
16-619. QUEUE_77_A Register ............................................................................................... 3324
16-620. QUEUE_77_B Register ............................................................................................... 3325
16-621. QUEUE_77_C Register ............................................................................................... 3326
16-622. QUEUE_77_D Register ............................................................................................... 3327
16-623. QUEUE_78_A Register ............................................................................................... 3328
16-624. QUEUE_78_B Register ............................................................................................... 3329
16-625. QUEUE_78_C Register ............................................................................................... 3330
16-626. QUEUE_78_D Register ............................................................................................... 3331
16-627. QUEUE_79_A Register ............................................................................................... 3332
16-628. QUEUE_79_B Register ............................................................................................... 3333
16-629. QUEUE_79_C Register ............................................................................................... 3334
16-630. QUEUE_79_D Register ............................................................................................... 3335
16-631. QUEUE_80_A Register ............................................................................................... 3336
16-632. QUEUE_80_B Register ............................................................................................... 3337
16-633. QUEUE_80_C Register ............................................................................................... 3338
16-634. QUEUE_80_D Register ............................................................................................... 3339
16-635. QUEUE_81_A Register ............................................................................................... 3340
16-636. QUEUE_81_B Register ............................................................................................... 3341
16-637. QUEUE_81_C Register ............................................................................................... 3342
16-638. QUEUE_81_D Register ............................................................................................... 3343
16-639. QUEUE_82_A Register ............................................................................................... 3344
16-640. QUEUE_82_B Register ............................................................................................... 3345
16-641. QUEUE_82_C Register ............................................................................................... 3346
16-642. QUEUE_82_D Register ............................................................................................... 3347
16-643. QUEUE_83_A Register ............................................................................................... 3348
16-644. QUEUE_83_B Register ............................................................................................... 3349
16-645. QUEUE_83_C Register ............................................................................................... 3350
16-646. QUEUE_83_D Register ............................................................................................... 3351
16-647. QUEUE_84_A Register ............................................................................................... 3352
16-648. QUEUE_84_B Register ............................................................................................... 3353
16-649. QUEUE_84_C Register ............................................................................................... 3354
16-650. QUEUE_84_D Register ............................................................................................... 3355
16-651. QUEUE_85_A Register ............................................................................................... 3356
16-652. QUEUE_85_B Register ............................................................................................... 3357
16-653. QUEUE_85_C Register ............................................................................................... 3358
16-654. QUEUE_85_D Register ............................................................................................... 3359

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16-655. QUEUE_86_A Register ............................................................................................... 3360

16-656. QUEUE_86_B Register ............................................................................................... 3361
16-657. QUEUE_86_C Register ............................................................................................... 3362
16-658. QUEUE_86_D Register ............................................................................................... 3363
16-659. QUEUE_87_A Register ............................................................................................... 3364
16-660. QUEUE_87_B Register ............................................................................................... 3365
16-661. QUEUE_87_C Register ............................................................................................... 3366
16-662. QUEUE_87_D Register ............................................................................................... 3367
16-663. QUEUE_88_A Register ............................................................................................... 3368
16-664. QUEUE_88_B Register ............................................................................................... 3369
16-665. QUEUE_88_C Register ............................................................................................... 3370
16-666. QUEUE_88_D Register ............................................................................................... 3371
16-667. QUEUE_89_A Register ............................................................................................... 3372
16-668. QUEUE_89_B Register ............................................................................................... 3373
16-669. QUEUE_89_C Register ............................................................................................... 3374
16-670. QUEUE_89_D Register ............................................................................................... 3375
16-671. QUEUE_90_A Register ............................................................................................... 3376
16-672. QUEUE_90_B Register ............................................................................................... 3377
16-673. QUEUE_90_C Register ............................................................................................... 3378
16-674. QUEUE_90_D Register ............................................................................................... 3379
16-675. QUEUE_91_A Register ............................................................................................... 3380
16-676. QUEUE_91_B Register ............................................................................................... 3381
16-677. QUEUE_91_C Register ............................................................................................... 3382
16-678. QUEUE_91_D Register ............................................................................................... 3383
16-679. QUEUE_92_A Register ............................................................................................... 3384
16-680. QUEUE_92_B Register ............................................................................................... 3385
16-681. QUEUE_92_C Register ............................................................................................... 3386
16-682. QUEUE_92_D Register ............................................................................................... 3387
16-683. QUEUE_93_A Register ............................................................................................... 3388
16-684. QUEUE_93_B Register ............................................................................................... 3389
16-685. QUEUE_93_C Register ............................................................................................... 3390
16-686. QUEUE_93_D Register ............................................................................................... 3391
16-687. QUEUE_94_A Register ............................................................................................... 3392
16-688. QUEUE_94_B Register ............................................................................................... 3393
16-689. QUEUE_94_C Register ............................................................................................... 3394
16-690. QUEUE_94_D Register ............................................................................................... 3395
16-691. QUEUE_95_A Register ............................................................................................... 3396
16-692. QUEUE_95_B Register ............................................................................................... 3397
16-693. QUEUE_95_C Register ............................................................................................... 3398
16-694. QUEUE_95_D Register ............................................................................................... 3399
16-695. QUEUE_96_A Register ............................................................................................... 3400
16-696. QUEUE_96_B Register ............................................................................................... 3401
16-697. QUEUE_96_C Register ............................................................................................... 3402
16-698. QUEUE_96_D Register ............................................................................................... 3403
16-699. QUEUE_97_A Register ............................................................................................... 3404
16-700. QUEUE_97_B Register ............................................................................................... 3405
16-701. QUEUE_97_C Register ............................................................................................... 3406
16-702. QUEUE_97_D Register ............................................................................................... 3407
16-703. QUEUE_98_A Register ............................................................................................... 3408

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16-704. QUEUE_98_B Register ............................................................................................... 3409

16-705. QUEUE_98_C Register ............................................................................................... 3410
16-706. QUEUE_98_D Register ............................................................................................... 3411
16-707. QUEUE_99_A Register ............................................................................................... 3412
16-708. QUEUE_99_B Register ............................................................................................... 3413
16-709. QUEUE_99_C Register ............................................................................................... 3414
16-710. QUEUE_99_D Register ............................................................................................... 3415
16-711. QUEUE_100_A Register .............................................................................................. 3416
16-712. QUEUE_100_B Register .............................................................................................. 3417
16-713. QUEUE_100_C Register ............................................................................................. 3418
16-714. QUEUE_100_D Register ............................................................................................. 3419
16-715. QUEUE_101_A Register .............................................................................................. 3420
16-716. QUEUE_101_B Register .............................................................................................. 3421
16-717. QUEUE_101_C Register ............................................................................................. 3422
16-718. QUEUE_101_D Register ............................................................................................. 3423
16-719. QUEUE_102_A Register .............................................................................................. 3424
16-720. QUEUE_102_B Register .............................................................................................. 3425
16-721. QUEUE_102_C Register ............................................................................................. 3426
16-722. QUEUE_102_D Register ............................................................................................. 3427
16-723. QUEUE_103_A Register .............................................................................................. 3428
16-724. QUEUE_103_B Register .............................................................................................. 3429
16-725. QUEUE_103_C Register ............................................................................................. 3430
16-726. QUEUE_103_D Register ............................................................................................. 3431
16-727. QUEUE_104_A Register .............................................................................................. 3432
16-728. QUEUE_104_B Register .............................................................................................. 3433
16-729. QUEUE_104_C Register ............................................................................................. 3434
16-730. QUEUE_104_D Register ............................................................................................. 3435
16-731. QUEUE_105_A Register .............................................................................................. 3436
16-732. QUEUE_105_B Register .............................................................................................. 3437
16-733. QUEUE_105_C Register ............................................................................................. 3438
16-734. QUEUE_105_D Register ............................................................................................. 3439
16-735. QUEUE_106_A Register .............................................................................................. 3440
16-736. QUEUE_106_B Register .............................................................................................. 3441
16-737. QUEUE_106_C Register ............................................................................................. 3442
16-738. QUEUE_106_D Register ............................................................................................. 3443
16-739. QUEUE_107_A Register .............................................................................................. 3444
16-740. QUEUE_107_B Register .............................................................................................. 3445
16-741. QUEUE_107_C Register ............................................................................................. 3446
16-742. QUEUE_107_D Register ............................................................................................. 3447
16-743. QUEUE_108_A Register .............................................................................................. 3448
16-744. QUEUE_108_B Register .............................................................................................. 3449
16-745. QUEUE_108_C Register ............................................................................................. 3450
16-746. QUEUE_108_D Register ............................................................................................. 3451
16-747. QUEUE_109_A Register .............................................................................................. 3452
16-748. QUEUE_109_B Register .............................................................................................. 3453
16-749. QUEUE_109_C Register ............................................................................................. 3454
16-750. QUEUE_109_D Register ............................................................................................. 3455
16-751. QUEUE_110_A Register .............................................................................................. 3456
16-752. QUEUE_110_B Register .............................................................................................. 3457

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16-753. QUEUE_110_C Register ............................................................................................. 3458

16-754. QUEUE_110_D Register ............................................................................................. 3459
16-755. QUEUE_111_A Register .............................................................................................. 3460
16-756. QUEUE_111_B Register .............................................................................................. 3461
16-757. QUEUE_111_C Register ............................................................................................. 3462
16-758. QUEUE_111_D Register ............................................................................................. 3463
16-759. QUEUE_112_A Register .............................................................................................. 3464
16-760. QUEUE_112_B Register .............................................................................................. 3465
16-761. QUEUE_112_C Register ............................................................................................. 3466
16-762. QUEUE_112_D Register ............................................................................................. 3467
16-763. QUEUE_113_A Register .............................................................................................. 3468
16-764. QUEUE_113_B Register .............................................................................................. 3469
16-765. QUEUE_113_C Register ............................................................................................. 3470
16-766. QUEUE_113_D Register ............................................................................................. 3471
16-767. QUEUE_114_A Register .............................................................................................. 3472
16-768. QUEUE_114_B Register .............................................................................................. 3473
16-769. QUEUE_114_C Register ............................................................................................. 3474
16-770. QUEUE_114_D Register ............................................................................................. 3475
16-771. QUEUE_115_A Register .............................................................................................. 3476
16-772. QUEUE_115_B Register .............................................................................................. 3477
16-773. QUEUE_115_C Register ............................................................................................. 3478
16-774. QUEUE_115_D Register ............................................................................................. 3479
16-775. QUEUE_116_A Register .............................................................................................. 3480
16-776. QUEUE_116_B Register .............................................................................................. 3481
16-777. QUEUE_116_C Register ............................................................................................. 3482
16-778. QUEUE_116_D Register ............................................................................................. 3483
16-779. QUEUE_117_A Register .............................................................................................. 3484
16-780. QUEUE_117_B Register .............................................................................................. 3485
16-781. QUEUE_117_C Register ............................................................................................. 3486
16-782. QUEUE_117_D Register ............................................................................................. 3487
16-783. QUEUE_118_A Register .............................................................................................. 3488
16-784. QUEUE_118_B Register .............................................................................................. 3489
16-785. QUEUE_118_C Register ............................................................................................. 3490
16-786. QUEUE_118_D Register ............................................................................................. 3491
16-787. QUEUE_119_A Register .............................................................................................. 3492
16-788. QUEUE_119_B Register .............................................................................................. 3493
16-789. QUEUE_119_C Register ............................................................................................. 3494
16-790. QUEUE_119_D Register ............................................................................................. 3495
16-791. QUEUE_120_A Register .............................................................................................. 3496
16-792. QUEUE_120_B Register .............................................................................................. 3497
16-793. QUEUE_120_C Register ............................................................................................. 3498
16-794. QUEUE_120_D Register ............................................................................................. 3499
16-795. QUEUE_121_A Register .............................................................................................. 3500
16-796. QUEUE_121_B Register .............................................................................................. 3501
16-797. QUEUE_121_C Register ............................................................................................. 3502
16-798. QUEUE_121_D Register ............................................................................................. 3503
16-799. QUEUE_122_A Register .............................................................................................. 3504
16-800. QUEUE_122_B Register .............................................................................................. 3505
16-801. QUEUE_122_C Register ............................................................................................. 3506

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16-802. QUEUE_122_D Register ............................................................................................. 3507

16-803. QUEUE_123_A Register .............................................................................................. 3508
16-804. QUEUE_123_B Register .............................................................................................. 3509
16-805. QUEUE_123_C Register ............................................................................................. 3510
16-806. QUEUE_123_D Register ............................................................................................. 3511
16-807. QUEUE_124_A Register .............................................................................................. 3512
16-808. QUEUE_124_B Register .............................................................................................. 3513
16-809. QUEUE_124_C Register ............................................................................................. 3514
16-810. QUEUE_124_D Register ............................................................................................. 3515
16-811. QUEUE_125_A Register .............................................................................................. 3516
16-812. QUEUE_125_B Register .............................................................................................. 3517
16-813. QUEUE_125_C Register ............................................................................................. 3518
16-814. QUEUE_125_D Register ............................................................................................. 3519
16-815. QUEUE_126_A Register .............................................................................................. 3520
16-816. QUEUE_126_B Register .............................................................................................. 3521
16-817. QUEUE_126_C Register ............................................................................................. 3522
16-818. QUEUE_126_D Register ............................................................................................. 3523
16-819. QUEUE_127_A Register .............................................................................................. 3524
16-820. QUEUE_127_B Register .............................................................................................. 3525
16-821. QUEUE_127_C Register ............................................................................................. 3526
16-822. QUEUE_127_D Register ............................................................................................. 3527
16-823. QUEUE_128_A Register .............................................................................................. 3528
16-824. QUEUE_128_B Register .............................................................................................. 3529
16-825. QUEUE_128_C Register ............................................................................................. 3530
16-826. QUEUE_128_D Register ............................................................................................. 3531
16-827. QUEUE_129_A Register .............................................................................................. 3532
16-828. QUEUE_129_B Register .............................................................................................. 3533
16-829. QUEUE_129_C Register ............................................................................................. 3534
16-830. QUEUE_129_D Register ............................................................................................. 3535
16-831. QUEUE_130_A Register .............................................................................................. 3536
16-832. QUEUE_130_B Register .............................................................................................. 3537
16-833. QUEUE_130_C Register ............................................................................................. 3538
16-834. QUEUE_130_D Register ............................................................................................. 3539
16-835. QUEUE_131_A Register .............................................................................................. 3540
16-836. QUEUE_131_B Register .............................................................................................. 3541
16-837. QUEUE_131_C Register ............................................................................................. 3542
16-838. QUEUE_131_D Register ............................................................................................. 3543
16-839. QUEUE_132_A Register .............................................................................................. 3544
16-840. QUEUE_132_B Register .............................................................................................. 3545
16-841. QUEUE_132_C Register ............................................................................................. 3546
16-842. QUEUE_132_D Register ............................................................................................. 3547
16-843. QUEUE_133_A Register .............................................................................................. 3548
16-844. QUEUE_133_B Register .............................................................................................. 3549
16-845. QUEUE_133_C Register ............................................................................................. 3550
16-846. QUEUE_133_D Register ............................................................................................. 3551
16-847. QUEUE_134_A Register .............................................................................................. 3552
16-848. QUEUE_134_B Register .............................................................................................. 3553
16-849. QUEUE_134_C Register ............................................................................................. 3554
16-850. QUEUE_134_D Register ............................................................................................. 3555

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16-851. QUEUE_135_A Register .............................................................................................. 3556

16-852. QUEUE_135_B Register .............................................................................................. 3557
16-853. QUEUE_135_C Register ............................................................................................. 3558
16-854. QUEUE_135_D Register ............................................................................................. 3559
16-855. QUEUE_136_A Register .............................................................................................. 3560
16-856. QUEUE_136_B Register .............................................................................................. 3561
16-857. QUEUE_136_C Register ............................................................................................. 3562
16-858. QUEUE_136_D Register ............................................................................................. 3563
16-859. QUEUE_137_A Register .............................................................................................. 3564
16-860. QUEUE_137_B Register .............................................................................................. 3565
16-861. QUEUE_137_C Register ............................................................................................. 3566
16-862. QUEUE_137_D Register ............................................................................................. 3567
16-863. QUEUE_138_A Register .............................................................................................. 3568
16-864. QUEUE_138_B Register .............................................................................................. 3569
16-865. QUEUE_138_C Register ............................................................................................. 3570
16-866. QUEUE_138_D Register ............................................................................................. 3571
16-867. QUEUE_139_A Register .............................................................................................. 3572
16-868. QUEUE_139_B Register .............................................................................................. 3573
16-869. QUEUE_139_C Register ............................................................................................. 3574
16-870. QUEUE_139_D Register ............................................................................................. 3575
16-871. QUEUE_140_A Register .............................................................................................. 3576
16-872. QUEUE_140_B Register .............................................................................................. 3577
16-873. QUEUE_140_C Register ............................................................................................. 3578
16-874. QUEUE_140_D Register ............................................................................................. 3579
16-875. QUEUE_141_A Register .............................................................................................. 3580
16-876. QUEUE_141_B Register .............................................................................................. 3581
16-877. QUEUE_141_C Register ............................................................................................. 3582
16-878. QUEUE_141_D Register ............................................................................................. 3583
16-879. QUEUE_142_A Register .............................................................................................. 3584
16-880. QUEUE_142_B Register .............................................................................................. 3585
16-881. QUEUE_142_C Register ............................................................................................. 3586
16-882. QUEUE_142_D Register ............................................................................................. 3587
16-883. QUEUE_143_A Register .............................................................................................. 3588
16-884. QUEUE_143_B Register .............................................................................................. 3589
16-885. QUEUE_143_C Register ............................................................................................. 3590
16-886. QUEUE_143_D Register ............................................................................................. 3591
16-887. QUEUE_144_A Register .............................................................................................. 3592
16-888. QUEUE_144_B Register .............................................................................................. 3593
16-889. QUEUE_144_C Register ............................................................................................. 3594
16-890. QUEUE_144_D Register ............................................................................................. 3595
16-891. QUEUE_145_A Register .............................................................................................. 3596
16-892. QUEUE_145_B Register .............................................................................................. 3597
16-893. QUEUE_145_C Register ............................................................................................. 3598
16-894. QUEUE_145_D Register ............................................................................................. 3599
16-895. QUEUE_146_A Register .............................................................................................. 3600
16-896. QUEUE_146_B Register .............................................................................................. 3601
16-897. QUEUE_146_C Register ............................................................................................. 3602
16-898. QUEUE_146_D Register ............................................................................................. 3603
16-899. QUEUE_147_A Register .............................................................................................. 3604

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16-900. QUEUE_147_B Register .............................................................................................. 3605

16-901. QUEUE_147_C Register ............................................................................................. 3606
16-902. QUEUE_147_D Register ............................................................................................. 3607
16-903. QUEUE_148_A Register .............................................................................................. 3608
16-904. QUEUE_148_B Register .............................................................................................. 3609
16-905. QUEUE_148_C Register ............................................................................................. 3610
16-906. QUEUE_148_D Register ............................................................................................. 3611
16-907. QUEUE_149_A Register .............................................................................................. 3612
16-908. QUEUE_149_B Register .............................................................................................. 3613
16-909. QUEUE_149_C Register ............................................................................................. 3614
16-910. QUEUE_149_D Register ............................................................................................. 3615
16-911. QUEUE_150_A Register .............................................................................................. 3616
16-912. QUEUE_150_B Register .............................................................................................. 3617
16-913. QUEUE_150_C Register ............................................................................................. 3618
16-914. QUEUE_150_D Register ............................................................................................. 3619
16-915. QUEUE_151_A Register .............................................................................................. 3620
16-916. QUEUE_151_B Register .............................................................................................. 3621
16-917. QUEUE_151_C Register ............................................................................................. 3622
16-918. QUEUE_151_D Register ............................................................................................. 3623
16-919. QUEUE_152_A Register .............................................................................................. 3624
16-920. QUEUE_152_B Register .............................................................................................. 3625
16-921. QUEUE_152_C Register ............................................................................................. 3626
16-922. QUEUE_152_D Register ............................................................................................. 3627
16-923. QUEUE_153_A Register .............................................................................................. 3628
16-924. QUEUE_153_B Register .............................................................................................. 3629
16-925. QUEUE_153_C Register ............................................................................................. 3630
16-926. QUEUE_153_D Register ............................................................................................. 3631
16-927. QUEUE_154_A Register .............................................................................................. 3632
16-928. QUEUE_154_B Register .............................................................................................. 3633
16-929. QUEUE_154_C Register ............................................................................................. 3634
16-930. QUEUE_154_D Register ............................................................................................. 3635
16-931. QUEUE_155_A Register .............................................................................................. 3636
16-932. QUEUE_155_B Register .............................................................................................. 3637
16-933. QUEUE_155_C Register ............................................................................................. 3638
16-934. QUEUE_155_D Register ............................................................................................. 3639
16-935. QUEUE_0_STATUS_A Register .................................................................................... 3640
16-936. QUEUE_0_STATUS_B Register .................................................................................... 3641
16-937. QUEUE_0_STATUS_C Register .................................................................................... 3642

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16-965. QUEUE_10_STATUS_A Register ................................................................................... 3670
16-966. QUEUE_10_STATUS_B Register ................................................................................... 3671
16-967. QUEUE_10_STATUS_C Register ................................................................................... 3672

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16-1000. QUEUE_21_STATUS_C Register ................................................................................. 3705
16-1001. QUEUE_22_STATUS_A Register ................................................................................. 3706
16-1002. QUEUE_22_STATUS_B Register ................................................................................. 3707

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16-1235. QUEUE_100_STATUS_A Register ................................................................................ 3940
16-1236. QUEUE_100_STATUS_B Register ................................................................................ 3941
16-1237. QUEUE_100_STATUS_C Register ................................................................................ 3942

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17-1. Mailbox Block Diagram ................................................................................................. 4112
17-2. REVISION Register ..................................................................................................... 4121
17-4. MESSAGE_0 Register.................................................................................................. 4123
17-12. FIFOSTATUS_0 Register .............................................................................................. 4131
17-20. MSGSTATUS_0 Register .............................................................................................. 4139
17-28. IRQSTATUS_RAW_0 Register ........................................................................................ 4147
17-29. IRQSTATUS_CLR_0 Register......................................................................................... 4149
17-30. IRQENABLE_SET_0 Register ......................................................................................... 4151
17-31. IRQENABLE_CLR_0 Register......................................................................................... 4153

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17-44. REV Register ............................................................................................................ 4182
17-46. SYSTATUS Register .................................................................................................... 4184
17-47. LOCK_REG_0 Register ................................................................................................ 4185
17-57. LOCK_REG_10 Register ............................................................................................... 4195
18-1. MMCHS Module SDIO Application.................................................................................... 4219
18-2. MMCHS SD (4-bit) Card Application.................................................................................. 4219
18-3. MMCHS Module MMC Application .................................................................................... 4220
18-4. MMC/SD1/2 Connectivity to an MMC/SD Card ..................................................................... 4223
18-5. MMC/SD0 Connectivity to an MMC/SD Card........................................................................ 4223
18-6. Sequential Read Operation (MMC Cards Only) ..................................................................... 4225
18-7. Sequential Write Operation (MMC Cards Only) ..................................................................... 4225

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18-8. Multiple Block Read Operation (MMC Cards Only) ................................................................ 4226
18-9. Multiple Block Write Operation (MMC Cards Only) ................................................................ 4226
18-10. Command Token Format ............................................................................................... 4227
18-11. 48-Bit Response Packet (R1, R3, R4, R5, R6) ...................................................................... 4227
18-12. 136-Bit Response Packet (R2) ........................................................................................ 4227
18-13. Data Packet for Sequential Transfer (1-Bit) ......................................................................... 4228
18-14. Data Packet for Block Transfer (1-Bit) ............................................................................... 4228
18-15. Data Packet for Block Transfer (4-Bit) ................................................................................ 4228
18-16. Data Packet for Block Transfer (8-Bit) ................................................................................ 4229
18-17. DMA Receive Mode ..................................................................................................... 4236
18-18. DMA Transmit Mode .................................................................................................... 4237
18-19. Buffer Management for a Write ........................................................................................ 4239
18-20. Buffer Management for a Read ....................................................................................... 4240
18-21. Busy Timeout for R1b, R5b Responses .............................................................................. 4243
18-22. Write CRC Status Timeout ............................................................................................. 4244
18-23. Read Data Timeout ..................................................................................................... 4244
18-24. Boot Acknowledge Timeout When Using CMD0 .................................................................... 4245
18-25. Boot Acknowledge Timeout When CMD Held Low ................................................................. 4245
18-26. Auto CMD12 Timing During Write Transfer .......................................................................... 4247
18-27. Auto Command 12 Timings During Read Transfer ................................................................. 4248
18-28. Output Driven on Falling Edge ........................................................................................ 4250
18-29. Output Driven on Rising Edge ......................................................................................... 4251
18-30. Boot Mode With CMD0 ................................................................................................. 4252
18-31. Boot Mode With CMD Line Tied to 0 ................................................................................. 4253
18-32. MMC/SD/SDIO Controller Software Reset Flow .................................................................... 4257
18-33. MMC/SD/SDIO Controller Bus Configuration Flow ................................................................. 4258
18-34. MMC/SD/SDIO Controller Card Identification and Selection - Part 1 ............................................ 4259
18-35. MMC/SD/SDIO Controller Card Identification and Selection - Part 2 ............................................ 4260
18-36. SD_SYSCONFIG Register ............................................................................................. 4262
18-37. SD_SYSSTATUS Register ............................................................................................. 4264
18-38. SD_CSRE Register ..................................................................................................... 4265
18-39. SD_SYSTEST Register ................................................................................................ 4266
18-40. SD_CON Register ....................................................................................................... 4270
18-41. SD_PWCNT Register ................................................................................................... 4274
18-42. SD_SDMASA Register ................................................................................................. 4275
18-43. SD_BLK Register........................................................................................................ 4276
18-44. SD_ARG Register ....................................................................................................... 4277
18-45. SD_CMD Register....................................................................................................... 4278
18-46. SD_RSP10 Register .................................................................................................... 4283
18-47. SD_RSP32 Register .................................................................................................... 4284
18-48. SD_RSP54 Register .................................................................................................... 4285
18-49. SD_RSP76 Register .................................................................................................... 4286
18-50. SD_DATA Register ..................................................................................................... 4287
18-51. SD_PSTATE Register .................................................................................................. 4288
18-52. SD_HCTL Register ...................................................................................................... 4291
18-53. SD_SYSCTL Register .................................................................................................. 4294
18-54. SD_STAT Register ...................................................................................................... 4296
18-55. SD_IE Register .......................................................................................................... 4301
18-56. SD_ISE Register ........................................................................................................ 4304

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18-57. SD_AC12 Register ...................................................................................................... 4307

18-58. SD_CAPA Register ..................................................................................................... 4309
18-59. SD_CUR_CAPA Register .............................................................................................. 4311
18-60. SD_FE Register ......................................................................................................... 4312
18-61. SD_ADMAES Register ................................................................................................. 4314
18-62. SD_ADMASAL Register ................................................................................................ 4315
18-63. SD_ADMASAH Register ............................................................................................... 4316
18-64. SD_REV Register ....................................................................................................... 4317
19-1. UART/IrDA Module — UART Application ............................................................................ 4321
19-2. UART/IrDA Module — IrDA/CIR Application......................................................................... 4321
19-3. UART/IrDA/CIR Functional Specification Block Diagram .......................................................... 4326
19-4. FIFO Management Registers .......................................................................................... 4331
19-5. RX FIFO Interrupt Request Generation .............................................................................. 4333
19-6. ..............................................................................
TX FIFO Interrupt Request Generation 4334
19-7. Receive FIFO DMA Request Generation (32 Characters) ......................................................... 4335
19-8. Transmit FIFO DMA Request Generation (56 Spaces) ............................................................ 4335
19-9. Transmit FIFO DMA Request Generation (8 Spaces).............................................................. 4336
19-10. Transmit FIFO DMA Request Generation (1 Space) ............................................................... 4337
19-11. Transmit FIFO DMA Request Generation Using Direct TX DMA Threshold Programming. (Threshold = 3;
Spaces = 8) .............................................................................................................. 4338
19-12. DMA Transmission ...................................................................................................... 4338
19-13. DMA Reception .......................................................................................................... 4339
19-14. UART Data Format...................................................................................................... 4346
19-15. Baud Rate Generation .................................................................................................. 4346
19-16. IrDA SIR Frame Format ................................................................................................ 4352
19-17. IrDA Encoding Mechanism ............................................................................................. 4353
19-18. IrDA Decoding Mechanism............................................................................................. 4354
19-19. SIR Free Format Mode ................................................................................................. 4354
19-20. MIR Transmit Frame Format........................................................................................... 4355
19-21. MIR BAUD Rate Adjustment Mechanism ............................................................................ 4356
19-22. SIP Pulse ................................................................................................................. 4356
19-23. FIR Transmit Frame Format ........................................................................................... 4356
19-24. Baud Rate Generator ................................................................................................... 4357
19-25. RC-5 Bit Encoding ...................................................................................................... 4361
19-26. SIRC Bit Encoding ...................................................................................................... 4361
19-27. RC-5 Standard Packet Format ........................................................................................ 4362
19-28. SIRC Packet Format .................................................................................................... 4362
19-29. SIRC Bit Transmission Example ...................................................................................... 4362
19-30. CIR Mode Block Components ......................................................................................... 4363
19-31. CIR Pulse Modulation................................................................................................... 4365
19-32. CIR Modulation Duty Cycle ............................................................................................ 4365
19-33. Variable Pulse Duration Definitions ................................................................................... 4367
19-34. THR Register ............................................................................................................ 4379
19-35. RHR Register ............................................................................................................ 4380
19-36. DLL Register ............................................................................................................. 4381
19-37. IER_IRDA Register ..................................................................................................... 4382
19-38. IER_CIR Register ....................................................................................................... 4383
19-39. IER_UART Register..................................................................................................... 4384
19-40. DLH Register............................................................................................................. 4385

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19-41. EFR Register............................................................................................................. 4386

19-42. IIR_UART Register ...................................................................................................... 4388
19-43. IIR_CIR Register ........................................................................................................ 4389
19-44. FCR Register ............................................................................................................ 4390
19-45. IIR_IRDA Register....................................................................................................... 4391
19-46. LCR Register............................................................................................................. 4392
19-47. MCR Register ............................................................................................................ 4393
19-48. XON1_ADDR1 Register ................................................................................................ 4394
19-49. XON2_ADDR2 Register ................................................................................................ 4395
19-50. LSR_CIR Register....................................................................................................... 4396
19-51. LSR_IRDA Register ..................................................................................................... 4397
19-52. LSR_UART Register .................................................................................................... 4399
19-53. TCR Register ............................................................................................................ 4401
19-54. MSR Register ............................................................................................................ 4402
19-55. XOFF1 Register ......................................................................................................... 4403
19-56. SPR Register ............................................................................................................ 4404
19-57. TLR Register ............................................................................................................. 4405
19-58. XOFF2 Register ......................................................................................................... 4406
19-59. MDR1 Register .......................................................................................................... 4407
19-60. MDR2 Register .......................................................................................................... 4408
19-61. TXFLL Register .......................................................................................................... 4409
19-62. SFLSR Register ......................................................................................................... 4410
19-63. RESUME Register ...................................................................................................... 4411
19-64. TXFLH Register ......................................................................................................... 4412
19-65. RXFLL Register.......................................................................................................... 4413
19-66. SFREGL Register ....................................................................................................... 4414
19-67. SFREGH Register ....................................................................................................... 4415
19-68. RXFLH Register ......................................................................................................... 4416
19-69. BLR Register ............................................................................................................. 4417
19-70. UASR Register .......................................................................................................... 4418
19-71. ACREG Register ........................................................................................................ 4419
19-72. SCR Register ............................................................................................................ 4420
19-73. SSR Register ............................................................................................................ 4421
19-74. EBLR Register ........................................................................................................... 4422
19-75. MVR Register ............................................................................................................ 4423
19-76. SYSC Register........................................................................................................... 4424
19-77. SYSS Register ........................................................................................................... 4425
19-78. WER Register ............................................................................................................ 4426
19-79. CFPS Register ........................................................................................................... 4427
19-80. RXFIFO_LVL Register .................................................................................................. 4428
19-81. TXFIFO_LVL Register .................................................................................................. 4429
19-82. IER2 Register ............................................................................................................ 4430
19-83. ISR2 Register ............................................................................................................ 4431
19-84. FREQ_SEL Register .................................................................................................... 4432
19-85. MDR3 Register .......................................................................................................... 4433
19-86. TX_DMA_THRESHOLD Register ..................................................................................... 4434
20-1. Timer Block Diagram ................................................................................................... 4437
20-2. Timer0 Integration ....................................................................................................... 4438
20-3. Timer2-7 Integration .................................................................................................... 4439

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20-4. TCRR Timing Value ..................................................................................................... 4442

20-5. Capture Wave Example for CAPT_MODE = 0 ...................................................................... 4443
20-6. Capture Wave Example for CAPT_MODE = 1 ...................................................................... 4444
20-7. Timing Diagram of Pulse-Width Modulation with SCPWM = 0 .................................................... 4445
20-8. Timing Diagram of Pulse-Width Modulation with SCPWM = 1 .................................................... 4446
20-9. TIDR Register ............................................................................................................ 4452
20-10. TIOCP_CFG Register .................................................................................................. 4453
20-11. IRQ_EOI Register ....................................................................................................... 4454
20-15. IRQENABLE_CLR Register............................................................................................ 4458
20-16. IRQWAKEEN Register ................................................................................................. 4459
20-17. TCLR Register ........................................................................................................... 4460
20-18. TCRR Register .......................................................................................................... 4462
20-19. TLDR Register ........................................................................................................... 4463
20-20. TTGR Register........................................................................................................... 4464
20-21. TWPS Register .......................................................................................................... 4465
20-22. TMAR Register .......................................................................................................... 4466
20-23. TCAR1 Register ......................................................................................................... 4467
20-24. TSICR Register .......................................................................................................... 4468
20-25. TCAR2 Register ......................................................................................................... 4469
20-26. Block Diagram ........................................................................................................... 4471
20-27. DMTimer 1 ms Integration ............................................................................................. 4472
20-28. TCRR Timing Value ..................................................................................................... 4474
20-29. 1ms Module Block Diagram ............................................................................................ 4475
20-30. Capture Wave Example for CAPT_MODE 0 ........................................................................ 4477
20-31. Capture Wave Example for CAPT_MODE 1 ........................................................................ 4477
20-32. Timing Diagram of Pulse-Width Modulation, SCPWM Bit = 0 ..................................................... 4479
20-33. Timing Diagram of Pulse-Width Modulation, SCPWM Bit = 1 ..................................................... 4479
20-34. Wake-up Request Generation ......................................................................................... 4481
20-35. TIDR Register ............................................................................................................ 4484
20-36. TIOCP_CFG Register .................................................................................................. 4485
20-37. TISTAT Register ......................................................................................................... 4486
20-38. TISR Register ............................................................................................................ 4487
20-39. TIER Register ............................................................................................................ 4488
20-40. TWER Register .......................................................................................................... 4489
20-41. TCLR Register ........................................................................................................... 4490
20-42. TCRR Register .......................................................................................................... 4492
20-43. TLDR Register ........................................................................................................... 4493
20-44. TTGR Register........................................................................................................... 4494
20-45. TWPS Register .......................................................................................................... 4495
20-46. TMAR Register .......................................................................................................... 4497
20-47. TCAR1 Register ......................................................................................................... 4498
20-48. TSICR Register .......................................................................................................... 4499
20-49. TCAR2 Register ......................................................................................................... 4500
20-50. TPIR Register ............................................................................................................ 4501
20-51. TNIR Register ............................................................................................................ 4502
20-52. TCVR Register........................................................................................................... 4503

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20-53. TOCR Register .......................................................................................................... 4504

20-54. TOWR Register .......................................................................................................... 4505
20-55. RTC Integration .......................................................................................................... 4507
20-56. RTC Block Diagram ..................................................................................................... 4509
20-57. RTC Functional Block Diagram........................................................................................ 4509
20-58. Kick Register State Machine Diagram ................................................................................ 4512
20-59. Flow Control for Updating RTC Registers ........................................................................... 4514
20-60. Compensation Illustration .............................................................................................. 4515
20-61. SECONDS_REG Register ............................................................................................. 4519
20-62. MINUTES_REG Register .............................................................................................. 4520
20-63. HOURS_REG Register ................................................................................................. 4521
20-64. DAYS_REG Register ................................................................................................... 4522
20-65. MONTHS_REG Register ............................................................................................... 4523
20-66. YEARS_REG Register ................................................................................................. 4524
20-67. WEEKS_REG Register ................................................................................................. 4525
20-68. ALARM_SECONDS_REG Register .................................................................................. 4526
20-69. ALARM_MINUTES_REG Register .................................................................................... 4527
20-70. ALARM_HOURS_REG Register ...................................................................................... 4528
20-71. ALARM_DAYS_REG Register ........................................................................................ 4529
20-72. ALARM_MONTHS_REG Register .................................................................................... 4530
20-73. ALARM_YEARS_REG Register ....................................................................................... 4531
20-74. RTC_CTRL_REG Register ............................................................................................ 4532
20-75. RTC_STATUS_REG Register ......................................................................................... 4534
20-76. RTC_INTERRUPTS_REG Register .................................................................................. 4535
20-77. RTC_COMP_LSB_REG Register ..................................................................................... 4536
20-78. RTC_COMP_MSB_REG Register .................................................................................... 4537
20-79. RTC_OSC_REG Register .............................................................................................. 4538
20-80. RTC_SCRATCH0_REG Register ..................................................................................... 4539
20-83. KICK0R Register ........................................................................................................ 4542
20-84. KICK1R Register ........................................................................................................ 4543
20-85. RTC_REVISION Register .............................................................................................. 4544
20-86. RTC_SYSCONFIG Register ........................................................................................... 4545
20-87. RTC_IRQWAKEEN Register .......................................................................................... 4546
20-88. ALARM2_SECONDS_REG Register ................................................................................. 4547
20-89. ALARM2_MINUTES_REG Register .................................................................................. 4548
20-90. ALARM2_HOURS_REG Register..................................................................................... 4549
20-91. ALARM2_DAYS_REG Register ....................................................................................... 4550
20-92. ALARM2_MONTHS_REG Register................................................................................... 4551
20-93. ALARM2_YEARS_REG Register ..................................................................................... 4552
20-94. RTC_PMIC Register .................................................................................................... 4553
20-95. RTC_DEBOUNCE Register............................................................................................ 4554
20-96. WDTimer Integration .................................................................................................... 4556
20-97. 32-Bit Watchdog Timer Functional Block Diagram ................................................................. 4558
20-98. Watchdog Timers General Functional View ......................................................................... 4559
20-99. WDT_WIDR Register ................................................................................................... 4567
20-100. WDT_WDSC Register ................................................................................................. 4568
20-101. WDT_WDST Register ................................................................................................. 4569

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20-102. WDT_WISR Register .................................................................................................. 4570

20-103. WDT_WIER Register .................................................................................................. 4571
20-104. WDT_WCLR Register ................................................................................................. 4572
20-105. WDT_WCRR Register ................................................................................................ 4573
20-106. WDT_WLDR Register ................................................................................................. 4574
20-107. WDT_WTGR Register ................................................................................................. 4575
20-108. WDT_WWPS Register ................................................................................................ 4576
20-109. WDT_WDLY Register ................................................................................................. 4577
20-110. WDT_WSPR Register ................................................................................................. 4578
20-111. WDT_WIRQSTATRAW Register .................................................................................... 4579
20-112. WDT_WIRQSTAT Register ........................................................................................... 4580
20-113. WDT_WIRQENSET Register......................................................................................... 4581
20-114. WDT_WIRQENCLR Register ........................................................................................ 4582
21-1. I2C0 Integration and Bus Application ................................................................................. 4585
21-2. I2C(1–2) Integration and Bus Application ............................................................................ 4585
21-3. I2C Functional Block Diagram ......................................................................................... 4587
21-4. Multiple I2C Modules Connected ...................................................................................... 4588
21-5. Bit Transfer on the I2C Bus ............................................................................................ 4589
21-6. Start and Stop Condition Events ...................................................................................... 4590
21-7. I2C Data Transfer ....................................................................................................... 4590
21-8. I2C Data Transfer Formats............................................................................................. 4591
21-9. Arbitration Procedure Between Two Master Transmitters ......................................................... 4592
21-10. Synchronization of Two I2C Clock Generators ...................................................................... 4593
21-11. Receive FIFO Interrupt Request Generation ........................................................................ 4595
21-12. Transmit FIFO Interrupt Request Generation ....................................................................... 4595
21-13. Receive FIFO DMA Request Generation ............................................................................ 4596
21-14. Transmit FIFO DMA Request Generation (High Threshold)....................................................... 4597
21-15. Transmit FIFO DMA Request Generation (Low Threshold) ....................................................... 4597
21-16. I2C_REVNB_LO Register .............................................................................................. 4602
21-17. I2C_REVNB_HI Register ............................................................................................... 4603
21-18. I2C_SYSC Register ..................................................................................................... 4604
21-19. I2C_IRQSTATUS_RAW Register ..................................................................................... 4606
21-20. I2C_IRQSTATUS Register ............................................................................................. 4612
21-21. I2C_IRQENABLE_SET Register ...................................................................................... 4614
21-22. I2C_IRQENABLE_CLR Register ...................................................................................... 4616
21-23. I2C_WE Register ........................................................................................................ 4618
21-24. I2C_DMARXENABLE_SET Register ................................................................................. 4621
21-25. I2C_DMATXENABLE_SET Register ................................................................................. 4622
21-26. I2C_DMARXENABLE_CLR Register ................................................................................. 4623
21-27. I2C_DMATXENABLE_CLR Register ................................................................................. 4624
21-28. I2C_DMARXWAKE_EN Register ..................................................................................... 4625
21-29. I2C_DMATXWAKE_EN Register...................................................................................... 4627
21-30. I2C_SYSS Register ..................................................................................................... 4629
21-31. I2C_BUF Register ....................................................................................................... 4630
21-32. I2C_CNT Register ....................................................................................................... 4632
21-33. I2C_DATA Register ..................................................................................................... 4633
21-34. I2C_CON Register ...................................................................................................... 4634
21-35. I2C_OA Register ........................................................................................................ 4637
21-36. I2C_SA Register ......................................................................................................... 4638

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21-37. I2C_PSC Register ....................................................................................................... 4639

21-38. I2C_SCLL Register ..................................................................................................... 4640
21-39. I2C_SCLH Register ..................................................................................................... 4641
21-40. I2C_SYSTEST Register ................................................................................................ 4642
21-41. I2C_BUFSTAT Register ................................................................................................ 4645
21-42. I2C_OA1 Register ....................................................................................................... 4646
21-43. I2C_OA2 Register ....................................................................................................... 4647
21-44. I2C_OA3 Register ....................................................................................................... 4648
21-45. I2C_ACTOA Register ................................................................................................... 4649
21-46. I2C_SBLOCK Register ................................................................................................. 4650
22-1. McASP0–1 Integration .................................................................................................. 4655
22-2. McASP Block Diagram ................................................................................................. 4658
22-3. McASP to Parallel 2-Channel DACs .................................................................................. 4659
22-4. McASP to 6-Channel DAC and 2-Channel DAC .................................................................... 4659
22-5. McASP to Digital Amplifier ............................................................................................. 4660
22-6. McASP as Digital Audio Encoder ..................................................................................... 4660
22-7. McASP as 16 Channel Digital Processor ............................................................................ 4660
22-8. TDM Format–6 Channel TDM Example .............................................................................. 4661
22-9. TDM Format Bit Delays from Frame Sync ........................................................................... 4662
22-10. Inter-Integrated Sound (I2S) Format .................................................................................. 4662
22-11. Biphase-Mark Code (BMC) ............................................................................................ 4663
22-12. S/PDIF Subframe Format .............................................................................................. 4664
22-13. S/PDIF Frame Format .................................................................................................. 4665
22-14. Definition of Bit, Word, and Slot ....................................................................................... 4666
22-15. Bit Order and Word Alignment Within a Slot Examples ............................................................ 4666
22-16. Definition of Frame and Frame Sync Width ......................................................................... 4667
22-17. Transmit Clock Generator Block Diagram ........................................................................... 4668
22-18. Receive Clock Generator Block Diagram ............................................................................ 4669
22-19. Frame Sync Generator Block Diagram ............................................................................... 4670
22-20. Burst Frame Sync Mode................................................................................................ 4672
22-21. Transmit DMA Event (AXEVT) Generation in TDM Time Slots ................................................... 4674
22-22. Individual Serializer and Connections Within McASP .............................................................. 4679
22-23. Receive Format Unit .................................................................................................... 4680
22-24. Transmit Format Unit ................................................................................................... 4680
22-25. McASP I/O Pin Control Block Diagram ............................................................................... 4682
22-26. Processor Service Time Upon Transmit DMA Event (AXEVT) ................................................... 4684
22-27. Processor Service Time Upon Receive DMA Event (AREVT) .................................................... 4685
22-28. McASP Audio FIFO (AFIFO) Block Diagram ........................................................................ 4687
22-29. Data Flow Through Transmit Format Unit, Illustrated .............................................................. 4690
22-30. Data Flow Through Receive Format Unit, Illustrated ............................................................... 4692
22-31. Transmit Clock Failure Detection Circuit Block Diagram ........................................................... 4696
22-32. Receive Clock Failure Detection Circuit Block Diagram ........................................................... 4698
22-33. Serializers in Loopback Mode ......................................................................................... 4699
22-34. Interrupt Multiplexing .................................................................................................... 4705
22-35. Audio Mute (AMUTE) Block Diagram ................................................................................. 4706
22-36. DMA Events in an Audio Example–Two Events (Scenario 1) ..................................................... 4708
22-37. DMA Events in an Audio Example–Four Events (Scenario 2) .................................................... 4708
22-38. DMA Events in an Audio Example .................................................................................... 4709
22-39. REV Register ............................................................................................................ 4712

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22-40. PWRIDLESYSCONFIG Register ...................................................................................... 4713

22-41. PFUNC Register ......................................................................................................... 4714
22-42. PDIR Register ........................................................................................................... 4715
22-43. PDOUT Register ........................................................................................................ 4717
22-44. PDIN Register ........................................................................................................... 4719
22-45. PDCLR Register ......................................................................................................... 4720
22-46. GBLCTL Register ....................................................................................................... 4722
22-47. AMUTE Register ........................................................................................................ 4724
22-48. DLBCTL Register........................................................................................................ 4726
22-49. DITCTL Register ........................................................................................................ 4727
22-50. RGBLCTL Register ..................................................................................................... 4728
22-51. RMASK Register ........................................................................................................ 4730
22-52. RFMT Register .......................................................................................................... 4731
22-53. AFSRCTL Register ...................................................................................................... 4733
22-54. ACLKRCTL Register .................................................................................................... 4734
22-55. AHCLKRCTL Register .................................................................................................. 4735
22-56. RTDM Register .......................................................................................................... 4736
22-57. RINTCTL Register....................................................................................................... 4737
22-58. RSTAT Register ......................................................................................................... 4739
22-59. RSLOT Register ......................................................................................................... 4741
22-60. RCLKCHK Register ..................................................................................................... 4742
22-61. REVTCTL Register ...................................................................................................... 4743
22-62. XGBLCTL Register ...................................................................................................... 4744
22-63. XMASK Register ........................................................................................................ 4746
22-64. XFMT Register........................................................................................................... 4747
22-65. AFSXCTL Register ...................................................................................................... 4749
22-66. ACLKXCTL Register .................................................................................................... 4750
22-67. AHCLKXCTL Register .................................................................................................. 4751
22-68. XTDM Register .......................................................................................................... 4752
22-69. XINTCTL Register ....................................................................................................... 4753
22-70. XSTAT Register ......................................................................................................... 4755
22-71. XSLOT Register ......................................................................................................... 4757
22-72. XCLKCHK Register ..................................................................................................... 4758
22-73. XEVTCTL Register ...................................................................................................... 4759
22-74. DITCSRA_0 to DITCSRA_5 Register ................................................................................ 4760
22-75. DITCSRB_0 to DITCSRB_5 Register ................................................................................ 4761
22-76. DITUDRA_0 to DITUDRA_5 Register ................................................................................ 4762
22-77. DITUDRB_0 to DITUDRB_5 Register ................................................................................ 4763
22-78. SRCTL_0 to SRCTL_5 Register ...................................................................................... 4764
22-79. XBUF_0 to XBUF_5 Register .......................................................................................... 4766
22-80. RBUF_0 to RBUF_5 Register ......................................................................................... 4767
22-81. WFIFOCTL Register .................................................................................................... 4768
22-82. WFIFOSTS Register .................................................................................................... 4769
22-83. RFIFOCTL Register ..................................................................................................... 4770
22-84. RFIFOSTS Register..................................................................................................... 4771
23-1. DCAN Integration........................................................................................................ 4774
23-2. DCAN Block Diagram ................................................................................................... 4776
23-3. CAN Module General Initialization Flow .............................................................................. 4778
23-4. CAN Bit-Timing Configuration ......................................................................................... 4779

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23-5. CAN Core in Silent Mode .............................................................................................. 4781

23-6. CAN Core in Loopback Mode ......................................................................................... 4782
23-7. CAN Core in External Loopback Mode ............................................................................... 4783
23-8. CAN Core in Loop Back Combined With Silent Mode ............................................................. 4784
23-9. CAN Interrupt Topology 1 .............................................................................................. 4786
23-10. CAN Interrupt Topology 2 .............................................................................................. 4786
23-11. Local Power-Down Mode Flow Diagram ............................................................................. 4788
23-12. CPU Handling of a FIFO Buffer (Interrupt Driven) .................................................................. 4797
23-13. Bit Timing ................................................................................................................. 4798
23-14. The Propagation Time Segment ...................................................................................... 4799
23-15. Synchronization on Late and Early Edges ........................................................................... 4801
23-16. Filtering of Short Dominant Spikes .................................................................................... 4802
23-17. Structure of the CAN Core’s CAN Protocol Controller ............................................................. 4803
23-18. Data Transfer Between IF1/IF2 Registers and Message RAM ................................................... 4807
23-19. CTL Register ............................................................................................................. 4816
23-20. ES Register .............................................................................................................. 4819
23-21. ERRC Register .......................................................................................................... 4821
23-22. BTR Register............................................................................................................. 4822
23-23. INT Register.............................................................................................................. 4823
23-24. TEST Register ........................................................................................................... 4824
23-25. PERR Register .......................................................................................................... 4825
23-26. ABOTR Register ......................................................................................................... 4826
23-27. TXRQ_X Register ....................................................................................................... 4827
23-28. TXRQ12 Register ....................................................................................................... 4828
23-29. TXRQ34 Register ....................................................................................................... 4829
23-30. TXRQ56 Register ....................................................................................................... 4830
23-31. TXRQ78 Register ....................................................................................................... 4831
23-32. NWDAT_X Register ..................................................................................................... 4832
23-33. NWDAT12 Register ..................................................................................................... 4833
23-34. NWDAT34 Register ..................................................................................................... 4834
23-35. NWDAT56 Register ..................................................................................................... 4835
23-36. NWDAT78 Register ..................................................................................................... 4836
23-37. INTPND_X Register..................................................................................................... 4837
23-38. INTPND12 Register ..................................................................................................... 4838
23-39. INTPND34 Register ..................................................................................................... 4839
23-40. INTPND56 Register ..................................................................................................... 4840
23-41. INTPND78 Register ..................................................................................................... 4841
23-42. MSGVAL_X Register ................................................................................................... 4842
23-43. MSGVAL12 Register .................................................................................................... 4843
23-44. MSGVAL34 Register .................................................................................................... 4844
23-45. MSGVAL56 Register .................................................................................................... 4845
23-46. MSGVAL78 Register .................................................................................................... 4846
23-47. INTMUX12 Register..................................................................................................... 4847
23-48. INTMUX34 Register..................................................................................................... 4848
23-49. INTMUX56 Register..................................................................................................... 4849
23-50. INTMUX78 Register..................................................................................................... 4850
23-51. IF1CMD Register ........................................................................................................ 4851
23-52. IF1MSK Register ........................................................................................................ 4854
23-53. IF1ARB Register ........................................................................................................ 4855

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23-54. IF1MCTL Register ....................................................................................................... 4856

23-55. IF1DATA Register ....................................................................................................... 4858
23-56. IF1DATB Register ....................................................................................................... 4859
23-57. IF2CMD Register ........................................................................................................ 4860
23-58. IF2MSK Register ........................................................................................................ 4863
23-59. IF2ARB Register ........................................................................................................ 4864
23-60. IF2MCTL Register ....................................................................................................... 4865
23-61. IF2DATA Register ....................................................................................................... 4867
23-62. IF2DATB Register ....................................................................................................... 4868
23-63. IF3OBS Register ........................................................................................................ 4869
23-64. IF3MSK Register ........................................................................................................ 4871
23-65. IF3ARB Register ........................................................................................................ 4872
23-66. IF3MCTL Register ....................................................................................................... 4873
23-67. IF3DATA Register ....................................................................................................... 4875
23-68. IF3DATB Register ....................................................................................................... 4876
23-69. IF3UPD12 Register ..................................................................................................... 4877
23-70. IF3UPD34 Register ..................................................................................................... 4878
23-71. IF3UPD56 Register ..................................................................................................... 4879
23-72. IF3UPD78 Register ..................................................................................................... 4880
23-73. TIOC Register ........................................................................................................... 4881
23-74. RIOC Register ........................................................................................................... 4883
24-1. SPI Master Application ................................................................................................. 4887
24-2. SPI Slave Application ................................................................................................... 4887
24-3. SPI Full-Duplex Transmission ......................................................................................... 4890
24-4. SPI Half-Duplex Transmission (Receive-only Slave) ............................................................... 4891
24-5. SPI Half-Duplex Transmission (Transmit-Only Slave).............................................................. 4891
24-6. Phase and Polarity Combinations ..................................................................................... 4893
24-7. Full Duplex Single Transfer Format with PHA = 0 .................................................................. 4894
24-8. Full Duplex Single Transfer Format With PHA = 1 ................................................................. 4895
24-9. Continuous Transfers With SPIEN Maintained Active (Single-Data-Pin Interface Mode) ..................... 4900
24-10. Continuous Transfers With SPIEN Maintained Active (Dual-Data-Pin Interface Mode) ....................... 4900
24-11. Extended SPI Transfer With Start Bit PHA = 1 ...................................................................... 4902
24-12. Chip-Select SPIEN Timing Controls .................................................................................. 4903
24-13. Transmit/Receive Mode With No FIFO Used ........................................................................ 4906
24-14. Transmit/Receive Mode With Only Receive FIFO Enabled ....................................................... 4906
24-15. Transmit/Receive Mode With Only Transmit FIFO Used .......................................................... 4907
24-16. Transmit/Receive Mode With Both FIFO Direction Used .......................................................... 4907
24-17. Transmit-Only Mode With FIFO Used ................................................................................ 4908
24-18. Receive-Only Mode With FIFO Used ................................................................................ 4908
24-19. Buffer Almost Full Level (AFL)......................................................................................... 4909
24-20. Buffer Almost Empty Level (AEL) ..................................................................................... 4910
24-21. Master Single Channel Initial Delay................................................................................... 4911
24-22. 3-Pin Mode System Overview ......................................................................................... 4912
24-23. Example of SPI Slave with One Master and Multiple Slave Devices on Channel 0............................ 4914
24-24. SPI Half-Duplex Transmission (Receive-Only Slave) .............................................................. 4916
24-25. SPI Half-Duplex Transmission (Transmit-Only Slave).............................................................. 4917
24-26. MCSPI_REVISION Register ........................................................................................... 4925
24-27. MCSPI_SYSCONFIG Register ........................................................................................ 4926
24-28. MCSPI_SYSSTATUS Register ........................................................................................ 4927

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24-29. MCSPI_IRQSTATUS Register ........................................................................................ 4928

24-30. MCSPI_IRQENABLE Register ........................................................................................ 4931
24-31. MCSPI_SYST Register ................................................................................................. 4933
24-32. MCSPI_MODULCTRL Register ....................................................................................... 4935
24-33. MCSPI_CH0CONF Register ........................................................................................... 4937
24-34. MCSPI_CH0STAT Register............................................................................................ 4941
24-35. MCSPI_CH0CTRL Register ........................................................................................... 4943
24-36. MCSPI_TX0 Register ................................................................................................... 4944
24-37. MCSPI_RX0 Register ................................................................................................... 4945
24-53. MCSPI_XFERLEVEL Register ........................................................................................ 4973
24-54. MCSPI_DAFTX Register ............................................................................................... 4974
24-55. MCSPI_DAFRX Register ............................................................................................... 4975
25-1. GPIO0 Module Integration ............................................................................................. 4978
25-2. GPIO[1–3] Module Integration ......................................................................................... 4978
25-3. Interrupt Request Generation .......................................................................................... 4983
25-4. Wake-Up Request Generation......................................................................................... 4984
25-5. Write @ GPIO_CLEARDATAOUT Register Example .............................................................. 4987
25-6. Write @ GPIO_SETIRQENABLEx Register Example .............................................................. 4988
25-7. General-Purpose Interface Used as a Keyboard Interface ........................................................ 4989
25-8. GPIO_REVISION Register ............................................................................................. 4991
25-9. GPIO_SYSCONFIG Register .......................................................................................... 4992
25-10. GPIO_EOI Register ..................................................................................................... 4993
25-11. GPIO_IRQSTATUS_RAW_0 Register ............................................................................... 4994
25-12. GPIO_IRQSTATUS_RAW_1 Register ............................................................................... 4995
25-13. GPIO_IRQSTATUS_0 Register ....................................................................................... 4996
25-14. GPIO_IRQSTATUS_1 Register ....................................................................................... 4997
25-15. GPIO_IRQSTATUS_SET_0 Register ................................................................................ 4998
25-16. GPIO_IRQSTATUS_SET_1 Register ................................................................................ 4999
25-17. GPIO_IRQSTATUS_CLR_0 Register ................................................................................ 5000
25-18. GPIO_IRQSTATUS_CLR_1 Register ................................................................................ 5001
25-19. GPIO_IRQWAKEN_0 Register ........................................................................................ 5002
25-20. GPIO_IRQWAKEN_1 Register ........................................................................................ 5003
25-21. GPIO_SYSSTATUS Register .......................................................................................... 5004
25-22. GPIO_CTRL Register ................................................................................................... 5005

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25-23. GPIO_OE Register ...................................................................................................... 5006

25-24. GPIO_DATAIN Register ................................................................................................ 5007
25-25. GPIO_DATAOUT Register ............................................................................................. 5008
25-26. GPIO_LEVELDETECT0 Register ..................................................................................... 5009
25-27. GPIO_LEVELDETECT1 Register ..................................................................................... 5010
25-28. GPIO_RISINGDETECT Register...................................................................................... 5011
25-29. GPIO_FALLINGDETECT Register .................................................................................... 5012
25-30. GPIO_DEBOUNCENABLE Register.................................................................................. 5013
25-31. GPIO_DEBOUNCINGTIME Register ................................................................................. 5014
25-32. GPIO_CLEARDATAOUT Register .................................................................................... 5015
25-33. GPIO_SETDATAOUT Register........................................................................................ 5016
26-1. Public ROM Code Architecture ........................................................................................ 5019
26-2. Public ROM Code Boot Procedure ................................................................................... 5020
26-3. Public ROM Code Boot Procedure ................................................................................... 5021
26-4. ROM Memory Map ...................................................................................................... 5022
26-5. ROM Memory Map ...................................................................................................... 5022
26-6. Public RAM Memory Map .............................................................................................. 5024
26-7. Public RAM Memory Map .............................................................................................. 5024
26-8. ROM Code Startup Sequence ......................................................................................... 5026
26-9. ROM Code Startup Sequence ......................................................................................... 5027
26-10. ROM Code Booting Procedure ........................................................................................ 5029
26-11. Fast External Boot ...................................................................................................... 5038
26-12. Memory Booting ......................................................................................................... 5039
26-13. Memory Booting ......................................................................................................... 5039
26-14. GPMC XIP Timings ..................................................................................................... 5042
26-15. Image Shadowing on GP Device...................................................................................... 5045
26-16. GPMC NAND Timings .................................................................................................. 5046
26-17. NAND Device Detection ................................................................................................ 5050
26-18. NAND Invalid Blocks Detection........................................................................................ 5051
26-19. NAND Read Sector Procedure ........................................................................................ 5052
26-20. ECC Data Mapping for 2 KB Page and 8b BCH Encoding ........................................................ 5053
26-21. ECC Data Mapping for 4 KB Page and 16b BCH Encoding ...................................................... 5054
26-22. MMC/SD Booting ........................................................................................................ 5056
26-23. MMC/SD Detection Procedure ........................................................................................ 5057
26-24. MMC/SD Booting, Get Booting File ................................................................................... 5059
26-25. MBR Detection Procedure ............................................................................................. 5060
26-26. MBR, Get Partition ...................................................................................................... 5061
26-27. FAT Detection Procedure .............................................................................................. 5064
26-28. Peripheral Booting Procedure ......................................................................................... 5068
26-29. Peripheral Booting Procedure ......................................................................................... 5069
26-30. USB Initialization Procedure ........................................................................................... 5074
26-31. Image Transfer for USB Boot .......................................................................................... 5075
26-32. Image Formats on GP Devices ........................................................................................ 5076
26-33. Image Formats on GP and HS Devices .............................................................................. 5076
26-34. Wakeup Booting by ROM .............................................................................................. 5080
26-35. Wakeup Booting by ROM .............................................................................................. 5080
27-1. Suspend Control Registers ............................................................................................ 5089

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List of Tables
1-1. Device_ID (Address 0x44E10600) Bit Field Descriptions ........................................................... 174
2-1. L3 Memory Map ........................................................................................................... 177
2-2. L4_WKUP Peripheral Memory Map .................................................................................... 179
2-3. L4_PER Peripheral Memory Map....................................................................................... 180
2-4. L4 Fast Peripheral Memory Map ....................................................................................... 184
3-1. MPU Subsystem Clock Frequencies ................................................................................... 190
3-2. Reset Scheme of the MPU Subsystem ................................................................................ 191
3-3. ARM Core Supported Features ........................................................................................ 193
3-4. Overview of the MPU Subsystem Power Domain .................................................................... 194
3-5. MPU Power States ....................................................................................................... 195
3-6. MPU Subsystem Operation Power Modes ............................................................................ 196
4-1. PRU-ICSS Connectivity Attributes ...................................................................................... 202
4-2. PRU-ICSS Clock Signals ................................................................................................ 202
4-3. PRU-ICSS Pin List ........................................................................................................ 203
4-6. Local Instruction Memory Map .......................................................................................... 206
4-7. Local Data Memory Map ................................................................................................. 206
4-8. Global Memory Map ...................................................................................................... 207
4-9. PRU0/1 Constants Table ................................................................................................ 209
4-10. Real-Time Status Interface Mapping (R31) Field Descriptions ..................................................... 211
4-11. Event Interface Mapping (R31) Field Descriptions ................................................................... 212
4-12. PRU R31 (GPI) Modes ................................................................................................... 213
4-13. PRU GPI Signals and Configurations .................................................................................. 213
4-14. Effective Clock Values ................................................................................................... 216
4-15. PRU R30 (GPO) Modes ................................................................................................. 217
4-16. PRU GPO Signals and Configurations ................................................................................. 217
4-17. Effective Clock Values ................................................................................................... 218
4-18. MPY/MAC XFR ID ........................................................................................................ 220
4-19. MAC_CTRL_STATUS Register (R25) Field Descriptions ........................................................... 221
4-20. Scratch Pad XFR ID ...................................................................................................... 223
4-21. Scratch Pad XFR Collision & Stall Conditions ........................................................................ 223
4-22. PRU-ICSS System Events............................................................................................... 227
4-23. Industrial Ethernet Timer Mode Mapping .............................................................................. 234
4-24. Baud Rate Examples for 192-MHZ UART Input Clock and 16× Over-sampling Mode .......................... 244
4-25. Baud Rate Examples for 192-MHZ UART Input Clock and 13× Over-sampling Mode .......................... 244
4-26. UART Signal Descriptions ............................................................................................... 245
4-27. Character Time for Word Lengths ...................................................................................... 248
4-28. UART Interrupt Requests Descriptions ................................................................................ 252
4-29. Data Path Configuration Comparison .................................................................................. 255
4-30. Frame Structure ........................................................................................................... 257
4-31. TX CRC Programming Models .......................................................................................... 258
4-32. PRU R31: Receive Interface Data and Status (Read Mode) ....................................................... 263
4-33. RX L2 Status .............................................................................................................. 265
4-34. RX L2 XFR ID ............................................................................................................. 266
4-35. PRU R30: Transmit Interface ........................................................................................... 268
4-36. PRU R31: Command Interface (Write Mode) ......................................................................... 269
SPRUH73Q – October 2011 – Revised December 2019 List of Tables 93

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4-37. RX Nibble and Byte Order ............................................................................................... 270

4-38. TX Nibble and Byte Order ............................................................................................... 271
4-39. Preamble Configuration Options ........................................................................................ 271
4-40. PRU_ICSS_PRU_CTRL Registers ..................................................................................... 274
4-41. CTRL Register Field Descriptions ...................................................................................... 275
4-42. STS Register Field Descriptions ........................................................................................ 277
4-43. WAKEUP_EN Register Field Descriptions ............................................................................ 278
4-44. CYCLE Register Field Descriptions .................................................................................... 279
4-45. STALL Register Field Descriptions ..................................................................................... 280
4-46. CTBIR0 Register Field Descriptions.................................................................................... 281
4-47. CTBIR1 Register Field Descriptions.................................................................................... 282
4-48. CTPPR0 Register Field Descriptions .................................................................................. 283
4-49. CTPPR1 Register Field Descriptions .................................................................................. 284
4-50. PRU_ICSS_PRU_DEBUG Registers .................................................................................. 284
4-51. GPREG0 Register Field Descriptions .................................................................................. 286
4-61. GPREG10 Register Field Descriptions ................................................................................ 296
4-83. CT_REG0 Register Field Descriptions ................................................................................. 318
94 List of Tables SPRUH73Q – October 2011 – Revised December 2019

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4-93. CT_REG10 Register Field Descriptions ............................................................................... 328
4-115. PRU_ICSS_INTC Registers ............................................................................................. 349
4-116. REVID Register Field Descriptions ..................................................................................... 351
4-117. CR Register Field Descriptions ......................................................................................... 352
4-118. GER Register Field Descriptions ....................................................................................... 353
4-119. GNLR Register Field Descriptions ...................................................................................... 354
4-120. SISR Register Field Descriptions ....................................................................................... 355
4-121. SICR Register Field Descriptions ....................................................................................... 356
4-122. EISR Register Field Descriptions ....................................................................................... 357
4-123. EICR Register Field Descriptions ....................................................................................... 358
4-124. HIEISR Register Field Descriptions .................................................................................... 359
4-125. HIDISR Register Field Descriptions .................................................................................... 360
4-126. GPIR Register Field Descriptions....................................................................................... 361
4-127. SRSR0 Register Field Descriptions .................................................................................... 362
4-128. SRSR1 Register Field Descriptions .................................................................................... 363
4-129. SECR0 Register Field Descriptions .................................................................................... 364
4-130. SECR1 Register Field Descriptions .................................................................................... 365
4-131. ESR0 Register Field Descriptions ...................................................................................... 366
4-132. ESR1 Register Field Descriptions ...................................................................................... 367
4-133. ECR0 Register Field Descriptions ...................................................................................... 368
4-134. ECR1 Register Field Descriptions ...................................................................................... 369

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4-135. CMR0 Register Field Descriptions ..................................................................................... 370

4-145. CMR10 Register Field Descriptions .................................................................................... 380
4-151. HMR0 Register Field Descriptions ..................................................................................... 386
4-154. HIPIR0 Register Field Descriptions .................................................................................... 389
4-164. SIPR0 Register Field Descriptions ..................................................................................... 399
4-165. SIPR1 Register Field Descriptions ..................................................................................... 400
4-166. SITR0 Register Field Descriptions ..................................................................................... 401
4-167. SITR1 Register Field Descriptions ..................................................................................... 402
4-168. HINLR0 Register Field Descriptions.................................................................................... 403
4-178. HIER Register Field Descriptions ....................................................................................... 413
4-179. PRU_ICSS_IEP Registers ............................................................................................... 413
4-180. IEP_TMR_GLB_CFG Register Field Descriptions ................................................................... 415
4-181. IEP_TMR_GLB_STS Register Field Descriptions .................................................................... 416
4-182. IEP_TMR_COMPEN Register Field Descriptions .................................................................... 417
4-183. IEP_TMR_CNT Register Field Descriptions .......................................................................... 418

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4-184. IEP_TMR_CAP_CFG Register Field Descriptions ................................................................... 419

4-185. IEP_TMR_CAP_STS Register Field Descriptions .................................................................... 421
4-186. IEP_TMR_CAPR0 Register Field Descriptions ....................................................................... 422
4-193. IEP_TMR_CAPF6 Register Field Descriptions ....................................................................... 429
4-195. IEP_TMR_CAPF7 Register Field Descriptions ....................................................................... 431
4-196. IEP_TMR_CMP_CFG Register Field Descriptions ................................................................... 432
4-197. IEP_TMR_CMP_STS Register Field Descriptions ................................................................... 433
4-198. IEP_TMR_CMP0 Register Field Descriptions ........................................................................ 434
4-206. IEP_TMR_RXIPG0 Register Field Descriptions ...................................................................... 442
4-207. IEP_TMR_RXIPG1 Register Field Descriptions ...................................................................... 443
4-208. IEP_SYNC_CTRL Register Field Descriptions ....................................................................... 444
4-209. IEP_SYNC_FIRST_STAT Register Field Descriptions .............................................................. 446
4-210. IEP_SYNC0_STAT Register Field Descriptions ...................................................................... 447
4-211. IEP_SYNC1_STAT Register Field Descriptions ...................................................................... 448
4-212. IEP_SYNC_PWIDTH Register Field Descriptions .................................................................... 449
4-213. IEP_SYNC0_PERIOD Register Field Descriptions .................................................................. 450
4-214. IEP_SYNC1_DELAY Register Field Descriptions .................................................................... 451
4-215. IEP_SYNC_START Register Field Descriptions ..................................................................... 452
4-216. IEP_WD_PREDIV Register Field Descriptions ....................................................................... 453
4-217. IEP_PDI_WD_TIM Register Field Descriptions ....................................................................... 454
4-218. IEP_PD_WD_TIM Register Field Descriptions ....................................................................... 455
4-219. IEP_WD_STATUS Register Field Descriptions ....................................................................... 456
4-220. IEP_WD_EXP_CNT Register Field Descriptions ..................................................................... 457
4-221. IEP_WD_CTRL Register Field Descriptions .......................................................................... 458
4-222. IEP_DIGIO_CTRL Register Field Descriptions ....................................................................... 459
4-223. IEP_DIGIO_DATA_IN Register Field Descriptions ................................................................... 460
4-224. IEP_DIGIO_DATA_IN_RAW Register Field Descriptions ........................................................... 461
4-225. IEP_DIGIO_DATA_OUT Register Field Descriptions ................................................................ 462
4-226. IEP_DIGIO_DATA_OUT_EN Register Field Descriptions .......................................................... 463
4-227. IEP_DIGIO_EXP Register Field Descriptions ......................................................................... 464
4-228. PRU_ICSS_UART Registers ............................................................................................ 465
4-229. Receiver Buffer Register (RBR) Field Descriptions .................................................................. 466
4-230. Transmitter Holding Register (THR) Field Descriptions ............................................................. 467
4-231. Interrupt Enable Register (IER) Field Descriptions ................................................................... 468
4-232. Interrupt Identification Register (IIR) Field Descriptions ............................................................. 469

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4-233. Interrupt Identification and Interrupt Clearing Information ........................................................... 470

4-234. FIFO Control Register (FCR) Field Descriptions ..................................................................... 471
4-235. Line Control Register (LCR) Field Descriptions....................................................................... 472
4-236. Relationship Between ST, EPS, and PEN Bits in LCR .............................................................. 473
4-237. Number of STOP Bits Generated ....................................................................................... 473
4-238. Modem Control Register (MCR) Field Descriptions .................................................................. 474
4-239. Line Status Register (LSR) Field Descriptions ........................................................................ 475
4-240. Modem Status Register (MSR) Field Descriptions ................................................................... 478
4-241. Scratch Pad Register (MSR) Field Descriptions ...................................................................... 479
4-242. Divisor LSB Latch (DLL) Field Descriptions ........................................................................... 480
4-243. Divisor MSB Latch (DLH) Field Descriptions .......................................................................... 480
4-244. Revision Identification Register 1 (REVID1) Field Descriptions .................................................... 481
4-245. Revision Identification Register 2 (REVID2) Field Descriptions .................................................... 481
4-246. Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions .......................... 482
4-247. Mode Definition Register (MDR) Field Descriptions.................................................................. 483
4-248. PRU_ICSS_MII_RT Registers .......................................................................................... 483
4-249. RXCFG0 Register Field Descriptions .................................................................................. 484
4-250. RXCFG1 Register Field Descriptions .................................................................................. 486
4-251. TXCFG0 Register Field Descriptions .................................................................................. 488
4-252. TXCFG1 Register Field Descriptions .................................................................................. 490
4-253. TXCRC0 Register Field Descriptions .................................................................................. 492
4-254. TXCRC1 Register Field Descriptions .................................................................................. 493
4-255. TXIPG0 Register Field Descriptions.................................................................................... 494
4-256. TXIPG1 Register Field Descriptions.................................................................................... 495
4-257. PRS0 Register Field Descriptions ...................................................................................... 496
4-258. PRS1 Register Field Descriptions ...................................................................................... 497
4-259. RXFRMS0 Register Field Descriptions ................................................................................ 498
4-260. RXFRMS1 Register Field Descriptions ................................................................................ 499
4-261. RXPCNT0 Register Field Descriptions................................................................................. 500
4-262. RXPCNT1 Register Field Descriptions................................................................................. 501
4-263. RXERR0 Register Field Descriptions .................................................................................. 502
4-264. RXERR1 Register Field Descriptions .................................................................................. 503
4-265. PRU_ICSS_CFG Registers ............................................................................................. 504
4-266. REVID Register Field Descriptions ..................................................................................... 505
4-267. SYSCFG Register Field Descriptions .................................................................................. 506
4-268. GPCFG0 Register Field Descriptions .................................................................................. 507
4-269. GPCFG1 Register Field Descriptions .................................................................................. 509
4-270. CGR Register Field Descriptions ....................................................................................... 511
4-271. ISRP Register Field Descriptions ....................................................................................... 513
4-272. ISP Register Field Descriptions ......................................................................................... 514
4-273. IESP Register Field Descriptions ....................................................................................... 515
4-274. IECP Register Field Descriptions ....................................................................................... 516
4-275. PMAO Register Field Descriptions ..................................................................................... 517
4-276. MII_RT Register Field Descriptions .................................................................................... 518
4-277. IEPCLK Register Field Descriptions.................................................................................... 519
4-278. SPP Register Field Descriptions ........................................................................................ 520
4-279. PIN_MX Register Field Descriptions ................................................................................... 521
5-1. SGX530 Connectivity Attributes ........................................................................................ 526
5-2. SGX530 Clock Signals ................................................................................................... 526

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6-1. ARM Cortex-A8 Interrupts ............................................................................................... 543

6-2. Crypto DMA Events ...................................................................................................... 547
6-3. Timer and eCAP Event Capture ........................................................................................ 549
6-4. INTC Registers ............................................................................................................ 550
6-5. INTC_REVISION Register Field Descriptions ........................................................................ 552
6-6. INTC_SYSCONFIG Register Field Descriptions ..................................................................... 553
6-7. INTC_SYSSTATUS Register Field Descriptions ..................................................................... 554
6-8. INTC_SIR_IRQ Register Field Descriptions........................................................................... 555
6-9. INTC_SIR_FIQ Register Field Descriptions ........................................................................... 556
6-10. INTC_CONTROL Register Field Descriptions ........................................................................ 557
6-11. INTC_PROTECTION Register Field Descriptions .................................................................... 558
6-12. INTC_IDLE Register Field Descriptions ............................................................................... 559
6-13. INTC_IRQ_PRIORITY Register Field Descriptions .................................................................. 560
6-14. INTC_FIQ_PRIORITY Register Field Descriptions................................................................... 561
6-15. INTC_THRESHOLD Register Field Descriptions ..................................................................... 562
6-16. INTC_ITR0 Register Field Descriptions ............................................................................... 563
6-17. INTC_MIR0 Register Field Descriptions ............................................................................... 564
6-18. INTC_MIR_CLEAR0 Register Field Descriptions .................................................................... 565
6-19. INTC_MIR_SET0 Register Field Descriptions ........................................................................ 566
6-20. INTC_ISR_SET0 Register Field Descriptions......................................................................... 567
6-21. INTC_ISR_CLEAR0 Register Field Descriptions ..................................................................... 568
6-22. INTC_PENDING_IRQ0 Register Field Descriptions ................................................................. 569
6-23. INTC_PENDING_FIQ0 Register Field Descriptions.................................................................. 570
6-48. INTC_ILR_0 to INTC_ILR_127 Register Field Descriptions ........................................................ 595
7-1. Unsupported GPMC Features .......................................................................................... 599

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7-2. GPMC Connectivity Attributes .......................................................................................... 600

7-3. GPMC Clock Signals ..................................................................................................... 600
7-4. GPMC Signal List ......................................................................................................... 601
7-5. GPMC Pin Multiplexing Options ........................................................................................ 602
7-6. GPMC Clocks ............................................................................................................. 607
7-7. GPMC_CONFIG1_i Configuration ...................................................................................... 607
7-8. GPMC Local Power Management Features .......................................................................... 607
7-9. GPMC Interrupt Events .................................................................................................. 608
7-10. Idle Cycle Insertion Configuration ...................................................................................... 619
7-11. Flattened BCH Codeword Mapping (512 Bytes + 104 Bits) ......................................................... 662
7-12. Aligned Message Byte Mapping in 8-bit NAND ....................................................................... 662
7-13. Aligned Message Byte Mapping in 16-bit NAND ..................................................................... 663
7-14. Aligned Nibble Mapping of Message in 8-bit NAND ................................................................. 663
7-15. Misaligned Nibble Mapping of Message in 8-bit NAND.............................................................. 663
7-16. Aligned Nibble Mapping of Message in 16-bit NAND ................................................................ 663
7-17. Misaligned Nibble Mapping of Message in 16-bit NAND (1 Unused Nibble) ..................................... 664
7-20. Prefetch Mode Configuration ............................................................................................ 675
7-21. GPMC Configuration in NOR Mode .................................................................................... 683
7-22. GPMC Configuration in NAND Mode .................................................................................. 683
7-23. Reset GPMC .............................................................................................................. 683
7-24. NOR Memory Type ....................................................................................................... 684
7-25. NOR Chip-Select Configuration ......................................................................................... 684
7-26. NOR Timings Configuration ............................................................................................. 684
7-27. WAIT Pin Configuration .................................................................................................. 684
7-28. Enable Chip-Select ....................................................................................................... 685
7-29. NAND Memory Type ..................................................................................................... 685
7-30. NAND Chip-Select Configuration ....................................................................................... 685
7-31. Asynchronous Read and Write Operations ........................................................................... 685
7-32. ECC Engine ............................................................................................................... 685
7-33. Prefetch and Write-Posting Engine ..................................................................................... 687
7-34. WAIT Pin Configuration .................................................................................................. 687
7-35. Enable Chip-Select ....................................................................................................... 687
7-36. Mode Parameters Check List Table .................................................................................... 688
7-37. Access Type Parameters Check List Table ........................................................................... 688
7-38. Timing Parameters ....................................................................................................... 690
7-39. GPMC Signals............................................................................................................. 692
7-40. Useful Timing Parameters on the Memory Side ...................................................................... 694
7-41. Calculating GPMC Timing Parameters ................................................................................ 695
7-42. AC Characteristics for Asynchronous Read Access ................................................................. 696
7-43. GPMC Timing Parameters for Asynchronous Read Access ........................................................ 697
7-44. AC Characteristics for Asynchronous Single Write (Memory Side) ................................................ 698
7-45. GPMC Timing Parameters for Asynchronous Single Write ......................................................... 699
7-46. NAND Interface Bus Operations Summary............................................................................ 700
7-47. NOR Interface Bus Operations Summary ............................................................................. 700
7-48. GPMC Registers .......................................................................................................... 702
7-49. GPMC_REVISION Register Field Descriptions ....................................................................... 707
7-50. GPMC_SYSCONFIG Register Field Descriptions .................................................................... 708

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7-51. GPMC_SYSSTATUS Register Field Descriptions ................................................................... 709

7-52. GPMC_IRQSTATUS Register Field Descriptions .................................................................... 710
7-53. GPMC_IRQENABLE Register Field Descriptions .................................................................... 711
7-54. GPMC_TIMEOUT_CONTROL Register Field Descriptions ......................................................... 712
7-55. GPMC_ERR_ADDRESS Register Field Descriptions ............................................................... 713
7-56. GPMC_ERR_TYPE Register Field Descriptions ..................................................................... 714
7-57. GPMC_CONFIG Register Field Descriptions ......................................................................... 715
7-58. GPMC_STATUS Register Field Descriptions ......................................................................... 716
7-59. GPMC_CONFIG1_0 Register Field Descriptions..................................................................... 717
7-66. GPMC_NAND_COMMAND_0 Register Field Descriptions ......................................................... 728
7-67. GPMC_NAND_ADDRESS_0 Register Field Descriptions .......................................................... 729
7-68. GPMC_NAND_DATA_0 Register Field Descriptions ................................................................ 730

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7-129. GPMC_PREFETCH_CONFIG1 Register Field Descriptions ....................................................... 815
7-130. GPMC_PREFETCH_CONFIG2 Register Field Descriptions ....................................................... 817
7-131. GPMC_PREFETCH_CONTROL Register Field Descriptions ...................................................... 818
7-132. GPMC_PREFETCH_STATUS Register Field Descriptions ......................................................... 819
7-133. GPMC_ECC_CONFIG Register Field Descriptions .................................................................. 820
7-134. GPMC_ECC_CONTROL Register Field Descriptions ............................................................... 822
7-135. GPMC_ECC_SIZE_CONFIG Register Field Descriptions .......................................................... 823
7-136. GPMC_ECC1_RESULT Register Field Descriptions ................................................................ 825
7-145. GPMC_BCH_RESULT0_0 Register Field Descriptions ............................................................. 843

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7-177. GPMC_BCH_SWDATA Register Field Descriptions ................................................................. 875

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7-202. OCMC RAM Connectivity Attributes.................................................................................... 901
7-203. OCMC RAM Clock Signals .............................................................................................. 901
7-204. Unsupported EMIF Features ............................................................................................ 903
7-205. EMIF Connectivity Attributes ............................................................................................ 904
7-206. EMIF Clock Signals ....................................................................................................... 904
7-207. EMIF Pin List .............................................................................................................. 904
7-208. DDR2/3/mDDR Memory Controller Signal Descriptions ............................................................. 906
7-209. Digital Filter Configuration ............................................................................................... 910
7-210. IBANK, RSIZE and PAGESIZE Fields Information ................................................................... 911
7-211. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=0 and REG_EBANK_POS=0 .. 912
7-216. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=1 and REG_EBANK_POS = 1. 914
7-217. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=2 and REG_EBANK_POS = 1. 915
7-219. Refresh Modes ............................................................................................................ 918
7-220. Filter Configurations for Performance Counters ...................................................................... 919
7-221. EMIF4D Registers ........................................................................................................ 928
7-222. EMIF_MOD_ID_REV Register Field Descriptions .................................................................... 930
7-223. STATUS Register Field Descriptions .................................................................................. 931
7-224. SDRAM_CONFIG Register Field Descriptions ....................................................................... 932
7-225. SDRAM_CONFIG_2 Register Field Descriptions .................................................................... 934
7-226. SDRAM_REF_CTRL Register Field Descriptions .................................................................... 935
7-227. SDRAM_REF_CTRL_SHDW Register Field Descriptions .......................................................... 936
7-228. SDRAM_TIM_1 Register Field Descriptions .......................................................................... 937
7-229. SDRAM_TIM_1_SHDW Register Field Descriptions ................................................................ 938
7-234. PWR_MGMT_CTRL Register Field Descriptions..................................................................... 943
7-235. PWR_MGMT_CTRL_SHDW Register Field Descriptions ........................................................... 945
7-236. OCP_CONFIG Register Field Descriptions ........................................................................... 946
7-237. OCP_CFG_VAL_1 Register Field Descriptions ...................................................................... 947
7-238. OCP_CFG_VAL_2 Register Field Descriptions ...................................................................... 948
7-239. PERF_CNT_1 Register Field Descriptions ............................................................................ 949
7-240. PERF_CNT_2 Register Field Descriptions ............................................................................ 950
7-241. PERF_CNT_CFG Register Field Descriptions ........................................................................ 951
7-242. PERF_CNT_SEL Register Field Descriptions ........................................................................ 952
7-243. PERF_CNT_TIM Register Field Descriptions ......................................................................... 953
7-244. READ_IDLE_CTRL Register Field Descriptions...................................................................... 954
7-245. READ_IDLE_CTRL_SHDW Register Field Descriptions ............................................................ 955
7-246. IRQSTATUS_RAW_SYS Register Field Descriptions ............................................................... 956

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7-247. IRQSTATUS_SYS Register Field Descriptions ....................................................................... 957

7-248. IRQENABLE_SET_SYS Register Field Descriptions ................................................................ 958
7-249. IRQENABLE_CLR_SYS Register Field Descriptions ................................................................ 959
7-250. ZQ_CONFIG Register Field Descriptions ............................................................................. 960
7-251. Read-Write Leveling Ramp Window Register Field Descriptions .................................................. 961
7-252. Read-Write Leveling Ramp Control Register Field Descriptions ................................................... 962
7-253. Read-Write Leveling Control Register Field Descriptions ........................................................... 963
7-254. DDR_PHY_CTRL_1 Register Field Descriptions ..................................................................... 964
7-255. DDR_PHY_CTRL_1_SHDW Register Field Descriptions ........................................................... 966
7-256. Priority to Class of Service Mapping Register Field Descriptions .................................................. 968
7-257. Connection ID to Class of Service 1 Mapping Register Field Descriptions ....................................... 969
7-258. Connection ID to Class of Service 2 Mapping Register Field Descriptions ....................................... 970
7-259. Read Write Execution Threshold Register Field Descriptions ...................................................... 971
7-260. Memory-Mapped Registers for DDR2/3/mDDR PHY ................................................................ 972
7-261. DDR PHY Command 0/1/2 Address/Command Slave Ratio Register
(CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0) Field Descriptions ............................................ 974
7-262. DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register
(CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0) Field Descriptions .................................................. 974
7-263. DDR PHY Command 0/1/2 Invert Clockout Selection Register(
CMD0/1/2_REG_PHY_INVERT_CLKOUT_0) Field Descriptions .................................................. 975
7-264. DDR PHY Data Macro 0/1 Read DQS Slave Ratio Register
(DATA0/1_REG_PHY_RD_DQS_SLAVE_RATIO_0) Field Descriptions ......................................... 975
7-265. DDR PHY Data Macro 0/1 Write DQS Slave Ratio Register
(DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0) ............................................................... 976
7-266. DDR PHY Data Macro 0/1 Write DQS Slave Ratio Register(
DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0) Field Descriptions ......................................... 976
7-267. DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0) Field Descriptions................................................ 976
7-268. DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_WRLVL_INIT_MODE_0) ..................................................................... 977
7-269. DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0) Field Descriptions .............................................. 977
7-270. DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_GATELVL_INIT_MODE_0) Field Descriptions ............................................ 978
7-271. DDR PHY Data Macro 0/1 DQS Gate Slave Ratio Register
(DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) Field Descriptions ........................................ 978
7-272. DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0) Field Descriptions ....................................... 979
7-273. DDR PHY Data Macro 0/1 Delay Selection Register (DATA0/1_REG_PHY_USE_RANK0_DELAYS)
Field Descriptions ......................................................................................................... 980
7-274. DDR PHY Data 0/1 DLL Lock Difference Register (DATA0/1_REG_PHY_DLL_LOCK_DIFF_0) Field
Descriptions ............................................................................................................... 980
7-275. Offset value from DQS to DQ for Data Macro Register (DATA0/DATA1 _REG_PHY_DQ_OFFSET_0)
Field Descriptions ......................................................................................................... 981
7-276. ELM Connectivity Attributes ............................................................................................. 983
7-277. ELM Clock Signals........................................................................................................ 983
7-278. Local Power Management Features ................................................................................... 984
7-279. Events ...................................................................................................................... 984
7-280. ELM_LOCATION_STATUS_i Value Decoding Table ................................................................ 986
7-281. ELM Processing Initialization ............................................................................................ 987
7-282. ELM Processing Completion for Continuous Mode .................................................................. 987
7-283. ELM Processing Completion for Page Mode ......................................................................... 988
7-284. Use Case: Continuous Mode ............................................................................................ 988

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7-285. 16-bit NAND Sector Buffer Address Map .............................................................................. 990

7-286. Use Case: Page Mode ................................................................................................... 990
7-287. ELM Registers............................................................................................................. 992
7-288. ELM_REVISION Register Field Descriptions ......................................................................... 997
7-289. ELM_SYSCONFIG Register Field Descriptions ...................................................................... 998
7-290. ELM_SYSSTATUS Register Field Descriptions ...................................................................... 999
7-291. ELM_IRQSTATUS Register Field Descriptions ..................................................................... 1000
7-292. ELM_IRQENABLE Register Field Descriptions ..................................................................... 1002
7-293. ELM_LOCATION_CONFIG Register Field Descriptions ........................................................... 1003
7-294. ELM_PAGE_CTRL Register Field Descriptions..................................................................... 1004
7-295. ELM_SYNDROME_FRAGMENT_0_0 Register Field Descriptions .............................................. 1005

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7-351. ELM_LOCATION_STATUS_0 Register Field Descriptions ........................................................ 1061
7-352. ELM_ERROR_LOCATION_0_0 Register Field Descriptions...................................................... 1062
7-362. ELM_ERROR_LOCATION_10_0 Register Field Descriptions .................................................... 1072

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8-1. Master Module Standby-Mode Settings .............................................................................. 1199
8-2. Master Module Standby Status ....................................................................................... 1200
8-3. Module Idle Mode Settings ............................................................................................. 1200
8-4. Idle States for a Slave Module ........................................................................................ 1201
8-5. Slave Module Mode Settings in PRCM............................................................................... 1201
8-6. Module Clock Enabling Condition ..................................................................................... 1202
8-7. Clock Domain Functional Clock States ............................................................................... 1203
8-8. Clock Domain States ................................................................................................... 1204
8-9. Clock Transition Mode Settings ....................................................................................... 1204
8-10. States of a Memory Area in a Power Domain ....................................................................... 1205
8-11. States of a Logic Area in a Power Domain .......................................................................... 1205
8-12. Power Domain Control and Status Registers........................................................................ 1206
8-13. Typical Power Modes ................................................................................................... 1207
8-14. USB Wakeup Use Cases Supported in System Sleep States .................................................... 1211
8-15. CMD_STAT Field........................................................................................................ 1214
8-16. CMD_ID Field ............................................................................................................ 1214
8-17. Output Clocks in Locked Condition ................................................................................... 1219
8-18. Output Clocks Before Lock and During Relock Modes ............................................................ 1219
8-19. Output Clocks in Locked Condition ................................................................................... 1221
8-20. Output Clocks Before Lock and During Relock Modes ............................................................ 1221
8-21. PLL and Clock Frequences ............................................................................................ 1227
8-22. Core PLL Typical Frequencies (MHz) ................................................................................ 1227
8-23. Bus Interface Clocks .................................................................................................... 1228
8-24. Per PLL Typical Frequencies (MHz) .................................................................................. 1229
8-25. Reset Sources ........................................................................................................... 1245
8-26. Reset Sources ........................................................................................................... 1246
8-27. Core Logic Voltage and Power Domains ............................................................................ 1249
8-28. Power Domain State Table ............................................................................................ 1249
8-29. Power Domain of Various Modules ................................................................................... 1250
8-30. CM_PER REGISTERS ................................................................................................. 1253
8-31. CM_PER_L4LS_CLKSTCTRL Register Field Descriptions ....................................................... 1255
8-32. CM_PER_L3S_CLKSTCTRL Register Field Descriptions ......................................................... 1257
8-33. CM_PER_L3_CLKSTCTRL Register Field Descriptions ........................................................... 1258
8-34. CM_PER_CPGMAC0_CLKCTRL Register Field Descriptions .................................................... 1259
8-35. CM_PER_LCDC_CLKCTRL Register Field Descriptions .......................................................... 1260
8-36. CM_PER_USB0_CLKCTRL Register Field Descriptions .......................................................... 1261
8-37. CM_PER_TPTC0_CLKCTRL Register Field Descriptions......................................................... 1262
8-38. CM_PER_EMIF_CLKCTRL Register Field Descriptions ........................................................... 1263
8-39. CM_PER_OCMCRAM_CLKCTRL Register Field Descriptions ................................................... 1264
8-40. CM_PER_GPMC_CLKCTRL Register Field Descriptions ......................................................... 1265
8-41. CM_PER_MCASP0_CLKCTRL Register Field Descriptions ...................................................... 1266
8-42. CM_PER_UART5_CLKCTRL Register Field Descriptions ........................................................ 1267
8-43. CM_PER_MMC0_CLKCTRL Register Field Descriptions ......................................................... 1268

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8-44. CM_PER_ELM_CLKCTRL Register Field Descriptions............................................................ 1269

8-45. CM_PER_I2C2_CLKCTRL Register Field Descriptions ........................................................... 1270
8-46. CM_PER_I2C1_CLKCTRL Register Field Descriptions ........................................................... 1271
8-47. CM_PER_SPI0_CLKCTRL Register Field Descriptions ........................................................... 1272
8-48. CM_PER_SPI1_CLKCTRL Register Field Descriptions ........................................................... 1273
8-49. CM_PER_L4LS_CLKCTRL Register Field Descriptions ........................................................... 1274
8-50. CM_PER_MCASP1_CLKCTRL Register Field Descriptions ...................................................... 1275
8-55. CM_PER_TIMER7_CLKCTRL Register Field Descriptions ....................................................... 1280
8-59. CM_PER_GPIO1_CLKCTRL Register Field Descriptions ......................................................... 1284
8-62. CM_PER_TPCC_CLKCTRL Register Field Descriptions .......................................................... 1287
8-63. CM_PER_DCAN0_CLKCTRL Register Field Descriptions ........................................................ 1288
8-64. CM_PER_DCAN1_CLKCTRL Register Field Descriptions ........................................................ 1289
8-65. CM_PER_EPWMSS1_CLKCTRL Register Field Descriptions.................................................... 1290
8-68. CM_PER_L3_INSTR_CLKCTRL Register Field Descriptions .................................................... 1293
8-69. CM_PER_L3_CLKCTRL Register Field Descriptions .............................................................. 1294
8-70. CM_PER_IEEE5000_CLKCTRL Register Field Descriptions ..................................................... 1295
8-71. CM_PER_PRU_ICSS_CLKCTRL Register Field Descriptions.................................................... 1296
8-78. CM_PER_SPINLOCK_CLKCTRL Register Field Descriptions ................................................... 1303
8-79. CM_PER_MAILBOX0_CLKCTRL Register Field Descriptions.................................................... 1304
8-80. CM_PER_L4HS_CLKSTCTRL Register Field Descriptions ....................................................... 1305
8-81. CM_PER_L4HS_CLKCTRL Register Field Descriptions .......................................................... 1306
8-82. CM_PER_OCPWP_L3_CLKSTCTRL Register Field Descriptions ............................................... 1307
8-83. CM_PER_OCPWP_CLKCTRL Register Field Descriptions ....................................................... 1308
8-84. CM_PER_PRU_ICSS_CLKSTCTRL Register Field Descriptions ................................................ 1309
8-85. CM_PER_CPSW_CLKSTCTRL Register Field Descriptions...................................................... 1310
8-86. CM_PER_LCDC_CLKSTCTRL Register Field Descriptions ...................................................... 1311
8-87. CM_PER_CLKDIV32K_CLKCTRL Register Field Descriptions................................................... 1312
8-88. CM_PER_CLK_24MHZ_CLKSTCTRL Register Field Descriptions .............................................. 1313
8-89. CM_WKUP Registers ................................................................................................... 1313
8-90. CM_WKUP_CLKSTCTRL Register Field Descriptions............................................................. 1316
8-91. CM_WKUP_CONTROL_CLKCTRL Register Field Descriptions ................................................. 1318
8-92. CM_WKUP_GPIO0_CLKCTRL Register Field Descriptions ...................................................... 1319

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8-93. CM_WKUP_L4WKUP_CLKCTRL Register Field Descriptions ................................................... 1320

8-94. CM_WKUP_TIMER0_CLKCTRL Register Field Descriptions ..................................................... 1321
8-95. CM_WKUP_DEBUGSS_CLKCTRL Register Field Descriptions ................................................. 1322
8-96. CM_L3_AON_CLKSTCTRL Register Field Descriptions .......................................................... 1324
8-97. CM_AUTOIDLE_DPLL_MPU Register Field Descriptions ......................................................... 1325
8-98. CM_IDLEST_DPLL_MPU Register Field Descriptions ............................................................. 1326
8-99. CM_SSC_DELTAMSTEP_DPLL_MPU Register Field Descriptions ............................................. 1327
8-100. CM-SSC_MODFREQDIV_DPLL_MPU Register Field Descriptions ............................................. 1328
8-101. CM_CLKSEL_DPLL_MPU Register Field Descriptions ............................................................ 1329
8-102. CM_AUTOIDLE_DPLL_DDR Register Field Descriptions ......................................................... 1330
8-103. CM_IDLEST_DPLL_DDR Register Field Descriptions ............................................................. 1331
8-104. CM_SSC_DELTAMSTEP_DPLL_DDR Register Field Descriptions ............................................. 1332
8-105. CM_SSC_MODFREQDIV_DPLL_DDR Register Field Descriptions ............................................. 1333
8-106. CM_CLKSEL_DPLL_DDR Register Field Descriptions ............................................................ 1334
8-107. CM_AUTOIDLE_DPLL_DISP Register Field Descriptions ........................................................ 1335
8-108. CM_IDLEST_DPLL_DISP Register Field Descriptions ............................................................ 1336
8-109. CM_SSC_DELTAMSTEP_DPLL_DISP Register Field Descriptions ............................................. 1337
8-110. CM_SSC_MODFREQDIV_DPLL_DISP Register Field Descriptions............................................. 1338
8-111. CM_CLKSEL_DPLL_DISP Register Field Descriptions............................................................ 1339
8-112. CM_AUTOIDLE_DPLL_CORE Register Field Descriptions ....................................................... 1340
8-113. CM_IDLEST_DPLL_CORE Register Field Descriptions ........................................................... 1341
8-114. CM_SSC_DELTAMSTEP_DPLL_CORE Register Field Descriptions ........................................... 1342
8-115. CM_SSC_MODFREQDIV_DPLL_CORE Register Field Descriptions ........................................... 1343
8-116. CM_CLKSEL_DPLL_CORE Register Field Descriptions .......................................................... 1344
8-117. CM_AUTOIDLE_DPLL_PER Register Field Descriptions ......................................................... 1345
8-118. CM_IDLEST_DPLL_PER Register Field Descriptions ............................................................. 1346
8-119. CM_SSC_DELTAMSTEP_DPLL_PER Register Field Descriptions.............................................. 1347
8-120. CM_SSC_MODFREQDIV_DPLL_PER Register Field Descriptions ............................................. 1348
8-121. CM_CLKDCOLDO_DPLL_PER Register Field Descriptions ...................................................... 1349
8-122. CM_DIV_M4_DPLL_CORE Register Field Descriptions ........................................................... 1350
8-124. CM_CLKMODE_DPLL_MPU Register Field Descriptions ......................................................... 1352
8-125. CM_CLKMODE_DPLL_PER Register Field Descriptions ......................................................... 1354
8-126. CM_CLKMODE_DPLL_CORE Register Field Descriptions ....................................................... 1355
8-127. CM_CLKMODE_DPLL_DDR Register Field Descriptions ......................................................... 1357
8-128. CM_CLKMODE_DPLL_DISP Register Field Descriptions......................................................... 1359
8-129. CM_CLKSEL_DPLL_PERIPH Register Field Descriptions ........................................................ 1361
8-130. CM_DIV_M2_DPLL_DDR Register Field Descriptions............................................................. 1362
8-131. CM_DIV_M2_DPLL_DISP Register Field Descriptions ............................................................ 1363
8-132. CM_DIV_M2_DPLL_MPU Register Field Descriptions ............................................................ 1364
8-133. CM_DIV_M2_DPLL_PER Register Field Descriptions ............................................................. 1365
8-134. CM_WKUP_WKUP_M3_CLKCTRL Register Field Descriptions ................................................. 1366
8-135. CM_WKUP_UART0_CLKCTRL Register Field Descriptions ...................................................... 1367
8-136. CM_WKUP_I2C0_CLKCTRL Register Field Descriptions ......................................................... 1368
8-137. CM_WKUP_ADC_TSC_CLKCTRL Register Field Descriptions .................................................. 1369
8-138. CM_WKUP_SMARTREFLEX0_CLKCTRL Register Field Descriptions ......................................... 1370
8-139. CM_WKUP_TIMER1_CLKCTRL Register Field Descriptions ..................................................... 1371
8-140. CM_WKUP_SMARTREFLEX1_CLKCTRL Register Field Descriptions ......................................... 1372
8-141. CM_L4_WKUP_AON_CLKSTCTRL Register Field Descriptions ................................................. 1373

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8-142. CM_WKUP_WDT1_CLKCTRL Register Field Descriptions ....................................................... 1374

8-144. CM_DPLL REGISTERS ................................................................................................ 1376
8-145. CLKSEL_TIMER7_CLK Register Field Descriptions ............................................................... 1377
8-149. CM_MAC_CLKSEL Register Field Descriptions .................................................................... 1381
8-152. CM_CPTS_RFT_CLKSEL Register Field Descriptions ............................................................ 1384
8-153. CLKSEL_TIMER1MS_CLK Register Field Descriptions ........................................................... 1385
8-154. CLKSEL_GFX_FCLK Register Field Descriptions .................................................................. 1386
8-155. CLKSEL_PRU_ICSS_OCP_CLK Register Field Descriptions .................................................... 1387
8-156. CLKSEL_LCDC_PIXEL_CLK Register Field Descriptions......................................................... 1388
8-157. CLKSEL_WDT1_CLK Register Field Descriptions ................................................................. 1389
8-158. CLKSEL_GPIO0_DBCLK Register Field Descriptions ............................................................. 1390
8-159. CM_MPU REGISTERS ................................................................................................. 1390
8-160. CM_MPU_CLKSTCTRL Register Field Descriptions ............................................................... 1391
8-161. CM_MPU_MPU_CLKCTRL Register Field Descriptions ........................................................... 1392
8-162. CM_DEVICE REGISTERS ............................................................................................. 1392
8-163. CM_CLKOUT_CTRL Register Field Descriptions .................................................................. 1394
8-164. CM_RTC REGISTERS ................................................................................................. 1395
8-165. CM_RTC_RTC_CLKCTRL Register Field Descriptions............................................................ 1396
8-166. CM_RTC_CLKSTCTRL Register Field Descriptions ............................................................... 1397
8-167. CM_GFX REGISTERS ................................................................................................. 1398
8-168. CM_GFX_L3_CLKSTCTRL Register Field Descriptions ........................................................... 1399
8-169. CM_GFX_GFX_CLKCTRL Register Field Descriptions............................................................ 1400
8-170. CM_GFX_L4LS_GFX_CLKSTCTRL Register Field Descriptions ................................................ 1401
8-171. CM_GFX_MMUCFG_CLKCTRL Register Field Descriptions ..................................................... 1402
8-172. CM_GFX_MMUDATA_CLKCTRL Register Field Descriptions ................................................... 1403
8-173. CM_CEFUSE REGISTERS ............................................................................................ 1403
8-174. CM_CEFUSE_CLKSTCTRL Register Field Descriptions .......................................................... 1405
8-175. CM_CEFUSE_CEFUSE_CLKCTRL Register Field Descriptions ................................................. 1406
8-176. PRM_IRQ REGISTERS ................................................................................................ 1407
8-177. REVISION_PRM Register Field Descriptions ....................................................................... 1408
8-178. PRM_IRQSTATUS_MPU Register Field Descriptions ............................................................. 1409
8-179. PRM_IRQENABLE_MPU Register Field Descriptions ............................................................. 1410
8-180. PRM_IRQSTATUS_M3 Register Field Descriptions ............................................................... 1411
8-181. PRM_IRQENABLE_M3 Register Field Descriptions ............................................................... 1412
8-182. PRM_PER REGISTERS ............................................................................................... 1413
8-183. RM_PER_RSTCTRL Register Field Descriptions .................................................................. 1414
8-184. PM_PER_PWRSTST Register Field Descriptions .................................................................. 1415
8-185. PM_PER_PWRSTCTRL Register Field Descriptions .............................................................. 1417
8-186. PRM_WKUP REGISTERS ............................................................................................. 1418
8-187. RM_WKUP_RSTCTRL Register Field Descriptions ................................................................ 1419
8-188. PM_WKUP_PWRSTCTRL Register Field Descriptions ............................................................ 1420
8-189. PM_WKUP_PWRSTST Register Field Descriptions ............................................................... 1421
8-190. RM_WKUP_RSTST Register Field Descriptions ................................................................... 1422

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8-191. PRM_MPU REGISTERS ............................................................................................... 1422

8-192. PM_MPU_PWRSTCTRL Register Field Descriptions .............................................................. 1424
8-193. PM_MPU_PWRSTST Register Field Descriptions ................................................................. 1426
8-194. RM_MPU_RSTST Register Field Descriptions...................................................................... 1427
8-195. PRM_DEVICE Registers ............................................................................................... 1427
8-196. PRM_RSTCTRL Register Field Descriptions ........................................................................ 1429
8-197. PRM_RSTTIME Register Field Descriptions ........................................................................ 1430
8-198. PRM_RSTST Register Field Descriptions ........................................................................... 1431
8-199. PRM_SRAM_COUNT Register Field Descriptions ................................................................. 1432
8-200. PRM_LDO_SRAM_CORE_SETUP Register Field Descriptions ................................................. 1433
8-201. PRM_LDO_SRAM_CORE_CTRL Register Field Descriptions ................................................... 1435
8-202. PRM_LDO_SRAM_MPU_SETUP Register Field Descriptions ................................................... 1436
8-203. PRM_LDO_SRAM_MPU_CTRL Register Field Descriptions ..................................................... 1438
8-204. PRM_RTC REGISTERS ............................................................................................... 1438
8-205. PM_RTC_PWRSTCTRL Register Field Descriptions .............................................................. 1439
8-206. PM_RTC_PWRSTST Register Field Descriptions .................................................................. 1440
8-207. PRM_GFX REGISTERS ............................................................................................... 1440
8-208. PM_GFX_PWRSTCTRL Register Field Descriptions .............................................................. 1442
8-209. RM_GFX_RSTCTRL Register Field Descriptions .................................................................. 1443
8-210. PM_GFX_PWRSTST Register Field Descriptions .................................................................. 1444
8-211. RM_GFX_RSTST Register Field Descriptions ...................................................................... 1445
8-212. PRM_CEFUSE REGISTERS .......................................................................................... 1445
8-213. PM_CEFUSE_PWRSTCTRL Register Field Descriptions ......................................................... 1446
8-214. PM_CEFUSE_PWRSTST Register Field Descriptions ............................................................ 1447
9-1. Pad Control Register Field Descriptions ............................................................................. 1449
9-2. Mode Selection .......................................................................................................... 1450
9-3. Pull Selection ............................................................................................................ 1450
9-4. Interconnect Priority Values ............................................................................................ 1452
9-5. Available Sources for Timer[5–7] and eCAP[0–2] Events ......................................................... 1455
9-6. Selection Mux Values ................................................................................................... 1456
9-7. DDR Slew Rate Control Settings ...................................................................................... 1457
9-8. DDR Impedance Control Settings ..................................................................................... 1457
9-9. DDR PHY to IO Pin Mapping .......................................................................................... 1457
9-10. CONTROL_MODULE REGISTERS .................................................................................. 1458
9-11. control_revision Register Field Descriptions ......................................................................... 1463
9-12. control_hwinfo Register Field Descriptions .......................................................................... 1464
9-13. control_sysconfig Register Field Descriptions ....................................................................... 1465
9-14. control_status Register Field Descriptions ........................................................................... 1466
9-15. control_emif_sdram_config Register Field Descriptions ........................................................... 1467
9-16. core_sldo_ctrl Register Field Descriptions ........................................................................... 1469
9-17. mpu_sldo_ctrl Register Field Descriptions ........................................................................... 1470
9-18. clk32kdivratio_ctrl Register Field Descriptions ...................................................................... 1471
9-19. bandgap_ctrl Register Field Descriptions ............................................................................ 1472
9-20. bandgap_trim Register Field Descriptions ........................................................................... 1473
9-21. pll_clkinpulow_ctrl Register Field Descriptions ...................................................................... 1474
9-22. mosc_ctrl Register Field Descriptions ................................................................................ 1475
9-23. deepsleep_ctrl Register Field Descriptions .......................................................................... 1476
9-24. dpll_pwr_sw_status Register Field Descriptions .................................................................... 1477
9-25. device_id Register Field Descriptions ................................................................................ 1478

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9-26. dev_feature Register Field Descriptions ............................................................................. 1479

9-27. init_priority_0 Register Field Descriptions............................................................................ 1480
9-28. init_priority_1 Register Field Descriptions............................................................................ 1481
9-29. tptc_cfg Register Field Descriptions .................................................................................. 1482
9-30. usb_ctrl0 Register Field Descriptions ................................................................................. 1483
9-31. usb_sts0 Register Field Descriptions ................................................................................. 1485
9-32. usb_ctrl1 Register Field Descriptions ................................................................................. 1486
9-33. usb_sts1 Register Field Descriptions ................................................................................. 1488
9-34. mac_id0_lo Register Field Descriptions .............................................................................. 1489
9-35. mac_id0_hi Register Field Descriptions .............................................................................. 1490
9-36. mac_id1_lo Register Field Descriptions .............................................................................. 1491
9-37. mac_id1_hi Register Field Descriptions .............................................................................. 1492
9-38. dcan_raminit Register Field Descriptions ............................................................................ 1493
9-39. usb_wkup_ctrl Register Field Descriptions .......................................................................... 1494
9-40. gmii_sel Register Field Descriptions .................................................................................. 1495
9-41. pwmss_ctrl Register Field Descriptions .............................................................................. 1496
9-42. mreqprio_0 Register Field Descriptions .............................................................................. 1497
9-43. mreqprio_1 Register Field Descriptions .............................................................................. 1498
9-44. hw_event_sel_grp1 Register Field Descriptions .................................................................... 1499
9-48. smrt_ctrl Register Field Descriptions ................................................................................. 1503
9-49. mpuss_hw_debug_sel Register Field Descriptions ................................................................. 1504
9-50. mpuss_hw_dbg_info Register Field Descriptions ................................................................... 1505
9-51. vdd_mpu_opp_050 Register Field Descriptions..................................................................... 1506
9-54. vdd_mpu_opp_turbo Register Field Descriptions ................................................................... 1509
9-55. vdd_core_opp_050 Register Field Descriptions..................................................................... 1510
9-56. vdd_core_opp_100 Register Field Descriptions..................................................................... 1511
9-57. bb_scale Register Field Descriptions ................................................................................. 1512
9-58. usb_vid_pid Register Field Descriptions ............................................................................. 1513
9-59. efuse_sma Register Field Descriptions .............................................................................. 1514
9-60. conf_<module>_<pin> Register Field Descriptions ................................................................. 1515
9-61. cqdetect_status Register Field Descriptions ......................................................................... 1516
9-62. ddr_io_ctrl Register Field Descriptions ............................................................................... 1517
9-63. vtp_ctrl Register Field Descriptions ................................................................................... 1518
9-64. vref_ctrl Register Field Descriptions .................................................................................. 1519
9-65. tpcc_evt_mux_0_3 Register Field Descriptions ..................................................................... 1520
9-66. tpcc_evt_mux_4_7 Register Field Descriptions ..................................................................... 1521
9-67. tpcc_evt_mux_8_11 Register Field Descriptions ................................................................... 1522
9-68. tpcc_evt_mux_12_15 Register Field Descriptions .................................................................. 1523

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9-81. timer_evt_capt Register Field Descriptions .......................................................................... 1536
9-82. ecap_evt_capt Register Field Descriptions .......................................................................... 1537
9-83. adc_evt_capt Register Field Descriptions............................................................................ 1538
9-84. reset_iso Register Field Descriptions ................................................................................. 1539
9-85. dpll_pwr_sw_ctrl Register Field Descriptions ........................................................................ 1540
9-86. ddr_cke_ctrl Register Field Descriptions ............................................................................. 1542
9-87. sma2 Register Field Descriptions ..................................................................................... 1543
9-88. m3_txev_eoi Register Field Descriptions ............................................................................ 1544
9-89. ipc_msg_reg0 Register Field Descriptions ........................................................................... 1545
9-97. ddr_cmd0_ioctrl Register Field Descriptions ........................................................................ 1553
9-100. ddr_data0_ioctrl Register Field Descriptions ........................................................................ 1557
9-101. ddr_data1_ioctrl Register Field Descriptions ........................................................................ 1559
10-1. L3 Master — Slave Connectivity ...................................................................................... 1564
11-1. TPCC Connectivity Attributes .......................................................................................... 1571
11-2. TPCC Clock Signals .................................................................................................... 1571
11-3. TPTC Connectivity Attributes .......................................................................................... 1572
11-4. TPTC Clock Signals..................................................................................................... 1572
11-5. EDMA3 Parameter RAM Contents .................................................................................... 1580
11-6. EDMA3 Channel Parameter Description ............................................................................. 1582
11-7. Channel Options Parameters (OPT) Field Descriptions ........................................................... 1583
11-8. Dummy and Null Transfer Request ................................................................................... 1587
11-9. Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set) .................................... 1588
11-10. Expected Number of Transfers for Non-Null Transfer .............................................................. 1594
11-11. Shadow Region Registers ............................................................................................. 1598
11-12. EDMA Shadow Regions ................................................................................................ 1598
11-13. Chain Event Triggers ................................................................................................... 1600
11-14. EDMA3 Transfer Completion Interrupts .............................................................................. 1600
11-15. EDMA3 Error Interrupts ................................................................................................ 1601
11-16. Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping ................................................ 1601
11-17. Number of Interrupts .................................................................................................... 1602
11-18. Allowed Accesses ....................................................................................................... 1607
11-19. MPPA Registers to Region Assignment .............................................................................. 1607
11-20. Example Access Denied ............................................................................................... 1608
11-21. Example Access Allowed............................................................................................... 1609

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11-22. Read/Write Command Optimization Rules........................................................................... 1613

11-23. EDMA3 Transfer Controller Configurations .......................................................................... 1615
11-24. Direct Mapped ........................................................................................................... 1635
11-25. Crossbar Mapped ....................................................................................................... 1636
11-26. EDMA3CC Registers ................................................................................................... 1638
11-27. PID Register Field Descriptions ....................................................................................... 1641
11-28. CCCFG Register Field Descriptions .................................................................................. 1642
11-29. SYSCONFIG Register Field Descriptions ............................................................................ 1644
11-30. DCHMAP_0 to DCHMAP_63 Register Field Descriptions ......................................................... 1645
11-31. QCHMAP_0 to QCHMAP_7 Register Field Descriptions .......................................................... 1646
11-32. DMAQNUM_0 to DMAQNUM_7 Register Field Descriptions ..................................................... 1647
11-33. QDMAQNUM Register Field Descriptions ........................................................................... 1652
11-34. QUEPRI Register Field Descriptions ................................................................................. 1655
11-35. EMR Register Field Descriptions ...................................................................................... 1656
11-36. EMRH Register Field Descriptions .................................................................................... 1657
11-37. EMCR Register Field Descriptions .................................................................................... 1658
11-38. EMCRH Register Field Descriptions .................................................................................. 1659
11-39. QEMR Register Field Descriptions.................................................................................... 1660
11-40. QEMCR Register Field Descriptions.................................................................................. 1661
11-41. CCERR Register Field Descriptions .................................................................................. 1662
11-42. CCERRCLR Register Field Descriptions ............................................................................. 1663
11-43. EEVAL Register Field Descriptions ................................................................................... 1664
11-44. DRAE0 Register Field Descriptions ................................................................................... 1665
11-45. DRAEH0 Register Field Descriptions ................................................................................. 1666
11-60. QRAE_0 to QRAE_7 Register Field Descriptions .................................................................. 1681
11-61. Q0E0 Register Field Descriptions ..................................................................................... 1682

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11-71. Q0E10 Register Field Descriptions ................................................................................... 1692

11-103. Q2E10 Register Field Descriptions .................................................................................. 1724
11-109. QSTAT_0 to QSTAT_2 Register Field Descriptions .............................................................. 1730
11-110. QWMTHRA Register Field Descriptions ............................................................................ 1731
11-111. CCSTAT Register Field Descriptions ............................................................................... 1732
11-112. MPFAR Register Field Descriptions ................................................................................. 1734
11-113. MPFSR Register Field Descriptions ................................................................................. 1735
11-114. MPFCR Register Field Descriptions ................................................................................. 1736
11-115. MPPAG Register Field Descriptions ................................................................................ 1737
11-116. MPPA_0 to MPPA_7 Register Field Descriptions ................................................................. 1738
11-117. ER Register Field Descriptions ...................................................................................... 1739
11-118. ERH Register Field Descriptions..................................................................................... 1740
11-119. ECR Register Field Descriptions..................................................................................... 1741

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11-120. ECRH Register Field Descriptions................................................................................... 1742

11-121. ESR Register Field Descriptions ..................................................................................... 1743
11-122. ESRH Register Field Descriptions ................................................................................... 1744
11-123. CER Register Field Descriptions..................................................................................... 1745
11-124. CERH Register Field Descriptions................................................................................... 1746
11-125. EER Register Field Descriptions ..................................................................................... 1747
11-126. EERH Register Field Descriptions ................................................................................... 1748
11-127. EECR Register Field Descriptions ................................................................................... 1749
11-128. EECRH Register Field Descriptions ................................................................................. 1750
11-129. EESR Register Field Descriptions ................................................................................... 1751
11-130. EESRH Register Field Descriptions ................................................................................. 1752
11-131. SER Register Field Descriptions ..................................................................................... 1753
11-132. SERH Register Field Descriptions ................................................................................... 1754
11-133. SECR Register Field Descriptions ................................................................................... 1755
11-134. SECRH Register Field Descriptions ................................................................................. 1756
11-135. IER Register Field Descriptions ...................................................................................... 1757
11-136. IERH Register Field Descriptions .................................................................................... 1758
11-137. IECR Register Field Descriptions .................................................................................... 1759
11-138. IECRH Register Field Descriptions .................................................................................. 1760
11-139. IESR Register Field Descriptions .................................................................................... 1761
11-140. IESRH Register Field Descriptions .................................................................................. 1762
11-141. IPR Register Field Descriptions ...................................................................................... 1763
11-142. IPRH Register Field Descriptions .................................................................................... 1764
11-143. ICR Register Field Descriptions...................................................................................... 1765
11-144. ICRH Register Field Descriptions .................................................................................... 1766
11-145. IEVAL Register Field Descriptions................................................................................... 1767
11-146. QER Register Field Descriptions .................................................................................... 1768
11-147. QEER Register Field Descriptions................................................................................... 1769
11-148. QEECR Register Field Descriptions ................................................................................. 1770
11-149. QEESR Register Field Descriptions ................................................................................. 1771
11-150. QSER Register Field Descriptions................................................................................... 1772
11-151. QSECR Register Field Descriptions ................................................................................. 1773
11-152. EDMA3TC Registers .................................................................................................. 1773
11-153. PID Register Field Descriptions ...................................................................................... 1775
11-154. TCCFG Register Field Descriptions ................................................................................. 1776
11-155. SYSCONFIG Register Field Descriptions .......................................................................... 1777
11-156. TCSTAT Register Field Descriptions ................................................................................ 1778
11-157. ERRSTAT Register Field Descriptions .............................................................................. 1780
11-158. ERREN Register Field Descriptions ................................................................................. 1781
11-159. ERRCLR Register Field Descriptions ............................................................................... 1782
11-160. ERRDET Register Field Descriptions ............................................................................... 1783
11-161. ERRCMD Register Field Descriptions .............................................................................. 1784
11-162. RDRATE Register Field Descriptions ............................................................................... 1785
11-163. SAOPT Register Field Descriptions ................................................................................. 1786
11-164. SASRC Register Field Descriptions ................................................................................. 1788
11-165. SACNT Register Field Descriptions ................................................................................. 1789
11-166. SADST Register Field Descriptions ................................................................................. 1790
11-167. SABIDX Register Field Descriptions ................................................................................ 1791
11-168. SAMPPRXY Register Field Descriptions ........................................................................... 1792

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11-169. SACNTRLD Register Field Descriptions ............................................................................ 1793

11-170. SASRCBREF Register Field Descriptions .......................................................................... 1794
11-171. SADSTBREF Register Field Descriptions .......................................................................... 1795
11-172. DFCNTRLD Register Field Descriptions ............................................................................ 1796
11-173. DFSRCBREF Register Field Descriptions .......................................................................... 1797
11-174. DFDSTBREF Register Field Descriptions .......................................................................... 1798
11-175. DFOPT0 Register Field Descriptions................................................................................ 1799
11-176. DFSRC0 Register Field Descriptions ............................................................................... 1801
11-177. DFCNT0 Register Field Descriptions................................................................................ 1802
11-178. DFDST0 Register Field Descriptions ................................................................................ 1803
11-179. DFBIDX0 Register Field Descriptions ............................................................................... 1804
11-180. DFMPPRXY0 Register Field Descriptions .......................................................................... 1805
11-199. Debug List .............................................................................................................. 1827
12-1. TSC_ADC Connectivity Attributes .................................................................................... 1833
12-2. TSC_ADC Clock Signals ............................................................................................... 1834
12-3. TSC_ADC Pin List ...................................................................................................... 1834
12-4. TSC_ADC_SS Registers ............................................................................................... 1842
12-5. REVISION Register Field Descriptions ............................................................................... 1844
12-7. IRQSTATUS_RAW Register Field Descriptions .................................................................... 1846
12-8. IRQSTATUS Register Field Descriptions ............................................................................ 1848
12-9. IRQENABLE_SET Register Field Descriptions ..................................................................... 1850
12-10. IRQENABLE_CLR Register Field Descriptions ..................................................................... 1852
12-11. IRQWAKEUP Register Field Descriptions ........................................................................... 1854
12-12. DMAENABLE_SET Register Field Descriptions .................................................................... 1855
12-13. DMAENABLE_CLR Register Field Descriptions .................................................................... 1856
12-14. CTRL Register Field Descriptions..................................................................................... 1857
12-15. ADCSTAT Register Field Descriptions ............................................................................... 1858
12-16. ADCRANGE Register Field Descriptions ............................................................................ 1859
12-17. ADC_CLKDIV Register Field Descriptions ........................................................................... 1860
12-18. ADC_MISC Register Field Descriptions .............................................................................. 1861

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12-19. STEPENABLE Register Field Descriptions .......................................................................... 1862

12-20. IDLECONFIG Register Field Descriptions ........................................................................... 1863
12-21. TS_CHARGE_STEPCONFIG Register Field Descriptions ........................................................ 1865
12-22. TS_CHARGE_DELAY Register Field Descriptions ................................................................. 1867
12-23. STEPCONFIG1 Register Field Descriptions......................................................................... 1868
12-24. STEPDELAY1 Register Field Descriptions .......................................................................... 1870
12-41. STEPCONFIG10 Register Field Descriptions ....................................................................... 1895
12-42. STEPDELAY10 Register Field Descriptions ......................................................................... 1897
12-55. FIFO0COUNT Register Field Descriptions .......................................................................... 1916
12-56. FIFO0THRESHOLD Register Field Descriptions ................................................................... 1917
12-57. DMA0REQ Register Field Descriptions .............................................................................. 1918
12-58. FIFO1COUNT Register Field Descriptions .......................................................................... 1919
12-59. FIFO1THRESHOLD Register Field Descriptions ................................................................... 1920
12-60. DMA1REQ Register Field Descriptions .............................................................................. 1921
12-61. FIFO0DATA Register Field Descriptions ............................................................................. 1922
12-62. FIFO1DATA Register Field Descriptions ............................................................................. 1923
13-1. LCD Controller Connectivity Attributes ............................................................................... 1927
13-2. LCD Controller Clock Signals .......................................................................................... 1928
13-3. LCD Controller Pin List ................................................................................................. 1928
13-4. LCD External I/O Signals ............................................................................................... 1931
13-5. Register Configuration for DMA Engine Programming ............................................................. 1932

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13-6. LIDD I/O Name Map .................................................................................................... 1934

13-7. Operation Modes Supported by Raster Controller .................................................................. 1939
13-8. Bits-Per-Pixel Encoding for Palette Entry 0 Buffer .................................................................. 1942
13-9. Frame Buffer Size According to BPP ................................................................................. 1942
13-10. Color/Grayscale Intensities and Modulation Rates ................................................................. 1947
13-11. Number of Colors/Shades of Gray Available on Screen ........................................................... 1947
13-12. Highlander 0.8 Interrupt Module Control Registers ................................................................. 1953
13-13. LCD Registers ........................................................................................................... 1963
13-14. PID Register Field Descriptions ....................................................................................... 1964
13-15. CTRL Register Field Descriptions..................................................................................... 1965
13-16. LIDD_CTRL Register Field Descriptions ............................................................................. 1966
13-17. LIDD_CS0_CONF Register Field Descriptions...................................................................... 1968
13-18. LIDD_CS0_ADDR Register Field Descriptions...................................................................... 1969
13-19. LIDD_CS0_DATA Register Field Descriptions ...................................................................... 1970
13-20. LIDD_CS1_CONF Register Field Descriptions...................................................................... 1971
13-21. LIDD_CS1_ADDR Register Field Descriptions...................................................................... 1972
13-22. LIDD_CS1_DATA Register Field Descriptions ...................................................................... 1973
13-23. RASTER_CTRL Register Field Descriptions ........................................................................ 1974
13-24. RASTER_TIMING_0 Register Field Descriptions ................................................................... 1977
13-27. RASTER_SUBPANEL Register Field Descriptions ................................................................. 1981
13-28. RASTER_SUBPANEL2 Register Field Descriptions ............................................................... 1982
13-29. LCDDMA_CTRL Register Field Descriptions ........................................................................ 1983
13-30. LCDDMA_FB0_BASE Register Field Descriptions ................................................................. 1985
13-31. LCDDMA_FB0_CEILING Register Field Descriptions ............................................................. 1986
13-32. LCDDMA_FB1_BASE Register Field Descriptions ................................................................. 1987
13-33. LCDDMA_FB1_CEILING Register Field Descriptions ............................................................. 1988
13-38. IRQENABLE_CLEAR Register Field Descriptions .................................................................. 1996
13-39. CLKC_ENABLE Register Field Descriptions ........................................................................ 1998
13-40. CLKC_RESET Register Field Descriptions .......................................................................... 1999
14-1. Unsupported CPGMAC Features ..................................................................................... 2002
14-2. Ethernet Switch Connectivity Attributes .............................................................................. 2004
14-3. Ethernet Switch Clock Signals ......................................................................................... 2005
14-4. Ethernet Switch Pin List ................................................................................................ 2006
14-5. GMII Interface Signal Descriptions in MII (100/10Mbps) Mode ................................................... 2009
14-6. RMII Interface Signal Descriptions .................................................................................... 2010
14-7. RGMII Interface Signal Descriptions .................................................................................. 2011
14-8. VLAN Header Encapsulation Word Field Descriptions ............................................................. 2031
14-9. Learned Address Control Bits ......................................................................................... 2032
14-10. Free (Unused) Address Table Entry Bit Values ..................................................................... 2032
14-11. Multicast Address Table Entry Bit Values ............................................................................ 2033
14-12. VLAN/Multicast Address Table Entry Bit Values .................................................................... 2033
14-13. Unicast Address Table Entry Bit Values ............................................................................. 2034
14-14. OUI Unicast Address Table Entry Bit Values ........................................................................ 2035

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14-15. Unicast Address Table Entry Bit Values ............................................................................. 2036

14-16. VLAN Table Entry ....................................................................................................... 2037
14-17. Operations of Emulation Control Input and Register Bits .......................................................... 2047
14-18. Rx Statistics Summary.................................................................................................. 2056
14-19. Tx Statistics Summary .................................................................................................. 2059
14-20. Values of messageType field .......................................................................................... 2069
14-21. MDIO Read Frame Format............................................................................................. 2070
14-22. MDIO Write Frame Format ............................................................................................. 2070
14-23. CPSW_ALE REGISTERS .............................................................................................. 2078
14-24. IDVER Register Field Descriptions ................................................................................... 2079
14-25. CONTROL Register Field Descriptions .............................................................................. 2080
14-26. PRESCALE Register Field Descriptions ............................................................................. 2082
14-27. UNKNOWN_VLAN Register Field Descriptions ..................................................................... 2083
14-28. TBLCTL Register Field Descriptions.................................................................................. 2084
14-29. TBLW2 Register Field Descriptions ................................................................................... 2085
14-32. PORTCTL0 Register Field Descriptions.............................................................................. 2088
14-38. CPSW_CPDMA REGISTERS ......................................................................................... 2094
14-39. TX_IDVER Register Field Descriptions .............................................................................. 2096
14-40. TX_CONTROL Register Field Descriptions ......................................................................... 2097
14-41. TX_TEARDOWN Register Field Descriptions ....................................................................... 2098
14-42. RX_IDVER Register Field Descriptions .............................................................................. 2099
14-43. RX_CONTROL Register Field Descriptions ......................................................................... 2100
14-44. RX_TEARDOWN Register Field Descriptions ....................................................................... 2101
14-45. CPDMA_SOFT_RESET Register Field Descriptions ............................................................... 2102
14-46. DMACONTROL Register Field Descriptions ........................................................................ 2103
14-47. DMASTATUS Register Field Descriptions ........................................................................... 2105
14-48. RX_BUFFER_OFFSET Register Field Descriptions ............................................................... 2107
14-49. EMCONTROL Register Field Descriptions .......................................................................... 2108
14-50. TX_PRI0_RATE Register Field Descriptions ........................................................................ 2109
14-58. TX_INTSTAT_RAW Register Field Descriptions .................................................................... 2117
14-59. TX_INTSTAT_MASKED Register Field Descriptions............................................................... 2118
14-60. TX_INTMASK_SET Register Field Descriptions .................................................................... 2119
14-61. TX_INTMASK_CLEAR Register Field Descriptions ................................................................ 2120
14-62. CPDMA_IN_VECTOR Register Field Descriptions ................................................................. 2121
14-63. CPDMA_EOI_VECTOR Register Field Descriptions ............................................................... 2122

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14-64. RX_INTSTAT_RAW Register Field Descriptions ................................................................... 2123

14-65. RX_INTSTAT_MASKED Register Field Descriptions .............................................................. 2124
14-66. RX_INTMASK_SET Register Field Descriptions .................................................................... 2125
14-67. RX_INTMASK_CLEAR Register Field Descriptions ................................................................ 2127
14-68. DMA_INTSTAT_RAW Register Field Descriptions ................................................................. 2129
14-69. DMA_INTSTAT_MASKED Register Field Descriptions ............................................................ 2130
14-70. DMA_INTMASK_SET Register Field Descriptions ................................................................. 2131
14-71. DMA_INTMASK_CLEAR Register Field Descriptions .............................................................. 2132
14-72. RX0_PENDTHRESH Register Field Descriptions .................................................................. 2133
14-80. RX0_FREEBUFFER Register Field Descriptions ................................................................... 2141
14-88. CPSW_CPTS REGISTERS............................................................................................ 2148
14-89. CPTS_IDVER Register Field Descriptions ........................................................................... 2150
14-90. CPTS_CONTROL Register Field Descriptions ...................................................................... 2151
14-91. CPTS_TS_PUSH Register Field Descriptions ...................................................................... 2152
14-92. CPTS_TS_LOAD_VAL Register Field Descriptions ................................................................ 2153
14-93. CPTS_TS_LOAD_EN Register Field Descriptions ................................................................. 2154
14-94. CPTS_INTSTAT_RAW Register Field Descriptions ................................................................ 2155
14-95. CPTS_INTSTAT_MASKED Register Field Descriptions ........................................................... 2156
14-96. CPTS_INT_ENABLE Register Field Descriptions .................................................................. 2157
14-97. CPTS_EVENT_POP Register Field Descriptions ................................................................... 2158
14-98. CPTS_EVENT_LOW Register Field Descriptions .................................................................. 2159
14-99. CPTS_EVENT_HIGH Register Field Descriptions .................................................................. 2160
14-100. CPSW_STATS REGISTERS ......................................................................................... 2161
14-101. CPDMA_STATERAM REGISTERS ................................................................................. 2162
14-102. TX0_HDP Register Field Descriptions .............................................................................. 2164
14-110. RX0_HDP Register Field Descriptions .............................................................................. 2172

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14-118. TX0_CP Register Field Descriptions ................................................................................ 2180
14-126. RX0_CP Register Field Descriptions ................................................................................ 2188
14-134. CPSW_PORT Registers .............................................................................................. 2195
14-135. P0_CONTROL Register Field Descriptions ........................................................................ 2197
14-136. P0_MAX_BLKS Register Field Descriptions ....................................................................... 2198
14-137. P0_BLK_CNT Register Field Descriptions ......................................................................... 2199
14-138. P0_TX_IN_CTL Register Field Descriptions ....................................................................... 2200
14-139. P0_PORT_VLAN Register Field Descriptions ..................................................................... 2201
14-140. P0_TX_PRI_MAP Register Field Descriptions ..................................................................... 2202
14-141. P0_CPDMA_TX_PRI_MAP Register Field Descriptions ......................................................... 2203
14-142. P0_CPDMA_RX_CH_MAP Register Field Descriptions .......................................................... 2204
14-143. P0_RX_DSCP_PRI_MAP0 Register Field Descriptions .......................................................... 2205
14-157. P1_TS_SEQ_MTYPE Register Field Descriptions ................................................................ 2220
14-158. P1_SA_LO Register Field Descriptions ............................................................................. 2221
14-159. P1_SA_HI Register Field Descriptions .............................................................................. 2222
14-160. P1_SEND_PERCENT Register Field Descriptions................................................................ 2223

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14-175. P2_TS_SEQ_MTYPE Register Field Descriptions ................................................................ 2239
14-176. P2_SA_LO Register Field Descriptions ............................................................................. 2240
14-177. P2_SA_HI Register Field Descriptions .............................................................................. 2241
14-178. P2_SEND_PERCENT Register Field Descriptions................................................................ 2242
14-187. CPSW_SL Registers .................................................................................................. 2251
14-188. IDVER Register Field Descriptions .................................................................................. 2252
14-189. MACCONTROL Register Field Descriptions ....................................................................... 2253
14-190. MACSTATUS Register Field Descriptions.......................................................................... 2256
14-191. SOFT_RESET Register Field Descriptions......................................................................... 2257
14-192. RX_MAXLEN Register Field Descriptions .......................................................................... 2258
14-193. BOFFTEST Register Field Descriptions ............................................................................ 2259
14-194. RX_PAUSE Register Field Descriptions ............................................................................ 2260
14-195. TX_PAUSE Register Field Descriptions ............................................................................ 2261
14-196. EMCONTROL Register Field Descriptions ......................................................................... 2262
14-197. RX_PRI_MAP Register Field Descriptions ......................................................................... 2263
14-198. TX_GAP Register Field Descriptions................................................................................ 2264
14-199. CPSW_SS REGISTERS .............................................................................................. 2264
14-200. ID_VER Register Field Descriptions ................................................................................ 2265
14-201. CONTROL Register Field Descriptions ............................................................................. 2266
14-203. STAT_PORT_EN Register Field Descriptions ..................................................................... 2268
14-204. PTYPE Register Field Descriptions ................................................................................. 2269
14-205. SOFT_IDLE Register Field Descriptions............................................................................ 2270
14-206. THRU_RATE Register Field Descriptions .......................................................................... 2271
14-207. GAP_THRESH Register Field Descriptions ........................................................................ 2272
14-208. TX_START_WDS Register Field Descriptions ..................................................................... 2273
14-209. FLOW_CONTROL Register Field Descriptions .................................................................... 2274
14-210. VLAN_LTYPE Register Field Descriptions ......................................................................... 2275

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14-211. TS_LTYPE Register Field Descriptions ............................................................................. 2276

14-212. DLR_LTYPE Register Field Descriptions ........................................................................... 2277
14-213. CPSW_WR REGISTERS ............................................................................................. 2277
14-214. IDVER Register Field Descriptions .................................................................................. 2279
14-216. CONTROL Register Field Descriptions ............................................................................. 2281
14-217. INT_CONTROL Register Field Descriptions ....................................................................... 2282
14-218. C0_RX_THRESH_EN Register Field Descriptions ................................................................ 2283
14-219. C0_RX_EN Register Field Descriptions ............................................................................ 2284
14-220. C0_TX_EN Register Field Descriptions............................................................................. 2285
14-221. C0_MISC_EN Register Field Descriptions ......................................................................... 2286
14-230. C0_RX_THRESH_STAT Register Field Descriptions............................................................. 2295
14-231. C0_RX_STAT Register Field Descriptions ......................................................................... 2296
14-232. C0_TX_STAT Register Field Descriptions ......................................................................... 2297
14-233. C0_MISC_STAT Register Field Descriptions ...................................................................... 2298
14-242. C0_RX_IMAX Register Field Descriptions ......................................................................... 2307
14-243. C0_TX_IMAX Register Field Descriptions .......................................................................... 2308
14-248. RGMII_CTL Register Field Descriptions ............................................................................ 2313
14-249. MDIO Registers ........................................................................................................ 2314
14-250. MDIOVER Register Field Descriptions .............................................................................. 2314
14-251. MDIOCONTROL Register Field Descriptions ...................................................................... 2315
14-252. MDIOALIVE Register Field Descriptions............................................................................ 2316
14-253. MDIOLINK Register Field Descriptions ............................................................................. 2316
14-254. MDIOLINKINTRAW Register Field Descriptions................................................................... 2317
14-255. MDIOLINKINTMASKED Register Field Descriptions ............................................................. 2317
14-256. MDIOUSERINTRAW Register Field Descriptions ................................................................. 2318
14-257. MDIOUSERINTMASKED Register Field Descriptions ............................................................ 2318
14-258. MDIOUSERINTMASKSET Register Field Descriptions .......................................................... 2319
14-259. MDIOUSERINTMASKCLR Register Field Descriptions .......................................................... 2319

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14-260. MDIOUSERACCESS0 Register Field Descriptions ............................................................... 2320

14-261. MDIOUSERPHYSEL0 Register Field Descriptions................................................................ 2321
14-262. MDIOUSERACCESS1 Register Field Descriptions ............................................................... 2322
14-263. MDIOUSERPHYSEL1 Register Field Descriptions................................................................ 2323
15-1. Unsupported Features .................................................................................................. 2326
15-2. PWMSS Connectivity Attributes ....................................................................................... 2328
15-3. PWMSS Clock Signals ................................................................................................. 2329
15-4. PWMSS Pin List ......................................................................................................... 2329
15-5. PWMSS Registers ...................................................................................................... 2329
15-6. IDVER Register Field Descriptions ................................................................................... 2330
15-8. CLKCONFIG Register Field Descriptions ............................................................................ 2332
15-9. CLKSTATUS Register Field Descriptions ............................................................................ 2333
15-10. Submodule Configuration Parameters................................................................................ 2338
15-11. Time-Base Submodule Registers ..................................................................................... 2343
15-12. Key Time-Base Signals ................................................................................................. 2344
15-13. Counter-Compare Submodule Registers ............................................................................ 2352
15-14. Counter-Compare Submodule Key Signals .......................................................................... 2352
15-15. Action-Qualifier Submodule Registers ................................................................................ 2356
15-16. Action-Qualifier Submodule Possible Input Events ................................................................. 2357
15-17. Action-Qualifier Event Priority for Up-Down-Count Mode .......................................................... 2359
15-18. Action-Qualifier Event Priority for Up-Count Mode.................................................................. 2359
15-19. Action-Qualifier Event Priority for Down-Count Mode .............................................................. 2359
15-20. Behavior if CMPA/CMPB is Greater than the Period ............................................................... 2360
15-21. EPWMx Initialization for ............................................................................................... 2363
15-22. EPWMx Run Time Changes for ...................................................................................... 2363
15-33. Dead-Band Generator Submodule Registers........................................................................ 2374
15-34. Classical Dead-Band Operating Modes ............................................................................. 2376
15-35. PWM-Chopper Submodule Registers ................................................................................ 2378
15-36. Trip-Zone Submodule Registers ...................................................................................... 2383
15-37. Possible Actions On a Trip Event ..................................................................................... 2384
15-38. Event-Trigger Submodule Registers ................................................................................. 2386
15-39. Resolution for PWM and HRPWM .................................................................................... 2391
15-40. HRPWM Submodule Registers ........................................................................................ 2392
15-41. Relationship Between MEP Steps, PWM Frequency and Resolution ............................................ 2393
15-42. CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right)....................................................... 2394
15-43. SFO Library Version Comparison ..................................................................................... 2397
15-44. SFO Library Routines ................................................................................................... 2398
15-45. Factor Values ............................................................................................................ 2399

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15-46. SFO V5 Library Routines ............................................................................................... 2402

15-47. Software Functions ...................................................................................................... 2405
15-48. EPWM1 Initialization for ............................................................................................... 2413
15-63. EPWM Registers ........................................................................................................ 2433
15-64. TBCTL Register Field Descriptions ................................................................................... 2434
15-65. TBSTS Register Field Descriptions ................................................................................... 2436
15-66. TBPHSHR Register Field Descriptions ............................................................................... 2437
15-67. TBPHS Register Field Descriptions ................................................................................... 2438
15-68. TBCNT Register Field Descriptions ................................................................................... 2439
15-69. TBPRD Register Field Descriptions .................................................................................. 2440
15-70. CMPCTL Register Field Descriptions................................................................................. 2441
15-71. CMPAHR Register Field Descriptions ................................................................................ 2443
15-72. CMPA Register Field Descriptions .................................................................................... 2444
15-73. CMPB Register Field Descriptions .................................................................................... 2445
15-74. AQCTLA Register Field Descriptions ................................................................................. 2446
15-75. AQCTLB Register Field Descriptions ................................................................................. 2448
15-76. AQSFRC Register Field Descriptions ................................................................................ 2450
15-77. AQCSFRC Register Field Descriptions .............................................................................. 2451
15-78. DBCTL Register Field Descriptions ................................................................................... 2452
15-79. DBRED Register Field Descriptions .................................................................................. 2454
15-80. DBFED Register Field Descriptions .................................................................................. 2455
15-81. TZSEL Register Field Descriptions ................................................................................... 2456
15-82. TZCTL Register Field Descriptions ................................................................................... 2457
15-83. TZEINT Register Field Descriptions .................................................................................. 2458
15-84. TZFLG Register Field Descriptions ................................................................................... 2459
15-85. TZCLR Register Field Descriptions ................................................................................... 2460
15-86. TZFRC Register Field Descriptions ................................................................................... 2461
15-87. ETSEL Register Field Descriptions ................................................................................... 2462
15-88. ETPS Register Field Descriptions..................................................................................... 2463
15-89. ETFLG Register Field Descriptions ................................................................................... 2464
15-90. ETCLR Register Field Descriptions ................................................................................... 2465
15-91. ETFRC Register Field Descriptions ................................................................................... 2466
15-92. PCCTL Register Field Descriptions ................................................................................... 2467
15-93. HRCNFG Register Field Descriptions ................................................................................ 2468
15-94. ECAP Initialization for CAP Mode Absolute Time, Rising Edge Trigger ......................................... 2481

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15-95. ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger ........................... 2483
15-96. ECAP Initialization for CAP Mode Delta Time, Rising Edge Trigger ............................................. 2485
15-97. ECAP Initialization for CAP Mode Delta Time, Rising and Falling Edge Triggers .............................. 2487
15-98. ECAP Initialization for APWM Mode .................................................................................. 2489
15-99. ECAP1 Initialization for Multichannel PWM Generation with Synchronization .................................. 2491
15-100. ECAP2 Initialization for Multichannel PWM Generation with Synchronization................................. 2491
15-103. ECAP1 Initialization for Multichannel PWM Generation with Phase Control ................................... 2494
15-106. ECAP Registers ........................................................................................................ 2495
15-107. TSCTR Register Field Descriptions ................................................................................. 2496
15-108. CTRPHS Register Field Descriptions ............................................................................... 2497
15-109. CAP1 Register Field Descriptions ................................................................................... 2498
15-113. ECCTL1 Register Field Descriptions ................................................................................ 2502
15-114. ECCTL2 Register Field Descriptions ................................................................................ 2504
15-115. ECEINT Register Field Descriptions ................................................................................ 2506
15-116. ECFLG Register Field Descriptions ................................................................................. 2507
15-117. ECCLR Register Field Descriptions ................................................................................. 2508
15-118. ECFRC Register Field Descriptions ................................................................................. 2509
15-119. REVID Register Field Descriptions .................................................................................. 2510
15-120. Quadrature Decoder Truth Table ................................................................................... 2517
15-121. EQEP Registers ........................................................................................................ 2532
15-122. QPOSCNT Register Field Descriptions ............................................................................. 2533
15-123. QPOSINIT Register Field Descriptions ............................................................................. 2534
15-124. QPOSMAX Register Field Descriptions............................................................................. 2535
15-125. QPOSCMP Register Field Descriptions ............................................................................ 2536
15-126. QPOSILAT Register Field Descriptions ............................................................................. 2537
15-127. QPOSSLAT Register Field Descriptions ............................................................................ 2538
15-128. QPOSLAT Register Field Descriptions ............................................................................. 2539
15-129. QUTMR Register Field Descriptions ................................................................................ 2540
15-130. QUPRD Register Field Descriptions ................................................................................ 2541
15-131. QWDTMR Register Field Descriptions .............................................................................. 2542
15-132. QWDPRD Register Field Descriptions .............................................................................. 2543
15-133. QDECCTL Register Field Descriptions ............................................................................. 2544
15-134. QEPCTL Register Field Descriptions ............................................................................... 2545
15-135. QCAPCTL Register Field Descriptions ............................................................................. 2547
15-136. QPOSCTL Register Field Descriptions ............................................................................. 2548
15-137. QEINT Register Field Descriptions .................................................................................. 2549
15-138. QFLG Register Field Descriptions ................................................................................... 2550
15-139. QCLR Register Field Descriptions ................................................................................... 2551
15-140. QFRC Register Field Descriptions................................................................................... 2552
15-141. QEPSTS Register Field Descriptions ............................................................................... 2553
15-142. QCTMR Register Field Descriptions ................................................................................ 2554
15-143. QCPRD Register Field Descriptions ................................................................................ 2555

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15-144. QCTMRLAT Register Field Descriptions ........................................................................... 2556

15-145. QCPRDLAT Register Field Descriptions............................................................................ 2557
15-146. REVID Register Field Descriptions .................................................................................. 2558
16-1. USB Connectivity Attributes............................................................................................ 2563
16-2. USB Clock Signals ...................................................................................................... 2564
16-3. USB Pin List.............................................................................................................. 2564
16-4. PERI_TXCSR Register Bit Configuration for Bulk IN Transactions .............................................. 2580
16-5. PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions ........................................... 2582
16-6. PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions ..................................... 2584
16-7. PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions .................................. 2585
16-8. Isochronous OUT Error Handling: Peripheral Mode ................................................................ 2586
16-9. Packet Descriptor Word 0 (PD0) Bit Field Descriptions ............................................................ 2605
16-17. Buffer Descriptor Word 0 (BD0) Bit Field Descriptions ............................................................. 2608
16-25. Teardown Descriptor Word 0 Bit Field Descriptions ................................................................ 2610
16-26. Teardown Descriptor Words 1 to 7 Bit Field Descriptions ......................................................... 2610
16-27. Queue-Endpoint Assignments ......................................................................................... 2611
16-28. 53 Bytes Test Packet Content ......................................................................................... 2627
16-29. USBSS Registers ....................................................................................................... 2630
16-30. REVREG Register Field Descriptions ................................................................................ 2632
16-32. IRQSTATRAW Register Field Descriptions .......................................................................... 2634
16-33. IRQSTAT Register Field Descriptions ................................................................................ 2635
16-34. IRQENABLER Register Field Descriptions .......................................................................... 2636
16-35. IRQCLEARR Register Field Descriptions ............................................................................ 2637
16-36. IRQDMATHOLDTX00 Register Field Descriptions ................................................................. 2638
16-40. IRQDMATHOLDRX00 Register Field Descriptions ................................................................. 2642

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16-52. IRQDMAENABLE0 Register Field Descriptions ..................................................................... 2654
16-53. IRQDMAENABLE1 Register Field Descriptions ..................................................................... 2656
16-54. IRQFRAMETHOLDTX00 Register Field Descriptions .............................................................. 2658
16-58. IRQFRAMETHOLDRX00 Register Field Descriptions ............................................................. 2662
16-70. IRQFRAMEENABLE0 Register Field Descriptions ................................................................. 2674
16-71. IRQFRAMEENABLE1 Register Field Descriptions ................................................................. 2675
16-72. USB0_CTRL Registers ................................................................................................. 2676
16-73. USB0REV Register Field Descriptions ............................................................................... 2677
16-74. USB0CTRL Register Field Descriptions.............................................................................. 2678
16-75. USB0STAT Register Field Descriptions .............................................................................. 2680
16-76. USB0IRQMSTAT Register Field Descriptions ....................................................................... 2681
16-77. USB0IRQSTATRAW0 Register Field Descriptions ................................................................. 2682
16-78. USB0IRQSTATRAW1 Register Field Descriptions ................................................................. 2684
16-79. USB0IRQSTAT0 Register Field Descriptions ....................................................................... 2686
16-80. USB0IRQSTAT1 Register Field Descriptions ....................................................................... 2688
16-81. USB0IRQENABLESET0 Register Field Descriptions .............................................................. 2690
16-82. USB0IRQENABLESET1 Register Field Descriptions .............................................................. 2692
16-83. USB0IRQENABLECLR0 Register Field Descriptions .............................................................. 2694
16-84. USB0IRQENABLECLR1 Register Field Descriptions .............................................................. 2696
16-85. USB0TXMODE Register Field Descriptions ......................................................................... 2698
16-86. USB0RXMODE Register Field Descriptions ......................................................................... 2700
16-87. USB0GENRNDISEP1 Register Field Descriptions ................................................................. 2704

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16-96. USB0GENRNDISEP10 Register Field Descriptions ................................................................ 2713

16-100. USB0GENRNDISEP14 Register Field Descriptions .............................................................. 2717
16-102. USB0AUTOREQ Register Field Descriptions ...................................................................... 2719
16-103. USB0SRPFIXTIME Register Field Descriptions ................................................................... 2721
16-104. USB0_TDOWN Register Field Descriptions ....................................................................... 2722
16-105. USB0UTMI Register Field Descriptions............................................................................. 2723
16-106. USB0MGCUTMILB Register Field Descriptions ................................................................... 2724
16-107. USB0MODE Register Field Descriptions ........................................................................... 2725
16-108. USB1_CTRL Registers ................................................................................................ 2725
16-109. USB1REV Register Field Descriptions .............................................................................. 2727
16-110. USB1CTRL Register Field Descriptions ............................................................................ 2728
16-111. USB1STAT Register Field Descriptions ............................................................................ 2730
16-112. USB1IRQMSTAT Register Field Descriptions ..................................................................... 2731
16-113. USB1IRQSTATRAW0 Register Field Descriptions ................................................................ 2732
16-114. USB1IRQSTATRAW1 Register Field Descriptions ................................................................ 2734
16-115. USB1IRQSTAT0 Register Field Descriptions ...................................................................... 2736
16-116. USB1IRQSTAT1 Register Field Descriptions ...................................................................... 2738
16-117. USB1IRQENABLESET0 Register Field Descriptions ............................................................. 2740
16-118. USB1IRQENABLESET1 Register Field Descriptions ............................................................. 2742
16-119. USB1IRQENABLECLR0 Register Field Descriptions ............................................................. 2744
16-120. USB1IRQENABLECLR1 Register Field Descriptions ............................................................. 2746
16-121. USB1TXMODE Register Field Descriptions ........................................................................ 2748
16-122. USB1RXMODE Register Field Descriptions ....................................................................... 2750
16-138. USB1AUTOREQ Register Field Descriptions ...................................................................... 2767
16-139. USB1SRPFIXTIME Register Field Descriptions ................................................................... 2769
16-140. USB1TDOWN Register Field Descriptions ......................................................................... 2770
16-141. USB1UTMI Register Field Descriptions............................................................................. 2771
16-142. USB1UTMILB Register Field Descriptions ......................................................................... 2772
16-143. USB1MODE Register Field Descriptions ........................................................................... 2773
16-144. USB2PHY Registers ................................................................................................... 2773

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16-145. Termination_control Register Field Descriptions .................................................................. 2775

16-146. RX_CALIB Register Field Descriptions ............................................................................. 2776
16-147. DLLHS_2 Register Field Descriptions............................................................................... 2778
16-148. RX_TEST_2 Register Field Descriptions ........................................................................... 2779
16-149. CHRG_DET Register Field Descriptions ........................................................................... 2780
16-150. PWR_CNTL Register Field Descriptions ........................................................................... 2782
16-151. UTMI_INTERFACE_CNTL_1 Register Field Descriptions ....................................................... 2783
16-152. UTMI_INTERFACE_CNTL_2 Register Field Descriptions ....................................................... 2784
16-153. BIST Register Field Descriptions .................................................................................... 2786
16-154. BIST_CRC Register Field Descriptions ............................................................................. 2787
16-155. CDR_BIST2 Register Field Descriptions ........................................................................... 2788
16-156. GPIO Register Field Descriptions ................................................................................... 2789
16-157. DLLHS Register Field Descriptions.................................................................................. 2790
16-158. USB2PHYCM_CONFIG Register Field Descriptions ............................................................. 2792
16-159. AD_INTERFACE_REG1 Register Field Descriptions ............................................................. 2793
16-162. ANA_CONFIG2 Register Field Descriptions ....................................................................... 2798
16-163. CPPI_DMA REGISTERS ............................................................................................. 2798
16-164. DMAREVID Register Field Descriptions ............................................................................ 2802
16-165. TDFDQ Register Field Descriptions ................................................................................. 2803
16-166. DMAEMU Register Field Descriptions .............................................................................. 2804
16-167. TXGCR0 Register Field Descriptions ............................................................................... 2805
16-168. RXGCR0 Register Field Descriptions ............................................................................... 2806
16-169. RXHPCRA0 Register Field Descriptions............................................................................ 2808
16-170. RXHPCRB0 Register Field Descriptions............................................................................ 2809

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16-207. TXGCR10 Register Field Descriptions .............................................................................. 2855
16-208. RXGCR10 Register Field Descriptions ............................................................................. 2856
16-209. RXHPCRA10 Register Field Descriptions .......................................................................... 2858
16-210. RXHPCRB10 Register Field Descriptions .......................................................................... 2859

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16-287. CPPI_DMA_SCHEDULER Registers ............................................................................... 2954
16-288. DMA_SCHED_CTRL Register Field Descriptions ................................................................. 2955
16-289. WORD_0 to WORD_63 Register Field Descriptions .............................................................. 2956
16-290. QUEUE_MGR REGISTERS .......................................................................................... 2957
16-291. QMGRREVID Register Field Descriptions.......................................................................... 2982

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16-292. QMGRRST Register Field Descriptions ............................................................................ 2983

16-293. FDBSC0 Register Field Descriptions................................................................................ 2984
16-301. LRAM0BASE Register Field Descriptions .......................................................................... 2992
16-302. LRAM0SIZE Register Field Descriptions ........................................................................... 2993
16-303. LRAM1BASE Register Field Descriptions .......................................................................... 2994
16-304. PEND0 Register Field Descriptions ................................................................................. 2995
16-309. QMEMRBASE0 Register Field Descriptions ....................................................................... 3000
16-310. QMEMCTRL0 Register Field Descriptions ......................................................................... 3001
16-325. QUEUE_0_A Register Field Descriptions .......................................................................... 3016
16-326. QUEUE_0_B Register Field Descriptions .......................................................................... 3017
16-327. QUEUE_0_C Register Field Descriptions .......................................................................... 3018
16-328. QUEUE_0_D Register Field Descriptions .......................................................................... 3019

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16-365. QUEUE_10_A Register Field Descriptions ......................................................................... 3056
16-366. QUEUE_10_B Register Field Descriptions ......................................................................... 3057
16-367. QUEUE_10_C Register Field Descriptions ......................................................................... 3058
16-368. QUEUE_10_D Register Field Descriptions ......................................................................... 3059

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16-725. QUEUE_100_A Register Field Descriptions ....................................................................... 3416
16-726. QUEUE_100_B Register Field Descriptions ....................................................................... 3417
16-727. QUEUE_100_C Register Field Descriptions ....................................................................... 3418
16-728. QUEUE_100_D Register Field Descriptions ....................................................................... 3419

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16-949. QUEUE_0_STATUS_A Register Field Descriptions .............................................................. 3640
16-950. QUEUE_0_STATUS_B Register Field Descriptions .............................................................. 3641
16-951. QUEUE_0_STATUS_C Register Field Descriptions .............................................................. 3642

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16-979. QUEUE_10_STATUS_A Register Field Descriptions ............................................................. 3670
16-980. QUEUE_10_STATUS_B Register Field Descriptions ............................................................. 3671
16-981. QUEUE_10_STATUS_C Register Field Descriptions............................................................. 3672
16-1000. QUEUE_17_STATUS_A Register Field Descriptions ........................................................... 3691
16-1001. QUEUE_17_STATUS_B Register Field Descriptions ........................................................... 3692
16-1002. QUEUE_17_STATUS_C Register Field Descriptions ........................................................... 3693

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16-1249. QUEUE_100_STATUS_A Register Field Descriptions .......................................................... 3940
16-1250. QUEUE_100_STATUS_B Register Field Descriptions .......................................................... 3941
16-1251. QUEUE_100_STATUS_C Register Field Descriptions.......................................................... 3942

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17-1. Mailbox Clock Signals .................................................................................................. 4111
17-2. Mailbox Implementation ................................................................................................ 4111

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17-3. Local Power Management Features .................................................................................. 4112

17-4. Interrupt Events .......................................................................................................... 4113
17-5. Global Initialization of Surrounding Modules for System Mailbox ................................................. 4115
17-6. Mailbox Global Initialization ............................................................................................ 4116
17-7. Sending a Message (Polling Method) ................................................................................ 4116
17-8. Sending a Message (Interrupt Method) .............................................................................. 4116
17-9. Receiving a Message (Polling Method) .............................................................................. 4117
17-10. Receiving a Message (Interrupt Method) ............................................................................ 4117
17-11. Events Servicing in Sending Mode ................................................................................... 4117
17-12. Events Servicing in Receiving Mode ................................................................................. 4117
17-13. MAILBOX REGISTERS ................................................................................................ 4118
17-14. REVISION Register Field Descriptions ............................................................................... 4121
17-16. MESSAGE_0 Register Field Descriptions ........................................................................... 4123
17-24. FIFOSTATUS_0 Register Field Descriptions ........................................................................ 4131
17-32. MSGSTATUS_0 Register Field Descriptions ........................................................................ 4139
17-40. IRQSTATUS_RAW_0 Register Field Descriptions ................................................................. 4147
17-41. IRQSTATUS_CLR_0 Register Field Descriptions .................................................................. 4149
17-42. IRQENABLE_SET_0 Register Field Descriptions .................................................................. 4151
17-43. IRQENABLE_CLR_0 Register Field Descriptions .................................................................. 4153

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17-56. SPINLOCK REGISTERS ............................................................................................... 4179
17-57. REV Register Field Descriptions ...................................................................................... 4182
17-59. SYSTATUS Register Field Descriptions ............................................................................. 4184
17-60. LOCK_REG_0 Register Field Descriptions .......................................................................... 4185
17-70. LOCK_REG_10 Register Field Descriptions ........................................................................ 4195
18-1. Unsupported MMCHS Features ....................................................................................... 4218
18-2. MMCHS Connectivity Attributes ....................................................................................... 4220
18-3. MMCHS Clock Signals ................................................................................................. 4221
18-4. MMCHS Pin List ......................................................................................................... 4221
18-5. DAT Line Direction for Data Transfer Modes ........................................................................ 4221
18-6. ADPDATDIROQ and ADPDATDIRLS Signal States ............................................................... 4222
18-7. MMC/SD/SDIO Controller Pins and Descriptions ................................................................... 4224
18-8. Response Type Summary ............................................................................................. 4227
18-9. Local Power Management Features .................................................................................. 4232

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18-10. Clock Activity Settings .................................................................................................. 4232

18-11. Events..................................................................................................................... 4233
18-12. Memory Size, BLEN, and Buffer Relationship ....................................................................... 4240
18-13. MMC, SD, SDIO Responses in the SD_RSPxx Registers......................................................... 4241
18-14. CC and TC Values Upon Error Detected ............................................................................ 4242
18-15. MMC/SD/SDIO Controller Transfer Stop Command Summary ................................................... 4249
18-16. MMC/SD/SDIO Hardware Status Features .......................................................................... 4255
18-17. Global Init for Surrounding Modules ................................................................................. 4256
18-18. MMC/SD/SDIO Controller Wake-Up Configuration ................................................................. 4257
18-19. MULTIMEDIA_CARD Registers ....................................................................................... 4261
18-20. SD_SYSCONFIG Register Field Descriptions ...................................................................... 4262
18-21. SD_SYSSTATUS Register Field Descriptions ...................................................................... 4264
18-22. SD_CSRE Register Field Descriptions ............................................................................... 4265
18-23. SD_SYSTEST Register Field Descriptions .......................................................................... 4266
18-24. SD_CON Register Field Descriptions ................................................................................ 4270
18-25. SD_PWCNT Register Field Descriptions ............................................................................ 4274
18-26. SD_SDMASA Register Field Descriptions ........................................................................... 4275
18-27. SD_BLK Register Field Descriptions ................................................................................. 4276
18-28. SD_ARG Register Field Descriptions................................................................................. 4277
18-29. SD_CMD Register Field Descriptions ................................................................................ 4279
18-30. SD_RSP10 Register Field Descriptions .............................................................................. 4283
18-34. SD_DATA Register Field Descriptions ............................................................................... 4287
18-35. SD_PSTATE Register Field Descriptions ............................................................................ 4288
18-36. SD_HCTL Register Field Descriptions ............................................................................... 4291
18-37. SD_SYSCTL Register Field Descriptions ............................................................................ 4294
18-38. SD_STAT Register Field Descriptions ............................................................................... 4296
18-39. SD_IE Register Field Descriptions .................................................................................... 4301
18-40. SD_ISE Register Field Descriptions .................................................................................. 4304
18-41. SD_AC12 Register Field Descriptions ................................................................................ 4307
18-42. SD_CAPA Register Field Descriptions ............................................................................... 4309
18-43. SD_CUR_CAPA Register Field Descriptions ........................................................................ 4311
18-44. SD_FE Register Field Descriptions ................................................................................... 4312
18-45. SD_ADMAES Register Field Descriptions ........................................................................... 4314
18-46. SD_ADMASAL Register Field Descriptions ......................................................................... 4315
18-47. SD_ADMASAH Register Field Descriptions ......................................................................... 4316
18-48. SD_REV Register Field Descriptions ................................................................................. 4317
19-1. Unsupported UART Features .......................................................................................... 4320
19-2. UART0 Connectivity Attributes ........................................................................................ 4321
19-3. UART1–5 Connectivity Attributes ..................................................................................... 4322
19-4. UART0 Clock Signals ................................................................................................... 4322
19-5. UART1–5 Clock Signals ................................................................................................ 4322
19-6. UART Mode Baud and Error Rates ................................................................................... 4323
19-7. IrDA Mode Baud and Error Rates ..................................................................................... 4323
19-8. UART Pin List ............................................................................................................ 4324
19-9. UART Muxing Control .................................................................................................. 4324
19-10. Local Power-Management Features .................................................................................. 4328

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19-11. UART Mode Interrupts .................................................................................................. 4328

19-12. IrDA Mode Interrupts .................................................................................................... 4329
19-13. CIR Mode Interrupts .................................................................................................... 4330
19-14. TX FIFO Trigger Level Setting Summary ............................................................................ 4332
19-15. RX FIFO Trigger Level Setting Summary ............................................................................ 4332
19-16. UART/IrDA/CIR Register Access Mode Programming (Using UART_LCR) .................................... 4339
19-17. Subconfiguration Mode A Summary .................................................................................. 4340
19-18. Subconfiguration Mode B Summary .................................................................................. 4340
19-19. Suboperational Mode Summary ....................................................................................... 4340
19-20. UART/IrDA/CIR Register Access Mode Overview .................................................................. 4340
19-21. UART Mode Selection .................................................................................................. 4341
19-22. UART Mode Register Overview ...................................................................................... 4342
19-23. IrDA Mode Register Overview ........................................................................................ 4343
19-24. CIR Mode Register Overview ......................................................................................... 4344
19-25. UART Baud Rate Settings (48-MHz Clock) .......................................................................... 4347
19-26. UART Parity Bit Encoding .............................................................................................. 4347
19-27. UART_EFR[3:0] Software Flow Control Options .................................................................... 4348
19-28. IrDA Baud Rate Settings ............................................................................................... 4358
19-29. UART Registers ......................................................................................................... 4377
19-30. THR Register Field Descriptions ...................................................................................... 4379
19-31. RHR Register Field Descriptions ...................................................................................... 4380
19-32. DLL Register Field Descriptions ....................................................................................... 4381
19-33. IER_IRDA Register Field Descriptions ............................................................................... 4382
19-34. IER_CIR Register Field Descriptions ................................................................................. 4383
19-35. IER_UART Register Field Descriptions .............................................................................. 4384
19-36. DLH Register Field Descriptions ...................................................................................... 4385
19-37. EFR Register Field Descriptions ...................................................................................... 4386
19-38. IIR_UART Register Field Descriptions ............................................................................... 4388
19-39. IIR_CIR Register Field Descriptions .................................................................................. 4389
19-40. FCR Register Field Descriptions ...................................................................................... 4390
19-41. IIR_IRDA Register Field Descriptions ................................................................................ 4391
19-42. LCR Register Field Descriptions ...................................................................................... 4392
19-43. MCR Register Field Descriptions ..................................................................................... 4393
19-44. XON1_ADDR1 Register Field Descriptions .......................................................................... 4394
19-45. XON2_ADDR2 Register Field Descriptions .......................................................................... 4395
19-46. LSR_CIR Register Field Descriptions ................................................................................ 4396
19-47. LSR_IRDA Register Field Descriptions .............................................................................. 4397
19-48. LSR_UART Register Field Descriptions.............................................................................. 4399
19-49. TCR Register Field Descriptions ...................................................................................... 4401
19-50. MSR Register Field Descriptions ...................................................................................... 4402
19-51. XOFF1 Register Field Descriptions ................................................................................... 4403
19-52. SPR Register Field Descriptions ...................................................................................... 4404
19-53. TLR Register Field Descriptions....................................................................................... 4405
19-54. XOFF2 Register Field Descriptions ................................................................................... 4406
19-55. MDR1 Register Field Descriptions .................................................................................... 4407
19-57. TXFLL Register Field Descriptions.................................................................................... 4409
19-58. SFLSR Register Field Descriptions ................................................................................... 4410
19-59. RESUME Register Field Descriptions ................................................................................ 4411

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19-60. TXFLH Register Field Descriptions ................................................................................... 4412

19-61. RXFLL Register Field Descriptions ................................................................................... 4413
19-62. SFREGL Register Field Descriptions ................................................................................. 4414
19-63. SFREGH Register Field Descriptions ................................................................................ 4415
19-64. RXFLH Register Field Descriptions ................................................................................... 4416
19-65. BLR Register Field Descriptions ...................................................................................... 4417
19-66. UASR Register Field Descriptions .................................................................................... 4418
19-67. ACREG Register Field Descriptions .................................................................................. 4419
19-68. SCR Register Field Descriptions ...................................................................................... 4420
19-69. SSR Register Field Descriptions ...................................................................................... 4421
19-70. EBLR Register Field Descriptions..................................................................................... 4422
19-71. MVR Register Field Descriptions ...................................................................................... 4423
19-72. SYSC Register Field Descriptions .................................................................................... 4424
19-73. SYSS Register Field Descriptions .................................................................................... 4425
19-74. WER Register Field Descriptions ..................................................................................... 4426
19-75. CFPS Register Field Descriptions .................................................................................... 4427
19-76. RXFIFO_LVL Register Field Descriptions ........................................................................... 4428
19-77. TXFIFO_LVL Register Field Descriptions ............................................................................ 4429
19-78. IER2 Register Field Descriptions ...................................................................................... 4430
19-79. ISR2 Register Field Descriptions ...................................................................................... 4431
19-80. FREQ_SEL Register Field Descriptions.............................................................................. 4432
19-82. TX_DMA_THRESHOLD Register Field Descriptions............................................................... 4434
20-1. Timer Resolution and Maximum Range .............................................................................. 4437
20-2. Timer[0] Connectivity Attributes ....................................................................................... 4439
20-3. Timer[2–7] Connectivity Attributes .................................................................................... 4440
20-4. Timer Clock Signals ..................................................................................................... 4441
20-5. Timer Pin List ............................................................................................................ 4441
20-6. Prescaler Functionality ................................................................................................. 4444
20-7. Prescaler Clock Ratios Value .......................................................................................... 4447
20-8. Value and Corresponding Interrupt Period ........................................................................... 4447
20-9. OCP Error Reporting .................................................................................................... 4448
20-10. TIMER Registers ........................................................................................................ 4451
20-11. TIDR Register Field Descriptions ..................................................................................... 4452
20-12. TIOCP_CFG Register Field Descriptions ............................................................................ 4453
20-13. IRQ_EOI Register Field Descriptions ................................................................................. 4454
20-17. IRQENABLE_CLR Register Field Descriptions ..................................................................... 4458
20-18. IRQWAKEEN Register Field Descriptions ........................................................................... 4459
20-19. TCLR Register Field Descriptions..................................................................................... 4460
20-20. TCRR Register Field Descriptions .................................................................................... 4462
20-21. TLDR Register Field Descriptions..................................................................................... 4463
20-22. TTGR Register Field Descriptions .................................................................................... 4464
20-23. TWPS Register Field Descriptions .................................................................................... 4465
20-24. TMAR Register Field Descriptions .................................................................................... 4466
20-25. TCAR1 Register Field Descriptions ................................................................................... 4467
20-26. TSICR Register Field Descriptions.................................................................................... 4468

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20-28. Timer1 Connectivity Attributes ......................................................................................... 4472
20-29. Timer Clock Signals ..................................................................................................... 4473
20-30. Value Loaded in TCRR to Generate 1ms Tick ...................................................................... 4475
20-31. Prescaler/Timer Reload Values Versus Contexts ................................................................... 4478
20-32. SmartIdle - Clock Activity Field Configuration ....................................................................... 4480
20-33. Prescaler Clock Ratios Value .......................................................................................... 4481
20-34. Value and Corresponding Interrupt Period ........................................................................... 4482
20-35. DMTIMER_1MS REGISTERS ......................................................................................... 4482
20-36. TIDR Register Field Descriptions ..................................................................................... 4484
20-37. TIOCP_CFG Register Field Descriptions ............................................................................ 4485
20-38. TISTAT Register Field Descriptions .................................................................................. 4486
20-39. TISR Register Field Descriptions ..................................................................................... 4487
20-40. TIER Register Field Descriptions ..................................................................................... 4488
20-41. TWER Register Field Descriptions .................................................................................... 4489
20-42. TCLR Register Field Descriptions..................................................................................... 4490
20-43. TCRR Register Field Descriptions .................................................................................... 4492
20-44. TLDR Register Field Descriptions..................................................................................... 4493
20-45. TTGR Register Field Descriptions .................................................................................... 4494
20-46. TWPS Register Field Descriptions .................................................................................... 4495
20-47. TMAR Register Field Descriptions .................................................................................... 4497
20-49. TSICR Register Field Descriptions.................................................................................... 4499
20-51. TPIR Register Field Descriptions ..................................................................................... 4501
20-52. TNIR Register Field Descriptions ..................................................................................... 4502
20-53. TCVR Register Field Descriptions .................................................................................... 4503
20-54. TOCR Register Field Descriptions .................................................................................... 4504
20-55. TOWR Register Field Descriptions ................................................................................... 4505
20-56. RTC Module Connectivity Attributes .................................................................................. 4507
20-57. RTC Clock Signals ...................................................................................................... 4508
20-58. RTC Pin List.............................................................................................................. 4508
20-59. RTC Signals.............................................................................................................. 4510
20-60. Interrupt Trigger Events ................................................................................................ 4510
20-61. RTC Register Names and Values ..................................................................................... 4513
20-62. pmic_power_en Description ........................................................................................... 4516
20-63. RTC Registers ........................................................................................................... 4517
20-64. SECONDS_REG Register Field Descriptions ....................................................................... 4519
20-65. MINUTES_REG Register Field Descriptions ........................................................................ 4520
20-66. HOURS_REG Register Field Descriptions........................................................................... 4521
20-67. DAYS_REG Register Field Descriptions ............................................................................. 4522
20-68. MONTHS_REG Register Field Descriptions......................................................................... 4523
20-69. YEARS_REG Register Field Descriptions ........................................................................... 4524
20-70. WEEKS_REG Register Field Descriptions........................................................................... 4525
20-71. ALARM_SECONDS_REG Register Field Descriptions ............................................................ 4526
20-72. ALARM_MINUTES_REG Register Field Descriptions ............................................................. 4527
20-73. ALARM_HOURS_REG Register Field Descriptions ................................................................ 4528
20-74. ALARM_DAYS_REG Register Field Descriptions .................................................................. 4529
20-75. ALARM_MONTHS_REG Register Field Descriptions .............................................................. 4530

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20-76. ALARM_YEARS_REG Register Field Descriptions ................................................................ 4531

20-77. RTC_CTRL_REG Register Field Descriptions ...................................................................... 4532
20-78. RTC_STATUS_REG Register Field Descriptions................................................................... 4534
20-79. RTC_INTERRUPTS_REG Register Field Descriptions ............................................................ 4535
20-80. RTC_COMP_LSB_REG Register Field Descriptions............................................................... 4536
20-81. RTC_COMP_MSB_REG Register Field Descriptions .............................................................. 4537
20-82. RTC_OSC_REG Register Field Descriptions ....................................................................... 4538
20-83. RTC_SCRATCH0_REG Register Field Descriptions ............................................................... 4539
20-86. KICK0R Register Field Descriptions .................................................................................. 4542
20-87. KICK1R Register Field Descriptions .................................................................................. 4543
20-88. RTC_REVISION Register Field Descriptions ........................................................................ 4544
20-89. RTC_SYSCONFIG Register Field Descriptions ..................................................................... 4545
20-90. RTC_IRQWAKEEN Register Field Descriptions .................................................................... 4546
20-91. ALARM2_SECONDS_REG Register Field Descriptions ........................................................... 4547
20-92. ALARM2_MINUTES_REG Register Field Descriptions ............................................................ 4548
20-93. ALARM2_HOURS_REG Register Field Descriptions .............................................................. 4549
20-94. ALARM2_DAYS_REG Register Field Descriptions ................................................................. 4550
20-95. ALARM2_MONTHS_REG Register Field Descriptions ............................................................ 4551
20-96. ALARM2_YEARS_REG Register Field Descriptions ............................................................... 4552
20-97. RTC_PMIC Register Field Descriptions .............................................................................. 4553
20-98. RTC_DEBOUNCE Register Field Descriptions ..................................................................... 4554
20-99. Public WD Timer Module Connectivity Attributes ................................................................... 4556
20-100. Public WD Timer Clock Signals ...................................................................................... 4557
20-101. Watchdog Timer Events .............................................................................................. 4558
20-102. Count and Prescaler Default Reset Values ........................................................................ 4559
20-103. Prescaler Clock Ratio Values ........................................................................................ 4560
20-104. Reset Period Examples ............................................................................................... 4560
20-105. Default Watchdog Timer Reset Periods ............................................................................ 4561
20-106. Global Initialization of Surrounding Modules ....................................................................... 4564
20-107. Watchdog Timer Module Global Initialization ...................................................................... 4564
20-108. Watchdog Timer Basic Configuration ............................................................................... 4564
20-109. Disable the Watchdog Timer ......................................................................................... 4565
20-110. Enable the Watchdog Timer .......................................................................................... 4565
20-111. WATCHDOG_TIMER Registers ..................................................................................... 4565
20-112. WDT_WIDR Register Field Descriptions ........................................................................... 4567
20-113. WDT_WDSC Register Field Descriptions .......................................................................... 4568
20-114. WDT_WDST Register Field Descriptions ........................................................................... 4569
20-115. WDT_WISR Register Field Descriptions............................................................................ 4570
20-116. WDT_WIER Register Field Descriptions............................................................................ 4571
20-117. WDT_WCLR Register Field Descriptions ........................................................................... 4572
20-118. WDT_WCRR Register Field Descriptions .......................................................................... 4573
20-119. WDT_WLDR Register Field Descriptions ........................................................................... 4574
20-120. WDT_WTGR Register Field Descriptions .......................................................................... 4575
20-121. WDT_WWPS Register Field Descriptions .......................................................................... 4576
20-122. WDT_WDLY Register Field Descriptions ........................................................................... 4577
20-123. WDT_WSPR Register Field Descriptions .......................................................................... 4578
20-124. WDT_WIRQSTATRAW Register Field Descriptions .............................................................. 4579

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20-125. WDT_WIRQSTAT Register Field Descriptions .................................................................... 4580

20-126. WDT_WIRQENSET Register Field Descriptions .................................................................. 4581
20-127. WDT_WIRQENCLR Register Field Descriptions .................................................................. 4582
21-1. Unsupported I2C Features ............................................................................................. 4584
21-2. I2C0 Connectivity Attributes ........................................................................................... 4585
21-3. I2C(1–2) Connectivity Attributes....................................................................................... 4586
21-4. I2C Clock Signals ....................................................................................................... 4586
21-5. I2C Pin List ............................................................................................................... 4586
21-6. Signal Pads .............................................................................................................. 4588
21-7. Reset State of I2C Signals ............................................................................................. 4588
21-8. I2C Registers ............................................................................................................ 4601
21-9. I2C_REVNB_LO Register Field Descriptions........................................................................ 4602
21-10. I2C_REVNB_HI Register Field Descriptions ........................................................................ 4603
21-11. I2C_SYSC Register Field Descriptions............................................................................... 4604
21-12. I2C_IRQSTATUS_RAW Register Field Descriptions ............................................................... 4606
21-13. I2C_IRQSTATUS Register Field Descriptions ...................................................................... 4612
21-14. I2C_IRQENABLE_SET Register Field Descriptions ................................................................ 4614
21-15. I2C_IRQENABLE_CLR Register Field Descriptions................................................................ 4616
21-16. I2C_WE Register Field Descriptions.................................................................................. 4618
21-17. I2C_DMARXENABLE_SET Register Field Descriptions ........................................................... 4621
21-18. I2C_DMATXENABLE_SET Register Field Descriptions ........................................................... 4622
21-19. I2C_DMARXENABLE_CLR Register Field Descriptions ........................................................... 4623
21-20. I2C_DMATXENABLE_CLR Register Field Descriptions ........................................................... 4624
21-21. I2C_DMARXWAKE_EN Register Field Descriptions ............................................................... 4625
21-22. I2C_DMATXWAKE_EN Register Field Descriptions ............................................................... 4627
21-23. I2C_SYSS Register Field Descriptions ............................................................................... 4629
21-24. I2C_BUF Register Field Descriptions................................................................................. 4630
21-25. I2C_CNT Register Field Descriptions ................................................................................ 4632
21-26. I2C_DATA Register Field Descriptions ............................................................................... 4633
21-27. I2C_CON Register Field Descriptions ................................................................................ 4634
21-28. I2C_OA Register Field Descriptions .................................................................................. 4637
21-29. I2C_SA Register Field Descriptions .................................................................................. 4638
21-30. I2C_PSC Register Field Descriptions ................................................................................ 4639
21-31. I2C_SCLL Register Field Descriptions ............................................................................... 4640
21-32. I2C_SCLH Register Field Descriptions ............................................................................... 4641
21-33. I2C_SYSTEST Register Field Descriptions .......................................................................... 4642
21-34. I2C_BUFSTAT Register Field Descriptions .......................................................................... 4645
21-35. I2C_OA1 Register Field Descriptions................................................................................. 4646
21-38. I2C_ACTOA Register Field Descriptions ............................................................................. 4649
21-39. I2C_SBLOCK Register Field Descriptions ........................................................................... 4650
22-1. Unsupported McASP Features ........................................................................................ 4654
22-2. McASP Connectivity Attributes ........................................................................................ 4655
22-3. McASP Clock Signals................................................................................................... 4656
22-4. McASP Pin List .......................................................................................................... 4656
22-5. Biphase-Mark Encoder ................................................................................................. 4663
22-6. Preamble Codes ......................................................................................................... 4664
22-7. McASP Interface Signals ............................................................................................... 4671

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22-8. Channel Status and User Data for Each DIT Block ................................................................ 4678
22-9. Transmit Bitstream Data Alignment ................................................................................... 4689
22-10. Receive Bitstream Data Alignment.................................................................................... 4691
22-11. MCASP Registers ....................................................................................................... 4710
22-12. REV Register Field Descriptions ...................................................................................... 4712
22-13. PWRIDLESYSCONFIG Register Field Descriptions ............................................................... 4713
22-14. PFUNC Register Field Descriptions .................................................................................. 4714
22-15. PDIR Register Field Descriptions ..................................................................................... 4715
22-16. PDOUT Register Field Descriptions .................................................................................. 4717
22-17. PDIN Register Field Descriptions ..................................................................................... 4719
22-18. PDCLR Register Field Descriptions .................................................................................. 4720
22-19. GBLCTL Register Field Descriptions ................................................................................. 4722
22-20. AMUTE Register Field Descriptions .................................................................................. 4724
22-21. DLBCTL Register Field Descriptions ................................................................................. 4726
22-22. DITCTL Register Field Descriptions .................................................................................. 4727
22-23. RGBLCTL Register Field Descriptions ............................................................................... 4728
22-24. RMASK Register Field Descriptions .................................................................................. 4730
22-25. RFMT Register Field Descriptions .................................................................................... 4731
22-26. AFSRCTL Register Field Descriptions ............................................................................... 4733
22-27. ACLKRCTL Register Field Descriptions.............................................................................. 4734
22-28. AHCLKRCTL Register Field Descriptions............................................................................ 4735
22-29. RTDM Register Field Descriptions .................................................................................... 4736
22-30. RINTCTL Register Field Descriptions ................................................................................ 4737
22-31. RSTAT Register Field Descriptions ................................................................................... 4739
22-32. RSLOT Register Field Descriptions ................................................................................... 4741
22-33. RCLKCHK Register Field Descriptions ............................................................................... 4742
22-34. REVTCTL Register Field Descriptions ............................................................................... 4743
22-35. XGBLCTL Register Field Descriptions ............................................................................... 4744
22-36. XMASK Register Field Descriptions .................................................................................. 4746
22-37. XFMT Register Field Descriptions .................................................................................... 4747
22-38. AFSXCTL Register Field Descriptions ............................................................................... 4749
22-39. ACLKXCTL Register Field Descriptions .............................................................................. 4750
22-40. AHCLKXCTL Register Field Descriptions ............................................................................ 4751
22-41. XTDM Register Field Descriptions .................................................................................... 4752
22-42. XINTCTL Register Field Descriptions ................................................................................ 4753
22-43. XSTAT Register Field Descriptions ................................................................................... 4755
22-44. XSLOT Register Field Descriptions ................................................................................... 4757
22-45. XCLKCHK Register Field Descriptions ............................................................................... 4758
22-46. XEVTCTL Register Field Descriptions ............................................................................... 4759
22-47. DITCSRA_0 to DITCSRA_5 Register Field Descriptions .......................................................... 4760
22-48. DITCSRB_0 to DITCSRB_5 Register Field Descriptions .......................................................... 4761
22-49. DITUDRA_0 to DITUDRA_5 Register Field Descriptions .......................................................... 4762
22-50. DITUDRB_0 to DITUDRB_5 Register Field Descriptions .......................................................... 4763
22-51. SRCTL_0 to SRCTL_5 Register Field Descriptions ................................................................ 4764
22-52. XBUF_0 to XBUF_5 Register Field Descriptions ................................................................... 4766
22-53. RBUF_0 to RBUF_5 Register Field Descriptions ................................................................... 4767
22-54. WFIFOCTL Register Field Descriptions .............................................................................. 4768
22-55. WFIFOSTS Register Field Descriptions .............................................................................. 4769
22-56. RFIFOCTL Register Field Descriptions .............................................................................. 4770

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22-57. RFIFOSTS Register Field Descriptions .............................................................................. 4771

23-1. DCAN Connectivity Attributes ......................................................................................... 4774
23-2. DCAN Clock Signals .................................................................................................... 4775
23-3. DCAN Pin List ........................................................................................................... 4775
23-4. Initialization of a Transmit Object ..................................................................................... 4791
23-5. Initialization of a single Receive Object for Data Frames .......................................................... 4791
23-6. Initialization of a Single Receive Object for Remote Frames ...................................................... 4792
23-7. Parameters of the CAN Bit Time ...................................................................................... 4799
23-8. Structure of a Message Object ........................................................................................ 4809
23-9. Field Descriptions ....................................................................................................... 4809
23-10. Message RAM addressing in Debug/Suspend and RDA Mode................................................... 4811
23-11. Message RAM Representation in Debug/Suspend Mode ......................................................... 4812
23-12. Message RAM Representation in RAM Direct Access Mode ..................................................... 4812
23-13. DCAN Registers ......................................................................................................... 4814
23-14. CTL Register Field Descriptions....................................................................................... 4816
23-15. ES Register Field Descriptions ........................................................................................ 4819
23-16. ERRC Register Field Descriptions .................................................................................... 4821
23-17. BTR Register Field Descriptions ...................................................................................... 4822
23-18. INT Register Field Descriptions ....................................................................................... 4823
23-19. TEST Register Field Descriptions ..................................................................................... 4824
23-20. PERR Register Field Descriptions .................................................................................... 4825
23-21. ABOTR Register Field Descriptions .................................................................................. 4826
23-22. TXRQ_X Register Field Descriptions ................................................................................. 4827
23-23. TXRQ12 Register Field Descriptions ................................................................................. 4828
23-27. NWDAT_X Register Field Descriptions .............................................................................. 4832
23-28. NWDAT12 Register Field Descriptions ............................................................................... 4833
23-32. INTPND_X Register Field Descriptions .............................................................................. 4837
23-33. INTPND12 Register Field Descriptions............................................................................... 4838
23-37. MSGVAL_X Register Field Descriptions ............................................................................. 4842
23-38. MSGVAL12 Register Field Descriptions ............................................................................. 4843
23-42. INTMUX12 Register Field Descriptions .............................................................................. 4847
23-46. IF1CMD Register Field Descriptions.................................................................................. 4851
23-47. IF1MSK Register Field Descriptions .................................................................................. 4854
23-48. IF1ARB Register Field Descriptions .................................................................................. 4855

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23-49. IF1MCTL Register Field Descriptions ................................................................................ 4856

23-50. IF1DATA Register Field Descriptions................................................................................. 4858
23-51. IF1DATB Register Field Descriptions................................................................................. 4859
23-52. IF2CMD Register Field Descriptions.................................................................................. 4860
23-58. IF3OBS Register Field Descriptions .................................................................................. 4869
23-64. IF3UPD12 Register Field Descriptions ............................................................................... 4877
23-68. TIOC Register Field Descriptions ..................................................................................... 4881
23-69. RIOC Register Field Descriptions ..................................................................................... 4883
24-1. Unsupported McSPI Features ......................................................................................... 4886
24-2. McSPI Connectivity Attributes ......................................................................................... 4888
24-3. McSPI Clock Signals .................................................................................................... 4888
24-4. McSPI Pin List ........................................................................................................... 4888
24-5. Phase and Polarity Combinations .................................................................................... 4893
24-6. Chip Select ↔ Clock Edge Delay Depending on Configuration .................................................. 4903
24-7. CLKSPIO High/Low Time Computation ............................................................................. 4904
24-8. Clock Granularity Examples ........................................................................................... 4904
24-9. FIFO Writes, Word Length Relationship ............................................................................. 4905
24-10. SPI Registers ............................................................................................................ 4923
24-11. MCSPI_REVISION Register Field Descriptions ..................................................................... 4925
24-12. MCSPI_SYSCONFIG Register Field Descriptions .................................................................. 4926
24-13. MCSPI_SYSSTATUS Register Field Descriptions.................................................................. 4927
24-14. MCSPI_IRQSTATUS Register Field Descriptions .................................................................. 4928
24-15. MCSPI_IRQENABLE Register Field Descriptions .................................................................. 4931
24-16. MCSPI_SYST Register Field Descriptions........................................................................... 4933
24-17. MCSPI_MODULCTRL Register Field Descriptions ................................................................. 4935
24-18. MCSPI_CH0CONF Register Field Descriptions..................................................................... 4937
24-19. MCSPI_CH0STAT Register Field Descriptions ..................................................................... 4941
24-20. MCSPI_CH0CTRL Register Field Descriptions ..................................................................... 4943
24-21. MCSPI_TX0 Register Field Descriptions ............................................................................. 4944
24-22. MCSPI_RX0 Register Field Descriptions ............................................................................ 4945

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24-38. MCSPI_XFERLEVEL Register Field Descriptions .................................................................. 4973
24-39. MCSPI_DAFTX Register Field Descriptions ......................................................................... 4974
24-40. MCSPI_DAFRX Register Field Descriptions ........................................................................ 4975
25-1. GPIO0 Connectivity Attributes ......................................................................................... 4979
25-2. GPIO[1:3] Connectivity Attributes ..................................................................................... 4979
25-3. GPIO Clock Signals ..................................................................................................... 4979
25-4. GPIO Pin List ............................................................................................................ 4980
25-5. GPIO Registers .......................................................................................................... 4990
25-6. GPIO_REVISION Register Field Descriptions ...................................................................... 4991
25-7. GPIO_SYSCONFIG Register Field Descriptions ................................................................... 4992
25-8. GPIO_EOI Register Field Descriptions ............................................................................... 4993
25-9. GPIO_IRQSTATUS_RAW_0 Register Field Descriptions ......................................................... 4994
25-10. GPIO_IRQSTATUS_RAW_1 Register Field Descriptions ......................................................... 4995
25-11. GPIO_IRQSTATUS_0 Register Field Descriptions ................................................................. 4996
25-12. GPIO_IRQSTATUS_1 Register Field Descriptions ................................................................. 4997
25-13. GPIO_IRQSTATUS_SET_0 Register Field Descriptions .......................................................... 4998
25-14. GPIO_IRQSTATUS_SET_1 Register Field Descriptions .......................................................... 4999
25-15. GPIO_IRQSTATUS_CLR_0 Register Field Descriptions .......................................................... 5000
25-16. GPIO_IRQSTATUS_CLR_1 Register Field Descriptions .......................................................... 5001
25-17. GPIO_IRQWAKEN_0 Register Field Descriptions .................................................................. 5002
25-18. GPIO_IRQWAKEN_1 Register Field Descriptions .................................................................. 5003
25-19. GPIO_SYSSTATUS Register Field Descriptions ................................................................... 5004
25-20. GPIO_CTRL Register Field Descriptions ............................................................................ 5005
25-21. GPIO_OE Register Field Descriptions ............................................................................... 5006
25-22. GPIO_DATAIN Register Field Descriptions ......................................................................... 5007
25-23. GPIO_DATAOUT Register Field Descriptions ...................................................................... 5008
25-24. GPIO_LEVELDETECT0 Register Field Descriptions ............................................................... 5009
25-25. GPIO_LEVELDETECT1 Register Field Descriptions ............................................................... 5010
25-26. GPIO_RISINGDETECT Register Field Descriptions ............................................................... 5011
25-27. GPIO_FALLINGDETECT Register Field Descriptions ............................................................. 5012
25-28. GPIO_DEBOUNCENABLE Register Field Descriptions ........................................................... 5013
25-29. GPIO_DEBOUNCINGTIME Register Field Descriptions ........................................................... 5014
25-30. GPIO_CLEARDATAOUT Register Field Descriptions ............................................................. 5015
25-31. GPIO_SETDATAOUT Register Field Descriptions ................................................................. 5016
26-1. ROM Exception Vectors ................................................................................................ 5023
26-2. Dead Loops .............................................................................................................. 5023
26-3. RAM Exception Vectors ................................................................................................ 5025
26-4. Tracing Data ............................................................................................................. 5025
26-5. Crystal Frequencies Supported ....................................................................................... 5028
26-6. ROM Code Default Clock Settings .................................................................................... 5028

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26-7. SYSBOOT Configuration Pins[4] ...................................................................................... 5031

26-8. XIP Timings Parameters ............................................................................................... 5042
26-9. Pins Used for Non-Muxed NOR Boot................................................................................. 5043
26-10. Pins Used for Muxed NOR Boot ...................................................................................... 5044
26-11. Special SYSBOOT Pins for NOR Boot ............................................................................... 5044
26-12. NAND Timings Parameters ............................................................................................ 5046
26-13. ONFI Parameters Page Description .................................................................................. 5047
26-14. Supported NAND Devices ............................................................................................. 5047
26-15. 4th NAND ID Data Byte ................................................................................................ 5048
26-16. Pins Used for NANDI2C Boot for I2C EEPROM Access .......................................................... 5049
26-17. NAND Geometry Information on I2C EEPROM ..................................................................... 5049
26-18. ECC Configuration for NAND Boot ................................................................................... 5049
26-19. Pins Used for NAND Boot .............................................................................................. 5055
26-20. Master Boot Record Structure ......................................................................................... 5059
26-21. Partition Entry ............................................................................................................ 5060
26-22. Partition Types ........................................................................................................... 5060
26-23. FAT Boot Sector ......................................................................................................... 5061
26-24. FAT Directory Entry ..................................................................................................... 5065
26-25. FAT Entry Description .................................................................................................. 5066
26-26. Pins Used for MMC0 Boot ............................................................................................. 5066
26-27. Pins Used for MMC1 Boot ............................................................................................. 5066
26-28. Pins Used for SPI Boot ................................................................................................. 5067
26-29. Blocks and Sectors Searched on Non-XIP Memories .............................................................. 5068
26-30. Pins Used for EMAC Boot in MII Mode .............................................................................. 5072
26-31. Pins Used for EMAC Boot in RGMII Mode .......................................................................... 5072
26-32. Pins Used for EMAC Boot in RMII Mode............................................................................. 5072
26-33. Ethernet PHY Mode Selection ......................................................................................... 5073
26-34. Pins Used for UART Boot .............................................................................................. 5073
26-35. Customized Descriptor Parameters ................................................................................... 5074
26-36. Pins Used for USB Boot ................................................................................................ 5075
26-37. GP Device Image Format .............................................................................................. 5077
26-38. The TOC Item Fields.................................................................................................... 5077
26-39. Magic Values for MMC RAW Mode ................................................................................... 5077
26-40. Filenames in TOC for GP Device ..................................................................................... 5077
26-41. Booting Parameters Structure ......................................................................................... 5078
26-42. Tracing Vectors .......................................................................................................... 5081
27-1. IEEE1149.1 Signals ..................................................................................................... 5086
27-2. ICEPick Boot Modes Upon POR ...................................................................................... 5087
27-3. Debug Resource Manager (DRM) Registers ........................................................................ 5088
27-4. Suspend Control Registers Field Descriptions ...................................................................... 5089
B-1. Document Revision History ............................................................................................ 5117

Preface
SPRUH73Q – October 2011 – Revised December 2019
Read This First
About This Manual

This Technical Reference Manual (TRM) details the integration, the environment, the functional
description, and the programming models for each peripheral and subsystem in the device
Related Documentation From Texas Instruments

For a complete listing of related documentation and development-support tools, visit www.ti.com.
(1) (2) (3)
(1)
Sitara is a trademark of Texas Instruments.
(2)
USSE is a trademark of Imagination Technologies Ltd..
(3)
POWERVR is a registered trademark of Imagination Technologies Ltd..
SPRUH73Q – October 2011 – Revised December 2019 Read This First 173
Chapter 1
Introduction
1.1 AM335x Family
1.1.1 Device Features

This architecture is configured with different sets of features in different devices. This technical reference
manual details all of the features available in current and future AM335x devices. Some features may not
be available or supported in your particular device. The features supported across different AM335x
devices are detailed in your device-specific data manual.
1.1.2 Device Identification

Several registers help identify the type and available features of the device. The DEV_FEATURE register
in the control module is summarized in the Device Comparison section of your device-specific data
manual, and Table 1-1 summarizes the Device_ID register.
Table 1-1. Device_ID (Address 0x44E10600) Bit Field Descriptions

Bit Field Value Description
31-28 DEVREV Device revision
0000b - Silicon Revision 1.0
See device errata for detailed information on functionality in each device revision.
Reset value is revision-dependent.
27-12 PARTNUM Device part number
0xB944
11-1 MFGR Manufacturer's ID
0x017
0 Reserved Read always as 0
0x0
1.2 Silicon Revision Functional Differences and Enhancements

This section describes the differences in functionality among different silicon revisions of AM335x.
Enhancements introduced in silicon revisions are also described. For a description of silicon bugs that
were fixed in later revisions of the device, see AM335x ARM Cortex-A8 Microprocessors (MPUs) Silicon
Errata (literature number SPRZ360). Errata items that were fixed may or may not show up in this section.
1.2.1 Added RTC Alarm Wakeup for DeepSleep Modes

See Section 8.1.4.5, Wakeup Sources/Events.
PG1.0: RTC alarm will not wake up device from DeepSleep0 and RTC-only modes.
PG2.x: RTC alarm was added as a wake-up source from DeepSleep modes and RTC-only modes.
1.2.2 Changed BOOTP Identifier

See Section 26.1.9.4.2, BOOTP (RFC 951) and Errata Advisory 1.0.8.
174 Introduction SPRUH73Q – October 2011 – Revised December 2019

www.ti.com Silicon Revision Functional Differences and Enhancements
PG1.0: BOOTP Identifier string is "DM814x ROM v1.0".

PG2.x: BOOTP Identifier string is "AM335x ROM".
1.2.3 Changed Product String in USB Descriptor

See Section 26.1.9.6.1.2, Enumeration Descriptors.
PG1.0: Product string in USB descriptor is "Subarctic".
PG2.x: Product string in USB descriptor is "AM335x USB".
1.2.4 Added DPLL Power Switch Control and Status Registers

See Section 9.3.1.14, dpll_pwr_sw_status Register, and Section 9.3.1.75, dpll_pwr_sw_ctrl Register.
PG1.0: DPLL Power Switch Control and Status registers do not exist.
PG2.x: Added DPLL Power Switch Control and DPLL Power Switch Status registers in the Control Module
to facilitate power optimization.
1.2.5 Added Control for CORE SRAM LDO Retention Mode

See newly added SMA2 register, Section 9.3.1.77.
PG1.0: SMA2 register does not exist.
PG2.x: Added SMA2.VSLDO_CORE_AUTO_RAMP_EN.
1.2.6 Added Pin Mux Options for GPMC_A9 to Facilitate RMII Pin Muxing
See newly added SMA2 register, Section 9.3.1.77.
PG1.0: SMA2 register does not exist.
PG2.x: Added SMA2.RMII2_CRS_DV_MODE_SEL.
1.2.7 Changed Polarity of Input Signal nNMI (Pin EXTINTn)

See Section 6.3, ARM Cortex-A8 Interrupts and Errata Advisory 1.0.6.
PG1.0: nNMI input signal is active high.
PG2.x: nNMI input signal is active low.
SPRUH73Q – October 2011 – Revised December 2019 Introduction 175

Silicon Revision Functional Differences and Enhancements www.ti.com
1.2.8 Changed Default Value of ncin and pcin Bits in vtp_ctrl Register
See Section 9.3.1.53, vtp_ctrl Register.
PG1.0: VTP_CTRL.NCIN and VTP_CTRL.PCIN reset value is 0.
PG2.x: VTP_CTRL.NCIN and VTP_CTRL.PCIN reset value is 1.
1.2.9 Changed Default Value of RGMII Mode to No Internal Delay

See Section 9.3.1.30, gmii_sel Register and Errata Advisory 1.0.10.
PG1.0: RGMII1_IDMODE And RGMII2_IDMODE reset value is 0.
PG2.x: RGMII1_IDMODE And RGMII2_IDMODE reset value is 1.
1.2.10 Changed Default Value of RMII Clock Source

See Section 9.3.1.30, gmii_sel Register and Errata Advisory 1.0.18.
PG1.0: RMII1_IO_CLK_EN and RMII2_IO_CLK_EN reset value is 0.
PG2.x: RMII1_IO_CLK_EN and RMII2_IO_CLK_EN reset value is 1.
1.2.11 Changed the Method of Determining Speed of Operation During EMAC Boot
See Section 26.1.9.4, EMAC Boot Procedure and Errata Advisory 1.0.7.
PG1.0: Link speed is determined by CONTROL register bit 6 in the external ethernet PHY. Note that some
PHYs may not update this bit, as it is not necessary as described in the 802.3 specification.
PG2.x: Link speed is determined by reading the Auto-Negotiation Advertisement and Auto-Negotiation
Link Partner Base Page Ability registers in the external ethernet PHY.
1.2.12 Added EFUSE_SMA Register for Help Identifying Different Device Variants
See Section 9.3.1.49, efuse_sma Register.
PG1.0: EFUSE_SMA register value is not applicable. Value is always 0.
PG2.x: Added EFUSE_SMA description to distinguish package type and maximum ARM frequency of the
device.
176 Introduction SPRUH73Q – October 2011 – Revised December 2019

Chapter 2
Memory Map
This sections describes the memory map for the device.
2.1 ARM Cortex-A8 Memory Map
Table 2-1. L3 Memory Map

Block Name Start_address (hex) End_address (hex) Size Description
GPMC 0x0000_0000 (1) 0x1FFF_FFFF 512MB 8-/16-bit External Memory
(External Memory) (Ex/R/W) (2)
Reserved 0x2000_0000 0x3FFF_FFFF 512MB Reserved
Boot ROM 0x4000_0000 0x4001_FFFF 128KB
0x4002_0000 0x4002_BFFF 48KB 32-bit Ex/R (2) – Public
Reserved 0x4002_C000 0x400F_FFFF 848KB Reserved
Reserved 0x4010_0000 0x401F_FFFF 1MB Reserved
Reserved 0x4020_0000 0x402E_FFFF 960KB Reserved
Reserved 0x402F_0000 0x402F_03FF 64KB Reserved
SRAM internal 0x402F_0400 0x402F_FFFF 32-bit Ex/R/W (2)
L3 OCMC0 0x4030_0000 0x4030_FFFF 64KB 32-bit Ex/R/W (2) OCMC SRAM
Reserved 0x4031_0000 0x403F_FFFF 960KB Reserved
Reserved 0x4040_0000 0x4041_FFFF 128KB Reserved
Reserved 0x4084_0000 0x40DF_FFFF 5888KB Reserved
Reserved 0x40E0_0000 0x40E0_7FFF 32KB Reserved
Reserved 0x40E0_8000 0x40EF_FFFF 992KB Reserved
Reserved 0x40F0_0000 0x40F0_7FFF 32KB Reserved
Reserved 0x40F0_8000 0x40FF_FFFF 992KB Reserved
Reserved 0x4100_0000 0x41FF_FFFF 16MB Reserved
L3F CFG Regs 0x4400_0000 0x443F_FFFF 4MB L3Fast configuration registers
L3S CFG Regs 0x4480_0000 0x44BF_FFFF 4MB L3Slow configuration registers
L4_WKUP 0x44C0_0000 0x44FF_FFFF 4MB L4_WKUP
McASP0 Data 0x4600_0000 0x463F_FFFF 4MB McASP0 Data Registers
McASP1 Data 0x4640_0000 0x467F_FFFF 4MB McASP1 Data Registers
(1)
The first 1MB of address space 0x0-0xFFFFF is inaccessible externally.
(2)
Ex/R/W – Execute/Read/Write.
SPRUH73Q – October 2011 – Revised December 2019 Memory Map 177

ARM Cortex-A8 Memory Map www.ti.com
Table 2-1. L3 Memory Map (continued)

USBSS 0x4740_0000 0x4740_0FFF 32KB USB Subsystem Registers
USB0 0x4740_1000 0x4740_12FF USB0 Controller Registers
USB0_PHY 0x4740_1300 0x4740_13FF USB0 PHY Registers
USB0 Core 0x4740_1400 0x4740_17FF USB0 Core Registers
USB1 0x4740_1800 0x4740_1AFF USB1 Controller Registers
USB1_PHY 0x4740_1B00 0x4740_1BFF USB1 PHY Registers
USB1 Core 0x4740_1C00 0x4740_1FFF USB1 Core Registers
USB CPPI DMA 0x4740_2000 0x4740_2FFF USB CPPI DMA Controller
Controller Registers
USB CPPI DMA 0x4740_3000 0x4740_3FFF USB CPPI DMA Scheduler
Scheduler Registers
USB Queue Manager 0x4740_4000 0x4740_7FFF USB Queue Manager Registers
Reserved 0x4740_8000 0x477F_FFFF 4MB-32KB Reserved
MMCHS2 0x4781_0000 0x4781_FFFF 64KB MMCHS2
Reserved 0x4782_0000 0x47BF_FFFF 4MB-128KB Reserved
Reserved 0x47C0_0000 0x47FF_FFFF 4MB Reserved
L4_PER 0x4800_0000 0x48FF_FFFF 16MB L4 Peripheral (see L4_PER table)
TPCC (EDMA3CC) 0x4900_0000 0x490F_FFFF 1MB EDMA3 Channel Controller
Registers
TPTC0 (EDMA3TC0) 0x4980_0000 0x498F_FFFF 1MB EDMA3 Transfer Controller 0
Registers
TPTC1 (EDMA3TC1) 0x4990_0000 0x499F_FFFF 1MB EDMA3 Transfer Controller 1
Registers
TPTC2 (EDMA3TC2) 0x49A0_0000 0x49AF_FFFF 1MB EDMA3 Transfer Controller 2
Registers
Reserved 0x49B0_0000 0x49BF_FFFF 1MB Reserved
Reserved 0x49C0_0000 0x49FF_FFFF 4MB Reserved
L4_FAST 0x4A00_0000 0x4AFF_FFFF 16MB L4_FAST
Reserved 0x4B00_0000 0x4B13_FFFF 1280KB Reserved
DebugSS_ETM 0x4B14_0000 0x4B14_0FFF 4KB CortexA8 ETM Unit
DebugSS_Debug 0x4B14_1000 0x4B14_1FFF 4KB CortexA8 Debug Unit
DebugSS_CTI 0x4B14_2000 0x4B14_2FFF 4KB CortexA8 CTI Unit
DebugSS_ICE 0x4B14_3000 0x4B14_3FFF 4KB ICECrusherCS APB
Reserved 0x4B14_4000 0x4B15_FFFF 128KB Reserved
DebugSS_DRM 0x4B16_0000 0x4B16_0FFF 4KB Debug Subsystem: Debug
Resource Manager
DebugSS_ETB 0x4B16_2000 0x4B16_2FFF 4KB Debug Subsystem: Embedded
Trace Buffer
Reserved 0x4B16_3000 0x4BFF_FFFF 15MB-396KB Reserved
EMIF0 0x4C00_0000 0x4CFF_FFFF 16MB EMIF0 Configuration registers
Reserved 0x4D00_0000 0x4DFF_FFFF 16MB Reserved
Reserved 0x4E00_0000 0x4FFF_FFFF 32MB Reserved
GPMC 0x5000_0000 0x50FF_FFFF 16MB GPMC Configuration registers
0x5310_0000 0x531F_FFFF 1MB Reserved
178 Memory Map SPRUH73Q – October 2011 – Revised December 2019

www.ti.com ARM Cortex-A8 Memory Map
Table 2-1. L3 Memory Map (continued)

0x5350_0000 0x535F_FFFF 1MB Reserved
Reserved 0x5360_0000 0x54BF_FFFF 22MB Reserved
ADC_TSC DMA 0x54C0_0000 0x54FF_FFFF 4MB ADC_TSC DMA Port
SGX530 0x5600_0000 0x56FF_FFFF 16MB SGX530 Slave Port
Reserved 0x5A00_0000 0x5AFF_FFFF 16MB Reserved
Reserved 0x5B00_0000 0x5BFF_FFFF 16MB Reserved
Reserved 0x5C00_0000 0x5DFF_FFFF 32MB Reserved
Reserved 0x5E00_0000 0x5FFF_FFFF 32MB Reserved
Reserved 0x6000_0000 0x7FFF_FFFF 512MB Reserved
EMIF0 SDRAM 0x8000_0000 0xBFFF_FFFF 1GB 8-/16-bit External Memory
(Ex/R/W) (2)
Reserved 0xC000_0000 0xFFFF_FFFF 1GB Reserved
Table 2-2. L4_WKUP Peripheral Memory Map

Region Name Start Address (hex) End Address (hex) Size Description
L4_WKUP configuration 0x44C0_0000 0x44C0_07FF 2KB Address/Protection (AP)
0x44C0_0800 0x44C0_0FFF 2KB Link Agent (LA)
0x44C0_1000 0x44C0_13FF 1KB Initiator Port (IP0)
0x44C0_1400 0x44C0_17FF 1KB Initiator Port (IP1)
Reserved 0x44C0_1800 0x44C0_1FFF 2KB Reserved (IP2 – IP3)
Reserved 0x44C0_2000 0x44CF_FFFF 1MB-8KB Reserved
Reserved 0x44D0_0000 0x44D0_3FFF 16KB Reserved
0x44D0_4000 0x44D0_4FFF 4KB Reserved
Reserved 0x44D0_5000 0x44D7_FFFF 492KB Reserved
Reserved 0x44D8_0000 0x44D8_1FFF 8KB Reserved
0x44D8_2000 0x44D8_2FFF 4KB Reserved
Reserved 0x44D8_3000 0x44DF_FFFF 500KB Reserved
CM_PER 0x44E0_0000 0x44E0_03FF 1KB Clock Module Peripheral Registers
CM_WKUP 0x44E0_0400 0x44E0_04FF 256 Bytes Clock Module Wakeup Registers
CM_DPLL 0x44E0_0500 0x44E0_05FF 256 Bytes Clock Module PLL Registers
CM_MPU 0x44E0_0600 0x44E0_06FF 256 Bytes Clock Module MPU Registers
CM_DEVICE 0x44E0_0700 0x44E0_07FF 256 Bytes Clock Module Device Registers
CM_RTC 0x44E0_0800 0x44E0_08FF 256 Bytes Clock Module RTC Registers
CM_GFX 0x44E0_0900 0x44E0_09FF 256 Bytes Clock Module Graphics Controller
Registers
CM_CEFUSE 0x44E0_0A00 0x44E0_0AFF 256 Bytes Clock Module Efuse Registers
PRM_IRQ 0x44E0_0B00 0x44E0_0BFF 256 Bytes Power Reset Module Interrupt
Registers
PRM_PER 0x44E0_0C00 0x44E0_0CFF 256 Bytes Power Reset Module Peripheral
Registers
PRM_WKUP 0x44E0_0D00 0x44E0_0DFF 256 Bytes Power Reset Module Wakeup
Registers
PRM_MPU 0x44E0_0E00 0x44E0_0EFF 256 Bytes Power Reset Module MPU
Registers

Table 2-2. L4_WKUP Peripheral Memory Map (continued)

Region Name Start Address (hex) End Address (hex) Size Description
PRM_DEV 0x44E0_0F00 0x44E0_0FFF 256 Bytes Power Reset Module Device
Registers
PRM_RTC 0x44E0_1000 0x44E0_10FF 256 Bytes Power Reset Module RTC
Registers
PRM_GFX 0x44E0_1100 0x44E0_11FF 256 Bytes Power Reset Module Graphics
Controller Registers
PRM_CEFUSE 0x44E0_1200 0x44E0_12FF 256 Bytes Power Reset Module Efuse
Registers
0x44E0_4000 0x44E0_4FFF 4KB Reserved
DMTIMER0 0x44E0_5000 0x44E0_5FFF 4KB DMTimer0 Registers
GPIO0 0x44E0_7000 0x44E0_7FFF 4KB GPIO Registers
UART0 0x44E0_9000 0x44E0_9FFF 4KB UART Registers
0x44E0_A000 0x44E0_AFFF 4KB Reserved
I2C0 0x44E0_B000 0x44E0_BFFF 4KB I2C Registers
0x44E0_C000 0x44E0_CFFF 4KB Reserved
ADC_TSC 0x44E0_D000 0x44E0_EFFF 8KB ADC_TSC Registers
0x44E0_F000 0x44E0_FFFF 4KB Reserved
Control Module 0x44E1_0000 0x44E1_1FFF 128KB Control Module Registers
DDR2/3/mDDR PHY 0x44E1_2000 0x44E1_23FF DDR2/3/mDDR PHY Registers
DMTIMER1_1MS 0x44E3_1000 0x44E3_1FFF 4KB DMTimer1 1ms Registers
(Accurate 1ms timer)
WDT1 0x44E3_5000 0x44E3_5FFF 4KB Watchdog Timer Registers
SmartReflex0 0x44E3_7000 0x44E3_7FFF 4KB L3 Registers
SmartReflex1 0x44E3_9000 0x44E3_9FFF 4KB L3 Registers
0x44E3_A000 0x44E3_AFFF 4KB Reserved
Reserved 0x44E3_B000 0x44E3_DFFF 12KB Reserved
RTCSS 0x44E3_E000 0x44E3_EFFF 4KB RTC Registers
0x44E3_F000 0x44E3_FFFF 4KB Reserved
DebugSS 0x44E4_0000 0x44E7_FFFF 256KB Debug Registers
Instrumentation
HWMaster1 Port
Reserved 0x44E8_1000 0x44EF_FFFF 508KB Reserved
Reserved 0x44F0_0000 0x44FF_FFFF 1MB Reserved
Table 2-3. L4_PER Peripheral Memory Map

Device Name Start_address (hex) End_address (hex) Size Description
0x4800_0000 0x4800_07FF 2KB Reserved
0x4800_0800 0x4800_0FFF 2KB Reserved
Reserved 0x4800_1000 0x4800_13FF 1KB Reserved

Table 2-3. L4_PER Peripheral Memory Map (continued)

0x4800_1400 0x4800_17FF 1KB Reserved
0x4800_1800 0x4800_1BFF 1KB Reserved
0x4800_1C00 0x4800_1FFF 1KB Reserved
Reserved 0x4800_2000 0x4800_3FFF 8KB Reserved
Reserved 0x4800_A000 0x4800_FFFF 24KB Reserved
UART1 0x4802_2000 0x4802_2FFF 4KB UART1 Registers
UART2 0x4802_4000 0x4802_4FFF 4KB UART2 Registers
I2C1 0x4802_A000 0x4802_AFFF 4KB I2C1 Registers
0x4802_B000 0x4802_BFFF 4KB Reserved
Reserved 0x4802_C000 0x4802_CFFF 4KB Reserved
0x4802_D000 0x4802_DFFF 4KB Reserved
Reserved 0x4802_E000 0x4802_EFFF 4KB Reserved
0x4802_F000 0x4802_FFFF 4KB Reserved
McSPI0 0x4803_0000 0x4803_0FFF 4KB McSPI0 Registers
McASP0 CFG 0x4803_8000 0x4803_9FFF 8KB McASP0 CFG Registers
0x4803_A000 0x4803_AFFF 4KB Reserved
Reserved 0x4803_B000 0x4803_BFFF 4KB Reserved
McASP1 CFG 0x4803_C000 0x4803_DFFF 8KB McASP1 CFG Registers
0x4803_E000 0x4803_EFFF 4KB Reserved
Reserved 0x4803_F000 0x4803_FFFF 4KB Reserved
DMTIMER2 0x4804_0000 0x4804_0FFF 4KB DMTimer2 Registers


0x4804_9000 0x4804_9FFF 4KB L4 Interconnect
DMTIMER7 0x4804_A000 0x4804_AFFF 4KB DMTimer7 Registers
GPIO1 0x4804_C000 0x4804_CFFF 4KB GPIO1 Registers
Reserved 0x4804_E000 0x4804_FFFF 8KB Reserved
MMCHS0 0x4806_0000 0x4806_0FFF 4KB MMCHS0 Registers
ELM 0x4808_0000 0x4808_FFFF 64KB ELM Registers
Reserved 0x480A_0000 0x480A_FFFF 64KB Reserved
0x480B_0000 0x480B_0FFF 4KB Reserved
Reserved 0x480B_1000 0x480B_FFFF 60KB Reserved
Reserved 0x480C_0000 0x480C_0FFF 4KB Reserved
0x480C_1000 0x480C_1FFF 4KB Reserved
Mailbox 0 0x480C_8000 0x480C_8FFF 4KB Mailbox Registers
Spinlock 0x480C_A000 0x480C_AFFF 4KB Spinlock Registers
0x480C_B000 0x480C_BFFF 4KB Reserved
Reserved 0x480C_C000 0x480F_FFFF 208KB Reserved
0x4816_0000 0x4816_0FFF 4K Reserved
Reserved 0x4818_A000 0x4818_AFFF 4KB Reserved
OCP Watchpoint 0x4818_C000 0x4818_CFFF 4KB OCP Watchpoint Registers


Reserved 0x4819_4000 0x4819_BFFF 32KB Reserved
I2C2 0x4819_C000 0x4819_CFFF 4KB I2C2 Registers
McSPI1 0x481A_0000 0x481A_0FFF 4KB McSPI1 Registers
0x481A_1000 0x481A_1FFF 4KB Reserved
Reserved 0x481A_2000 0x481A_5FFF 16KB Reserved
UART3 0x481A_6000 0x481A_6FFF 4KB UART3 Registers
UART4 0x481A_8000 0x481A_8FFF 4KB UART4 Registers
UART5 0x481A_A000 0x481A_AFFF 4KB UART5 Registers
0x481A_B000 0x481A_BFFF 4KB Reserved
GPIO2 0x481A_C000 0x481A_CFFF 4KB GPIO2 Registers
0x481A_D000 0x481A_DFFF 4KB Reserved
GPIO3 0x481A_E000 0x481A_EFFF 4KB GPIO3 Registers
0x481A_F000 0x481A_FFFF 4KB Reserved
Reserved 0x481B_0000 0x481B_FFFF 64KB Reserved
Reserved 0x481C_A000 0x481C_AFFF 4KB Reserved
0x481C_B000 0x481C_BFFF 4KB Reserved
DCAN0 0x481C_C000 0x481C_DFFF 8KB DCAN0 Registers
0x481C_E000 0x481C_FFFF 8KB Reserved
DCAN1 0x481D_0000 0x481D_1FFF 8KB DCAN1 Registers
0x481D_2000 0x481D_3FFF 8KB Reserved
Reserved 0x481D_4000 0x481D_4FFF 4KB Reserved
Reserved 0x481D_6000 0x481D_6FFF 4KB Reserved
MMC1 0x481D_8000 0x481D_8FFF 4KB MMC1 Registers
Reserved 0x481D_A000 0x481F_FFFF 152KB Reserved
Interrupt controller 0x4820_0000 0x4820_0FFF 4KB Interrupt Controller Registers
(INTCPS)
MPUSS config register 0x4824_0000 0x4824_0FFF 4KB Host ARM non-shared device
mapping


PWM Subsystem 0 0x4830_0000 0x4830_00FF PWMSS0 Configuration Registers
eCAP0 0x4830_0100 0x4830_017F PWMSS eCAP0 Registers
4KB
eQEP0 0x4830_0180 0x4830_01FF PWMSS eQEP0 Registers
ePWM0 0x4830_0200 0x4830_025F PWMSS ePWM0 Registers
4KB
4KB
Reserved 0x4830_6000 0x4830_DFFF 32KB Reserved
LCD Controller 0x4830_E000 0x4830_EFFF 4KB LCD Registers
Reserved 0x4831_8000 0x4831_BFFF 16KB Reserved
0x4831_C000 0x4831_CFFF 4KB Reserved
Reserved 0x4831_D000 0x4831_FFFF 12KB Reserved
Reserved 0x4832_6000 0x48FF_FFFF 13MB-152KB Reserved
Table 2-4. L4 Fast Peripheral Memory Map

L4_Fast configuration 0x4A00_0000 0x4A00_07FF 2KB Address/Protection (AP)
0x4A00_0800 0x4A00_0FFF 2KB Link Agent (LA)
0x4A00_1000 0x4A00_13FF 1KB Initiator Port (IP0)
0x4A00_1400 0x4A00_17FF 1KB Reserved
0x4A00_1800 0x4A00_1FFF 2KB Reserved (IP2 – IP3)
Reserved 0x4A00_2000 0x4A07_FFFF 504KB Reserved
0x4A0A_0000 0x4A0A_0FFF 4KB Reserved
Reserved 0x4A0A_1000 0x4A0F_FFFF 380KB Reserved
CPSW_SS 0x4A10_0000 0x4A10_7FFF 32KB Ethernet Switch
Subsystem
CPSW_PORT 0x4A10_0100 0x4A10_07FF Ethernet Switch Port
Control
CPSW_CPDMA 0x4A10_0800 0x4A10_08FF CPPI DMA Controller
Module
CPSW_STATS 0x4A10_0900 0x4A10_09FF Ethernet Statistics

Table 2-4. L4 Fast Peripheral Memory Map (continued)

CPSW_STATERAM 0x4A10_0A00 0x4A10_0BFF CPPI DMA State RAM
CPSW_CPTS 0x4A10_0C00 0x4A10_0CFF Ethernet Time Sync
Module
CPSW_ALE 0x4A10_0D00 0x4A10_0D7F Ethernet Address
Lookup Engine
CPSW_SL1 0x4A10_0D80 0x4A10_0DBF Ethernet Sliver for Port 1
CPSW_SL2 0x4A10_0DC0 0x4A10_0DFF Ethernet Sliver for Port 2
Reserved 0x4A10_0E00 0x4A10_0FFF Reserved
MDIO 0x4A10_1000 0x4A10_10FF Ethernet MDIO
Controller
Reserved 0x4A10_1100 0x4A10_11FF Reserved
CPSW_WR 0x4A10_1200 0x4A10_1FFF Ethernet Subsystem
Wrapper for RMII/RGMII
CPPI_RAM 0x4A10_2000 0x4A10_3FFF Communications Port
Programming Interface
RAM
0x4A15_0000 0x4A15_0FFF 4KB Reserved
Reserved 0x4A18_0000 0x4A1A_1FFF 136KB Reserved
Reserved 0x4A1A_2000 0x4A1A_3FFF 8KB Reserved
0x4A1A_A000 0x4A1A_AFFF 4KB Reserved
Reserved 0x4A1A_B000 0x4A1A_BFFF 4KB Reserved
0x4A1A_C000 0x4A1A_CFFF 4KB Reserved
Reserved 0x4A1A_D000 0x4A1A_DFFF 4KB Reserved
Reserved 0x4A1A_E000 0x4A1A_FFFF 8KB Reserved
0x4A1B_0000 0x4A1B_0FFF 4KB Reserved
Reserved 0x4A1B_1000 0x4A1B_1FFF 4KB Reserved
Reserved 0x4A1B_4000 0x4A1F_FFFF 304KB Reserved
Reserved 0x4A20_0000 0x4A2F_FFFF 1MB Reserved
PRU_ICSS 0x4A30_0000 0x4A37_FFFF 512KB PRU-ICSS
Instruction/Data/Control
Space
0x4A38_0000 0x4A38_0FFF 4KB Reserved
Reserved 0x4A38_1000 0x4A3F_FFFF 508KB Reserved
Reserved 0x4A40_0000 0x4AFF_FFFF 12MB Reserved

Chapter 3
ARM MPU Subsystem
This chapter describes the MPU Subsystem for the device.
Topic ........................................................................................................................... Page
3.1 ARM Cortex-A8 MPU Subsystem ........................................................................ 187
186 ARM MPU Subsystem SPRUH73Q – October 2011 – Revised December 2019
www.ti.com ARM Cortex-A8 MPU Subsystem
3.1 ARM Cortex-A8 MPU Subsystem

The Microprocessor Unit (MPU) subsystem of the device handles transactions between the ARM core
(ARM® Cortex™-A8 Processor), the L3 interconnect, and the interrupt controller (INTC). The MPU
subsystem is a hard macro that integrates the ARM® Cortex™-A8 Processor with additional logic for
protocol conversion, emulation, interrupt handling, and debug enhancements.
Cortex™-A8 is an ARMv7 compatible, dual-issue, in-order execution engine with integrated L1 and L2
caches with NEON™ SIMD Media Processing Unit.
An Interrupt Controller is included in the MPU subsystem to handle host interrupt requests in the system.
The MPU subsystem includes CoreSight compliant logic to allow the Debug Sub-system access to the
CortexA8 debug and emulation resources, including the Embedded Trace Macrocell.
The MPU subsystem has three functional clock domains, including a high-frequency clock domain used by
the Cortex™-A8. The high-frequency domain is isolated from the rest of the system by asynchronous
bridges.
Figure 3-1 shows the high-level block diagram of the MPU subsystem.
Figure 3-1. Microprocessor Unit (MPU) Subsystem
MPU
Integer Neon Subsystem
Core Core
ETMSOC
L1 I L1 D
32KB w/SED 32KB w/SED
OCP2 Debug Bus

ATB 32 (OCP)
Cortex A8
L2
256KB w/ECC
ICE Crusher
128
AXI2OCP
ROM 275 MHz
64 AINTC System
176 KB 32
Interrupts
275 MHz
128 64
OCM RAM
(SRAM internal) I2ASYNC I2ASYNC
550 MHz 550 MHz MPU PLL
64 KB
128 64
OCP Master 0 OCP Master 1
CLK_M_OSC
T2ASYNC T2ASYNC Frm Master OSC
200 MHz 200 MHz
To L3 To L3
SPRUH73Q – October 2011 – Revised December 2019 ARM MPU Subsystem 187
ARM Cortex-A8 MPU Subsystem www.ti.com
3.1.1 Features
This section outlines the key features of the MPU subsystem:
• ARM Microprocessor
– Cortex-A8
– ARM Architecture version 7 ISA.
– 2-issue, in-order execution pipeline.
– L1 Instruction and Data Cache of 32KB, 4-way, 16-word line with 128-bit interface.
– Integrated L2 cache of 256 KB, 8-way, 16 word line, 128 bit interface to L1 along with ECC/Parity
supported.
– Includes the Neon Media coprocessor (NEON™) which implements the Advanced SIMD media
processing architecture.
– Includes the VFP coprocessor which implements the VFPv3 architecture and is fully compliant with
IEEE 754 standard.
– The external interface uses the AXI protocol configured to 128-bit data width.
– Includes the Embedded Trace Macrocell (ETM) support for non-invasive debugging.
– Implements the ARMv7 debug with watch-point and breakpoint registers and 32-bit Advanced
Peripheral Bus (APB) slave interface to CoreSight debug systems.
• AXI2OCP Bridge
– Support OCP 2.2.
– Single Request Multiple Data Protocol on two ports.
– Multiple targets, including three OCP ports (128-bit, 64-bit and 32-bit).
• Interrupt Controller
– Support up to 128 interrupt requests
• Emulation/Debug
– Compatible with CoreSight Architecture.
• Clock Generation
– Through PRCM
3.1.2 MPU Subsystem Integration

The MPU subsystem integrates the following group of submodules:
ARM® Cortex®-A8 Processor: Provides a high processing capability, including the NEON technology for
mobile multimedia acceleration. The ARM communicates through an AXI bus with the AXI2OCP bridge
and receives interrupts from the MPU subsystem interrupt controller (MPU INTC).
Interrupt controller: Handles the module interrupts (for details, see Chapter 6, Interrupts).
AXI2OCP bridge: Allows communication between the ARM (AXI), the INTC (OCP), and the modules
(OCP L3).
I2Async bridge: This is an asynchronous bridge interface providing an asynchronous OCP to OCP
interface. This interface is between the AXI2OCP bridge within the MPU subsystem and the T2Async
bridge external to the MPU subsystem.
Clock Generator: Provides the required divided clocks to the internal modules of the MPU subsystem
and has a clock input from MPU_CLK which is fed by the power, reset, and clock management (PRCM)
module of the device.
In-Circuit Emulator: It is fully Compatible with CoreSight Architecture and enables debugging capabilities.
Device
MPU subsystem
ARM Cortex-A8 NEON_RST

NEON
MPU_MSTANDBY
MPU_INTC_IRQ
MPU_INTC_FIQ
Device
modules
AXI
Interrupts
sys_nirq
PRCM
INTC
AXI
MOCP CORE_RST
(P)
AXI2OCP
MOCP MPU MPU_CLK

(P) clock
generator
L3_ICLK
MPU_RST
Non-OCP Level T2Async

I2Async L3
shift
Figure 3-2. Microprocessor Unit (MPU) Subsystem Signal Interface
3.1.3 MPU Subsystem Clock and Reset Distribution
3.1.3.1 Clock Distribution

The MPU subsystem includes an embedded DPLL which sources the clock for the ARM Cortex-A8
processor. A clock divider within the subsystem is used for deriving the clocks for other internal modules.
All major modules inside the MPU subsystem are clocked at half the frequency of the ARM core. The
divider of the output clock can be programmed with the CM_DIV_M2_DPLL_MPU.DPLL_CLKOUT_DIV
register field, the frequency is relative to the ARM core. For details see Chapter 8, Power, Reset, and
Clock Management (PRCM).
The clock generator generates the following functional clocks:
ARM (ARM_FCLK): This is the core clock. It is the base fast clock that is routed internally to the ARM
logic and internal RAMs, including NEON, L2 cache, the ETM core (emulation), and the ARM core.
AXI2OCP Clock (AXI_FCLK): This clock is half the frequency of the ARM clock (ARM_FCLK). The OCP
interface thus performs at one half the frequency of ARM.
Interrupt Controller Functional Clock (MPU_INTC_FCLK): This clock, which is part of the INTC
module, is half the frequency of the ARM clock (ARM_FCLK).
ICE-Crusher Functional Clock (ICECRUSHER_FCLK): ICE-Crusher clocking operates on the APB
interface, using the ARM core clocking. This clock is half the frequency of the ARM clock (ARM_FCLK).
I2Async Clock (I2ASYNC_FCLK): This clock is half the frequency of the ARM clock (ARM_FCLK). It
matches the OCP interface of the AXI2OCP bridge.
NOTE: The second half of the asynchronous bridge (T2ASYNC) is clocked directly by the PRCM
with the core clock. T2ASYNC is not part of the MPU subsystem.
Emulation Clocking: Emulation clocks are distributed by the PRCM module and are asynchronous to the
ARM core clock (ARM_FCLK) and can run at a maximum of 1/3 the ARM core clock.
Table 3-1 summarizes the clocks generated in the MPU subsystem by the MPU clock generator.
MPU subsystem
INTC_FCLK (ARM_FCLK/2)
INTC
AXI2OP_FCLK (ARM_FCLK/2)
AXI2OCP
MPU_CLK MPU I2ASYNC_FCLK (ARM_FCLK/2)
clock I2Async
generator
PRCM ICECRUSHER_FCLK (ARM_FCLK/2)
ICECrusher
ARM_FCLK
ARM Cortex-A8
EMU EMU_CLOCKS
Emulation/
DPLL trace/debug
Figure 3-3. MPU Subsystem Clocking Scheme
Table 3-1. MPU Subsystem Clock Frequencies

Clock signal Frequency
Cortex A8 Core Functional Clock MPU_CLK
AXI2OCP Bridge Functional Clock MPU_CLK / 2
Device Clock MPU_CLK / 2
I2Async Bridge Functional Clock MPU_CLK / 2
3.1.3.2 Reset Distribution

Resets to the MPU subsystem are provided by the PRCM and controlled by the clock generator module.
MPU subsystem
CORE_RST
INTC
MPU_RST
AXI2OCP
I2Async
PRCM
ARM Cortex-A8
NEON_RST
NEON
EMU_RST
EMU_RSTPWRON EMU
MPU_RSTPWRON
ICECrusher
Figure 3-4. Reset Scheme of the MPU Subsystem
Table 3-2. Reset Scheme of the MPU Subsystem

Signal Name I/O Interface
MPU_RST I PRCM
NEON_RST I PRCM
CORE_RST I PRCM
MPU_RSTPWRON I PRCM
EMU_RST I PRCM
EMU_RSTPWRON I PRCM
For details about clocks, resets, and power domains, see Chapter 8, Power, Reset, and Clock
Management (PRCM).
3.1.4 ARM Subchip
3.1.4.1 ARM Overview

The ARM Cortex-A8 processor incorporates the technologies available in the ARM7™ architecture. These
technologies include NEON™ for media and signal processing and Jazelle™ RCT for acceleration of
realtime compilers, Thumb®-2 technology for code density and the VFPv3 floating point architecture.
3.1.4.2 ARM Description
3.1.4.2.1 ARM® Cortex™-A8 Instruction, Data, and Private Peripheral Port

The AXI bus interface is the main interface to the ARM system bus. It performs L2 cache fills and non-
cacheable accesses for both instructions and data. The AXI interface supports 128bit and 64-bit wide
input and output data buses. It supports multiple outstanding requests on the AXI bus and a wide range of
bus clock to core clock ratios. The bus clock is synchronous with the core clock.
See the ARM ® Cortex™-A8 Technical Reference Manual for a complete programming model of the
transaction rules (ordering, posting, and pipeline synchronization) that are applied depending on the
memory region attribute associated with the transaction destination address.
3.1.4.2.2 Secure Monitor Calls to Access CP15 Registers

The device supports special secure monitor functions that allows access to certain ARM core registers in
privileged mode. Functions to write to the Auxiliary Control Register, Nonsecure Access Control Register,
and the L2 Cache Auxiliary Control Register are provided (see the ARM Technical Reference Manual for a
description of these registers).
Service ID (R12) Description

0x100 Write value in R0 to Auxiliary Control Register
0x101 Write value in R0 to Non Secure Access Control Register
0x102 Write value in R0 to L2 Cache Auxiliary Control Register
In general, the procedure to use these secure monitor call is as follows:

• Write the appropriate service ID to R12 .
• Load R0 with the value to write to the ARM core register.
• Perform barrier operations to ensure proper execution.
• Use SMC #1 (or SMI #1) to make the secure monitor call
Barrier instructions are also necessary to ensure a clean state before entering the secure monitor. Refer
to the following example which provides the proper code sequence. This code provides an example of
enabling ECC on L2 cache. Note: This function should be executed in an ARM privileged mode.
_enableL2ECC:
STMFD sp!, {r0 - r4} ; save context of R0-R4, which secure monitor call may use
MRC p15, #1, r0, c9, c0, #2 ; Read L2 Cache Auxiliary Control Reg into R0
MOV r1, #0 ; Clear R1
MOVT r1, #0x1020 ; enable mask for ECC (set bits 21 and 28 to enable ECC)
ORR r0, r0, r1 ; OR with original register value
MOV r12, #0x0102 ; setup service ID in R12
MCR p15,#0x0,r1,c7,c5,#6 ; invalidate entire branch predictor array
DSB ; data synchronization barrier operation
ISB ; instruction synchronization barrier operation
DMB ; data memory barrier operation
SMC #1 ; secure monitor call SMC (previously SMI)
LDMFD sp!, {r0 - r4} ; after returning from SMC, restore R0-R4
MOV pc, lr ; return
3.1.4.2.3 ARM Core Supported Features

Table 3-3 provides a list of main functions of the Cortex™-A8 core supported inside the MPU Subsystem.
Table 3-3. ARM Core Supported Features

Features Comments
ARM version 7 ISA Standard ARM instruction set + Thumb2™, JazelleX™ Java
accelerator, and Media extensions.
Backward compatible with previous ARM ISA versions.
L1 Icache and Dcache 32 KB , 4-way, 16 word line, 128 bit interface.
L2 Cache 256 KB, 8-way, 16 word line, 128 bit interface to L1, ECC/Parity
is supported. The L2 cache and cache controller are embedded
within the ARM core.
L2 valid bits cleared by software loop or by hardware.
TLB Fully associative and separate ITLB with 32 entries and DTLB
with 32 entries.
CoreSight ETM The CoreSight ETM is embedded with the ARM core. The 32KB
buffer (ETB) exists at the Chip Level (DebugSS)
Branch Target Address Cache 512 entries
Enhanced Memory Management Unit Mapping sizes are 4KB, 64KB, 1MB, and 16MB. (ARM MMU
adds extended physical address ranges)
Neon Gives greatly enhanced throughput for media workloads and
VFP-Lite support.
Flat Memories 176 Kbytes of ROM
64 Kbytes of RAM
Buses 128 bit AXI internal bus from CortexA8 routed by an AXI2OCP
bridge to the interrupt controller, ROM, RAM, and 3
asynchronous OCP bridges (128 bits, and 64 bits)
Low interrupt latency Closely coupled INTC to the ARM core with 128 interrupt lines
Vectored Interrupt Controller Port Present.
JTAG based debug Supported via DAP
Trace support Supported via TPIU
External Coprocessor Not supported
3.1.5 Interrupt Controller

The Host ARM Interrupt Controller (AINTC) is responsible for prioritizing all service requests from the
system peripherals and generating either nIRQ or nFIQ to the host. The type of the interrupt (nIRQ or
nFIQ) and the priority of the interrupt inputs are programmable. The AINTC interfaces to the ARM
processor via the AXI port through an AXI2OCP bridge and runs at half the processor speed. It has the
capability to handle up to 128 requests which can be steered/prioritized as A8 nFIQ or nIRQ interrupt
requests.
The general features of the AINTC are:
• Up to 128 level sensitive interrupts inputs
• Individual priority for each interrupt input
• Each interrupt can be steered to nFIQ or nIRQ
• Independent priority sorting for nFIQ and nIRQ
3.1.6 Power Management
3.1.6.1 Power Domains

The MPU subsystem is divided into four power domains controlled by the PRCM, as shown in Figure 3-5.
NOTE: The emulation domain and the core domain are not fully embedded in MPU subsystem.
MPU subsystem
MPU_RST
MPU domain
ARM Cortex™-A8
I2Async
AXI2OCP
SRAM L1
SRAM L2
MPU_RSTPWRON
IceCrusher
EMU_RSTPWRON
Emulation domain EMU_RST
NEON_RST
NEON domain
INTC
CORE_RST
Core domain
Figure 3-5. MPU Subsystem Power Domain Overview
Power management requirements at the device level govern power domains for the MPU subsystem. The
device-level power domains are directly aligned with voltage domains and thus can be represented as a
cross reference to the different voltage domains.
Table 3-4 shows the different power domains of the MPU subsystem and the modules inside.
Table 3-4. Overview of the MPU Subsystem Power Domain

Functional Power Domain Physical Power Domain per System/Module
MPU subsystem domain ARM, AXI2OCP, I2Asynch Bridge, ARM L1 and L2 periphery
logic and array, ICE-Crusher, ETM, APB modules
MPU NEON domain ARM NEON accelerator
CORE domain MPU interrupt controller
EMU domain EMU (ETB,DAP)
NOTE: L1 and L2 array memories have separate control signals into the in MPU Subsystem, thus
directly controlled by PRCM For details on the physical power domains and the voltage
domains, see Chapter 8, Power, Reset, and Clock Management (PRCM).
3.1.6.2 Power States

Each power domain can be driven by the PRCM in 3 different states, depending on the functional mode
required by the user.
For each power domain the PRCM manages all transitions by controlling domain clocks, domain resets,
domain logic power switches and memory power switches.
Table 3-5. MPU Power States

Power State Logic Power Memory Power Clocks
Active On On or Off On (at least one clock)
Inactive On On or Off Off
Off Off Off Off (all clocks)
3.1.6.3 Power Modes

The major part of the MPU subsystem belongs to the MPU power domain. The modules inside this power
domain can be off at a time when the ARM processor is in an OFF or standby mode. IDLE/WAKEUP
control is managed by the clock generator block but initiated by the PRCM module.
The MPU Standby status can be checked with CM_MPU_MPU_CLKCTRL.STBYST. For the MPU to be
on, the core (referred here as the device core) power must be on. Device power management does not
allow INTC to go to OFF state when MPU domain is on (active or one of retention modes).
The NEON core has independent power off mode when not in use. Enabling and disabling of NEON can
be controlled by software.
CAUTION
The MPU L1 cache memory does not support retention mode, and its array
switch is controlled together with the MPU logic. For compliance, the L1
retention control signals exist at the PRCM boundary, but are not used. The
ARM L2 can be put into retention independently of the other domains.
Table 3-6 outlines the supported operational power modes. All other combinations are illegal. The ARM
L2, NEON, and ETM/Debug can be powered up/down independently. The APB/ATB ETM/Debug column
refers to all three features: ARM emulation, trace, and debug.
The MPU subsystem must be in a power mode where the MPU power domain, NEON power domain,
debug power domain, and INTC power domain are in standby, or off state.
Table 3-6. MPU Subsystem Operation Power Modes

Mode MPU and ARM Core ARM L2 RAM NEON INTC Device Core and ETM APB/ATB Debug
Logic
1 Active Active Active Active Disabled or enabled
2 Active Active OFF Active Disabled or enabled
3 Active RET Active Active Disabled or enabled
4 Active RET OFF Active Disabled or enabled
5 Active OFF Active Active Disabled or enabled
6 Active OFF OFF Active Disabled or enabled
7 OFF RET OFF OFF Disabled or enabled
8 Standby Active Standby Active Disabled or enabled
9 Standby Active OFF Active Disabled or enabled
10 Standby RET Standby Active Disabled or enabled
11 Standby RET OFF Active Disabled or enabled
12 Standby OFF Standby Active Disabled or enabled
13 Standby OFF OFF Active Disabled or enabled
14 OFF OFF OFF OFF Disabled or enabled
3.1.7 ARM Programming Model

For detailed descriptions of registers used for MPU configuration, see Chapter 8, Power, Reset, and Clock
Management (PRCM).
3.1.7.1 Clock Control

For clock configuration settings, see Chapter 8, Power, Reset, and Clock Management (PRCM).
3.1.7.2 MPU Power Mode Transitions

The following subsections describe transitions of different power modes for MPU power domain:
• Basic power on reset
• MPU into standby mode
• MPU out of standby mode
• MPU power on from a powered off state
3.1.7.2.1 Basic Power-On Reset

The power-on reset follows the following sequence of operation and is applicable to initial power-up and
wakeup from device off mode:
Reset the INTC (CORE_RST) and the MPU subsystem modules (MPU_RST). The clocks must be
active during the MPU reset and CORE reset.
3.1.7.2.2 MPU Into Standby Mode

The MPU into standby mode follows the following sequence of operation and is applicable to initial power-
up and wakeup from device Off mode.
1. The ARM core initiates entering into standby via software only (CP15 - WFI).
2. MPU modules requested internally of MPU subsystem to enter idle, after ARM core standby detected.
3. MPU is in standby output asserted for PRCM (all outputs guaranteed to be at reset values).
4. PRCM can now request INTC to enter into idle mode. Acknowledge from INTC goes to PRCM.
NOTE: The INTC SWAKEUP output is a pure hardware signal to PRCM for the status of its IDLE
request and IDLE acknowledge handshake.
NOTE: In debug mode, ICE-Crusher could prevent MPU subsystem from entering into IDLE mode.
3.1.7.2.3 MPU Out Of Standby Mode

The MPU out of standby mode follows the following sequence of operation and is applicable to initial
power-up and wakeup from device Off mode.
1. PRCM must start clocks through DPLL programming.
2. Detect active clocking via status output of DPLL.
3. Initiate an interrupt through the INTC to wake up the ARM core from STANDBYWFI mode.
3.1.7.2.4 MPU Power On From a Powered-Off State

1. MPU Power On, NEON Power On, Core Power On (INTC) should follow the ordered sequence per
power switch daisy chain to minimize the peaking of current during power-up.
NOTE: The core domain must be on, and reset, before the MPU can be reset.
2. Follow the reset sequence as described in the Basic Power-On Reset section.
Chapter 4
Programmable Real-Time Unit Subsystem and Industrial

Communication Subsystem (PRU-ICSS)
This chapter describes the PRU-ICSS for the device.
Topic ........................................................................................................................... Page
4.1 Introduction ..................................................................................................... 199

4.2 Integration ....................................................................................................... 201
4.3 PRU-ICSS Memory Map Overview ....................................................................... 206
4.4 Functional Description ...................................................................................... 208
4.5 Registers ......................................................................................................... 274
198 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
Subsystem (PRU-ICSS) Submit Documentation Feedback
www.ti.com Introduction
4.1 Introduction
The Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
consists of dual 32-bit RISC cores (Programmable Real-Time Units, or PRUs), shared, data, and
instruction memories, internal peripheral modules, and an interrupt controller (INTC). The programmable
nature of the PRU, along with its access to pins, events and all SoC resources, provides flexibility in
implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces,
and in offloading tasks from the other processor cores of the system-on-chip (SoC).
Figure 4-1 shows the PRU-ICSS details.
The PRUs have access to all resources on the SoC through the Interface/OCP Master port, and the
external host processors can access the PRU-ICSS resources through the Interface/OCP Slave port. The
32-bit interconnect bus connects the various internal and external masters to the resources inside the
PRU-ICSS. The INTC handles system input events and posts events back to the device-level host CPU.
The PRU cores are programmed with a small, deterministic instruction set. Each PRU can operate
independently or in coordination with each other and can also work in coordination with the device-level
host CPU. This interaction between processors is determined by the nature of the firmware loaded into the
PRU’s instruction memories.
Figure 4-1. PRU-ICSS Block Diagram
PRU-ICSS
Data Mem0
PRU0 Core (8KB)
(8KB Program)
Data Mem1
EGP IO MAC (8KB)
32-Bit Interconnect Bus
SPAD Shared RAM

(12KB)
PRU1 Core
(8KB Program) eCAP0
EGP IO MAC MII0_RT
IEP
INTC UART0
CFG
SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 199
Submit Documentation Feedback Subsystem (PRU-ICSS)
Introduction www.ti.com
4.1.1 Features
The PRU-ICSS includes the following main features:
• Two PRUs each with:
– 8KB program memory
– 8KB data memory
– High Performance Interface/OCP Master port for accessing external memories
– Enhanced GPIO (EGPIO) with async capture and serial support
– Multiplier with optional accumulation (MPY/MAC)
• One scratch pad (SPAD) memory
– 3 Banks of 30 32-bit registers
• Broadside direct connect between PRU cores within subsystem
• 12 KB general purpose shared memory
• One Interrupt Controller (INTC)
– Up to 64 input events supported
– Interrupt mapping to 10 interrupt channels
– 10 Host interrupts (2 to PRU0 and PRU1, 8 output to chip level)
– Each system event can be enabled and disabled
– Each host event can be enabled and disabled
– Hardware prioritization of events
• 16 software events generated by 2 PRUs
• One Ethernet MII_RT module with two MII ports and configurable connections to PRUs*
• One MDIO Port*
• One Industrial Ethernet Peripheral (IEP) to manage/generate Industrial Ethernet functions
– One Industrial Ethernet timer with 10 capture* and eight compare events
– Two Industrial Ethernet sync signals*
– Two Industrial Ethernet 16-bit watchdog timers*
– Industrial Ethernet digital IOs
• One 16550-compatible UART with a dedicated 192-MHz clock, supporting up to 12Mbaud for
PROFIBUS DP
• One Enhanced Capture Module (ECAP)
• Flexible power management support
• Integrated 32-bit interconnect bus for connecting the various internal and external masters to the
resources inside the PRU-ICSS
• Interface/OCP Slave port for external masters to access PRU-ICSS memories
• Optional address translation for PRU transaction to External Host
• All memories within the PRU-ICSS support parity
www.ti.com Integration
4.2 Integration
The device includes a Programmable Real-Time Unit Subsystem and Industrial Communication
Subsystem (PRU-ICSS) consisting of two independent Programmable Real-time Units (PRUs). Each PRU
is a 32-bit Load/Store RISC processor with dedicated memories. The PRU-ICSS integration is shown in
Figure 4-2.
Figure 4-2. PRU-ICSS Integration

pr1_mii_mt0_clk
pr1_mii0_rxlink
pr1_mii0_crs
pr1_mii0_col
pr1_mii0_rxer
pr1_mii0_txen
pr1_mii0_txd3
PRU-ICSS pr1_mii0_txd2
pr1_mii0_txd1
pr1_mii0_txd0
Bridge
pr1_mii_mr0_clk
Async
Interface/ pr1_mii0_rxdv
L4 Fast
OCP Slave port pr1_mii0_rxd3
pr1_mii0_rxd2
pr1_mii0_rxd1
pr1_mii0_rxd0
pr1_mdio_data
OCP_HP0 MII_RT pr1_mdio_mdclk
Bridge
Async
PRU0 Core
L3 Fast (Interface/OCP pr1_mii_mt1_clk
(8KB Program RAM) pr1_mii1_rxlink
Master port)
Data RAM0 pr1_mii1_crs
(8KB) pr1_mii1_col
pr1_mii1_rxer
pr1_mii1_txen
pr1_pru0_pru_r31[16:0] Enhanced pr1_mii1_txd3
MAC Data RAM1
pr1_pru0_pru_r30[15:0] GPIO pr1_mii1_txd2
32-bit Interconnect Bus (8KB) pr1_mii1_txd1
Scratch pr1_mii1_txd0
ocp_clk Pad pr1_mii_mr1_clk
Shared RAM pr1_mii1_rxdv
uart_clk (12KB)
PRCM iep_clk Clocks/Reset pr1_mii1_rxd3
rst_main_arst_n pr1_mii1_rxd2
pr1_mii1_rxd1
CFG pr1_mii1_rxd0
pr1_edio_sof
OCP_HP1 Industrial pr1_edio_latch_in
Bridge
Async
PRU1 Core pr1_edio_data_in/out[7:0]

L3 Fast (Interface/OCP (8KB Program RAM) Ethernet
pr1_edc_latch0_in
Master port) Peripheral pr1_edc_latch1_in
(IEP) pr1_edc_sync0_out
pr1_edc_sync1_out
pr1_pru1_pru_r31[16:0] Enhanced pr1_uart0_cts_n

MAC UART0
pr1_pru1_pru_r30[15:0] GPIO pr1_uart0_rts_n
pr1_uart0_rxd
To Host ARM Interrupts pr1_uart0_txd
To EDMA Events
To TSC_ADC Event eCAP pr1_ecap0_ecap_capin_apwm_o
INTC
Events from Select
Peripherals
For the availability of all features, see the device features in Chapter 1, Introduction.
Integration www.ti.com
4.2.1 PRU-ICSS Connectivity Attributes

The general connectivity attributes for the PRU subsystem are shown in Table 4-1.
Table 4-1. PRU-ICSS Connectivity Attributes

Attributes Type
Power Domain Peripheral Domain
Clock Domain PD_PER_PRU_ICSS_OCP_GCLK (OCP clock)
PD_PER_PRU_ICSS_IEP_GCLK (IEP clock)
PD_PER_PRU_ICSS_UART_GCLK (UART clock)
Reset Signals PRU_ICSS_LRST_N
Idle/Wakeup Signals Standby
Idle
Interrupt Requests 8 Interrupts
pr1_host_intr[7:1] (1) to MPU Subsystem
pr1_host_intr[0] (1) to MPU Subsystem and TSC_ADC
DMA Requests No dedicated DMA events but pr1_host_intr[7:6] (1) interrupt
outputs also connected as DMA events
Physical Address L4 Fast Slave Port
(1)
pr1_host_intr[0:7] corresponds to Host-2 to Host-9 of the PRU-ICSS interrupt controller.
4.2.2 PRU-ICSS Clock and Reset Management

The PRU-ICSS module uses the following functional and OCP interface clocks.
Table 4-2. PRU-ICSS Clock Signals

Clock Signal Max Freq Reference / Source Comments
l3_clk 200 MHz CORE_CLKOUTM4 or Display pd_per_pru_icss_ocp_gclk
Interface Clock PLL CLKOUT from PRCM
Clocks both L3 master and L4F
slave
uart_clk 192 MHz PER_CLKOUTM2 pd_per_pru_icss_uart_gclk
Functional Clock from PRCM
UART Clock
iep_clk 200 MHz CORE_CLKOUTM4 pd_per_pru_icss_iep_gclk from
Functional Clock PRCM
Industrial Ethernet Peripheral
Clock
4.2.3 PRU-ICSS Pin List

The PRU-ICSS external interface signals are shown in Table 4-3. PRU GPI/GPO pin function depends on
the operation mode. SeeTable 4-3 for a complete list of pin functions for each mode.
Table 4-3. PRU-ICSS Pin List

Pin Type Description
pr1_mii_mr0_clk I MII0 Receive Clock
pr1_mii0_rxdv I MII0 Receive Data Valid
pr1_mii0_rxd[3:0] I MII0 Receive Data
pr1_mii0_rxlink I MII0 Receive Link
pr1_mii0_rxer I MII0 Receive Data Error
pr1_mii0_crs I MII0 Carrier Sense
pr1_mii0_col I MII0 Carrier Sense
pr1_mii_mt0_clk I MII0 Transmit Clock
pr1_mii0_txen O MII0 Transmit Enable
pr1_mii0_txd[3:0] O MII0 Transmit Data
pr1_mii_mr1_clk I MII1 Receive Clock
pr1_mii1_rxdv I MII1 Receive Data Valid
pr1_mii1_rxd[3:0] I MII1 Receive Data
pr1_mii1_rxlink I MII1 Receive Link
pr1_mii1_rxer I MII1 Receive Data Error
pr1_mii1_crs I MII1 Carrier Sense
pr1_mii1_col I MII1 Carrier Sense
pr1_mii_mt1_clk I MII1 Transmit Clock
pr1_mii1_txen O MII1 Transmit Enable
pr1_mii1_txd[3:0] O MII1 Transmit Data
pr1_mdio_mdclk O MDIO Clk
pr1_mdio_data I/O MDIO Data
pr1_edio_sof O ECAT Digital I/O Start of Frame
pr1_edio_latch_in I ECAT Digital I/O Latch In
pr1_edio_data_in[7:0] I ECAT Digital I/O Data In
pr1_edio_data_out[7:0] O ECAT Digital I/O Data Out
pr1_edc_sync0_out O ECAT Distributed Clock Sync Out
pr1_edc_sync1_out O ECAT Distributed Clock Sync Out
pr1_edc_latch0_in I ECAT Distributed Clock Latch In
pr1_edc_latch1_in I ECAT Distributed Clock Latch In
pr1_uart0_cts_n I UART Clear to Send
pr1_uart0_rts_n O UART Request to Send
pr1_uart0_rxd I UART Receive Data
pr1_uart0_txd O UART Transmit Data
pr1_ecap0_ecap_capin_apwm_o I/O Enhanced capture (ECAP) input or
Auxiliary PWM out
pr1_pru0_pru_r30[15:0] O PRU0 Register R30 (GPO) Outputs
pr1_pru0_pru_r31[16:0] I PRU0 Register R31 (GPI)Inputs
pr1_pru1_pru_r30[15:0] O PRU1 Register R30 (GPO) Outputs
pr1_pru1_pru_r31[16:0] I PRU1 Register R31 (GPI) Inputs
4.2.4 PRU-ICSS Internal Pinmux

The PRU-ICSS supports an internal pinmux selection option that expands the device-level pinmuxing. The
internal pinmuxing is programmable through the PIN_MX register of the PRU-ICSS CFG register space.
The pin_mux_sel[0] determines the external signals routed to the internal input signals, mii0_rxd[3:0]. The
pin_mux_sel[1] determines the internal output signals routed to the external signals,
pr1_pru0_pru_r30[13:8], and the external signals routed to the internal input signals, pru0_r30[5:0].
Note: pin_mux_sel[x] = 0 is always the standard pin mapping (default).
Table 4-4. PRU-ICSS Internal Signal Muxing: pin_mux_sel[0]

pin_mux_sel[0] = 1 pin_mux_sel[0] = 0
Internal PRU-ICSS Signal Name External Chip Level Signal Name
mii0_rxd[3:0] pr1_pru1_pru_r31[8:11] pr1_mii0_rxd[3:0]
Figure 4-3. PRU-ICSS Internal Signal Muxing: pin_mux_sel[0]
PRU-ICSS
pr1_mii0_rxd[3:0]
0
mii0_rxd[3:0]
pr1_pru1_pru_r31[8:11]
1
pin_mux_sel[0]
pru1_r31_status[8:11]
Table 4-5. PRU-ICSS Internal Signal Muxing: pin_mux_sel[1]

pin_mux_sel[1] = 1 pin_mux_sel[1] = 0
External Chip Level Signal Name Internal PRU-ICSS Signal Name
pr1_pru0_pru_r30[13:8] pru1_r30[5:0] pru0_r30[13:8]
Internal PRU-ICSS Signal Name External Chip Level Signal Name
pru1_r31_status[5:0] pr1_pru0_pru_r31[13:8] pr1_pru1_pru_r31[5:0]
Figure 4-4. PRU-ICSS Internal Signal Muxing: pin_mux_sel[1]
PRU-ICSS
pru1_r30[5:0]
1
pru0_r30[13:8]
0
pin_mux_sel[1]
0
pru1_r31[5:0]
1
pin_mux_sel[1]
pru0_r31[13:8]
PRU-ICSS Memory Map Overview www.ti.com
4.3 PRU-ICSS Memory Map Overview

The PRU-ICSS comprises various distinct addressable regions that are mapped to both a local and global
memory map. The local memory maps are maps with respect to the PRU core point of view. The global
memory maps are maps with respect to the Host point of view, but can also be accessed by the PRU-
ICSS.
4.3.1 Local Memory Map

The PRU-ICSS memory map is documented in Table 4-6 (Instruction Space) and in Table 4-7 (Data
Space). Note that these two memory maps are implemented inside the PRU-ICSS and are local to the
components of the PRU-ICSS.
4.3.1.1 Local Instruction Memory Map

Each PRU core has a dedicated 8KB of Instruction Memory which needs to be initialized by a Host
processor before the PRU executes instructions. This region is only accessible to masters via the
interface/ OCP slave port when the PRU is not running.
Table 4-6. Local Instruction Memory Map

Start Address PRU0 PRU1
0x0000_0000 8KB IRAM 8KB IRAM
4.3.1.2 Local Data Memory Map

The local data memory map in Table 4-7 allows each PRU core to access the PRU-ICSS addressable
regions and the external host’s memory map.
The PRU accesses the external Host memory map through the Interface/OCP Master port (System
OCP_HP0/1) starting at address 0x0008_0000. By default, memory addresses between 0x0000_0000 –
0x0007_FFFF will correspond to the PRU-ICSS local address in Table 4-7. To access an address
between 0x0000_0000–0x0007_FFFF of the external Host map, the address offset of –0x0008_0000
feature is enabled through the PMAO register of the PRU-ICSS CFG register space.
Table 4-7. Local Data Memory Map

(1)
0x0000_0000 Data 8KB RAM 0 Data 8KB RAM 1 (1)
(1)
0x0000_2000 Data 8KB RAM 1 Data 8KB RAM 0 (1)
0x0001_0000 Shared Data 12KB RAM 2 Shared Data 12KB RAM 2
0x0002_0000 INTC INTC
0x0002_2000 PRU0 Control PRU0 Control
0x0002_2400 Reserved Reserved
0x0002_4000 PRU1 Control PRU1 Control
0x0002_6000 CFG CFG
0x0002_8000 UART 0 UART 0
0x0002_A000 Reserved Reserved
0x0002_C000 Reserved Reserved
0x0002_E000 IEP IEP
0x0003_0000 eCAP 0 eCAP 0
0x0003_2000 MII_RT_CFG MII_RT_CFG
0x0003_2400 MII_MDIO MII_MDIO
(1)
Data RAM0 is intended to be the primary data memory for PRU0, as is Data RAM1 for PRU1. However, both PRU cores can
access Data RAM0 and Data RAM1 to pass information between PRUs. Each PRU core accesses their intended Data RAM at
address 0x0000_0000 and the other Data RAM at address 0x0000_2000.
www.ti.com PRU-ICSS Memory Map Overview
Table 4-7. Local Data Memory Map (continued)

0x0008_0000 System OCP_HP0 System OCP_HP1
4.3.2 Global Memory Map

The global view of the PRU-ICSS internal memories and control ports is shown in Table 4-8. The offset
addresses of each region are implemented inside the PRU-ICSS but the global device memory mapping
places the PRU-ICSS slave port in the address range shown in the external Host top-level memory map.
The global memory map is with respect to the Host point of view, but it can also be accessed by the PRU-
ICSS. Note that PRU0 and PRU1 can use either the local or global addresses to access their internal
memories, but using the local addresses will provide access time several cycles faster than using the
global addresses. This is because when accessing via the global address the access needs to be routed
through the switch fabric outside PRU-ICSS and back in through the PRU-ICSS slave port.
Each of the PRUs can access the rest of the device memory (including memory mapped peripheral and
configuration registers) using the global memory space addresses. See Table 4-8, Global Memory Map,
for base addresses of each module in the device.
Table 4-8. Global Memory Map

Offset Address PRU-ICSS
0x0000_0000 Data 8KB RAM 0
0x0000_2000 Data 8KB RAM 1
0x0001_0000 Shared Data 12KB RAM 2
0x0002_0000 INTC
0x0002_2000 PRU0 Control
0x0002_2400 PRU0 Debug
0x0002_4000 PRU1 Control
0x0002_4400 PRU1 Debug
0x0002_6000 CFG
0x0002_8000 UART 0
0x0002_A000 Reserved
0x0002_C000 Reserved
0x0002_E000 IEP
0x0003_0000 eCAP 0
0x0003_2000 MII_RT_CFG
0x0003_2400 MII_MDIO
0x0003_4000 PRU0 8KB IRAM
0x0003_8000 PRU1 8KB IRAM
0x0004_0000 Reserved
Functional Description www.ti.com
4.4 Functional Description
4.4.1 PRU Cores

The PRU is a processor optimized for performing embedded tasks that require manipulation of packed
memory mapped data structures, handling of system events that have tight real-time constraints and
interfacing with systems external to the SoC. The PRU is both very small and very efficient at handling
such tasks.
The major attributes of the PRU are as follows.
Attribute Value
IO Architecture Load / Store
Data Flow Architecture Register to Register
Core Level Bus Architecture
4-Bus Harvard (1 Instruction, 3 Data)
Type
32-Bit
Instruction I/F
32-Bit
Memory I/F 0
32-Bit
Memory I/F 1
Execution Model
Scalar
Issue Type
None (Purposefully)
Pipelining
In Order
Ordering
Unsigned Integer
ALU Type
Registers
30 (R1 – R30)
General Purpose (GP)
1 (R31)
External Status
1 (R0)
GP / Indexing
Bit, Byte (8-bit), Halfword (16-bit), Word (32-bit), Pointer
Addressability in Instruction
Addressing Modes
16-bit Immediate
Load Immediate
Load / Store – Memory Register Base + Register Offset

Register Base + 8-bit Immediate Offset
Register Base with auto increment / decrement
Constant Table Base + Register Offset
Constant Table Base + 8-bit Immediate Offset
Constant Table Base with auto increment / decrement
Data Path Width 32-Bits
Instruction Width 32-Bits
Accessibility to Internal PRU Structures Provides 32-bit slave with three regions:
• Instruction RAM
• Control / Status registers
• Debug access to internal registers (R0-R31) and constant
table
www.ti.com Functional Description
The processor is based on a four-bus architecture which allows instructions to be fetched and executed
concurrently with data transfers. In addition, an input is provided in order to allow external status
information to be reflected in the internal processor status register. Figure 4-5 shows a block diagram of
the processing element and the associated instruction RAM/ROM that contains the code that is to be
executed.
Figure 4-5. PRU Block Diagram
Op4 iram_XXX
i_data[31:0]
R0 Decode and Control
R0
op1 Mux
R1 Instruction
... Output RAM/ROM
Shifter (Clocked)
R1 R30 Shift/Mask
R31 Program i_addr[31:0]
Counter
R2
R0
Destination Selector
const_base_sel[4:0]
op2 Mux
R1 ALU Constants
... Shift/Mask Data
... I/F Constants Table
Path
R30 const_base[31:0]
R31
R29
R0 Memory mem0_XXX
Shift/Mask
I/F
op3 Mux
R30 R1 mem1_XXX
...
R30
R31(Status) Coprocessor I/F regs_XXX
R31
Register Execution Unit
File
R31(Event)
Output
Multiplexers PRU Core PRU
status_in[31:0] events_out[31:0]
4.4.1.1 Constants Table

The PRU Constants Table is a structure of hard-coded memory addresses for commonly used peripherals
and memories. The Constants table exists to more efficiently load/store data to these commonly accessed
addresses by:
• Reduce a PRU instruction by not needing to pre-load an address into the internal register file before
loading or storing data to a memory address
• Maximize the usage of the PRU register file for embedded processing applications by moving many of
the commonly used constants or deterministically calculated base addresses from the internal register
file to an external table.
Table 4-9. PRU0/1 Constants Table

Entry No. Region Pointed To Value [31:0]
0 PRU-ICSS INTC (local) 0x0002_0000
1 DMTIMER2 0x4804_0000
2 I2C1 0x4802_A000
3 PRU-ICSS eCAP (local) 0x0003_0000
4 PRU-ICSS CFG (local) 0x0002_6000
Table 4-9. PRU0/1 Constants Table (continued)

Entry No. Region Pointed To Value [31:0]
5 MMCHS 0 0x4806_0000
6 MCSPI 0 0x4803_0000
7 PRU-ICSS UART0 (local) 0x0002_8000
8 McASP0 DMA 0x4600_0000
9 GEMAC 0x4A10_0000
10 Reserved 0x4831_8000
11 UART1 0x4802_2000
12 UART2 0x4802_4000
13 Reserved 0x4831_0000
14 DCAN0 0x481C_C000
15 DCAN1 0x481D_0000
16 MCSPI 1 0x481A_0000
17 I2C2 0x4819_C000
18 eHRPWM1/eCAP1/eQEP1 0x4830_0000
21 PRU-ICSS MDIO (local) 0x0003_2400
22 Mailbox 0 0x480C_8000
23 Spinlock 0x480C_A000
24 PRU-ICSS PRU0/1 Data RAM (local) 0x0000_0n00, n = c24_blk_index[3:0]
25 PRU-ICSS PRU1/0 Data RAM (local) 0x0000_2n00, n = c25_blk_index[3:0]
26 PRU-ICSS IEP (local) 0x0002_En00, n = c26_blk_index[3:0]
27 PRU-ICSS MII_RT (local) 0x0003_2n00, n = c27_blk_index[3:0]
28 PRU-ICSS Shared RAM (local) 0x00nn_nn00, nnnn = c28_pointer[15:0]
29 TPCC 0x49nn_nn00, nnnn = c29_pointer[15:0]
30 L3 OCMC0 0x40nn_nn00, nnnn = c30_pointer[15:0]
31 EMIF0 DDR Base 0x80nn_nn00, nnnn = c31_pointer[15:0]
NOTE: Addresses in constants entries 24–31 are partially programmable. Their programmable bit
field (for example, c24_blk_index[3:0]) is programmable through the PRU CTRL register
space. As a general rule, the PRU should configure this field before using the partially
programmable constant entries.
4.4.1.2 PRU Module Interface to PRU I/Os and INTC

The PRU module interface consists of the PRU internal registers 30 and 31 (R30 and R31). Figure 4-6
shows the PRU module interface and the functionality of R30 and R31. The register R31 serves as an
interface with the dedicated PRU general purpose input (GPI) pins and PRU interrupt controller (INTC).
Reading R31 returns status information from the GPI pins and INTC via the PRU Real-Time Status
Interface. Writing to R31 generates PRU system events via the PRU Event Interface. The register R30
serves as an interface with the dedicated PRU general purpose output (GPO) pins. The R30/R31 GPO or
GPI register content changes depending on the selected configuration (such as MII_RT, Parallel Capture,
Shift Out, and so forth). See the subsequent sections for more details.
Figure 4-6. PRU Module Interface
PRU<n>
i
R30 GPO Content PR1_PRU<n>_PRU_R30[ i:0 ]
INTC INTC j
GPI Content
R31(R) status status PR1_PRU<n>_PRU_R31[ j:0 ]
(bits 29:0)
(bit 31) (bit 30)
R31(W) INTC System Event Generation
4.4.1.2.1 Real-Time Status Interface Mapping (R31): Interrupt Events Input

The PRU Real-Time Status Interface directly feeds information into register 31 (R31) of the PRU’s internal
register file. The firmware on the PRU uses the status information to make decisions during execution.
The status interface is comprised of signals from different modules inside of the PRU-ICSS which require
some level of interaction with the PRU. More details on the Host interrupts imported into bit 30 and 31 of
register R31 of both the PRUs is provided in Section 4.4.2, Interrupt Controller (INTC).
Table 4-10. Real-Time Status Interface Mapping (R31) Field Descriptions

31 pru_intr_in[1] PRU Host Interrupt 1 from local INTC
30 pru_intr_in[0] PRU Host Interrupt 0 from local INTC
29-0 pru<n>_r31_status[29: Status inputs from primary input via Enhanced GPI port
0]
4.4.1.2.2 Event Interface Mapping (R31): PRU System Events

This PRU Event Interface directly feeds pulsed event information out of the PRU’s internal ALU. These
events are exported out of the PRU-ICSS and need to be connected to the system event controller at the
SoC level. The event interface can be used by the firmware to create interrupts from the PRU to the Host
processor.
Figure 4-7. Event Interface Mapping (R31)
PRU0
R31(W) 5 3 2 1 0
4
D Q
EN
INTC System Events:

PRU1
pr1_pru_mst_intr[15:0]_intr_req
see
R31(W) 5 3 2 1 0
4
D Q
EN
Table 4-11. Event Interface Mapping (R31) Field Descriptions

31-6 Reserved
5 pru<n>_r31_vec_ Valid strobe for vector output
valid
4 Reserved
3-0 pru<n>_r31_vec[3 Vector output
:0]
Simultaneously writing a '1' to pru<n>_r31_vec_valid (R31 bit 5) and a channel number from 0-15 to
pru<n>_r31_vec[3:0] (R31 bits 3:0) creates a pulse on the output of the corresponding
pr1_pru_mst_intr[x]_intr_req INTC system event (Table 4-22). For example, writing '100000' will generate
a pulse on pr1_pru_mst_intr[0]_intr_req, writing '100001' will generate a pulse on
pr1_pru_mst_intr[1]_intr_req, and so on to where writing '101111' will generate a pulse on
pr1_pru_mst_intr[15]_intr_req and writing '0xxxxx' will not generate any system event pulses. The output
values from both PRU cores in a subsystem are ORed together.
The output channels 0-15 are connected to the PRU-ICSS INTC system events 16-31, respectively. This
allows the PRU to assert one of the system events 16-31 by writing to its own R31 register. The system
event is used to either post a completion event to one of the host CPUs (ARM) or to signal the other PRU.
The host to be signaled is determined by the system event to interrupt channel mapping (programmable).
The 16 events are named as pr1_pru_mst_intr<15:0>_intr_req. For more details, see Section 4.4.2,
Interrupt Controller (INTC).
4.4.1.2.3 General-Purpose Inputs (R31): Enhanced PRU GP Module

The PRU-ICSS implements an enhanced General-Purpose Input/Output (GPIO) module that supports the
following general-purpose input modes: direct input, 16-bit parallel capture, 28-bit serial shift in, and
MII_RT. Register R31 serves as an interface with the general purpose inputs.
Table 4-12 describes the input modes in detail. Note each PRU core can only be configured for one GPI
mode at a time. Each mode uses the same R31 signals and internal register bits for different purposes. A
summary is found in Table 4-13.
Table 4-12. PRU R31 (GPI) Modes

Mode Function Configuration
Direct input GPI[0:29] feeds directly into the PRU R31 Default mode
16-bit parallel capture DATAIN[0:15] is captured by the posedge • Enabled by CFG_GPCFGn register
or negedge of CLOCKIN
• CLOCKIN edge selected by
CFG_GPCFGn register
28-bit shift in DATAIN is sampled and shifted into a 28- • Enabled by CFG_GPCFGn register
bit shift. Shift Counter (Cnt_16) feature
• Cnt_16 is self clearing and is
uses:
connected to the PRU INTC
• Cnt_16 (Shift Counter) feature is
• Start Bit (SB) is cleared by
mapped to pru<n>_r31_status[28]
CFG_GPCFGn register
• SB (Start Bit detection) feature is
mapped to pru<n>_r31_status[29]
MII_RT mii_rt_r31_status [29:0] internally driven Enabled by CFG
by the MII_RT module
Table 4-13. PRU GPI Signals and Configurations

GPI Modes
Pad Names at Device Level
Direct Input Parallel Capture 28-Bit Shift In
pr1_pru<n>_pru_r31_0 GPI0 DATAIN0 DATAIN
pr1_pru<n>_pru_r31_1 GPI1 DATAIN1
pr1_pru<n>_pru_r31_16 GPI16 CLOCKIN
pr1_pru<n>_pru_r31_17 GPI17
Table 4-13. PRU GPI Signals and Configurations (continued)

GPI Modes
Direct Input Parallel Capture 28-Bit Shift In
NOTE: Some devices may not pin out all 30 bits of R31. For which pins are available on this device,
see Section 4.2.3, PRU-ICSS Pin List. See the device's datasheet for device-specific pin
mapping.
4.4.1.2.3.1 Direct Input

The pru<n>_r31_status [0:29] bits of the internal PRU register file are mapped to device-level general
purpose input pins (PRU<n>_GPI[0:29]). In GPI Direct Input mode, PRU<n>_GPI[0:29] feeds directly to
pru<n>_r31_status [0:29]. There are 30 possible general purpose inputs per PRU core; however, some
devices may not pin out all of these signals. See the device-specific datasheet for device specific pin
mapping.
Figure 4-8. PRU R31 (GPI) Direct Input Mode Block Diagram
PRU<n>_R31
0
1
PRU<n>_GPI [0:29] …
30 28
29
4.4.1.2.3.2 16-Bit Parallel Capture

The pru<n>_r31_status [0:15] and pru<n>_r31_status [16] bits of the internal PRU register file are mapped
to device-level general purpose input pins (PRU<n>_DATAIN[0:15] and PRU<n>_CLOCKIN, respectively).
PRU<n>_CLOCKIN is designated as an external strobe clock and is used to capture
PRU<n>_DATAIN[0:15].
The PRU<n>_DATAIN can be captured either on the positive or negative edge of PRU<n>_CLOCK,
programmable through the PRU-ICSS CFG register space. If the clocking is configured through the PRU-
ICSS CFG register space to be positive, then it will equal PRU<n>_CLOCK. If the clocking is configured to
be negative, then it will equal PRU<n>_CLOCK inverted.
Figure 4-9. PRU R31 (GPI) 16-Bit Parallel Capture Mode Block Diagram
PRU<n>_R31
16
PRU<n>_DATAIN 0
1
PRU<n>_CLOCKIN …
14
ocp_clk 15
Sync Flop 16
ocp_clk ocp_clk
Sync Flop Sync Flop
4.4.1.2.3.3 28-Bit Shift In

In 28-bit Shift In mode, the device-level general purpose input pin PRU<n>_DATAIN is sampled and
shifted into a 28-bit shift register on an internal clock pulse. The register fills in lsb order (from bit 0 to 27)
and then overflows into a bit bucket. The 28-bit register is mapped to pru<n>_r31_status [0:27] and can be
cleared in software through the PRU-ICSS CFG register space.
Note that the PRU will continually capture and shift the DATAIN input when the GPI mode has been set to
28-bit shift in.
The shift rate is controlled by the effective divisor of two cascaded dividers applied to the ocp_clk. These
cascaded dividers can each be configured through the PRU-ICSS CFG register space to a value of {1,
1.5, …, 16}. Table 4-14 lists sample effective clock values and the divisor values that can be used to
generate these clocks.
Table 4-14. Effective Clock Values

Generated clock PRU<n>_GPI_DIV0 PRU<n>_GPI_DIV1
8-MHz 12.5 (0x17) 2 (0x02)
10-MHz 10 (0x12) 2 (0x02)
16-MHz 16 (0x1e) 1 (0x00)
20-MHz 10 (0x12) 1 (0x00)
The 28-bit Shift In mode also supports these features:

• Start Bit detection (SB) is mapped to pru<n>_r31_status [29] and is set when the first 1 is captured on
PRU<n>_DATAIN. The SB flag in pru<n>_r31_status [29] is cleared in software through the
CFG_GPCFGn register of the PRU-ICSS CFG register space.
• CNT_16 (Shift Counter) is mapped to pru<n>_r31_status [28] and is set on every 16 shift clock sample
after the Start Bit has been received. CNT_16 is self clearing and is connected to the PRU-ICSS INTC.
For more details, see Section 4.4.2, Interrupt Controller (INTC).
Figure 4-10. PRU R31 (GPI) 28-Bit Shift In Mode
PRU<n>_R31
PRU<n>_DATAIN 0
27 …
27
28 (CNT_16)
28-bit shift register 29 (SB)
Bit Bucket
Bit 0 Bit 27
ocp_clk PRU<n> PRU<n>

GPO_DIV0 GPO_DIV1
4.4.1.2.4 General-Purpose Outputs (R30): Enhanced PRU GP Module

The PRU-ICSS implements an enhanced General Purpose Input Output (GPIO) module that supports two
general-purpose output modes: direct output and shift out..
Table 4-15 describes these modes in detail. Note that each PRU core can only be configured for one GPO
mode at a time. Each mode uses the same R30 signals and internal register bits for different purposes. A
summary is found in Table 4-16.
Table 4-15. PRU R30 (GPO) Modes

Mode Function Configuration
Direct Output pru<n>_r30[0:31] feeds directly to GPO[0:31] Default mode
• pru<n>_r30[0] is shifted out on DATAOUT on every rising
edge of pru<n>_r30[1] (CLOCKOUT).
• LOAD_GPO_SH0 (Load Shadow Register 0) is mapped to
Enabled by CFG_GPCFGn
Shift Out pru<n>_r30[29]
register
• LOAD_GPO_SH1 (Load Shadow Register 1) is mapped to
pru<n>_r30[30]
• ENABLE_SHIFT is mapped to pru<n>_r30[31]
Table 4-16. PRU GPO Signals and Configurations

GPO Modes
Direct Output Shift Out
pr1_pru<n>_pru_r30_0 GPO0 DATAOUT
pr1_pru<n>_pru_r30_1 GPO1 CLOCKOUT
pr1_pru<n>_pru_r30_2 GPO2
NOTE: Some devices may not pin out all 32 bits of R30. For which pins are available on this device,
see Section 4.2.3, PRU-ICSS Pin List. See the device's datasheet for device-specific pin
mapping.
4.4.1.2.4.1 Direct Output

The pru<n>_r30 [0:31] bits of the internal PRU register file are mapped to device-level general purpose
output pins (PRU<n>_GPO [0:31]). In GPO Direct Output mode, pru<n>_r30 [0:31] feed directly to
PRU<n>_GPO [0:31]. There are 32 possible general purpose outputs per PRU core; however, some
devices may not pin out all of these signals. See the device-specific datasheet for device specific pin
mapping.
NOTE: R30 is not initialized after reset. To avoid unintended output signals, R30 should be
initialized before pinmux configuration of PRU signals.
Figure 4-11. PRU R30 (GPO) Direct Output Mode Block Diagram
PRU<n>_R30
0
PRU<n>_GPO[0:31]
1
… 32
31
4.4.1.2.4.2 Shift Out

In shift out mode, data is shifted out of pru<n>_r30[0] (on PRU<n>_DATAOUT) on every rising edge of
pru<n>_r30[1] (PRU<n>_CLOCKOUT). The shift rate is controlled by the effective divisor of two cascaded
dividers applied to the op_clk. These cascaded dividers can each be configured through the PRU-ICSS
CFG register space to a value of {1, 1.5, …, 16}. Table 4-17 shows sample effective clock values and the
divisor values that can be used to generate these clocks. The shift out clock is a free-running clock that is
always running internally. This clock will be output to PRU<n>_CLOCKOUT (or pr1_pru<n>_pru_r30_1)
when the PRU GPO mode is set to shift out mode.
Table 4-17. Effective Clock Values

Generated Clock PRU<n>_GPO_DIV0 PRU<n>_GPO_DIV1
8 MHz 12.5 (0x17) 2 (0x02)
10 MHz 10 (0x12) 2 (0x02)
16 MHz 16 (0x1e) 1 (0x00)
20 MHz 10 (0x12) 1 (0x00)
Shift out mode uses two 16-bit shadow registers (gpo_sh0 and gpo_sh1) to support ping-pong buffers.
Each shadow register has independent load controls programmable through pru<n>_r30[29:30]
(PRU<n>_LOAD_GPO_SH [0:1]). While PRU<n>_LOAD_GPO_SH [0/1] is set, the contents of
pru<n>_r31[0:15] are loaded into gpo_sh0/1.
NOTE: If any device-level pins mapped to pru<n>_r30 [2:15] are configured for the pru<n>_r30
[2:15] pinmux mode, then these pins will reflect the shadow register value written to
pru<n>_r30. Any pin configured for a different pinmux setting will not reflect the shadow
register value written to pru<n>_r30.
The data shift will start from the lsb of gpo_sh0 when pru<n>_r30[31] (PRU<n>_ENABLE_SHIFT) is set.
Note that if no new data is loaded into gpo_shn<n> after shift operation, the shift operation will continue
looping and shifting out the pre-loaded data. When PRU<n>_ENABLE_SHIFT is cleared, the shift
operation will finish shifting out the current shadow register, stop, and reset.
Figure 4-12. PRU R30 (GPO) Shift Out Mode Block Diagram
GP_SH0
16 16
PRU<n>_R30
0
1
… 16
PRU<n>_DATAOUT
15
… GP_SH1
29 (gp_sh0_load)
30 (gp_sh1_load)
31 (enable_shift)
16 16
ocp_clk PRU<n> PRU<n>

GPO_DIV0 GPO_DIV1 PRU<n>_CLOCKOUT
Follow these steps to use the GPO shift out mode:

Step One: Initialization
1. Load 16-bits of data into gpo_sh0:
a. Set R30[29] = 1 (PRU<n>_LOAD_GPO_SH0)
b. Load data in R30[15:0]
c. Clear R30[29] to turn off load controller
2. Load 16-bits of data into gpo_sh1:
a. Set R30[30] = 1 (PRU<n>_LOAD_GPO_SH1)
b. Load data in R30[15:0]
c. Clear R30[30] to turn off load controller
3. Start shift operation:
a. Set R30[31] = 1 (PRU<n>_ENABLE_SHIFT)
Step Two: Shift Loop
1. Monitor when a shadow register has finished shifting out data and can be loaded with new data:
1. Poll PRU<n>_GPI_SH_SEL bit of the GPCFG<n> register
2. Load new 16-bits of data into gpo_sh0 if PRU<n>_GPI_SH_SEL = 1
3. Load new 16-bits of data into gpo_sh1 if PRU<n>_GPI_SH_SEL = 0
2. If more data to be shifted out, loop to Shift Loop
3. If no more data, exit loop
Exit:
1. End shift operation:
1. Clear R30[31] to turn off shift operation
NOTE: Until the shift operation is disabled, the shift loop will continue looping and shifting out the
pre-loaded data if no new data has been loaded into gpo_sh<n>.
4.4.1.3 Multiplier With Optional Accumulation (MPY/MAC)

Each PRU core has a designated unsigned multiplier with optional accumulation (MPY/MAC). The MAC
has two modes of operation: Multiply Only or Multiply and Accumulate. The MAC is directly connected with
the PRU internal registers R25–R29 and uses the broadside load/store PRU interface and XFR
instructions to both control the mode of the MAC and import the multiplication results into the PRU.
4.4.1.3.1 Features
• Configurable Multiply Only and Multiply and Accumulate functionality via PRU register R25
• 32-bit operands with direct connection to PRU registers R28 and R29
• 64-bit result (with carry flag) with direct connection to PRU registers R26 and R27
• PRU broadside interface and XFR instructions (XIN, XOUT) allow for importing multiplication results
and initiating accumulate function
4.4.1.3.2 PRU and MPY/MAC Interface

The MAC directly connects with the PRU internal registers R25–R29 through use of the PRU broadside
interface and XFR instructions. Figure 4-13 shows the functionality of each register.
Figure 4-13. Integration of the PRU and MPY/MAC

Function Function
PRU
Bit Bit
[0] loads current state of MAC_mode XIN R25 XOUT [0] Loads MAC_mode, if set to “1”, the
[1] loads the current state of MAC will perform one multiply and
MAC mode /status accumulate function.
ACC_carry
[1] write “1” clears ACC_carry
XIN R26
Lower 32 bit product R26
Lower product
XIN R27
Upper 32 bit product R27
Upper product
R28 Auto-sampled
R28 32-bit operands:
Operand Sampled every clock.
In MAC mode, the product
R29 Auto-sampled of R28*R29 will be added
R29 to the accumulator on
Operand
every XOUT of R25.
MPY/MAC
XFR device ID for

MPY/MAC = 0
The XFR instructions (XIN and XOUT) are used to load/store register contents between the PRU core and
the MAC. These instructions define the start, size, direction of the operation, and device ID. The device ID
number corresponding to the MPY/MAC is shown in Table 4-18.
Table 4-18. MPY/MAC XFR ID

Device ID Function
0 Selects MPY/MAC
The PRU register R25 is mapped to the MAC_CTRL_STATUS register (Table 4-19). The MAC’s current
status (MAC_mode and ACC_carry states) is loaded into R25 using the XIN command on R25. The PRU
sets the MAC’s mode and clears the ACC_carry using the XOUT command on R25.
Table 4-19. MAC_CTRL_STATUS Register (R25) Field Descriptions

7-2 Reserved Reserved
1 ACC_carry Write 1 to clear
0 64-bit accumulator carry has not occurred
1 64-bit accumulator carry occurred
0 MAC_mode
0 Accumulation mode disabled and accumulator is cleared
1 Accumulation mode enabled
The two 32-bit operands for the multiplication are loaded into R28 and R29. These registers have a
direction connection with the MAC, and the MAC samples these registers every clock cycle. Note, XOUT
is not required to load the MAC. In multiply and accumulate mode, the product of R28*R29 is added to the
accumulator on every XOUT of R25.
The product from the MAC is linked to R26 (lower 32 bits) and R27 (upper 32 bits). The product is loaded
into register R26 and R27 using XIN.
4.4.1.3.2.1 Multiply-Only Mode (Default State), MAC_mode = 0

On every clock cycle, the MAC multiplies the contents of R28 and R29.
Figure 4-14. Multiply-Only Mode Functional Diagram

R28 R29 R27 R26
X =
32-bit operand 32-bit operand Upper 32-bit product Lower 32-bit product
Multiply mode :
sampled every clock cycle XIN
MAC
The following steps are performed by the PRU firmware for multiply-only mode:
1. Enable multiply only MAC_mode.
a. Clear R25[0] for multiply only mode.
b. Store MAC_mode to MAC using XOUT instruction with the following parameters:
• Device ID = 0
• Base register = R25
• Size = 1
2. Load operands into R28 and R29.
3. Delay at least 1 PRU cycle before executing XIN in step 4.
4. Load product into PRU using XIN instruction on R26, R27.
Repeat steps 2 through 4 for each new operand.
4.4.1.3.2.2 Multiply and Accumulate Mode, MAC_mode = 1

On every XOUT R25_reg[7:0] transaction, the MAC multiplies the contents of R28 and R29, adds the
product to its accumulated result, and sets ACC_carry if an accumulation overflow occurs.
Figure 4-15. Multiply and Accumulate Mode Functional Diagram

R28 R29 R27 R26
X =
32-bit operand 32-bit operand Upper 32-bit product Lower 32-bit product
Multiply and Accumulate mode

:
sampled every XOUT of R25
XIN
MAC
The following steps are performed by the PRU firmware for multiply and accumulate mode:
1. Enable multiply and accumulate MAC_mode.
a. Set R25[1:0] = 1 for accumulate mode.
b. Store MAC_mode to MAC using XOUT instruction with the following parameters:
• Device ID = 0
• Base register = R25
• Size = 1
2. Clear accumulator and carry flag.
a. Set R25[1:0] = 3 to clear accumulator (R25[1]=1) and preserve accumulate mode (R25[0]=1).
b. Store accumulator to MAC using XOUT instruction on R25.
3. Load operands into R28 and R29.
4. Multiply and accumulate, XOUT R25[1:0] = 1
Repeat step 4 for each multiply and accumulate using same operands.
Repeat step 3 and 4 for each multiply and accumulate for new operands.
5. Load the accumulated product into R26, R27 and the ACC_carry status into R25 using the XIN
instruction.
Note: Steps one and two are required to set the accumulator mode and clear the accumulator and carry
flag.
4.4.1.4 PRU0/1 Scratch Pad

The PRU-ICSS supports a scratch pad with three independent banks accessible by the PRU cores. The
PRU cores interact with the scratch pad through broadside load/store PRU interface and XFR instructions.
The scratch pad can be used as a temporary place holder for the register contents of the PRU cores.
Direct connection between the PRU cores is also supported for transferring register contents directly
between the cores.
4.4.1.4.1 Features
The PRU-ICSS scratch pad supports the following features:
• Three scratch pad banks of 30, 32-bit registers (R29:0)
• Flexible load/store options
– User-defined start byte and length of the transfer
– Length of transfer ranges from one byte of a register to the entire register content (R29 to R0)
– Simultaneous transactions supported between PRU0 ↔ Bank<n> and PRU1 ↔ Bank<m>
– Direct connection of PRU0 → PRU1 or PRU1 → PRU0 for all registers R29–R0
• XFR instructions operate in one clock cycle
• Optional XIN/XOUT shift functionality allows remapping of registers (R<n> → R<m>) during load/store
operation
Figure 4-16. Integration of PRU and Scratch Pad
Bank0
R0
R1
R2
…
R28
R29
broadside interface
broadside interface
PRU0 Bank1 PRU1
R0 R0 R0
R1 R1 R1
R2 R2 R2
… … …
R28 R28 R28
R29 R29 R29
Bank2
R0
R1
R2
…
R28
R29
4.4.1.4.2 Implementations and Operations

XFR instructions are used to load/store register contents between the PRU cores and the scratch pad
banks. These instructions define the start, size, direction of the operation, and device ID. The device ID
corresponds to the external source or destination (either a scratch pad bank or the other PRU core). The
device ID numbers are shown in Table 4-20. Note the direct connect mode (device ID 14) can be used to
synchronize the PRU cores. This mode requires the transmitting PRU core to execute XOUT and the
receiving PRU core to execute XIN.
Table 4-20. Scratch Pad XFR ID

Device ID Function
10 Selects Bank0
11 Selects Bank1
12 Selects Bank2
13 Reserved
14 Selects other PRU core (Direct connect mode)
A collision occurs when two XOUT commands simultaneously access the same asset or device ID.
Table 4-21 shows the priority assigned to each operation when a collision occurs. In direct connect mode
(device ID 14), any PRU transaction will be terminated if the stall is greater than 1024 cycles. This will
generate the event pr1_xfr_timeout that is connected to INTC.
Table 4-21. Scratch Pad XFR Collision & Stall Conditions

Operation Collision Handling
PRU<n> XOUT (→) bank[j] If both PRU cores access the same bank simultaneously, PRU0
is given priority. PRU1 will temporarily stall until the PRU0
operation completes.
PRU<n> XOUT (→) PRU<m> Direct Connect mode requires the transmitting core (PRU<n>) to
execute XOUT and the receiving core (PRU<m>) to execute
XIN. If PRU<n> executes XOUT before PRU<m> executes XIN,
then PRU<n> will stall until either PRU<m> executes XIN or the
stall is greater than 1024 cycles.
Table 4-21. Scratch Pad XFR Collision & Stall Conditions (continued)
PRU<m> XIN (←) PRU<n> Direct Connect mode requires the transmitting core (PRU<n>) to
execute XOUT and the receiving core (PRU<m>) to execute
XIN. If PRU<m> executes XIN before PRU<n> executes XOUT,
then PRU<m> will stall until either PRU<n> executes XOUT or
the stall is greater than 1024 cycles.
4.4.1.4.2.1 Optional XIN/XOUT Shift

The optional XIN/XOUT shift functionality allows register contents to be remapped or shifted within the
destination’s register space. For example, the contents of PRU0 R6-R8 could be remapped to Bank1 R10-
12. The XIN/XOUT shift feature is not supported for direct connect mode, only for transfers between a
PRU core and scratch pad bank.
The shift feature is enabled or disabled through the SPP register of the PRU-ICSS CFG register space.
When enabled, R0[4:0] (internal to the PRU) defines the number of 32-bit registers in which content is
shifted in the scratch pad bank. Note that scratch pad banks do not have registers R30 or R31.
4.4.1.4.2.2 Example Scratch Pad Operations

The following PRU firmware examples demonstrate the shift functionality. Note these assume the
SHIFT_EN bit of the SPP register of the PRU-ICSS CFG register space has been set.
XOUT Shift By 4 Registers
Store R4:R7 to R8:R11 in bank0:
• Load 4 into R0.b0
• XOUT using the following parameters:
– Device ID = 10
– Base register = R4
– Size = 16
XOUT Shift By 9 Registers, With Wrap Around
Store R25:R29 to R4:R8 in bank1:
• XOUT using the following parameters:
– Device ID = 11
– Size = 20
XIN Shift By 10 Registers
Store R14:R16 from bank2 to R4:R6:
• XIN using the following parameters:
– Device ID = 12
– Size = 12
4.4.2 Interrupt Controller (INTC)

The PRU-ICSS interrupt controller (INTC) is an interface between interrupts coming from different parts of
the system (referred to as system events; see Section 4.4.2.2) and the PRU-ICSS interrupt interface.
The PRU-ICSS INTC has the following features:
• Capturing up to 64 System Events
• Supports up to 10 interrupt channels.
• Generation of 10 Host Interrupts
– 2 Host Interrupts for the PRUs.
– 8 Host Interrupts exported from the PRU-ICSS for signaling the ARM interrupt controllers.
• Each system event can be enabled and disabled.
• Each host event can be enabled and disabled.
• Hardware prioritization of events.
4.4.2.1 INTC Overview

The PRU-ICSS INTC supports up to 64 system events from different peripherals and PRUs to be mapped
to 10 channels inside the INTC (see Figure 4-17). Interrupts from these 10 channels are further mapped to
10 Host Interrupts.
• Any of the 64 system events can be mapped to any of the 10 channels.
• Multiple interrupts can be mapped to a single channel.
• An interrupt should not be mapped to more than one channel.
• Any of the 10 channels can be mapped to any of the 10 host interrupts. It is recommended to map
channel “x” to host interrupt “x”, where x is from 0 to 9
• A channel should not be mapped to more than one host interrupt
• For channels mapping to the same host interrupt, lower number channels have higher priority.
• For interrupts on same channel, priority is determined by the hardware interrupt number. The lower the
interrupt number, the higher the priority.
• Host Interrupt 0 is connected to bit 30 in register 31 of PRU0 and PRU1.
• Host Interrupt 1 is connected to bit 31 in register 31 for PRU0 and PRU1.
• Host Interrupts 2 through 9 exported from PRU-ICSS for signaling ARM interrupt controllers or other
machines like EDMA.
Figure 4-17. Interrupt Controller Block Diagram

Host Mapping of channels Channel Mapping of System events
PRU0/1 Sys_event 1
R31 bit 30 Host-0 Channel-0
PRU0/1 Sys_event 2 Peripheral A
Host-1 Channel-1
R31 bit 31
Host-2 Channel-2
Host-3 Channel-3
Host-4 Channel-4
Host-5 Channel-5 Sys_event 30
Host-6 Sys_event 31
Channel-6
Host-7 Channel-7 Sys_event 34
Host-8 Channel-8
Peripheral Z
Host-9 Channel-9
Sys_event 58
4.4.2.2 PRU-ICSS System Events

The PRU-ICSS system events can be found in Table 4-22.
Table 4-22. PRU-ICSS System Events

Int Number Signal Name Source Signal Name (MII_RT Mode) (1) (2)
(Standard Mode)
63 tpcc_int_pend_po1 TPCC (EDMA)
62 tpcc_errint_pend_po TPCC (EDMA)
61 tptc_erint_pend_po TPTC0 (EDMA)
60 initiator_sinterrupt_q_n1 Mbox0 - mail_u1_irq
(mailbox interrupt for pru0)
59 initiator_sinterrupt_q_n2 Mbox0 - mail_u2_irq
(mailbox interrupt for pru1)
58 Emulation Suspend Signal Debugss
(software use)
57 POINTRPEND1 GPIO0
56 pwm_trip_zone eHRPWM0/eHRPWM1/eHR
PWM2
55 mcasp_x_intr_pend McASP0 Tx (pr1_mii1_col & pr1_mii1_txen)
(external)
54 mcasp_r_intr_pend McASP0 Rx PRU-ICSS0 PRU1_RX_EOF
53 gen_intr_pend ADC_TSC PRU-ICSS0 MDIO_MII_LINK[1]
52 nirq UART2 PRU-ICSS0 PORT1_TX_OVERFLOW
51 nirq UART0 PRU-ICSS0
PORT1_TX_UNDERFLOW
50 c0_rx_thresh_pend 3PGSW (GEMAC) PRU-ICSS0 PRU1_RX_OVERFLOW
49 c0_rx_pend 3PGSW (GEMAC) PRU-ICSS0 PRU1_RX_NIBBLE_ODD
48 c0_tx_pend 3PGSW (GEMAC) PRU-ICSS0 PRU1_RX_CRC
47 c0_misc_pend 3PGSW (GEMAC) PRU-ICSS0 PRU1_RX_SOF
46 epwm_intr_intr_pend eHRPWM1 PRU-ICSS0 PRU1_RX_SFD
45 eqep_intr_intr_pend eQEP0 PRU-ICSS0 PRU1_RX_ERR32
44 SINTERRUPTN McSPI0 PRU-ICSS0 PRU1_RX_ERR
43 epwm_intr_intr_pend eHRPWM0 (pr1_mii0_col & pr1_mii0_txen)
(external)
42 ecap_intr_intr_pend eCAP0 PRU-ICSS0 PRU0_RX_EOF
41 POINTRPEND I2C0 PRU-ICSS0 MDIO_MII_LINK[0]
40 dcan_intr DCAN0 PRU-ICSS0 PORT0_TX_OVERFLOW
39 dcan_int1 DCAN0 PRU-ICSS0
PORT0_TX_UNDERFLOW
38 dcan_uerr DCAN0 PRU-ICSS0 PRU0_RX_OVERFLOW
37 epwm_intr_intr_pend eHRPWM2 PRU-ICSS0 PRU0_RX_NIBBLE_ODD
36 ecap_intr_intr_pend eCAP2 PRU-ICSS0 PRU0_RX_CRC
35 ecap_intr_intr_pend eCAP1 PRU-ICSS0 PRU0_RX_SOF
34 mcasp_r_intr_pend McASP1 Rx PRU-ICSS0 PRU0_RX_SFD
33 mcasp_x_intr_pend McASP1 Tx PRU-ICSS0 PRU0_RX_ERR32
32 nirq UART1 PRU-ICSS0 PRU0_RX_ERR
(1)
MII_RT mode is selected through the MII_RT register in the PRU-ICSS0 CFG register space.
(2)
Signals 63-56 and 31-0 for MII_RT Mode are the same as for Standard Mode.
Table 4-22. PRU-ICSS System Events (continued)

Int Number Signal Name Source Signal Name (MII_RT Mode) (1) (2)
(Standard Mode)
31 pr1_pru_mst_intr[15]_intr_re pru0 or pru1 PRU-ICSS0 Internal Interrupts
q
30 pr1_pru_mst_intr[14]_intr_re pru0 or pru1
q
q
q
q
q
25 pr1_pru_mst_intr[9]_intr_req pru0 or pru1
15 pr1_ecap_intr_req PRU-ICSS eCAP
14 sync0_out_pend PRU-ICSS IEP
13 sync1_out_pend PRU-ICSS IEP
12 latch0_in (input to PRU- PRU-ICSS IEP
ICSS)
11 latch1_in (input to PRU- PRU-ICSS IEP
ICSS)
10 pdi_wd_exp_pend PRU-ICSS IEP
9 pd_wd_exp_pend PRU-ICSS IEP
8 pr1_digio_event_req PRU-ICSS IEP
7 pr1_iep_tim_cap_cmp_pend PRU-ICSS IEP
6 pr1_uart_uint_intr_req PRU-ICSS UART
5 pr1_uart_utxevt_intr_req PRU-ICSS UART
4 pr1_uart_urxevt_intr_req PRU-ICSS UART
3 pr1_xfr_timeout PRU-ICSS Scratch Pad
2 pr1_pru1_r31_status_cnt16 PRU-ICSS PRU1 (Shift
Capture)
1 pr1_pru0_r31_status_cnt16 PRU-ICSS PRU0 (Shift
Capture)
0 pr1_parity_err_intr_pend PRU-ICSS Parity Logic
4.4.2.3 INTC Methodology

The INTC module controls the system event mapping to the host interrupt interface. System events are
generated by the device peripherals or PRUs. The INTC receives the system events and maps them to
internal channels. The channels are used to group interrupts together and to prioritize them. These
channels are then mapped onto the host interrupts. Interrupts from the system side are active high in
polarity. They are also pulse type of interrupts.
The INTC encompasses many functions to process the system events and prepare them for the host
interface. These functions are: processing, enabling, status, channel mapping, host interrupt mapping,
prioritization, and host interfacing. Figure 4-18 illustrates the flow of system events through the functions
to the host. The following subsections describe each part of the flow.
Figure 4-18. Flow of System Events to Host
System
Status Enabling Processing
Interrupts
Prioritization
Debug Debug Ints

Channel
Vectorization Int
Mapping
Host Int Host

Mapping Interfacing Host Ints
4.4.2.3.1 Interrupt Processing

This block does the following tasks:
• Synchronization of slower and asynchronous interrupts
• Conversion of polarity to active high
• Conversion of interrupt type to pulse interrupts
After the processing block, all interrupts will be active high pulses.
4.4.2.3.2 Interrupt Enabling

The next stage of INTC is to enable system events based on programmed settings. The following
sequence is to be followed to enable interrupts:
• Enable required system events: System events that are required to get propagated to host are to be
enabled individually by writing to IDX field in the system event enable indexed set register (EISR). The
event to enable is the index value written. This sets the Enable Register bit of the given index.
• Enable required host interrupts: By writing to the IDX field in the host interrupt enable indexed set
register (HIEISR), enable the required host interrupts. The host interrupt to enable is the index value
written. This enables the host interrupt output or triggers the output again if that host interrupt is
already enabled.
• Enable all host interrupts: By setting the EN bit in the global enable register (GER) to 1, all host
interrupts will be enabled. Individual host interrupts are still enabled or disabled from their individual
enables and are not overridden by the global enable.
4.4.2.3.3 Interrupt Status Checking

The next stage is to capture which system events are pending. There are two kinds of pending status: raw
status and enabled status. Raw status is the pending status of the system event without regards to the
enable bit for the system event. Enabled status is the pending status of the system events with the enable
bits active. When the enable bit is inactive, the enabled status will always be inactive. The enabled status
of system events is captured in system event status enabled/clear registers (SECR1-SECR2).
Status of system event 'N' is indicated by the Nth bit of SECR1-SECR2. Since there are 64 system
events, two 32-bit registers are used to capture the enabled status of events. The pending status reflects
whether the system event occurred since the last time the status register bit was cleared. Each bit in the
status register can be individually cleared.
4.4.2.3.4 Interrupt Channel Mapping

The INTC has 10 internal channels to which enabled system events can be mapped. Channel 0 has
highest priority and channel 9 has the lowest priority. Channels are used to group the system events into a
smaller number of priorities that can be given to a host interface with a very small number of interrupt
inputs.
When multiple system events are mapped to the same channel their interrupts are ORed together so that
when one or more is active the output is active. The channel map registers (CMRm) define the channel for
each system event. There is one register per 4 system events; therefore, there are16 channel map
registers for a system of 64 events. The channel for each system event can be set using these registers.
4.4.2.3.4.1 Host Interrupt Mapping

The hosts can be the PRUs or ARM CPU. The 10 channels from the INTC can mapped to any of the 10
Host events. The Host map registers (HMRm) define the channel for each system event. There is one
register per 4 channels; therefore, there are 3 host map registers for 10 channels. When multiple channels
are mapped to the same host interrupt, then prioritization is done to select which interrupt is in the highest-
priority channel and which should be sent first to the host.
4.4.2.3.4.2 Interrupt Prioritization

The next stage of the INTC is prioritization. Since multiple events can feed into a single channel and
multiple channels can feed into a single host interrupt, it is to read the status of all system events to
determine the highest priority event that is pending. The INTC provides hardware to perform this
prioritization with a given scheme so that software does not have to do this. There are two levels of
prioritizations:
• The first level of prioritization is between the active channels for a host interrupt. Channel 0 has the
highest priority and channel 9 has the lowest. So the first level of prioritization picks the lowest
numbered active channel.
• The second level of prioritization is between the active system events for the prioritized channel. The
system event in position 0 has the highest priority and system event 63 has the lowest priority. So the
second level of prioritization picks the lowest position active system event.
This is the final prioritized system event for the host interrupt and is stored in the global prioritized index
register (GPIR). The highest priority pending event with respect to each host interrupt can be obtained
using the host interrupt prioritized index registers (HIPIRn).
4.4.2.3.5 Interrupt Nesting

The INTC can also perform a nesting function in its prioritization. Nesting is a method of enabling certain
interrupts (usually higher-priority interrupts) when an interrupt is taken so that only those desired interrupts
can trigger to the host while it is servicing the current interrupt. The typical usage is to nest on the current
interrupt and disable all interrupts of the same or lower priority (or channel). Then the host will only be
interrupted from a higher priority interrupt.
The nesting is done in one of three methods:
1. Nesting for all host interrupts, based on channel priority: When an interrupt is taken, the nesting level is
set to its channel priority. From then, that channel priority and all lower priority channels will be
disabled from generating host interrupts and only higher priority channels are allowed. When the
interrupt is completely serviced, the nesting level is returned to its original value. When there is no
interrupt being serviced, there are no channels disabled due to nesting. The global nesting level
register (GNLR) allows the checking and setting of the global nesting level across all host interrupts.
The nesting level is the channel (and all of lower priority channels) that are nested out because of a
current interrupt.
2. Nesting for individual host interrupts, based on channel priority: Always nest based on channel priority
for each host interrupt individually. When an interrupt is taken on a host interrupt, then, the nesting
level is set to its channel priority for just that host interrupt, and other host interrupts do not have their
nesting affected. Then for that host interrupt, equal or lower priority channels will not interrupt the host
but may on other host interrupts if programmed. When the interrupt is completely serviced the nesting
level for the host interrupt is returned to its original value. The host interrupt nesting level registers
(HINLR1 and HINLR2) display and control the nesting level for each host interrupt. The nesting level
controls which channel and lower priority channels are nested. There is one register per host interrupt.
3. Software manually performs the nesting of interrupts. When an interrupt is taken, the software will
disable all the host interrupts, manually update the enables for any or all the system events, and then
re-enables all the host interrupts. This now allows only the system events that are still enabled to
trigger to the host. When the interrupt is completely serviced the software must reverse the changes to
re-enable the nested out system events. This method requires the most software interaction but gives
the most flexibility if simple channel based nesting mechanisms are not adequate.
4.4.2.3.6 Interrupt Status Clearing

After servicing the event (after execution of the ISR), event status is to be cleared. If a system event
status is not cleared, then another host interrupt may not be triggered or another host interrupt may be
triggered incorrectly. It is also essential to clear all system events before the PRU is halted as the PRU
does not power down unless all the event status are cleared. For clearing the status of an event, whose
event number is N, write a 1 to the Nth bit position in the system event status enabled/clear registers
(SECR1-SECR2). System event N can also be cleared by writing the value N into the system event status
indexed clear register (SICR).
4.4.2.4 Interrupt Disabling

At any time, if any event is not to be propagated to the host, then that event should be disabled. For
disabling an event whose event number is N, write a 1 to the Nth bit in the system event enable clear
registers (ECR1-ECR2). System event N can also be disabled by writing the value N in the system event
enable indexed clear register (EICR).
4.4.2.5 INTC Basic Programming Model

Follow these steps to configure the interrupt controller.
1. Set polarity and type of system event through the System Event Polarity Registers (SIPR1 and SPIR2)
and the System Event Type Registers (SITR1 and SITR2). Polarity of all system events is always high.
Type of all system events is always pulse.
2. Map system event to INTC channel through Channel Map registers.
3. Map channel to host interrupt through Host Interrupt Map registers. Recommend channel “x” be
mapped to host interrupt “x”.
4. Clear system event by writing 1s to SECR registers.
5. Enable host interrupt by writing index value to HIER register.
6. Enable interrupt nesting if desired.
7. Globally enable all interrupts through GER register.
4.4.3 Industrial Ethernet Peripheral (IEP)

The industrial ethernet peripheral (IEP) performs hardware work required for industrial ethernet functions.
The IEP module features an industrial ethernet timer with 8 compare events, industrial ethernet sync
generator and latch capture, industrial ethernet watchdog timer, and a digital I/O port (DIGIO). The IEP
functional block diagram is shown in Figure 4-19.
Figure 4-19. Industrial Ethernet Peripheral Block Diagram
4.4.3.1 IEP Clock Source

The IEP has a selectable module input clock. The clock source is selected by the state of the
IEPCLK.OCP_EN bit within the PRU-ICSS CFG register space. Two clock sources are supported for the
IEP input clock:
• iep_clk (default): Runs at 200 MHz
• ocp_clk
Switching from iep_clk to ocp_clk is done by writing 1 to the IEPCLK.OCP_EN bit. This is a one time
configuration step before enabling the IEP function. Switching back from ocp_clk to iep_clk is only
supported through a hardware reset of the PRU-ICSS.
4.4.3.2 Industrial Ethernet Timer

The industrial ethernet timer is a simple 32-bit timer. This timer is intended for use by industrial ethernet
functions but can also be leveraged as a generic timer in other applications.
4.4.3.2.1 Features
The industrial ethernet timer supports the following features:
• One master 32-bit count-up counter with an overflow status bit
– Runs on iep_clk or ocp_clk
– Write 1 to clear status
– Supports a programmable increment value from 1 to 16 (default 5)
– An optional compensation method allows the increment value to apply a compensation increment
value from 1 to 16, counting up to 2^24 iep_clk/ocp_clk events
• Ten 32-bit capture registers (CAPR[5:0], CAPR[7:6], CAPF[7:6])
– Eight capture inputs with optional synchronous or asynchronous mode
• Six rise-only capture inputs (CAPR[5:0])
• Two rise-and-fall capture inputs:
• CAPR[7] and CAPF[7]
• CAPR[6] and CAPF[6]

• One input signal will be used by two capture registers:
• One register for rising edge
• One register for falling edge
• One global event (any capture event) output for interrupt generation, triggered by any capture
event
• Eight 32-bit compare registers (CMP[7:0], CMP_STAT)
– Eight status bits, write 1 to clear
– Eight individual event outputs
– One global event (any compare event) output for interrupt generation triggered by any compare
event
• Sixteen outputs, one high level and one high pulse for each compare hit event
• CMP[0], if enabled, will reset the counter on the next iep_clk or ocp_clk cycle
4.4.3.2.2 Basic Programming Model

Follow these basic steps to configure the IEP Timer.
1. Initialize timer to known state (default values)
a. Disable counter (GLB_CFG.CNT_ENABLE)
b. Reset Count Register (CNT) by writing 0xFFFFFFFF to clear
c. Clear overflow status register (GLB_STS.CNT_OVF)
d. Clear compare status (CMP_STS)
2. Set compare values (CMP0-CMPx)
3. Enable compare event (CMP_CFG.CMP_EN)
4. Set increment value (GLB_CFG.DEFAULT_INC)
5. Set compensation value (COMPEN.COMPEN_CNT)
6. Enable counter (GLB_CFG.CNT_ENABLE)
4.4.3.3 Industrial Ethernet Mapping

Some of the capture inputs and compare registers are mapped to specific industrial ethernet functions in
hardware, shown in Table 4-23. All capture inputs are mapped to industrial ethernet functions, and these
inputs are not available for any other application. The cmp1 and cmp2 compare registers also function as
the start time triggers for SYNC0 and SYNC1, respectively.
Table 4-23. Industrial Ethernet Timer Mode Mapping

Capture Input IEP Line/Function
cap0, rise only PRU0_RX_SOF
cap1, rise only PRU0_RX_SFD
cap2, rise only PRU1_RX_SOF
cap3, rise only PRU1_RX_SFD
cap4, rise only PORT0_TX_SOF
cap5, rise only PORT1_TX_SOF
cap6, rise and fall latch0_in, SOC IO inputs
cap7, rise and fall latch1_in, SOC IO inputs
cmp1 For SYNC0 trigger of start time
For SYNC1 trigger of start time; only valid in the independent
cmp2
mode
For MII TX0 start trigger, if MII register
cmp3
TXCFG0/1[TX_EN_MODE] is enabled.
Table 4-23. Industrial Ethernet Timer Mode Mapping (continued)

Capture Input IEP Line/Function
For MII TX1 start trigger, if MII register
cmp4
TXCFG0/1[TX_EN_MODE] is enabled.
4.4.3.4 Industrial Ethernet SYNC0/SYNC1

The industrial ethernet sync block supports the generation of two synchronization signals: SYNC0 and
SYNC1. SYNC0 and SYNC1 can be directly mapped to output signals (pr1_edc_sycn0_out and
pr1_edc_sync1_out) for external devices to use. They can also be used for internal synchronization within
the PRU-ICSS. These signals are also mapped as system events and can therefore be mapped to the
ARM core's Host interrupts.
4.4.3.4.1 Features
The industrial ethernet sync block supports the following features:
• Two synchronize generation signals (SYNC0, SYNC1)
– Activation time synchronized with IEP Timer
• CMP[1] triggers SYNC0 activation time
• CMP[2] triggers SYNC1 activation time (only valid in the independent mode)
– Pulse width defined by registers or ack mode (remain asserted until software acknowledged)
– Cyclic or single-shot operation
– Option to enable or disable sync generation
• Programmable number of clock cycles between the start of SYNC0 to the start of SYNC1
4.4.3.4.2 Sync Generation Modes

There are four modes of operation for the sync signals: cyclic mode, single shot mode, cyclic with
acknowledge mode, and single shot with acknowledge mode. Figure 4-20 shows examples of these
modes. The start time is set by the SYNC_START register. The cycle time is configured by the
SYNC0_PERIOD register. The pulse length is defined by SYNC_PWIDTH register.
Figure 4-20. Sync Signal Generation Mode

Start time
Activation Cycle time Pulse length
Cyclic generation
SYNC0
Defined by SYNC_START
Single shot
SYNC0
Acknowledge
Cyclic generation
with acknowledgement
SYNC0
Acknowledge
Single shot
with acknowledgement
SYNC0
In SYNC1 dependent mode (SYNC_CTRL.sync1_ind_en = 0), SYNC1 depends on SYNC0 and the start
time of the SYNC1 can be defined by the SYNC1_DELAY register. Figure 4-21 shows different examples
when changing the value in the SYNC1_DELAY register. Note if the SYNC1 delay time is 0, SYNC1
reflects SYNC0.
Cyclic generation cannot be used for network time synchronized applications because only the
CMP1/CMP2 hit occurs in the compensated time domain.
Figure 4-21. Examples of the Dependent Mode of SYNC1
SYNC0 : Cyclic generation Start time

Activation
SYNC0_PERIOD SYNC_HPW
Field Value
SYNC0_CYCLIC_EN 1
SYNC0_ACK_EN 0
SYNC_START
SYNC0 : Single shot Start time

Activation
Field Value SYNC_HPW

SYNC0_CYCLIC_EN 0
SYNC0_ACK_EN 0
SYNC_START
Cyclic generation
SYNC0 : Start time
with Acknowledge Activation
Acknowledge
Field Value
SYNC0_CYCLIC_EN 1
SYNC0_ACK_EN 1
SYNC_START SYNC0_PERIOD
Single shot
SYNC0 : Start time
with Acknowledge Activation
Acknowledge
Field Value
SYNC0_CYCLIC_EN 0
SYNC0_ACK_EN 1
SYNC_START
4.4.3.5 Industrial Ethernet Watchdog Timer

In industrial ethernet applications, the watchdog timer (WD) is used as a safety feature to monitor process
data communication and to turn off the outputs of the digital input/output (DIGIO) functional block after a
set time. The WD will thereby protect the system from errors or faults by timeout or expiration. The
expiration is used to initiate corrective action in order to keep the system in a safe state and restore
normal operation based on configuration. Therefore, if the system is stable, the watchdog timer should be
regularly reset or cleared to avoid timeout or expiration.
4.4.3.5.1 Features
The industrial ethernet watchdog timer supports the following features:
• One 32-bit pre-divider for generating a WD clock (default 100μs) based on iep_clk input
• Two 16-bit Watchdog Timers:
– PDI_WD for Sync Managers WD, used in conjunction with digital input/output (DIGIO)
– PD_WD for data link layer user WD, used in conjunction with data link layer or application layer
interface actions
4.4.3.6 Industrial Ethernet Digital I/O (DIGIO)

The IEP Digital I/O (DIGIO) block provides dedicated I/Os intended for industrial ethernet protocols, but
they can also be used as generic I/Os in other applications. The digital inputs can be sampled when
specific events occur, or continuously as a raw input. Likewise, driving the digital outputs can be triggered
by specific events, or controlled by software. The timing, delay cycle clocks, data sources, and data valid
of the digital input and outputs are controlled by the DIGIO_CTRL and DIGIO_EXT registers.
4.4.3.6.1 Features
The industrial ethernet digital I/O supports the following features:
• Digital data output
– 32 channels (pr1_edio_data_out[31:0])
– Five event options for driving output data output:
• End of frame event (PRU0/1_RX_EOF)
• SYNC0 events
• SYNC1 events
• Watchdog trigger
• Software enable
• Digital data out enable (optional tri-state control)
• Digital data input
– 32 channels (pr1_edio_data_in[31:0])
– DIGIO_DATA_IN_RAW supports direct sampling of pr1_edio_data_in
– DIGIO_DATA_IN supports four event options to trigger sampling of pr1_edio_data_in:
• Start of frame event in start of frame (SOF) mode
• pr1_edio_latch_in event
• SYNC0 events
• SYNC1 events
NOTE: Some devices may not pin out all 32 data I/O signals. For which data pins are available on
this device, see Table 4-3, PRU-ICSS Pin List.
4.4.3.6.2 DIGIO Block Diagrams

Figure 4-22 shows the signals and registers for capturing the DIGIO data in. In PRU0/1_RX_SOF mode,
the delay time of capturing pr1_edio_data_in is programmable through the SOF_DLY bit of the
DIGIO_EXT register.
Figure 4-22. IEP DIGIO Data In
Industrial Ethernet Peripheral (IEP)

pr<k>_edio_data_in
DATA_IN_RAW
IN_MODE
RX_SOF
PRU<0/1> Delay function
SOF_DLY
pr<k>_edio_latch_in
D Q DATA_IN
SYNC0 EN
SYNC_PWIDTH
SYNC0_PERIOD SYNC1
SYNC1_DELAY
SYNC0/1
: (1) : (2) : (3)
(1) Register
(2) Internal signal wire
(3) External pin input/output
Figure 4-23 shows the signals and registers for driving the DIGIO data out. The pr1_edio_data_out is
immediately forced to zero when OUTVALID_MODE = 1, pr1_edio_oe_ext = 1, and PD_WD_EXP = 1, or
the next update hardware post PD_WD_EXP. Delay assertion of pr1_edio_outvalid from
pr1_edio_data_out update events are controlled by software (SW_OUTVALID).
Figure 4-23. IEP DIGIO Data Out
Industrial Ethernet Peripheral (IEP)
OUTVALID_OVR_EN
Delay function pr<k>_edio_outvalid
SW_OUTVALID
OUTVALID_DLY
OUT_MODE
RX_EOF
PRU<0/1> pr<k>_edio_data_out
SYNC0 DATA_OUT D Q
SYNC_PWIDTH
SYNC0_PERIOD EN
SYNC1
SYNC1_DELAY
SYNC0/1
SW_DATA_OUT_UPDATE
OUTVALID_MODE
WatchDog Timer
pr1_edio_oe_ext
32-bit WD_PREDIV
pd_wd_exp
16-bit PD_WD Timing
DATA_OUT_EN pr<k>_edio_data_out_en
16-bit PDI_WD WD_MODE Function
: (1) : (2) : (3)
(1) Register
(2) Internal signal wire
(3) External pin input/output
NOTE: pr1_edio_oe_ext is tied high internally.
4.4.3.6.3 Basic Programming Model

Follow these steps to configure and read the DIGIO Data Input.
1. Read DIGIO_DATA_IN_RAW for raw input data
or
1. Enable sampling of pr1_edio_data_in[31:0] by setting DIGIO_CTRL.IN_MODE
2. Read DIGIO_DATA_IN for data sampled by the selected trigger source
Follow these steps to configure and write to the DIGIO Data Output.
1. Pre-configure DIGIO by setting DIGIO_EXP.OUTVALID_OVR_EN and
DIGIO_EXP.SW_DATA_OUT_UPDATE
2. Write to DIGIO_DATA_OUT to configure output data
3. To Hi-Z output, set DIGIO_DATA_OUT_EN (clear DIGIO_DATA_OUT_EN to drive value stored in
DIGIO_DATA_OUT)
4.4.4 Universal Asynchronous Receiver/Transmitter (UART)
4.4.4.1 Introduction
4.4.4.1.1 Purpose of the Peripheral

The PRU UART peripheral within the PRU-ICSS is based on the industry standard TL16C550
asynchronous communications element, which in turn is a functional upgrade of the TL16C450.
Functionally similar to the TL16C450 on power up (single character or TL16C450 mode), the UART can
be placed in an alternate FIFO (TL16C550) mode. This relieves the CPU of excessive software overhead
by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes
including three additional bits of error status per byte for the receiver FIFO.
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-
to-serial conversion on data received from the CPU. The CPU can read the UART status at any time. The
UART includes control capability and a processor interrupt system that can be tailored to minimize
software management of the communications link.
The UART includes a programmable baud rate generator capable of dividing the PRU_ICSS_UART_CLK
input clock by divisors from 1 to 65535 and producing a 16× reference clock or a 13× reference clock for
the internal transmitter and receiver logic. For detailed timing and electrical specifications for the UART,
see your device-specific data manual.
4.4.4.1.2 Functional Block Diagram

A functional block diagram of the UART is shown in Figure 4-24.
4.4.4.1.3 Industry Standard(s) Compliance Statement

The UART peripheral is based on the industry standard TL16C550 asynchronous communications
element, which is a functional upgrade of the TL16C450. The information in this chapter assumes you are
familiar with these standards.
Figure 4-24. UART Block Diagram
S
e
l 8 Receiver 8
e FIFO
8
c
t
Peripheral 8 Receiver UARTn_RXD

Bus Data Receiver Shift
Bus Buffer Register signal
Buffer Register
16
Receiver
Line Timing and
Control Control
Register
Divisor
Latch (LS) 16 Baud
Divisor Generator
Latch (MS)
Line Transmitter
Status Timing and
Register Control
8 Transmitter 8 S
FIFO e
l
Transmitter 8 e 8 Transmitter UARTn_TXD
Holding c Shift
t Register signal
Register
Modem
8 Control
Control
Logic
Register
Interrupt 8 Interrupt/
Enable Event Interrupt to CPU
Register Control
Logic
Event to DMA controller
Interrupt 8
Identification
Register Power and
Emulation
Control
FIFO Register
Control
Register
NOTE: The value n indicates the applicable UART where there are multiple instances. For the PRU-ICSS, there is
only one instance and all UART signals should reflect this (e.g., UART0_TXD instead of UARTn_TXD).
4.4.4.2 Functional Description
4.4.4.2.1 Clock Generation and Control

The UART bit clock is derived from an input clock to the UART. See your device-specific data manual to
check the maximum data rate supported by the UART.
Figure 4-25 is a conceptual clock generation diagram for the UART. The PRU_ICSS_UART_CLK is input
to the Clock Generator, which uses a programmable divider to produce the UART input clock. The UART
contains a programmable baud generator that takes the UART input clock and divides it by a divisor in the
range between 1 and (216 - 1) to produce a baud clock (BCLK). The frequency of BCLK is sixteen times
(16×) the baud rate (each received or transmitted bit lasts 16 BCLK cycles) or thirteen times (13×) the
baud rate (each received or transmitted bit lasts 13 BCLK cycles). When the UART is receiving, the bit is
sampled in the 8th BCLK cycle for 16× over sampling mode and on the 6th BCLK cycle for 13× over-
sampling mode. The 16× or 13× reference clock is selected by configuring the OSM_SEL bit in the mode
definition register (MDR). The formula to calculate the divisor is:
UART input clock frequency

Divisor = ëéMDR.OSM _ SEL = 0ûù
Desired baud rate ´ 16
UART input clock frequency

Divisor = ëéMDR.OSM _ SEL = 1ûù
Desired baud rate ´ 13
Two 8-bit register fields (DLH and DLL), called divisor latches, hold this 16-bit divisor. DLH holds the most
significant bits of the divisor, and DLL holds the least significant bits of the divisor. For information about
these register fields, see the UART register descriptions. These divisor latches must be loaded during
initialization of the UART in order to ensure desired operation of the baud generator. Writing to the divisor
latches results in two wait states being inserted during the write access while the baud generator is loaded
with the new value.
Figure 4-26 summarizes the relationship between the transferred data bit, BCLK, and the UART input
clock. Note that the timing relationship depicted in Figure 4-26 shows that each bit lasts for 16 BCLK
cycles . This is in case of 16x over-sampling mode. For 13× over-sampling mode each bit lasts for 13
BCLK cycles .
Example baud rates and divisor values relative to a 192-MHz UART input clock and 16× over-sampling
mode are shown in Table 4-24.
Figure 4-25. UART Clock Generation Diagram
PRU-ICSS
UART
Receiver
DLH:DLL timing and
control
Clock UART input clock Baud BCLK

Input clock
generator generator
Transmitter
timing and
control
Other logic
Figure 4-26. Relationships Between Data Bit, BCLK, and UART Input Clock
n UART input clock cycles, where n = divisor in DLH:DLL
UART input clock

n
BCLK
Each bit lasts 16 BCLK cycles.

When receiving, the UART samples the bit in the 8th cycle.
BCLK
UARTn_TXD,
D1 D2
UARTn_RXD
D0
UARTn_TXD, START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP1 STOP2

UARTn_RXD
Table 4-24. Baud Rate Examples for 192-MHZ UART Input Clock and 16× Over-sampling Mode
Baud Rate Divisor Value Actual Baud Rate Error (%)
2400 5000 2400 0.00
4800 2500 4800 0.00
9600 1250 9600 0.00
19200 625 19200 0.00
38400 313 38338.658 -0.16
56000 214 56074.766 0.13
128000 94 127659.574 -0.27
300000 40 300000 0.00
Table 4-25. Baud Rate Examples for 192-MHZ UART Input Clock and 13× Over-sampling Mode
Baud Rate Divisor Value Actual Baud Rate Error (%)
2400 6154 2399.940 -0.0025
4800 3077 4799.880 -0.0025
9600 1538 9602.881 0.03
19200 769 19205.762 0.03
38400 385 38361.638 -0.10
56000 264 55944.056 -0.10
128000 115 128428.094 0.33
300000 49 301412.873 0.47
4.4.4.2.2 Signal Descriptions

The UARTs utilize a minimal number of signal connections to interface with external devices. The UART
signal descriptions are included in Table 4-26. Note that the number of UARTs and their supported
features vary on each device. See your device-specific data manual for more details.
Table 4-26. UART Signal Descriptions

Signal Name (1) Signal Type Function
UARTn_TXD Output Serial data transmit
UARTn_RXD Input Serial data receive
(2)
UARTn_CTS Input Clear-to-Send handshaking signal
(2)
UARTn_RTS Output Request-to-Send handshaking signal
(1)
The value n indicates the applicable UART; that is, UART0, UART1, etc.
(2)
This signal is not supported in all UARTs. See your device-specific data manual to check if it is
supported.
4.4.4.2.3 Pin Multiplexing

Extensive pin multiplexing is used to accommodate the largest number of peripheral functions in the
smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at
device reset and software programmable register settings. See your device-specific data manual to
determine how pin multiplexing affects the UART.
4.4.4.2.4 Protocol Description
4.4.4.2.4.1 Transmission
The UART transmitter section includes a transmitter hold register (THR) and a transmitter shift register
(TSR). When the UART is in the FIFO mode, THR is a 16-byte FIFO. Transmitter section control is a
function of the UART line control register (LCR). Based on the settings chosen in LCR, the UART
transmitter sends the following to the receiving device:
• 1 START bit
• 5, 6, 7, or 8 data bits
• 1 PARITY bit (optional)
• 1, 1.5, or 2 STOP bits
4.4.4.2.4.2 Reception
The UART receiver section includes a receiver shift register (RSR) and a receiver buffer register (RBR).
When the UART is in the FIFO mode, RBR is a 16-byte FIFO. Receiver section control is a function of the
UART line control register (LCR). Based on the settings chosen in LCR, the UART receiver accepts the
following from the transmitting device:
• 1 START bit
• 1 STOP bit (any other STOP bits transferred with the above data are not detected)
4.4.4.2.4.3 Data Format

The UART transmits in the following format:
1 START bit + data bits (5, 6, 7, 8) + 1 PARITY bit (optional) + STOP bit (1, 1.5, 2)
It transmits 1 START bit; 5, 6, 7, or 8 data bits, depending on the data width selection; 1 PARITY bit, if
parity is selected; and 1, 1.5, or 2 STOP bits, depending on the STOP bit selection.
The UART receives in the following format:
1 START bit + data bits (5, 6, 7, 8) + 1 PARITY bit (optional) + 1 STOP bit
It receives 1 START bit; 5, 6, 7, or 8 data bits, depending on the data width selection; 1 PARITY bit, if
parity is selected; and 1 STOP bit.
The protocol formats are shown in Figure 4-27.
Figure 4-27. UART Protocol Formats

Transmit/Receive for 5-bit data, parity Enable, 1 STOP bit
D0 D1 D2 D3 D4 PARITY STOP1

D0 D1 D2 D3 D4 D5 PARITY STOP1

D0 D1 D2 D3 D4 D5 D6 PARITY STOP1

D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP1
4.4.4.2.5 Operation
4.4.4.2.5.1 Transmission
The UART transmitter section includes a transmitter hold register (THR) and a transmitter shift register
function of the UART line control register (LCR). Based on the settings chosen in LCR, the UART
transmitter sends the following to the receiving device:
• 1 START bit
• 1, 1.5, or 2 STOP bits
THR receives data from the internal data bus, and when TSR is ready, the UART moves the data from
THR to TSR. The UART serializes the data in TSR and transmits the data on the UARTn_TXD pin.
In the non-FIFO mode, if THR is empty and the THR empty (THRE) interrupt is enabled in the interrupt
enable register (IER), an interrupt is generated. This interrupt is cleared when a character is loaded into
THR or the interrupt identification register (IIR) is read. In the FIFO mode, the interrupt is generated when
the transmitter FIFO is empty, and it is cleared when at least one byte is loaded into the FIFO or IIR is
read.
4.4.4.2.5.2 Reception
The UART receiver section includes a receiver shift register (RSR) and a receiver buffer register (RBR).
When the UART is in the FIFO mode, RBR is a 16-byte FIFO. Timing is supplied by the 16× receiver
clock. Receiver section control is a function of the UART line control register (LCR). Based on the settings
chosen in LCR, the UART receiver accepts the following from the transmitting device:
• 1 START bit
• 1 STOP bit (any other STOP bits transferred with the above data are not detected)
RSR receives the data bits from the UARTn_RXD pin. Then RSR concatenates the data bits and moves
the resulting value into RBR (or the receiver FIFO). The UART also stores three bits of error status
information next to each received character, to record a parity error, framing error, or break.
In the non-FIFO mode, when a character is placed in RBR and the receiver data-ready interrupt is enabled
in the interrupt enable register (IER), an interrupt is generated. This interrupt is cleared when the character
is read from RBR. In the FIFO mode, the interrupt is generated when the FIFO is filled to the trigger level
selected in the FIFO control register (FCR), and it is cleared when the FIFO contents drop below the
trigger level.
4.4.4.2.5.3 FIFO Modes

The following two modes can be used for servicing the receiver and transmitter FIFOs:
• FIFO interrupt mode. The FIFO is enabled and the associated interrupts are enabled. Interrupts are
sent to the CPU to indicate when specific events occur.
• FIFO poll mode. The FIFO is enabled but the associated interrupts are disabled. The CPU polls status
bits to detect specific events.
Because the receiver FIFO and the transmitter FIFO are controlled separately, either one or both can be
placed into the interrupt mode or the poll mode.
4.4.4.2.5.3.1 FIFO Interrupt Mode

When the receiver FIFO is enabled in the FIFO control register (FCR) and the receiver interrupts are
enabled in the interrupt enable register (IER), the interrupt mode is selected for the receiver FIFO. The
following are important points about the receiver interrupts:
• The receiver data-ready interrupt is issued to the CPU when the FIFO has reached the trigger level
that is programmed in FCR. It is cleared when the CPU or the DMA controller reads enough characters
from the FIFO such that the FIFO drops below its programmed trigger level.
• The receiver line status interrupt is generated in response to an overrun error, a parity error, a framing
error, or a break. This interrupt has higher priority than the receiver data-ready interrupt. For details,
see Section 4.4.4.2.8.
• The data-ready (DR) bit in the line status register (LSR) indicates the presence or absence of
characters in the receiver FIFO. The DR bit is set when a character is transferred from the receiver
shift register (RSR) to the empty receiver FIFO. The DR bit remains set until the FIFO is empty again.
• A receiver time-out interrupt occurs if all of the following conditions exist:
– At least one character is in the FIFO,
– The most recent character was received more than four continuous character times ago. A
character time is the time allotted for 1 START bit, n data bits, 1 PARITY bit, and 1 STOP bit,
where n depends on the word length selected with the WLS bits in the line control register (LCR).
See Table 4-27.
– The most recent read of the FIFO has occurred more than four continuous character times before.
• Character times are calculated by using the baud rate.
• When a receiver time-out interrupt has occurred, it is cleared and the time-out timer is cleared when
the CPU or the EDMA controller reads one character from the receiver FIFO. The interrupt is also
cleared if a new character is received in the FIFO or if the URRST bit is cleared in the power and
emulation management register (PWREMU_MGMT).
• If a receiver time-out interrupt has not occurred, the time-out timer is cleared after a new character is
received or after the CPU or EDMA reads the receiver FIFO.
When the transmitter FIFO is enabled in FCR and the transmitter holding register empty (THRE) interrupt
is enabled in IER, the interrupt mode is selected for the transmitter FIFO. The THRE interrupt occurs when
the transmitter FIFO is empty. It is cleared when the transmitter hold register (THR) is loaded (1 to 16
characters may be written to the transmitter FIFO while servicing this interrupt) or the interrupt
identification register (IIR) is read.
Table 4-27. Character Time for Word Lengths

Word Length (n) Character Time Four Character Times
5 Time for 8 bits Time for 32 bits
4.4.4.2.5.3.2 FIFO Poll Mode

When the receiver FIFO is enabled in the FIFO control register (FCR) and the receiver interrupts are
disabled in the interrupt enable register (IER), the poll mode is selected for the receiver FIFO. Similarly,
when the transmitter FIFO is enabled and the transmitter interrupts are disabled, the transmitted FIFO is in
the poll mode. In the poll mode, the CPU detects events by checking bits in the line status register (LSR):
• The RXFIFOE bit indicates whether there are any errors in the receiver FIFO.
• The TEMT bit indicates that both the transmitter holding register (THR) and the transmitter shift
register (TSR) are empty.
• The THRE bit indicates when THR is empty.
• The BI (break), FE (framing error), PE (parity error), and OE (overrun error) bits specify which error or
errors have occurred.
• The DR (data-ready) bit is set as long as there is at least one byte in the receiver FIFO.
Also, in the FIFO poll mode:
• The interrupt identification register (IIR) is not affected by any events because the interrupts are
disabled.
• The UART does not indicate when the receiver FIFO trigger level is reached or when a receiver time-
out occurs.
4.4.4.2.5.4 Autoflow Control

The UART can employ autoflow control by connecting the UARTn_CTS and UARTn_RTS signals. Note
that all UARTs do not support autoflow control; see your device-specific data manual for supported
features. The UARTn_CTS input must be active before the transmitter FIFO can transmit data. The
UARTn_RTS output becomes active when the receiver needs more data and notifies the sending device.
When UARTn_RTS is connected to UARTn_CTS, data transmission does not occur unless the receiver
FIFO has space for the data. Therefore, when two UARTs are connected as shown in Figure 4-28 with
autoflow enabled, overrun errors are eliminated.
Figure 4-28. UART Interface Using Autoflow Diagram

UART UART
Serial to UARTn_RXD tx Parallel to

Parallel Serial
Receiver Transmitter
FIFO Flow UARTn_RTS cts Flow FIFO
Control Control
D[7:0] D[7:0]
Parallel to UARTn_TXD rx Serial to
Transmitter Serial Parallel Receiver
FIFO Flow Flow FIFO
UARTn_CTS rts
Control Control
Device Off-chip
4.4.4.2.5.4.1 UARTn_RTS Behavior

UARTn_RTS data flow control originates in the receiver block (see Figure 4-24). When the receiver FIFO
level reaches a trigger level of 1, 4, 8, or 14 (see Figure 4-29), UARTn_RTS is deasserted. The sending
UART may send an additional byte after the trigger level is reached (assuming the sending UART has
another byte to send), because it may not recognize the deassertion of UARTn_RTS until after it has
begun sending the additional byte. For trigger level 1, 4, and 8, UARTn_RTS is automatically reasserted
once the receiver FIFO is emptied. For trigger level 14, UARTn_RTS is automatically reasserted once the
receiver FIFO drops below the trigger level.
Figure 4-29. Autoflow Functional Timing Waveforms for UARTn_RTS
Start Bits N Stop Start Bits N+1 Stop Start

UARTn_RXD
UARTn_RTS
(1) N = Receiver FIFO trigger level.

(2) The block in dashed lines covers the case where an additional byte is sent.
4.4.4.2.5.4.2 UARTn_CTS Behavior

The transmitter checks UARTn_CTS before sending the next data byte. If UARTn_CTS is active, the
transmitter sends the next byte. To stop the transmitter from sending the following byte, UARTn_CTS
must be released before the middle of the last STOP bit that is currently being sent (see Figure 4-30).
When flow control is enabled, UARTn_CTS level changes do not trigger interrupts because the device
automatically controls its own transmitter. Without autoflow control, the transmitter sends any data present
in the transmitter FIFO and a receiver overrun error may result.
Figure 4-30. Autoflow Functional Timing Waveforms for UARTn_CTS
Start Bits0−7 Stop Start Bits 0−7 Stop Start Bits 0−7 Stop
UARTn_TXD
UARTn_CTS
(1) When UARTn_CTS is active (low), the transmitter keeps sending serial data out.
(2) When UARTn_CTS goes high before the middle of the last STOP bit of the current byte, the transmitter
finishes sending the current byte but it does not send the next byte.
(3) When UARTn_CTS goes from high to low, the transmitter begins sending data again.
4.4.4.2.5.5 Loopback Control

The UART can be placed in the diagnostic mode using the LOOP bit in the modem control register (MCR),
which internally connects the UART output back to the UART input. In this mode, the transmit and receive
data paths, the transmitter and receiver interrupts, and the modem control interrupts can be verified
without connecting to another UART.
4.4.4.2.6 Reset Considerations
4.4.4.2.6.1 Software Reset Considerations

Two bits in the power and emulation management register (PWREMU_MGMT) control resetting the parts
of the UART:
• The UTRST bit controls resetting the transmitter only. If UTRST = 1, the transmitter is active;
if UTRST = 0, the transmitter is in reset.
• The URRST bit controls resetting the receiver only. If URRST = 1, the receiver is active;
if URRST = 0, the receiver is in reset.
In each case, putting the receiver and/or transmitter in reset will reset the state machine of the affected
portion but does not affect the UART registers.
4.4.4.2.6.2 Hardware Reset Considerations

When the processor RESET pin is asserted, the entire processor is reset and is held in the reset state
until the RESET pin is released. As part of a device reset, the UART state machine is reset and the UART
registers are forced to their default states. The default states of the registers are shown in Section 4.5.5.
4.4.4.2.7 Initialization
The following steps are required to initialize the UART:
1. Perform the necessary device pin multiplexing setup (see your device-specific data manual).
2. Set the desired baud rate by writing the appropriate clock divisor values to the divisor latch registers
(DLL and DLH).
3. If the FIFOs will be used, select the desired trigger level and enable the FIFOs by writing the
appropriate values to the FIFO control register (FCR). The FIFOEN bit in FCR must be set first, before
the other bits in FCR are configured.
4. Choose the desired protocol settings by writing the appropriate values to the line control register
(LCR).
5. If autoflow control is desired, write appropriate values to the modem control register (MCR). Note that
all UARTs do not support autoflow control; see your device-specific data manual for supported
features.
6. Choose the desired response to emulation suspend events by configuring the FREE bit, and enable
the UART by setting the UTRST and URRST bits in the power and emulation management register
(PWREMU_MGMT).
4.4.4.2.8 Interrupt Support
4.4.4.2.8.1 Interrupt Events and Requests

The UART generates the interrupt requests described in Table 4-28. All requests are multiplexed through
an arbiter to a single UART interrupt request to the CPU, as shown in Figure 4-31. Each of the interrupt
requests has an enable bit in the interrupt enable register (IER) and is recorded in the interrupt
identification register (IIR).
If an interrupt occurs and the corresponding enable bit is set to 1, the interrupt request is recorded in IIR
and is forwarded to the CPU. If an interrupt occurs and the corresponding enable bit is cleared to 0, the
interrupt request is blocked. The interrupt request is neither recorded in IIR nor forwarded to the CPU.
4.4.4.2.8.2 Interrupt Multiplexing

The UARTs have dedicated interrupt signals to the CPU and the interrupts are not multiplexed with any
other interrupt source.
Table 4-28. UART Interrupt Requests Descriptions

UART Interrupt
Request Interrupt Source Comment
THREINT THR-empty condition: The transmitter holding register If THREINT is enabled in IER, by setting the ETBEI
(THR) or the transmitter FIFO is empty. All of the data bit, it is recorded in IIR.
has been copied from THR to the transmitter shift As an alternative to using THREINT, the CPU can poll
register (TSR). the THRE bit in the line status register (LSR).
RDAINT Receive data available in non-FIFO mode or trigger If RDAINT is enabled in IER, by setting the ERBI bit,
level reached in the FIFO mode. it is recorded in IIR.
As an alternative to using RDAINT, the CPU can poll
the DR bit in the line status register (LSR). In the
FIFO mode, this is not a functionally equivalent
alternative because the DR bit does not respond to
the FIFO trigger level. The DR bit only indicates the
presence or absence of unread characters.
RTOINT Receiver time-out condition (in the FIFO mode only): The receiver time-out interrupt prevents the UART
No characters have been removed from or input to from waiting indefinitely, in the case when the receiver
the receiver FIFO during the last four character times FIFO level is below the trigger level and thus does not
(see Table 4-27), and there is at least one character generate a receiver data-ready interrupt.
in the receiver FIFO during this time. If RTOINT is enabled in IER, by setting the ERBI bit,
it is recorded in IIR.
There is no status bit to reflect the occurrence of a
time-out condition.
RLSINT Receiver line status condition: An overrun error, parity If RLSINT is enabled in IER, by setting the ELSI bit, it
error, framing error, or break has occurred. is recorded in IIR.
As an alternative to using RLSINT, the CPU can poll
the following bits in the line status register (LSR):
overrun error indicator (OE), parity error indicator
(PE), framing error indicator (FE), and break indicator
(BI).
Figure 4-31. UART Interrupt Request Enable Paths

Conditions Enable bits UART interrupt requests
Transmitter holding
register empty THREINT
IER(ETBEI)
Receiver data ready RDRINT
IER(ERBI)
RTOINT Arbiter UART interrupt
request to CPU
Receiver time-out
Overrun error
Parity error RLSINT
Framing error IER(ELSI)
Break
4.4.4.2.9 DMA Event Support

In the FIFO mode, the UART generates the following two DMA events:
• Receive event (URXEVT): The trigger level for the receiver FIFO (1, 4, 8, or 14 characters) is set with
the RXFIFTL bit in the FIFO control register (FCR). Every time the trigger level is reached or a receiver
time-out occurs, the UART sends a receive event to the EDMA controller. In response, the EDMA
controller reads the data from the receiver FIFO by way of the receiver buffer register (RBR). Note that
the receive event is not asserted if the data at the top of the receiver FIFO is erroneous even if the
trigger level has been reached.
• Transmit event (UTXEVT): When the transmitter FIFO is empty (when the last byte in the transmitter
FIFO has been copied to the transmitter shift register), the UART sends a UTXEVT signal to the EDMA
controller. In response, the EDMA controller refills the transmitter FIFO by way of the transmitter
holding register (THR). The UTXEVT signal is also sent to the DMA controller when the UART is taken
out of reset using the UTRST bit in the power and emulation management register
(PWREMU_MGMT).
Activity in DMA channels can be synchronized to these events. In the non-FIFO mode, the UART
generates no DMA events. Any DMA channel synchronized to either of these events must be enabled at
the time the UART event is generated. Otherwise, the DMA channel will miss the event and, unless the
UART generates a new event, no data transfer will occur.
4.4.4.2.10 Power Management

The UART peripheral can be placed in reduced-power modes to conserve power during periods of low
activity. The power management of the UART peripheral is controlled by the processor Power and Clock
Management (PRCM). The PRCM acts as a master controller for power management for all of the
peripherals on the device. For detailed information on power management procedures using the PSC, see
the chapter Power, Reset, and Clock Management (PRCM) in the device reference manual.
4.4.4.2.11 Emulation Considerations

The FREE bit in the power and emulation management register (PWREMU_MGMT) determines how the
UART responds to an emulation suspend event such as an emulator halt or breakpoint. If FREE = 0 and a
transmission is in progress, the UART halts after completing the one-word transmission; if FREE = 0 and
a transmission is not in progress, the UART halts immediately. If FREE = 1, the UART does not halt and
continues operating normally.
Note also that most emulator accesses are transparent to UART operation. Emulator read operations do
not affect any register contents, status bits, or operating states, with the exception of the interrupt
identification register (IIR). Emulator writes, however, may affect register contents and may affect UART
operation, depending on which register is accessed and what value is written.
The UART registers can be read from or written to during emulation suspend events, even if the UART
activity has stopped.
4.4.4.2.12 Exception Processing
4.4.4.2.12.1 Divisor Latch Not Programmed

Since the processor reset signal has no effect on the divisor latch, the divisor latch will have an unknown
value after power up. If the divisor latch is not programmed after power up, the baud clock (BCLK) will not
operate and will instead be set to a constant logic 1 state.
The divisor latch values should always be reinitialized following a processor reset.
4.4.4.2.12.2 Changing Operating Mode During Busy Serial Communication

Since the serial link characteristics are based on how the control registers are programmed, the UART will
expect the control registers to be static while it is busy engaging in a serial communication. Therefore,
changing the control registers while the module is still busy communicating with another serial device will
most likely cause an error condition and should be avoided.
4.4.5 ECAP
The PRU ECAP module within the PRU-ICSS is identical to the ECAP module in the AM335x PWMSS.
For additional details about the ECAP module, see Section 15.3, Pulse-Width Modulation Subsystem
(PWMSS).
4.4.6 MII_RT
4.4.6.1 Introduction
The Real-time Media Independent Interface (MII_RT) provides a programmable I/O interface for the PRUs
to access and control up to two MII ports. The MII_RT module can also be configured to push and pull
data independent of the PRU cores.
NOTE: To ensure the MII_RT IO timing values published in the device data manual, the ocp_clk
must be configured for 200 MHz (default value) and the TX_CLK_DELAY bit field in the
PRUSS_MII_RT_TXCFG0/1 register must be configured as follows:
• 100 Mbps mode: 6h (non-default value)
• 10 Mbps mode: 0h (default value)
4.4.6.1.1 Features
The PRU-ICSS MII_RT module supports:
• Two MII ports
– Each MII port has:
• 32-byte RX L1 FIFO
• 64-byte RX L2 buffer
• 64-byte TX L1 FIFO
– Rate decoupling on TX L1 FIFO
– Configurable pre-amble removal on RX L1 FIFO and insertion on TX L1 FIFO
– Configurable TX L1 FIFO trigger (10 bits with 40 ns ticks)
• MII port multiplexer per direction to support line/ring structure
– Link detection through RX_ERR
• Cyclic redundancy check (CRC)
– CRC32 generation on TX path
– CRC32 checker on RX path
4.4.6.1.2 Unsupported Features

The PRU-ICSS MII_RT module does not support:
• Auto padding in TX L1 FIFO
• Dynamic TX multiplexer switching during packet handling
– Can allow one PRU to handle both MII interfaces and a second PRU to manage the host and
switch functions.
4.4.6.1.3 Block Diagram

Figure 4-32 shows the MII_RT in context of the PRU-ICSS. This diagram is a conceptual block diagram
and does not necessarily reflect actual topologies.
Figure 4-32. MII_RT Block Diagram
PRU0
RX MII to PRU RX MII or PRU to

Interface 0 TX MII
Interface 0
RX L2 buffer
MII RX Port 0 TX L1 FIFO MII TX Port 0
RX L1 FIFO
RX MII to PRU RX MII or PRU to

Interface 1 TX MII
Interface 1
RX L2 buffer
TX L1 FIFO MII TX Port 1
RX L1 FIFO
MII RX Port 1
PRU1
4.4.6.2 Functional Description
4.4.6.2.1 Data Path Configuration

The MII_RT module supports three basic data path configurations. These configurations are compared in
Table 4-29 and described in the following sections.
Table 4-29. Data Path Configuration Comparison

Configuration PRU Dependency Data Servicing Port-to-Port Latency
Auto-forward Snoop only One word in flight Low
8- or 16-bit processing with on- Yes One word or byte in flight Low
the-fly modifications
(RX L1)
32-byte double buffer or ping- Yes Multi-words in flight Medium (application-
pong processing dependent)
(RX L2)
4.4.6.2.1.1 Auto-forward with Optional PRU Snoop

Data is automatically forwarded from the MII RX port to the MII TX port without manipulations, as shown in
Figure 4-33. This configuration does not depend on the PRU core. However, it does support an option for
PRU to snoop or monitor the received data through the RX L2, shown in Figure 4-34. The PRU does not
access data and status bits through R31, and it does not modify and push data.
Figure 4-33. Auto-forward

RX L1 TX L1
RX_DV TX_DATA
MII RX port FIFO 32 bytes FIFO 64 bytes MII TX port
RX_CLK TX_EN
Figure 4-34. Auto-forward with PRU Snoop

RX L2
Bank 0
32 bytes of data XFR
PRU
Bank 1
32 bytes of data
RX L1 TX L1
RX_DV TX_DATA
RX_CLK TX_EN
4.4.6.2.1.2 8- or 16-bit Processing with On-the-Fly Modifications

This configuration services one byte or word in flight and has low latency. The PRU has the option to
manipulate the received word and control popping data from the RX L1 FIFO and pushing it on the TX L1
FIFO.
Figure 4-35. 8- or 16-bit Processing with On-the-Fly Modifications
PRU
RX L1 TX L1
RX_DV TX_DATA
RX_CLK TX_EN
4.4.6.2.1.3 32-byte Double Buffer or Ping-Pong Processing

This configuration supports high bandwidth, high efficiency transactions. Often implementations using this
mode permit relaxed servicing requirements allowing the PRU to manipulate the received data before
transmitting.
Data received in this configuration is passed into the RX L2 buffer. The PRU reads multiple bytes of data
from one of the RX L2 banks through the high bandwidth broadside interface and XFR instructions. The
PRU can then store or manipulate data before pushing it to the TX L1 FIFO for transmission on the MII TX
port.
Figure 4-36. 32-byte Double Buffer or Ping-Pong Processing

RX L2
Bank 0
32 bytes of data XFR Memory
PRU
Bank 1
32 bytes of data
RX L1 TX L1
RX_DV TX_DATA
RX_CLK TX_EN
4.4.6.2.2 Definition and Terms
4.4.6.2.2.1 Data Frame Structure

The data received and transmitted over MII conforms with the following frame structure:
Table 4-30. Frame Structure

Inter-frame Preamble Start of Frame Delimiter (SFD) Data Cyclic Redundancy Check (CRC)
The data following the SFD is formatted in a 4-bit nibble structure. Figure 4-37 illustrates the nibble order.
The MSB arriving first is on the LSB side of a nibble. When receiving data, the MII_RT receive logic will
wait for the next nibble to arrive before constructing a byte and delivering to the PRU.
Figure 4-37. Data Nibble Structure

Serial Bit Stream
LSB MSB
D0 D1 D2 D3 D4 D5 D6 D7
MII Nibble Stream
D0 D1 D2 D3 D0 D1 D2 D3
Constructing a byte and LSB MSB LSB MSB
sent to PRU and TX L1 FIFO
First Nibble Second Nibble
4.4.6.2.2.2 PRU R30 and R31

The PRU registers R30 and R31 are used to receive, transmit, and control the data for the PRU. As
shown in Figure 4-38, the R31 is used to access data in the RX L1 FIFO, the R30 is used to transmit data
from the PRU, and the R31 output is used the control the flow of receive and transmit. For more details
about these registers, see the following sections.
Figure 4-38. PRU R30, R31 Operations

PRU
R30 (W):
TX Interface Data
R31 (R):
Data
RX Interface
R31 (W):
RX & TX cmd Interface
4.4.6.2.2.3 RX and TX L1 FIFO Data Movement

To advance the next data byte seen by R31, the PRU must pop the data from the RX L1 FIFO. Likewise,
the PRU can push the data from R30 to the TX L1 FIFO. These operations are illustrated in Figure 4-39.
Figure 4-39. Reading and Writing FIFO Data
pop push
(R31 cmd) (R31 cmd)
FIFO 32 bytes
FIFO 64 bytes
RX L1 TX L1
4.4.6.2.2.4 CRC Computation
4.4.6.2.2.4.1 Receive CRC Computation

For the incoming data, the MII_RT calculates CRC32 and then compares against the value provided in the
incoming frame. If there is a mismatch, the MII RT signals ERROR_CRC to the PRU. If a previous node or
Ethernet device appended an error nibble, the CRC calculation of received packet will be wrong because
the longer frame and the frame length will end at a 4-bit boundary instead of the usual 8-bit boundary.
When RX_DV goes inactive on the 4-bit boundary, the interface will assert DATA_RDY and BYTE_RDY
flag with the ERROR NIBBLE. The error event is also mapped into the PRU-ICSS INTC.
4.4.6.2.2.4.2 Transmit CRC Computation

For the outgoing data, the MII_RT calculates the CRC32 value and inserts it into outgoing packets. The
CRC value computed on each MII transmit path is also available in memory map registers (MMRs) that
can be read by the PRU and used primarily for debug and diagnostic purposes. The CRC is inserted into
the outgoing packet based on the commands received through the R31 register of the PRU. The CRC will
be inserted into the TX L1 FIFO, and there must be enough room to store the CRC value in the FIFO or
else the FIFO will overflow. As Table 4-31 shows, the CRC programming model supports three sequences
that provide more flexibility. Note “cmdR31” indicates write to the mentioned bits of the R31 command
interface.
NOTE: If “auto-generation of preamble” option is used (i.e. with the first push of payload into the TX
FIFO the preamble is inserted into the TX FIFO automatically), then the first push of payload
must be a byte push (i.e. TX_PUSH8). If you push a word first, the CRC is not calculated
correctly.
Table 4-31. TX CRC Programming Models

Option 1 Step 1: cmdR31 [TX_CRC_HIGH + TX_CRC_LOW + TX_EOF]
Step 1: cmdR31 [TX_CRC_HIGH]
Option 2 Step 2: wait > 6 clocks (PRU cycles)
Step 3: cmdR31 [TX_CRC_LOW + TX_EOF]
Step 1: cmdR31 [TX_CRC_HIGH]
Step 2: wait > 6 clocks (PRU cycles)
Option 3 Step 3: read TXCRC0/1
Step 4: modify CRC[15:0]
Step 5: cmdR31 [TX_PUSH16 + TX_EOF + TX_ERROR_NIBBLE]
4.4.6.2.3 RX MII Interface
4.4.6.2.3.1 RX MII Submodule Overview

The RX MII interface is composed of multiple submodules that process the incoming frames and pass
receive data and status information into the PRU register R31. These submodules include:
• Latch received data
• Start of frame detection
• Start frame delimiter detection
• CRC calculation and error detection
• Enhanced link detection through RX error detection
Table 4-32 includes more details about the internal signals and output of these submodules.
4.4.6.2.3.1.1 Receive Data Latch

The receive data from the MII interface is stored in the receive data FIFO which is 32 bytes. The PRU can
access this data through the register R31. Depending on the configuration settings, the data can be
latched on reception of one or two bytes. In each scheme, the configured number of nibbles is assembled
before being copied into the PRU registers. Figure 4-40 shows the inputs and outputs of the data latch
logic block.
The receiver logic in MII_RT can be programmed through the RXCFG0 and RXCFG1 registers to remove
or retain the preamble + SFD from incoming frames.
Figure 4-40. RX Data Latch

DATA_RDY
RX_DV
BYTE_RDY
RX_DATA WORD_RDY
4x4 Bit
8/16 Bit RX_NIBBLE_ODD
Output
BYTE1 (RX FIFO DATA)
RX_CLK
BYTE2 (RX FIFO DATA)
4.4.6.2.3.1.1.1 Start of Frame Detection

The start of frame detection logic tracks the frame boundaries and signals the beginning of a frame to
other components of the PRU-ICSS. This logic detects two events:
• Start of Frame (SOF) event that occurs when Receive Data Valid MII signal is sampled high.
• Start of Frame Delimiter (SFD) event is seen on MII Receive Data bus.
These event triggers can be used to add timestamp to the frames. The notification for these events is
available through R31 as well as through INTC which is integrated in the PRU-ICSS. Figure 4-41 shows
the inputs and outputs of the start of frame detection logic block.
Figure 4-41. Start of Frame Detection

RX_CLK
SOF
RX_DV Frame
Detection
SFD
RX_DATA
4.4.6.2.3.1.1.2 CRC Error Detection

For each incoming frame, the CRC is calculated by the MII_RT and compared against the CRC included
in the frame. When the two values do not match, a CRC error is flagged. The ERROR_CRC indication is
available in the register interface (PRU R31 Receive Interface) as well as in the FIFO interface (RX L2
Status Interface). It is also provided to the INTC which is integrated in the PRU-ICSS. Figure 4-42 shows
the inputs and outputs of CRC error detection logic block.
Figure 4-42. CRC Error Detection

SFD
RX_CLK
CRC Checksum ERROR_CRC
RX_DV and
Error Detection
RX_DATA
4.4.6.2.3.1.1.3 RX Error Detection and Action

The RX error detection logic tracks the receive error signaled by the physical layer and informs the PRU-
ICSS INTC whenever an error is detected. Figure 4-43 shows the inputs and outputs of the RX error
detection logic block. Note the following dependencies:
• RX_ERR signal is only sampled when RX_DV is asserted.
• All nibbles are discarded post RX_ERR event, including the nibble which had RX_ERR asserted. This
state will remain until EOF occurs.
• Due to this fact, RX L1 FIFO and RX L2 FIFO will never receive any data with RX_ERR or post
RX_ERR during that frame.
Figure 4-43. RX Error Detection
RX_ERR RX Error RX_ERR32

Detection 0/1 (interrupt event)
This submodule also keeps track of a running count of receive error events within a 10 μs error detection
window, as shown in Figure 4-44. The INTC is notified when 32 or more events have occurred in a 10 μs
error detection window. The error detection window is not a sliding window but a non-overlapping window
with no specific initialization time with respect to incoming traffic. The timer starts its 10 μs counts
immediately after de-assertion of reset to the MII_RT module.
Figure 4-44. Error Detection Window with Running Counter

10 μs
(A)
10 μs
(B)
A There are fewer than 32 consecutive error events in the 10 μs window. The detection module will not forward to the
interrupt controller (INTC).
B There are more or equal to 32 error events in the 10 μs window. The detection module will notify the interrupt
controller (INTC).
4.4.6.2.3.1.2 RX Data Path Options to PRU

There are two data path options for delivering received data to the PRU, described further in the
subsequent sections:
1. RX MII port → RX L1 FIFO → PRU (one word in flight)
2. RX MII port → RX L1 FIFO → RX L2 buffer → PRU (multi-word in flight)
Once the PRU has received RX data, the PRU can both manipulate received data or send data to the TX
MII Interface.
4.4.6.2.3.1.2.1 RX MII Port → RX L1 FIFO → PRU

The RX L1 FIFO to PRU interface is depicted in Figure 4-45. In this mode, the data received from the MII
interface is fed into the 32-byte RX L1 FIFO. The first data byte into the FIFO is automatically available in
R31 of the PRU. Therefore, the PRU firmware can directly operate on this data without having to read it in
a separate instruction. This allows the PRU to access receive data with low latency.
Figure 4-45. RX L1 to PRU Interface
PRU
R31
RX L1
RX_DV
MII RX port FIFO 32 bytes
RX_CLK
When the new data is received, the PRU is provided with up to two bytes at a time in the R31 register, as
shown in Figure 4-46. Once the PRU processes the incoming data, it instructs the MII_RT by writing to the
R31 command interface bits to pop one or two bytes of data from the 32-byte RX FIFO. The pop operation
causes current contents of R31 to be refreshed with new data from the incoming packet. Each time the
data is popped, the status bits change to indicate so. If the pop is completed and there is no new data, the
status bits immediately change to indicate no new data. Note the current R31 content, including data, will
be lost after issuing the pop operation. If this information needs to be accessed later, the PRU should
store the existing R31 content before popping new data.
Figure 4-46. MII RX Data to PRU R31 (R) and RX FIFO
PRU - R31 0:7 8:15 16 17 18 19 20 21 22 23 24 25:29 30:31
RESERVED
<ERR> bits
FIFO ERROR_CRC
ERROR_NIBBLE
RX_SOF
MII RX_DV
RX_SFD
MII RX_CLK
RX_EOF
RX_ERROR
WORD_RDY
BYTE_RDY
DATA_RDY
Table 4-32 describes the receive interface data and status contents provided by the R31 register. These
contents are available when R31 is read. To configure this register, the PRU GPI mode should be set for
MII_RT mode in the CFG register space. Note the following:
1. If the data from the receive path is not read in time, it could cause an overflow event because the data
is still continuously provided to the 32-byte receive FIFO. Due to the receive FIFO overflow, the data
gets automatically discarded to avoid lack of space in the FIFO. At the same time, an interrupt is raised
to the INTC through a system event (PRU<n>_RX_OVERFLOW). To detect an overflow condition, the
PRU should poll for this system event condition, and a RX RESET command through the R31
command interface is required to clear out from this condition. The received Ethernet frame is
corrupted and should not be used for further processing, as bytes have been dropped due to the
overflow condition. A FIFO reset is recommended.
2. The receive data in the R31 register is available following synchronization to the PRU clock domain.
So, there is a finite delay (120 ns) when data is available from MII interface and it is accessible to the
PRU.
3. The receive FIFO also has the capability to be reset through software. When reset, all contents of
receive FIFO are purged and it may result in the current frame not being received as expected. When
a frame is being received and the PRU resets the RX FIFO, the remaining frame is not placed into the
RX FIFO. However, any new frame arriving on the receive MII port will be stored in the FIFO.
Table 4-32. PRU R31: Receive Interface Data and Status (Read Mode)
Bits Field Name Description
31:30 RESERVED In case of register interface, these bits are provided to PRU by other
modules in PRU-ICSS. From the MII_RT module point of view, these
bits are always zero.
29 RX_MIN_FRM_CNT_ERR RX_MIN_FRM_CNT_ERR is set to 1 when the count of total bytes of
incoming frame is less than the value defined by RX_MIN_FRM_CNT.
RX_MIN_FRM_CNT_ERR is cleared by RX_ERROR_CLR.
28 RX_MAX_FRM_CNT_ERR RX_MAX_FRM_CNT_ERR is set to 1 when the count of total bytes of
incoming frame is more than the value defined by
RX_MAX_FRM_CNT_ERR. RX_MAX_FRM_CNT_ERR is cleared by
RX_ERROR_CLR.
27 RX_EOF_ERROR RX_EOF_ERROR is set to 1 when an RX_EOF event or RX_ERROR
event occurs. RX_EOF_ERROR is cleared by RX_ EOF_CLR and/or
RX_ ERROR_CLR.
26 RX_MAX_PRE_CNT_ERR RX_MAX_PRE_CNT_ERR is set to 1 when the number of nibbles
equaling 0x5 before SFD event (0x5D) is more than the value defined by
RXPCNT0/1 [RX_MAX_PRE_CNT]. RX_MAX_PRE_CNT_ERR is
cleared by RX_ERROR_CLR.
25 RX_ERR RX_ERR is set to 1 when pr1_mii0/1_rxer is asserted while
pr1_mii0/1_rxdv bit is set. RX_ERR is cleared by RX_ERROR_CLR.
24 ERROR_CRC ERROR_CRC indicates that the frame has a CRC mismatch. This bit is
valid when the RX_EOF bit is set. It should be noted that ERROR_CRC
bit is ready in early status, which means it is calculated before data is
available in RXL1 FIFO. ERROR_CRC is cleared by RX_ERROR_CLR.
23 ERROR_NIBBLE ERROR_NIBBLE indicates that the frame ended in odd nibble. It should
be considered valid only when the RX_EOF bit and pr1_mii0/1_rxdv are
set. Nibble counter is enabled post SFD event. It should be noted that
ERROR_NIBBLE bit is ready in early status, which means it is
calculated before data is available in RXL1 FIFO. ERROR_NIBBLE is
cleared by RX_ERROR_CLR.
22 RX_SOF RX_SOF transitions from low to high when the frame data starts to
arrive and pr1_mii0/1_rxdv is asserted. Note there will be a small sync
delay of 0ns – 5ns. The PRU must write one to this bit through the R31
command interface to clear it. The recommended time to clear this bit is
at the end of frame (EOF). It should be noted that RX_SOF bit is ready
in early status, which means it is calculated before data is available in
RXL1 FIFO.
21 RX_SFD RX_SFD transitions from low to high when the SFD sequence (0x5D)
post RX_SOF is observed on the receive MII data. The PRU must write
one to this bit through the R31 command interface to clear it. The
recommended time to clear this bit is at the end of frame (EOF). It
should be noted that RX_SFD bit is ready in early status, which means it
is calculated before data is available in RXL1 FIFO.
20 RX_EOF RX_EOF indicates that the frame has ended and pr1_mii0/1_rxdv is de-
asserted. It also validates the CRC match bit. Note there will be a small
sync delay of 0ns – 5ns. The PRU must write one to clear this bit in the
R31 command interface at the end of the frame. It should be noted that
RX_EOF bit is ready in early status, which means it is calculated before
data is available in RXL1 FIFO.
19 RX_ERROR RX_ERROR indicates one or more of the following errors occurred:
• RX_MAX/MIN_FRM_CNT_ERR
• RX_MAX/MIN_PRE_CNT_ERR
• RX_ERR
RX_ERROR is cleared by RX_ERROR_CLR.
18 WORD_RDY WORD_RDY indicates that all four nibbles in R31 have valid data. There
is a 2 clock cycle latency from the command RX_POP16 to
WORD_RDY update. Therefore, firmware needs to insure it does not
read WORD_RDY until 2 clock cycles after RX_POP16.
17 BYTE_RDY BYTE_RDY indicates that the lower two nibbles in R31 have valid data.
There is a 2 clock cycle latency from the command RX_POP8 to
BYTE_RDY update. Therefore, PRU firmware needs to insure it does
not read BYTE_RDY until 2 clock cycles after RX_POP8.
Table 4-32. PRU R31: Receive Interface Data and Status (Read Mode) (continued)
16 DATA_RDY DATA_RDY indicates there is valid data in R31 ready to be read. This
bit goes to zero when the PRU does a POP8/16 and there is no new
data left in the receive MII port. This bit is high if there is more receive
data for PRU to read. There is a 2 clock cycle latency from the
command RX_POP16/8 to WORD_RDY/BYTE_RDY update. Therefore,
PRU firmware must einsure it does not read BYTE_RDY/WORD_RDY
until 2 clock cycles after RX_POP16/8.
15:8 BYTE1 Data Byte 1. This data is available such that it is safe to read by the
PRU when the DATA_RDY/BYTE_RDY/WORD_RDY bits are asserted.
7:0 BYTE0 Data Byte 0. This data is available such that it is safe to read by the
PRU when the DATA_RDY/BYTE_RDY/WORD_RDY bits are asserted.
4.4.6.2.3.1.2.2 RX MII Port → RX L1 FIFO → RX L2 Buffer → PRU

The RX L2 is an optional high performance buffer between the RX L1 FIFO and the PRU. Figure 4-47
illustrates the receive data path using RX L2 buffer. This data path is characterized by multi-word in flight
transactions.
Figure 4-47. RX L2 to PRU Interface
PRU
RX L2
Bank 0 R2
32 bytes of data XFR …
R13
Bank 1
32 bytes of data R18
R31
RX L1
RX_DV
MII RX port FIFO 32 bytes
RX_CLK
The 64-byte RX L2 buffer is divided into two 32 byte banks, or ping/pong buffers. When the RX L2 is
enabled, the incoming data from the MII RX port will transmit first to the 32 byte RX L1 FIFO. RX L1
pushes data into RX L2, starting when the first byte is ready until the final EOF marker. The RX L2 buffer
does not apply any backpressure to the RX L1 FIFO. Therefore, it is the PRU firmware’s responsibility to
fetch the data in RX L2 before it is overwritten by the cyclic buffer. The RX L1 will remain near empty, with
only one byte (nibble) stored.
Each RX L2 bank holds up to 32 bytes of data, and every four nibbles (or 16 bits) of data has a
corresponding 8-bit status. The data and status information are stored in packed arrays. In each bank, R2
to R9 contains the data packed array and R10 to R13 contains the status packed array. Figure 4-48
shows the relationship of the data registers and status registers. The RX L2 status registers record status
information about the received data, such as ERROR_CRC, RX_ERROR, STATUS_RDY, etc. The RX L2
status register details are described in Table 4-33. Note RX_RESET clears all Data and Status elements
and resets R18.
Figure 4-48. Data and Status Register Dependency
Data Register R2 R3 R4 R5 R6 R7 R8 R9
Status Register R10 R11 R12 R13
Table 4-33. RX L2 Status

Bit Field Name Description
7 ERROR_CRC ERROR_CRC indicates that the frame has a CRC mismatch. This
bit is valid when the RX_EOF bit is set. It should be noted that
ERROR_CRC bit is ready in early status, which means it is
calculated before data is available in RXL1 FIFO. ERROR_CRC will
only be set for one entry, self clear on next entry.
6 ERROR_NIBBLE ERROR_NIBBLE indicates that the frame ended in odd nibble. It
should be considered valid only when the RX_EOF bit and
pr1_mii0/1_rxdv are set. Nibble counter is enabled post SFD event.
It should be noted that ERROR_NIBBLE bit is ready in early status,
which means it is calculated before data is available in RXL1 FIFO.
ERROR_NIBBLE will only be set for one entry, self clear on next
entry.
Table 4-33. RX L2 Status (continued)

Bit Field Name Description
5 RX_SOF RX_SOF transitions from low to high when the frame data starts to
arrive and pr1_mii0/1_rxdv is asserted. Note there will be a small
sync delay of 0ns – 5ns. The recommended time to clear this bit is
at the end of frame (EOF). It should be noted that RX_SOF bit is
ready in early status, which means it is calculated before data is
available in RXL1 FIFO. RX_SOF will only be set for one entry, self
clear on next entry.
4 RX_SFD RX_SFD transitions from low to high when the SFD sequence
(0x5D) post RX_SOF is observed on the receive MII data. The
recommended time to clear this bit is at the end of frame (EOF). It
should be noted that RX_SFD bit is ready in early status, which
means it is calculated before data is available in RXL1 FIFO.
RX_SOF will only be set for one entry, self clear on next entry.
3 RX_EOF RX_EOF indicates that the frame has ended and pr1_mii0/1_rxdv is
de-asserted. It also validates the CRC match bit. Note there will be
a small sync delay of 0ns – 5ns. It should be noted that RX_EOF bit
is ready in early status, which means it is calculated before data is
available in RXL1 FIFO. RX_EOF will only be set for one entry, self
clear on next entry.
RX_EOF is set relative to the write pointer advancing, i.e. the
RX_EOF bit is set after the write pointer advances, rather than
before.
2 RX_ERROR RX_ERROR indicates one or more of the following errors occurred:
• RX_MAX/MIN_FRM_CNT_ERR
• RX_MAX/MIN_PRE_CNT_ERR
• RX_ERR
RX_ERROR is cleared by RX_ERROR_CLR.
1 STATUS_RDY STATUS_RDY is set when RX_EOF or write pointer advanced by 2.
This is a simple method for software to determine if RX_EOF event
has occurred or new data is available. If RX_EOF is not set, all
status bits are static.
0 RX_ERR RX_ERR is set to 1 when pr1_mii0/1_rxer is asserted while
pr1_mii0/1_rxdv bit is set. It will get set for first pr1_mii0/1_rxer
event and self clear on SOF for the next FRAME.
Bank 0 and Bank 1 are used as ping/pong buffers. RX L2 supports the reading of a write pointer in R18
that allows software to determine which bank has active write transactions, as well as the specific write
address within packed data arrays.
The PRU interacts with the RX L2 buffer using the high performance XFR read instructions and broadside
interface. Table 4-34 shows the device XFR ID numbers for each bank.
Table 4-34. RX L2 XFR ID

Device ID Function Description
20 Selects RX L2 Bank0 R2:R9 Data packed array
R10:R13 Status packed array
21 Selects RX L2 Bank1 R2:R9 Data packed array
R10:R13 Status packed array
20/21 Byte pointer of current write R18[5:0] Pointer indicating location of current
write in data packed array.
0 = Bank0.R2.Byte0 (default and reset value)
1 = Bank0.R2.Byte1
2 = Bank0.R2.Byte2
3 = Bank0.R2.Byte3
4 = Bank0.R3.Byte0
…
63=Bank1.R9.Byte3
XFR read transactions are passive and have no effect on any status or other states in RX L2. The
firmware can also read R18 to determine which bank has active write transactions, and the location of the
transaction. With this information, the firmware can read multiple times the stable preserved data. When
RX L1 data is written to RX L2, the next status byte gets cleared at the same time the current status byte
gets updated. The rest of the status buffer is persistent. When the software accesses any register of the
ping/pong buffer, the software must issue an XFER read transaction to fetch the latest or current state of
the ping/pong buffer. The PRU registers do not reflect the current snapshot of L2 unless an XFER is
issued by the software.
4.4.6.2.4 TX MII Interface

Data to be transmitted is loaded into the TX L1 FIFO. The transmit FIFO (TX L1) stores up to 64 bytes of
transmit data. From the FIFO, the data is sent to the MII TX port of the PHY by the MII_RT transmit logic.
The transmit FIFO also has the capability to be reset through software (TX_RESET). When reset, all
contents of transmit FIFO are purged and this may result in a frame not getting transmitted as expected, if
the transmission is already ongoing. Any new data written in the transmit FIFO results in a new frame
being composed and transmitted. An overflow event will require a TX_RESET to recover from this
condition.
There are four dependencies that must be true for TX_EN to assert:
1. TX L1 FIFO not empty
2. Interpacket gap (IPG) timer expiration
3. RX_DV to TX_EN timer expiration
4. TX_EN compare timer expiration
The transmit interface also provides an underflow error signal if there was no data loaded when TX_EN
triggered. The transmit underflow signal is mapped to the INTC in PRU-ICSS. The PRU firmware must
track the FIFO fill level, such as with a timer or the PRU cycle count register
(PRU_ICSS_CTRL_CYCLE).The current FIFO fill level cannot be accessed by PRU firmware. The
firmware can issue an R31 command through R31 bit 29 (TX_EOF) to indicate that the last byte has been
written into the TX FIFO.
4.4.6.2.4.1 TX Data Path Options to TX L1 FIFO

There are two data path options for delivering data to the TX L1 FIFO and transmit port, described further
in the subsequent sections:
1. PRU → TX L1 FIFO → TX MII port
2. RX L1 FIFO → TX L1 FIFO → TX MII port
4.4.6.2.4.1.1 PRU → TX L1 FIFO → TX MII Port

The PRU can be used to feed data into the TX L1 FIFO using the R30 and R31 registers, shown in
Figure 4-49. The PRU writes up to two bytes of data into R30 and then pushes the data into the TX L1
FIFO by writing to the R31 command interface.
Figure 4-49. PRU to TX L1 Interface
PRU
R30
R31
TX L1
TX_DATA
FIFO 64 bytes MII TX port
TX_EN
Figure 4-50 shows the R30 transmit interface. The lower 16 bits of the R30 (or FIFO transmit word)
contain transmit data nibbles. The upper 16 bits contain mask information. The operation to be performed
on the transmit interface is controlled by PRU writes to the R31 command interface. Table 4-35 describes
the TXMASK and TXDATA bit fields of the R30 transmit interface.
Figure 4-50. PRU to TX MII Interface
PRU R30 0:7 8:15 16:23 24:31
TX MASK[15:8]
MII TX DATA
TX MASK[7:0]
Table 4-35. PRU R30: Transmit Interface

31:16 TXMASK The TXMASK is used to determine which of RX L1 FIFO received
data and R30 data is sent to transmit FIFO. It must to be applied to
TXDATA and RXDATA before it is transmitted. To disable TXMASK
and transmit only TXDATA through R30, set to 0xFFFF. Note
software should not pop the RXDATA from the RX L1 FIFO before
pushing the TXDATA. This will cause new data to propagate before
the push. Otherwise, software can pop and push on the same
command for bytes only or delay the pop after the push for words or
bytes.
15:0 TXDATA Data provided by the PRU to be sent to transmit path after applying
the mask. When 16 bits are to be transmitted, all bits of this and
TXMASK field are used. When 8 bits are to be transmitted, the bits
[7:0] of this and TXMASK field are used.
Using the TX mask, the PRU can send a mix of R30 and RX L1 FIFO data to the TX L1 FIFO. Note the
TX mask is only available when the PRU is fed one word or byte at a time by the RX L1 FIFO. It is not
applicable when the RX L2 buffer is enabled. To disable TX mask, set TXMASK to 0xFFFF.
As shown in Figure 4-51, the PRU drives the MII transmit interface through its R30 register. The contents
of R30 and RX data from the receive interface are taken and fed into a 64 byte transmit FIFO.
Before transmission, a mask is applied to the data portion of the R30 register. By using the mask, the
PRU firmware can control whether received data from the RX L1 FIFO is sent to transmit, R30 data is sent
to transmit, or a mix of the two is sent. The Boolean equation that is used by MII_RT to compose TX data
is:
TXDATA[7/15:0] = (R30[7/15:0] & MASK[7/15:0]) | (RXDATA[7/15:0] & ~MASK [7/15:0])
Figure 4-51. TX Mask Mode

Process data
PRU 0/1
R30
R31
TXDATA[7/15:0] = (R30[7/15:0] & MASK[7/15:0]) |
(RXDATA[7/15:0] & ~MASK [7/15:0])
TX L1
RX L1 TX_DATA
RX_DV FIFO 64 bytes MII TX port
MII RX port FIFO 32 bytes TX_EN
RX_CLK
1. Push
2. Pop
Mask
4.4.6.2.4.1.2 RX L1 FIFO → TX L1 FIFO → TX MII Port

When TXCFG0/1[TX_AUTO_SEQUENCE] is set, the data frame is passed from the RX to TX FIFOs
without the any interaction of the PRU. This mode of operations is shown in Figure 4-52. The RX L1 will
push into TX L1 as long as it is enabled and not full.
There is no PRU dependency in this mode and no option for the PRU to perform any operation to the TX
L1 FIFO. RX_RESET clears all data and status elements.
Figure 4-52. RX L1 to TX L1 Interface

RX L1 TX L1
TX_DATA
FIFO 32 bytes FIFO 64 bytes MII TX port
TX_EN
4.4.6.2.5 PRU R31 Command Interface

The PRU uses writes to R31[31:16] to control the reception and transmission of packets in register mode.
Table 4-36 lists the available commands. Each bit in the table is a single clock pulse output from the PRU.
When more than one action is to be performed in the same instant, the PRU firmware must set those
command bits in one instruction.
Table 4-36. PRU R31: Command Interface (Write Mode)

Bit Command Description
31 TX_CRC_ERR TX_CRC_ERR command when set will add 0xa5 byte to the TX L1
FIFO if the current FCS is valid. This bit can only be set with the
TX_EOF command and optionally with the TX_ERROR_NIBBLE
command. It cannot get set with any other commands. Note for
proper operations auto-forward preamble must be enabled.
30 TX_RESET TX_RESET command is used to reset the transmit FIFO and clear
all its contents. This is required to recover from a TX FIFO overrun.
29 TX_EOF TX_EOF command is used to indicate that the data loaded is
considered last for the current frame
28 TX_ERROR_NIBBLE TX_ERROR_NIBBLE command is used to insert an error nibble.
This makes the frame invalid. Also, it will add 0x0 after the 32-bit
CRC.
27 TX_CRC_HIGH TX_CRC_HIGH command ends the CRC calculations and pushes
CRC[31:16] to append to the outgoing frame in the TX L1 FIFO.
Note TXCRC0/1 will become valid after 6 clock cycles.
26 TX_CRC_LOW TX_CRC_LOW command pushes CRC[15:0] to append to the
outgoing frame in the TX L1 FIFO.
Table 4-36. PRU R31: Command Interface (Write Mode) (continued)

Bit Command Description
25 TX_PUSH16 TX_PUSH16 command applies mask to two bytes from receive path
and transmit. Note TX_PUSH16 needs to occur before TX_POP16
if data is not fully masked. TX CRC requires the data to be valid for
2 clock cycles.
24 TX_PUSH8 TX_PUSH8 command applies mask to one byte from receive path
and transmit. Note TX_PUSH8 needs to occur before TX_POP8 if
data is not fully masked.
23 RX_ ERROR_CLR RX_ERROR_CLR command is used to clear RX_ ERROR indicator
bit by writing 1.
22 RX_EOF_CLR RX_EOF_CLR command is used to clear RX_EOF status indicator
bit by writing 1.
21 RX_SFD_CLR RX_SFD_CLR command is used to clear RX_SFD indicator bit by
writing 1.
20 RX_SOF_CLR RX_SOF_CLR command is used to clear RX_SOF indicator bit by
writing 1.
19 Reserved Reserved
18 RX_RESET RX_RESET is used to reset the receive FIFO and clear all contents.
This is required to recover from a RX FIFO overrun, if software
does not want to undrain. The typical use case is assertion after
RX_EOF. If asserted during an active frame, the following actions
will occur:
1. Terminate the current frame
2. Block/terminate all new data
3. Flush/clear all FIFO elements
4. Cause RX state machine into an idle state
5. Cause EOF event
6. Cause minimum frame error, if you abort before minimum size
reached
17 RX_POP16 RX_POP16 command advances the receive traffic by two bytes.
This is only required when you are using R31 to read the data. After
R31[15:0] is ready to read by PRU, it will set 1 to WORD_RDY, and
the next new data will be allowed to advance. RX_POP16 to
WORD_RDY update has 2 clock cycles latency. Firmware needs to
insure it does not read WORD_RDY/BYTE_RDY until 2 clock cycles
after RX_POP16.
16 RX_POP8 RX_POP8 command advances the receive traffic by one bytes. This
is only required when you are using R31 to read the data. After
R31[7:0] is ready to read by PRU, it will set 1 to BYTE_RDY, and
the next new data will be allowed to advance. RX_POP8 to
BYTE_RDY update has 2 clock cycles latency. Firmware needs to
insure it does not read WORD_RDY/BYTE_RDY until 2 clock cycles
after RX_POP8.
4.4.6.2.6 Other Configuration Options
4.4.6.2.6.1 Nibble and Byte Order

The PRU core is little endian. To support this difference, the MII_RT supports optional nibble swapping on
both the RX and TX side.
On the receive side, the order of the two data bytes in RX R31 and the RX L2 buffer are configurable
through the RX_BYTE_SWAP bit in the RXCFG0/1 registers, as shown in Table 4-37. Note the Nibble0 is
the first nibble received.
Table 4-37. RX Nibble and Byte Order

Configuration Order
RXCFG0/1[RX_BYTE_SWAP] = 0 (default) R31[15:8] / RXL2[15:8] = Byte1{Nibble3,Nibble2}
R31[7:0] / RXL2[7:0] = Byte0{Nibble1,Nibble0}
Table 4-37. RX Nibble and Byte Order (continued)

Configuration Order
RXCFG0/1[RX_BYTE_SWAP] = 1 R31[15:8] / RXL2[15:8] = Byte0{Nibble1,Nibble0}
R31[7:0] / RXL2[7:0] = Byte1{Nibble3,Nibble2}
On the transmit side, the order of the two data bytes and mask bytes in TX R30 are configurable through
the TX_BYTE_SWAP bit in the TXCFG0/1 registers, as shown in Table 4-38. Note the Nibble0 is the first
nibble received.
Table 4-38. TX Nibble and Byte Order

Configuration Order
TXCFG0/1[TX_BYTE_SWAP] = 0 (default) R30[15:8] = Byte1{Nibble3,Nibble2}
R30[7:0] = Byte0{Nibble1,Nibble0}
R30[31:24] = TX_MASK[15:8]
R30[23:16] = TX_MASK[7:0]
TXCFG0/1[TX_BYTE_SWAP] = 1 R30[15:8] = Byte0{Nibble1,Nibble0}
R30[7:0] = Byte1{Nibble3,Nibble2}
R30[31:24] = TX_MASK[7:0]
R30[23:16] = TX_MASK[15:8]
4.4.6.2.6.2 Preamble Source

The MII_RT module has the option to preserve and forward a received preamble in the TX data stream,
use a preamble provided by the PRU, or auto-generate a preamble. These configurations are highlighted
in Table 4-39.
Table 4-39. Preamble Configuration Options

RX_CUT_PREAMBLE Determines whether RX preamble is passed onto RX L1/L2
FIFO
RX_AUTO_FWD_PRE Determines whether RX preamble is automatically passed to TX
L1 FIFO
TX_AUTO_PREAMBLE TX interface logic auto-generates and appends preamble to TX
data stream with the first push of data into the TX L1 FIFO.
Enabling this option fills the TX FIFO with the preamble length,
thus software must consider this to not overrun the TX FIFO.
4.4.6.2.6.3 PRU and MII Port Multiplexer

The MII_RT module supports configurable PRU core to MII TXn / RXn port mapping. By default, PRU0 is
mapped to TX1 and RX0 and PRU1 is mapped to TX0 and RX1. However, the system supports the
flexibility to map any PRU core to any TX and RX port. Note the mapping options are destination fixed.
For example, the input to PRU0 can be either RX_MII0 or RX_MII1. Similarly, the input to TX_MII0 can be
either PRU0 or PRU1.
4.4.6.2.6.3.1 Receive Multiplexer

A multiplexer is provided to allow selecting either of the two MII interfaces for the receive data that is sent
to PRU. Figure 4-53 shows the symbol of receive multiplexer of PRU.
Figure 4-53. MII Receive Multiplexer

RX_DATA[3:0]
RX_MII0
RX_DV RX_DATA[3:0]
RX MII
Multiplexer PRU0/1
RX_DV
RX_DATA[3:0] (PRU0/1)
RX_MII1
RX_DV
There are two receive multiplexer instances to enable selection of RX MII path for each PRU. The select
lines of the RX multiplexers are driven from the PRU-ICSS programmable registers (RXCFG0/1).
4.4.6.2.6.3.2 Transmit Multiplexer

On the MII transmit ports, there is a multiplexer for each MII transmit port that enables selection of either
the transmit data from the PRUs or from the RX MII interface of the other MII interface. Figure 4-54 shows
the symbol of transmit multiplexer of PRU.
Figure 4-54. MII Transmit Multiplexer

TX_DATA[3:0]
TX_PRU0
TX_EN
TX_DATA[3:0]
TX_DATA[3:0]
TX MII
TX_PRU1 TX_EN
TX_EN Multiplexer TX_MII1/0
(Port 0/1)
TX_SOF
TX_DATA[3:0]
RX_MII0/1
TX_EN
The transmit multiplexers enable the PRU-ICSS to either operate in a bypass mode where the PRU is not
involved in processing MII traffic or use of one of the PRU cores for transmitting data into the MII interface.
There are two instances of the TX MII multiplexer and the select lines for each TX multiplexer are
provided by the PRU-ICSS. The select lines are common between register and FIFO interface. It is
expected that the select lines will not change during the course of a frame so that can avoid data
exchange error.
4.4.6.2.6.4 RX L2 Scratch Pad

When the RX L2 is disabled (RXCFG0/1[RX_L2_ENABLE] = 0), the RX L2 banks can be used as a
generic scratch pad. In scrach pad mode, RX L2 Bank0 and RX L2 Bank1 operate like simple write/read
memory mapped registers (MMRs). All XFR size and start operations are supported. RX_RESET has no
effect in this mode. This mode is shown in Figure 4-55.
Figure 4-55. Scratch Pad Mode

RX L2
Bank 0 PRU
32 bytes of data XFR R0
…
Bank 1 R31
32 bytes of data
4.4.7 MDIO
The MDIO module within the PRU-ICSS is identical to the MDIO module in Section 14.3.8.
Registers www.ti.com
4.5 Registers
4.5.1 PRU_ICSS_PRU_CTRL Registers

Table 4-40 lists the memory-mapped registers for the PRU_ICSS_PRU_CTRL. All register offset
addresses not listed in Table 4-40 should be considered as reserved locations and the register contents
should not be modified.
Table 4-40. PRU_ICSS_PRU_CTRL Registers

Offset Acronym Register Name Section
0h CTRL Section 4.5.1.1
4h STS Section 4.5.1.2
8h WAKEUP_EN Section 4.5.1.3
Ch CYCLE Section 4.5.1.4
10h STALL Section 4.5.1.5
20h CTBIR0 Section 4.5.1.6
24h CTBIR1 Section 4.5.1.7
28h CTPPR0 Section 4.5.1.8
2Ch CTPPR1 Section 4.5.1.9
www.ti.com Registers
4.5.1.1 CTRL Register (offset = 0h) [reset = 1h]

CTRL is shown in Figure 4-56 and described in Table 4-41.
CONTROL REGISTER
Figure 4-56. CTRL Register

31 30 29 28 27 26 25 24
PCTR_RST_VAL
R/W-0h
23 22 21 20 19 18 17 16
PCTR_RST_VAL
R/W-0h
15 14 13 12 11 10 9 8
RUNSTATE RESERVED RESERVED SINGLE_STEP
R-0h R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED CTR_EN SLEEPING EN SOFT_RST_N
R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-41. CTRL Register Field Descriptions

Bit Field Type Reset Description
31-16 PCTR_RST_VAL R/W 0h Program Counter Reset Value: This field controls the address where
the PRU will start executing code from after it is taken out of reset.
15 RUNSTATE R 0h Run State: This bit indicates whether the PRU is currently executing
an instruction or is halted.
0 = PRU is halted and host has access to the instruction RAM and
debug registers regions.
1 = PRU is currently running and the host is locked out of the
instruction RAM and debug registers regions.
This bit is used by an external debug agent to know when the PRU
has actually halted when waiting for a HALT instruction to execute, a
single step to finish, or any other time when the pru_enable has
been cleared.
14 RESERVED R 0h Reserved.
13-9 RESERVED R/W 0h
8 SINGLE_STEP R/W 0h Single Step Enable: This bit controls whether or not the PRU will
only execute a single instruction when enabled.
0 = PRU will free run when enabled.
1 = PRU will execute a single instruction and then the pru_enable bit
will be cleared.
Note that this bit does not actually enable the PRU, it only sets the
policy for how much code will be run after the PRU is enabled.
The pru_enable bit must be explicitly asserted.
It is legal to initialize both the single_step and pru_enable bits
simultaneously.
(Two independent writes are not required to cause the stated
functionality.)
7-4 RESERVED R/W 0h
3 CTR_EN R/W 0h PRU Cycle Counter Enable: Enables PRU cycle counters.
0 = Counters not enabled
1 = Counters enabled
2 SLEEPING R/W 0h PRU Sleep Indicator: This bit indicates whether or not the PRU is
currently asleep.
0 = PRU is not asleep
1 = PRU is asleep If this bit is written to a 0, the PRU will be forced
to power up from sleep mode.
Table 4-41. CTRL Register Field Descriptions (continued)

1 EN R/W 0h Processor Enable: This bit controls whether or not the PRU is
allowed to fetch new instructions.
0 = PRU is disabled.
1 = PRU is enabled.
If this bit is de-asserted while the PRU is currently running and has
completed the initial cycle of a multi-cycle instruction
(LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to
complete before the PRU pauses execution.
Otherwise, the PRU will halt immediately.
Because of the unpredictability/timing sensitivity of the instruction
execution loop, this bit is not a reliable indication of whether or not
the PRU is currently running.
The pru_state bit should be consulted for an absolute indication of
the run state of the core.
When the PRU is halted, its internal state remains coherent therefore
this bit can be reasserted without issuing a software reset and the
PRU will resume processing exactly where it left off in the instruction
stream.
0 SOFT_RST_N R/W 1h Soft Reset: When this bit is cleared, the PRU will be reset.
This bit is set back to 1 on the next cycle after it has been cleared.
4.5.1.2 STS Register (offset = 4h) [reset = 0h]

STS is shown in Figure 4-57 and described in Table 4-42.
STATUS REGISTER
Figure 4-57. STS Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PCTR
R-0h R-0h
Table 4-42. STS Register Field Descriptions

31-16 RESERVED R 0h
15-0 PCTR R 0h Program Counter: This field is a registered (1 cycle delayed)
reflection of the PRU program counter.
Note that the PC is an instruction address where each instruction is
a 32 bit word.
This is not a byte address and to compute the byte address just
multiply the PC by 4 (PC of
2 = byte address of 0x8, or PC of
8 = byte address of 0x20).
4.5.1.3 WAKEUP_EN Register (offset = 8h) [reset = 0h]

WAKEUP_EN is shown in Figure 4-58 and described in Table 4-43.
WAKEUP ENABLE REGISTER
Figure 4-58. WAKEUP_EN Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITWISE_ENS
R/W-0h
Table 4-43. WAKEUP_EN Register Field Descriptions

31-0 BITWISE_ENS R/W 0h Wakeup Enables: This field is ANDed with the incoming R31 status
inputs (whose bit positions were specified in the stmap parameter) to
produce a vector which is unary ORed to produce the
status_wakeup source for the core.
Setting any bit in this vector will allow the corresponding status input
to wake up the core when it is asserted high.
The PRU should set this enable vector prior to executing a SLP
(sleep) instruction to ensure that the desired sources can wake up
the core.
4.5.1.4 CYCLE Register (offset = Ch) [reset = 0h]

CYCLE is shown in Figure 4-59 and described in Table 4-44.
CYCLE COUNT. This register counts the number of cycles for which the PRU has been enabled.
Figure 4-59. CYCLE Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CYCLECOUNT
0h
Table 4-44. CYCLE Register Field Descriptions

31-0 CYCLECOUNT 0h This value is incremented by 1 for every cycle during which the PRU
is enabled and the counter is enabled (both bits EN and CTR_EN
set in the PRU control register).
Counting halts while the PRU is disabled or counter is disabled, and
resumes when re-eneabled.
Counter clears the CTR_EN bit in the PRU control register when the
count reaches 0xFFFFFFFF.
(Count does does not wrap).
The register can be read at any time.
The register can be cleared when the counter or PRU is disabled.
Clearing this register also clears the PRU Stall Count Register.
4.5.1.5 STALL Register (offset = 10h) [reset = 0h]

STALL is shown in Figure 4-60 and described in Table 4-45.
STALL COUNT. This register counts the number of cycles for which the PRU has been enabled, but
unable to fetch a new instruction. It is linked to the Cycle Count Register (0x0C) such that this register
reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the
value of this register is always less than or equal to cycle count.
Figure 4-60. STALL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STALLCOUNT
0h
Table 4-45. STALL Register Field Descriptions

31-0 STALLCOUNT 0h This value is incremented by 1 for every cycle during which the PRU
is enabled and the counter is enabled (both bits EN and CTR_EN
set in the PRU control register), and the PRU was unable to fetch a
new instruction for any reason.
4.5.1.6 CTBIR0 Register (offset = 20h) [reset = 0h]

CTBIR0 is shown in Figure 4-61 and described in Table 4-46.
CONSTANT TABLE BLOCK INDEX REGISTER 0. This register is used to set the block indices which are
used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU
whenever it needs to change to a new base pointer for a block in the State / Scratchpad RAM. This
function is useful since the PRU is often processing multiple processing threads which require it to change
contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive
context switching. The format of this register is as follows:
Figure 4-61. CTBIR0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED C25_BLK_IDX
R/W-0h R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W-0h R/W-0h
Table 4-46. CTBIR0 Register Field Descriptions

23-16 C25_BLK_IDX R/W 0h PRU Constant Entry 25 Block Index: This field sets the value that will
appear in bits
11:8 of entry 25 in the PRU Constant Table.
appear in bits
4.5.1.7 CTBIR1 Register (offset = 24h) [reset = 0h]

CTBIR1 is shown in Figure 4-62 and described in Table 4-47.
CONSTANT TABLE BLOCK INDEX REGISTER 1. This register is used to set the block indices which are
used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU
whenever it needs to change to a new base pointer for a block in the State / Scratchpad RAM. This
function is useful since the PRU is often processing multiple processing threads which require it to change
contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive
context switching. The format of this register is as follows:
Figure 4-62. CTBIR1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W-0h R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W-0h R/W-0h
Table 4-47. CTBIR1 Register Field Descriptions

appear in bits
appear in bits
4.5.1.8 CTPPR0 Register (offset = 28h) [reset = 0h]

CTPPR0 is shown in Figure 4-63 and described in Table 4-48.
CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 0. This register allows the PRU to set up
the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose
pointers which can be configured to point to any locations inside the session router address map. This
register is useful when the PRU needs to frequently access certain structures inside the session router
address space whose locations are not hard coded such as tables in scratchpad memory. This register is
formatted as follows:
Figure 4-63. CTPPR0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C29_POINTER C28_POINTER
R/W-0h R/W-0h
Table 4-48. CTPPR0 Register Field Descriptions

31-16 C29_POINTER R/W 0h PRU Constant Entry 29 Pointer: This field sets the value that will
appear in bits
appear in bits
4.5.1.9 CTPPR1 Register (offset = 2Ch) [reset = 0h]

CTPPR1 is shown in Figure 4-64 and described in Table 4-49.
CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 1. This register functions the same as the
PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in
the PRU Constant Table. This register is formatted as follows:
Figure 4-64. CTPPR1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C31_POINTER C30_POINTER
R/W-0h R/W-0h
Table 4-49. CTPPR1 Register Field Descriptions

appear in bits
appear in bits
4.5.2 PRU_ICSS_PRU_DEBUG Registers

Table 4-50 lists the memory-mapped registers for the PRU_ICSS_PRU_DEBUG. All register offset
addresses not listed in Table 4-50 should be considered as reserved locations and the register contents
should not be modified.
Table 4-50. PRU_ICSS_PRU_DEBUG Registers

0h GPREG0 Section 4.5.2.1
Ch GPREG3 Section 4.5.2.4
1Ch GPREG7 Section 4.5.2.8
Table 4-50. PRU_ICSS_PRU_DEBUG Registers (continued)

80h CT_REG0 Section 4.5.2.33
8Ch CT_REG3 Section 4.5.2.36
9Ch CT_REG7 Section 4.5.2.40
A0h CT_REG8 Section 4.5.2.41
ACh CT_REG11 Section 4.5.2.44
B0h CT_REG12 Section 4.5.2.45
BCh CT_REG15 Section 4.5.2.48
C0h CT_REG16 Section 4.5.2.49
CCh CT_REG19 Section 4.5.2.52
D0h CT_REG20 Section 4.5.2.53
DCh CT_REG23 Section 4.5.2.56
E0h CT_REG24 Section 4.5.2.57
ECh CT_REG27 Section 4.5.2.60
F0h CT_REG28 Section 4.5.2.61
FCh CT_REG31 Section 4.5.2.64
4.5.2.1 GPREG0 Register (offset = 0h) [reset = 0h]

GPREG0 is shown in Figure 4-65 and described in Table 4-51.
DEBUG PRU GENERAL PURPOSE REGISTER 0. This register allows an external agent to debug the
PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write
to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse
outputs whenever the register is written.
Figure 4-65. GPREG0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG0
R/W-0h
Table 4-51. GPREG0 Register Field Descriptions

31-0 GP_REG0 R/W 0h PRU Internal GP Register n: Reading / writing this field directly
inspects/modifies the corresponding internal register in the PRU
internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG1
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG2
R/W-0h

internal regfile.
4.5.2.4 GPREG3 Register (offset = Ch) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG3
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG4
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG5
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG6
R/W-0h

internal regfile.
4.5.2.8 GPREG7 Register (offset = 1Ch) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG7
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG8
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG9
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG10
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG11
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG12
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG13
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG14
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG15
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG16
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG17
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG18
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG19
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG20
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG21
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG22
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG23
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG24
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG25
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG26
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG27
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG28
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG29
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG30
R/W-0h

internal regfile.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP_REG31
R/W-0h

31-0 GP_REG31 R/W 0h
4.5.2.33 CT_REG0 Register (offset = 80h) [reset = 20000h]

CT_REG0 is shown in Figure 4-97 and described in Table 4-83.
DEBUG PRU CONSTANTS TABLE ENTRY 0. This register allows an external agent to debug the PRU
while it is disabled. Since some of the constants table entries may actually depend on system inputs / and
or the internal state of the PRU, these registers are provided to allow an external agent to easily
determine the state of the constants table.
Figure 4-97. CT_REG0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG0
R-20000h
Table 4-83. CT_REG0 Register Field Descriptions

31-0 CT_REG0 R 20000h PRU Internal Constants Table Entry n: Reading this field directly
inspects the corresponding entry in the PRU internal constants table.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG1
R-48040000h

4.5.2.35 CT_REG2 Register (offset = 88h) [reset = 4802A000h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG2
R-4802A000h

31-0 CT_REG2 R 4802A000h PRU Internal Constants Table Entry n: Reading this field directly
4.5.2.36 CT_REG3 Register (offset = 8Ch) [reset = 30000h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG3
R-30000h



31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG4
R-26000h



31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG5
R-48060000h



31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG6
R-48030000h

4.5.2.40 CT_REG7 Register (offset = 9Ch) [reset = 28000h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG7
R-28000h

4.5.2.41 CT_REG8 Register (offset = A0h) [reset = 46000000h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG8
R-46000000h

4.5.2.42 CT_REG9 Register (offset = A4h) [reset = 4A100000h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG9
R-4A100000h

4.5.2.43 CT_REG10 Register (offset = A8h) [reset = 48318000h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG10
R-48318000h

4.5.2.44 CT_REG11 Register (offset = ACh) [reset = 48022000h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG11
R-48022000h

4.5.2.45 CT_REG12 Register (offset = B0h) [reset = 48024000h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG12
R-48024000h

4.5.2.46 CT_REG13 Register (offset = B4h) [reset = 48310000h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG13
R-48310000h

4.5.2.47 CT_REG14 Register (offset = B8h) [reset = 481CC000h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG14
R-481CC000h

31-0 CT_REG14 R 481CC000h PRU Internal Constants Table Entry n: Reading this field directly
4.5.2.48 CT_REG15 Register (offset = BCh) [reset = 481D0000h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG15
R-481D0000h

31-0 CT_REG15 R 481D0000h PRU Internal Constants Table Entry n: Reading this field directly
4.5.2.49 CT_REG16 Register (offset = C0h) [reset = 481A0000h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG16
R-481A0000h

4.5.2.50 CT_REG17 Register (offset = C4h) [reset = 4819C000h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG17
R-4819C000h

31-0 CT_REG17 R 4819C000h PRU Internal Constants Table Entry n: Reading this field directly
4.5.2.51 CT_REG18 Register (offset = C8h) [reset = 48300000h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG18
R-48300000h

4.5.2.52 CT_REG19 Register (offset = CCh) [reset = 48302000h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG19
R-48302000h

4.5.2.53 CT_REG20 Register (offset = D0h) [reset = 48304000h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG20
R-48304000h

4.5.2.54 CT_REG21 Register (offset = D4h) [reset = 32400h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG21
R-32400h

4.5.2.55 CT_REG22 Register (offset = D8h) [reset = 480C8000h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG22
R-480C8000h

31-0 CT_REG22 R 480C8000h PRU Internal Constants Table Entry n: Reading this field directly
4.5.2.56 CT_REG23 Register (offset = DCh) [reset = 480CA000h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG23
R-480CA000h

31-0 CT_REG23 R 480CA000h PRU Internal Constants Table Entry n: Reading this field directly
4.5.2.57 CT_REG24 Register (offset = E0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG24
R-0h

This entry is partially programmable through the C24_BLK_INDEX in
the PRU Control register.
The reset value for this Constant Table Entry is 0x00000n00,
n=C24_BLK_INDEX[3:0].


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG25
R-0h



31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG26
R-0h

The reset value for this Constant Table Entry is 0x0002En00,
4.5.2.60 CT_REG27 Register (offset = ECh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG27
R-0h

4.5.2.61 CT_REG28 Register (offset = F0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG28
R-0h

This entry is partially programmable through the C28_POINTER in
The reset value for this Constant Table Entry is 0x00nnnn00,
nnnn=C28_POINTER[15:0].


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG29
R-0h



31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG30
R-0h

4.5.2.64 CT_REG31 Register (offset = FCh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT_REG31
R-0h

4.5.3 PRU_ICSS_INTC Registers

Table 4-115 lists the memory-mapped registers for the PRU_ICSS_INTC. All register offset addresses not
listed in Table 4-115 should be considered as reserved locations and the register contents should not be
modified.
Table 4-115. PRU_ICSS_INTC Registers

0h REVID Section 4.5.3.1
4h CR Section 4.5.3.2
10h GER Section 4.5.3.3
1Ch GNLR Section 4.5.3.4
20h SISR Section 4.5.3.5
24h SICR Section 4.5.3.6
28h EISR Section 4.5.3.7
2Ch EICR Section 4.5.3.8
34h HIEISR Section 4.5.3.9
38h HIDISR Section 4.5.3.10
80h GPIR Section 4.5.3.11
200h SRSR0 Section 4.5.3.12
204h SRSR1 Section 4.5.3.13
280h SECR0 Section 4.5.3.14
284h SECR1 Section 4.5.3.15
300h ESR0 Section 4.5.3.16
304h ESR1 Section 4.5.3.17
380h ECR0 Section 4.5.3.18
384h ECR1 Section 4.5.3.19
400h CMR0 Section 4.5.3.20
Table 4-115. PRU_ICSS_INTC Registers (continued)

40Ch CMR3 Section 4.5.3.23
800h HMR0 Section 4.5.3.36
900h HIPIR0 Section 4.5.3.39
90Ch HIPIR3 Section 4.5.3.42
91Ch HIPIR7 Section 4.5.3.46
D00h SIPR0 Section 4.5.3.49
D04h SIPR1 Section 4.5.3.50
D80h SITR0 Section 4.5.3.51
D84h SITR1 Section 4.5.3.52
1100h HINLR0 Section 4.5.3.53
110Ch HINLR3 Section 4.5.3.56
111Ch HINLR7 Section 4.5.3.60
1500h HIER Section 4.5.3.63
4.5.3.1 REVID Register (offset = 0h) [reset = 4E82A900h]

REVID is shown in Figure 4-129 and described in Table 4-116.
Revision ID Register
Figure 4-129. REVID Register

31 30 29 28 27 26 25 24
REV_SCHEME RESERVED REV_MODULE
R-1h R-0h R-E82h
23 22 21 20 19 18 17 16
REV_MODULE
R-E82h
15 14 13 12 11 10 9 8
REV_RTL REV_MAJOR
R-15h R-1h
7 6 5 4 3 2 1 0
REV_CUSTOM REV_MINOR
R-0h R-0h
Table 4-116. REVID Register Field Descriptions

31-30 REV_SCHEME R 1h SCHEME
29-28 RESERVED R 0h
27-16 REV_MODULE R E82h MODULE ID
15-11 REV_RTL R 15h RTL REVISIONS
10-8 REV_MAJOR R 1h MAJOR REVISION
7-6 REV_CUSTOM R 0h CUSTOM REVISION
5-0 REV_MINOR R 0h MINOR REVISION
4.5.3.2 CR Register (offset = 4h) [reset = 0h]

CR is shown in Figure 4-130 and described in Table 4-117.
The Control Register holds global control parameters and can forces a soft reset on the module.
Figure 4-130. CR Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED NEST_MODE RESERVED RESERVED
R/W-0h R-0h R/W-0h R/W-0h R/W-0h
Table 4-117. CR Register Field Descriptions

4 RESERVED R 0h Reserved.
3-2 NEST_MODE R/W 0h The nesting mode.
0 = no nesting
1 = automatic individual nesting (per host interrupt)
2 = automatic global nesting (over all host interrupts)
3 = manual nesting
1 RESERVED R/W 0h Reserved.
0 RESERVED R/W 0h
4.5.3.3 GER Register (offset = 10h) [reset = 0h]

GER is shown in Figure 4-131 and described in Table 4-118.
The Global Host Interrupt Enable Register enables all the host interrupts. Individual host interrupts are still
enabled or disabled from their individual enables and are not overridden by the global enable.
Figure 4-131. GER Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED EN_HINT_ANY
R/W-0h R/W-0h
Table 4-118. GER Register Field Descriptions

0 EN_HINT_ANY R/W 0h The current global enable value when read.
Writes set the global enable.
4.5.3.4 GNLR Register (offset = 1Ch) [reset = 100h]

GNLR is shown in Figure 4-132 and described in Table 4-119.
The Global Nesting Level Register allows the checking and setting of the global nesting level across all
host interrupts when automatic global nesting mode is set. The nesting level is the channel (and all of
lower priority) that are nested out because of a current interrupt. This register is only available when
nesting is configured.
Figure 4-132. GNLR Register

31 30 29 28 27 26 25 24
AUTO_OVERR RESERVED
IDE
W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED GLB_NEST_LE
VEL
R/W-0h R/W-100h
7 6 5 4 3 2 1 0
GLB_NEST_LEVEL
R/W-100h
Table 4-119. GNLR Register Field Descriptions

31 AUTO_OVERRIDE W 0h Always read as 0.
Writes of 1 override the automatic nesting and set the nesting_level
to the written data.
8-0 GLB_NEST_LEVEL R/W 100h The current global nesting level (highest channel that is nested).
Writes set the nesting level.
In auto nesting mode this value is updated internally unless the
auto_override bit is set.
4.5.3.5 SISR Register (offset = 20h) [reset = 0h]

SISR is shown in Figure 4-133 and described in Table 4-120.
The System Event Status Indexed Set Register allows setting the status of an event. The event to set is
the index value written (0-63). This sets the Raw Status Register bit of the given index.
Figure 4-133. SISR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED STS_SET_IDX
W-0h W-0h
Table 4-120. SISR Register Field Descriptions

31-10 RESERVED W 0h
9-0 STS_SET_IDX W 0h Writes set the status of the event given in the index value (
0-63).
Reads return 0.
4.5.3.6 SICR Register (offset = 24h) [reset = 0h]

SICR is shown in Figure 4-134 and described in Table 4-121.
The System Event Status Indexed Clear Register allows clearing the status of an event. The event to clear
is the index value written (0-63). This clears the Raw Status Register bit of the given index.
Figure 4-134. SICR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED STS_CLR_IDX
W-0h W-0h
Table 4-121. SICR Register Field Descriptions

31-10 RESERVED W 0h
9-0 STS_CLR_IDX W 0h Writes clear the status of the event given in the index value (
0-63).
Reads return 0.
4.5.3.7 EISR Register (offset = 28h) [reset = 0h]

EISR is shown in Figure 4-135 and described in Table 4-122.
The System Event Enable Indexed Set Register allows enabling an event. The event to enable is the
index value written (0-63). This sets the Enable Register bit of the given index.
Figure 4-135. EISR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED EN_SET_IDX
W-0h W-0h
Table 4-122. EISR Register Field Descriptions

31-10 RESERVED W 0h
9-0 EN_SET_IDX W 0h Writes set the enable of the event given in the index value (
0-63).
Reads return 0.
4.5.3.8 EICR Register (offset = 2Ch) [reset = 0h]

EICR is shown in Figure 4-136 and described in Table 4-123.
The System Event Enable Indexed Clear Register allows disabling an event. The event to disable is the
index value written (0-63). This clears the Enable Register bit of the given index.
Figure 4-136. EICR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED EN_CLR_IDX
W-0h W-0h
Table 4-123. EICR Register Field Descriptions

31-10 RESERVED W 0h
9-0 EN_CLR_IDX W 0h Writes clear the enable of the event given in the index value (
0-63).
Reads return 0.
4.5.3.9 HIEISR Register (offset = 34h) [reset = 0h]

HIEISR is shown in Figure 4-137 and described in Table 4-124.
The Host Interrupt Enable Indexed Set Register allows enabling a host interrupt output. The host interrupt
to enable is the index value written (0-9). This enables the host interrupt output or triggers the output
again if already enabled.
Figure 4-137. HIEISR Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED HINT_EN_SET_IDX
R/W-0h R/W-0h
Table 4-124. HIEISR Register Field Descriptions

3-0 HINT_EN_SET_IDX R/W 0h Writes set the enable of the host interrupt given in the index value (
0-9).
Reads return 0.
4.5.3.10 HIDISR Register (offset = 38h) [reset = 0h]

HIDISR is shown in Figure 4-138 and described in Table 4-125.
The Host Interrupt Enable Indexed Clear Register allows disabling a host interrupt output. The host
interrupt to disable is the index value written (0-9). This disables the host interrupt output.
Figure 4-138. HIDISR Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED HINT_EN_CLR_IDX
R/W-0h R/W-0h
Table 4-125. HIDISR Register Field Descriptions

3-0 HINT_EN_CLR_IDX R/W 0h Writes clear the enable of the host interrupt given in the index value (
0-9).
Reads return 0.
4.5.3.11 GPIR Register (offset = 80h) [reset = 80000000h]

GPIR is shown in Figure 4-139 and described in Table 4-126.
The Global Prioritized Index Register shows the event number of the highest priority event pending across
all the host interrupts.
Figure 4-139. GPIR Register

31 30 29 28 27 26 25 24
GLB_NONE RESERVED
R-1h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED GLB_PRI_INTR
R-0h R-0h
7 6 5 4 3 2 1 0
GLB_PRI_INTR
R-0h
Table 4-126. GPIR Register Field Descriptions

31 GLB_NONE R 1h No Interrupt is pending.
Can be used by host to test for a negative value to see if no
interrupts are pending.
30-10 RESERVED R 0h
9-0 GLB_PRI_INTR R 0h The currently highest priority event index (
0-63) pending across all the host interrupts.
4.5.3.12 SRSR0 Register (offset = 200h) [reset = 0h]

SRSR0 is shown in Figure 4-140 and described in Table 4-127.
The System Event Status Raw/Set Register0 show the pending enabled status of the system events 0 to
31. Software can write to the Status Set Registers to set a system event without a hardware trigger. There
is one bit per system event
Figure 4-140. SRSR0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAW_STS_31_0
R/W-0h
Table 4-127. SRSR0 Register Field Descriptions

31-0 RAW_STS_31_0 R/W 0h System event raw status and setting of the system events 0 to 31.
Reads return the raw status.
Write a 1 in a bit position to set the status of the system event.
Writing a 0 has no effect.
4.5.3.13 SRSR1 Register (offset = 204h) [reset = 0h]

SRSR1 is shown in Figure 4-141 and described in Table 4-128.
The System Event Status Raw/Set Register1 show the pending enabled status of the system events 32 to
63. Software can write to the Status Set Registers to set a system event without a hardware trigger. There
is one bit per system event
Figure 4-141. SRSR1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAW_STS_63_32
R/W-0h
Table 4-128. SRSR1 Register Field Descriptions

31-0 RAW_STS_63_32 R/W 0h System event raw status and setting of the system events 32 to 63.
Reads return the raw status.
Write a 1 in a bit position to set the status of the system event.
4.5.3.14 SECR0 Register (offset = 280h) [reset = 0h]

SECR0 is shown in Figure 4-142 and described in Table 4-129.
The System Event Status Enabled/Clear Register0 show the pending enabled status of the system events
0 to 31. Software can write to the Status Clear Registers to clear a system event after it has been
serviced. If a system event status is not cleared then another host interrupt may not be triggered or
another host interrupt may be triggered incorrectly. There is one bit per system event.
Figure 4-142. SECR0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENA_STS_31_0
R/W-0h
Table 4-129. SECR0 Register Field Descriptions

31-0 ENA_STS_31_0 R/W 0h System event enabled status and clearing of the system events 0 to
31.
Reads return the enabled status (before enabling with the Enable
Registers).
Write a 1 in a bit position to clear the status of the system event.
4.5.3.15 SECR1 Register (offset = 284h) [reset = 0h]

SECR1 is shown in Figure 4-143 and described in Table 4-130.
The System Event Status Enabled/Clear Register1 show the pending enabled status of the system events
32 to 63. Software can write to the Status Clear Registers to clear a system event after it has been
serviced. If a system event status is not cleared then another host interrupt may not be triggered or
another host interrupt may be triggered incorrectly. There is one bit per system event.
Figure 4-143. SECR1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENA_STS_63_32
R/W-0h
Table 4-130. SECR1 Register Field Descriptions

31-0 ENA_STS_63_32 R/W 0h System event enabled status and clearing of the system events 32
to 63.
Reads return the enabled status (before enabling with the Enable
Registers).
Write a 1 in a bit position to clear the status of the system event.
4.5.3.16 ESR0 Register (offset = 300h) [reset = 0h]

ESR0 is shown in Figure 4-144 and described in Table 4-131.
The System Event Enable Set Register0 enables system events 0 to 31 to trigger outputs. System events
that are not enabled do not interrupt the host. There is a bit per system event.
Figure 4-144. ESR0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_SET_31_0
0h
Table 4-131. ESR0 Register Field Descriptions

31-0 EN_SET_31_0 0h System event enables system events 0 to 31.
Read returns the enable value (
0 = disabled,
1 = enabled).
Write a 1 in a bit position to set that enable.
4.5.3.17 ESR1 Register (offset = 304h) [reset = 0h]

ESR1 is shown in Figure 4-145 and described in Table 4-132.
The System Event Enable Set Register1 enables system events 32 to 63 to trigger outputs. System
events that are not enabled do not interrupt the host. There is a bit per system event.
Figure 4-145. ESR1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_SET_63_32
0h
Table 4-132. ESR1 Register Field Descriptions

31-0 EN_SET_63_32 0h System event enables system events 32 to 63.
0 = disabled,
1 = enabled).
Write a 1 in a bit position to set that enable.
4.5.3.18 ECR0 Register (offset = 380h) [reset = 0h]

ECR0 is shown in Figure 4-146 and described in Table 4-133.
The System Event Enable Clear Register0 disables system events 0 to 31 to map to channels. System
Figure 4-146. ECR0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_CLR_31_0
0h
Table 4-133. ECR0 Register Field Descriptions

31-0 EN_CLR_31_0 0h System event enables system events 0 to 31.
0 = disabled,
1 = enabled).
Write a 1 in a bit position to clear that enable.
4.5.3.19 ECR1 Register (offset = 384h) [reset = 0h]

ECR1 is shown in Figure 4-147 and described in Table 4-134.
The System Event Enable Clear Register1 disables system events 32 to 63 to map to channels. System
Figure 4-147. ECR1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_CLR_63_32
0h
Table 4-134. ECR1 Register Field Descriptions

31-0 EN_CLR_63_32 0h System event enables system events 32 to 63.
0 = disabled,
1 = enabled).
Write a 1 in a bit position to clear that enable.
4.5.3.20 CMR0 Register (offset = 400h) [reset = 0h]

CMR0 is shown in Figure 4-148 and described in Table 4-135.
The Channel Map Register0 specify the channel for the system events 0 to 3. There is one register per 4
system events. Note each CH_MAP_x bitfield corresponds to a system event. Channel numbers (0-9)
should be written to these bitfields.
Figure 4-148. CMR0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED CH_MAP_3 RESERVED CH_MAP_2
R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Table 4-135. CMR0 Register Field Descriptions

27-24 CH_MAP_3 R/W 0h Sets the channel for the system event 3
7-4 RESERVED R/W 0h

system events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7-4 RESERVED R/W 0h

system events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7-4 RESERVED R/W 0h
4.5.3.23 CMR3 Register (offset = 40Ch) [reset = 0h]

The Channel Map Register3 specify the channel for the system events 12 to 15. There is one register per
4 system events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7-4 RESERVED R/W 0h

4 system events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7-4 RESERVED R/W 0h

4 system events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7-4 RESERVED R/W 0h

4 system events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7-4 RESERVED R/W 0h

4 system events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7-4 RESERVED R/W 0h

4 system events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7-4 RESERVED R/W 0h

4 system events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7-4 RESERVED R/W 0h

The Channel Map Register10 specify the channel for the system events 40 to 43. There is one register
per 4 system events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7-4 RESERVED R/W 0h


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7-4 RESERVED R/W 0h


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7-4 RESERVED R/W 0h


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7-4 RESERVED R/W 0h


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7-4 RESERVED R/W 0h


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7-4 RESERVED R/W 0h
4.5.3.36 HMR0 Register (offset = 800h) [reset = 0h]

HMR0 is shown in Figure 4-164 and described in Table 4-151.
The Host Interrupt Map Register0 define the host interrupt for channels 0 to 3. There is one register per 4
channels. Channels with forced host interrupt mappings will have their fields read-only.
Figure 4-164. HMR0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED HINT_MAP_3 RESERVED HINT_MAP_2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Table 4-151. HMR0 Register Field Descriptions

27-24 HINT_MAP_3 R/W 0h HOST INTERRUPT MAP FOR CHANNEL 3
7-4 RESERVED R/W 0h


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7-4 RESERVED R/W 0h


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7-4 RESERVED R/W 0h
4.5.3.39 HIPIR0 Register (offset = 900h) [reset = 80000000h]

HIPIR0 is shown in Figure 4-167 and described in Table 4-154.
The Host Interrupt Prioritized Index Register0 shows the highest priority current pending interrupt for the
host interrupt 0. There is one register per host interrupt.
Figure 4-167. HIPIR0 Register

31 30 29 28 27 26 25 24
NONE_HINT_0 RESERVED
R-1h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED PRI_HINT_0
R-0h R-0h
7 6 5 4 3 2 1 0
PRI_HINT_0
R-0h
Table 4-154. HIPIR0 Register Field Descriptions

31 NONE_HINT_0 R 1h No pending interrupt.
30-10 RESERVED R 0h
9-0 PRI_HINT_0 R 0h HOST INT 0 PRIORITIZED INTERRUPT.
Interrupt number of the highest priority pending interrupt for this host
interrupt.


31 30 29 28 27 26 25 24
R-1h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED PRI_HINT_1
R-0h R-0h
7 6 5 4 3 2 1 0
PRI_HINT_1
R-0h

30-10 RESERVED R 0h
interrupt.


31 30 29 28 27 26 25 24
R-1h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED PRI_HINT_2
R-0h R-0h
7 6 5 4 3 2 1 0
PRI_HINT_2
R-0h

30-10 RESERVED R 0h
interrupt.
4.5.3.42 HIPIR3 Register (offset = 90Ch) [reset = 80000000h]


31 30 29 28 27 26 25 24
R-1h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED PRI_HINT_3
R-0h R-0h
7 6 5 4 3 2 1 0
PRI_HINT_3
R-0h

30-10 RESERVED R 0h
interrupt.


31 30 29 28 27 26 25 24
R-1h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED PRI_HINT_4
R-0h R-0h
7 6 5 4 3 2 1 0
PRI_HINT_4
R-0h

30-10 RESERVED R 0h
interrupt.


31 30 29 28 27 26 25 24
R-1h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED PRI_HINT_5
R-0h R-0h
7 6 5 4 3 2 1 0
PRI_HINT_5
R-0h

30-10 RESERVED R 0h
interrupt.


31 30 29 28 27 26 25 24
R-1h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED PRI_HINT_6
R-0h R-0h
7 6 5 4 3 2 1 0
PRI_HINT_6
R-0h

30-10 RESERVED R 0h
interrupt.
4.5.3.46 HIPIR7 Register (offset = 91Ch) [reset = 80000000h]


31 30 29 28 27 26 25 24
R-1h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED PRI_HINT_7
R-0h R-0h
7 6 5 4 3 2 1 0
PRI_HINT_7
R-0h

30-10 RESERVED R 0h
interrupt.


31 30 29 28 27 26 25 24
R-1h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED PRI_HINT_8
R-0h R-0h
7 6 5 4 3 2 1 0
PRI_HINT_8
R-0h

30-10 RESERVED R 0h
interrupt.


31 30 29 28 27 26 25 24
R-1h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED PRI_HINT_9
R-0h R-0h
7 6 5 4 3 2 1 0
PRI_HINT_9
R-0h

30-10 RESERVED R 0h
interrupt.
4.5.3.49 SIPR0 Register (offset = D00h) [reset = 1h]

SIPR0 is shown in Figure 4-177 and described in Table 4-164.
The System Event Polarity Register0 define the polarity of the system events 0 to 31. There is a polarity
for each system event. The polarity of all system events is active high; always write 1 to the bits of this
register.
Figure 4-177. SIPR0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POLARITY_31_0
R/W-1h
Table 4-164. SIPR0 Register Field Descriptions

31-0 POLARITY_31_0 R/W 1h Interrupt polarity of the system events 0 to 31.
0 = active low.
1 = active high.
4.5.3.50 SIPR1 Register (offset = D04h) [reset = 1h]

SIPR1 is shown in Figure 4-178 and described in Table 4-165.
The System Event Polarity Register1 define the polarity of the system events 32 to 63. There is a polarity
for each system event. The polarity of all system events is active high; always write 1 to the bits of this
register.
Figure 4-178. SIPR1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POLARITY_63_32
R/W-1h
Table 4-165. SIPR1 Register Field Descriptions

31-0 POLARITY_63_32 R/W 1h Interrupt polarity of the system events 32 to 63.
0 = active low.
1 = active high.
4.5.3.51 SITR0 Register (offset = D80h) [reset = 0h]

SITR0 is shown in Figure 4-179 and described in Table 4-166.
The System Event Type Register0 define the type of the system events 0 to 31. There is a type for each
system event. The type of all system events is pulse; always write 0 to the bits of this register.
Figure 4-179. SITR0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TYPE_31_0
R/W-0h
Table 4-166. SITR0 Register Field Descriptions

31-0 TYPE_31_0 R/W 0h Interrupt type of the system events 0 to 31.
0 = level or pulse interrupt.
1 = edge interrupt (required edge detect).
4.5.3.52 SITR1 Register (offset = D84h) [reset = 0h]

SITR1 is shown in Figure 4-180 and described in Table 4-167.
The System Event Type Register1 define the type of the system events 32 to 63. There is a type for each
system event. The type of all system events is pulse; always write 0 to the bits of this register.
Figure 4-180. SITR1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TYPE_63_32
R/W-0h
Table 4-167. SITR1 Register Field Descriptions

31-0 TYPE_63_32 R/W 0h Interrupt type of the system events 32 to 63.
0 = level or pulse interrupt.
1 = edge interrupt (required edge detect).
4.5.3.53 HINLR0 Register (offset = 1100h) [reset = 100h]

HINLR0 is shown in Figure 4-181 and described in Table 4-168.
The Host Interrupt Nesting Level Register0 display and control the nesting level for host interrupt 0. The
nesting level controls which channel and lower priority channels are nested. There is one register per host
interrupt.
Figure 4-181. HINLR0 Register

31 30 29 28 27 26 25 24
AUTO_OVERR RESERVED
IDE
W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED NEST_HINT_0
R/W-0h R/W-100h
7 6 5 4 3 2 1 0
NEST_HINT_0
R/W-100h
Table 4-168. HINLR0 Register Field Descriptions

31 AUTO_OVERRIDE W 0h Reads return 0.
Writes of a 1 override the auto updating of the nesting_level and use
the write data.
8-0 NEST_HINT_0 R/W 100h Reads return the current nesting level for the host interrupt.
Writes set the nesting level for the host interrupt.
In auto mode the value is updated internally unless the
auto_override is set and then the write data is used.

interrupt.

31 30 29 28 27 26 25 24
AUTO_OVERR RESERVED
IDE
W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
R/W-0h R/W-100h
7 6 5 4 3 2 1 0
NEST_HINT_1
R/W-100h

the write data.

interrupt.

31 30 29 28 27 26 25 24
AUTO_OVERR RESERVED
IDE
W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
R/W-0h R/W-100h
7 6 5 4 3 2 1 0
NEST_HINT_2
R/W-100h

the write data.
4.5.3.56 HINLR3 Register (offset = 110Ch) [reset = 100h]

interrupt.

31 30 29 28 27 26 25 24
AUTO_OVERR RESERVED
IDE
W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
R/W-0h R/W-100h
7 6 5 4 3 2 1 0
NEST_HINT_3
R/W-100h

the write data.

interrupt.

31 30 29 28 27 26 25 24
AUTO_OVERR RESERVED
IDE
W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
R/W-0h R/W-100h
7 6 5 4 3 2 1 0
NEST_HINT_4
R/W-100h

the write data.

interrupt.

31 30 29 28 27 26 25 24
AUTO_OVERR RESERVED
IDE
W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
R/W-0h R/W-100h
7 6 5 4 3 2 1 0
NEST_HINT_5
R/W-100h

the write data.

interrupt.

31 30 29 28 27 26 25 24
AUTO_OVERR RESERVED
IDE
W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
R/W-0h R/W-100h
7 6 5 4 3 2 1 0
NEST_HINT_6
R/W-100h

the write data.
4.5.3.60 HINLR7 Register (offset = 111Ch) [reset = 100h]

interrupt.

31 30 29 28 27 26 25 24
AUTO_OVERR RESERVED
IDE
W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
R/W-0h R/W-100h
7 6 5 4 3 2 1 0
NEST_HINT_7
R/W-100h

the write data.

interrupt.

31 30 29 28 27 26 25 24
AUTO_OVERR RESERVED
IDE
W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
R/W-0h R/W-100h
7 6 5 4 3 2 1 0
NEST_HINT_8
R/W-100h

the write data.

interrupt.

31 30 29 28 27 26 25 24
AUTO_OVERR RESERVED
IDE
W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
R/W-0h R/W-100h
7 6 5 4 3 2 1 0
NEST_HINT_9
R/W-100h

the write data.
4.5.3.63 HIER Register (offset = 1500h) [reset = 0h]

HIER is shown in Figure 4-191 and described in Table 4-178.
The Host Interrupt Enable Registers enable or disable individual host interrupts. These work separately
from the global enables. There is one bit per host interrupt. These bits are updated when writing to the
Host Interrupt Enable Index Set and Host Interrupt Enable Index Clear registers.
Figure 4-191. HIER Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED EN_HINT
R/W-0h R/W-0h
Table 4-178. HIER Register Field Descriptions

9-0 EN_HINT R/W 0h The enable of the host interrupts (one per bit).
0 = disabled
1 = enabled
4.5.4 PRU_ICSS_IEP Registers

Table 4-179 lists the memory-mapped registers for the PRU_ICSS_IEP. All register offset addresses not
modified.
Table 4-179. PRU_ICSS_IEP Registers

0h IEP_TMR_GLB_CFG Section 4.5.4.1
4h IEP_TMR_GLB_STS Section 4.5.4.2
8h IEP_TMR_COMPEN Section 4.5.4.3
Ch IEP_TMR_CNT Section 4.5.4.4
10h IEP_TMR_CAP_CFG Section 4.5.4.5
14h IEP_TMR_CAP_STS Section 4.5.4.6
18h IEP_TMR_CAPR0 Section 4.5.4.7
1Ch IEP_TMR_CAPR1 Section 4.5.4.8
2Ch IEP_TMR_CAPR5 Section 4.5.4.12
34h IEP_TMR_CAPF6 Section 4.5.4.14
3Ch IEP_TMR_CAPF7 Section 4.5.4.16
40h IEP_TMR_CMP_CFG Section 4.5.4.17
44h IEP_TMR_CMP_STS Section 4.5.4.18
48h IEP_TMR_CMP0 Section 4.5.4.19
4Ch IEP_TMR_CMP1 Section 4.5.4.20
5Ch IEP_TMR_CMP5 Section 4.5.4.24
Table 4-179. PRU_ICSS_IEP Registers (continued)

80h IEP_TMR_RXIPG0 Section 4.5.4.27
84h IEP_TMR_RXIPG1 Section 4.5.4.28
100h IEP_SYNC_CTRL Section 4.5.4.29
104h IEP_SYNC_FIRST_STAT Section 4.5.4.30
108h IEP_SYNC0_STAT Section 4.5.4.31
10Ch IEP_SYNC1_STAT Section 4.5.4.32
110h IEP_SYNC_PWIDTH Section 4.5.4.33
114h IEP_SYNC0_PERIOD Section 4.5.4.34
118h IEP_SYNC1_DELAY Section 4.5.4.35
11Ch IEP_SYNC_START Section 4.5.4.36
200h IEP_WD_PREDIV Section 4.5.4.37
204h IEP_PDI_WD_TIM Section 4.5.4.38
208h IEP_PD_WD_TIM Section 4.5.4.39
20Ch IEP_WD_STATUS Section 4.5.4.40
210h IEP_WD_EXP_CNT Section 4.5.4.41
214h IEP_WD_CTRL Section 4.5.4.42
300h IEP_DIGIO_CTRL Section 4.5.4.43
308h IEP_DIGIO_DATA_IN Section 4.5.4.44
30Ch IEP_DIGIO_DATA_IN_RAW Section 4.5.4.45
310h IEP_DIGIO_DATA_OUT Section 4.5.4.46
314h IEP_DIGIO_DATA_OUT_EN Section 4.5.4.47
318h IEP_DIGIO_EXP Section 4.5.4.48
4.5.4.1 IEP_TMR_GLB_CFG Register (offset = 0h) [reset = 550h]

IEP_TMR_GLB_CFG is shown in Figure 4-192 and described in Table 4-180.
GLOBAL CONFIGURE
Figure 4-192. IEP_TMR_GLB_CFG Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED CMP_INC
R-0h R/W-5h
15 14 13 12 11 10 9 8
CMP_INC
R/W-5h
7 6 5 4 3 2 1 0
DEFAULT_INC RESERVED CNT_ENABLE
R/W-5h R-0h R/W-0h
Table 4-180. IEP_TMR_GLB_CFG Register Field Descriptions

31-20 RESERVED R 0h
19-8 CMP_INC R/W 5h Defines the increment value when compensation is active
7-4 DEFAULT_INC R/W 5h Defines the default increment value
3-1 RESERVED R 0h
0 CNT_ENABLE R/W 0h Counter enable
0: Disables the counter.
The counter maintains the current count.
1: Enables the counter.
4.5.4.2 IEP_TMR_GLB_STS Register (offset = 4h) [reset = 0h]

IEP_TMR_GLB_STS is shown in Figure 4-193 and described in Table 4-181.
GLOBAL STATUS
Figure 4-193. IEP_TMR_GLB_STS Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CNT_OVF
R-0h R/W1toClr-0h
Table 4-181. IEP_TMR_GLB_STS Register Field Descriptions

31-1 RESERVED R 0h
0 CNT_OVF R/W1toClr 0h Counter overflow status
0: No overflow
1: Overflow occurred
4.5.4.3 IEP_TMR_COMPEN Register (offset = 8h) [reset = 0h]

IEP_TMR_COMPEN is shown in Figure 4-194 and described in Table 4-182.
COMPENSATION
Figure 4-194. IEP_TMR_COMPEN Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED COMPEN_CNT
R-0h R/W-0h
Table 4-182. IEP_TMR_COMPEN Register Field Descriptions

31-24 RESERVED R 0h
23-0 COMPEN_CNT R/W 0h Compensation counter.
Read returns the current compen_cnt value.
0: Compensation is disabled and counter will increment by
DEFAULT_INC.
n: Compensation is enabled until COMPEN_CNT decrements to 0.
The COMPEN_CNT value decrements on every iep_clk/ocp_clk
cycle.
When COMPEN_CNT is greater than 0, then count value increments
by CMP_INC.
4.5.4.4 IEP_TMR_CNT Register (offset = Ch) [reset = 0h]

IEP_TMR_CNT is shown in Figure 4-195 and described in Table 4-183.
COUNT is a free running counter with a sticky over flag status bit. The counter overflow flag is set when
the counter switches or rolls over from 0xffff_ffff -> 0x0000_0000 and continues to count up. The software
must read and clear the counter overflow flag, and increment the MSB in software variable.
Figure 4-195. IEP_TMR_CNT Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNT
R/W1toClr-0h
Table 4-183. IEP_TMR_CNT Register Field Descriptions

31-0 COUNT R/W1toClr 0h 32-bit count value.
Increments by (DEFAULT_INC or CMP_INC) on every positive edge
of iep_clk (200MHz) or ocp_clk.
4.5.4.5 IEP_TMR_CAP_CFG Register (offset = 10h) [reset = 1FC00h]

IEP_TMR_CAP_CFG is shown in Figure 4-196 and described in Table 4-184.
CAPTURE CONFIGURE
Figure 4-196. IEP_TMR_CAP_CFG Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED CAP_ASYNC_EN
R/W-0h R/W-7Fh
15 14 13 12 11 10 9 8
CAP_ASYNC_EN CAP7F_1ST_E CAP7R_1ST_E
VENT_EN VENT_EN
R/W-7Fh R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CAP6F_1ST_E CAP6R_1ST_E CAP_1ST_EVENT_EN
VENT_EN VENT_EN
R/W-0h R/W-0h R/W-0h
Table 4-184. IEP_TMR_CAP_CFG Register Field Descriptions

17-10 CAP_ASYNC_EN R/W FFh Synchronization of the capture inputs to the iep_clk/ocp_clk enable.
Note if input capture signal is asynchronous to iep_clk, enabling
synchronization will cause the capture contents to be invalid.
CAP_ASYNC_EN[n] maps to CAPR[n].
0: Disable synchronization
1: Enable synchronization
9 CAP7F_1ST_EVENT_EN R/W 0h Capture 1st Event Enable for CAPF7
0: Continues mode.
The capture status is not set when events occur.
1: First Event mode.
The capture status is set when the first event occurs and must be
cleared before new data will fill buffer.
Time value is captured when first event occurs and held until time is
read.
8 CAP7R_1ST_EVENT_EN R/W 0h Capture 1st Event Enable for CAPR7
0: Continues mode.
read.
7 CAP6F_1ST_EVENT_EN R/W 0h Capture 1st Event Enable for CAPF6
0: Continues mode.
read.
Table 4-184. IEP_TMR_CAP_CFG Register Field Descriptions (continued)

6 CAP6R_1ST_EVENT_EN R/W 0h Capture 1st Event Enable for CAPR6
0: Continues mode.
read.
5-0 CAP_1ST_EVENT_EN R/W 0h Capture 1st Event Enable for registers.
CAP_1ST_EVENT_EN[n] maps to CAPR[n], where n = 0-5.
0: Continues mode.
read.
4.5.4.6 IEP_TMR_CAP_STS Register (offset = 14h) [reset = 0h]

IEP_TMR_CAP_STS is shown in Figure 4-197 and described in Table 4-185.
CAPTURE STATUS CONFIGURE. Note: Capture will always occur as long as it is enabled, if enabled the
user cannot tell if 2 events occurred.
Figure 4-197. IEP_TMR_CAP_STS Register

31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
CAP_RAW
R-X
15 14 13 12 11 10 9 8
RESERVED CAP_VALID CAPF7_VALID CAPR7_VALID
R-X R-0h RtoClr-0h RtoClr-0h
7 6 5 4 3 2 1 0
CAPF6_VALID CAPR6_VALID CAPR_VALID
RtoClr-0h RtoClr-0h RtoClr-0h
Table 4-185. IEP_TMR_CAP_STS Register Field Descriptions

31-24 RESERVED R X
23-16 CAP_RAW R X Raw/Current status bit for each of the capture registers, where
CAP_RAW[n] maps to CAPR[n].
0: Current state is low
1: Current state is high
15-11 RESERVED R X
10 CAP_VALID R 0h Valid status for capture function.
Reflects the ORed result from CAP_STATUS
[9:0].
0: No Hit for any capture event, i.e., there are all 0 in CAP_STATUS
[9:0].
1: Hit for 1 or more captures events is pending, i.e., there has at
least one value equal to 1 in CAP_STATUS
[9:0].
9 CAPF7_VALID RtoClr 0h Valid status for CAPF7 (fall).
0: No Hit, no capture event occurred
1: Hit, capture event occurred
8 CAPR7_VALID RtoClr 0h Valid status for CAPR7 (rise).
7 CAPF6_VALID RtoClr 0h Valid status for CAPF6 (fall).
6 CAPR6_VALID RtoClr 0h Valid status for CAPR6 (rise).
5-0 CAPR_VALID RtoClr 0h Valid status bit for each compare register, where CAPR_VALID[n]
maps to CAPR[n] (rise), where n = 0-5.
4.5.4.7 IEP_TMR_CAPR0 Register (offset = 18h) [reset = 0h]

IEP_TMR_CAPR0 is shown in Figure 4-198 and described in Table 4-186.
CAPTURE RISE0
Figure 4-198. IEP_TMR_CAPR0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPR0
R-0h
Table 4-186. IEP_TMR_CAPR0 Register Field Descriptions

31-0 CAPR0 R 0h Value captured for CAPR0 event
4.5.4.8 IEP_TMR_CAPR1 Register (offset = 1Ch) [reset = 0h]

CAPTURE RISE1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPR1
R-0h


CAPTURE RISE2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPR2
R-0h


CAPTURE RISE3

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPR3
R-0h


CAPTURE RISE4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPR4
R-0h

4.5.4.12 IEP_TMR_CAPR5 Register (offset = 2Ch) [reset = 0h]

CAPTURE RISE5

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPR5
R-0h


CAPTURE RISE6

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPR6
R-0h

4.5.4.14 IEP_TMR_CAPF6 Register (offset = 34h) [reset = 0h]

IEP_TMR_CAPF6 is shown in Figure 4-205 and described in Table 4-193.
CAPTURE FALL6
Figure 4-205. IEP_TMR_CAPF6 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPF6
R-0h
Table 4-193. IEP_TMR_CAPF6 Register Field Descriptions

31-0 CAPF6 R 0h Value captured for CAPF6 event

CAPTURE RISE7

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPR7
R-0h

4.5.4.16 IEP_TMR_CAPF7 Register (offset = 3Ch) [reset = 0h]

IEP_TMR_CAPF7 is shown in Figure 4-207 and described in Table 4-195.
CAPTURE FALL7
Figure 4-207. IEP_TMR_CAPF7 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPF7
R-0h
Table 4-195. IEP_TMR_CAPF7 Register Field Descriptions

31-0 CAPF7 R 0h Value captured for CAPF7 event
4.5.4.17 IEP_TMR_CMP_CFG Register (offset = 40h) [reset = 0h]

IEP_TMR_CMP_CFG is shown in Figure 4-208 and described in Table 4-196.
COMPARE CONFIGURE
Figure 4-208. IEP_TMR_CMP_CFG Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED CMP_EN
R-0h R/W-0h
7 6 5 4 3 2 1 0
CMP_EN CMP0_RST_C
NT_EN
R/W-0h R/W-0h
Table 4-196. IEP_TMR_CMP_CFG Register Field Descriptions

31-9 RESERVED R 0h
8-1 CMP_EN R/W 0h Compare registers enable, where CMP_EN[0] maps to CMP[0].
0: Disables event
1: Enables event
0 CMP0_RST_CNT_EN R/W 0h Counter reset enable.
0: Disable
1: Enable the reset of the counter if a CMP0 event occurs
4.5.4.18 IEP_TMR_CMP_STS Register (offset = 44h) [reset = 0h]

IEP_TMR_CMP_STS is shown in Figure 4-209 and described in Table 4-197.
COMPARE STATUS
Figure 4-209. IEP_TMR_CMP_STS Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CMP_HIT
R-0h R/W1toClr-0h
Table 4-197. IEP_TMR_CMP_STS Register Field Descriptions

31-8 RESERVED R 0h
7-0 CMP_HIT R/W1toClr 0h Status bit for each of the compare registers, where CMP_HIT[n]
maps to CMP[n].
"Match" indicates the current counter is greater than or equal to the
compare value.
Note it is the firmware's responsibility to handle the IEP overflow.
0: Match has not occurred.
1: Match occurred.
The associated hardware event signal will assert and remain high
until the status is cleared.
4.5.4.19 IEP_TMR_CMP0 Register (offset = 48h) [reset = 0h]

IEP_TMR_CMP0 is shown in Figure 4-210 and described in Table 4-198.
COMPARE0
Figure 4-210. IEP_TMR_CMP0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP0
R/W-0h
Table 4-198. IEP_TMR_CMP0 Register Field Descriptions

31-0 CMP0 R/W 0h Compare 0 value
4.5.4.20 IEP_TMR_CMP1 Register (offset = 4Ch) [reset = 0h]

COMPARE1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP1
R/W-0h


COMPARE2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP2
R/W-0h


COMPARE3

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP3
R/W-0h


COMPARE4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP4
R/W-0h

4.5.4.24 IEP_TMR_CMP5 Register (offset = 5Ch) [reset = 0h]

COMPARE5

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP5
R/W-0h


COMPARE6

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP6
R/W-0h


COMPARE7

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP7
R/W-0h

4.5.4.27 IEP_TMR_RXIPG0 Register (offset = 80h) [reset = FFFF0000h]

IEP_TMR_RXIPG0 is shown in Figure 4-218 and described in Table 4-206.
RX InterPackage Gap (IPG) 0
Figure 4-218. IEP_TMR_RXIPG0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_MIN_IPG RX_IPG
R/WtoReset-FFFFh R-0h
Table 4-206. IEP_TMR_RXIPG0 Register Field Descriptions

31-16 RX_MIN_IPG R/WtoReset FFFFh Defines the minimum number of iep_clk/ocp_clk cycles that is
RX_DV is sampled low.
It stores the smallest RX_IPG duration.
It can be read at any time and gets updated after RX_IPG is
updated, if RX_MIN_IPG is greater than RX_IPG.
15-0 RX_IPG R 0h Records the current number of iep_clk/ocp_clk cycles RX_DV is
sampled low.
Value is updated after RX_DV transitions from low to high.
It will saturate at 0xffff.
4.5.4.28 IEP_TMR_RXIPG1 Register (offset = 84h) [reset = FFFF0000h]

IEP_TMR_RXIPG1 is shown in Figure 4-219 and described in Table 4-207.
RX InterPackage Gap (IPG) 1
Figure 4-219. IEP_TMR_RXIPG1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_MIN_IPG RX_IPG
R/WtoReset-FFFFh R-0h
Table 4-207. IEP_TMR_RXIPG1 Register Field Descriptions

31-16 RX_MIN_IPG R/WtoReset FFFFh Defines the minimum number of iep_clk/ocp_clk cycles that is
RX_DV is sampled low.
It stores the smallest RX_IPG duration.
It can be read at any time and gets updated after RX_IPG is
updated, if RX_MIN_IPG is greater than RX_IPG.
15-0 RX_IPG R 0h Records the current number of iep_clk/ocp_clk cycles RX_DV is
sampled low.
Value is updated after RX_DV transitions from low to high.
It will saturate at 0xffff.
4.5.4.29 IEP_SYNC_CTRL Register (Offset = 100h) [reset = 0h]

IEP_SYNC_CTRL is shown in Figure 4-220 and described in Table 4-208.
SYNC GENERATION CONTROL
Figure 4-220. IEP_SYNC_CTRL Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED SYNC1_IND_E
N
R-0h R/W-0h
7 6 5 4 3 2 1 0
SYNC1_CYCLI SYNC1_ACK_ SYNC0_CYCLI SYNC0_ACK_ RESERVED SYNC1_EN SYNC0_EN SYNC_EN
C_EN EN C_EN EN
R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h R/W-0h
Table 4-208. IEP_SYNC_CTRL Register Field Descriptions

31-9 RESERVED R 0h
8 SYNC1_IND_EN R/W 0h SYNC1 independent mode enable.
Independent mode means the SYNC1 signal can be different from
SYNC0.
0: Dependent mode
1: Independent mode
7 SYNC1_CYCLIC_EN R/W 0h SYNC1 single shot or cyclic/auto generation mode enable
0: Disable, single shot mode
1: Enable, cyclic generation mode
6 SYNC1_ACK_EN R/W 0h SYNC1 acknowledgement mode enable
0: Disable, SYNC1 will go low after pulse width is met.
1: Enable, SYNC1 will remain asserted until receiving software
acknowledges by reading SYNC1_STATUS which clears on read.
5 SYNC0_CYCLIC_EN R/W 0h SYNC0 single shot or cyclic/auto generation mode enable

0: Disable, single shot mode
1: Enable, cyclic generation mode
4 SYNC0_ACK_EN R/W 0h SYNC0 acknowledgement mode enable
0: Disable, SYNC0 will go low after pulse width is met.
1: Enable, SYNC0 will remain asserted until receiving software
acknowledges by reading SYNC1_STATUS which clears on read.
3 RESERVED R 0h
2 SYNC1_EN R/W 0h SYNC1 generation enable
0: Disable
1: Enable
1 SYNC0_EN R/W 0h SYNC0 generation enable
0: Disable
1: Enable
Table 4-208. IEP_SYNC_CTRL Register Field Descriptions (continued)

0 SYNC_EN R/W 0h SYNC generation enable
0: Disable the generation and clocking of SYNC0 and SYNC1 logic
1: Enables SYNC0 and SYNC1 generation
4.5.4.30 IEP_SYNC_FIRST_STAT Register (Offset = 104h) [reset = 0h]

IEP_SYNC_FIRST_STAT is shown in Figure 4-221 and described in Table 4-209.
SYNC GENERATION FIRST EVENT STATUS
Figure 4-221. IEP_SYNC_FIRST_STAT Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED FIRST_SYNC1 FIRST_SYNC0
R-0h R-0h R-0h
Table 4-209. IEP_SYNC_FIRST_STAT Register Field Descriptions

31-2 RESERVED R 0h
1 FIRST_SYNC1 R 0h SYNC1 First Event status.
This bit is cleared when SYNC1_EN = 0.
0: Not occurred
1: Occurred
0 FIRST_SYNC0 R 0h SYNC0 First Event status.
This bit is cleared when SYNC0_EN = 0.
0: Not occurred
1: Occurred
4.5.4.31 IEP_SYNC0_STAT Register (Offset = 108h) [reset = 0h]

IEP_SYNC0_STAT is shown in Figure 4-222 and described in Table 4-210.
SYNC0 STATUS
Figure 4-222. IEP_SYNC0_STAT Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED SYNC0_PEND
R-0h R/W1C-0h
Table 4-210. IEP_SYNC0_STAT Register Field Descriptions

31-1 RESERVED R 0h
0 SYNC0_PEND R/W1C 0h SYNC0 pending state.
0: Not pending
1: Pending or the SYNC0_PEND has occurred when
SYNC0_ACK_EN = 0 (Disable).
4.5.4.32 IEP_SYNC1_STAT Register (Offset = 10Ch) [reset = 0h]

IEP_SYNC1_STAT is shown in Figure 4-223 and described in Table 4-211.
SYNC1 STATUS
Figure 4-223. IEP_SYNC1_STAT Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED SYNC1_PEND
R-0h R/W1C-0h
Table 4-211. IEP_SYNC1_STAT Register Field Descriptions

31-1 RESERVED R 0h
0 SYNC1_PEND R/W1C 0h SYNC1 pending state.
0: Not pending
1: Pending or the SYNC1_PEND has occurred when
SYNC1_ACK_EN = 0 (Disable).
4.5.4.33 IEP_SYNC_PWIDTH Register (Offset = 110h) [reset = 0h]

IEP_SYNC_PWIDTH is shown in Figure 4-224 and described in Table 4-212.
SYNC PULSE WIDTH CONFIGURE
Figure 4-224. IEP_SYNC_PWIDTH Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNC_HPW
R/W-0h
Table 4-212. IEP_SYNC_PWIDTH Register Field Descriptions

31-0 SYNC_HPW R/W 0h Defines the number of clock cycles SYNC0/1 will be high.
Note if SYNC0/1 is disabled during pulse width time (that is,
SYNC_CTRL[SYNC0_EN | SYNC1_EN | SYNC_EN] = 0), the
ongoing pulse will be terminated.
0: 1 clock cycle.
1: 2 clock cycles.
N: N+1 clock cycles.
4.5.4.34 IEP_SYNC0_PERIOD Register (Offset = 114h) [reset = 1h]

IEP_SYNC0_PERIOD is shown in Figure 4-225 and described in Table 4-213.
SYNC PERIOD CONFIGURE
Figure 4-225. IEP_SYNC0_PERIOD Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNC0_PERIOD
R/W-1h
Table 4-213. IEP_SYNC0_PERIOD Register Field Descriptions

31-0 SYNC0_PERIOD R/W 1h Defines the period between the rising edges of SYNC0.
0: reserved.
1: 2 clock cycles period.
N: N+1 clock cycles period.
4.5.4.35 IEP_SYNC1_DELAY Register (Offset = 118h) [reset = 0h]

IEP_SYNC1_DELAY is shown in Figure 4-226 and described in Table 4-214.
SYNC CTRL
Figure 4-226. IEP_SYNC1_DELAY Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNC1_DELAY
R/W-0h
Table 4-214. IEP_SYNC1_DELAY Register Field Descriptions

31-0 SYNC1_DELAY R/W 0h When SYNC1_IND_EN = 0, defines number of clock cycles from the
start of SYNC0 to the start of SYNC1.
Note this is the delay before the start of SYNC1.
0: No delay.
1: 1 clock cycle delay.
N: N clock cycles delay.
When SYNC1_IND_EN = 1, defines the period between the rising
edges of SYNC1.
0: reserved.
1: 2 clock cycles period.
N: N+1 clock cycles period.
4.5.4.36 IEP_SYNC_START Register (Offset = 11Ch) [reset = 0h]

IEP_SYNC_START is shown in Figure 4-227 and described in Table 4-215.
SYNC START CONFIGURE
Figure 4-227. IEP_SYNC_START Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNC_START
R/W-0h
Table 4-215. IEP_SYNC_START Register Field Descriptions

31-0 SYNC_START R/W 0h Defines the start time after the activation event.
0: 1 clock cycle delay.
1: 2 clock cycles delay.
N: N+1 clock cycles delay.
4.5.4.37 IEP_WD_PREDIV Register (offset = 200h) [reset = 4E20h]

IEP_WD_PREDIV is shown in Figure 4-228 and described in Table 4-216.
WATCHDOG PRE-DIVIDER
Figure 4-228. IEP_WD_PREDIV Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
PRE_DIV
R/WtoClr-4E20h
7 6 5 4 3 2 1 0
PRE_DIV
R/WtoClr-4E20h
Table 4-216. IEP_WD_PREDIV Register Field Descriptions

31-16 Reserved R 0h
15-0 PRE_DIV R/WtoClr 4E20h Defines the number of iep_clk cycles per WD clock event. Note that
the WD clock is a free-running clock.
The value 0x4e20 (or 20000) generates a rate of 100 us if iep_clk is
200 MHz.
seconds/(WD event) = (clock cycles per WD event)/(clock cycles per
second) = 20000/(200 x [10]^6 ) = 100 us
4.5.4.38 IEP_PDI_WD_TIM Register (offset = 204h) [reset = 3E8h]

IEP_PDI_WD_TIM is shown in Figure 4-229 and described in Table 4-217.
PDI WATCHDOG TIMER CONFIGURE
Figure 4-229. IEP_PDI_WD_TIM Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
PDI_WD_TIME
R/WtoReset-3E8h
7 6 5 4 3 2 1 0
PDI_WD_TIME
R/WtoReset-3E8h
Table 4-217. IEP_PDI_WD_TIM Register Field Descriptions

31-16 Reserved R 0h
15-0 PDI_WD_TIME R/WtoReset 3E8h Defines the number of WD ticks (or increments) for PDI WD, that is,
the number of WD increments.
If PRE_DIV is set to 100 us, then the value 0x03e8 (or 1000)
provides a rate of 100ms.
Read returns the current count.
Counter is reset by software write to register or when Digital Data In
capture occurs.
WD is disabled if WD time is set to 0x0.
Note when an expiration event occurs, the expiration counter
(PDI_EXP_CNT) increments and status (PDI_WD_STAT) clears.
4.5.4.39 IEP_PD_WD_TIM Register (offset = 208h) [reset = 3E8h]

IEP_PD_WD_TIM is shown in Figure 4-230 and described in Table 4-218.
PD WATCHDOG TIMER CONFIGURE
Figure 4-230. IEP_PD_WD_TIM Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
PD_WD_TIME
R/WtoReset-3E8h
7 6 5 4 3 2 1 0
PD_WD_TIME
R/WtoReset-3E8h
Table 4-218. IEP_PD_WD_TIM Register Field Descriptions

31-16 Reserved R 0h
15-0 PD_WD_TIME R/WtoReset 3E8h Defines the number of WD ticks (or increments) for PD WD, that is,
the number of WD increments.
If PRE_DIV is set to 100 us, then 0x03e8 (or 1000) provides a rate
of 100ms.
Read returns the current count.
Counter is reset by software write to register. WD is restarted with
every write access to Sync Managers with WD trigger enable bit set.
WD is disabled if WD time is set to 0x0.
Expiration actions: Increment expiration counter, clear status.
Digital Data out forced to zero if pr1_edio_oe_ext = 1 and
DIGIO_EXT.SW_DATA_OUT_UPDATE = 0.
4.5.4.40 IEP_WD_STATUS Register (offset = 20Ch) [reset = 10001h]

IEP_WD_STATUS is shown in Figure 4-231 and described in Table 4-219.
WATCHDOG STATUS
Figure 4-231. IEP_WD_STATUS Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved PDI_WD_STAT
R-0h R-1h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved PD_WD_STAT
R-0h R-1h
Table 4-219. IEP_WD_STATUS Register Field Descriptions

31-17 Reserved R 0h
16 PDI_WD_STAT R 1h WD PDI status.
0: Expired (PDI_WD_EXP event generated)
1: Active or disabled
15-1 Reserved R 0h
0 PD_WD_STAT R 1h WD PD status (triggered by Sync Mangers status).
Note reading this register clears application event request.
0: Expired (PD_WD_EXP event generated)
1: Active or disabled
4.5.4.41 IEP_WD_EXP_CNT Register (offset = 210h) [reset = 0h]

IEP_WD_EXP_CNT is shown in Figure 4-232 and described in Table 4-220.
WATCHDOG TIMER EXPIRATION COUNTER
Figure 4-232. IEP_WD_EXP_CNT Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
PD_EXP_CNT
R/WtoClr-0h
7 6 5 4 3 2 1 0
PDI_EXP_CNT
R/WtoClr-0h
Table 4-220. IEP_WD_EXP_CNT Register Field Descriptions

31-16 Reserved R 0h
15-8 PD_EXP_CNT R/WtoClr 0h WD PD expiration counter.
Counter increments on every PD time out and stops at 0xff.
7-0 PDI_EXP_CNT R/WtoClr 0h WD PDI expiration counter.
Counter increments on every PDI time out and stops at 0xff.
4.5.4.42 IEP_WD_CTRL Register (offset = 214h) [reset = 0h]

IEP_WD_CTRL is shown in Figure 4-233 and described in Table 4-221.
WATCHDOG CONTROL
Figure 4-233. IEP_WD_CTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved PDI_WD_EN
R-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved PD_WD_EN
R-0h R/W-0h
Table 4-221. IEP_WD_CTRL Register Field Descriptions

31-17 Reserved R 0h
16 PDI_WD_EN R/W 0h Enable WD PDI
0: Disable
1: Enable
15-1 Reserved R 0h
0 PD_WD_EN R/W 0h Enable WD PD
0: Disable
1: Enable
4.5.4.43 IEP_DIGIO_CTRL Register (offset = 300h) [reset = 4h]

IEP_DIGIO_CTRL is shown in Figure 4-234 and described in Table 4-222.
DIGITAL INPUT OUTPUT CONTROL
Figure 4-234. IEP_DIGIO_CTRL Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
OUT_MODE IN_MODE WD_MODE BIDI_MODE OUTVALID_M OUTVALID_PO
ODE L
R/W-0h R/W-0h R/W-0h R-1h R/W-0h R-0h
Table 4-222. IEP_DIGIO_CTRL Register Field Descriptions

31-8 RESERVED R 0h
7-6 OUT_MODE R/W 0h Defines event that triggers data out to be updated.
Note if OUTVALID_MODE is set, then data out is forced to zero if a
WD PD expiration occurs (PD_WD_EXP) from the WD block and
pr1_edio_oe_ext = 1.
0: PRU0/1_RX_EOF
1: Reserved
2: DC SYNC0 event
3: DC SYNC1 event
5-4 IN_MODE R/W 0h Defines event that triggers data in to be sampled.
0: PRU0/1_RX_SOF
1: Rising edge of pr1_edio_latch_in
2: DC rising edge of SYNC0 event
3: DC rising edge of SYNC1 event
3 WD_MODE R/W 0h Defines watchdog behavior.
0: Outputs are reset immediately after watchdog expires
1: Outputs are reset with next output event that follows watchdog
expiration
2 BIDI_MODE R 1h Defines the digital input/output direction.
0: Unidirectional mode: digital input/output direction of pins
configured individually
1: Bidirectional mode: all I/O pins are bidirectional and direction
configuration is Ignored
1 OUTVALID_MODE R/W 0h Defines the outvalid mode behavior.
0: Output event signaling
1: Output data is updated if watchdog is triggered.
Output data is forced to zero if PD_WD_EXP from the WD block and
pr1_edio_oe_ext = 1
0 OUTVALID_POL R 0h Defines outvalid polarity.
0: Active high
1: Active low
4.5.4.44 IEP_DIGIO_DATA_IN Register (offset = 308h) [reset = 0h]

IEP_DIGIO_DATA_IN is shown in Figure 4-235 and described in Table 4-223.
DIGITAL DATA INPUT
Figure 4-235. IEP_DIGIO_DATA_IN Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA_IN
R-X
Table 4-223. IEP_DIGIO_DATA_IN Register Field Descriptions

31-0 DATA_IN R X Data input.
Digital inputs can be configured to be sampled in four ways.
1: Digital inputs are sampled at the start of each frame.
The SOF signal can be used externally to update the input data,
because the SOF is signaled before input data is sampled.
2: The sample time can be controlled externally by using the
pr1_edio_latch_in signal.
3: Digital inputs are sampled at SYNC0 events.
4: Digital inputs are sampled at SYNC1 events.
These can be configured by in_mode.
4.5.4.45 IEP_DIGIO_DATA_IN_RAW Register (offset = 30Ch) [reset = 0h]

IEP_DIGIO_DATA_IN_RAW is shown in Figure 4-236 and described in Table 4-224.
DIGITAL DATA INPUT DIRECT SAMPLE
Figure 4-236. IEP_DIGIO_DATA_IN_RAW Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA_IN_RAW
R-X
Table 4-224. IEP_DIGIO_DATA_IN_RAW Register Field Descriptions

31-0 DATA_IN_RAW R X Raw data input.
Direct sample of pr1_edio_data_in[31:0].
4.5.4.46 IEP_DIGIO_DATA_OUT Register (offset = 310h) [reset = 0h]

IEP_DIGIO_DATA_OUT is shown in Figure 4-237 and described in Table 4-225.
DIGITAL DATA OUTPUT
Figure 4-237. IEP_DIGIO_DATA_OUT Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA_OUT
R/W-0h
Table 4-225. IEP_DIGIO_DATA_OUT Register Field Descriptions

31-0 DATA_OUT R/W 0h Data output.
Digital outputs can be configured to be updated in four ways.
1: Digital outputs are updated at the end of each frame (EOF mode).
2: Digital outputs are updated with SYNC0 events
3: Digital outputs are updated SYNC1events.
4: Digital outputs are updated at the end of a frame which triggered
the Process Data Watchdog.
Digital Outputs are only updated if the frame was correct (WD_TRIG
mode).
These can be configured by out_mode.
4.5.4.47 IEP_DIGIO_DATA_OUT_EN Register (offset = 314h) [reset = 0h]

IEP_DIGIO_DATA_OUT_EN is shown in Figure 4-238 and described in Table 4-226.
DIGITAL DATA OUT ENABLE
Figure 4-238. IEP_DIGIO_DATA_OUT_EN Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA_OUT_EN
R/W-0h
Table 4-226. IEP_DIGIO_DATA_OUT_EN Register Field Descriptions

31-0 DATA_OUT_EN R/W 0h Enables tri-state control for pr1_edio_data_out[31:0].
4.5.4.48 IEP_DIGIO_EXP Register (offset = 318h) [reset = 20h]

IEP_DIGIO_EXP is shown in Figure 4-239 and described in Table 4-227.
DIGIO EXPANSION REGISTER
Figure 4-239. IEP_DIGIO_EXP Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED EOF_SEL SOF_SEL SOF_DLY
R-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OUTVALID_DLY RESERVED SW_OUTVALI OUTVALID_OV SW_DATA_OU
D R_EN T_UPDATE
Table 4-227. IEP_DIGIO_EXP Register Field Descriptions

31-14 RESERVED R 0h
13 EOF_SEL R/W 0h Defines the source of RX_EOF is used for pr1_edio_data_in capture.
0: PRU0_RX_EOF
1: PRU1_RX_EOF
12 SOF_SEL R/W 0h Defines the source of RX_SOF is used for pr1_edio_data_in capture.
0: PRU0_RX_SOF
1: PRU1_RX_SOF
11-8 SOF_DLY R/W 0h Defines the number of iep_clk cycles delay before pr1_edio_data_in
captures.
7-4 OUTVALID_DLY R/W 2h Define the number of iep_clk cycles delay on assertion of
pr1_edio_outvalid.
Minimum is 2 clock cycles Maximum is 16 clock cycles
3 RESERVED R 0h
2 SW_OUTVALID R/W 0h pr1_edio_outvalid = SW_OUTVALID, only if OUTVALID_OVR_EN is
set.
1 OUTVALID_OVR_EN R/W 0h Software override enable
0: Disable override
1: Enable override
0 SW_DATA_OUT_UPDAT R/W 0h Defines the value of pr1_edio_data_out when OUTVALID_OVR_EN
E = 1.
Read 1: Start bit event occurred
Read 0: Start bit event has not occurred
Write 1: pr1_edio_data_out by software data out.
Write 0: No Effect
4.5.5 PRU_ICSS_UART Registers

The system programmer has access to and control over any of the UART registers that are listed in
Table 4-228. These registers, which control UART operations, receive data, and transmit data, are
available at 32-bit addresses in the device memory map.
• RBR, THR, and DLL share one address. When the DLAB bit in LCR is 0, reading from the address
gives the content of RBR, and writing to the address modifies THR. When DLAB = 1, all accesses at
the address read or modify DLL. DLL can also be accessed with address offset 20h.
• IER and DLH share one address. When DLAB = 0, all accesses read or modify IER. When DLAB = 1,
all accesses read or modify DLH. DLH can also be accessed with address offset 24h.
• IIR and FCR share one address. Regardless of the value of the DLAB bit, reading from the address
gives the content of IIR, and writing modifies FCR.
Table 4-228. PRU_ICSS_UART Registers

Offset Acronym Register Description Section
0h RBR Receiver Buffer Register (read only) Section 4.5.5.1
0h THR Transmitter Holding Register (write only) Section 4.5.5.2
4h IER Interrupt Enable Register Section 4.5.5.3
8h IIR Interrupt Identification Register (read only) Section 4.5.5.4
8h FCR FIFO Control Register (write only) Section 4.5.5.5
Ch LCR Line Control Register Section 4.5.5.6
10h MCR Modem Control Register Section 4.5.5.7
14h LSR Line Status Register Section 4.5.5.8
18h MSR Modem Status Register Section 4.5.5.9
1Ch SCR Scratch Pad Register Section 4.5.5.10
20h DLL Divisor LSB Latch Section 4.5.5.11
24h DLH Divisor MSB Latch Section 4.5.5.11
28h REVID1 Revision Identification Register 1 Section 4.5.5.12
2Ch REVID2 Revision Identification Register 2 Section 4.5.5.12
30h PWREMU_MGMT Power and Emulation Management Register Section 4.5.5.13
34h MDR Mode Definition Register Section 4.5.5.14
4.5.5.1 Receiver Buffer Register (RBR)

The receiver buffer register (RBR) is shown in Figure 4-240 and described in Table 4-229.
The UART receiver section consists of a receiver shift register (RSR) and a receiver buffer register (RBR).
When the UART is in the FIFO mode, RBR is a 16-byte FIFO. Timing is supplied by the 16x receiver clock
or 13x receiver clock by programming OSM_SEL bit field of MDR register. Receiver section control is a
function of the line control register (LCR).
RSR receives serial data from the UARTn_RXD pin. Then RSR concatenates the data and moves it into
RBR (or the receiver FIFO). In the non-FIFO mode, when a character is placed in RBR and the receiver
data-ready interrupt is enabled (DR = 1 in IER), an interrupt is generated. This interrupt is cleared when
the character is read from RBR. In the FIFO mode, the interrupt is generated when the FIFO is filled to the
trigger level selected in the FIFO control register (FCR), and it is cleared when the FIFO contents drop
below the trigger level.
Access considerations:
RBR, THR, and DLL share one address. To read RBR, write 0 to the DLAB bit in LCR, and read from the
shared address. When DLAB = 0, writing to the shared address modifies THR. When DLAB = 1, all
accesses at the shared address read or modify DLL.
DLL also has a dedicated address. If you use the dedicated address, you can keep DLAB = 0, so that
RBR and THR are always selected at the shared address.
Figure 4-240. Receiver Buffer Register (RBR)

31 16
Reserved
R-0
15 8 7 0
Reserved DATA
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 4-229. Receiver Buffer Register (RBR) Field Descriptions

31-8 Reserved 0 Reserved
7-0 DATA 0-FFh Received data
4.5.5.2 Transmitter Holding Register (THR)

The transmitter holding register (THR) is shown in Figure 4-241 and described in Table 4-230.
The UART transmitter section consists of a transmitter hold register (THR) and a transmitter shift register
function of the line control register (LCR).
THR receives data from the internal data bus and when TSR is idle, the UART moves the data from THR
to TSR. The UART serializes the data in TSR and transmits the data on the TX pin. In the non-FIFO
mode, if THR is empty and the THR empty (THRE) interrupt is enabled (ETBEI = 1 in IER), an interrupt is
generated. This interrupt is cleared when a character is loaded into THR or the interrupt identification
register (IIR) is read. In the FIFO mode, the interrupt is generated when the transmitter FIFO is empty,
and it is cleared when at least one byte is loaded into the FIFO or IIR is read.
RBR, THR, and DLL share one address. To load THR, write 0 to the DLAB bit of LCR, and write to the
shared address. When DLAB = 0, reading from the shared address gives the content of RBR. When
DLAB = 1, all accesses at the address read or modify DLL.
DLL also has a dedicated address. If you use the dedicated address, you can keep DLAB = 0, so that
RBR and THR are always selected at the shared address.
Figure 4-241. Transmitter Holding Register (THR)

31 16
Reserved
R-0
15 8 7 0
Reserved DATA
R-0 W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 4-230. Transmitter Holding Register (THR) Field Descriptions

7-0 DATA 0-FFh Data to transmit
4.5.5.3 Interrupt Enable Register (IER)

The interrupt enable register (IER) is used to individually enable or disable each type of interrupt request
that can be generated by the UART. Each interrupt request that is enabled in IER is forwarded to the
CPU. IER is shown in Figure 4-242 and described in Table 4-231.
IER and DLH share one address. To read or modify IER, write 0 to the DLAB bit in LCR. When DLAB = 1,
all accesses at the shared address read or modify DLH.
DLH also has a dedicated address. If you use the dedicated address, you can keep DLAB = 0, so that IER
is always selected at the shared address.
Figure 4-242. Interrupt Enable Register (IER)

31 16
Reserved
R-0
15 4 3 2 1 0
Reserved Rsvd ELSI ETBEI ERBI
R-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-231. Interrupt Enable Register (IER) Field Descriptions

3 EDSSI 0 Enable Modem Status Interrupt
2 ELSI Receiver line status interrupt enable.
0 Receiver line status interrupt is disabled.
1 Receiver line status interrupt is enabled.
1 ETBEI Transmitter holding register empty interrupt enable.
0 Transmitter holding register empty interrupt is disabled.
1 Transmitter holding register empty interrupt is enabled.
0 ERBI Receiver data available interrupt and character timeout indication interrupt enable.
0 Receiver data available interrupt and character timeout indication interrupt is disabled.
1 Receiver data available interrupt and character timeout indication interrupt is enabled.
4.5.5.4 Interrupt Identification Register (IIR)

The interrupt identification register (IIR) is a read-only register at the same address as the FIFO control
register (FCR), which is a write-only register. When an interrupt is generated and enabled in the interrupt
enable register (IER), IIR indicates that an interrupt is pending in the IPEND bit and encodes the type of
interrupt in the INTID bits. Reading IIR clears any THR empty (THRE) interrupts that are pending.
IIR is shown in Figure 4-243 and described in Figure 4-243.
The UART has an on-chip interrupt generation and prioritization capability that permits flexible
communication with the CPU. The UART provides three priority levels of interrupts:
• Priority 1 - Receiver line status (highest priority)
• Priority 2 - Receiver data ready or receiver timeout
• Priority 3 - Transmitter holding register empty
The FIFOEN bit in IIR can be checked to determine whether the UART is in the FIFO mode or the non-
FIFO mode.
Access consideration:
IIR and FCR share one address. Regardless of the value of the DLAB bit in LCR, reading from the
address gives the content of IIR, and writing to the address modifies FCR.
Figure 4-243. Interrupt Identification Register (IIR)

31 16
Reserved
R-0
15 8 7 6 5 4 3 1 0
Reserved FIFOEN Reserved INTID IPEND
R-0 R-0 R-0 R-0 R-1
Table 4-232. Interrupt Identification Register (IIR) Field Descriptions

7-6 FIFOEN 0-3h FIFOs enabled.
0 Non-FIFO mode
1h-2h Reserved
3h FIFOs are enabled. FIFOEN bit in the FIFO control register (FCR) is set to 1.
3-1 INTID 0-7h Interrupt type. See Table 4-233.
0 Reserved
1h Transmitter holding register empty (priority 3)
2h Receiver data available (priority 2)
3h Receiver line status (priority 1, highest)
4h-5h Reserved
6h Character timeout indication (priority 2)
7h Reserved
0 IPEND Interrupt pending. When any UART interrupt is generated and is enabled in IER, IPEND is forced to 0.
IPEND remains 0 until all pending interrupts are cleared or until a hardware reset occurs. If no interrupts
are enabled, IPEND is never forced to 0.
0 Interrupts pending.
1 No interrupts pending.
Table 4-233. Interrupt Identification and Interrupt Clearing Information

IIR Bits
Priority
Level 3 2 1 0 Interrupt Type Interrupt Source Event That Clears Interrupt
None 0 0 0 1 None None None
1 0 1 1 0 Receiver line status Overrun error, parity error, framing For an overrun error, reading the line
error, or break is detected. status register (LSR) clears the
interrupt. For a parity error, framing
error, or break, the interrupt is
cleared only after all the erroneous
data have been read.
2 0 1 0 0 Receiver data-ready Non-FIFO mode: Receiver data is Non-FIFO mode: The receiver buffer
ready. register (RBR) is read.
FIFO mode: Trigger level reached. If FIFO mode: The FIFO drops below
four character times (see Table 4-27) the trigger level. (1)
pass with no access of the FIFO, the
interrupt is asserted again.
2 1 1 0 0 Receiver time-out FIFO mode only: No characters have One of the following events:
been removed from or input to the • A character is read from the
receiver FIFO during the last four receiver FIFO. (1)
character times (see Table 4-27),
• A new character arrives in the
and there is at least one character in
receiver FIFO.
the receiver FIFO during this time.
• The URRST bit in the power
and emulation management
register (PWREMU_MGMT) is
loaded with 0.
3 0 0 1 0 Transmitter holding Non-FIFO mode: Transmitter holding A character is written to the
register empty register (THR) is empty. transmitter holding register (THR) or
FIFO mode: Transmitter FIFO is the interrupt identification register
empty. (IIR) is read.
(1)
In the FIFO mode, the receiver data-ready interrupt or receiver time-out interrupt is cleared by the CPU or by the DMA controller,
whichever reads from the receiver FIFO first.
4.5.5.5 FIFO Control Register (FCR)

The FIFO control register (FCR) is a write-only register at the same address as the interrupt identification
register (IIR), which is a read-only register. Use FCR to enable and clear the FIFOs and to select the
receiver FIFO trigger level FCR is shown in Figure 4-244 and described in Table 4-234. The FIFOEN bit
must be set to 1 before other FCR bits are written to or the FCR bits are not programmed.
Access consideration:
IIR and FCR share one address. Regardless of the value of the DLAB bit, reading from the address gives
the content of IIR, and writing to the address modifies FCR.
CAUTION
For proper communication between the UART and the EDMA controller, the
DMAMODE1 bit must be set to 1. Always write a 1 to the DMAMODE1 bit, and
after a hardware reset, change the DMAMODE1 bit from 0 to 1.
Figure 4-244. FIFO Control Register (FCR)

31 16
Reserved
R-0
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
RXFIFTL Reserved DMAMODE1 (1) TXCLR RXCLR FIFOEN
W-0 R-0 W-0 W1C-0 W1C-0 W-0
LEGEND: R = Read only; W = Write only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
(1)
Always write 1 to the DMAMODE1 bit. After a hardware reset, change the DMAMODE1 bit from 0 to 1. DMAMODE = 1 is required for
proper communication between the UART and the DMA controller.
Table 4-234. FIFO Control Register (FCR) Field Descriptions

7-6 RXFIFTL 0-3h Receiver FIFO trigger level. RXFIFTL sets the trigger level for the receiver FIFO. When the trigger level
is reached, a receiver data-ready interrupt is generated (if the interrupt request is enabled). Once the
FIFO drops below the trigger level, the interrupt is cleared.
0 1 byte
1h 4 bytes
2h 8 bytes
3h 14 bytes
3 DMAMODE1 DMA MODE1 enable if FIFOs are enabled. Always write 1 to DMAMODE1. After a hardware reset,
change DMAMODE1 from 0 to 1. DMAMOD1 = 1 is a requirement for proper communication between
the UART and the EDMA controller.
0 DMA MODE1 is disabled.
1 DMA MODE1 is enabled.
2 TXCLR Transmitter FIFO clear. Write a 1 to TXCLR to clear the bit.
0 No effect.
1 Clears transmitter FIFO and resets the transmitter FIFO counter. The shift register is not cleared.
1 RXCLR Receiver FIFO clear. Write a 1 to RXCLR to clear the bit.
0 No effect.
1 Clears receiver FIFO and resets the receiver FIFO counter. The shift register is not cleared.
0 FIFOEN Transmitter and receiver FIFOs mode enable. FIFOEN must be set before other FCR bits are written to
or the FCR bits are not programmed. Clearing this bit clears the FIFO counters.
0 Non-FIFO mode. The transmitter and receiver FIFOs are disabled, and the FIFO pointers are cleared.
1 FIFO mode. The transmitter and receiver FIFOs are enabled.
4.5.5.6 Line Control Register (LCR)

The line control register (LCR) is shown in Figure 4-245 and described in Table 4-235.
The system programmer controls the format of the asynchronous data communication exchange by using
LCR. In addition, the programmer can retrieve, inspect, and modify the content of LCR; this eliminates the
need for separate storage of the line characteristics in system memory.
Figure 4-245. Line Control Register (LCR)

31 16
Reserved
R-0
15 8 7 6 5 4 3 2 1 0
Reserved DLAB BC SP EPS PEN STB WLS
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Table 4-235. Line Control Register (LCR) Field Descriptions

7 DLAB Divisor latch access bit. The divisor latch registers (DLL and DLH) can be accessed at dedicated
addresses or at addresses shared by RBR, THR, and IER. Using the shared addresses requires
toggling DLAB to change which registers are selected. If you use the dedicated addresses, you can
keep DLAB = 0.
0 Allows access to the receiver buffer register (RBR), the transmitter holding register (THR), and the
interrupt enable register (IER) selected. At the address shared by RBR, THR, and DLL, the CPU can
read from RBR and write to THR. At the address shared by IER and DLH, the CPU can read from and
write to IER.
1 Allows access to the divisor latches of the baud generator during a read or write operation (DLL and
DLH). At the address shared by RBR, THR, and DLL, the CPU can read from and write to DLL. At the
address shared by IER and DLH, the CPU can read from and write to DLH.
6 BC Break control.
0 Break condition is disabled.
1 Break condition is transmitted to the receiving UART. A break condition is a condition where the
UARTn_TXD signal is forced to the spacing (cleared) state.
5 SP Stick parity. The SP bit works in conjunction with the EPS and PEN bits. The relationship between the
SP, EPS, and PEN bits is summarized in Table 4-236.
0 Stick parity is disabled.
1 Stick parity is enabled.
• When odd parity is selected (EPS = 0), the PARITY bit is transmitted and checked as set.
• When even parity is selected (EPS = 1), the PARITY bit is transmitted and checked as cleared.
4 EPS Even parity select. Selects the parity when parity is enabled (PEN = 1). The EPS bit works in
conjunction with the SP and PEN bits. The relationship between the SP, EPS, and PEN bits is
summarized in Table 4-236.
0 Odd parity is selected (an odd number of logic 1s is transmitted or checked in the data and PARITY
bits).
1 Even parity is selected (an even number of logic 1s is transmitted or checked in the data and PARITY
bits).
3 PEN Parity enable. The PEN bit works in conjunction with the SP and EPS bits. The relationship between the
SP, EPS, and PEN bits is summarized in Table 4-236.
0 No PARITY bit is transmitted or checked.
1 Parity bit is generated in transmitted data and is checked in received data between the last data word
bit and the first STOP bit.
Table 4-235. Line Control Register (LCR) Field Descriptions (continued)

2 STB Number of STOP bits generated. STB specifies 1, 1.5, or 2 STOP bits in each transmitted character.
When STB = 1, the WLS bit determines the number of STOP bits. The receiver clocks only the first
STOP bit, regardless of the number of STOP bits selected. The number of STOP bits generated is
summarized in Table 4-237.
0 1 STOP bit is generated.
1 WLS bit determines the number of STOP bits:
• When WLS = 0, 1.5 STOP bits are generated.
• When WLS = 1h, 2h, or 3h, 2 STOP bits are generated.
1-0 WLS 0-3h Word length select. Number of bits in each transmitted or received serial character. When STB = 1, the
WLS bit determines the number of STOP bits.
0 5 bits
1h 6 bits
2h 7 bits
3h 8 bits
Table 4-236. Relationship Between ST, EPS, and PEN Bits in LCR
ST Bit EPS Bit PEN Bit Parity Option
x x 0 Parity disabled: No PARITY bit is transmitted or checked
0 0 1 Odd parity selected: Odd number of logic 1s
0 1 1 Even parity selected: Even number of logic 1s
1 0 1 Stick parity selected with PARITY bit transmitted and checked as set
1 1 1 Stick parity selected with PARITY bit transmitted and checked as cleared
Table 4-237. Number of STOP Bits Generated

Word Length Selected Number of STOP Bits Baud Clock (BCLK)
STB Bit WLS Bits with WLS Bits Generated Cycles
0 x Any word length 1 16
1 0h 5 bits 1.5 24
1 1h 6 bits 2 32
1 2h 7 bits 2 32
1 3h 8 bits 2 32
4.5.5.7 Modem Control Register (MCR)

The modem control register (MCR) is shown in Figure 4-246 and described in Table 4-238. The modem
control register provides the ability to enable/disable the autoflow functions, and enable/disable the
loopback function for diagnostic purposes.
Figure 4-246. Modem Control Register (MCR)

31 16
Reserved
R-0
15 6 5 4 3 2 1 0
Reserved AFE (1) LOOP OUT2 OUT1 RTS (1) Rsvd
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0
(1)
All UARTs do not support this feature, see your device-specific data manual for supported features. If this feature is not available, this bit
is reserved and should be cleared to 0.
Table 4-238. Modem Control Register (MCR) Field Descriptions

5 AFE Autoflow control enable. Autoflow control allows the UARTn_RTS and UARTn_CTS signals to provide
handshaking between UARTs during data transfer. When AFE = 1, the RTS bit determines the autoflow
control enabled. Note that all UARTs do not support this feature, see your device-specific data manual
for supported features. If this feature is not available, this bit is reserved and should be cleared to 0.
0 Autoflow control is disabled.
1 Autoflow control is enabled:
• When RTS = 0, UARTn_CTS is only enabled.
• When RTS = 1, UARTn_RTS and UARTn_CTS are enabled.
4 LOOP Loop back mode enable. LOOP is used for the diagnostic testing using the loop back feature.
0 Loop back mode is disabled.
1 Loop back mode is enabled. When LOOP is set, the following occur:
• The UARTn_TXD signal is set high.
• The UARTn_RXD pin is disconnected
• The output of the transmitter shift register (TSR) is lopped back in to the receiver shift register (RSR)
input.
3 OUT2 0 OUT2 Control Bit
2 OUT1 0 OUT1 Control Bit
1 RTS RTS control. When AFE = 1, the RTS bit determines the autoflow control enabled. Note that all UARTs
do not support this feature, see your device-specific data manual for supported features. If this feature
is not available, this bit is reserved and should be cleared to 0.
0 UARTn_RTS is disabled, UARTn_CTS is only enabled.
1 UARTn_RTS and UARTn_CTS are enabled.
0 Reserved 0 Reserved
4.5.5.8 Line Status Register (LSR)

The line status register (LSR) is shown in Figure 4-247 and described in Table 4-239. LSR provides
information to the CPU concerning the status of data transfers. LSR is intended for read operations only;
do not write to this register. Bits 1 through 4 record the error conditions that produce a receiver line status
interrupt.
Figure 4-247. Line Status Register (LSR)

31 16
Reserved
R-0
15 8 7 6 5 4 3 2 1 0
Reserved RXFIFOE TEMT THRE BI FE PE OE DR
R-0 R-0 R-1 R-1 R-0 R-0 R-0 R-0 R-0
Table 4-239. Line Status Register (LSR) Field Descriptions

7 RXFIFOE Receiver FIFO error.
In non-FIFO mode:
0 There has been no error, or RXFIFOE was cleared because the CPU read the erroneous character
from the receiver buffer register (RBR).
1 There is a parity error, framing error, or break indicator in the receiver buffer register (RBR).
In FIFO mode:
0 There has been no error, or RXFIFOE was cleared because the CPU read the erroneous character
from the receiver FIFO and there are no more errors in the receiver FIFO.
1 At least one parity error, framing error, or break indicator in the receiver FIFO.
6 TEMT Transmitter empty (TEMT) indicator.
In non-FIFO mode:
0 Either the transmitter holding register (THR) or the transmitter shift register (TSR) contains a data
character.
1 Both the transmitter holding register (THR) and the transmitter shift register (TSR) are empty.
In FIFO mode:
0 Either the transmitter FIFO or the transmitter shift register (TSR) contains a data character.
1 Both the transmitter FIFO and the transmitter shift register (TSR) are empty.
5 THRE Transmitter holding register empty (THRE) indicator. If the THRE bit is set and the corresponding
interrupt enable bit is set (ETBEI = 1 in IER), an interrupt request is generated.
In non-FIFO mode:
0 Transmitter holding register (THR) is not empty. THR has been loaded by the CPU.
1 Transmitter holding register (THR) is empty (ready to accept a new character). The content of THR has
been transferred to the transmitter shift register (TSR).
In FIFO mode:
0 Transmitter FIFO is not empty. At least one character has been written to the transmitter FIFO. You can
write to the transmitter FIFO if it is not full.
1 Transmitter FIFO is empty. The last character in the FIFO has been transferred to the transmitter shift
register (TSR).
Table 4-239. Line Status Register (LSR) Field Descriptions (continued)

4 BI Break indicator. The BI bit is set whenever the receive data input (UARTn_RXD) was held low for longer
than a full-word transmission time. A full-word transmission time is defined as the total time to transmit
the START, data, PARITY, and STOP bits. If the BI bit is set and the corresponding interrupt enable bit
is set (ELSI = 1 in IER), an interrupt request is generated.
In non-FIFO mode:
0 No break has been detected, or the BI bit was cleared because the CPU read the erroneous character
1 A break has been detected with the character in the receiver buffer register (RBR).
In FIFO mode:
0 No break has been detected, or the BI bit was cleared because the CPU read the erroneous character
from the receiver FIFO and the next character to be read from the FIFO has no break indicator.
1 A break has been detected with the character at the top of the receiver FIFO.
3 FE Framing error (FE) indicator. A framing error occurs when the received character does not have a valid
STOP bit. In response to a framing error, the UART sets the FE bit and waits until the signal on the RX
pin goes high. Once the RX signal goes high, the receiver is ready to detect a new START bit and
receive new data. If the FE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER),
an interrupt request is generated.
In non-FIFO mode:
0 No framing error has been detected, or the FE bit was cleared because the CPU read the erroneous
data from the receiver buffer register (RBR).
1 A framing error has been detected with the character in the receiver buffer register (RBR).
In FIFO mode:
0 No framing error has been detected, or the FE bit was cleared because the CPU read the erroneous
data from the receiver FIFO and the next character to be read from the FIFO has no framing error.
1 A framing error has been detected with the character at the top of the receiver FIFO.
2 PE Parity error (PE) indicator. A parity error occurs when the parity of the received character does not
match the parity selected with the EPS bit in the line control register (LCR). If the PE bit is set and the
corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated.
In non-FIFO mode:
0 No parity error has been detected, or the PE bit was cleared because the CPU read the erroneous data
1 A parity error has been detected with the character in the receiver buffer register (RBR).
In FIFO mode:
0 No parity error has been detected, or the PE bit was cleared because the CPU read the erroneous data
from the receiver FIFO and the next character to be read from the FIFO has no parity error.
1 A parity error has been detected with the character at the top of the receiver FIFO.
1 OE Overrun error (OE) indicator. An overrun error in the non-FIFO mode is different from an overrun error
in the FIFO mode. If the OE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER),
an interrupt request is generated.
In non-FIFO mode:
0 No overrun error has been detected, or the OE bit was cleared because the CPU read the content of
the line status register (LSR).
1 Overrun error has been detected. Before the character in the receiver buffer register (RBR) could be
read, it was overwritten by the next character arriving in RBR.
In FIFO mode:
0 No overrun error has been detected, or the OE bit was cleared because the CPU read the content of
the line status register (LSR).
1 Overrun error has been detected. If data continues to fill the FIFO beyond the trigger level, an overrun
error occurs only after the FIFO is full and the next character has been completely received in the shift
register. An overrun error is indicated to the CPU as soon as it happens. The new character overwrites
the character in the shift register, but it is not transferred to the FIFO.
Table 4-239. Line Status Register (LSR) Field Descriptions (continued)

0 DR Data-ready (DR) indicator for the receiver. If the DR bit is set and the corresponding interrupt enable bit
is set (ERBI = 1 in IER), an interrupt request is generated.
In non-FIFO mode:
0 Data is not ready, or the DR bit was cleared because the character was read from the receiver buffer
register (RBR).
1 Data is ready. A complete incoming character has been received and transferred into the receiver buffer
register (RBR).
In FIFO mode:
0 Data is not ready, or the DR bit was cleared because all of the characters in the receiver FIFO have
been read.
1 Data is ready. There is at least one unread character in the receiver FIFO. If the FIFO is empty, the DR
bit is set as soon as a complete incoming character has been received and transferred into the FIFO.
The DR bit remains set until the FIFO is empty again.
4.5.5.9 Modem Status Register (MSR)

The Modem status register (MSR) is shown in Figure 4-248 and described in Table 4-240. MSR provides
information to the CPU concerning the status of modem control signals. MSR is intended for read
operations only; do not write to this register.
Figure 4-248. Modem Status Register (MSR)

31 16
Reserved
R-0
15 8 7 6 5 4 3 2 1 0
Reserved CD RI DSR CTS DCD TERI DDSR DCTS
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
Table 4-240. Modem Status Register (MSR) Field Descriptions

7 CD 0 Complement of the Carrier Detect input. When the UART is in the diagnostic test mode (loopback mode
MCR[4] = 1), this bit is equal to the MCR bit 3 (OUT2).
6 RI 0 Complement of the Ring Indicator input. When the UART is in the diagnostic test mode (loopback mode
MCR[4] = 1), this bit is equal to the MCR bit 2 (OUT1).
5 DSR 0 Complement of the Data Set Ready input. When the UART is in the diagnostic test mode (loopback
mode MCR[4] = 1), this bit is equal to the MCR bit 0 (DTR).
4 CTS 0 Complement of the Clear To Send input. When the UART is in the diagnostic test mode (loopback
mode MCR[4] = 1), this bit is equal to the MCR bit 1 (RTS).
3 DCD 0 Change in DCD indicator bit. DCD indicates that the DCD input has changed state since the last time it
was read by the CPU. When DCD is set and the modem status interrupt is enabled, a modem status
interrupt is generated.
2 TERI 0 Trailing edge of RI (TERI) indicator bit. TERI indicates that the RI input has changed from a low to a
high. When TERI is set and the modem status interrupt is enabled, a modem status interrupt is
generated.
1 DDSR 0 Change in DSR indicator bit. DDSR indicates that the DSR input has changed state since the last time it
was read by the CPU. When DDSR is set and the modem status interrupt is enabled, a modem status
0 DCTS 0 Change in CTS indicator bit. DCTS indicates that the CTS input has changed state since the last time it
was read by the CPU. When DCTS is set (autoflow control is not enabled and the modem status
interrupt is enabled), a modem status interrupt is generated. When autoflow control is enabled, no
4.5.5.10 Scratch Pad Register (SCR)

The Scratch Pad register (SCR) is shown in Figure 4-249 and described in Table 4-241. SCR is intended
for programmer's use as a scratch pad. It temporarily holds the programmer's data without affecting UART
operation.
Figure 4-249. Scratch Pad Register (SCR)

31 16
Reserved
R-0
15 8 7 0
Reserved SCR
R-0 R-0
Table 4-241. Scratch Pad Register (MSR) Field Descriptions

7-0 SCR 0 These bits are intended for the programmer's use as a scratch pad in the sense that it temporarily holds
the programmer's data without affecting any other UART operation.
4.5.5.11 Divisor Latches (DLL and DLH)

Two 8-bit register fields (DLL and DLH), called divisor latches, store the 16-bit divisor for generation of the
baud clock in the baud generator. The latches are in DLH and DLL. DLH holds the most-significant bits of
the divisor, and DLL holds the least-significant bits of the divisor. These divisor latches must be loaded
during initialization of the UART in order to ensure desired operation of the baud generator. Writing to the
divisor latches results in two wait states being inserted during the write access while the baud generator is
loaded with the new value.
• RBR, THR, and DLL share one address. When DLAB = 1 in LCR, all accesses at the shared address
are accesses to DLL. When DLAB = 0, reading from the shared address gives the content of RBR, and
writing to the shared address modifies THR.
• IER and DLH share one address. When DLAB = 1 in LCR, accesses to the shared address read or
modify to DLH. When DLAB = 0, all accesses at the shared address read or modify IER.
DLL and DLH also have dedicated addresses. If you use the dedicated addresses, you can keep the
DLAB bit cleared, so that RBR, THR, and IER are always selected at the shared addresses.
The divisor LSB latch (DLL) is shown in Figure 4-250 and described in Table 4-242. The divisor MSB latch
(DLH) is shown in Figure 4-251 and described in Table 4-243.
Figure 4-250. Divisor LSB Latch (DLL)

31 16
Reserved
R-0
15 8 7 0
Reserved DLL
R-0 R/W-0
Table 4-242. Divisor LSB Latch (DLL) Field Descriptions

7-0 DLL 0-Fh The 8 least-significant bits (LSBs) of the 16-bit divisor for generation of the baud clock in the baud rate
generator.
Figure 4-251. Divisor MSB Latch (DLH)

31 16
Reserved
R-0
15 8 7 0
Reserved DLH
R-0 R/W-0
Table 4-243. Divisor MSB Latch (DLH) Field Descriptions

7-0 DLH 0-Fh The 8 most-significant bits (MSBs) of the 16-bit divisor for generation of the baud clock in the baud rate
generator.
4.5.5.12 Revision Identification Registers (REVID1 and REVID2)

The revision identification registers (REVID1 and REVID2) contain peripheral identification data for the
peripheral. REVID1 is shown in Figure 4-252 and described in Table 4-244. REVID2 is shown in Figure 4-
253 and described in Table 4-245.
Figure 4-252. Revision Identification Register 1 (REVID1)

31 0
REVID1
R-1102 0002h
Table 4-244. Revision Identification Register 1 (REVID1) Field Descriptions

31-0 REVID1 1102 0002h Peripheral Identification Number
Figure 4-253. Revision Identification Register 2 (REVID2)

31 16
Reserved
R-0
15 8 7 0
Reserved REVID2
R-0 R-0
Table 4-245. Revision Identification Register 2 (REVID2) Field Descriptions

7-0 REVID2 0 Peripheral Identification Number
4.5.5.13 Power and Emulation Management Register (PWREMU_MGMT)

The power and emulation management register (PWREMU_MGMT) is shown in Figure 4-254 and
described in Table 4-246.
Figure 4-254. Power and Emulation Management Register (PWREMU_MGMT)

31 16
Reserved
R-0
15 14 13 12 1 0
Rsvd UTRST URRST Reserved FREE
R/W-0 R/W-0 R/W-0 R-1 R/W-0
Table 4-246. Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions
15 Reserved 0 Reserved. This bit must always be written with a 0.
14 UTRST UART transmitter reset. Resets and enables the transmitter.
0 Transmitter is disabled and in reset state.
1 Transmitter is enabled.
13 URRST UART receiver reset. Resets and enables the receiver.
0 Receiver is disabled and in reset state.
1 Receiver is enabled.
0 FREE Free-running enable mode bit. This bit determines the emulation mode functionality of the UART. When
halted, the UART can handle register read/write requests, but does not generate any
transmission/reception, interrupts or events.
0 If a transmission is not in progress, the UART halts immediately. If a transmission is in progress, the
UART halts after completion of the one-word transmission.
1 Free-running mode is enabled; UART continues to run normally.
4.5.5.14 Mode Definition Register (MDR)

The Mode Definition register (MDR) determines the over-sampling mode for the UART. MDR is shown in
Figure 4-255 and described in Table 4-247.
Figure 4-255. Mode Definition Register (MDR)

31 16
Reserved
R-0
15 1 0
Reserved OSM_SEL
R-0 R/W-0
Table 4-247. Mode Definition Register (MDR) Field Descriptions

0 OSM_SEL Over-Sampling Mode Select.
0 16× over-sampling.
1 13× over-sampling.
4.5.6 PRU_ICSS_ECAP Registers

The PRU ECAP module within the PRU-ICSS is identical to the ECAP module in the AM335x PWMSS.
For additional details about the ECAP registers, see Section 15.3.
4.5.7 PRU_ICSS_MII_RT Registers

Table 4-248 lists the memory-mapped registers for the PRU_ICSS_MII_RT. All register offset addresses
not listed in Table 4-248 should be considered as reserved locations and the register contents should not
be modified.
Table 4-248. PRU_ICSS_MII_RT Registers

0h RXCFG0 Section 4.5.7.1
4h RXCFG1 Section 4.5.7.2
10h TXCFG0 Section 4.5.7.3
14h TXCFG1 Section 4.5.7.4
20h TXCRC0 Section 4.5.7.5
24h TXCRC1 Section 4.5.7.6
30h TXIPG0 Section 4.5.7.7
34h TXIPG1 Section 4.5.7.8
38h PRS0 Section 4.5.7.9
3Ch PRS1 Section 4.5.7.10
40h RXFRMS0 Section 4.5.7.11
44h RXFRMS1 Section 4.5.7.12
48h RXPCNT0 Section 4.5.7.13
4Ch RXPCNT1 Section 4.5.7.14
50h RXERR0 Section 4.5.7.15
54h RXERR1 Section 4.5.7.16
4.5.7.1 RXCFG0 Register (Offset = 0h) [reset = 0h]

RXCFG0 is shown in Figure 4-256 and described in Table 4-249.
Return to Summary Table.
RX CONFIG0
Figure 4-256. RXCFG0 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RX_AUTOFWD RX_BYTE_SW RX_L2_ENABL RX_MUX_SEL RX_CUT_PRE RESERVED RX_ENABLE
_PRE AP E AMBLE
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h
Table 4-249. RXCFG0 Register Field Descriptions

31-7 RESERVED R 0h
6 RX_AUTOFWD_PRE R/W 0h Enables auto-forward of received preamble.
When enabled, this will forward the preamble nibbles including the
SFD to the TX L1 FIFO that is attached to the PRU.
First data byte seen by PRU R31 and/or RX L2 is destination
address (DA).
Odd number of preamble nibbles is supported in this mode.
For example, 0x55D.
Note that new RX should only occur after the current TX completes.
0x
0: Disable 0x
1: Enable, it must disable RX_CUT_PREAMBLE and
TX_AUTO_PREAMBLE
5 RX_BYTE_SWAP R/W 0h Defines the order of Byte0/1 placement for RX R31 and RX L2.
Note that if TX_AUTO_SEQUENCE enabled, this bit cannot get
enable since TX_BYTE_SWAP on swaps the PRU output.
This bit must be selected/updated when the port is disabled or there
is no traffic.
0x
0: R31
[15:8]/RXL2
[15:8] = Byte1{Nibble3,Nibble2} R31[
7:0]/RXL2
[7:0] = Byte0{Nibble1,Nibble0} 0x
1: R31
[15:8]/RXL2
7:0]/RXL2
[7:0] = Byte1{Nibble3,Nibble2} Nibble0 is the first nibble received.
4 RX_L2_ENABLE R/W 0h Enables RX L2 buffer.
0x
0: Disable (RX L2 can function as generic scratch pad) 0x
1: Enable
Table 4-249. RXCFG0 Register Field Descriptions (continued)

3 RX_MUX_SEL R/W 0h Selects receive data source.
Typically, the setting for this will not be identical for the two MII
receive configuration registers.
0x
0: MII RX Data from Port 0 (default for RXCFG0) 0x
1: MII RX Data from Port 1 (default for RXCFG1)
2 RX_CUT_PREAMBLE R/W 0h Removes received preamble.
0x
0: All data from Ethernet PHY are passed on to PRU register.
This assumes Ethernet PHY which does not shorten the preamble.
0x
1: MII interface suppresses preamble and sync frame delimiter.
First data byte seen by PRU register is destination address.
1 RESERVED R 0h
0 RX_ENABLE R/W 0h Enables the receive traffic currently selected by RX_MUX_SELECT.
0x
0: Disable 0x
1: Enable
4.5.7.2 RXCFG1 Register (Offset = 4h) [reset = 8h]

RXCFG1 is shown in Figure 4-257 and described in Table 4-250.
RX CONFIG1
Figure 4-257. RXCFG1 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RX_AUTOFWD RX_BYTE_SW RX_L2_ENABL RX_MUX_SEL RX_CUT_PRE RESERVED RX_ENABLE
_PRE AP E AMBLE
R-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h R-0h R/W-0h
Table 4-250. RXCFG1 Register Field Descriptions

31-7 RESERVED R 0h
6 RX_AUTOFWD_PRE R/W 0h Enables auto-forward of received preamble.
When enabled, this will forward the preamble nibbles including the
SFD to the TX L1 FIFO that is attached to the PRU.
First data byte seen by PRU R31 and/or RX L2 is destination
address (DA).
Odd number of preamble nibbles is supported in this mode.
For example, 0x55D.
Note that new RX should only occur after the current TX completes.
0x
0: Disable 0x
1: Enable, it must disable RX_CUT_PREAMBLE and
TX_AUTO_PREAMBLE
5 RX_BYTE_SWAP R/W 0h Defines the order of Byte0/1 placement for RX R31 and RX L2.
Note that if TX_AUTO_SEQUENCE enabled, this bit cannot get
enable since TX_BYTE_SWAP on swaps the PRU output.
is no traffic.
0x
0: R31
[15:8]/RXL2
7:0]/RXL2
[7:0] = Byte0{Nibble1,Nibble0} 0x
1: R31
[15:8]/RXL2
7:0]/RXL2
[7:0] = Byte1{Nibble3,Nibble2} Nibble0 is the first nibble received.
4 RX_L2_ENABLE R/W 0h Enables RX L2 buffer.
0x
0: Disable (RX L2 can function as generic scratch pad) 0x
1: Enable
Table 4-250. RXCFG1 Register Field Descriptions (continued)

3 RX_MUX_SEL R/W 1h Selects receive data source.
Typically, the setting for this will not be identical for the two MII
receive configuration registers.
0x
0: MII RX Data from Port 0 (default for RXCFG0) 0x
1: MII RX Data from Port 1 (default for RXCFG1)
2 RX_CUT_PREAMBLE R/W 0h Removes received preamble.
0x
0: All data from Ethernet PHY are passed on to PRU register.
This assumes Ethernet PHY which does not shorten the preamble.
0x
1: MII interface suppresses preamble and sync frame delimiter.
First data byte seen by PRU register is destination address.
1 RESERVED R 0h
0 RX_ENABLE R/W 0h Enables the receive traffic currently selected by RX_MUX_SELECT.
0x
0: Disable 0x
1: Enable
4.5.7.3 TXCFG0 Register (Offset = 10h) [reset = 00020010h]

TXCFG0 is shown in Figure 4-258 and described in Table 4-251.
TX CONFIG0
Figure 4-258. TXCFG0 Register

31 30 29 28 27 26 25 24
RESERVED TX_CLK_DELAY RESERVED TX_START_DELAY
R-0h R/W-0h R-0h R/W-2h
23 22 21 20 19 18 17 16
TX_START_DELAY
R/W-2h
15 14 13 12 11 10 9 8
RESERVED TX_AUTO_SE TX_MUX_SEL
QUENCE
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED TX_BYTE_SW TX_EN_MODE TX_AUTO_PR TX_ENABLE
AP EAMBLE
R-1h R/W-0h R/W-0h R/W-0h R/W-0h
Table 4-251. TXCFG0 Register Field Descriptions

31 RESERVED R 0h
30-28 TX_CLK_DELAY R/W 0h To ensure the MII_RT IO timing values published in the device data
manual, the ocp_clk must be configured for 200 MHz and
TX_CLK_DELAY must be set to 6h.
27-26 RESERVED R 0h
25-16 TX_START_DELAY R/W 2h Defines the minimum time interval (delay) between receiving the
RXDV for the current frame and the start of the transmit interface
sending data to the MII interface.
Delay value is in units of MII_RT clock cycles, which uses the
ocp_clk (default is 200MHz, or 5ns).
Default TX_START_DELAY value is 320ns, which is optimized for
minimum latency at 16 bit processing.
Counter is started with RX_DV signal going active.
Transmit interface stops sending data when no more data is written
into transmit interface by PRU along with TX_EOF marker bit set.
If the TX FIFO has data when the delay expires, then TX will start
sending data.
But if the TX FIFO is empty, it will not start until the TX FIFO is not
empty.
It is possible to overflow the TX FIFO with the max delay setting
when auto-forwarding is enabled since the time delay is larger than
the amount of data it needs to store.
As long as TX L1 FIFO overflows, software will need to issue a
TX_RESET to reset the TX FIFO.
The total delay is
64-byte times (size of TX FIFO), but you need to allow delays for
synchronization.
Do to this fact, the maximum delay should be 80ns less when auto
forwarding is enabled.
Therefore, 0x3F0 is the maximum in this configuration.
15-10 RESERVED R 0h
Table 4-251. TXCFG0 Register Field Descriptions (continued)

9 TX_AUTO_SEQUENCE R/W 0h Enables transmit auto-sequence.
Note the transmit data source is determined by TX_MUX_SEL
setting.
0x
0: Disable 0x
1: Enable, transmit state machine based on events on receiver path
that is connected to the respective transmitter.
Also, the masking logic is disabled and only the MII data is used.
8 TX_MUX_SEL R/W 0h Selects transmit data source.
The default/reset setting for TX Port 0 is 1.
This setting permits MII TX Port 0 to receive data from PRU1 and
the MII TX Port 1 which is connected to PRU0 by default.
0x
0: Data from PRU0 (default for TXCFG1) 0x
1: Data from PRU1 (default for TXCFG0)
7-4 RESERVED R 1h
3 TX_BYTE_SWAP R/W 0h Defines the order of Byte0/1 placement for TX R30.
is no traffic.
0x
0: R30
7:0] = Byte0{Nibble1,Nibble0} R30
[31:24] = TX_MASK
[15:8] R30
[23:16] = TX_MASK
[7:0] 0x
1: R30
[31:24] = TX_MASK
[7:0] R30
[23:16] = TX_MASK
[15:8] Nibble0 is the first nibble received.
2 TX_EN_MODE R/W 0h Enables transmit self clear on TX_EOF event.
Note that iep.cmp[3] must be set before transmission will start for
TX0, and iep_cmp[4] for TX1.
This is a new dependency, in addition to TX L1 FIFO not empty and
TX_START_DELAY expiration, to start transmission.
0x
0: Disable 0x
1: Enable, TX_ENABLE will be clear for a TX_EOF event by itself.
1 TX_AUTO_PREAMBLE R/W 0h Transmit data auto-preamble.
0x
0: PRU will provide full preamble 0x
1: TX FIFO will insert pre-amble automatically.
Note that the TX FIFO does not get preloaded with the preamble
until the first write occurs.
This can cause the latency to be larger than the minimum latency.
0 TX_ENABLE R/W 0h Enables transmit traffic on TX PORT.
If TX_EN_MODE is set, then TX_ENABLE will self clear during a
TX_EOF event.
Note Software can use this to pre-fill the TX FIFO and then start the
TX frame during non-ECS operations.
0x
0: TX PORT is disabled/stopped immediately 0x
1: TX PORT is enabled and the frame will start once the IPG counter
expired and TX Start Delay counter has expired
4.5.7.4 TXCFG1 Register (Offset = 14h) [reset = 00400000h]

TXCFG1 is shown in Figure 4-259 and described in Table 4-252.
TX CONFIG1
Figure 4-259. TXCFG1 Register

31 30 29 28 27 26 25 24
RESERVED TX_CLK_DELAY RESERVED TX_START_DELAY
23 22 21 20 19 18 17 16
TX_START_DELAY
R/W-40h
15 14 13 12 11 10 9 8
RESERVED TX_AUTO_SE TX_MUX_SEL
QUENCE
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED TX_BYTE_SW TX_EN_MODE TX_AUTO_PR TX_ENABLE
AP EAMBLE
R-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 4-252. TXCFG1 Register Field Descriptions

31 RESERVED R 0h
30-28 TX_CLK_DELAY R/W 0h To ensure the MII_RT IO timing values published in the device data
manual, the ocp_clk must be configured for 200 MHz and
TX_CLK_DELAY must be set to 6h.
27-26 RESERVED R 0h
25-16 TX_START_DELAY R/W 40h Defines the minimum time interval (delay) between receiving the
RXDV for the current frame and the start of the transmit interface
sending data to the MII interface.
Delay value is in units of MII_RT clock cycles, which uses the
ocp_clk (default is 200MHz, or 5ns).
Default TX_START_DELAY value is 320ns, which is optimized for
minimum latency at 16 bit processing.
Counter is started with RX_DV signal going active.
Transmit interface stops sending data when no more data is written
into transmit interface by PRU along with TX_EOF marker bit set.
If the TX FIFO has data when the delay expires, then TX will start
sending data.
But if the TX FIFO is empty, it will not start until the TX FIFO is not
empty.
It is possible to overflow the TX FIFO with the max delay setting
when auto-forwarding is enabled since the time delay is larger than
the amount of data it needs to store.
As long as TX L1 FIFO overflows, software will need to issue a
TX_RESET to reset the TX FIFO.
The total delay is
64-byte times (size of TX FIFO), but you need to allow delays for
synchronization.
Do to this fact, the maximum delay should be 80ns less when auto
forwarding is enabled.
Therefore, 0x3F0 is the maximum in this configuration.
15-10 RESERVED R 0h
Table 4-252. TXCFG1 Register Field Descriptions (continued)

9 TX_AUTO_SEQUENCE R/W 0h Enables transmit auto-sequence.
Note the transmit data source is determined by TX_MUX_SEL
setting.
0x
0: Disable 0x
1: Enable, transmit state machine based on events on receiver path
that is connected to the respective transmitter.
Also, the masking logic is disabled and only the MII data is used.
8 TX_MUX_SEL R/W 0h Selects transmit data source.
The default/reset setting for TX Port 0 is 1.
This setting permits MII TX Port 0 to receive data from PRU1 and
the MII TX Port 1 which is connected to PRU0 by default.
0x
0: Data from PRU0 (default for TXCFG1) 0x
1: Data from PRU1 (default for TXCFG0)
7-4 RESERVED R 0h
3 TX_BYTE_SWAP R/W 0h Defines the order of Byte0/1 placement for TX R30.
is no traffic.
0x
0: R30
[31:24] = TX_MASK
[15:8] R30
[23:16] = TX_MASK
[7:0] 0x
1: R30
[31:24] = TX_MASK
[7:0] R30
[23:16] = TX_MASK
[15:8] Nibble0 is the first nibble received.
2 TX_EN_MODE R/W 0h Enables transmit self clear on TX_EOF event.
Note that iep.cmp[3] must be set before transmission will start for
TX0, and iep_cmp[4] for TX1.
This is a new dependency, in addition to TX L1 FIFO not empty and
TX_START_DELAY expiration, to start transmission.
0x
0: Disable 0x
1: Enable, TX_ENABLE will be clear for a TX_EOF event by itself.
1 TX_AUTO_PREAMBLE R/W 0h Transmit data auto-preamble.
0x
0: PRU will provide full preamble 0x
1: TX FIFO will insert pre-amble automatically.
Note that the TX FIFO does not get preloaded with the preamble
until the first write occurs.
This can cause the latency to be larger than the minimum latency.
0 TX_ENABLE R/W 0h Enables transmit traffic on TX PORT.
If TX_EN_MODE is set, then TX_ENABLE will self clear during a
TX_EOF event.
Note Software can use this to pre-fill the TX FIFO and then start the
TX frame during non-ECS operations.
0x
0: TX PORT is disabled/stopped immediately 0x
1: TX PORT is enabled and the frame will start once the IPG counter
expired and TX Start Delay counter has expired
4.5.7.5 TXCRC0 Register (Offset = 20h) [reset = 0h]

TXCRC0 is shown in Figure 4-260 and described in Table 4-253.
TX CYCLIC REDUNDANCY CHECK0
Figure 4-260. TXCRC0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_CRC32
R-0h
Table 4-253. TXCRC0 Register Field Descriptions

31-0 TX_CRC32 R 0h FCS (CRC32) data can be read by PRU for diagnostics.
It is only valid after 6 clocks after a TX_CRC_HIGH command is
given.
4.5.7.6 TXCRC1 Register (Offset = 24h) [reset = 0h]

TX CYCLIC REDUNDANCY CHECK1
Figure 4-261. TXCRC1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_CRC32
R-0h
Table 4-254. TXCRC1 Register Field Descriptions

31-0 TX_CRC32 R 0h FCS (CRC32) data can be read by PRU for diagnostics.
It is only valid after 6 clocks after a TX_CRC_HIGH command is
given.
4.5.7.7 TXIPG0 Register (Offset = 30h) [reset = 28h]

TXIPG0 is shown in Figure 4-262 and described in Table 4-255.
TX INTERPACKET GAP0
Figure 4-262. TXIPG0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TX_IPG
R-0h R/W-28h
Table 4-255. TXIPG0 Register Field Descriptions

31-10 RESERVED R 0h
9-0 TX_IPG R/W 28h Defines the minimum of transmit Inter Packet Gap (IPG) which is the
number of ocp_clk cycles between the de-assertion of TX_EN and
the assertion of TX_EN.
The start of the TX will get delayed when the incoming packet IPG is
less than defined minimum value.
In general, software should program in increments of 8, 40ns to
insure the extra delays takes effect.
4.5.7.8 TXIPG1 Register (Offset = 34h) [reset = 28h]

TXIPG1 is shown in Figure 4-263 and described in Table 4-256.
TX INTERPACKET GAP1
Figure 4-263. TXIPG1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TX_IPG
R-0h R/W-28h
Table 4-256. TXIPG1 Register Field Descriptions

31-10 RESERVED R 0h
9-0 TX_IPG R/W 28h Defines the minimum of transmit Inter Packet Gap (IPG) which is the
number of ocp_clk cycles between the de-assertion of TX_EN and
the assertion of TX_EN.
The start of the TX will get delayed when the incoming packet IPG is
less than defined minimum value.
In general, software should program in increments of 8, 40ns to
insure the extra delays takes effect.
4.5.7.9 PRS0 Register (Offset = 38h) [reset = 0h]

PRS0 is shown in Figure 4-264 and described in Table 4-257.
PORT RAW STATUS0
Figure 4-264. PRS0 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED pr1_mii0_crs pr1_mii0_col
R-0h R-0h R-0h
Table 4-257. PRS0 Register Field Descriptions

31-2 RESERVED R 0h
1 pr1_mii0_crs R 0h Current state of pr1_mii0_crs
0 pr1_mii0_col R 0h Current state of pr1_mii0_col
4.5.7.10 PRS1 Register (Offset = 3Ch) [reset = 0h]

PRS1 is shown in Figure 4-265 and described in Table 4-258.
PORT RAW STATUS1
Figure 4-265. PRS1 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED pr1_mii1_crs pr1_mii1_col
R-0h R-0h R-0h
Table 4-258. PRS1 Register Field Descriptions

31-2 RESERVED R 0h
1 pr1_mii1_crs R 0h Current state of pr1_mii1_crs
0 pr1_mii1_col R 0h Current state of pr1_mii1_col
4.5.7.11 RXFRMS0 Register (Offset = 40h) [reset = 9E1h]

RXFRMS0 is shown in Figure 4-266 and described in Table 4-259.
RX FRAME SIZE0
Figure 4-266. RXFRMS0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_MAX_FRM_CNT RX_MIN_FRM_CNT
R/W-0h R/W-9E1h
Table 4-259. RXFRMS0 Register Field Descriptions

31-16 RX_MAX_FRM_CNT R/W 5F1h Defines the maximum received frame count.
If the total byte count of the received frame is more than defined
value, RX_MAX_FRM_ERR will get set.
0x
0: 1 byte after SFD and including CRC.
N: N+1 bytes after SFD and including CRC Note if the incoming
frame is truncated at the marker, RX_CRC and RX_NIBBLE_ODD
will not get asserted.
15-0 RX_MIN_FRM_CNT R/W 3Fh Defines the minimum received frame count.
If the total byte count of received frame is less than defined value,
RX_MIN_FRM_ERR will get set.
0x
N: N+1 bytes after SFD and including CRC
4.5.7.12 RXFRMS1 Register (Offset = 44h) [reset = 05F1003Fh]

RXFRMS1 is shown in Figure 4-267 and described in Table 4-260.
RX FRAME SIZE1
Figure 4-267. RXFRMS1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_MAX_FRM_CNT RX_MIN_FRM_CNT
R/W-5F1h R/W-3Fh
Table 4-260. RXFRMS1 Register Field Descriptions

31-16 RX_MAX_FRM_CNT R/W 5F1h Defines the maximum received frame count.
If the total byte count of the received frame is more than defined
value, RX_MAX_FRM_ERR will get set.
0x
N: N+1 bytes after SFD and including CRC Note if the incoming
frame is truncated at the marker, RX_CRC and RX_NIBBLE_ODD
will not get asserted.
15-0 RX_MIN_FRM_CNT R/W 3Fh Defines the minimum received frame count.
If the total byte count of received frame is less than defined value,
RX_MIN_FRM_ERR will get set.
0x
N: N+1 bytes after SFD and including CRC
4.5.7.13 RXPCNT0 Register (Offset = 48h) [reset = E1h]

RXPCNT0 is shown in Figure 4-268 and described in Table 4-261.
RX PREAMABLE COUNT0
Figure 4-268. RXPCNT0 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RX_MAX_PRE_CNT RX_MIN_PRE_CNT
R/W-Eh R/W-1h
Table 4-261. RXPCNT0 Register Field Descriptions

31-8 RESERVED R 0h
7-4 RX_MAX_PRE_CNT R/W Eh Defines the maximum number of nibbles until the start of frame
delimiter (SFD) event occurred (i.e.
matches 0x5D).
RX_MAX_PRE_COUNT_ERR will be set if the preamble counts
more than the value of RX_MAX_PRE_CNT.
If the SFD does not occur within 16 nibbles, the error will assert and
the incoming frame will be truncated.
0x
0: Disabled 0x
1: Reserved 0x
2: 4th nibble needs to have built 0x5D 0xe: 16th nibble needs to
have built 0x5D Note the 16th nibble is transmitted.
3-0 RX_MIN_PRE_CNT R/W 1h Defines the minimum number of nibbles until the start of frame
delimiter (SFD) event occurred, which is matched the value 0x5D.
RX_MIN_PRE_COUNT_ERR will be set if the preamble counts less
than the value of RX_MIN_PRE_CNT.
0x
0: Disabled 0x
1: 1 0x5 before 0x5D 0x
2: 2 0x5 before 0x5D N: N 0x5 before 0x5D Note it does not need to
be 0x5.
4.5.7.14 RXPCNT1 Register (Offset = 4Ch) [reset = E1h]

RXPCNT1 is shown in Figure 4-269 and described in Table 4-262.
RX PREAMABLE COUNT1
Figure 4-269. RXPCNT1 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RX_MAX_PRE_CNT RX_MIN_PRE_CNT
R/W-Eh R/W-1h
Table 4-262. RXPCNT1 Register Field Descriptions

31-8 RESERVED R 0h
7-4 RX_MAX_PRE_CNT R/W Eh Defines the maximum number of nibbles until the start of frame
delimiter (SFD) event occurred (i.e.
matches 0x5D).
RX_MAX_PRE_COUNT_ERR will be set if the preamble counts
more than the value of RX_MAX_PRE_CNT.
If the SFD does not occur within 16 nibbles, the error will assert and
the incoming frame will be truncated.
0x
0: Disabled 0x
1: Reserved 0x
2: 4th nibble needs to have built 0x5D 0xe: 16th nibble needs to
have built 0x5D Note the 16th nibble is transmitted.
3-0 RX_MIN_PRE_CNT R/W 1h Defines the minimum number of nibbles until the start of frame
delimiter (SFD) event occurred, which is matched the value 0x5D.
RX_MIN_PRE_COUNT_ERR will be set if the preamble counts less
than the value of RX_MIN_PRE_CNT.
0x
0: Disabled 0x
1: 1 0x5 before 0x5D 0x
2: 2 0x5 before 0x5D N: N 0x5 before 0x5D Note it does not need to
be 0x5.
4.5.7.15 RXERR0 Register (Offset = 50h) [reset = 0h]

RXERR0 is shown in Figure 4-270 and described in Table 4-263.
RX ERROR0
Figure 4-270. RXERR0 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RX_MAX_FRM RX_MIN_FRM_ RX_MAX_PRE RX_MIN_PRE_
_CNT_ERR CNT_ERR _CNT_ERR CNT_ERR
R-0h R-0h R-0h R-0h R-0h
Table 4-263. RXERR0 Register Field Descriptions

31-4 RESERVED R 0h
3 RX_MAX_FRM_CNT_ER R 0h Error status of received frame is more than the value of
R RX_MAX_FRM_CNT.
0x
0: No error occurred 0x
1: Error occurred
2 RX_MIN_FRM_CNT_ERR R 0h Error status of received frame is less than the value of
RX_MIN_FRM_CNT.
0x
1: Error occurred
1 RX_MAX_PRE_CNT_ER R 0h Error status of received preamble nibble is more than the value of
R RX_MAX_PRE_CNT.
0x
1: Error occurred
0 RX_MIN_PRE_CNT_ERR R 0h Error status of received preamble nibble is less than the value of
RX_MIN_PRE_CNT.
0x
1: Error occurred
4.5.7.16 RXERR1 Register (Offset = 54h) [reset = 0h]

RXERR1 is shown in Figure 4-271 and described in Table 4-264.
RX ERROR1
Figure 4-271. RXERR1 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RX_MAX_FRM RX_MIN_FRM_ RX_MAX_PRE RX_MIN_PRE_
_CNT_ERR CNT_ERR _CNT_ERR CNT_ERR
Table 4-264. RXERR1 Register Field Descriptions

31-4 RESERVED R 0h
3 RX_MAX_FRM_CNT_ER R 0h Error status of received frame is more than the value of
R RX_MAX_FRM_CNT.
0x
1: Error occurred
2 RX_MIN_FRM_CNT_ERR R 0h Error status of received frame is less than the value of
RX_MIN_FRM_CNT.
0x
1: Error occurred
1 RX_MAX_PRE_CNT_ER R 0h Error status of received preamble nibble is more than the value of
R RX_MAX_PRE_CNT.
0x
1: Error occurred
0 RX_MIN_PRE_CNT_ERR R 0h Error status of received preamble nibble is less than the value of
RX_MIN_PRE_CNT.
0x
1: Error occurred
4.5.8 PRU_ICSS_MDIO Registers

For additional details about the MDIO registers, see Section 14.5.10, MDIO Registers.
4.5.9 PRU_ICSS_CFG Registers

Table 4-265 lists the memory-mapped registers for the PRU_ICSS_CFG. All register offset addresses not
modified.
Table 4-265. PRU_ICSS_CFG Registers

0h REVID Section 4.5.9.1
4h SYSCFG Section 4.5.9.2
8h GPCFG0 Section 4.5.9.3
Ch GPCFG1 Section 4.5.9.4
10h CGR Section 4.5.9.5
14h ISRP Section 4.5.9.6
18h ISP Section 4.5.9.7
1Ch IESP Section 4.5.9.8
20h IECP Section 4.5.9.9
28h PMAO Section 4.5.9.10
2Ch MII_RT Section 4.5.9.11
30h IEPCLK Section 4.5.9.12
34h SPP Section 4.5.9.13
40h PIN_MX Section 4.5.9.14
4.5.9.1 REVID Register (offset = 0h) [reset = 47000000h]

REVID is shown in Figure 4-272 and described in Table 4-266.
The Revision Register contains the ID and revision information.
Figure 4-272. REVID Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REVID
R-47000000h
Table 4-266. REVID Register Field Descriptions

31-0 REVID R 47000000h Revision ID
4.5.9.2 SYSCFG Register (offset = 4h) [reset = 1Ah]

SYSCFG is shown in Figure 4-273 and described in Table 4-267.
The System Configuration Register defines the power IDLE and STANDBY modes.
Figure 4-273. SYSCFG Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED SUB_MWAIT STANDBY_INI STANDBY_MODE IDLE_MODE
T
Table 4-267. SYSCFG Register Field Descriptions

5 SUB_MWAIT R 0h Status bit for wait state.
0 = Ready for Transaction
1 = Wait until 0
4 STANDBY_INIT R/W 1h 1 = Initiate standby sequence.
0 = Enable OCP master ports.
3-2 STANDBY_MODE R/W 2h 0h = Force standby mode: Initiator unconditionally in standby
(standby = 1).
1h = No standby mode: Initiator unconditionally out of standby
(standby = 0).
2h = Smart standby mode: Standby requested by initiator depending
on internal conditions.
3h = Reserved.
1-0 IDLE_MODE R/W 2h 0h = Force-idle mode.
1h = No-idle mode.
2h = Smart-idle mode.
3h = Reserved.
4.5.9.3 GPCFG0 Register (offset = 8h) [reset = 0h]

GPCFG0 is shown in Figure 4-274 and described in Table 4-268.
The General Purpose Configuration 0 Register defines the GPI/O configuration for PRU0.
Figure 4-274. GPCFG0 Register

31 30 29 28 27 26 25 24
RESERVED PRU0_GPO_S PRU0_GPO_DI
H_SEL V1
R/W-0h R-0h R/W-0h
23 22 21 20 19 18 17 16
PRU0_GPO_DIV1 PRU0_GPO_DIV0
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
PRU0_GPO_DI PRU0_GPO_M PRU0_GPI_SB PRU0_GPI_DIV1
V0 ODE
7 6 5 4 3 2 1 0
PRU0_GPI_DIV0 PRU0_GPI_CL PRU0_GPI_MODE
K_MODE
Table 4-268. GPCFG0 Register Field Descriptions

25 PRU0_GPO_SH_SEL R/W 0h Defines which shadow register is currently getting used for GPO
shifting.
0 = gpo_sh0 is selected
24-20 PRU0_GPO_DIV1 R/W 0h Divisor value (divide by PRU0_GPO_DIV1 + 1).
0h = div 1.0.
1h = div 1.5.
2h = div 2.0.
..
1eh = div 16.0.
1fh = reserved.
0h = div 1.0.
1h = div 1.5.
2h = div 2.0.
..
1eh = div 16.0.
1fh = reserved.
14 PRU0_GPO_MODE R/W 0h PRU GPO (R30) modes:
0 = Direct output mode
1 = Serial output mode
13 PRU0_GPI_SB R/W 0h Start Bit event for 28-bit shift in mode.
PRU0_GPI_SB (pru0_r31_status[29]) is set when first capture of a 1
on pru0_r31_status[0].
Read 1: Start Bit event occurred.
Read 0: Start Bit event has not occurred.
Write 1: Will clear PRU0_GPI_SB and clear the whole shift register.
Write 0: No Effect.
12-8 PRU0_GPI_DIV1 R/W 0h Divisor value (divide by PRU0_GPI_DIV1 + 1).
0h = div 1.0.
1h = div 1.5.
2h = div 2.0.
..
1eh = div 16.0.
1fh = reserved.
Table 4-268. GPCFG0 Register Field Descriptions (continued)

0h = div 1.0.
1h = div 1.5.
2h = div 2.0.
..
1eh = div 16.0.
1fh = reserved.
2 PRU0_GPI_CLK_MODE R/W 0h Parallel
16-bit capture mode clock edge.
0 = Use the positive edge of pru0_r31_status[16]
1 = Use the negative edge of pru0_r31_status[16]
1-0 PRU0_GPI_MODE R/W 0h PRU GPI (R31) modes:
0h = Direct input mode.
1h = 16bit parallel capture mode.
2h = 28bit shift in mode.
3h = Mii_rt mode
4.5.9.4 GPCFG1 Register (offset = Ch) [reset = 0h]

GPCFG1 is shown in Figure 4-275 and described in Table 4-269.
The General Purpose Configuration 1 Register defines the GPI/O configuration for PRU1.
Figure 4-275. GPCFG1 Register

31 30 29 28 27 26 25 24
RESERVED PRU1_GPO_S PRU1_GPO_DI
H_SEL V1
R/W-0h R-0h R/W-0h
23 22 21 20 19 18 17 16
PRU1_GPO_DIV1 PRU1_GPO_DIV0
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
PRU1_GPO_DI PRU1_GPO_M PRU1_GPI_SB PRU1_GPI_DIV1
V0 ODE
7 6 5 4 3 2 1 0
PRU1_GPI_DIV0 PRU1_GPI_CL PRU1_GPI_MODE
K_MODE
Table 4-269. GPCFG1 Register Field Descriptions

25 PRU1_GPO_SH_SEL R/W 0h Defines which shadow register is currently getting used for GPO
shifting.
0h = div 1.0.
1h = div 1.5.
2h = div 2.0.
..
1eh = div 16.0.
1fh = reserved.
0h = div 1.0.
1h = div 1.5.
2h = div 2.0.
..
1eh = div 16.0.
1fh = reserved.
14 PRU1_GPO_MODE R/W 0h PRU GPO (R30) modes:
0 = Direct output mode
1 = Serial output mode
13 PRU1_GPI_SB R/W 0h 28-bit shift in mode Start Bit event.
PRU1_GPI_SB (pru1_r31_status[29]) is set when first capture of a 1
on pru1_r31_status[0].
Read 1: Start Bit event occurred.
Read 0: Start Bit event has not occurred.
Write 1: Will clear PRU1_GPI_SB and clear the whole shift register.
Write 0: No Effect.
0h = div 1.0.
1h = div 1.5.
2h = div 2.0.
..
1eh = div 16.0.
1fh = reserved.
Table 4-269. GPCFG1 Register Field Descriptions (continued)

0h = div 1.0.
1h = div 1.5.
2h = div 2.0.
..
1eh = div 16.0.
1fh = reserved.
2 PRU1_GPI_CLK_MODE R/W 0h Parallel
16-bit capture mode clock edge.
0 = Use the positive edge of pru1_r31_status[16]
1 = Use the negative edge of pru1_r31_status[16]
1-0 PRU1_GPI_MODE R/W 0h PRU GPI (R31) modes:
0h = Direct input mode.
1h = 16bit parallel capture mode.
2h = 28bit shift in mode.
3h = Mii_rt mode
4.5.9.5 CGR Register (offset = 10h) [reset = 24924h]

CGR is shown in Figure 4-276 and described in Table 4-270.
The Clock Gating Register controls the state of Clock Management of the different modules. Software
should not clear {module}_CLK_EN until {module}_CLK_STOP_ACK is 0x1.
Figure 4-276. CGR Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED IEP_CLK_EN IEP_CLK_STO
P_ACK
R/W-0h R/W-1h R-0h
15 14 13 12 11 10 9 8
IEP_CLK_STO ECAP_CLK_E ECAP_CLK_ST ECAP_CLK_ST UART_CLK_E UART_CLK_ST UART_CLK_ST INTC_CLK_EN
P_REQ N OP_ACK OP_REQ N OP_ACK OP_REQ
R/W-0h R/W-1h R-0h R/W-0h R/W-1h R-0h R/W-0h R/W-1h
7 6 5 4 3 2 1 0
INTC_CLK_ST INTC_CLK_ST PRU1_CLK_EN PRU1_CLK_ST PRU1_CLK_ST PRU0_CLK_EN PRU0_CLK_ST PRU0_CLK_ST
OP_ACK OP_REQ OP_ACK OP_REQ OP_ACK OP_REQ
R-0h R/W-0h R/W-1h R-0h R/W-0h R/W-1h R-0h R/W-0h
Table 4-270. CGR Register Field Descriptions

17 IEP_CLK_EN R/W 1h IEP clock enable.
0 = Disable Clock
1 = Enable Clock
16 IEP_CLK_STOP_ACK R 0h Acknowledgement that IEP clock can be stopped.
0 = Not Ready to Gate Clock
1 = Ready to Gate Clock
15 IEP_CLK_STOP_REQ R/W 0h IEP request to stop clock.
0 = do not request to stop Clock
1 = request to stop Clock
14 ECAP_CLK_EN R/W 1h ECAP clock enable.
0 = Disable Clock
1 = Enable Clock
13 ECAP_CLK_STOP_ACK R 0h Acknowledgement that ECAP clock can be stopped.
12 ECAP_CLK_STOP_REQ R/W 0h ECAP request to stop clock.
11 UART_CLK_EN R/W 1h UART clock enable.
0 = Disable Clock
1 = Enable Clock
10 UART_CLK_STOP_ACK R 0h Acknowledgement that UART clock can be stopped.
9 UART_CLK_STOP_REQ R/W 0h UART request to stop clock.
8 INTC_CLK_EN R/W 1h INTC clock enable.
0 = Disable Clock
1 = Enable Clock
Table 4-270. CGR Register Field Descriptions (continued)

7 INTC_CLK_STOP_ACK R 0h Acknowledgement that INTC clock can be stopped.
6 INTC_CLK_STOP_REQ R/W 0h INTC request to stop clock.
5 PRU1_CLK_EN R/W 1h PRU1 clock enable.
0 = Disable Clock
1 = Enable Clock
4 PRU1_CLK_STOP_ACK R 0h Acknowledgement that PRU1 clock can be stopped.
3 PRU1_CLK_STOP_REQ R/W 0h PRU1 request to stop clock.
2 PRU0_CLK_EN R/W 1h PRU0 clock enable.
0 = Disable Clock
1 = Enable Clock
1 PRU0_CLK_STOP_ACK R 0h Acknowledgement that PRU0 clock can be stopped.
0 PRU0_CLK_STOP_REQ R/W 0h PRU0 request to stop clock.
4.5.9.6 ISRP Register (offset = 14h) [reset = 0h]

ISRP is shown in Figure 4-277 and described in Table 4-271.
The IRQ Status Raw Parity register is a snapshot of the IRQ raw status for the PRU ICSS memory parity
events. The raw status is set even if the event is not enabled.
Figure 4-277. ISRP Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED RAM_PE_RAW
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
PRU1_DMEM_PE_RAW PRU1_IMEM_PE_RAW
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PRU0_DMEM_PE_RAW PRU0_IMEM_PE_RAW
R/W-0h R/W-0h
Table 4-271. ISRP Register Field Descriptions

19-16 RAM_PE_RAW R/W 0h RAM Parity Error RAW for Byte3, Byte2, Byte1, Byte0.
Note RAM_PE_RAW[0] maps to Byte0.
Write 0: No action.
Read 0: No event pending.
Read 1: Event pending.
Write 1: Set event (debug).
15-12 PRU1_DMEM_PE_RAW R/W 0h PRU1 DMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0.
Note PRU1_DMEM_PE_RAW[0] maps to Byte0.
Write 0: No action.
11-8 PRU1_IMEM_PE_RAW R/W 0h PRU1 IMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0.
Note PRU1_IMEM_PE_RAW[0] maps to Byte0.
Write 0: No action.
7-4 PRU0_DMEM_PE_RAW R/W 0h PRU0 DMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0.
Note PRU0_DMEM_PE_RAW[0] maps to Byte0.
Write 0: No action.
Write 1: Set event (debug) .
3-0 PRU0_IMEM_PE_RAW R/W 0h PRU0 IMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0.
Note PRU0_IRAM_PE_RAW[0] maps to Byte0.
Write 0: No action.
Write 1: Set event (debug) .
4.5.9.7 ISP Register (offset = 18h) [reset = 0h]

ISP is shown in Figure 4-278 and described in Table 4-272.
The IRQ Status Parity Register is a snapshot of the IRQ status for the PRU ICSS memory parity events.
The status is set only if the event is enabled. Write 1 to clear the status after the interrupt has been
serviced.
Figure 4-278. ISP Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED RAM_PE
R-0h 0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRU1_DMEM_PE PRU1_IMEM_PE PRU0_DMEM_PE PRU0_IMEM_PE
0h 0h 0h 0h
Table 4-272. ISP Register Field Descriptions

31-20 RESERVED R 0h
19-16 RAM_PE 0h RAM Parity Error for Byte3, Byte2, Byte1, Byte0.
Note RAM_PE[0] maps to Byte0.
Write 0: No action.
Read 0: No (enabled) event pending.
Write 1: Clear event.
15-12 PRU1_DMEM_PE 0h PRU1 DMEM Parity Error for Byte3, Byte2, Byte1, Byte0.
Note PRU1_DMEM_PE[0] maps to Byte0.
Write 0: No action.
11-8 PRU1_IMEM_PE 0h PRU1 IMEM Parity Error for Byte3, Byte2, Byte1, Byte0.
Note PRU1_IMEM_PE[0] maps to Byte0.
Write 0: No action.
7-4 PRU0_DMEM_PE 0h PRU0 DMEM Parity Error for Byte3, Byte2, Byte1, Byte0.
Note PRU0_DMEM_PE[0] maps to Byte0.
Write 0: No action.
Read 0: No(enabled) event pending.
3-0 PRU0_IMEM_PE 0h PRU0 IMEM Parity Error for Byte3, Byte2, Byte1, Byte0.
Note PRU0_IMEM_PE[0] maps to Byte0.
Write 0: No action.
4.5.9.8 IESP Register (offset = 1Ch) [reset = 0h]

IESP is shown in Figure 4-279 and described in Table 4-273.
The IRQ Enable Set Parity Register enables the IRQ PRU ICSS memory parity events.
Figure 4-279. IESP Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED RAM_PE_SET
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
PRU1_DMEM_PE_SET PRU1_IMEM_PE_SET
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PRU0_DMEM_PE_SET PRU0_IMEM_PE_SET
R/W-0h R/W-0h
Table 4-273. IESP Register Field Descriptions

19-16 RAM_PE_SET R/W 0h RAM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0.
Note RAM_PE_SET[0] maps to Byte0.
Write 0: No action.
Read 0: Interrupt disabled (masked).
Read 1: Interrupt enabled.
Write 1: Enable interrupt.
15-12 PRU1_DMEM_PE_SET R/W 0h PRU1 DMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0.
Note PRU1_DMEM_PE_SET[0] maps to Byte0.
Write 0: No action.
11-8 PRU1_IMEM_PE_SET R/W 0h PRU1 IMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0.
Note PRU1_IMEM_PE_SET[0] maps to Byte0.
Write 0: No action.
7-4 PRU0_DMEM_PE_SET R/W 0h PRU0 DMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0.
Note PRU0_DMEM_PE_SET[0] maps to Byte0.
Write 0: No action.
3-0 PRU0_IMEM_PE_SET R/W 0h PRU0 IMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0.
Note PRU0_IMEM_PE_SET[0] maps to Byte0.
Write 0: No action.
4.5.9.9 IECP Register (offset = 20h) [reset = 0h]

IECP is shown in Figure 4-280 and described in Table 4-274.
The IRQ Enable Clear Parity Register disables the IRQ PRU ICSS memory parity events.
Figure 4-280. IECP Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
PRU1_DMEM_PE_CLR PRU1_IMEM_PE_CLR
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PRU0_DMEM_PE_CLR PRU0_IMEM_PE_CLR
R/W-0h R/W-0h
Table 4-274. IECP Register Field Descriptions

15-12 PRU1_DMEM_PE_CLR R/W 0h PRU1 DMEM Parity Error Clear Enable for Byte3, Byte2, Byte1,
Byte0.
Note PRU1_DMEM_PE_CLR[0] maps to Byte0.
Write 0: No action.
Write 1: Disable interrupt.
11-8 PRU1_IMEM_PE_CLR R/W 0h PRU1 IMEM Parity Error Clear Enable for Byte3, Byte2, Byte1,
Byte0.
Note PRU1_IMEM_PE_CLR[0] maps to Byte0.
Write 0: No action.
7-4 PRU0_DMEM_PE_CLR R/W 0h PRU0 DMEM Parity Error Clear Enable for Byte3, Byte2, Byte1,
Byte0.
Note PRU0_DMEM_PE_CLR[0] maps to Byte0.
Write 0: No action.
3-0 PRU0_IMEM_PE_CLR R/W 0h PRU0 IMEM Parity Error Clear Enable for Byte3, Byte2, Byte1,
Byte0.
Note PRU0_IMEM_PE_CLR[0] maps to Byte0.
Write 0: No action .
4.5.9.10 PMAO Register (offset = 28h) [reset = 0h]

PMAO is shown in Figure 4-281 and described in Table 4-275.
The PRU Master OCP Address Offset Register enables for the PRU OCP Master Port Address to have an
offset of minus 0x0008_0000. This enables the PRU to access External Host address space starting at
0x0000_0000.
Figure 4-281. PMAO Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED PMAO_PRU1 PMAO_PRU0
Table 4-275. PMAO Register Field Descriptions

1 PMAO_PRU1 R/W 0h PRU1 OCP Master Port Address Offset Enable.
0 = Disable address offset.
1 = Enable address offset of -0x0008_0000.
0 PMAO_PRU0 R/W 0h PRU0 OCP Master Port Address Offset Enable.
0 = Disable address offset.
1 = Enable address offset of -0x0008_0000.
4.5.9.11 MII_RT Register (Offset = 2Ch) [reset = 0h]

The MII_RT Event Enable Register enables MII_RT mode events to the INTC.
Figure 4-282. MII_RT Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED MII_RT_EVEN
T_EN
R/W-0h R/W-1h
Table 4-276. MII_RT Register Field Descriptions

0 MII_RT_EVENT_EN R/W 1h Enables the MII_RT Events to the INTC.
0h = Disabled (use external events)
1h = Enabled (use MII_RT events)
4.5.9.12 IEPCLK Register (offset = 30h) [reset = 0h]

IEPCLK is shown in Figure 4-283 and described in Table 4-277.
The IEP Clock Source Register defines the source of the IEP clock.
Figure 4-283. IEPCLK Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED OCP_EN
R/W-0h R/W-0h
Table 4-277. IEPCLK Register Field Descriptions

0 OCP_EN R/W 0h Selects IEP clock source
0 = iep_clk is the source.
1 = ocp_clk is the source.
4.5.9.13 SPP Register (offset = 34h) [reset = 0h]

SPP is shown in Figure 4-284 and described in Table 4-278.
The Scratch Pad Priority and Configuration Register defines the access priority assigned to the PRU cores
and configures the scratch pad XFR shift functionality.
Figure 4-284. SPP Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED XFR_SHIFT_E PRU1_PAD_H
N P_EN
Table 4-278. SPP Register Field Descriptions

1 XFR_SHIFT_EN R/W 0h Enables XIN/XOUT shift functionality.
When enabled, R0
[4:0] (internal to PRU) defines the
32-bit offset for XIN and XOUT operations with the scratch pad.
0 = Disabled.
1 = Enabled.
0 PRU1_PAD_HP_EN R/W 0h Defines which PRU wins write cycle arbitration to a common scratch
pad bank.
The PRU which has higher priority will always perform the write cycle
with no wait states.
The lower PRU will get stalled/wait states until higher PRU is not
performing write cycles.
If the lower priority PRU writes to the same byte has the higher
priority PRU, then the lower priority PRU will over write the bytes.
0 = PRU0 has highest priority.
1 = PRU1 has highest priority.
4.5.9.14 PIN_MX Register (offset = 40h) [reset = 0h]

PIN_MX is shown in Figure 4-285 and described in Table 4-279.
The Pin Mux Select Register defines the state of the PRU ICSS internal pinmuxing.
Figure 4-285. PIN_MX Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PIN_MUX_SEL
R/W-0h R/W-0h
Table 4-279. PIN_MX Register Field Descriptions

7-0 PIN_MUX_SEL R/W 0h Defines the state of PIN_MUX_SEL
[1:0] for internal pinmuxing.
Chapter 5
Graphics Accelerator (SGX)
This chapter describes the graphics accelerator for the device.
Topic ........................................................................................................................... Page
5.1 Integration ....................................................................................................... 526

522 Graphics Accelerator (SGX) SPRUH73Q – October 2011 – Revised December 2019
www.ti.com
Introduction
This chapter describes the 2D/3D graphics accelerator (SGX) for the device.
NOTE: The SGX subsystem is a Texas Instruments instantiation of the POWERVR® SGX530 core
from Imagination Technologies Ltd.
This document contains materials that are ©2003-2007 Imagination Technologies Ltd.
POWERVR® and USSE™ are trademarks or registered trademarks of Imagination
Technologies Ltd.
The 2D/3D graphics accelerator (SGX) subsystem accelerates 2-dimensional (2D) and 3-dimensional (3D)
graphics applications. The SGX subsystem is based on the POWERVR® SGX core from Imagination
Technologies. SGX is a new generation of programmable POWERVR graphic cores. The POWERVR
SGX530 v1.2.5 architecture is scalable and can target market segments, from portable devices to HMI.
5.0.10 POWERVR SGX Main Features

• 2D and 3D graphics
• Tile-based architecture
• Universal scalable shader engine (USSE™) – multithreaded engine incorporating pixel and vertex
shader functionality
• Advanced shader feature set: in excess of OpenGL2.0
• Industry-standard API support: OpenGL ES 1.1 and 2.0, OpenVG v1.0.1
• Fine-grained task switching, load balancing, and power management
• Advanced geometry direct memory access (DMA) driven operation for minimum CPU interaction
• Programmable high-quality image anti-aliasing
• POWERVR SGX core MMU for address translation from the core virtual address to the external
physical address (up to 4GB address range)
• Fully virtualized memory addressing for OS operation in a unified memory architecture
• Advanced and standard 2D operations [e.g., vector graphics, BLTs (block level transfers), ROPs
(raster operations)]
• 32K stride support
SPRUH73Q – October 2011 – Revised December 2019 Graphics Accelerator (SGX) 523
www.ti.com
5.0.11 SGX 3D Features

• Deferred pixel shading
• On-chip tile floating point depth buffer
• 8-bit stencil with on-chip tile stencil buffer
• 8 parallel depth/stencil tests per clock
• Scissor test
• Texture support:
– Cube map
– Projected textures
– 2D textures
– Nonsquare textures
• Texture formats:
– RGBA 8888, 565, 1555
– Monochromatic 8, 16, 16f, 32f, 32int
– Dual channel, 8:8, 16:16, 16f:16f
– Compressed textures PVR-TC1, PVR-TC2, ETC1
– Programmable support for YUV 420 and 422 formats for YUV/RGB color conversion
• Resolution support:
– Frame buffer maximum size = 2048 x 2048
– Texture maximum size = 2048 x 2048
• Texture filtering:
– Bilinear, trilinear, anisotropic
– Independent minimum and maximum control
• Antialiasing:
– 4x multisampling
– Up to 16x full scene anti-aliasing
– Programmable sample positions
• Indexed primitive list support
– Bus mastered
• Programmable vertex DMA
• Render to texture:
– Including twiddled formats
– Auto MipMap generation
• Multiple on-chip render targets (MRT).
Note: Performance is limited when the on-chip memory is not available.
www.ti.com
5.0.12 Universal Scalable Shader Engine (USSE) – Key Features

The USSE is the engine core of the POWERVR SGX architecture and supports a broad range of
instructions.
• Single programming model:
– Multithreaded with 16 simultaneous execution threads and up to 64 simultaneous data instances
– Zero-cost swapping in, and out, of threads
– Cached program execution model
– Dedicated pixel processing instructions
– Dedicated video encode/decode instructions
• SIMD execution unit supporting operations in:
– 32-bit IEEE float
– 2-way 16-bit fixed point
– 4-way 8-bit integer
– 32-bit bit-wise (logical only)
• Static and dynamic flow control:
– Subroutine calls
– Loops
– Conditional branches
– Zero-cost instruction predication
• Procedural geometry:
– Allows generation of primitives
– Effective geometry compression
– High-order surface support
• External data access:
– Permits reads from main memory using cache
– Permits writes to main memory
– Data fence facility
– Dependent texture reads
5.0.13 Unsupported Features

There are no unsupported SGX530 features for this device.
5.1 Integration
GFX Subsystem
L3 Fast Master
Interconnect
L3 Fast Slave
Interconnect
THALIAIRQ
MPU Subsystem
PRCM
CORE_CLKOUTM4
(200 MHz) pd_gfx_gfx_l3_gclk
SYSCLK
MEMCLK
0 pd_gfx_gfx_fclk
/1, /2 CORECLK
1
PER_CLKOUTM2
(192 MHz)
SGX530 Integration
5.1.1 SGX530 Connectivity Attributes

The general connectivity attributes of the SGX530 are shown in the following table.
Table 5-1. SGX530 Connectivity Attributes

Attributes Type
Power domain GFX Domain
Clock domain SGX_CLK
Reset signals SGX_RST
Idle/Wakeup signals Smart Idle
Initiator Standby
Interrupt request THALIAIRQ (GFXINT) to MPU Subsystem
DMA request None
Physical address L3 Fast slave port
5.1.2 SGX530 Clock and Reset Management

The SGX530 uses separate functional and interface clocks. The SYSCLK is the clock for the slave
interface and runs at the L3F frequency. The MEMCLK is the clock for the memories and master interface
and also runs at the L3F frequency. The CORECLK is the functional clock. It can be sourced from either
the L3F clock (CORE_CLKOUTM4) or from the 192 MHz PER_CLKOUTM2 and can optionally be divided
by 2.
Table 5-2. SGX530 Clock Signals

Clock signal Max Freq Reference / Source Comments
SYSCLK 200 MHz CORE_CLKOUTM4 pd_gfx_gfx_l3_gclk
Interface clock From PRCM
MEMCLK 200 MHz CORE_CLKOUTM4 pd_gfx_gfx_l3_gclk
Memory Clock From PRCM
CORECLK 200 MHz PER_CLKOUTM2 or pd_gfx_gfx_fclk
Functional clock CORE_CLKOUTM4 From PRCM
5.1.3 SGX530 Pin List

The SGX530 module does not include any external interface pins.
5.2.1 SGX Block Diagram

The SGX subsystem is based on the POWERVR® SGX530 core from Imagination Technologies. The
architecture uses programmable and hard coded pipelines to perform various processing tasks required in
2D, 3D, and video processing. The SGX architecture comprises the following elements:
• Coarse grain scheduler
– Programmable data sequencer (PDS)
– Data master selector (DMS)
• Vertex data master (VDM)
• Pixel data master (PDM)
• General-purpose data master
• USSE
• Tiling coprocessor
• Pixel coprocessor
• Texturing coprocessor
• Multilevel cache
Figure 5-1 shows a block diagram of the SGX cores.
Figure 5-1. SGX Block Diagram
POWERVR
SGX530 Vertex data Coarse-grain
master scheduler Tiling
coprocessor
Universal
Prog. data
Pixel data sequencer scalable
master shader
engine
(USSE)
Data master Pixel
General-purpose selector coprocessor
data master
Power Texturing coprocessor Multilevel cache

management
control
register
block
MMU
SOCIF BIF
L3 interconnect L3 interconnect
sgx-003
5.2.2 SGX Elements Description

The coarse grain scheduler (CGS) is the main system controller for the POWERVR SGX architecture. It
consists of two stages, the DMS and the PDS. The DMS processes requests from the data masters and
determines which tasks can be executed given the resource requirements. The PDS then controls the
loading and processing of data on the USSE.
There are three data masters in the SGX core:
• The VDM is the initiator of transform and lighting processing within the system. The VDM reads an
input control stream, which contains triangle index data and state data. The state data indicates the
PDS program, size of the vertices, and the amount of USSE output buffer resource available to the
VDM. The triangle data is parsed to determine unique indices that must be processed by the USSE.
These are grouped together according to the configuration provided by the driver and presented to the
DMS.
• The PDM is the initiator of rasterization processing within the system. Each pixel pipeline processes
pixels for a different half of a given tile, which allows for optimum efficiency within each pipe due to
locality of data. It determines the amount of resource required within the USSE for each task. It merges
this with the state address and issues a request to the DMS for execution on the USSE.
• The general-purpose data master responds to events within the system (such as end of a pass of
triangles from the ISP, end of a tile from the ISP, end of render, or parameter stream breakpoint
event). Each event causes either an interrupt to the host or synchronized execution of a program on
the PDS. The program may, or may not cause a subsequent task to be executed on the USSE.
The USSE is a user-programmable processing unit. Although general in nature, its instructions and
features are optimized for three types of task: processing vertices (vertex shading), processing pixels
(pixel shading), and video/imaging processing.
The multilevel cache is a 2-level cache consisting of two modules: the main cache and the
mux/arbiter/demux/decompression unit (MADD). The MADD is a wrapper around the main cache module
designed to manage and format requests to and from the cache, as well as providing Level 0 caching for
texture and USSE requests. The MADD can accept requests from the PDS, USSE, and texture address
generator modules. Arbitration, as well as any required texture decompression, are performed between
the three data streams.
The texturing coprocessor performs texture address generation and formatting of texture data. It receives
requests from either the iterators or USSE modules and translates these into requests in the multilevel
cache. Data returned from the cache are then formatted according to the texture format selected, and sent
to the USSE for pixel-shading operations.
To process pixels in a tiled manner, the screen is divided into tiles and arranged as groups of tiles by the
tiling coprocessor. An inherent advantage of tiling architecture is that a large amount of vertex data can be
rejected at this stage, thus reducing the memory storage requirements and the amount of pixel processing
to be performed.
The pixel coprocessor is the final stage of the pixel-processing pipeline and controls the format of the final
pixel data sent to the memory. It supplies the USSE with an address into the output buffer and then USSE
returns the relevant pixel data. The address order is determined by the frame buffer mode. The pixel
coprocessor contains a dithering and packing function.
Chapter 6
Interrupts
This section describes the interrupts for the device.
Topic ........................................................................................................................... Page

6.2 Basic Programming Model ................................................................................. 534
6.3 ARM Cortex-A8 Interrupts .................................................................................. 543
6.4 Crypto DMA Events .......................................................................................... 547
6.5 PWM Events..................................................................................................... 549
6.6 Interrupt Controller Registers ............................................................................ 550
530 Interrupts SPRUH73Q – October 2011 – Revised December 2019


The interrupt controller processes incoming interrupts by masking and priority sorting to produce the
interrupt signals for the processor to which it is attached. Figure 6-1 shows the top-level view of interrupt
processing.
NOTE: FIQ is not available on general-purpose (GP) devices.
Figure 6-1. Interrupt Controller Block Diagram

IRQ_q
Interrupt of
bank p
Software Interrupt
ISR_SETp
Interrupt Input Status

ITRp
Mask
MIRp
Priority Threshold
THRESHOLD Priority
Comparator
If (INT Priority
>Threshold)
Interrupt Priority and

FIQ/IRQ Steering
ILRq
PRIORITY
FIQNIRQ IRQ/FIQ Selector
PENDING_IRQp
PENDING_FIQp
New Agreement Bits

Active Interrupt Nb,
Control Priority Sorting Spurious Flag
and Priority
NEWFIQAGR
FIQ SIR_FIQ
NEWIRQAGR Priority
IRQ Sorter FIQ_PRIORITY
Priority
Sorter
SIR_IRQ
IRQ_PRIORITY
IRQ Input FIQ Input
Processor
SPRUH73Q – October 2011 – Revised December 2019 Interrupts 531

6.1.1 Interrupt Processing
6.1.1.1 Input Selection

The INTC supports only level-sensitive incoming interrupt detection. A peripheral asserting an interrupt
maintains it until software has handled the interrupt and instructed the peripheral to deassert the interrupt.
A software interrupt is generated if the corresponding bit in the MPU_INTC.INTC_ISR_SETn register is set
(register bank number: n = [0,1,2,3] for the MPU subsystem INTC, 128 incoming interrupt lines are
supported). The software interrupt clears when the corresponding bit in the
MPU_INTC.INTC_ISR_CLEARn register is written. Typical use of this feature is software debugging.
6.1.1.2 Masking
6.1.1.2.1 Individual Masking

Detection of interrupts on each incoming interrupt line can be enabled or disabled independently by the
MPU_INTC.INTC_MIRn interrupt mask register. In response to an unmasked incoming interrupt, the INTC
can generate one of two types of interrupt requests to the processor:
• IRQ: low-priority interrupt request
• FIQ: fast interrupt request (Not available on General Purpose (GP) devices)
The type of interrupt request is determined by the MPU_INTC.INTC_ILRm[0] FIQNIRQ bit (m= [0,127]).
The current incoming interrupt status before masking is readable from the MPU_INTC.INTC_ITRn register.
After masking and IRQ/FIQ selection, and before priority sorting is done, the interrupt status is readable
from the MPU_INTC.INTC_PENDING_IRQn and MPU_INTC.INTC_PENDING_FIQn registers.
6.1.1.2.2 Priority Masking

To enable faster processing of high-priority interrupts, a programmable priority masking threshold is
provided (the MPU_INTC.INTC_THRESHOLD[7:0] PRIORITYTHRESHOLD field). This priority threshold
allows preemption by higher priority interrupts; all interrupts of lower or equal priority than the threshold
are masked. However, priority 0 can never be masked by this threshold; a priority threshold of 0 is treated
the same way as priority 1. PRIORITY and PRIORITYTHRESHOLD fields values can be set between 0x0
and 0x7F; 0x0 is the highest priority and 0x7F is the lowest priority. When priority masking is not
necessary, a priority threshold value of 0xFF disables the priority threshold mechanism. This value is also
the reset default for backward compatibility with previous versions of the INTC.
6.1.1.3 Priority Sorting

A priority level (0 being the highest) is assigned to each incoming interrupt line. Both the priority level and
the interrupt request type are configured by the MPU_INTC.INTC_ILRm register. If more than one
incoming interrupt with the same priority level and interrupt request type occur simultaneously, the highest-
numbered interrupt is serviced first. When one or more unmasked incoming interrupts are detected, the
INTC separates between IRQ and FIQ using the corresponding MPU_INTC.INTC_ILRm[0] FIQNIRQ bit.
The result is placed in INTC_PENDING_IRQn or INTC_PENDING_FIQn If no other interrupts are currently
being processed, INTC asserts IRQ/FIQ and starts the priority computation. Priority sorting for IRQ and
FIQ can execute in parallel. Each IRQ/FIQ priority sorter determines the highest priority interrupt number
and that number is placed in the corresponding MPU_INTC.INTC_SIR_IRQ[6:0] ACTIVEIRQ field or
MPU_INTC.INTC_SIR_FIQ[6:0] ACTIVEFIQ field. The value is preserved until the corresponding
MPU_INTC.INTC_CONTROL NEWIRQAGR or NEWFIQAGR bit is set. Once the interrupting peripheral
device has been serviced and the incoming interrupt deasserted, the user must write to the appropriate
NEWIRQAGR or NEWFIQAGR bit to indicate to the INTC the interrupt has been handled. If there are any
pending unmasked incoming interrupts for this interrupt request type, the INTC restarts the appropriate
priority sorter; otherwise, the IRQ or FIQ interrupt line is deasserted.

6.1.2 Register Protection

If the MPU_INTC.INTC_PROTECTION[0] PROTECTION bit is set, access to the INTC registers is
restricted to privileged mode. Access to the MPU_INTC.INTC_PROTECTION register is always restricted
to privileged mode. For more information, see Section 6.6.1.7, INTC_PROTECTION Register (offset =
4Ch) [reset = 0h].
6.1.3 Module Power Saving

The INTC provides an auto-idle function in its three clock domains:
• Interface clock
• Functional clock
• Synchronizer clock
The interface clock auto-idle power-saving mode is enabled if the MPU_INTC.INTC_SYSCONFIG[0]
AUTOIDLE bit is set to 1. When this mode is enabled and there is no activity on the bus interface, the
interface clock is disabled internally to the module, thus reducing power consumption. When there is new
activity on the bus interface, the interface clock restarts without any latency penalty. After reset, this mode
is disabled, by default. The functional clock auto-idle power-saving mode is enabled if the
MPU_INTC.INTC_IDLE[0] FUNCIDLE bit is set to 0. When this mode is enabled and there is no active
interrupt (IRQ or FIQ interrupt being processed or generated) or no pending incoming interrupt, the
functional clock is disabled internally to the module, thus reducing power consumption.
When a new unmasked incoming interrupt is detected, the functional clock restarts and the INTC
processes the interrupt. If this mode is disabled, the interrupt latency is reduced by one cycle. After reset,
this mode is enabled, by default. The synchronizer clock allows external asynchronous interrupts to be
resynchronized before they are masked. The synchronizer input clock has an auto-idle power-saving
mode enabled if the MPU_INTC.INTC_IDLE[1] TURBO bit is set to 1. If the auto-idle mode is enabled, the
standby power is reduced, but the IRQ or FIQ interrupt latency increases from four to six functional clock
cycles. This feature can be enabled dynamically according to the requirements of the device. After reset,
this mode is disabled, by default.
6.1.4 Error Handling

The following accesses will cause an error:
• Privilege violation (attempt to access PROTECTION register in user mode or any register in user mode
if Protection bit is set)
• Unsupported commands
The following accesses will not cause any error response:
• Access to a non-decoded address
• Write to a read-only register
6.1.5 Interrupt Handling

The IRQ/FIQ interrupt generation takes four INTC functional clock cycles (plus or minus one cycle) if the
MPU_INTC.INTC_IDLE[1] TURBO bit is set to 0. If the TURBO bit is set to 1, the interrupt generation
takes six cycles, but power consumption is reduced while waiting for an interrupt. These latencies can be
reduced by one cycle by disabling functional clock auto-idle (MPU_INTC.INTC_IDLE[0] FUNCIDLE bit set
to 1), but power consumption is increased, so the benefit is minimal.
To minimize interrupt latency when an unmasked interrupt occurs, the IRQ or FIQ interrupt is generated
before priority sorting completion. The priority sorting takes 10 functional clock cycles, which is less than
the minimum number of cycles required for the MPU to switch to the interrupt context after reception of the
IRQ or FIQ event.
Any read of the MPU_INTC.INTC_SIR_IRQ or MPU_INTC.INTC_SIR_FIQ register during the priority
sorting process stalls until priority sorting is complete and the relevant register is updated. However, the
delay between the interrupt request being generated and the interrupt service routine being executed is
such that priority sorting always completes before the MPU_INTC.INTC_SIR_IRQ or
MPU_INTC.INTC_SIR_FIQ register is read.

Basic Programming Model www.ti.com
6.2 Basic Programming Model
6.2.1 Initialization Sequence

1. Program the MPU_INTC.INTC_SYSCONFIG register: If necessary, enable the interface clock
autogating by setting the AUTOIDLE bit.
2. Program the MPU_INTC.INTC_IDLE register: If necessary, disable functional clock autogating or
enable synchronizer autogating by setting the FUNCIDLE bit or TURBO bit accordingly.
3. Program the MPU_INTC.INTC_ILRm register for each interrupt line: Assign a priority level and set the
FIQNIRQ bit for an FIQ interrupt (by default, interrupts are mapped to IRQ and priority is 0x0 [highest]).
4. Program the MPU_INTC.INTC_MIRn register: Enable interrupts (by default, all interrupt lines are
masked). NOTE: To program the MPU_INTC.INTC_MIRn register, the MPU_INTC.INTC_MIR_SETn
and MPU_INTC.INTC_MIR_CLEARn registers are provided to facilitate the masking, even if it is
possible for backward-compatibility to write directly to the MPU_INTC.INTC_MIRn register.
6.2.2 INTC Processing Sequence

After the INTC_MIRn and INTC_ILRm registers are configured to enable and assign priorities to incoming
interrupts, the interrupt is processed as explained in the following subsections. IRQ and FIQ processing
sequences are quite similar, the differences for the FIQ sequence are shown after a '/' character in the
code below.
1. One or more unmasked incoming interrupts (M_IRQ_n signals) are received and IRQ or FIQ outputs
(IRQ/FIQ) are not currently asserted.
2. If the INTC_ILRm[0] FIQNIRQ bit is cleared to 0, the MPU_INTC_IRQ output signal is generated. If the
FIQNIRQ bit is set to 1, the MPU_INTC_FIQ output signal is generated.
3. The INTC performs the priority sorting and updates the INTC_SIR_IRQ[6:0] ACTIVEIRQ
/INTC_SIR_FIQ[6:0] ACTIVEFIQ field with the current interrupt number.
4. During priority sorting, if the IRQ/FIQ is enabled at the host processor side, the host processor
automatically saves the current context and executes the ISR as follows.
The ARM host processor automatically performs the following actions in pseudo code:
LR = PC + 4 /* return link */
SPSR = CPSR /* Save CPSR before execution */
CPSR[5] = 0 /* Execute in ARM state */
CPSR[7] = 1 /* Disable IRQ */
CPSR[8] = 1 /* Disable Imprecise Data Aborts */
CPSR[9] = CP15_reg1_EEbit /* Endianness on exception entry */
if interrupt == IRQ then
CPSR[4:0] = 0b10010 /* Enter IRQ mode */
if high vectors configured then
PC = 0xFFFF0018
else
PC = 0x00000018 /* execute interrupt vector */
else if interrupt == FIQ then
CPSR[4:0] = 0b10001 /* Enter FIQ mode */
CPSR[6] = 1 /* Disable FIQ */
if high vectors configured then
PC = 0xFFFF001C
else
PC = 0x0000001C /* execute interrupt vector */
endif

www.ti.com Basic Programming Model
5. The ISR saves the remaining context, identifies the interrupt source by reading the
ACTIVEIRQ/ACTIVEFIQ field, and jumps to the relevant subroutine handler as follows:
CAUTION
The code in steps 5 and 7 is an assembly code compatible with ARM
architecture V6 and V7. This code is developed for the Texas Instruments Code
Composer Studio tool set. It is a draft version, only tested on an emulated
environment.
;INTC_SIR_IRQ/INTC_SIR_FIQ register address

INTC_SIR_IRQ_ADDR/INTC_SIR_FIQ_ADDR .word 0x48200040/0x48200044
; ACTIVEIRQ bit field mask to get only the bit field
ACTIVEIRQ_MASK .equ 0x7F
_IRQ_ISR/_FIQ_ISR:
; Save the critical context
STMFD SP!, {R0-R12, LR} ; Save working registers and the Link register
MRS R11, SPSR ; Save the SPSR into R11
; Get the number of the highest priority active IRQ/FIQ
LDR R10, INTC_SIR_IRQ_ADDR/INTC_SIR_FIQ_ADDR
LDR R10, [R10] ; Get the INTC_SIR_IRQ/INTC_SIR_FIQ register
AND R10, R10, #ACTIVEIRQ_MASK ; Apply the mask to get the active IRQ number
; Jump to relevant subroutine handler
LDR PC, [PC, R10, lsl #2] ; PC base address points this instruction + 8
NOP ; To index the table by the PC
; Table of handler start addresses
.word IRQ0handler ;For IRQ0 of BANK0
.word IRQ1handler
.word IRQ2handler
6. The subroutine handler executes code specific to the peripheral generating the interrupt by handling
the event and deasserting the interrupt condition at the peripheral side.
; IRQ0 subroutine
IRQ0handler:
; Save working registers
STMFD SP!, {R0-R1}
; Now read-modify-write the peripheral module status register
; to de-assert the M_IRQ_0 interrupt signal
; De-Assert the peripheral interrupt
MOV R0, #0x7 ; Mask for 3 flags
LDR R1, MODULE0_STATUS_REG_ADDR ; Get the address of the module Status Register
STR R0, [R1] ; Clear the 3 flags
; Restore working registers LDMFD SP!, {R0-R1}
; Jump to the end part of the ISR
B IRQ_ISR_end/FIQ_ISR_end

7. After the return of the subroutine, the ISR sets the NEWIRQAGR/NEWFIQAGR bit to enable the
processing of subsequent pending IRQs/FIQs and to restore ARM context in the following code.
Because the writes are posted on an Interconnect bus, to be sure that the preceding writes are done
before enabling IRQs/FIQs, a Data Synchronization Barrier is used. This operation ensure that the
IRQ/FIQ line is de-asserted before IRQ/FIQ enabling. After that, the INTC processes any other pending
interrupts or deasserts the IRQ/FIQ signal if there is no interrupt.
; INTC_CONTROL register address
INTC_CONTROL_ADDR .word 0x48200048;
NEWIRQAGR/NEWFIQAGR bit mask to set only the NEWIRQAGR/NEWFIQAGR bit
NEWIRQAGR_MASK/NEWFIQAGR_MASK .equ 0x01/0x02
IRQ_ISR_end/FIQ_ISR_end:
; Allow new IRQs/FIQs at INTC side
; The INTC_CONTROL register is a write only register so no need to write back others bits
MOV R0, #NEWIRQAGR_MASK/NEWFIQAGR_MASK ; Get the NEWIRQAGR/NEWFIQAGR bit position
LDR R1, INTC_CONTROL_ADDR
STR R0, [R1] ; Write the NEWIRQAGR/NEWFIQAGR bit to allow new IRQs/FIQ
; Data Synchronization Barrier
MOV R0, #0
MCR P15, #0, R0, C7, C10, #4
; restore critical context
MSR SPSR, R11 ; Restore the SPSR from R11
LDMFD SP!, {R0-R12, LR} ; Restore working registers and Link register
; Return after handling the interrupt
SUBS PC, LR, #4
8. After the ISR return, the ARM automatically restores its context as follows:
CPSR = SPSR
PC = LR
Figure 6-2 shows the IRQ/FIQ processing sequence from the originating device peripheral module to the
main program interruption.
The priority sorting mechanism is frozen during an interrupt processing sequence. If an interrupt condition
occurs during this time, the interrupt is not lost. It is sorted when the NEWIRQAGR/NEWFIQAGR bit is set
(priority sorting is reactivated).

Figure 6-2. IRQ/FIQ Processing Sequence

Hardware Software
SOC Peripheral Module
Step 1 M_IRQ_n Asserted
MPU INTC
If the IRQ_n is not masked and configured as an IRQ/FIQ,
the MPU_INTC_IRQ/MPU_INTC_FIQ line is asserted.
MPU_INTC_IRQ/
Step 2
MPU_INTC_FIQ Asserted Main Program
ARM Host Processor (Step 4) ? Execution of instruction number 1

? Execution of instruction number N
If FIQs are enabled (F==0):
? Finish the current instruction number N
? Store address of next instruction to be
executed in the Link Register
? Save CPSR before execution in the SPSR ISR in IRQ/FIQ Mode (Step 5)
Branch
? Enter ARM FIQ mode
? Save ARM critical context
? Disable IRQs and FIQs at ARM side
? Identify interrupt source
? Execute the interrupt vector.
? Branch to relevant interrupt subroutine handler
Branch
Relevant Subroutine Handler in IRQ/FIQ Mode (Step 6)
? Handles the event (functional procedure)

? Deassert the interrupt M_IRQ_n at SOC peripheral
module side.
Branch
ISR in IRQ/FIQ Mode (Step 7)
? Allow a new IRQ/FIQ at INTC side by setting the

Return NEWIRQAGR/NEWFIQAGR bit to 1.
ARM Host Processor (Step 8) ? Restore ARM critical context.
? Restore the whole CPSR Return

? Restore the PC Main Program
? Execution of instruction number N + 1

6.2.3 INTC Preemptive Processing Sequence

Preemptive interrupts, also called nested interrupts, can reduce the latencies for higher priority interrupts.
A preemptive ISR can be suspended by a higher priority interrupt. Thus, the higher priority interrupt can be
served immediately. Nested interrupts must be used carefully to avoid using corrupted data. Programmers
must save corruptible registers and enable IRQ or FIQ at ARM side. IRQ and FIQ processing sequences
are quite similar, the differences for the FIQ sequence are shown after a '/' character in the code below.
To enable IRQ/FIQ preemption by higher priority IRQs/FIQs, programers can follow this procedure to write
the ISR.
At the beginning of an IRQ/FIQ ISR:
1. Save the ARM critical context registers.
2. Save the INTC_THRESHOLD PRIORITYTHRESHOLD field before modifying it.
3. Read the active interrupt priority in the INTC_IRQ_PRIORITY IRQPRIORITY/INTC_FIQ_PRIORITY
FIQPRIORITY field and write it to the PRIORITYTHRESHOLD(1) field.
4. Read the active interrupt number in the INTC_SIR_IRQ[6:0] ACTIVEIRQ/INTC_SIR_FIQ[6:0]
ACTIVEFIQ field to identify the interrupt source.
5. Write 1 to the appropriate INTC_CONTROL NEWIRQAGR and (2) NEWFIQAGR bit while an interrupt
is still processing to allow only higher priority interrupts to preempt.
6. Because the writes are posted on an Interconnect bus, to be sure that the preceding writes are done
before enabling IRQs/FIQs, a Data Synchronization Barrier is used. This operation ensure that the IRQ
line is de-asserted before IRQ/FIQ enabling.
7. Enable IRQ/FIQ at ARM side.
8. Jump to the relevant subroutine handler.

The following sample code shows the previous steps:
CAUTION
The following code is an assembly code compatible with ARM architecture V6
and V7. This code is developed for the Texas Instruments Code Composer
Studio tool set. It is a draft version, only tested on an emulated environment.
; bit field mask to get only the bit field

ACTIVEPRIO_MASK .equ 0x7F
_IRQ_ISR:
; Step 1 : Save the critical context
STMFD SP!, {R0-R12, LR} ; Save working registers
MRS R11, SPSR ; Save the SPSR into R11
; Step 2 : Save the INTC_THRESHOLD register into R12
LDR R0, INTC_THRESHOLD_ADDR
LDR R12, [R0]
(1) The priority-
threshold mechanism is enabled automatically when writing a priority in the range of 0x00 to
0x3F. Writing a value of 0xFF (reset default) disables the priority-
threshold mechanism. Values between 0x3F and 0xFF must not be used. When the hardware-
priority threshold is in use, the priorities of interrupts selected as FIQ or IRQ become linked
otherwise, they are independent. When they are linked, all FIQ priorities must be set higher than
all IRQ priorities to maintain the relative priority of FIQ over IRQ.
(2) When handling FIQs using the priority-
threshold mechanism, both NEWFIQAGR and NEWIRQAGR bits must be written at the same time to ensure
that the new priority threshold is applied while an IRQ sort is in progress. This IRQ will not
have been seen by the ARM, as it will have been masked on entry to the FIQ ISR. However, the
source of the IRQ remains active and it is finally processed when the priority threshold falls to
a priority sufficiently low to allow it to be processed. The precaution of writing to New FIQ
Agreement is not required during an IRQ ISR, as FIQ sorting is not affected (provided all FIQ
priorities are higher than all IRQ priorities).
; Step 3 : Get the priority of the highest priority active IRQ
LDR R1, INTC_IRQ_PRIORITY_ADDR/INTC_FIQ_PRIORITY_ADDR
LDR R1, [R1] ; Get the INTC_IRQ_PRIORITY/INTC_FIQ_PRIORITY register
AND R1, R1, #ACTIVEPRIO_MASK ; Apply the mask to get the priority of the IRQ
STR R1, [R0] ; Write it to the INTC_THRESHOLD register
; Step 4 : Get the number of the highest priority active IRQ
LDR R10, INTC_SIR_IRQ_ADDR/INTC_SIR_FIQ_ADDR
LDR R10, [R10] ; Get the INTC_SIR_IRQ/INTC_SIR_FIQ register
AND R10, R10, #ACTIVEIRQ_MASK ; Apply the mask to get the active IRQ number
; Step 5 : Allow new IRQs and FIQs at INTC side
MOV R0, #0x1/0x3 ; Get the NEWIRQAGR and NEWFIQAGR bit position
LDR R1, INTC_CONTROL_ADDR
STR R0, [R1] ; Write the NEWIRQAGR and NEWFIQAGR bit
; Step 6 : Data Synchronization Barrier
MOV R0, #0
MCR P15, #0, R0, C7, C10, #4
; Step 7 : Read-modify-write the CPSR to enable IRQs/FIQs at ARM side
MRS R0, CPSR ; Read the status register
BIC R0, R0, #0x80/0x40 ; Clear the I/F bit
MSR CPSR, R0 ; Write it back to enable IRQs
; Step 8 : Jump to relevant subroutine handler
LDR PC, [PC, R10, lsl #2] ; PC base address points this instruction + 8
NOP ; To index the table by the PC
; Table of handler start addresses
.word IRQ0handler ;IRQ0 BANK0
.word IRQ1handler
.word IRQ2handler

After the return of the relevant IRQ/FIQ subroutine handle:

1. Disable IRQs/FIQs at ARM side.
2. Restore the INTC_THRESHOLD PRIORITYTHRESHOLD field.
3. Restore the ARM critical context registers.
The following sample code shows the three previous steps:
CAUTION
The following code is an assembly code compatible with ARM architecture V6
and V7. This code is developed for the Texas Instruments Code Composer
Studio tool set. It is a draft version, only tested on an emulated environment.
IRQ_ISR_end:
; Step 1 : Read-modify-write the CPSR to disable IRQs/FIQs at ARM side
MRS R0, CPSR ; Read the CPSR
ORR R0, R0, #0x80/0x40 ; Set the I/F bit
MSR CPSR, R0 ; Write it back to disable IRQs
; Step 2 : Restore the INTC_THRESHOLD register from R12
LDR R0, INTC_THRESHOLD_ADDR
STR R12, [R0]
; Step 3 : Restore critical context
MSR SPSR, R11 ; Restore the SPSR from R11
LDMFD SP!, {R0-R12, LR} ; Restore working registers and Link register
; Return after handling the interrupt
SUBS PC, LR, #4
Figure 6-3 shows the nested IRQ/FIQ processing sequence from the originating device peripheral module
to the main program interruption.

Figure 6-3. Nested IRQ/FIQ Processing Sequence

Hardware Software
SOC Peripheral Module
Step 1 M_IRQ_n Asserted
MPU INTC
If the IRQ_n is not masked and configured as an IRQ/FIQ,
the MPU_INTC_IRQ/MPU_INTC_FIQ line is asserted.
MPU_INTC_IRQ/
Step 2
MPU_INTC_FIQ Asserted Main Program
ARM Host Processor ? Execution of instruction number 1

? Execution of instruction number N
If FIQs are enabled (F==0):
? Finish the current instruction number N
? Store address of next instruction to be
executed in the Link Register
? Save CPSR before execution in the SPSR ISR in IRQ/FIQ Mode (Step 5)
Branch
? Enter ARM FIQ mode
? Save ARM critical context
? Disable IRQs and FIQs at ARM side
? Save INTC priority threshold
? Execute the interrupt vector.
? Get active IRQ priority
? Set the IRQ priority to priority threshold
? Identify interrupt source
? Allow a new IRQ and FIQ at INTC side by setting
the NEWIRQAGR and NEWFIQAGR bits to 1
? Enable IRQ/FIQ at ARM side
? Jump to relevant ISR handler
Branch
Relevant Subroutine Handler in IRQ/FIQ Mode
? Handles the event (functional procedure)

? Deassert the interrupt M_IRQ_n at SOC peripheral
module side.
Branch
ISR in IRQ/FIQ Mode
? Allow a new IRQ/FIQ at ARM side.

Return ? Restore the INTC priority threshold.
ARM Host Processor (Step 8) ? Restore ARM critical context.
? Restore the whole CPSR Return
? Restore the PC Main Program
? Execution of instruction number N + 1

6.2.4 Interrupt Preemption

If wanting to enable pre-emption by higher priority interrupts, the ISR should read the active interrupt
priority and write it to the priority threshold register. Writing a ‘1’ to the appropriate NEW_IRQ_AGR or
NEW_FIQ_AGR bits of the CONTROL register while still processing the interrupt will now allow only
higher priority interrupts to pre-empt.
For each level of pre-emption, the programmer must save the threshold value before modifying it and
restore it at the end of that ISR level.
The priority threshold mechanism is enabled automatically when writing a priority in the range of 0 to 7Fh
as will be read from the IRQ_PRIORITY and FIQ_PRIORITY registers. Writing a value of FFh (reset
default) disables the priority threshold mechanism.
When the hardware priority threshold is in use the priorities of interrupts selected as FIQ or IRQ become
linked, otherwise they are independent. When linked, it is required that all FIQ priorities be set higher than
all IRQ priorities to maintain the relative priority of FIQ over IRQ.
When handling FIQs using the priority threshold mechanism, it is required to write both New FIQ
Agreement and New IRQ Agreement bits at the same time to cover the case that the new priority
threshold is applied while an IRQ sorting is in progress. This IRQ will not have been seen by the ARM as
it will have been masked on entry to the FIQ ISR. However, the source of the IRQ will remain active and it
will be finally processed when the priority threshold falls to a low enough priority. The precaution of writing
to New FIQ Agreement (as well as New IRQ Agreement) is not required during an IRQ ISR as FIQ sorting
will not be affected (provided all FIQ priorities are higher than all IRQ priorities).
6.2.5 ARM A8 INTC Spurious Interrupt Handling

The spurious flag indicates whether the result of the sorting (a window of 10 INTC functional clock cycles
after the interrupt assertion) is invalid. The sorting is invalid if:
• The interrupt that triggered the sorting is no longer active during the sorting.
• A change in the mask has affected the result during the sorting time.
As a result, the values in the INTC_MIRn, INTC_ILRm, or INTC_MIR_SETn registers must not be
changed while the corresponding interrupt is asserted. Only the active interrupt input that triggered the
sort can be masked before it turn on the sort. If these registers are changed within the 10-cycle window
after the interrupt assertion. The resulting values of the following registers become invalid:
• INTC_SIR_IRQ
• INTC_SIR_FIQ
• INTC_IRQ_PRIORITY
• INTC_FIQ_PRIORITY
This condition is detected for both IRQ and FIQ, and the invalid status is flagged across the
SPURIOUSIRQFLAG (see NOTE 1) and SPURIOUSFIQFLAG (see NOTE 2) bit fields in the SIR and
PRIORITY registers. A 0 indicates valid and a 1 indicates invalid interrupt number and priority. The invalid
indication can be tested in software as a false register value.
NOTE:
1. The INTC_SIR_IRQ[31:7] SPURIOUSIRQFLAG bit field is a copy of the
INTC_IRQ_PRIORITY[31:7] SPURIOUSIRQFLAG bit field.
2. The INTC_SIR_FIQ[31:7] SPURIOUSFIQFLAG bit field is a copy of the
INTC_FIQ_PRIORITY[31:7] SPURIOUSFIQFLAG bit field.

www.ti.com ARM Cortex-A8 Interrupts
6.3 ARM Cortex-A8 Interrupts
Table 6-1. ARM Cortex-A8 Interrupts

Int Number Acronym/name Source Signal Name
0 EMUINT MPU Subsystem Internal Emulation interrupt
(EMUICINTR)
1 COMMTX MPU Subsystem Internal CortexA8 COMMTX
2 COMMRX MPU Subsystem Internal CortexA8 COMMRX
3 BENCH MPU Subsystem Internal CortexA8 NPMUIRQ
4 ELM_IRQ ELM Sinterrupt (Error location
process completion)
5 SSM_WFI_IRQ MPU Subsystem Internal MPU s/s Secure State Machine
(SSM) Wait for Interrupt (WFI)
tracking mechanism
5 Reserved
6 SSM_IRQ MPU Subsystem Internal MPU s/s Secure State Machine
(SSM) interrupt generation for Public
FIQ support
6 Reserved
7 NMI External Pin (active low) (1) nmi_int
8 SEC_EVNT Firewalls security_events_irq
8 Reserved
9 L3DEBUG L3 l3_FlagMux_top_FlagOut1
10 L3APPINT L3 l3_FlagMux_top_FlagOut0
11 PRCMINT PRCM irq_mpu
12 EDMACOMPINT TPCC (EDMA) tpcc_int_pend_po0
13 EDMAMPERR TPCC (EDMA) tpcc_mpint_pend_po
14 EDMAERRINT TPCC (EDMA) tpcc_errint_pend_po
15 WDT0INT WDTIMER0 PO_INT_PEND
15 Reserved
16 ADC_TSC_GENINT ADC_TSC (Touchscreen gen_intr_pend
Controller)
17 USBSSINT USBSS usbss_intr_pend
18 USBINT0 USBSS usb0_intr_pend
19 USBINT1 USBSS usb1_intr_pend
20 PRU_ICSS_EVTOUT0 pr1_host[0] output/events pr1_host_intr0_intr_pend
exported from PRU-ICSS (2)
28 MMCSD1INT MMCSD1 SINTERRUPTN
(1)
For differences in operation based on AM335x silicon revisions, see Section 1.2, Silicon Revision Functional Differences and
Enhancements.
(2)
pr1_host_intr[0:7] corresponds to Host-2 to Host-9 of the PRU-ICSS interrupt controller.

ARM Cortex-A8 Interrupts www.ti.com
Table 6-1. ARM Cortex-A8 Interrupts (continued)

30 I2C2INT I2C2 POINTRPEND
31 eCAP0INT eCAP0 event/interrupt ecap_intr_intr_pend
32 GPIOINT2A GPIO 2 POINTRPEND1
33 GPIOINT2B GPIO 2 POINTRPEND2
34 USBWAKEUP USBSS slv0p_Swakeup
35 PCIeWAKEUP PCIe sle_idlep_SWakeup
35 Reserved
36 LCDCINT LCDC lcd_irq
37 GFXINT SGX530 THALIAIRQ
38 Reserved
39 ePWM2INT eHRPWM2 (PWM Subsystem) epwm_intr_intr_pend
40 3PGSWRXTHR0 CPSW (Ethernet) c0_rx_thresh_pend
(RX_THRESH_PULSE)
41 3PGSWRXINT0 (RX_PULSE) CPSW (Ethernet) c0_rx_pend
42 3PGSWTXINT0 (TX_PULSE) CPSW (Ethernet) c0_tx_pend
43 3PGSWMISC0 (MISC_PULSE) CPSW (Ethernet) c0_misc_pend
44 UART3INT UART3 niq
47 eCAP1INT eCAP1 (PWM Subsystem) ecap_intr_intr_pend
48 PCIINT0 PCIe pcie_int_i_intr0_pend
48 Reserved
49 Reserved
50 Reserved
51 Reserved
52 DCAN0_INT0 DCAN0 dcan_intr0_intr_pend
54 DCAN0_PARITY DCAN0 dcan_uerr_intr_pend
57 DCAN1_PARITY DCAN1 dcan_uerr_intr_pend
58 ePWM0_TZINT eHRPWM0 TZ interrupt (PWM epwm_tz_intr_pend
Subsystem)
Subsystem)
Subsystem)
61 eCAP2INT eCAP2 (PWM Subsystem) ecap_intr_intr_pend
65 McSPI0INT McSPI0 SINTERRUPTN
66 TINT0 Timer0 POINTR_PEND
67 TINT1_1MS DMTIMER_1ms POINTR_PEND
68 TINT2 DMTIMER2 POINTR_PEND

www.ti.com ARM Cortex-A8 Interrupts

75 RTCINT RTC timer_intr_pend
76 RTCALARMINT RTC alarm_intr_pend
77 MBINT0 Mailbox0 (mail_u0_irq) initiator_sinterrupt_q_n0
78 M3_TXEV Wake M3 Subsystem TXEV
79 eQEP0INT eQEP0 (PWM Subsystem) eqep_intr_intr_pend
80 MCATXINT0 McASP0 mcasp_x_intr_pend
81 MCARXINT0 McASP0 mcasp_r_intr_pend
82 MCATXINT1 McASP1 mcasp_x_intr_pend
83 MCARXINT1 McASP1 mcasp_r_intr_pend
84 Reserved
85 Reserved
90 DMA_INTR_PIN2 External DMA/Interrupt Pin2 pi_x_dma_event_intr2
(xdma_event_intr2)
91 WDT1INT (Public Watchdog) WDTIMER1 PO_INT_PEND
100 GPMCINT GPMC gpmc_sinterrupt
101 DDRERR0 EMIF sys_err_intr_pend
102 AES0_IRQ_S AES module 0 Interrupt secure AES_SINTREQUEST_S
side
102 Reserved
103 AES0_IRQ_P AES module 0 Interrupt public AES_SINTREQUEST_P
side
103 Reserved
104 Reserved
105 Reserved
106 Reserved
107 Reserved
108 Reserved
109 Reserved
110 Reserved
111 Reserved

ARM Cortex-A8 Interrupts www.ti.com

108 SHA_IRQ_S SHA2 crypto-accelerator SHA_SINTREQUEST_S
secure side
109 SHA_IRQ_P SHA2 crypto-accelerator public SHA_SINTREQUEST_P
side
110 FPKA_SINTREQUEST_S PKA PKA_SINTREQUEST_S
111 RNG_IRQ RNG TRNG_intr_pend
112 TCERRINT0 TPTC0 tptc_erint_pend_po
115 ADC_TSC_PENINT ADC_TSC pen_intr_pend
116 Reserved
117 Reserved
118 Reserved
119 Reserved
120 SMRFLX_MPU subsystem Smart Reflex 0 intrpend
121 SMRFLX_Core Smart Reflex 1 intrpend
122 Reserved
(xdma_event_intr0)
(xdma_event_intr1)
125 McSPI1INT McSPI1 SINTERRUPTN
126 Reserved
127 Reserved

www.ti.com Crypto DMA Events
6.4 Crypto DMA Events
Table 6-2. Crypto DMA Events

Event# Event Name Source Module
1 AES0_s_dma_ctx_in_req AES Module 0: Request a new context on
the Secure HIB
2 AES0_s_dma_data_in_req AES Module 0: Request input data on the
Secured HIB
3 AES0_s_dma_data_out_req AES Module 0: Request output data read
on the Secured HIB
4 AES0_p_dma_ctx_in_req AES Module 0: Request a new context on
the Public HIB
5 AES0_p_dma_data_in_req AES Module 0: Request input data on the
Public HIB
6 AES0_p_dma_data_out_req AES Module 0: Request output data read
on the Public HIB
7 AES1_s_dma_ctx_in_req AES Module 1: Request a new context on
the Secured HIB
8 AES1_s_dma_data_in_req AES Module 1: Request input data on the
Secured HIB
9 AES1_s_dma_data_out_req AES Module 1: Request output data read
on the Secured HIB
10 AES1_p_dma_ctx_in_req AES Module 1: Request a new context on
the Public HIB
11 AES1_p_dma_data_in_req AES Module 1: Request input data on the
Public HIB
12 AES1_p_dma_data_out_req AES Module 1: Request output data read
on the Public HIB
13 Reserved
14 Reserved
15 DES_s_dma_ctx_in_req DES Module: Request a new context on
the secure HIB
16 DES_s_dma_data_in_req DES Module: Request input data on the
secure HIB
17 DES_s_dma_data_out_req DES Module: Request output data read on
the secure HIB
18 DES_p_dma_ctx_in_req DES Module: Request a new context on
the public HIB
19 DES_p_dma_data_in_req DES Module: Request input data on the
public HIB
20 DES_p_dma_data_out_req DES Module: Request output data read on
the public HIB
21 SHA2_dma_ctxin_s SHA2MD5 Module 1: Request a context
on secure HIB
22 SHA2_dma_din_s SHA2MD5 Module 1: Request input data
on secure HIB
23 SHA2_dma_ctxout_s SHA2MD5 Module 1: Request output
data/context on secure HIB
24 SHA2_dma_ctxin_p SHA2MD5 Module 1: Request a context
on public HIB
25 SHA2_dma_din_p SHA2MD5 Module 1: Request input data
on public HIB
26 SHA2_dma_ctxout_p SHA2MD5 Module 1: Request output
data/context on public HIB
27 AES0_s_dma_context_out_req AES Module 0: Request the authentication
result (TAG) or result IV read on the
Secured HIB

Crypto DMA Events www.ti.com
Table 6-2. Crypto DMA Events (continued)

Event# Event Name Source Module
28 AES0_p_dma_context_out_req AES Module 0: Request the authentication
Public HIB
29 AES1_s_dma_context_out_req AES Module 1: Request the authentication
Secured HIB
30 AES1_p_dma_context_out_req AES Module 1: Request the authentication
Public HIB
31 Reserved
32 Reserved

www.ti.com PWM Events
6.5 PWM Events
Table 6-3. Timer and eCAP Event Capture

Event # IP Interrupt Name/Pin
For Timer 5 MUX input from IO signal TIMER5 IO pin
TIMER5
For Timer 6 MUX input from IO signal TIMER6 IO pin
TIMER6
0 For Timer 7 MUX input from IO signal TIMER7 IO pin
TIMER7
For eCAP 0 MUX input from IO signal eCAP0 IO pin
eCAP0
eCAP1
eCAP2
1 UART0 UART0INT
2 UART1 UART1INT
3 UART2 UART2INT
4 UART3 UART3INT
5 UART4 UART4INT
6 UART5 UART5INT
7 3PGSW 3PGSWRXTHR0
8 3PGSW 3PGSWRXINT0
9 3PGSW 3PGSWTXINT0
10 3PGSW 3PGSWMISC0
11 McASP0 MCATXINT0
12 McASP0 MCARXINT0
13 McASP1 MCATXINT1
14 McASP1 MCARXINT1
17 GPIO 0 GPIOINT0A
18 GPIO 0 GPIOINT0B
19 GPIO 1 GPIOINT1A
20 GPIO 1 GPIOINT1B
21 GPIO 2 GPIOINT2A
22 GPIO 2 GPIOINT2B
23 GPIO 3 GPIOINT3A
24 GPIO 3 GPIOINT3B
25 DCAN0 DCAN0_INT0
26 DCAN0 DCAN0_INT1
27 DCAN0 DCAN0_PARITY
28 DCAN1 DCAN1_INT0
29 DCAN1 DCAN1_INT1
30 DCAN1 DCAN1_PARITY

Interrupt Controller Registers www.ti.com
6.6 Interrupt Controller Registers
NOTE: FIQ is not available on general-purpose (GP) devices.
6.6.1 INTC Registers

Table 6-4 lists the memory-mapped registers for the INTC. All register offset addresses not listed in
Table 6-4 should be considered as reserved locations and the register contents should not be modified.
Table 6-4. INTC Registers

0h INTC_REVISION Section 6.6.1.1
10h INTC_SYSCONFIG Section 6.6.1.2
14h INTC_SYSSTATUS Section 6.6.1.3
40h INTC_SIR_IRQ Section 6.6.1.4
44h INTC_SIR_FIQ Section 6.6.1.5
48h INTC_CONTROL Section 6.6.1.6
4Ch INTC_PROTECTION Section 6.6.1.7
50h INTC_IDLE Section 6.6.1.8
60h INTC_IRQ_PRIORITY Section 6.6.1.9
64h INTC_FIQ_PRIORITY Section 6.6.1.10
68h INTC_THRESHOLD Section 6.6.1.11
80h INTC_ITR0 Section 6.6.1.12
84h INTC_MIR0 Section 6.6.1.13
88h INTC_MIR_CLEAR0 Section 6.6.1.14
8Ch INTC_MIR_SET0 Section 6.6.1.15
90h INTC_ISR_SET0 Section 6.6.1.16
94h INTC_ISR_CLEAR0 Section 6.6.1.17
98h INTC_PENDING_IRQ0 Section 6.6.1.18
9Ch INTC_PENDING_FIQ0 Section 6.6.1.19
A0h INTC_ITR1 Section 6.6.1.20
A4h INTC_MIR1 Section 6.6.1.21
A8h INTC_MIR_CLEAR1 Section 6.6.1.22
ACh INTC_MIR_SET1 Section 6.6.1.23
B0h INTC_ISR_SET1 Section 6.6.1.24
B4h INTC_ISR_CLEAR1 Section 6.6.1.25
B8h INTC_PENDING_IRQ1 Section 6.6.1.26
BCh INTC_PENDING_FIQ1 Section 6.6.1.27
C0h INTC_ITR2 Section 6.6.1.28
C4h INTC_MIR2 Section 6.6.1.29
C8h INTC_MIR_CLEAR2 Section 6.6.1.30
CCh INTC_MIR_SET2 Section 6.6.1.31
D0h INTC_ISR_SET2 Section 6.6.1.32
D4h INTC_ISR_CLEAR2 Section 6.6.1.33
D8h INTC_PENDING_IRQ2 Section 6.6.1.34
DCh INTC_PENDING_FIQ2 Section 6.6.1.35
E0h INTC_ITR3 Section 6.6.1.36
E4h INTC_MIR3 Section 6.6.1.37
E8h INTC_MIR_CLEAR3 Section 6.6.1.38
ECh INTC_MIR_SET3 Section 6.6.1.39

www.ti.com Interrupt Controller Registers
Table 6-4. INTC Registers (continued)

F0h INTC_ISR_SET3 Section 6.6.1.40
F4h INTC_ISR_CLEAR3 Section 6.6.1.41
F8h INTC_PENDING_IRQ3 Section 6.6.1.42
FCh INTC_PENDING_FIQ3 Section 6.6.1.43
100h to INTC_ILR_0 to INTC_ILR_127 Section 6.6.1.44
2FCh

6.6.1.1 INTC_REVISION Register (offset = 0h) [reset = 50h]

Register mask: FFFFFFFFh
INTC_REVISION is shown in Figure 6-4 and described in Table 6-5.
This register contains the IP revision code
Figure 6-4. INTC_REVISION Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED Rev
R-0h R-50h
Table 6-5. INTC_REVISION Register Field Descriptions

31-8 RESERVED R 0h Reads returns 0
7-0 Rev R 50h IP revision
[7:4] Major revision
[3:0] Minor revision Examples: 0x10 for 1.0, 0x21 for 2.1

6.6.1.2 INTC_SYSCONFIG Register (offset = 10h) [reset = 0h]

INTC_SYSCONFIG is shown in Figure 6-5 and described in Table 6-6.
This register controls the various parameters of the OCP interface
Figure 6-5. INTC_SYSCONFIG Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED SoftReset Autoidle
Table 6-6. INTC_SYSCONFIG Register Field Descriptions

4-3 RESERVED R 0h Write 0's for future compatibility.
Reads returns 0
2 RESERVED R/W 0h
1 SoftReset R/W 0h Software reset.
Set this bit to trigger a module reset.
The bit is automatically reset by the hardware.
During reads, it always returns 0.
0h(Read) = always_Always returns 0
1h(Read) = never_never happens
0 Autoidle R/W 0h Internal OCP clock gating strategy
0h = clkfree : OCP clock is free running
1h = autoClkGate : Automatic OCP clock gating strategy is applied,
bnased on the OCP interface activity

6.6.1.3 INTC_SYSSTATUS Register (offset = 14h) [reset = 0h]

Register mask: FFFFFFFEh
INTC_SYSSTATUS is shown in Figure 6-6 and described in Table 6-7.
This register provides status information about the module
Figure 6-6. INTC_SYSSTATUS Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ResetDone
R-0h R-X
Table 6-7. INTC_SYSSTATUS Register Field Descriptions

31-8 RESERVED R 0h
7-1 RESERVED R 0h Reserved for OCP socket status information Read returns 0
0 ResetDone R X Internal reset monitoring
0h = rstOngoing : Internal module reset is on-going
1h = rstComp : Reset completed

6.6.1.4 INTC_SIR_IRQ Register (offset = 40h) [reset = FFFFFF80h]

INTC_SIR_IRQ is shown in Figure 6-7 and described in Table 6-8.
This register supplies the currently active IRQ interrupt number.
Figure 6-7. INTC_SIR_IRQ Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SpuriousIRQ
R/W-1FFFFFFh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SpuriousIRQ ActiveIRQ
R/W-1FFFFFFh R/W-0h
Table 6-8. INTC_SIR_IRQ Register Field Descriptions

31-7 SpuriousIRQ R/W 1FFFFFFh Spurious IRQ flag
6-0 ActiveIRQ R/W 0h Active IRQ number

6.6.1.5 INTC_SIR_FIQ Register (offset = 44h) [reset = FFFFFF80h]

INTC_SIR_FIQ is shown in Figure 6-8 and described in Table 6-9.
This register supplies the currently active FIQ interrupt number
Figure 6-8. INTC_SIR_FIQ Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SpuriousFIQ
R-1FFFFFFh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SpuriousFIQ ActiveFIQ
R-1FFFFFFh R-0h
Table 6-9. INTC_SIR_FIQ Register Field Descriptions

31-7 SpuriousFIQ R 1FFFFFFh Spurious FIQ flag
6-0 ActiveFIQ R 0h Active FIQ number

6.6.1.6 INTC_CONTROL Register (offset = 48h) [reset = 0h]

INTC_CONTROL is shown in Figure 6-9 and described in Table 6-10.
This register contains the new interrupt agreement bits
Figure 6-9. INTC_CONTROL Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED NewFIQAgr NewIRQAgr
R-0h W-0h W-0h
Table 6-10. INTC_CONTROL Register Field Descriptions

Reads returns 0
1 NewFIQAgr W 0h Reset FIQ output and enable new FIQ generation
0h(Write) = nofun_no function effect
1h(Write) = NewFiq_Reset FIQ output and enable new FIQ
generation
0 NewIRQAgr W 0h New IRQ generation
0h(Write) = nofun_no function effect
1h(Write) = NewIrq_Reset IRQ output and enable new IRQ
generation

6.6.1.7 INTC_PROTECTION Register (offset = 4Ch) [reset = 0h]

INTC_PROTECTION is shown in Figure 6-10 and described in Table 6-11.
This register controls protection of the other registers. This register can only be accessed in priviledged
mode, regardless of the curent value of the protection bit.
Figure 6-10. INTC_PROTECTION Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED Protection
R-0h R/W-0h
Table 6-11. INTC_PROTECTION Register Field Descriptions

Reads returns 0
0 Protection R/W 0h Protection mode
0h = ProtMDis : Protection mode disabled (default)
1h = ProtMEnb : Protection mode enabled. When enabled, only
priviledged mode can access registers.

6.6.1.8 INTC_IDLE Register (offset = 50h) [reset = 0h]

INTC_IDLE is shown in Figure 6-11 and described in Table 6-12.
This register controls the clock auto-idle for the functional clock and the input synchronisers
Figure 6-11. INTC_IDLE Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED Turbo FuncIdle
R-0h R/W-0h R/W-0h
Table 6-12. INTC_IDLE Register Field Descriptions

Reads returns 0
1 Turbo R/W 0h Input synchroniser clock auto-gating
0h = SyncFree : Input synchroniser clock is free running (default)
1h = SyncAuto : Input synchroniser clock is auto-gated based on
interrupt input activity
0 FuncIdle R/W 0h Functional clock auto-idle mode
0h = FuncAuto : Functional clock gating strategy is applied (default)
1h = FuncFree : Functional clock is free-running

6.6.1.9 INTC_IRQ_PRIORITY Register (offset = 60h) [reset = FFFFFFC0h]

INTC_IRQ_PRIORITY is shown in Figure 6-12 and described in Table 6-13.
This register supplies the currently active IRQ priority level
Figure 6-12. INTC_IRQ_PRIORITY Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SpuriousIRQflag
R-1FFFFFFh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SpuriousIRQflag IRQPriority
R-1FFFFFFh R-40h
Table 6-13. INTC_IRQ_PRIORITY Register Field Descriptions

31-7 SpuriousIRQflag R 1FFFFFFh Spurious IRQ flag
6-0 IRQPriority R 40h Current IRQ priority

6.6.1.10 INTC_FIQ_PRIORITY Register (offset = 64h) [reset = FFFFFFC0h]

INTC_FIQ_PRIORITY is shown in Figure 6-13 and described in Table 6-14.
This register supplies the currently active FIQ priority level
Figure 6-13. INTC_FIQ_PRIORITY Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SpuriousFIQflag
R-1FFFFFFh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SpuriousFIQflag FIQPriority
R-1FFFFFFh R-40h
Table 6-14. INTC_FIQ_PRIORITY Register Field Descriptions

31-7 SpuriousFIQflag R 1FFFFFFh Spurious FIQ flag
6-0 FIQPriority R 40h Current FIQ priority

6.6.1.11 INTC_THRESHOLD Register (offset = 68h) [reset = FFh]

INTC_THRESHOLD is shown in Figure 6-14 and described in Table 6-15.
This register sets the priority threshold
Figure 6-14. INTC_THRESHOLD Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PriorityThreshold
R-0h R/W-FFh
Table 6-15. INTC_THRESHOLD Register Field Descriptions

31-8 RESERVED R 0h Reads returns 0
7-0 PriorityThreshold R/W FFh Priority threshold.
Values used are 00h to 3Fh.
Value FFh disables the threshold.

6.6.1.12 INTC_ITR0 Register (offset = 80h) [reset = 0h]

Register mask: 0h
INTC_ITR0 is shown in Figure 6-15 and described in Table 6-16.
This register shows the raw interrupt input status before masking
Figure 6-15. INTC_ITR0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Itr
R-X
Table 6-16. INTC_ITR0 Register Field Descriptions

31-0 Itr R X Interrupt status before masking

6.6.1.13 INTC_MIR0 Register (offset = 84h) [reset = FFFFFFFFh]

INTC_MIR0 is shown in Figure 6-16 and described in Table 6-17.
This register contains the interrupt mask
Figure 6-16. INTC_MIR0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mir
R/W-FFFFFFFFh
Table 6-17. INTC_MIR0 Register Field Descriptions

31-0 Mir R/W FFFFFFFFh Interrupt mask

6.6.1.14 INTC_MIR_CLEAR0 Register (offset = 88h) [reset = 0h]

Register mask: 0h
INTC_MIR_CLEAR0 is shown in Figure 6-17 and described in Table 6-18.
This register is used to clear the interrupt mask bits.
Figure 6-17. INTC_MIR_CLEAR0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MirClear
W-X
Table 6-18. INTC_MIR_CLEAR0 Register Field Descriptions

31-0 MirClear W X Write 1 clears the mask bit to 0, reads return 0

6.6.1.15 INTC_MIR_SET0 Register (offset = 8Ch) [reset = 0h]

Register mask: 0h
INTC_MIR_SET0 is shown in Figure 6-18 and described in Table 6-19.
This register is used to set the interrupt mask bits.
Figure 6-18. INTC_MIR_SET0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MirSet
W-X
Table 6-19. INTC_MIR_SET0 Register Field Descriptions

31-0 MirSet W X Write 1 sets the mask bit to 1, reads return 0

6.6.1.16 INTC_ISR_SET0 Register (offset = 90h) [reset = 0h]

INTC_ISR_SET0 is shown in Figure 6-19 and described in Table 6-20.
This register is used to set the software interrupt bits. It is also used to read the currently active software
interrupts.
Figure 6-19. INTC_ISR_SET0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IsrSet
R/W-0h
Table 6-20. INTC_ISR_SET0 Register Field Descriptions

31-0 IsrSet R/W 0h Reads returns the currently active software interrupts, Write 1 sets
the software interrupt bits to 1

6.6.1.17 INTC_ISR_CLEAR0 Register (offset = 94h) [reset = 0h]

Register mask: 0h
INTC_ISR_CLEAR0 is shown in Figure 6-20 and described in Table 6-21.
This register is used to clear the software interrupt bits
Figure 6-20. INTC_ISR_CLEAR0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IsrClear
W-X
Table 6-21. INTC_ISR_CLEAR0 Register Field Descriptions

31-0 IsrClear W X Write 1 clears the software interrupt bits to 0, reads return 0

6.6.1.18 INTC_PENDING_IRQ0 Register (offset = 98h) [reset = 0h]

INTC_PENDING_IRQ0 is shown in Figure 6-21 and described in Table 6-22.
This register contains the IRQ status after masking
Figure 6-21. INTC_PENDING_IRQ0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PendingIRQ
R-0h
Table 6-22. INTC_PENDING_IRQ0 Register Field Descriptions

31-0 PendingIRQ R 0h IRQ status after masking

6.6.1.19 INTC_PENDING_FIQ0 Register (offset = 9Ch) [reset = 0h]

INTC_PENDING_FIQ0 is shown in Figure 6-22 and described in Table 6-23.
This register contains the FIQ status after masking
Figure 6-22. INTC_PENDING_FIQ0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PendingFIQ
R-0h
Table 6-23. INTC_PENDING_FIQ0 Register Field Descriptions

31-0 PendingFIQ R 0h FIQ status after masking

6.6.1.20 INTC_ITR1 Register (offset = A0h) [reset = 0h]

Register mask: 0h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Itr
R-X


6.6.1.21 INTC_MIR1 Register (offset = A4h) [reset = FFFFFFFFh]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mir
R/W-FFFFFFFFh


6.6.1.22 INTC_MIR_CLEAR1 Register (offset = A8h) [reset = 0h]

Register mask: 0h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MirClear
W-X


6.6.1.23 INTC_MIR_SET1 Register (offset = ACh) [reset = 0h]

Register mask: 0h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MirSet
W-X


6.6.1.24 INTC_ISR_SET1 Register (offset = B0h) [reset = 0h]

interrupts.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IsrSet
R/W-0h


6.6.1.25 INTC_ISR_CLEAR1 Register (offset = B4h) [reset = 0h]

Register mask: 0h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IsrClear
W-X


6.6.1.26 INTC_PENDING_IRQ1 Register (offset = B8h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PendingIRQ
R-0h


6.6.1.27 INTC_PENDING_FIQ1 Register (offset = BCh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PendingFIQ
R-0h


6.6.1.28 INTC_ITR2 Register (offset = C0h) [reset = 0h]

Register mask: 0h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Itr
R-X


6.6.1.29 INTC_MIR2 Register (offset = C4h) [reset = FFFFFFFFh]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mir
R/W-FFFFFFFFh


6.6.1.30 INTC_MIR_CLEAR2 Register (offset = C8h) [reset = 0h]

Register mask: 0h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MirClear
W-X


6.6.1.31 INTC_MIR_SET2 Register (offset = CCh) [reset = 0h]

Register mask: 0h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MirSet
W-X


6.6.1.32 INTC_ISR_SET2 Register (offset = D0h) [reset = 0h]

interrupts.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IsrSet
R/W-0h


6.6.1.33 INTC_ISR_CLEAR2 Register (offset = D4h) [reset = 0h]

Register mask: 0h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IsrClear
W-X


6.6.1.34 INTC_PENDING_IRQ2 Register (offset = D8h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PendingIRQ
R-0h


6.6.1.35 INTC_PENDING_FIQ2 Register (offset = DCh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PendingFIQ
R-0h


6.6.1.36 INTC_ITR3 Register (offset = E0h) [reset = 0h]

Register mask: 0h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Itr
R-X


6.6.1.37 INTC_MIR3 Register (offset = E4h) [reset = FFFFFFFFh]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mir
R/W-FFFFFFFFh


6.6.1.38 INTC_MIR_CLEAR3 Register (offset = E8h) [reset = 0h]

Register mask: 0h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MirClear
W-X


6.6.1.39 INTC_MIR_SET3 Register (offset = ECh) [reset = 0h]

Register mask: 0h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MirSet
W-X


6.6.1.40 INTC_ISR_SET3 Register (offset = F0h) [reset = 0h]

interrupts.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IsrSet
R/W-0h


6.6.1.41 INTC_ISR_CLEAR3 Register (offset = F4h) [reset = 0h]

Register mask: 0h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IsrClear
W-X


6.6.1.42 INTC_PENDING_IRQ3 Register (offset = F8h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PendingIRQ
R-0h


6.6.1.43 INTC_PENDING_FIQ3 Register (offset = FCh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PendingFIQ
R-0h


6.6.1.44 INTC_ILR_0 to INTC_ILR_127 Register (offset = 100h to 2FCh) [reset = 0h]

INTC_ILR_0 to INTC_ILR_127 is shown in Figure 6-47 and described in Table 6-48.
The INTC_ILRx registers contain the priority for the interrupts and the FIQ/IRQ steering.
Figure 6-47. INTC_ILR_0 to INTC_ILR_127 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
Priority RESERVED FIQnIRQ
Table 6-48. INTC_ILR_0 to INTC_ILR_127 Register Field Descriptions

Reads returns 0
7-2 Priority R/W 0h Interrupt priority
1 RESERVED R/W 0h
0 FIQnIRQ R/W 0h Interrupt IRQ FiQ mapping
0h = IntIRQ : Interrupt is routed to IRQ.
1h = IntFIQ : Interrupt is routed to FIQ (this selection is reserved on
GP devices).

Chapter 7
Memory Subsystem
This chapter describes the memory subsystem of the device.
Topic ........................................................................................................................... Page
7.1 GPMC.............................................................................................................. 597

7.2 OCMC-RAM...................................................................................................... 900
7.3 EMIF ............................................................................................................... 902
7.4 ELM ................................................................................................................ 982
596 Memory Subsystem SPRUH73Q – October 2011 – Revised December 2019

www.ti.com GPMC
7.1 GPMC
7.1.1 Introduction
The general-purpose memory controller (GPMC) is an unified memory controller dedicated to interfacing
external memory devices:
• Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
• Asynchronous, synchronous, and page mode (only available in non-multiplexed mode) burst NOR flash
devices
• NAND Flash
• Pseudo-SRAM devices
7.1.1.1 GPMC Features

The general features of the GPMC module include:
• Data path to external memory device can be 16- or 8-bit wide
• 32-bit OCPIP 2.0 compliant core, single slave interface. Support non-wrapping and wrapping burst up
to 16x32bits.
• Up to 100 MHz external memory clock performance (single device)
• Support for the following memory types:
– External asynchronous or synchronous 8-bit width memory or device (non burst device)
– External asynchronous or synchronous 16-bit width memory or device
– External 16-bit non-multiplexed NOR Flash device
– External 16-bit address and data multiplexed NOR Flash device
– External 8-bit and 16-bit NAND flash device
– External 16-bit pSRAM device
• Up to 16-bit ECC support for NAND flash using BCH code (t=4, 8 or 16) or Hamming code for 8-bit or
16-bit NAND-flash, organized with page size of 512 bytes, 1K bytes, or more.
• Support 512M Bytes maximum addressing capability which can be divided into seven independent
chip-select with programmable bank size and base address on 16M Bytes, 32M Bytes, 64M Bytes, or
128M Bytes boundary
• Fully pipelined operation for optimal memory bandwidth usage
• Support external device clock frequency of 1, 2, 3 and 4 divider from L3 clock.
• Support programmable auto-clock gating when there is no access.
• Support Midlereq/SidleAck protocol
• Support the following interface protocols when communicating with external memory or external
devices.
– Asynchronous read/write access
– Asynchronous read page access (4-8-16 Word16)
– Synchronous read/write access
– Synchronous read burst access without wrap capability (4-8-16 Word16)
– Synchronous read burst access with wrap capability (4-8-16 Word16)
• Address and Data multiplexed access
• Each chip-select as independent and programmable control signal timing parameters for Setup and
Hold time. Parameters are set according to the memory device timing parameters, with one L3 clock
cycle timing granularity.
• Flexible internal access time control (wait state) and flexible handshake mode using external WAIT
pins monitoring (up to two WAIT pins)
• Support bus keeping
• Support bus turn around
SPRUH73Q – October 2011 – Revised December 2019 Memory Subsystem 597

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• Pre-fetch and write posting engine associated with system DMA to get full performance from NAND
device with minimum impact on NOR/SRAM concurrent access.
• On the fly ECC Hamming Code calculation to improve NAND usage reliability with minimum impact on
SW
7.1.1.2 Block Diagram

The GPMC can access various external devices through the L3 Slow Interconnect. The flexible
programming model allows a wide range of attached device types and access schemes. Based on the
programmed configuration bit fields stored in the GPMC registers, the GPMC is able to generate all
control signals timing depending on the attached device and access type. Given the chip-select decoding
and its associated configuration registers, the GPMC selects the appropriate device type control signals
timing.
Figure 7-1 shows the GPMC functional block diagram. The GPMC consists of six blocks:
• Interconnect port interface
• Address decoder, GPMC configuration, and chip-select configuration register file
• Access engine
• Prefetch and write-posting engine
• Error correction code engine (ECC)
• External device/memory port interface

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Figure 7-1. GPMC Block Diagram
Interconnect port interface
Address
GPMC Address decoder

Data configuration
Chip-select
configuration Address
CS selection
Access engine
FIFO
Data Address
Prefetch and write-
posting engine
Control
ECC
NAND access only
External memory port interface
7.1.1.3 Unsupported GPMC Features

The following module features are not supported in this device.
Table 7-1. Unsupported GPMC Features

Feature Reason
Chip Select 7 Not pinned out
32-bit devices Only 16 data lines pinned out
WAIT[3:2] Not pinned out. All CS regions must use WAIT0 or WAIT1

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7.1.2 Integration
An instantiation of GPMC provides this device with access to NAND Flash, NOR Flash, and other
asynchronous and synchronous interface peripherals. Figure 7-2 shows the integration of the GPMC
module in this device.
Figure 7-2. GPMC Integration
Device GPMC CLKRET GPMC Pads

L3 Slow CLK GPMC_CLK
Interconnect ADD[27:11] GPMC_A[27:11]
ADD[10:0] GPMC_A[10:0]
DATA[15:0] GPMC_AD[15:0]
MPU Subsystem SINTERRUPT CSn[6:0] GPMC_CSn[6:0]
ADVn/ALE GPMC_ADVn_ALE
EDMA SDMAREQ_N OEn/REn GPMC_OEn_REn
WEn GPMC_WEn
Module
Control
BE0n/CLE GPMC_BEN0_CLE
BE1n GPMC_BEN1
WPn GPMC_WPn
CONTROL_STATUS
SYSBOOT[11]
LCD_DATA11 WAIT[1:0] GPMC_WAIT[1:0]
SYSBOOT[10] ADMUX
LCD_DATA10 CS0MuxDevice[1:0] DIR2 GPMC_DIR
SYSBOOT[8] BW BootDeviceSize0
LCD_DATA8 WAITEN
SYSBOOT[9] BootWaitEn DATA[31:16]
LCD_DATA9
WaitSelectPin[1:0] CS[7]
BootDeviceSize1 WAIT[3:2]
7.1.2.1 GPMC Connectivity Attributes

The general connectivity attributes for the GPMC module are shown in Table 7-2.
Table 7-2. GPMC Connectivity Attributes

Attributes Type
Clock Domain PD_PER_L3S_GCLK
Reset Signals PER_DOM_RST_N
Idle/Wakeup Signals Smart Idle
Interrupt Requests 1 interrupt to MPU Subsystem (GPMCINT)
DMA Requests 1 DMA request to EDMA (GPMCEVT)
Physical Address L3 Slow Slave Port
Memory and control register regions qualified with
MAddressSpace bit
7.1.2.2 GPMC Clock and Reset Management

The GPMC is a synchronous design and operates from the same clock as the Slow L3. All timings use
this clock as a reference.
Table 7-3. GPMC Clock Signals

prcm_gpmc_clk 100 MHz CORE_CLKOUTM4 / 2 pd_per_l3s_gclk
Interface / Functional clock From PRCM
7.1.2.3 GPMC Signal List

The GPMC external interface signals are shown in Table 7-4.
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Table 7-4. GPMC Signal List

Signal Type Description
GPMC_A[27:0] O Address outputs
GPMC_AD[15:0] I/O Data[15:0] in non-muxed mode.
A[16:1], D[15:0] in AD-muxed mode.
A[27:17], A[16:1], D[15:0] in AAD-muxed
mode.
GPMC_CSn[6:0] O Chip selects (active low)
(1)
GPMC_CLK O Synchronous mode clock
GPMC_ADVn_ALE O Address Valid or Address Latch Enable
depending if NOR or NAND protocol
memories are selected.
GPMC_OEn_REn O Output Enable (active low). Also used as
Read Enable (active low) for NAND
protocol memories
GPMC_WEn O Write Enable (active low)
GPMC_BE0n_CLE O Lower Byte Enable (active low). Also used
as Command Latch Enable for NAND
protocol memories
GPMC_BE1n O Upper Byte Enable (active low)
GPMC_WPn O Write Protect (active low)
GPMC_WAIT[1:0] I External wait signal for NOR and NAND
protocol memories.
GPMC_DIR O GPMC.D[15:0] signal direction control
Low during transmit (for write access: data
OUT from GPMC to memory)
High during receive (for read access: data
IN from memory to GPMC)
(1)
These signals are also used as inputs to re-time or sync data. The associated CONF_<module>_<pin>_RXACTIVE bit for these
signals must be set to 1 to enable the inputs back to the module. It is also recommended to place a 33-ohm resistor in series
(close to the processor) on each of these signals to avoid signal reflections.

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Functional Description
7.1.2.1 GPMC Signals
Table 7-5 shows the use of address and data GPMC controller pins based on the type of external device.
Table 7-5. GPMC Pin Multiplexing Options

Non Multiplexed Non Multiplexed Multiplexed
16-Bit NAND
GPMC Signal Address Data 16- Address Data 8-Bit Address Data 16- 8-Bit NAND Device
Device
Bit Device (1) Device Bit Device (1)
GPMC_A[27] A26 A27 A26 Not Used Not Used
GPMC_A[26] A25 A26 Not Used Not Used Not Used
GPMC_A[0] Not Used A0 Not Used Not Used Not Used
GPMC_AD[15] D15 Not Used A/D[15] D15 Not Used
GPMC_AD[7] D7 D7 A/D[7] D7 D7
(1)
The values in this column represent the signals on the memory. Be aware that some 16-bit memories may label the address
lines differently. Some label the LSB as A0, while others use A1 for the LSB. These columns assume the LSB is A0.

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Table 7-5. GPMC Pin Multiplexing Options (continued)

Non Multiplexed Non Multiplexed Multiplexed
16-Bit NAND
GPMC Signal Address Data 16- Address Data 8-Bit Address Data 16- 8-Bit NAND Device
Device
Bit Device (1) Device Bit Device (1)
GPMC_CS[0]n CS0n (Chip Select) CS0n (Chip Select) CS0n (Chip Select) CE0n (Chip Enable) CE0n (Chip Enable)
GPMC_CS[1]n CS1n CS1n CS1n CE1n CE1n
ADVn (Address ADVn (Address ADVn (Address ALE (address latch ALE (address latch
GPMC_ADVn_ALE
Value) Value) Value) enable) enable)
CLE (command CLE (command
GPMC_BE0n_CLE BE0n (Byte Enable) BE0n (Byte Enable) BE0n (Byte Enable)
latch enable) latch enable)
GPMC_BE1n BE1n BE1n BE1n
GPMC_CLK CLK CLK CLK
OEn (Output OEn (Output OEn (Output
GPMC_OE_REn REn (read enable) REn (read enable)
Enable) Enable) Enable)
GPMC_WAIT0 WAIT0 WAIT0 WAIT0 R/B0n (ready/busy) R/B0n (ready/busy)
GPMC_WAIT1 WAIT1 WAIT1 WAIT1 R/B1n (ready/busy) R/B1n (ready/busy)
GPMC_WEn WEn (Write Enable) WEn (Write Enable) WEn (Write Enable) WEn (write enable) WEn (write enable)
GPMC_WPn WPn (Write Protect) WPn (Write Protect) WPn (Write Protect) WPn (write protect) WPn (write protect)
With all device types, the GPMC does not drive unnecessary address lines. They stay at their reset value
of 00.
Address mapping supports address/data-multiplexed 16-bit wide devices:
• The NOR flash memory controller still supports non-multiplexed address and data memory devices.
• Multiplexing mode can be selected through the GPMC_CONFIG1_i[9-8] MUXADDDATA bit field.
• Asynchronous page mode is not supported for multiplexed address and data devices.

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7.1.2.2 GPMC Modes

This section shows three GPMC external connections options:
• Figure 7-3 shows a connection between the GPMC and a 16-bit synchronous address/data-multiplexed
(or AAD-multiplexed, but this protocol use less address pins) external memory device.
• Figure 7-4 shows a connection between the GPMC and a 16-bit synchronous nonmultiplexed external
memory device .
• Figure 7-5 shows a connection between the GPMC and a 8-bit NAND device
Figure 7-3. GPMC to 16-Bit Address/Data-Multiplexed Memory
Device
GPMC External device/

memory
gpmc_a[11:1] 11
A[27:17] A[26:16]
gpmc_ad[15:0] 16
A[16:1]/D[15:0] A/D[15:0]
CSn[6:0] gpmc_csn[6:0] CEn
gpmc_advn_ale
ADVn_ALE ADVn
gpmc_oen
OEn_REn OEn
WEn gpmc_wen
WEn
gpmc_be0n_cle
BE0n_CLE BE0n/CLE
BE1n gpmc_be1n
BE1n
WPn gpmc_wpn
WPn
gpmc_wait[1:0]
WAIT[1:0] WAIT
gpmc_clk
CLK CLK

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Figure 7-4. GPMC to 16-Bit Non-multiplexed Memory
Device

memory
gpmc_a[27:1] 27
A[27:1] A[26:0]
gpmc_ad[15:0] 16
D[15:0] D[15:0]
CSn[6:0] gpmc_csn[6:0] CEn
gpmc_advn_ale
ADVn_ALE ADVn
OEn_REn gpmc_oen
OEn
WEn gpmc_wen
WEn
gpmc_be0n_cle
BE0n_CLE BE0n/CLE
BE1n gpmc_be1n
BE1n
WPn gpmc_wpn
WPn
gpmc_wait[1:0]
WAIT[1:0] WAIT
gpmc_clk
CLK CLK
Figure 7-5. GPMC to 8-Bit NAND Device
Device

memory
gpmc_ad[7:0] 8
D[7:0] D[7:0]
CSn[6:0] gpmc_csn[6:0] CSn
ADVn_ALE gpmc_advn_ale
ADVn/ALE
OEn_REn gpmc_oen
OEn/REn
WEn gpmc_wen
WEn
BE0n_CLE gpmc_be0n_cle
CLE
BE1n gpmc_be1n
WPn gpmc_wpn
WPn
gpmc_wait[1:0]
WAIT[1:0] WAIT
gpmc_clk
CLK

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7.1.2.3 GPMC Functional Description

The GPMC basic programming model offers maximum flexibility to support various access protocols for
each of the eight configurable chip-selects. Use optimal chip-select settings, based on the characteristics
of the external device:
• Different protocols can be selected to support generic asynchronous or synchronous random-access
devices (NOR flash, SRAM) or to support specific NAND devices.
• The address and the data bus can be multiplexed on the same external bus.
• Read and write access can be independently defined as asynchronous or synchronous.
• System requests (byte, 16-bit word, burst) are performed through single or multiple accesses. External
access profiles (single, multiple with optimized burst length, native- or emulated-wrap) are based on
external device characteristics (supported protocol, bus width, data buffer size, native-wrap support).
• System burst read or write requests are synchronous-burst (multiple-read or multiple-write). When
neither burst nor page mode is supported by external memory or ASIC devices, system burst read or
write requests are translated to successive single synchronous or asynchronous accesses (single
reads or single writes). 8-bit wide devices are supported only in single synchronous or single
asynchronous read or write mode.
• To simulate a programmable internal-wait state, an external wait pin can be monitored to dynamically
control external access at the beginning (initial access time) of and during a burst access.
Each control signal is controlled independently for each chip-select. The internal functional clock of the
GPMC (GPMC_FCLK) is used as a time reference to specify the following:
• Read- and write-access duration
• Most GPMC external interface control-signal assertion and deassertion times
• Data-capture time during read access
• External wait-pin monitoring time
• Duration of idle time between accesses, when required

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7.1.2.3.1 GPMC Clock Configuration

Table 7-6 describes the GPMC clocks.
Table 7-6. GPMC Clocks

Signal I/O Description
GPMC_FCLK I Functional and interface clock
GPMC_CLK O External clock provided to synchronous external memory devices.
The GPMC_CLK is generated by the GPMC from the internal GPMC_FCLK clock. The source of the
GPMC_FCLK is described in Table 7-3. The GPMC_CLK is configured via the GPMC_CONFIG1_i[1-0]
GPMCFCLKDIVIDER field (for i = 0 to 3) as shown in Table 7-7.
Table 7-7. GPMC_CONFIG1_i Configuration

GPMC_CONFIG1_i[1-0] GPMC_CLK Generated Clock
Source Clock
GPMCFCLKDIVIDER Provided to External Memory Device
00 GPMC_FCLK
01 GPMC_FCLK/2
GPMC_FCLK
10 GPMC_FCLK/3
11 GPMC_FCLK/4
7.1.2.3.2 GPMC Software Reset

The GPMC can be reset by software through the GPMC_SYSCONFIG[1] SOFTRESET bit. Setting the bit
to 1 enables an active software reset that is functionally equivalent to a hardware reset. Hardware and
software resets initialize all GPMC registers and the finite state-machine (FSM) immediately and
unconditionally. The GPMC_SYSSTATUS[0] RESETDONE bit indicates that the software reset is
complete when its value is 1. The software must ensure that the software reset completes before doing
GPMC operations.
7.1.2.3.3 GPMC Power Management

GPMC power is supplied by the CORE power domain, and GPMC power management complies with
system power-management guidelines. Table 7-8 describes power-management features available for the
GPMC module.
Table 7-8. GPMC Local Power Management Features

Feature Registers Description
GPMC_SYSCONFIG[0] This bit allows a local power optimization inside the module, by
Clock Auto Gating
AUTOIDLE] bit gating the GPMC_FCLK clock upon the internal activity.
GPMC_SYSCONFIG[4-3]
Slave Idle Modes Force-idle, No-idle and Smart-idle wakeup modes are available
SIDLEMODE bit field
Clock Activity N/A Feature not available
Master Standby Modes N/A Feature not available
Global Wake-up Enable N/A Feature not available
Wake-up Sources Enable N/A Feature not available

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7.1.2.3.4 GPMC Interrupt Requests

The GPMC generates one interrupt event as shown in Figure 7-2.
• The interrupt request goes from GPMC (GPMC_IRQ) to the MPU subsystem: A_IRQ_100
Table 7-9 lists the event flags, and their mask, that can cause module interrupts.
Table 7-9. GPMC Interrupt Events

Event Flag Event Mask Sensitivity Map to Description
Wait1 edge detection interrupt: Triggered if a rising or falling
GPMC_IRQSTATUS[9] GPMC_IRQENABLE[9]
edge is detected on the GPMC_WAIT1 signal. The rising or
WAIT1EDGEDETECTIO WAIT1EDGEDETECTIO Edge A_IRQ_100
falling edge detection of Wait1 is selected through
NSTATUS NENABLE
GPMC_CONFIG[9] WAIT1PINPOLARITY bit.
Wait0 edge detection interrupt: Triggered if a rising or falling
GPMC_IRQSTATUS[8] GPMC_IRQENABLE[8]
edge is detected on the GPMC_WAIT0 signal. The rising or
WAIT0EDGEDETECTIO WAIT0EDGEDETECTIO Edge A_IRQ_100
falling edge detection of Wait0 is selected through
NSTATUS NENABLE
GPMC_CONFIG[8] WAIT0PINPOLARITY bit.
GPMC_IRQSTATUS[1] GPMC_IRQENABLE[1] Terminal count event: Triggered on prefetch process
TERMINALCOUNTSTAT TERMINALCOUNTENA Level A_IRQ_100 completion, that is when the number of currently remaining
US BLE data to be requested reaches 0.
FIFO event interrupt: Indicates FIFO levels availability for in
GPMC_IRQSTATUS[0] GPMC_IRQENABLE[0] Write-Posting mode and prefetch mode.
Level A_IRQ_100
FIFOEVENTSTATUS FIFOEVENTENABLE GPMC_PREFETCH_CONFIG[2] DMAMODE bit shall be
cleared to 0.
7.1.2.3.5 GPMC DMA Requests

The GPMC generates one DMA event, from GPMC (GPMC_DMA_REQ) to the eDMA: e_DMA_53
7.1.2.3.6 L3 Slow Interconnect Interface

The GPMC L3 Slow interconnect interface is a pipelined interface including an 16 × 32-bit word write
buffer. Any system host can issue external access requests through the GPMC. The device system can
issue the following requests through this interface:
• One 8-bit / 16-bit / 32-bit interconnect access (read/write)
• Two incrementing 32-bit interconnect accesses (read/write)
• Two wrapped 32-bit interconnect accesses (read/write)
• Four incrementing 32-bit interconnect accesses (read/write)
• Four wrapped 32-bit interconnect accesses (read/write)
• Eight incrementing 32-bit interconnect accesses (read/write)
• Eight wrapped 32-bit interconnect accesses (read/write)
Only linear burst transactions are supported; interleaved burst transactions are not supported. Only power-
of-two-length precise bursts 2 × 32, 4 × 32, 8 × 32 or 16 × 32 with the burst base address aligned on the
total burst size are supported (this limitation applies to incrementing bursts only).
This interface also provides one interrupt and one DMA request line, for specific event control.
It is recommended to program the GPMC_CONFIG1_i ATTACHEDDEVICEPAGELENGTH field ([24-23])
according to the effective attached device page length and to enable the GPMC_CONFIG1_i
WRAPBURST bit ([31]) if the attached device supports wrapping burst. However, it is possible to emulate
wrapping burst on a non-wrapping memory by providing relevant addresses within the page or splitting
transactions. Bursts larger than the memory page length are chopped into multiple bursts transactions.
Due to the alignment requirements, a page boundary is never crossed.

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7.1.2.3.7 GPMC Address and Data Bus

The current application supports GPMC connection to NAND devices and to address/data-multiplexed
memories or devices. Connection to address/data-nonmultiplexed memories Depending on the GPMC
configuration of each chip-select, address and data bus lines that are not required for a particular access
protocol are not updated (changed from current value) and are not sampled when input (input data bus).
• For address/data-multiplexed and AAD-multiplexed NOR devices, the address is multiplexed on the
data bus.
• 8-bit wide NOR devices do not use GPMC I/O: GPMC_AD[15-8] for data (they are used for address if
needed).
• 16-bit wide NAND devices do not use GPMC I/O: GPMC_A[27-0].
• 8-bit wide NAND devices do not use GPMC I/O: GPMC_A[27-0] and GPMC I/O: GPMC_AD[15-8].
7.1.2.3.7.1 GPMC I/O Configuration Setting
NOTE: In this section and next sections, the i in GPMC_CONFIGx_i stands for the GPMC chip-
select i where i = 0 to 6.
To select a NAND device, program the following register fields:

• GPMC_CONFIG1_i[11-10] DEVICETYPE field = 10b
• GPMC_CONFIG1_i[9-8] MUXADDDATA bit = 00
To select an address/data-multiplexed device, program the following register fields:
• GPMC_CONFIG1_i[11-10] DEVICETYPE field = 00
• GPMC_CONFIG1_i[9-8] MUXADDDATA bit = 10b
To select an address/address/data-multiplexed device, program the following register fields:
• GPMC_CONFIG1_i[9-8] MUXADDDATA bit = 01b
To select an address/data-nonmultiplexed device , program the following register fields:
• GPMC_CONFIG1_i[9-8] MUXADDDATA bit = 00
7.1.2.3.8 Address Decoder and Chip-Select Configuration

Addresses are decoded accordingly with the address request of the chip-select and the content of the
chip-select base address register file, which includes a set of global GPMC configuration registers and
eight sets of chip-select configuration registers.
The GPMC configuration register file is memory-mapped and can be read or written with byte, 16-bit word,
or 32-bit word accesses. The register file should be configured as a noncacheable, nonbufferable region
to prevent any desynchronization between host execution (write request) and the completion of register
configuration (write completed with register updated). provides the GPMC register locations. For the map
of GPMC memory locations, see Table 7-48.
After the chip-select is configured, the access engine accesses the external device, drives the external
interface control signals, and applies the interface protocol based on user-defined timing parameters and
settings.

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7.1.2.3.8.1 Chip-Select Base Address and Region Size

Any external memory or ASIC device attached to the GPMC external interface can be accessed by any
device system host within the GPMC 512-Mbyte contiguous address space. For details, see Table 7-48.
The GPMC 512 Mbyte address space can be divided into a maximum of seven chip-select regions with
programmable base address and programmable CS size. The CS size is programmable from 16 Mbytes
to 256 Mbytes (must be a power-of-2) and is defined by the mask field. Attached memory smaller than the
programmed CS region size is accessed through the entire CS region (aliasing).
Each chip-select has a 6-bit base address encoding and a 4-bit decoding mask, which must be
programmed according to the following rules:
• The programmed chip-select region base address must be aligned on the chip-select region size
address boundary and is limited to a power-of-2 address value. During access decoding, the register
base address value is used for address comparison with the address-bit line mapping as described in
Figure 7-6 (with A0 as the device system byte-address line). Base address is programmed through the
GPMC_CONFIG7_i[5-0] BASEADDRESS bit field.
• The register mask is used to exclude some address lines from the decoding. A register mask bit field
cleared to 0 suppresses the associated address line from the address comparison (incoming address
bit line is don't care). The register mask value must be limited to the subsequent value, based on the
desired chip-select region size. Any other value has an undefined result. When multiple chip-select
regions with overlapping addresses are enabled concurrently, access to these chip-select regions is
cancelled and a GPMC access error is posted. The mask field is programmed through the
GPMC_CONFIG7_i[11-8] MASKADDRESS bit field.
Figure 7-6. Chip-Select Address Mapping and Decoding Mask

512 MBytes
256 MBytes
128 MBytes
64 MBytes
32 MBytes
16 MBytes
1 GBytes
A29 A28 A27 A26 A25 A24 A23 ... ... A0
Base address A29 A28 A27 A26 A25 A24 (16-MBytes minimum granularity)
Mask field (Chip-select decoding allowing

A27 A26 A25 A24 maximum CS size = 256 MBytes)
CS size Mask field
256 MBytes 0 0 0 0
128 MBytes 1 0 0 0
64 MBytes 1 1 0 0
32 MBytes 1 1 1 0
16 MBytes 1 1 1 1
A mask value of 0010 or 1001 must be avoided because it will create holes in the chip-select address space.
Chip-select configuration (base and mask address or any protocol and timing settings) must be performed
while the associated chip-select is disabled through the GPMC_CONFIG7_i[6] CSVALID bit. In addition, a
chip-select configuration can only be disabled if there is no ongoing access to that chip-select. This
requires activity monitoring of the prefetch or write-posting engine if the engine is active on the chip-select.
Also, the write buffer state must be monitored to wait for any posted write completion to the chip-select.

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Any access attempted to a nonvalid GPMC address region (CSVALID disabled or address decoding
outside a valid chip-select region) is not propagated to the external interface and a GPMC access error is
posted. In case of chip-selects overlapping, an error is generated and no access will occur on either chip-
select. Chip-select 0 is the only chip-select region enabled after either a power-up or a GPMC reset.
Although the GPMC interface can drive up to seven chip-selects, the frequency specified for this interface
is for a specific load. If this load is exceeded, the maximum frequency cannot be reached. One solution is
to implement a board with buffers, to allow the slowest device to maintain the total load on the lines.
7.1.2.3.8.2 Access Protocol
7.1.2.3.8.2.1 Supported Devices

The access protocol of each chip-select can be independently specified through the
GPMC_CONFIG1_i[11-10] DEVICETYPE parameter for:
• Random-access synchronous or asynchronous memory like NOR flash, SRAM
• NAND flash asynchronous devices
For more information about the NAND flash GPMC basic programming model and NAND support, see
Section 7.1.2.3.12 and Section 7.1.2.3.12.1.
7.1.2.3.8.2.2 Access Size Adaptation and Device Width

Each chip-select can be independently configured through the GPMC_CONFIG1_i[13-12] DEVICESIZE
field to interface with a 16-bit wide device or an 8-bit wide device. System requests with data width greater
than the external device data bus width are split into successive accesses according to both the external
device data-bus width and little-endian data organization.
An 8-bit wide device must be interfaced to the D0-D7 external interface bus lane. GPMC data accesses
only use this bus lane when the associated chip-select is attached to an 8-bit wide device.
The 8-bit wide device can be interfaced in asynchronous or synchronous mode in single data phase (no 8-
bit wide device burst mode). If the 8-bit wide device is set in the chip-select configuration register,
ReadMultiple and WriteMultiple bit fields are considered “don’t care” and only single accesses are
performed.
A 16-bit wide device can be interfaced in asynchronous or synchronous mode, with single or multiple data
phases for an access, and with native or emulated wrap mode support.
7.1.2.3.8.2.3 Address/Data-Multiplexing Interface

For random synchronous or asynchronous memory interfacing (DEVICETYPE = 0b00), an address- and
data-multiplexing protocol can be selected through the GPMC_CONFIG1_i[[9-8] MUXADDDATA bit field.
The ADVn signal must be used as the external device address latch control signal. For the associated
chip-select configuration, ADVn assertion and deassertion time and OEn assertion time must be set to the
appropriate value to meet the address latch setup/hold time requirements of the external device (see
Section 7.1.2).
This address/data-multiplexing interface is not applicable to NAND device interfacing. NAND devices
require a specific address, command, and data multiplexing protocol (see Section 7.1.2.3.12).
7.1.2.3.8.3 External Signals
7.1.2.3.8.3.1 WAIT Pin Monitoring Control

GPMC access time can be dynamically controlled using an external gpmc_wait pin when the external
device access time is not deterministic and cannot be defined and controlled only using the GPMC internal
RDACCESSTIME, WRACCESSTIME and PAGEBURSTACCESSTIME wait state generator.
The GPMC features two input wait pin:gpmc_wait1, and gpmc_wait0. This pin allow control of external
devices with different wait-pin polarity. They also allow the overlap of wait-pin assertion from different
devices without affecting access to devices for which the wait pin is not asserted.

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• The GPMC_CONFIG1_i[17-16] WAITPINSELECT bit field (where i = 0 to 6) selects which input

gpmc_wait pin is used for the device attached to the corresponding chip-select.
• The polarity of the wait pin is defined through the WAITxPINPOLARITY bit of the GPMC_CONFIG
register. A wait pin configured to be active low means that low level on the WAIT signal indicates that
the data is not ready and that the data bus is invalid. When WAIT is inactive, data is valid.
The GPMC access engine can be configured per CS to monitor the wait pin of the external memory
device or not, based on the access type: read or write.
• The GPMC_CONFIG1_i[22] WAITREADMONITORING bit defines whether the wait pin should be
monitored during read accesses or not.
• The GPMC_CONFIG1_i[21] WAITWRITEMONITORING bit defines whether the wait pin should be
monitored during write accesses or not.
The GPMC access engine can be configured to monitor the wait pin of the external memory device
asynchronously or synchronously with the GPMC_CLK clock, depending on the access type: synchronous
or asynchronous (the GPMC_CONFIG1_i[29] READTYPE and GPMC_CONFIG1_i[27] WRITETYPE bits).
7.1.2.3.8.3.2 Wait Monitoring During an Asynchronous Read Access

When wait-pin monitoring is enabled for read accesses (WAITREADMONITORING), the effective access
time is a logical AND combination of the RDACCESSTIME timing completion and the wait-deasserted
state.
During asynchronous read accesses with wait-pin monitoring enabled, the wait pin must be at a valid level
(asserted or deasserted) for at least two GPMC clock cycles before RDACCESSTIME completes, to
ensure correct dynamic access-time control through wait-pin monitoring. The advance pipelining of the two
GPMC clock cycles is the result of the internal synchronization requirements for the WAIT signal.
In this context, RDACCESSTIME is used as a WAIT invalid timing window and is set to such a value that
the wait pin is at a valid state two GPMC clock cycles before RDACCESSTIME completes.
Similarly, during a multiple-access cycle (for example, asynchronous read page mode), the effective
access time is a logical AND combination of PAGEBURSTACCESSTIME timing completion and the wait-
deasserted state. Wait-monitoring pipelining is also applicable to multiple accesses (access within a
page).
• WAIT monitored as active freezes the CYCLETIME counter. For an access within a page, when the
CYCLETIME counter is by definition in a lock state, WAIT monitored as asserted extends the current
access time in the page. Control signals are kept in their current state. The data bus is considered
invalid, and no data are captured during this clock cycle.
• WAIT monitored as inactive unfreezes the CYCLETIME counter. For an access within a page, when
the CYCLETIME counter is by definition in a lock state, WAIT monitored as inactive completes the
current access time and starts the next access phase in the page. The data bus is considered valid,
and data are captured during this clock cycle. In case of a single access or if this was the last access
in a multiple-access cycle, all signals are controlled according to their related control timing value and
according to the CYCLETIME counter status.
When a delay larger than two GPMC clocks must be observed between wait-pin deactivation time and
data valid time (including the required GPMC and the device data setup time), an extra delay can be
added between wait-pin deassertion time detection and effective data-capture time and the effective
unlock of the CYCLETIME counter. This extra delay can be programmed in the GPMC_CONFIG1_i[19-18]
WAITMONITORINGTIME field.
• The WAITMONITORINGTIME parameter does not delay the wait-pin active or inactive detection, nor
does it modify the two GPMC clocks pipelined detection delay.
• This extra delay is expressed as a number of GPMC_CLK clock cycles, even though the access is
defined as asynchronous, and no GPMC_CLK clock is provided to the external device. Still,
GPMCFCLKDIVIDER is used as a divider for the GPMC clock, so it must be programmed to define the
correct WAITMONITORINGTIME delay.
Figure 7-7 shows wait behavior during an asynchronous single read access.

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Figure 7-7. Wait Behavior During an Asynchronous Single Read Access (GPMCFCLKDivider = 1)
RDCYCLETIME
RDACCESSTIME
GPMC_FCLK
GPMC_CLK
A[27:17] Valid Address
A[16:1]/D[15:0] Valid Address Data 0 Data 0
nBE1/nBE0
CSRDOFFTIME
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
nADV
OEOFFTIME
OEONTIME
nOE
DIR OUT IN OUT
WAIT
WAITPINMONITORING = 0b00
WAITPINMONITORING = 0b01
The WAIT signal is active low. GPMC_CONFIG1_i[19-18] WAITMONITORINGTIME = 00b or 01b.
7.1.2.3.8.3.3 Wait Monitoring During an Asynchronous Write Access

When wait-pin monitoring is enabled for write accesses (GPMC_CONFIG1_i[21]
WAITWRITEMONITORING bit = 1), the WAIT-invalid timing window is defined by the WRACCESSTIME
field. WRACCESSTIME must be set so that the wait pin is at a valid state two GPMC clock cycles before
WRACCESSTIME completes. The advance pipelining of the two GPMC clock cycles is the result of the
internal synchronization requirements for the WAIT signal.
• WAIT monitored as active freezes the CYCLETIME counter. This informs the GPMC that the data bus
is not captured by the external device. The control signals are kept in their current state. The data bus
still drives the data.
• WAIT monitored as inactive unfreezes the CYCLETIME counter. This informs that the data bus is
correctly captured by the external device. All signals, including the data bus, are controlled according
to their related control timing value and to the CYCLETIME counter status.

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When a delay larger than two GPMC clock cycles must be observed between wait-pin deassertion time
and the effective data write into the external device (including the required GPMC data setup time and the
device data setup time), an extra delay can be added between wait-pin deassertion time detection and
effective data write time into the external device and the effective unfreezing of the CYCLETIME counter.
This extra delay can be programmed in the GPMC_CONFIG1_i[19-18] WAITMONITORINGTIME fields.
• The WAITMONITORINGTIME parameter does not delay the wait-pin assertion or deassertion
detection, nor does it modify the two GPMC clock cycles pipelined detection delay.
• This extra delay is expressed as a number of GPMC_CLK clock cycles, even though the access is
defined as asynchronous, and even though no clock is provided to the external device. Still,
GPMC_CONFIG1_i[1-0] GPMCFCLKDIVIDER is used as a divider for the GPMC clock and so it must
be programmed to define the correct WAITMONITORINGTIME delay.
7.1.2.3.8.3.4 Wait Monitoring During a Synchronous Read Access

During synchronous accesses with wait-pin monitoring enabled, the wait pin is captured synchronously
with GPMC_CLK, using the rising edge of this clock.
The WAIT signal can be programmed to apply to the same clock cycle it is captured in. Alternatively, it can
be sampled one or two GPMC_CLK cycles ahead of the clock cycle it applies to. This pipelining is
applicable to the entire burst access, and to all data phase in the burst access. This WAIT pipelining depth
is programmed in the GPMC_CONFIG1_i[19-18] WAITMONITORINGTIME field, and is expressed as a
number of GPMC_CLK clock cycles.
In synchronous mode, when wait-pin monitoring is enabled (GPMC_CONFIG1_i[22]
WAITREADMONITORING bit), the effective access time is a logical AND combination of the
RDACCESSTIME timing completion and the WAIT deasserted-state detection.
Depending on the programmed WAITMONITORINGTIME value, the wait pin should be at a valid level,
either asserted or deasserted:
• In the same clock cycle the data is valid if WAITMONITORINGTIME = 0 ( at RDACCESSTIME
completion)
• In the WAITMONITORINGTIME x (GPMCFCLKDIVIDER + 1) GPMC_FCLK clock cycles before
RDACCESSTIME completion if WAITMONITORINGTIME not equal to 0
Similarly, during a multiple-access cycle (burst mode), the effective access time is a logical AND
combination of PAGEBURSTACCESSTIME timing completion and the wait-inactive state. The Wait
pipelining depth programming applies to the whole burst access.
• WAIT monitored as active freezes the CYCLETIME counter. For an access within a burst (when the
CYCLETIME counter is by definition in a lock state), WAIT monitored as active extends the current
access time in the burst. Control signals are kept in their current state. The data bus is considered
invalid, and no data are captured during this clock cycle.
• WAIT monitored as inactive unfreezes the CYCLETIME counter. For an access within a burst (when
the CYCLETIME counter is by definition in lock state), WAIT monitored as inactive completes the
current access time and starts the next access phase in the burst. The data bus is considered valid,
and data are captured during this clock cycle. In a single access or if this was the last access in a
multiple-access cycle, all signals are controlled according to their relative control timing value and the
CYCLETIME counter status.
Figure 7-8 shows wait behavior during a synchronous read burst access.

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Figure 7-8. Wait Behavior During a Synchronous Read Burst Access

RDCYCLETIME0 RDCYCLETIME1
PAGEBURSTACCESSTIME
PAGEBURSTACCESSTIME
RDACCESSTIME PAGEBURSTACCESSTIME
WAITMONITORINGTIME = 0b01
WAITMONITORINGTIME = 0b00
CLKACTIVATIONTIME
GPMC_FCLK
GPMC_CLK
A[16:1]/D[15:0] D0 D1 D2 D3
nBE1/nBE0
CSRDOFFTIME0 CSRDOFFTIME1
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
nADV
OEOFFTIME0 OEOFFTIME1
OEONTIME
nOE
DIR OUT IN OUT
WAIT
Wait deasserted one Wait deasserted
GPMC.CLK cycle same cycle as
before valid data valid data
The WAIT signal is active low. WAITMONITORINGTIME = 00b or 01b.
7.1.2.3.8.3.5 Wait Monitoring During a Synchronous Write Access

During synchronous accesses with wait-pin monitoring enabled (the WAITWRITEMONITORING bit), the
wait pin is captured synchronously with GPMC_CLK, using the rising edge of this clock.
If enabled, external wait-pin monitoring can be used in combination with WRACCESSTIME to delay the
effective memory device GPMC_CLK capture edge.
Wait-monitoring pipelining depth is similar to synchronous read access:
• At WRACCESSTIME completion if WAITMONITORINGTIME = 0
• In the WAITMONITORINGTIME x (GPMCFCLKDIVIDER + 1) GPMC_FCLK cycles before
WRACCESSTIME completion if WAITMONITORINGTIME not equal to 0.

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Wait-monitoring pipelining definition applies to whole burst accesses:

• WAIT monitored as active freezes the CYCLETIME counter. For accesses within a burst, when the
CYCLETIME counter is by definition in a lock state, WAIT monitored as active indicates that the data
bus is not being captured by the external device. Control signals are kept in their current state. The
data bus is kept in its current state.
• WAIT monitored as inactive unfreezes the CYCLETIME counter. For accesses within a burst, when the
CYCLETIME counter is by definition in a lock state, WAIT monitored as inactive indicates the effective
data capture of the bus by the external device and starts the next access of the burst. In case of a
single access or if this was the last access in a multiple access cycle, all signals, including the data
bus, are controlled according to their related control timing value and the CYCLETIME counter status.
Wait monitoring is supported for all configurations except for GPMC_CONFIG1_i[19-18]
WAITMONITORINGTIME = 0 for write bursts with a clock divider of 1 or 2 (GPMC_CONFIG1_i[1-0]
GPMCFCLKDIVIDER field equal to 0 or 1, respectively).
7.1.2.3.8.3.6 WAIT With NAND Device

For details about the use of the wait pin for communication with a NAND flash external device, see
Section 7.1.2.3.12.2.
7.1.2.3.8.3.7 Idle Cycle Control Between Successive Accesses
7.1.2.3.8.3.7.1 Bus Turnaround (BUSTURNAROUND)

To prevent data-bus contention, an access that follows a read access to a slow memory/device must be
delayed (in other words, control the CSn/OEn de-assertion to data bus in high-impedance delay).
The bus turnaround is a time-out counter starting after CSn or OEn de-assertion time, whichever occurs
first, and delays the next access start-cycle time. The counter is programmed through the
GPMC_CONFIG6_i[3-0] BUSTURNAROUND bit field.
After a read access to a chip-select with a non zero BUSTURNAROUND, the next access is delayed until
the BUSTURNAROUND delay completes, if the next access is one of the following:
• A write access to any chip-select (same or different from the chip-select data was read from)
• A read access to a different chip-select from the chip-select data was read access from
• A read or write access to a chip-select associated with an address/data-multiplexed device
Bus keeping starts after bus turnaround completion so that DIR changes from IN to OUT after bus
turnaround. The bus will not have enough time to go into high-impedance even though it could be driven
with the same value before bus turnaround timing.
BUSTURNAROUND delay runs in parallel with GPMC_CONFIG6_i[3-0] CYCLE2CYCLEDELAY delays. It
should be noted that BUSTURNAROUND is a timing parameter for the ending chip-select access while
CYCLE2CYCLEDELAY is a timing parameter for the following chip-select access. The effective minimum
delay between successive accesses is driven by these delay timing parameters and by the access type of
the following access. See Figure 7-9 to Figure 7-11.
Another way to prevent bus contention is to define an earlier CSn or OEn deassertion time for slow
devices or to extend the value of RDCYCLETIME. Doing this prevents bus contention, but affects all
accesses of this specific chip-select.

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Figure 7-9. Read to Read for an Address-Data Multiplexed Device, On Different CS,
Without Bus Turnaround (CS0n Attached to Fast Device)
New read/write access
RD/WRCYCLETIME
RDCYCLETIME
D[15:0] DATA 0
OEOFFTIME
nOE
CSOFFTIME
nCS0
nCS1
DIR IN
Figure 7-10. Read to Read / Write for an Address-Data Multiplexed Device, On Different CS,
With Bus Turnaround
New read/write
access
A[16:1]/D[15:0] DATA 0 ADD 1
OEOFFTIME
nOE
RDCYCLETIME RD/WRCYCLETIME
CSOFFTIME
nCS0
BUSTURNAROUND
nCS1
DIR IN OUT

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Figure 7-11. Read to Read / Write for a Address-Data or AAD-Multiplexed Device, On Same CS,
With Bus Turnaround
New read/write
access
A[16:1]/D[15:0] DATA 0 ADD 1
OEOFFTIME
nOE
BUSTURNAROUND
RDCYCLETIME RD/WRCYCLETIME
CSOFFTIME
nCS0
DIR IN OUT
7.1.2.3.8.3.7.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN,

CYCLE2CYCLEDELAY)
Some devices require a minimum chip-select signal inactive time between accesses. The
GPMC_CONFIG6_i[7] CYCLE2CYCLESAMECSEN bit enables insertion of a minimum number of
GPMC_FCLK cycles, defined by the GPMC_CONFIG6_i[11-8] CYCLE2CYCLEDELAY field, between
successive accesses of any type (read or write) to the same chip-select.
If CYCLE2CYCLESAMECSEN is enabled, any subsequent access to the same chip-select is delayed until
its CYCLE2CYCLEDELAY completes. The CYCLE2CYCLEDELAY counter starts when
CSRDOFFTIME/CSWROFFTIME completes.
The same applies to successive accesses occurring during 32-bit word or burst accesses split into
successive single accesses when the single-access mode is used (GPMC_CONFIG1_i[30]
READMULTIPLE = 0 or GPMC_CONFIG1_i[28] WRITEMULTIPLE = 0).
All control signals are kept in their default states during these idle GPMC_FCLK cycles. This prevents
back-to-back accesses to the same chip-select without idle cycles between accesses.
7.1.2.3.8.3.7.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN,

CYCLE2CYCLEDELAY)
Because of the pipelined behavior of the system, successive accesses to different chip-selects can occur
back-to-back with no idle cycles between accesses. Depending on the control signals (CSn, ADV_ALEn,
BE0_CLEn, OE_REn, WEn) assertion and de-assertion timing parameters and on the IC timing
parameters, some control signals assertion times may overlap between the successive accesses to
different CS. Similarly, some control signals (WEn, OE_REn) may not respect required transition times.
To work around the overlapping and to observe the required control-signal transitions, a minimum of
CYCLE2CYCLEDELAY inactive cycles is inserted between the access being initiated to this chip-select
and the previous access ending for a different chip-select. This applies to any type of access (read or
write).

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If GPMC_CONFIG6_i[6] CYCLE2CYCLEDIFFCSEN is enabled, the chip-select access is delayed until

CYCLE2CYCLEDELAY cycles have expired since the end of a previous access to a different chip-select.
CYCLE2CYCLEDELAY count starts at CSRDOFFTIME/CSWROFFTIME completion. All control signals
are kept inactive during the idle GPMC_FCLK cycles.
CYCLE2CYCLESAMECSEN and CYCLE2CYCLEDIFFCSEN should be set in registers to respectively get
idle cycles inserted between accesses on this chip-select and after accesses to a different chip-select.
The CYCLE2CYCLEDELAY delay runs in parallel with the BUSTURNAROUND delay. It should be noted
that BUSTURNAROUND is a timing parameter defined for the ending chip-select access, whereas
CYCLE2CYCLEDELAY is a timing parameter defined for the starting chip-select access. The effective
minimum delay between successive accesses is based on the larger delay timing parameter and on
access type combination, since bus turnaround does not apply to all access types. See
Section 7.1.2.3.8.3.7.1 for more details on bus turnaround.
Table 7-10 describes the configuration required for idle cycle insertion.
Table 7-10. Idle Cycle Insertion Configuration

BUSTURN CYCLE2 CYCLE2
First Second Idle Cycle Insertion
AROUND Addr/Data CYCLE CYCLE
Access Access Chip-Select Between the Two
Timing Multiplexed SAMECSEN DIFFCSEN
Type Type Accesses
Parameter Parameter Parameter
No idle cycles are inserted
R/W 0 R/W Any Any 0 x if the two accesses are well
pipelined.
R >0 R Same Nonmuxed x 0 if the two accesses are well
pipelined.
BUSTURNAROUND cycles
R >0 R Different Nonmuxed 0 0
are inserted.
R >0 R/W Any Muxed 0 0
are inserted.
R >0 W Any Any 0 0
are inserted.
W >0 R/W Any Any 0 0 if the two accesses are well
pipelined.
CYCLE2CYCLEDELAY
R/W 0 R/W Same Any 1 x
cycles are inserted.
CYCLE2CYCLEDELAY
R/W 0 R/W Different Any x 1
cycles are inserted.
CYCLE2CYCLEDELAY
cycles are inserted. If BTA
idle cycles already apply on
these two back-to-back
R/W >0 R/W Same Any 1 x
accesses, the effective
delay is max
(BUSTURNAROUND,
CYCLE2CYCLEDELAY).
CYCLE2CYCLEDELAY
cycles are inserted. If BTA
idle cycles already apply on
these two back-to-back
R/W >0 R/W Different Any x 1
accesses, the effective
delay is maximum
(BUSTURNAROUND,
CYCLE2CYCLEDELAY).

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7.1.2.3.8.3.8 Slow Device Support (TIMEPARAGRANULARITY Parameter)

All access-timing parameters can be multiplied by 2 by setting the GPMC_CONFIG1_i[4]
TIMEPARAGRANULARITY bit. Increasing all access timing parameters allows support of slow devices.
7.1.2.3.8.3.9 GPMC_DIR Pin

The GPMC_DIR pin is used to control I/O direction on the GPMC data bus GPMC_D[15-0]. Depending on
top-level pad multiplexing, this signal can be output and used externally to the device, if required. The
GPMC_DIR pin is low during transmit (OUT) and high during receive (IN).
For write accesses, the GPMC_DIR pin stays OUT from start-cycle time to end-cycle time.
For read accesses, the GPMC_DIR pin goes from OUT to IN at OEn assertion time and stays IN until:
• BUSTURNAROUND is enabled
– The GPMC_DIR pin goes from IN to OUT at end-cycle time plus programmable bus turnaround
time.
• BUSTURNAROUND is disabled
– After an asynchronous read access, the GPMC_DIR pin goes from IN to OUT at RDACCESSTIME
+ 1 GPMC_FCLK cycle or when RDCYCLETIME completes, whichever occurs last.
– After a synchronous read access, the GPMC_DIR pin goes from IN to OUT at RDACCESSTIME +
2 GPMC_FCLK cycles or when RDCYCLETIME completes, whichever occurs last.
Because of the bus-keeping feature of the GPMC, after a read or write access and with no other accesses
pending, the default value of the GPMC_DIR pin is OUT (see Section 7.1.2.3.9.10). In nonmultiplexed
devices, the GPMC_DIR pin stays IN between two successive read accesses to prevent unnecessary
toggling.
7.1.2.3.8.3.10 Reset
No reset signal is sent to the external memory device by the GPMC. For more information about external-
device reset, see Chapter 8, Power, Reset, and Clock Management (PRCM).
The PRCM module provides an input pin, global_rst_n, to the GPMC:
• The global_rst_n pin is activated during device warm reset and cold reset.
• The global_rst_n pin initializes the internal state-machine and the internal configuration registers.
7.1.2.3.8.3.11 Write Protect Signal (WPn)

When connected to the attached memory device, the write protect signal can enable or disable the
lockdown function of the attached memory. The GPMC_WPn output pin value is controlled through the
GPMC_CONFIG[4] WRITEPROTECT bit, which is common to all CS.
7.1.2.3.8.3.12 Byte Enable (BE1n/BE0n)

Byte enable signals (BE1n/BE0n) are:
• Valid (asserted or nonasserted according to the incoming system request) from access start to access
completion for asynchronous and synchronous single accesses
• Asserted low from access start to access completion for asynchronous and synchronous multiple read
accesses
• Valid (asserted or nonasserted, according to the incoming system request) synchronously to each
written data for synchronous multiple write accesses
7.1.2.3.8.4 Error Handling

When an error occurs in the GPMC, the error information is stored in the GPMC_ERR_TYPE register and
the address of the illegal access is stored in the GPMC_ERR_ADDRESS register. The GPMC keeps only
the first error abort information until the GPMC_ERR_TYPE register is reset. Subsequent accesses that
cause errors are not logged until the error is cleared by hardware with the
GPMC_ERR_TYPE[0]ERRORVALID bit.
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• ERRORNOTSUPPADD occurs when an incoming system request address decoding does not match
any valid chip-select region, or if two chip-select regions are defined as overlapped, or if a register file
access is tried outside the valid address range of 1KB.
• ERRORNOTSUPPMCMD occurs when an unsupported command request is decoded at the L3 Slow
interconnect interface
• ERRORTIMEOUT: A time-out mechanism prevents the system from hanging. The start value of the
9-bit time-out counter is defined in the GPMC_TIMEOUT_CONTROL register and enabled with the
GPMC_TIMEOUT_CONTROL[0] TIMEOUTENABLE bit. When enabled, the counter starts at start-cycle
time until it reaches 0 and data is not responded to from memory, and then a time-out error occurs. When
data are sent from memory, this counter is reset to its start value. With multiple accesses (asynchronous
page mode or synchronous burst mode), the counter is reset to its start value for each data access within
the burst.
The GPMC does not generate interrupts on these errors. True abort to the MPU or interrupt generation is
handled at the interconnect level.
7.1.2.3.9 Timing Setting

The GPMC offers the maximum flexibility to support various access protocols. Most of the timing
parameters of the protocol access used by the GPMC to communicate with attached memories or devices
are programmable on a chip-select basis. Assertion and deassertion times of control signals are defined to
match the attached memory or device timing specifications and to get maximum performance during
accesses. For more information on GPMC_CLK and GPMC_FCLK see Section 7.1.2.3.9.6.
In the following sections, the start access time refer to the time at which the access begins.
7.1.2.3.9.1 Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
The GPMC_CONFIG5_i[4-0] RDCYCLETIME and GPMC_CONFIG5_i[12-8] WRCYCLETIME fields define
the address bus and byte enables valid times for read and write accesses. To ensure a correct duty cycle
of GPMC_CLK between accesses, RDCYCLETIME and WRCYCLETIME are expressed in GPMC_FCLK
cycles and must be multiples of the GPMC_CLK cycle. RDCYCLETIME and WRCYCLETIME bit fields can
be set with a granularity of 1 or 2 throught GPMC_CONFIG1_i[4] TIMEPARAGRANULARITY.
When either RDCYCLETIME or WRCYCLETIME completes, if they are not already deasserted, all control
signals (CSn, ADV_ALEn, OE_REn, WEn, and BE0_CLEn) are deasserted to their reset values,
regardless of their deassertion time parameters.
An exception to this forced deassertion occurs when a pipelined request to the same chip-select or to a
different chip-select is pending. In such a case, it is not necessary to deassert a control signal with
deassertion time parameters equal to the cycle-time parameter. This exception to forced deassertion
prevents any unnecessary glitches. This requirement also applies to BE signals, thus avoiding an
unnecessary BE glitch transition when pipelining requests.
If no inactive cycles are required between successive accesses to the same or to a different chip-select
(GPMC_CONFIG6_i[7] CYCLE2CYCLESAMECSEN = 0 or GPMC_CONFIG6_i[6]
CYCLE2CYCLEDIFFCSEN = 0, where i = 0 to 3), and if assertion-time parameters associated with the
pipelined access are equal to 0, asserted control signals (CSn, ADV_ALEn, BE0_CLEn, WEn, and
OE_REn) are kept asserted. This applies to any read/write to read/write access combination.
If inactive cycles are inserted between successive accesses, that is, CYCLE2CYCLESAMECSEN = 1 or
CYCLE2CYCLEDIFFCSEN = 1, the control signals are forced to their respective default reset values for
the number of GPMC_FCLK cycles defined in CYCLE2CYCLEDELAY.
7.1.2.3.9.2 CSn: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME /

CSWROFFTIME / CSEXTRADELAY)
The GPMC_CONFIG2_i[3-0] CSONTIME field defines the CSn signal-assertion time relative to the start
access time. It is common for read and write accesses.

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The GPMC_CONFIG2_i[12-8] CSRDOFFTIME (read access) and GPMC_CONFIG2_i[20-16]

CSWROFFTIME (write access) bit fields define the CSn signal deassertion time relative to start access
time.
CSONTIME, CSRDOFFTIME and CSWROFFTIME parameters are applicable to synchronous and
asynchronous modes. CSONTIME can be used to control an address and byte enable setup time before
chip-select assertion. CSRDOFFTIME and CSWROFFTIME can be used to control an address and byte
enable hold time after chip-select deassertion.
CSn signal transitions as controlled through CSONTIME, CSRDOFFTIME, and CSWROFFTIME can be
delayed by half a GPMC_FCLK period by enabling the GPMC_CONFIG2_i[7] CSEXTRADELAY bit. This
half of a GPMC_FCLK period provides more granularity on the CSn assertion and deassertion time to
guarantee proper setup and hold time relative to GPMC_CLK. CSEXTRADELAY is especially useful in
configurations where GPMC_CLK and GPMC_FCLK have the same frequency, but can be used for all
GPMC configurations. If enabled, CSEXTRADELAY applies to all parameters controlling CSn transitions.
The CSEXTRADELAY bit must be used carefully to avoid control-signal overlap between successive
accesses to different chip-selects. This implies the need to program the RDCYCLETIME and
WRCYCLETIME bit fields to be greater than the CSn signal-deassertion time, including the extra half-
GPMC_FCLK-period delay.
7.1.2.3.9.3 ADVn/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time
(ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME /
ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME
)
The GPMC_CONFIG3_i[3-0] ADVONTIME field defines the ADVn_ALE signal-assertion time relative to
start access time. It is common to read and write accesses.
The GPMC_CONFIG3_i[12-8] ADVRDOFFTIME (read access) and GPMC_CONFIG3_i[20-16]
ADVWROFFTIME (write access) bit fields define the ADVn_ALE signal-deassertion time relative to start
access time.
ADVONTIME can be used to control an address and byte enable valid setup time control before
ADVn_ALE assertion. ADVRDOFFTIME and ADVWROFFTIME can be used to control an address and
byte enable valid hold time control after ADVn_ALE de-assertion. ADVRDOFFTIME and
ADVWROFFTIME are applicable to both synchronous and asynchronous modes.
ADVn_ALE signal transitions as controlled through ADVONTIME, ADVRDOFFTIME, and
ADVWROFFTIME can be delayed by half a GPMC_FCLK period by enabling the GPMC_CONFIG3_i[7]
ADVEXTRADELAY bit. This half of a GPMC_FCLK period provides more granularity on ADVn_ALE
assertion and deassertion time to assure proper setup and hold time relative to GPMC_CLK. The
ADVEXTRADELAY configuration parameter is especially useful in configurations where GPMC_CLK and
GPMC_FCLK have the same frequency, but can be used for all GPMC configurations. If enabled,
ADVEXTRADELAY applies to all parameters controlling ADVn_ALE transitions.
ADVEXTRADELAY must be used carefully to avoid control-signal overlap between successive accesses
to different chip-selects. This implies the need to program the RDCYCLETIME and WRCYCLETIME bit
fields to be greater than ADVn_ALE signal-deassertion time, including the extra half-GPMC_FCLK-period
delay.
The GPMC_CONFIG3_i[6-4] ADVAADMUXONTIME, GPMC_CONFIG3_i[26-24]
ADVAADMUXRDOFFTIME, and GPMC_CONFIG3_i[30-28] ADVAADMUXWROFFTIME parameters have
the same functions as ADVONTIME, ADVRDOFFTIME, and ADVWROFFTIME, but apply to the first
address phase in the AAD-multiplexed protocol. It is the user responsibility to make sure
ADVAADMUXxxOFFTIME is programmed to a value lower than or equal to ADVxxOFFTIME. Functionality
in AAD-mux mode is undefined if the settings do not comply with this requirement.
ADVAADMUXxxOFFTIME can be programmed to the same value as ADVONTIME if no high ADVn pulse
is needed between the two AAD-mux address phases, which is the typical case in synchronous mode. In
this configuration, ADVn is kept low until it reaches the correct ADVxxOFFTIME.
See Section 7.1.2.3.12 for more details on ADVONTIME, ADVRDOFFTIME, ADVWROFFTIME, and
ADVAADMUXRDOFFTIME, ADVAADMUXWROFFTIME usage for CLE and ALE (Command / Address
Latch Enable) usage for a NAND Flash interface.

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7.1.2.3.9.4 OEn/REn: Output Enable / Read Enable Signal Control Assertion / Deassertion Time
(OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
The GPMC_CONFIG4_i[3-0] OEONTIME field defines the OEn_REn signal assertion time relative to start
access time. It is applicable only to read accesses.
The GPMC_CONFIG4_i[12-8] OEOFFTIME field defines the OEn_REn signal deassertion time relative to
start access time. It is applicable only to read accesses. OEn_REn is not asserted during a write cycle.
OEONTIME, OEOFFTIME, OEAADMUXONTIME and OEAADMUXOFFTIME parameters are applicable to
synchronous and asynchronous modes. OEONTIME can be used to control an address and byte enable
valid setup time control before OEn_REn assertion. OEOFFTIME can be used to control an address and
byte enable valid hold time control after OEn_REn assertion.
OEAADMUXONTIME and OEAADMUXOFFTIME parameters have the same functions as OEONTIME
and OEOFFTIME, but apply to the first OE assertion in the AAD-multiplexed protocol for a read phase, or
to the only OE assertion for a write phase. It is the user responsibility to make sure OEAADMUXOFFTIME
is programmed to a value lower than OEONTIME. Functionality in AAD-mux mode is undefined if the
settings do not comply with this requirement. OEAADMUXOFFTIME shall never be equal to OEONTIME
because the AAD-mux protocol requires a second address phase with the OEn signal de-asserted before
OEn can be asserted again to define a read command.
The OEn_REn signal transitions as controlled through OEONTIME, OEOFFTIME, OEAADMUXONTIME
and OEAADMUXOFFTIME can be delayed by half a GPMC_FCLK period by enabling the
GPMC_CONFIG4_i[7] OEEXTRADELAY bit. This half of a GPMC_FCLK period provides more granularity
on OEn_REn assertion and deassertion time to assure proper setup and hold time relative to GPMC_CLK.
If enabled, OEEXTRADELAY applies to all parameters controlling OEn_REn transitions.
OEEXTRADELAY must be used carefully, to avoid control-signal overlap between successive accesses to
different chip-selects. This implies the need to program RDCYCLETIME and WRCYCLETIME to be
greater than OEn_REn signal-deassertion time, including the extra half-GPMC_FCLK-period delay.
When the GPMC generates a read access to an address-/data-multiplexed device, it drives the address
bus until OEn assertion time.
7.1.2.3.9.5 WEn: Write Enable Signal Control Assertion / Deassertion Time (WEONTIME / WEOFFTIME /
WEEXTRADELAY)
The GPMC_CONFIG4_i[19-16] WEONTIME field (where i = 0 to 3) defines the WEn signal-assertion time
relative to start access time. The GPMC_CONFIG4_i[28-24] WEOFFTIME field defines the WEn signal-
deassertion time relative to start access time. These bit fields only apply to write accesses. WEn is not
asserted during a read cycle.
WEONTIME can be used to control an address and byte enable valid setup time control before WEn
assertion. WEOFFTIME can be used to control an address and byte enable valid hold time control after
WEn assertion.
WEn signal transitions as controlled through WEONTIME, and WEOFFTIME can be delayed by half a
GPMC_FCLK period by enabling the GPMC_CONFIG4_i[23] WEEXTRADELAY bit. This half of a
GPMC_FCLK period provides more granularity on WEn assertion and deassertion time to guaranty proper
setup and hold time relative to GPMC_CLK. If enabled, WEEXTRADELAY applies to all parameters
controlling WEn transitions.
The WEEXTRADELAY bit must be used carefully to avoid control-signal overlap between successive
accesses to different chip-selects. This implies the need to program the WRCYCLETIME bit field to be
greater than the WEn signal-deassertion time, including the extra half-GPMC_FCLK-period delay.

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7.1.2.3.9.6 GPMC_CLK
GPMC_CLK is the external clock provided to the attached synchronous memory or device.
• The GPMC_CLK clock frequency is the GPMC_FCLK functional clock frequency divided by 1, 2, 3, or
4, depending on the GPMC_CONFIG1_i[1-0] GPMCFCLKDIVIDER bit field, with a guaranteed 50-
percent duty cycle.
• The GPMC_CLK clock is only activated when the access in progress is defined as synchronous (read
or write access).
• The GPMC_CONFIG1_i[26-25] CLKACTIVATIONTIME field defines the number of GPMC_FCLK
cycles from start access time to GPMC_CLK activation.
• The GPMC_CLK clock is stopped when cycle time completes and is asserted low between accesses.
• The GPMC_CLK clock is kept low when access is defined as asynchronous.
• When the GPMC is configured for synchronous mode, the GPMC_CLK signal (which is an output)
must also be set as an input in the Pin Mux configuration for the pin. GPMC_CLK is looped back
through the output and input buffers of the corresponding GPMC_CLK pad at the device boundary.
The looped-back clock is used to synchronize the sampling of the memory signals.
When cycle time completes, the GPMC_CLK may be high because of the GPMCFCLKDIVIDER bit field.
To ensure correct stoppage of the GPMC_CLK clock within the 50-percent required duty cycle, it is the
user's responsibility to extend the RDCYCLETIME or WRCYCLETIME value.
To ensure a correct external clock cycle, the following rules must be applied:
• (RDCYCLETIME - CLKACTIVATIONTIME) must be a multiple of (GPMCFCLKDIVIDER + 1).
• The PAGEBURSTACCESSTIME value must be a multiple of (GPMCFCLKDIVIDER + 1).
7.1.2.3.9.7 GPMC_CLK and Control Signals Setup and Hold

Control-signal transition (assertion and deassertion) setup and hold values with respect to the GPMC_CLK
edge can be controlled in the following ways:
• For the GPMC_CLK signal, the GPMC_CONFIG1_i[26-25] CLKACTIVATIONTIME field allows setup
and hold control of control-signal assertion time.
• The use of a divided GPMC_CLK allows setup and hold control of control-signal assertion and
deassertion times.
• When GPMC_CLK runs at the GPMC_FCLK frequency so that GPMC_CLK edge and control-signal
transitions refer to the same GPMC_FCLK edge, the control-signal transitions can be delayed by half
of a GPMC_FCLK period to provide minimum setup and hold times. This half-GPMC_FCLK delay is
enabled with the CSEXTRADELAY, ADVEXTRADELAY, OEEXTRADELAY, or WEEXTRADELAY
parameter. This delay must be used carefully to prevent control-signal overlap between successive
accesses to different chip-selects. This implies that the RDCYCLETIME and WRCYCLETIME are
greater than the last control-signal deassertion time, including the extra half-GPMC_FCLK cycle.
7.1.2.3.9.8 Access Time (RDACCESSTIME / WRACCESSTIME)

The read access time and write access time durations can be programmed independently through
GPMC_CONFIG5_i[20-16] RDACCESSTIME and GPMC_CONFIG6_i[28-24] WRACCESSTIME. This
allows OEn and GPMC data capture timing parameters to be independent of WEn and memory device
data capture timing parameters. RDACCESSTIME and WRACCESSTIME bit fields can be set with a
granularity of 1 or 2 throught GPMC_CONFIG1_i[4] TIMEPARAGRANULARITY.
7.1.2.3.9.8.1 Access Time on Read Access

In asynchronous read mode, for single and paged accesses, GPMC_CONFIG5_i[[20-16]
RDACCESSTIME field defines the number of GPMC_FCLK cycles from start access time to the
GPMC_FCLK rising edge used for the first data capture. RDACCESSTIME must be programmed to the
rounded greater value (in GPMC_FCLK cycles) of the read access time of the attached memory device.
In synchronous read mode, for single or burst accesses, RDACCESSTIME defines the number of
GPMC_FCLK cycles from start access time to the GPMC_FCLK rising edge corresponding to the
GPMC_CLK rising edge used for the first data capture.
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GPMC_CLK which is sent to the memory device for synchronization with the GPMC controller, is internally
retimed to correctly latch the returned data. GPMC_CONFIG5_i[4-0] RDCYCLETIME must be greater than
RDACCESSTIME in order to let the GPMC latch the last return data using the internally retimed
GPMC_CLK.
The external WAIT signal can be used in conjunction with RDACCESSTIME to control the effective GPMC
data-capture GPMC_FCLK edge on read access in both asynchronous mode and synchronous mode. For
details about wait monitoring, see Section 7.1.2.3.8.1.
7.1.2.3.9.8.2 Access Time on Write Access

In asynchronous write mode, the GPMC_CONFIG6_i[[28-24] WRACCESSTIME timing parameter is not
used to define the effective write access time. Instead, it is used as a WAIT invalid timing window, and
must be set to a correct value so that the gpmc_wait pin is at a valid state two GPMC_CLK cycles before
WRACCESSTIME completes. For details about wait monitoring, see Section 7.1.2.3.8.1.
In synchronous write mode , for single or burst accesses, WRACCESSTIME defines the number of
GPMC_FCLK cycles from start access time to the GPMC_CLK rising edge used by the memory device for
the first data capture.
The external WAIT signal can be used in conjunction with WRACCESSTIME to control the effective
memory device data capture GPMC_CLK edge for a synchronous write access. For details about wait
monitoring, see Section 7.1.2.3.8.1.
7.1.2.3.9.9 Page Burst Access Time (PAGEBURSTACCESSTIME)

GPMC_CONFIG5_i[27-24] PAGEBURSTACCESSTIME bit field can be set with a granularity of 1 or 2
throught the GPMC_CONFIG1_i[[4] TIMEPARAGRANULARITY.
7.1.2.3.9.9.1 Page Burst Access Time on Read Access

In asynchronous page read mode, the delay between successive word captures in a page is controlled
through the PAGEBURSTACCESSTIME bit field. The PAGEBURSTACCESSTIME parameter must be
programmed to the rounded greater value (in GPMC_FCLK cycles) of the read access time of the
attached device.
In synchronous burst read mode, the delay between successive word captures in a burst is controlled
through the PAGEBURSTACCESSTIME field.
The external WAIT signal can be used in conjunction with PAGEBURSTACCESSTIME to control the
effective GPMC data capture GPMC_FCLK edge on read access. For details about wait monitoring, see
Section 7.1.2.3.8.1.
7.1.2.3.9.9.2 Page Burst Access Time on Write Access

Asynchronous page write mode is not supported. PAGEBURSTACCESSTIME is irrelevant in this case.
In synchronous burst write mode, PAGEBURSTACCESSTIME controls the delay between successive
memory device word captures in a burst.
The external WAIT signal can be used in conjunction with PAGEBURSTACCESSTIME to control the
effective memory-device data capture GPMC_CLK edge in synchronous write mode. For details about
wait monitoring, see Section 7.1.2.3.8.1.
7.1.2.3.9.10 Bus Keeping Support

At the end-cycle time of a read access, if no other access is pending, the GPMC drives the bus with the
last data read after RDCYCLETIME completion time to prevent bus floating and reduce power
consumption.
After a write access, if no other access is pending, the GPMC keeps driving the data bus after
WRCYCLETIME completes with the same data to prevent bus floating and power consumption.

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7.1.2.3.10 NOR Access Description

For each chip-select configuration, the read access can be specified as either asynchronous or
synchronous access through the GPMC_CONFIG1_i[29] READTYPE bit. For each chip-select
configuration, the write access can be specified as either synchronous or asynchronous access through
the GPMC_CONFIG1_i[27] WRITETYPE bit.
Asynchronous and synchronous read and write access time and related control signals are controlled
through timing parameters that refer to GPMC_FCLK. The primary difference of synchronous mode is the
availability of a configurable clock interface (GPMC_CLK) to control the external device. Synchronous
mode also affects data-capture and wait-pin monitoring schemes in read access.
For details about asynchronous and synchronous access, see the descriptions of GPMC_CLK,
RdAccessTime, WrAccessTime, and wait-pin monitoring.
For more information about timing-parameter settings, see the sample timing diagrams in this chapter.
The address bus and BE[1:0]n are fixed for the duration of a synchronous burst read access, but they are
updated for each beat of an asynchronous page-read access.
7.1.2.3.10.1 Asynchronous Access Description

This section describes:
• Asynchronous single read operation on an address/data multiplexed device
• Asynchronous single write operation on an address/data-multiplexed device
• Asynchronous single read operation on an AAD-multiplexed device
• Asynchronous single write operation on an AAD-multiplexed device
• Asynchronous multiple (page) read operation on a non-multiplexed device
In asynchronous operations GPMC_CLK is not provided outside the GPMC and is kept low.

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7.1.2.3.10.1.1 Access on Address/Data Multiplexed Devices
7.1.2.3.10.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device

Figure 7-12 shows an asynchronous single read operation on an address/data-multiplexed device.
Figure 7-12. Asynchronous Single Read Operation on an Address/Data Multiplexed Device

RDCYCLETIME
RDACCESSTIME
GPMC_FCLK
GPMC_CLK
A[16:1]/D[15:0] Valid Address Data 0 Data 0
nBE1/nBE0
CSRDOFFTIME
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
nADV
OEOFFTIME
OEONTIME
nOE
DIR OUT IN OUT
WAIT
7.1.2.3.10.1.1.2 Asynchronous Single Read on an Address/Data-Multiplexed Device

See the device-specific datasheet for formulas to calculate timing parameters.
Table 7-38 lists the timing bit fields to set up in order to configure the GPMC in asynchronous single read
mode.
When the GPMC generates a read access to an address/data-multiplexed device, it drives the address
bus until OEn assertion time. For details, see Section 7.1.2.3.8.2.3.
Address bits (A[16:1] from a GPMC perspective, A[15:0] from an external device perspective) are placed
on the address/data bus, and the remaining address bits GPMC_A[25:16] are placed on the address bus.
The address phase ends at OEn assertion, when the DIR signal goes from OUT to IN.
• Chip-select signal CSn
– CSn assertion time is controlled by the GPMC_CONFIG2_i[3-0] CSONTIME field. It controls the
address setup time to CSn assertion.
– CSn deassertion time is controlled by the GPMC_CONFIG2_i[12-8] CSRDOFFTIME field. It
controls the address hold time from CSn deassertion
• Address valid signal ADVn
– ADVn assertion time is controlled by the GPMC_CONFIG3_i[3-0] ADVONTIME field.
– ADVn deassertion time is controlled by the GPMC_CONFIG3_i[[12-8] ADVRDOFFTIME field.

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• Output enable signal OEn

– OEn assertion indicates a read cycle.
– OEn assertion time is controlled by the GPMC_CONFIG4_i[[3-0] OEONTIME field.
– OEn deassertion time is controlled by the GPMC_CONFIG4_i[[12-8] OEOFFTIME field.
• Read data is latched when RDACCESSTIME completes. Access time is defined in the
GPMC_CONFIG5_i[20-16] RDACCESSTIME field.
• Direction signal DIR: DIR goes from OUT to IN at the same time that OEn is asserted.
• The end of the access is defined by the GPMC_CONFIG5_i[4-0] RDCYCLETIME parameter.
In the GPMC, when a 16-bit wide device is attached to the controller, a 32-bit word write access is split
into two 16-bit word write accesses. For more information about GPMC access size and type adaptation,
see Section 7.1.2.3.10.5. Between two successive accesses, if a OEn pulse is needed:
• The GPMC_CONFIG6_i[[11-8] CYCLE2CYCLEDELAY field can be programmed with
GPMC_CONFIG6_i[[7] CYCLE2CYCLESAMECSEN enabled.
• The CSWROFFTIME and CSONTIME parameters also allow a chip-select pulse, but this affects all
other types of access.
Figure 7-13 shows two asynchronous single-read accesses on an address/data-multiplexed devices.
Figure 7-13. Two Asynchronous Single Read Accesses on an Address/Data Multiplexed Device
(32-Bit Read Split Into 2 × 16-Bit Read)
CYCLE2CYCLEDELAY
RDCYCLETIME RDCYCLETIME
GPMC_FCLK
GPMC_CLK
A[27:17] Valid address 0 Valid address 1
A[16:1]/D[15:0] Valid address 0 Data 0 Valid address 1 Data 1 Data 1
nBE1/nBE0
CSRDOFFTIME CSRDOFFTIME
CSONTIME CSONTIME
nCS
ADVRDOFFTIME ADVRDOFFTIME
ADVONTIME ADVONTIME
nADV
OEOFFTIME OEOFFTIME
OEONTIME OEONTIME
nOE
DIR OUT IN OUT IN OUT
WAIT

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7.1.2.3.10.1.1.3 Asynchronous Single Write Operation on an Address/Data-Multiplexed Device

Figure 7-14 shows an asynchronous single write operation on an address/data-multiplexed device.
Figure 7-14. Asynchronous Single Write on an Address/Data-Multiplexed Device

WRCYCLETIME
GPMC_FCLK
GPMC_CLK
WRDATAONADMUXBUS
A[16:1]/D[15:0] Valid Address Data
nBE1/nBE0
CSWROFFTIME
CSONTIME
nCS
ADVWROFFTIME
ADVONTIME
nADV
WEOFFTIME
WEONTIME
nWE
DIR OUT
WAIT
7.1.2.3.10.1.1.4 Asynchronous Single Write on an Address/Data-Multiplexed Device

Table 7-38 lists the timing bit fields to set up in order to configure the GPMC in asynchronous single write
mode. When the GPMC generates a write access to an address/data-multiplexed device, it drives the
address bus until WEn assertion time. For more information, see Section 7.1.2.3.8.2.3.
The CSn and ADVn signals are controlled in the same way as for asynchronous single read operation on
an address/data-multiplexed device.
• Write enable signal WEn
– WEn assertion indicates a write cycle.
– WEn assertion time is controlled by the GPMC_CONFIG4_i[19-16] WEONTIME field.
– WEn deassertion time is controlled by the GPMC_CONFIG4_i[28-24] WEOFFTIME field.
• Direction signal DIR: DIR signal is OUT during the entire access.
• The end of the access is defined by the GPMC_CONFIG5_i[12-8] WRCYCLETIME parameter.
Address bits A[16:1] (GPMC point of view) are placed on the address/data bus at the start of cycle time,
and the remaining address bits A[26:17] are placed on the address bus.
Data is driven on the address/data bus at a GPMC_CONFIG6_i[19-16] WRDATAONADMUXBUS time.
Write multiple access in asynchronous mode is not supported. If WRITEMULTIPLE is enabled with
WRITETYPE as asynchronous, the GPMC processes single asynchronous accesses.

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After a write operation, if no other access (read or write) is pending, the data bus keeps its previous value.
See Section 7.1.2.3.9.10.
7.1.2.3.10.1.1.5 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device

Write multiple (page) access in asynchronous mode is not supported for address/data-multiplexed
devices. If GPMC_CONFIG1_i[28] WRITEMULTIPLE is enabled (1) with GPMC_CONFIG1_i[27]
WRITETYPE as asynchronous (0), the GPMC processes single asynchronous accesses.
For accesses on non-multiplexed devices, see Section 7.1.2.3.10.3.
7.1.2.3.10.1.2 Access on Address/Address/Data (AAD) Multiplexed Devices
7.1.2.3.10.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device

Figure 7-15 shows an asynchronous single read operation on an AAD-multiplexed device.
Figure 7-15. Asynchronous Single-Read on an AAD-Multiplexed Device
RDCYCLETIME
RDACCESSTIME
GPMC_FCLK
GPMC_CLK
A[16:1]/D[15:0] MSB Address LSB Add Data 0 Data 0
nBE1/nBE0
CSRDOFFTIME
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
ADVAADMUXRDOFFTIME
ADVAADMUXONTIME
nADV
OEOFFTIME
OEONTIME
OEAADMUXOFFTIME
OEAADMUXONTIME
nOE
DIR OUT IN OUT
WAIT

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7.1.2.3.10.1.2.2 Asynchronous Single Read on an AAD-Multiplexed Device

Table 7-38 lists the timing bit fields to set up in order to configure the GPMC in asynchronous single write
mode.
When the GPMC generates a read access to an AAD-multiplexed device, all address bits are driven onto
the address/data bus in two separate phases. The first phase is used for the MSB address and is qualified
with OEn driven low. The first address phase ends at the first OEn deassertion time. The second phase
for LSB address is qualified with OEn driven high. The second address phase ends at the second OEn
assertion time, when the DIR signal goes from OUT to IN.
The CSn and DIR signals are controlled in the same way as for asynchronous single read operation on an
address/data-multiplexed device.
• Address valid signal ADVn. ADVn is asserted and deasserted twice during a read transaction:
– ADVn first assertion time is controlled by the GPMC_CONFIG3_i[6-4] ADVAADMUXONTIME field.
– ADVn first deassertion time is controlled by the GPMC_CONFIG3_i[26-24]
ADVAADMUXRDOFFTIME field.
– ADVn second assertion time is controlled by the GPMC_CONFIG3_i[3-0] ADVONTIME field.
– ADVn second deassertion time is controlled by the GPMC_CONFIG3_i[12-8] ADVRDOFFTIME
field.
• Output Enable signal OEn. OEn is asserted and deasserted twice during a read transaction (OEn
second assertion indicates a read cycle):
– OEn first assertion time is controlled by the GPMC_CONFIG4_i[6-4] OEAADMUXONTIME field.
– OEn first deassertion time is controlled by the GPMC_CONFIG3_i[15-13] OEAADMUXOFFTIME
field.
– OEn second assertion time is controlled by the GPMC_CONFIG4_i[3-0] OEONTIME field.
– OEn second deassertion time is controlled by the GPMC_CONFIG4_i[12-8] OEOFFTIME field.

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7.1.2.3.10.1.2.3 Asynchronous Single Write Operation on an AAD-Multiplexed Device

Figure 7-16 shows an asynchronous single write operation on an AAD-multiplexed device.
Figure 7-16. Asynchronous Single Write on an AAD-Multiplexed Device
WRCYCLETIME
GPMC_FCLK
GPMC_CLK
WRDATAONADMUXBUS
A[16:1]/D[15:0] MSB Address LSB Address Data
nBE1/nBE0
CSWROFFTIME
CSONTIME
nCS
ADVWROFFTIME
ADVONTIME
ADVAADMUXWROFFTIME
ADVAADMUXONTIME
nADV
OEAADMUXOFFTIME
OEAADMUXONTIME
nOE
WEOFFTIME
WEONTIME
nWE
DIR OUT
WAIT

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Table 7-38 lists the timing bit fields to set up to configure the GPMC in asynchronous single write mode.
When the GPMC generates a write access to an AAD-multiplexed device, all address bits are driven onto
with OEn driven low. The second phase for LSB address is qualified with OEn driven high. The address
phase ends at WEn assertion time.
The CSn, WEn, and DIR signals are controlled in the same way as for asynchronous single write
operation on an address/data-multiplexed device.
• Address valid signal ADVn is asserted and deasserted twice during a write transaction
ADVAADMUXWROFFTIME field.
– ADVn second deassertion time is controlled by the GPMC_CONFIG3_i[20-16] ADVWROFFTIME
field.
• Output Enable signal OEn is asserted during the address phase of a write transaction
– OEn assertion time is controlled by the GPMC_CONFIG4_i[6-4] OEAADMUXONTIME field.
– OEn deassertion time is controlled by the GPMC_CONFIG3_i[15-13] OEAADMUXOFFTIME field.
The address bits for the first address phase are driven onto the data bus until OEn deassertion. Data is
driven onto the address/data bus at the clock edge defined by the GPMC_CONFIG6_i[19-16]
WRDATAONADMUXBUS parameter.
7.1.2.3.10.1.2.4 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device

Write multiple (page) access in asynchronous mode is not supported for AAD-multiplexed devices.
If GPMC_CONFIG1_i[28] WRITEMULTIPLE is enabled (1) with GPMC_CONFIG1_i[27] WRITETYPE as
asynchronous (0), the GPMC processes single asynchronous accesses.
For accesses on non-multiplexed devices, see Section 7.1.2.3.10.3.
7.1.2.3.10.2 Synchronous Access Description

This section details read and write synchronous accesses on address/data multiplexed. All information in
this section can be applied to any type of memory - non-multiplexed, address and data multiplexed or
AAD-multiplexed - with a difference limited to the address phase. For accesses on non-multiplexed
devices, see Section 7.1.2.3.10.3.
In synchronous operations:
• The GPMC_CLK clock is provided outside the GPMC when accessing the memory device.
• The GPMC_CLK clock is derived from the GPMC_FCLK clock using the GPMC_CONFIG1_i[1-0]
GPMCFCLKDIVIDER field. In the following section, i stands for the chip-select number, i = 0 to 3.
• The GPMC_CONFIG1_i[26-25] CLKACTIVATIONTIME field specifies that the GPMC_CLK is provided
outside the GPMC 0, 1, or 2 GPMC_FCLK cycles after start access time until RDCYCLETIME or
WRCYCLETIME completion.

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7.1.2.3.10.2.1 Synchronous Single Read

Figure 7-17 and Figure 7-18 show a synchronous single-read operation with GPMCFCLKDIVIDER equal
to 0 and 1, respectively.
Figure 7-17. Synchronous Single Read (GPMCFCLKDIVIDER = 0)

RDCYCLETIME
RDACCESSTIME
GPMC_FCLK
CLKACTIVATIONTIME
GPMC_CLK

WRDATAONADMUXBUS
A[16:1]/D[15:0] Valid Address D0
nBE1/nBE0
CSRDOFFTIME
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
nADV
OEOFFTIME
OEONTIME
nOE
DIR OUT IN OUT
WAIT

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Figure 7-18. Synchronous Single Read (GPMCFCLKDIVIDER = 1)

RDCYCLETIME
GPMC_FCLK
RDACCESSTIME
CLKACTIVATIONTIME
GPMC_CLK

WRDATAONADMUXBUS
A[16:1]/D[15:0] Valid Address D0
nBE1/nBE0
CSRDOFFTIME
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
nADV
OEOFFTIME
OEONTIME
nOE
DIR OUT IN OUT
WAIT

Table 7-38 lists the timing bit fields to set up in order to configure the GPMC in asynchronous single read
mode.
– CSn assertion time is controlled by the GPMC_CONFIG2_i[3-0] CSONTIME field and ensures
– CSn deassertion time is controlled by the GPMC_CONFIG2_i[12-8] CSRDOFFTIME field and
ensures address hold time to CSn deassertion.
– ADVn deassertion time is controlled by the GPMC_CONFIG3_i[12-8] ADVRDOFFTIME field.
• Output enable signal OEn
– OEn assertion indicates a read cycle.
– OEn assertion time is controlled by the GPMC_CONFIG4_i[3-0] OEONTIME field.
– OEn deassertion time is controlled by the GPMC_CONFIG4_i[12-8] OEOFFTIME field.
• Initial latency for the first read data is controlled by GPMC_CONFIG5_i[20-16] RDACCESSTIME or by
monitoring the WAIT signal.
• Total access time (GPMC_CONFIG5_i[4-0] RDCYCLETIME) corresponds to RDACCESSTIME plus
the address hold time from CSn deassertion, plus time from RDACCESSTIME to CSRDOFFTIME.
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• Direction signal DIR: DIR goes from OUT to IN at the same time as OEn assertion.
The CSn and DIR signals are controlled in the same way as for synchronous single read operation on an
address/data-multiplexed device.
• Address valid signal ADVn is asserted and deasserted twice during a read transaction
– ADVn second deassertion time is controlled by the GPMC_CONFIG3_i[12-8] ADVRDOFFTIME
field.
• Output Enable signal OEn is asserted and deasserted twice during a read transaction (OEn second
assertion indicates a read cycle)
– OEn first assertion time is controlled by the GPMC_CONFIG4_i[6-4] OEAADMUXONTIME field.
field.
After a read operation, if no other access (read or write) is pending, the data bus is driven with the
previous read value. See Section 7.1.2.3.9.10.

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7.1.2.3.10.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
Figure 7-19 and Figure 7-20 show a synchronous multiple read operation with GPMCFCLKDivider equal
to 0 and 1, respectively.
Figure 7-19. Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 0)

PAGEBURSTACCESSTIME
CLKACTIVATIONTIME PAGEBURSTACCESSTIME
GPMC_FCLK
GPMC_CLK
A[16:1]/D[15:0] Valid Address D0 D1 D2 D3
nBE1/nBE0
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
nADV
OEOFFTIME
OEONTIME
nOE
DIR OUT IN OUT
WAIT

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Figure 7-20. Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 1)

RDCYCLETIME1
RDCYCLETIME0
PAGEBURSTACCESSTIME
CLKACTIVATIONTIME PAGEBURSTACCESSTIME
GPMC_FCLK
GPMC_CLK
A[16:1]/D[15:0] Valid Address D0 D1 D2 D3
nBE1/nBE0
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
nADV
OEONTIME
nOE
DIR OUT IN OUT
WAIT
When GPMC_CONFIG5_i[20-16] RDACCESSTIME completes, control-signal timings are frozen during

the multiple data transactions, corresponding to GPMC_CONFIG5_i[27-24] PAGEBURSTACCESSTIME
multiplied by the number of remaining data transactions.
The CSn, ADVn, OEn and DIR signals are controlled in the same way as for synchronous single read
operation. See Section 7.1.2.3.10.2.1.
Initial latency for the first read data is controlled by RDACCESSTIME or by monitoring the WAIT signal.
Successive read data are provided by the memory device each one or two GPMC_CLK cycles. The
PAGEBURSTACCESSTIME parameter must be set accordingly with GPMC_CONFIG1_i[1-0]
GPMCFCLKDIVIDER and the memory-device internal configuration. Depending on the device page
length, the GPMC checks device page crossing during a new burst request and purposely insert initial
latency (of RDACCESSTIME) when required.
Total access time GPMC_CONFIG5_i[4-0] RDCYCLETIME corresponds to RDACCESSTIME plus the
address hold time from CSn deassertion. In Figure 7-19, RDCYCLETIME programmed value equals to
RDCYCLETIME0 + RDCYCLETIME1.
After a read operation, if no other access (read or write) is pending, the data bus is driven with the
previous read value. See Section 7.1.2.3.9.10.
Burst wraparound is enabled through the GPMC_CONFIG1_i[31] WRAPBURST bit and allows a 4-, 8-, or
16-Word16 linear burst access to wrap within its burst-length boundary through GPMC_CONFIG1_i[24-23]
ATTACHEDDEVICEPAGELENGTH.

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7.1.2.3.10.2.3 Synchronous Single Write

Burst write mode is used for synchronous single or burst accesses (see Figure 7-21).
Figure 7-21. Synchronous Single Write on an Address/Data-Multiplexed Device

WRCYCLETIME
GPMC_FCLK
GPMC_CLK
WRDATAONADMUXBUS
A[16:1]/D[15:0] Valid Address Data
nBE1/nBE0
CSWROFFTIME
CSONTIME
nCS
ADVWROFFTIME
ADVONTIME
nADV
WEOFFTIME
WEONTIME
nWE
DIR OUT
WAIT
When the GPMC generates a write access to an address/data-multiplexed device, it drives the data bus
(with address bits A[16:1]) until [19:16] WRDATAONADMUXBUS time. First data of the burst is driven on
the address/data bus at WRDATAONADMUXBUS time.

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7.1.2.3.10.2.4 Synchronous Multiple (Burst) Write

Synchronous burst write mode provides synchronous single or consecutive accesses. Figure 7-22 shows
a synchronous burst write access when the chip-select is configured in address/data-multiplexed mode.
Figure 7-22. Synchronous Multiple Write (Burst Write) in Address/Data-Multiplexed Mode

PAGEBURSTACCESSTIME
WRCYCLETIME0 PAGEBURSTACCESSTIME
WRACCESSTIME PAGEBURSTACCESSTIME WRCYCLETIME1
GPMC_FCLK
CLKACTIVATIONTIME
GPMC_CLK

WRDATAONADMUXBUS
A[16:1]/D[15:0] Valid Address D0 D1 D2 D3 D4 D5 D6 D7 D7
nBE1/nBE0
CSWROFFTIME
CSONTIME
nCS
ADVWROFFTIME
ADVONTIME
nADV
WEOFFTIME
WEONTIME
nWE
DIR OUT
WAIT
Figure 7-23 shows the same synchronous burst write access when the chip-select is configured in
address/address/data-multiplexed (AAD-multiplexed) mode.

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Figure 7-23. Synchronous Multiple Write (Burst Write) in Address/Address/Data-Multiplexed Mode

PAGEBURSTACCESSTIME
WRCYCLETIME0 PAGEBURSTACCESSTIME
WRACCESSTIME PAGEBURSTACCESSTIME WRCYCLETIME1
GPMC_FCLK
CLKACTIVATIONTIME
GPMC_CLK

WRDATAONADMUXBUS
A[16:1]/D[15:0] Valid Address D0 D1 D2 D3 D4 D5 D6 D7 D7
nBE1/nBE0
CSWROFFTIME
CSONTIME
nCS
ADVWROFFTIME
ADVONTIME
ADVAADMUXOFFTIME
ADVAADMUXONTIME
nADV
OEAADMUXOFFTIME
OEAADMUXONTIME
nOE
WEOFFTIME
WEONTIME
nWE
DIR OUT
WAIT
The first data of the burst is driven on the A/D bus at GPMC_CONFIG6_i[19:16]
WRDATAONADMUXBUS.
When WRACCESSTIME completes, control-signal timings are frozen during the multiple data
transactions, corresponding to the GPMC_CONFIG5_i[27-24] PAGEBURSTACCESSTIME multiplied by
the number of remaining data transactions.
– CSn assertion time is controlled by the GPMC_CONFIG2_i[3-0] CSONTIME field and ensures
– CSn deassertion time controlled by the GPMC_CONFIG2_i[20-16] CSWROFFTIME field and
ensures address hold time to CSn deassertion.
– ADVn deassertion time is controlled by the GPMC_CONFIG3_i[20-16] ADVWROFFTIME field.

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• Write enable signal WEn

– WEn assertion indicates a read cycle.
– WEn assertion time is controlled by the GPMC_CONFIG4_i[19-16] WEONTIME field.
– WEn deassertion time is controlled by the GPMC_CONFIG4_i[28-24] WEOFFTIME field.
The WEn falling edge must not be used to control the time when the burst first data is driven in the
address/data bus because some new devices require the WEn signal at low during the address phase.
• Direction signal DIR is OUT during the entire access.
The CSn and DIR signals are controlled as detailled above.
• Address valid signal ADVn is asserted and deasserted twice during a read transaction
– ADVn first assertion time is controlled by the GPMC_CONFIG3_i[[6-4] ADVAADMUXONTIME field.
– ADVn first deassertion time is controlled by the GPMC_CONFIG3_i[[26-24]
– ADVn second assertion time is controlled by the GPMC_CONFIG3_i[[3-0] ADVONTIME field.
– ADVn second deassertion time is controlled by the GPMC_CONFIG3_i[[12-8] ADVRDOFFTIME
field.
• Output Enable signal OEn is asserted and deasserted twice during a read transaction (OEn second
assertion indicates a read cycle)
– OEn first assertion time is controlled by the GPMC_CONFIG4_i[[6-4] OEAADMUXONTIME field.
field.
First write data is driven by the GPMC at GPMC_CONFIG6_i[19-16] WRDATAONADMUXBUS, when in
address/data mux configuration. The next write data of the burst is driven on the bus at WRACCESSTIME
+ 1 during GPMC_CONFIG5_i[27-24] PAGEBURSTACCESSTIME GPMC_FCLK cycles. The last data of
the synchronous burst write is driven until GPMC_CONFIG5_i[12-8] WRCYCLETIME completes.
• WRACCESSTIME is defined in the GPMC_CONFIG6_i[28-24] register.
• The PAGEBURSTACCESSTIME parameter must be set accordingly with GPMCFCLKDIVIDER and
the memory-device internal configuration.
Total access time GPMC_CONFIG5_i[12-8] WRCYCLETIME corresponds to WRACCESSTIME plus the
address hold time from CSn deassertion. In Figure 7-23 the WRCYCLETIME programmed value equals
WRCYCLETIME0 + WRCYCLETIME1. WRCYCLETIME0 and WRCYCLETIME1 delays are not actual
parameters and are only a graphical representation of the full WRCYCLETIME value.
After a write operation, if no other access (read or write) is pending, the data bus keeps the previous
value. See Section 7.1.2.3.9.10.
7.1.2.3.10.3 Asynchronous and Synchronous Accesses in Nonmultiplexed Mode

Page mode is only available in non-multiplexed mode.
• Asynchronous single read operation on a nonmultiplexed device
• Asynchronous single write operation on a nonmultiplexed device
• Asynchronous multiple (page mode) read operation on a nonmultiplexed device
• Synchronous operations on a nonmultiplexed device

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7.1.2.3.10.3.1 Asynchronous Single Read Operation on a Nonmultiplexed Device

Figure 7-24 shows an asynchronous single read operation on a nonmultiplexed device.
Figure 7-24. Asynchronous Single Read on an Address/Data-Nonmultiplexed Device

RDCYCLETIME
RDACCESSTIME
GPMC_FCLK
GPMC_CLK

D[15:0] Data 0 Data 0
nBE1/nBE0
CSRDOFFTIME
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
nADV
OEOFFTIME
OEONTIME
nOE
WAIT
The 27-bit address is driven onto the address bus A[27:1] and the 16-bit data is driven onto the data bus
D[15:0].
Read data is latched at GPMC_CONFIG1_5[20-16] RDACCESSTIME completion time. The end of the
access is defined by the GPMC_CONFIG1_5[4-0] RDCYCLETIME parameter.
CSn, ADVn, OEn and DIR signals are controlled in the same way as address/data multiplexed accesses,
see Section 7.1.2.3.10.1.1.2.

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7.1.2.3.10.3.2 Asynchronous Single Write Operation on a Nonmultiplexed Device

Figure 7-25 shows an asynchronous single write operation on a nonmultiplexed device.
Figure 7-25. Asynchronous Single Write on an Address/Data-Nonmultiplexed Device

WRCYCLETIME
GPMC_FCLK
GPMC_CLK
A[27:1] Valid address
D[15:0] Write data
nBE1/nBE0
CSWROFFTIME
CSONTIME
nCS
ADVWROFFTIME
ADVONTIME
nADV
WEOFFTIME
WEONTIME
nWE
WAIT
The 27-bit address is driven onto the address bus A[27:1] and the 16-bit data is driven onto the data bus
D[15:0].
CSn, ADVn, WEn and DIR signals are controlled in the same way as address/data multiplexed accesses,
see Section 7.1.2.3.10.1.1.3.

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7.1.2.3.10.3.3 Asynchronous Multiple (Page Mode) Read Operation on a Nonmultiplexed Device

Figure 7-26 shows an asynchronous multiple read operation on a Nonmultiplexed Device, in which two
word32 host read accesses to the GPMC are split into one multiple (page mode of 4 word16) read access
to the attached device.
Figure 7-26. Asynchronous Multiple (Page Mode) Read

GPMC_FCLK
GPMC_CLK
RDACCESSTIME
PAGEBURSTACCESSTIME
PAGEBURSTACCESSTIME
A[27:1] A0 A1 A2 A3 A4
D[15:0] D0 D1 D2 D3 D3
nBE1/nBE0
CSONTIME
nCS
ADVRDOFFTIME0
ADVONTIME
nADV
OEONTIME
nOE
DIR OUT IN OUT
WAIT
The WAIT signal is active low.

CSn, ADVn, OEn and DIR signals are controlled in the same way as address/data multiplexed accesses,
see Section 7.1.2.3.10.1.1.2.
When RDACCESSTIME completes, control-signal timings are frozen during the multiple data transactions,
corresponding to PAGEBURSTACCESSTIME multiplied by the number of remaining data transactions.
Read data is latched at GPMC_CONFIG5_i[20-16] RDACCESSTIME completion time. The end of the
access is defined by the GPMC_CONFIG5_i[4-0] RDCYCLETIME parameter.
During consecutive accesses, the GPMC increments the address after each data read completes.
Delay between successive read data in the page is controlled by the GPMC_CONFIG5_i[27-24]
PAGEBURSTACCESSTIME parameter. Depending on the device page length, the GPMC can control
device page crossing during a burst request and insert initial RDACCESSTIME latency. Note that page
crossing is only possible with a new burst access, meaning a new initial access phase is initiated.
Total access time RDCYCLETIME corresponds to RDACCESSTIME plus the address hold time starting
from the CSn deassertion.
• The read cycle time is defined in the GPMC_CONFIG5_i[4-0] RDCYCLETIME field.
• In Figure 7-26, the RDCYCLETIME programmed value equals RDCYCLETIME0 (before paged
accesses) + RDCYCLETIME1 (after paged accesses).

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7.1.2.3.10.3.4 Synchronous Operations on a Nonmultiplexed Device

All information for this section is equivalent to similar operations for address/data- or AAD-multiplexed
accesses. The only difference resides in the address phase. See Section 7.1.3.2.
7.1.2.3.10.4 Page and Burst Support

Each chip-select can be configured to process system single or burst requests into successive single
accesses or asynchronous page/synchronous burst accesses, with appropriate access size adaptation.
Depending on the external device page or burst capability, read and write accesses can be independently
configured through the GPMC. The GPMC_CONFIG1_i[30] READMULTIPLE and GPMC_CONFIG1_i[28]
WRITMULTIPLE bits are associated with the READTYPE and WRITETYPE parameters.
• Asynchronous write page mode is not supported.
• 8-bit wide device support is limited to nonburstable devices (READMULTIPLE and WRITEMULTIPLE
are ignored).
• Not applicable to NAND device interfacing.
7.1.2.3.10.5 System Burst Versus External Device Burst Support

The device system can issue the following requests to the GPMC:
• Byte, 16-bit word, 32-bit word requests (byte enable controlled). This is always a single request from
the interconnect point of view.
• Incrementing fixed-length bursts of two words, four words, and eight words
• Wrapped (critical word access first) fixed-length burst of two, four, or eight words
To process a system request with the optimal protocol, the READMULTIPLE (and READTYPE) and
WRITEMULTIPLE (and WRITETYPE) parameters must be set according to the burstable capability
(synchronous or asynchronous) of the attached device.
The GPMC access engine issues only fixed-length burst. The maximum length that can be issued is
defined per CS by the GPMC_CONFIG1_i[24-23] ATTACHEDDEVICEPAGELENGTH field. When the
ATTACHEDDEVICEPAGELENGTH value is less than the system burst request length (including the
appropriate access size adaptation according to the device width), the GPMC splits the system burst
request into multiple bursts. Within the specified 4-, 8-, or 16-word value, the
ATTACHEDDEVICEPAGELENGTH field value must correspond to the maximum-length burst supported
by the memory device configured in fixed-length burst mode (as opposed to continuous burst mode).
To get optimal performance from memory devices that natively support 16 Word16-length-wrapping burst
capability (critical word access first), the ATTACHEDDEVICEPAGELENGTH parameter must be set to 16
words and the GPMC_CONFIG1_i[31] WRAPBURST bit must be set to 1. Similarly
DEVICEPAGELENGTH is set to 4 and 8 for memories supporting respectively 4 and 8 Word16-length-
wrapping burst.
When the memory device does not offer (or is not configured to offer) native 16 Word16-length-wrapping
burst, the WRAPBURST parameter must be cleared, and the GPMC access engine emulates the
wrapping burst by issuing the appropriate burst sequences according to the
ATTACHEDDEVICEPAGELENGTH value.
When the memory device does not support native-wrapping burst, there is usually no difference in
behavior between a fixed burst length mode and a continuous burst mode configuration (except for a
potential power increase from a memory-speculative data prefetch in a continuous burst read). However,
even though continuous burst mode is compatible with GPMC behavior, because the GPMC access
engine issues only fixed-length burst and does not benefit from continuous burst mode, it is best to
configure the memory device in fixed-length burst mode.
The memory device maximum-length burst (configured in fixed-length burst wrap or nonwrap mode)
usually corresponds to the memory device data buffer size. Memory devices with a minimum of 16 half-
word buffers are the most appropriate (especially with wrap support), but memory devices with smaller
buffer size (4 or 8) are also supported, assuming that the GPMC_CONFIG1_i[24-23]
ATTACHEDDEVICEPAGELENGTH field is set accordingly to 4 or 8 words.

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The device system issues only requests with addresses or starting addresses for nonwrapping burst
requests; that is, the request size boundary is aligned. In case of an eight-word-wrapping burst, the
wrapping address always occurs on the eight-words boundary. As a consequence, all words requested
must be available from the memory data buffer when the buffer size is equal to or greater than the
ATTACHEDDEVICEPAGELENGTH value. This usually means that data can be read from or written to the
buffer at a constant rate (number of cycles between data) without wait states between data accesses. If
the memory does not behave this way (nonzero wait state burstable memory), wait-pin monitoring must be
enabled to dynamically control data-access completion within the burst.
When the system burst request length is less than the ATTACHEDDEVICEPAGELENGTH value, the
GPMC proceeds with the required accesses.
7.1.2.3.11 pSRAM Access Specificities

pSRAM devices are SRAM-pin-compatible low-power memories that contain a self-refreshed DRAM
memory array. The GPMC_CONFIG1_i[[11-10] DEVICETYPE field shall be cleared to 0b00.
The pSRAM devices uses the NOR protocol. It support the following operations:
• Asynchronous single read
• Asynchronous page read
• Asynchronous single write
• Synchronous single read and write
• Synchronous burst read
• Synchronous burst write (not supported by NOR Flash memory)
pSRAM devices must be powered up and initialized in a predefined manner according to the specifications
of the attached device.
pSRAM devices can be programmed to use either mode: fixed or variable latency. pSRAM devices can
either automatically schedule autorefresh operations, which force the GPMC to use its WAIT signal
capability when read or write operations occur during an internal self-refresh operation, or pSRAM devices
automatically include the autorefresh operation in the access time. These devices do not require additional
WAIT signal capability or a minimum CSn high pulse width between consecutive accesses to ensure that
the correct internal refresh operation is scheduled.
7.1.2.3.12 NAND Access Description

NAND (8-bit and 16-bit) memory devices using a standard NAND asynchronous address/data-multiplexing
scheme can be supported on any chip-select with the appropriate asynchronous configuration settings
As for any other type of memory compatible with the GPMC interface, accesses to a chip-select allocated
to a NAND device can be interleaved with accesses to chip-selects allocated to other external devices.
This interleaved capability limits the system to chip enable don't care NAND devices, because the chip-
select allocated to the NAND device must be de-asserted if accesses to other chip-selects are requested.
7.1.2.3.12.1 NAND Memory Device in Byte or 16-Bit Word Stream Mode

NAND devices require correct command and address programming before data array read or write
accesses. The GPMC does not include specific hardware to translate a random address system request
into a NAND-specific multiphase access. In that sense, GPMC NAND support, as opposed to random
memory-map device support, is data-stream-oriented (byte or 16-bit word).
The GPMC NAND programming model relies on a software driver for address and command formatting
with the correct data address pointer value according to the block and page structure. Because of NAND
structure and protocol interface diversity, the GPMC does not support automatic command and address
phase programming, and software drivers must access the NAND device ID to ensure that correct
command and address formatting are used for the identified device.
NAND device data read and write accesses are achieved through an asynchronous read or write access.
The associated chip-select signal timing control must be programmed according to the NAND device
timing specification.

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Any chip-select region can be qualified as a NAND region to constrain the ADVn_ALE signal as Address
Latch Enable (ALE active high, default state value at low) during address program access, and the
BE0n_CLE signal as Command Latch Enable (CLE active high, default state value at low) during
command program access. GPMC address lines are not used (the previous value is not changed) during
NAND access.
7.1.2.3.12.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
The GPMC_CONFIG7_i register associated with a NAND device region interfaced in byte or word stream
mode can be initialized with a minimum size of 16 Mbytes, because any address location in the chip-select
memory region can be used to access a NAND data array. The NAND Flash protocol specifies an address
sequence where address bits are passed through the data bus in a series of write accesses with the ALE
pin asserted. After this address phase, all operations are streamed and the system requests address is
irrelevant.
To allow correct command, address, and data-access controls, the GPMC_CONFIG1_i register
associated with a NAND device region must be initialized in asynchronous read and write modes with the
parameters shown in Chip-Select Configuration for NAND Interfacing. Failure to comply with these
settings corrupts the NAND interface protocol.
The GPMC_CONFIG1_i to GPMC_CONFIG4_i register associated with a NAND device region must be
initialized with the correct control-signal timing value according to the NAND device timing parameters.
Chip-Select Configuration for NAND Interfacing

Bit Field Register Value Comments
WRAPBURST GPMC_CONFIG1_i 0 No wrap
READMULTIPLE GPMC_CONFIG1_i 0 Single access
READTYPE GPMC_CONFIG1_i 0 Asynchronous mode
WRITEMULTIPLE GPMC_CONFIG1_i 0 Single access
WRITETYPE GPMC_CONFIG1_i 0 Asynchronous mode
CLKACTIVATIONTIME GPMC_CONFIG1_i 0b00
ATTACHEDDEVICEPAGELENGTH GPMC_CONFIG1_i Don't care Single-access mode
WAITREADMONITORING GPMC_CONFIG1_i 0 Wait not monitored by GPMC access engine
WAITWRITEMONITORING GPMC_CONFIG1_i 0 Wait not monitored by GPMC access engine
WAITMONITORINGTIME GPMC_CONFIG1_i Don't care Wait not monitored by GPMC access engine
WAITPINSELECT GPMC_CONFIG1_i Select which wait is monitored by edge detectors
DEVICESIZE GPMC_CONFIG1_i 0b00 or
8- or 16-bit interface
0b01
DEVICETYPE GPMC_CONFIG1_i 0b10 NAND device in stream mode
MUXADDDATA GPMC_CONFIG1_i 0b00 Nonmultiplexed mode
TIMEPARAGRANULARITY GPMC_CONFIG1_i 0 Timing achieved with best GPMC clock
granularity
GPMCFCLKDIVIDER GPMC_CONFIG1_i Don't care Asynchronous mode
7.1.2.3.12.1.2 NAND Device Command and Address Phase Control

NAND devices require multiple address programming phases. The MPU software driver is responsible for
issuing the correct number of command and address program accesses, according to the device
command set and the device address-mapping scheme.
NAND device-command and address-phase programming is achieved through write requests to the
GPMC_NAND_COMMAND_i and GPMC_NAND_ADDRESS_i register locations with the correct
command and address values. These locations are mapped in the associated chip-select register region.
The associated chip-select signal timing control must be programmed according to the NAND device
timing specification.

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Command and address values are not latched during the access and cannot be read back at the register
location.
• Only write accesses must be issued to these locations, but the GPMC does not discard any read
access. Accessing a NAND device with OEn and CLE or ALE asserted (read access) can produce
undefined results.
• Write accesses to the GPMC_NAND_COMMAND_i register location and to the
GPMC_NAND_ADDRESS_i register location must be posted for faster operations. The
GPMC_CONFIG[0] NANDFORCEPOSTEDWRITE bit enables write accesses to these locations as
posted, even if they are defined as nonposted.
A write buffer is used to store write transaction information before the external device is accessed:
• Up to eight consecutive posted write accesses can be accepted and stored in the write buffer.
• For nonposted write, the pipeline is one deep.
• A GPMC_STATUS[0] EMPTYWRITEBUFFERSTATUS bit stores the empty status of the write buffer.
The GPMC_NAND_COMMAND_i and GPMC_NAND_ADDRESS_i registers are 32-bit word locations,
which means any 32-bit word or 16-bit word access is split into 4- or 2-byte accesses if an 8-bit wide
NAND device is attached. For multiple-command phase or multiple-address phase, the software driver can
use 32-bit word or 16-bit word access to these registers, but it must account for the splitting and little-
endian ordering scheme. When only one byte command or address phase is required, only byte write
access to a GPMC_NAND_COMMAND_i and GPMC_NAND_ADDRESS_i can be used, and any of the
four byte locations of the registers are valid.
The same applies to GPMC_NAND_COMMAND_i and GPMC_NAND_ADDRESS_i 32-bit word write
access to a 16-bit wide NAND device (split into two 16-bit word accesses). In the case of a 16-bit word
write access, the MSByte of the 16-bit word value must be set according to the NAND device requirement
(usually 0). Either 16-bit word location or any one of the four byte locations of the registers is valid

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7.1.2.3.12.1.3 Command Latch Cycle

Writing data at the GPMC_NAND_COMMAND_i location places the data as the NAND command value on
the bus, using a regular asynchronous write access.
• CSn[i] is controlled by the CSONTIME and CSWROFFTIME timing parameters.
• CLE is controlled by the ADVONTIME and ADVWROFFTIME timing parameters.
• WE is controlled by the WEONTIME and WEOFFTIME timing parameters.
• ALE and REn (OEn) are maintained inactive.
Figure 7-27 shows the NAND command latch cycle.
CLE is shared with the BE0n output signal and has an inverted polarity from BE0n. The NAND qualifier
deals with this. During the asynchronous NAND data access cycle, BE0n (also BE1n) must not toggle,
because it is shared with CLE.
NAND Flash memories do not use byte enable signals at all.
Figure 7-27. NAND Command Latch Cycle

WRCYCLETIME
CSWROFFTIME
CSONTIME = 0
nCS
nBE0/CLE
WEOFFTIME
WEONTIME = 0
nWE
nADV/ALE
D[15:0] Command

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7.1.2.3.12.1.4 Address Latch Cycle

Writing data at the GPMC_NAND_ADDRESS_i location places the data as the NAND partial address
value on the bus, using a regular asynchronous write access.
• CSn is controlled by the CSONTIME and CSWROFFTIME timing parameters.
• ALE is controlled by the ADVONTIME and ADVWROFFTIME timing parameters.
• WEn is controlled by the WEONTIME and WEOFFTIME timing parameters.
• CLE and REn (OEn) are maintained inactive.
Figure 7-28 shows the NAND address latch cycle.
ALE is shared with the ADVn output signal and has an inverted polarity from ADVn. The NAND qualifier
deals with this. During the asynchronous NAND data access cycle, ALE is kept stable.
Figure 7-28. NAND Address Latch Cycle

WRCYCLETIME
CSWROFFTIME = WRCYCLETIME
CSONTIME = 0
nCS
nBE0/CLE
WEOFFTIME
WEONTIME = 0
nWE
ADVWROFFTIME = WRCYCLETIME
ADVONTIME = 0
nADV/ALE
D[15:0] Address

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7.1.2.3.12.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
NAND device data read and write accesses are achieved through a read or write request to the chip-
select-associated memory region at any address location in the region or through a read or write request
to the GPMC_NAND_DATA_i location mapped in the chip-select-associated control register region.
GPMC_NAND_DATA_i is not a true register, but an address location to enable REn or WEn signal
control. The associated chip-select signal timing control must be programmed according to the NAND
device timing specification.
Reading data from the GPMC_NAND_DATA_i location or from any location in the associated chip-select
memory region activates an asynchronous read access.
• CSn is controlled by the CSONTIME and CSRDOFFTIME timing parameters.
• REn is controlled by the OEONTIME and OEOFFTIME timing parameters.
• To take advantage of REn high-to-data invalid minimum timing value, the RDACCESSTIME can be set
so that data are effectively captured after REn deassertion. This allows optimization of NAND read
access cycle time completion. For optimal timing parameter settings, see the NAND device and the
device IC timing parameters.
ALE, CLE, and WEn are maintained inactive.
Figure 7-29 shows the NAND data read cycle.
Figure 7-29. NAND Data Read Cycle

RDCYCLETIME
CSRDOFFTIME = RDCYCLETIME
CSONTIME = 0
nCS
nBE0/CLE
RDACCESSTIME
OEOFFTIME
OEONTIME = 0
nOE/nRE
nADV/ALE
D[15:0] Data
WAIT
Writing data to the GPMC_NAND_DATA_i location or to any location in the associated chip-select
memory region activates an asynchronous write access.
• CSn is controlled by the CSONTIME and CSWROFFTIME timing parameters.
• WEn is controlled by the WEONTIME and WEOFFTIME timing parameters.
• ALE, CLE, and REn (OEn) are maintained inactive.
Figure 7-30 shows the NAND data write cycle.

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Figure 7-30. NAND Data Write Cycle

WRCYCLETIME
CSONTIME = 0
CSWROFFTIME = WRCYCLETIME
nCS
nBE0/CLE
WEOFFTIME
WEONTIME = 0
nWE
D [15:0] Data
7.1.2.3.12.1.6 NAND Device General Chip-Select Timing Control Requirement

For most NAND devices, read data access time is dominated by CSn-to-data-valid timing and has faster
REn-to-data-valid timing. Successive accesses with CSn deassertions between accesses are affected by
this timing constraint. Because accesses to a NAND device can be interleaved with other chip-select
accesses, there is no certainty that CSn always stays low between two accesses to the same chip-select.
Moreover, an CSn deassertion time between the same chip-select NAND accesses is likely to be required
as follows: the CSn deassertion requires programming CYCLETIME and RDACCESSTIME according to
the CSn-to-data-valid critical timing.
To get full performance from NAND read and write accesses, the prefetch engine can dynamically reduce
RDCYCLETIME, WRCYCLETIME, RDACCESSTIME, WRACCESSTIME, CSRDOFFTIME,
CSWROFFTIME, ADVRDOFFTIME, ADVWROFFTIME, OEOFFTIME, and WEOFFTIME on back-to-back
NAND accesses (to the same memory) and suppress the minimum CSn high pulse width between
accesses. For more information about optimal prefetch engine access, see Section 7.1.2.3.12.4.
Some NAND devices require minimum write-to-read idle time, especially for device-status read accesses
following status-read command programming (write access). If such write-to-read transactions are used, a
minimum CSn high pulse width must be set. For this, CYCLE2CYCLESAMECSEN and
CYCLE2CYCLEDELAY must be set according to the appropriate timing requirement to prevent any timing
violation.
NAND devices usually have an important REn high to data bus in tristate mode. This requires a bus
turnaround setting (BUSTURNAROUND = 1), so that the next access to a different chip-select is delayed
until the BUSTURNAROUND delay completes. Back-to-back NAND read accesses to the same NAND
Flash are not affected by the programmed bus turnaround delay.
7.1.2.3.12.1.7 Read and Write Access Size Adaptation
7.1.2.3.12.1.7.1 8-Bit Wide NAND Device

Host 16-bit word and 32-bit word read and write access requests to a chip-select associated with an 8-bit
wide NAND device are split into successive read and write byte accesses to the NAND memory device.
Byte access is ordered according to little-endian organization. A NAND 8-bit wide device must be
interfaced on the D0D7 interface bus lane. GPMC data accesses are justified on this bus lane when the
chip-select is associated with an 8-bit wide NAND device.
7.1.2.3.12.1.7.2 16-Bit Wide NAND Device

Host 32-bit word read and write access requests to a chip-select associated with a 16-bit wide NAND
device are split into successive read and write 16-bit word accesses to the NAND memory device. 16-bit
word access is ordered according to little-endian organization.

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Host byte read and write access requests to a 16-bit wide NAND device are completed as 16-bit accesses
on the device itself, because there is no byte-addressing capability on 16-bit wide NAND devices. This
means that the NAND device address pointer is incremented on a 16-bit word basis and not on a byte
basis. For a read access, only the requested byte is given back to the host, but the remaining byte is not
stored or saved by the GPMC, and the next byte or 16-bit word read access gets the next 16-bit word
NAND location. For a write access, the invalid byte part of the 16-bit word is driven to FF, and the next
byte or 16-bit word write access programs the next 16-bit word NAND location.
Generally, byte access to a 16-bit wide NAND device should be avoided, especially when ECC calculation
is enabled. 8-bit or 16-bit ECC-based computations are corrupted by a byte read to a 16-bit wide NAND
device, because the nonrequested byte is considered invalid on a read access (not captured on the
external data bus; FF is fed to the ECC engine) and is set to FF on a write access.
Host requests (read/write) issued in the chip-select memory region are translated in successive single or
split accesses (read/write) to the attached device. Therefore, incrementing 32-bit burst requests are
translated in multiple 32-bit sequential accesses following the access adaptation of the 32-bit to 8- or 16-
bit device.
7.1.2.3.12.2 NAND Device-Ready Pin

The NAND memory device provides a ready pin to indicate data availability after a block/page opening
and to indicate that data programming is complete. The ready pin can be connected to one of the WAIT
GPMC input pins; data read accesses must not be tried when the ready pin is sampled inactive (device is
not ready) even if the associated chip-select WAITREADMONITORING bit field is set. The duration of the
NAND device busy state after the block/page opening is so long (up to 50 µs) that accesses occurring
when the ready pin is sampled inactive can stall GPMC access and eventually cause a system time-out.
If a read access to a NAND flash is done using the wait monitoring mode, the device is blocked during a
page opening, and so is the GPMC. If the correct settings are used, other chip-selects can be used while
the memory processes the page opening command.
To avoid a time-out caused by a block/page opening delay in NAND flash, disable the wait pin monitoring
for read and write accesses (that is, set the GPMC_CONFIG1_i[[21] WAITWRITEMONITORING and
GPMC_CONFIG1_i[[22] WAITREADMONITORING bits to 0 and use one of the following methods
instead:
• Use software to poll the WAITnSTATUS bit (n = 0 to 1) of the GPMC_STATUS register.
• Configure an interrupt that is generated on the WAIT signal change (through the GPMC_IRQENABLE
[11-8]bits).
Even if the READWAITMONITORING bit is not set, the external memory nR/B pin status is captured in the
programmed WAIT bit in the GPMC_STATUS register.
The READWAITMONITORING bit method must be used for other memories than NAND flash, if they
require the use of a WAIT signal.
7.1.2.3.12.2.1 Ready Pin Monitored by Software Polling

The ready signal state can be monitored through the GPMC_STATUS WAITxSTATUS bit (x = 0 or 1). The
software must monitor the ready pin only when the signal is declared valid. Refer to the NAND device
timing parameters to set the correct software temporization to monitor ready only after the invalid window
is complete from the last read command written to the NAND device.
7.1.2.3.12.2.2 Ready Pin Monitored by Hardware Interrupt

Each gpmc_wait input pin can generate an interrupt when a wait-to-no-wait transition is detected.
Depending on whether the GPMC_CONFIG WAITxPINPOLARITY bits (x = 0 or 1) is active low or active
high, the wait-to-no-wait transition is a low-to-high external WAIT signal transition or a high-to-low external
WAIT signal transition, respectively.

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The wait transition pin detector must be cleared before any transition detection. This is done by writing 1
to the WAITxEDGEDETECTIONSTATUS bit (x = 0 or 1) of the GPMC_IRQSTATUS register according to
the gpmc_wait pin used for the NAND device-ready signal monitoring. To detect a wait-to-no-wait
transition, the transition detector requires a wait active time detection of a minimum of two GPMC_FCLK
cycles. Software must incorporate precautions to clear the wait transition pin detector before wait (busy)
time completes.
A wait-to-no-wait transition detection can issue a GPMC interrupt if the WAITxEDGEDETECTIONENABLE
bit in the GPMC_IRQENABLE register is set and if the WAITxEDGEDETECTIONSTATUS bit field in the
GPMC_IRQSTATUS register is set.
The WAITMONITORINGTIME field does not affect wait-to-no-wait transition time detection.
It is also possible to poll the WAITxEDGEDETECTIONSTATUS bit field in the GPMC_IRQSTATUS
register according to the gpmc_wait pin used for the NAND device ready signal monitoring.
7.1.2.3.12.3 ECC Calculator

The General Purpose Memory Controller includes an Error Code Correction (ECC) calculator circuitry that
enables on the fly ECC calculation during data read or data program (that is, write) operations. The page
size supported by the ECC calculator in one calculation/context is 512 bytes.
The user can choose from two different algorithms with different error correction capabilities through the
GPMC_ECC_CONFIG[16] ECCALGORITHM bit:
• Hamming code for 1-bit error code correction on 8- or 16-bit NAND Flash organized with page size
greater than 512 bytes
• BCH (Bose-Chaudhurl-Hocquenghem) code for 4- to 16-bit error correction
The GPMC does not directly handle the error code correction itself. During writes, the GPMC computes
parity bits. During reads, the GPMC provides enough information for the processor to correct errors
without reading the data buffer all over again.
The Hamming code ECC is based on a 2-dimensional (row and column) bit parity accumulation. This
parity accumulation is either accomplished on the programmed number of bytes or 16-bit words read from
the memory device, or written to the memory device in stream mode.
Because the ECC engine includes only one accumulation context, it can be allocated to only one chip-
select at a time through the GPMC_ECC_CONFIG[3-1] ECCCS bit field. Even if two CS use different ECC
algorithms, one the Hamming code and the other a BCH code, they must define separate ECC contexts
because some of the ECC registers are common to all types of algorithms.
7.1.2.3.12.3.1 Hamming Code

All references to Error Code Correction (ECC) in this subsection refer to the 1-bit error correction
Hamming code.
The ECC is based on a two-dimensional (row and column) bit parity accumulation known as Hamming
Code. The parity accumulation is done for a programmed number of bytes or 16-bit word read from the
memory device or written to the memory device in stream mode.
There is no automatic error detection or correction, and it is the software NAND driver responsibility to
read the multiple ECC calculation results, compare them to the expected code value, and take the
appropriate corrective actions according to the error handling strategy (ECC storage in spare byte, error
correction on read, block invalidation).
The ECC engine includes a single accumulation context. It can be allocated to a single designated chip-
select at a time and parallel computations on different chip-selects are not possible. Since it is allocated to
a single chip-select, the ECC computation is not affected by interleaved GPMC accesses to other chip-
selects and devices. The ECC accumulation is sequentially processed in the order of data read from or
written to the memory on the designated chip-select. The ECC engine does not differentiate read
accesses from write accesses and does not differentiate data from command or status information. It is
the software responsibility to make sure only relevant data are passed to the NAND flash memory while
the ECC computation engine is active.

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The starting NAND page location must be programmed first, followed by an ECC accumulation context
reset with an ECC enabling, if required. The NAND device accesses discussed in the following sections
must be limited to data read or write until the specified number of ECC calculations is completed.
7.1.2.3.12.3.1.1 ECC Result Register and ECC Computation Accumulation Size

The GPMC includes up to nine ECC result registers (GPMC_ECCj_RESULT, j = 1 to 9) to store ECC
computation results when the specified number of bytes or 16-bit words has been computed.
The ECC result registers are used sequentially; one ECC result is stored in one ECC result register on the
list, the next ECC result is stored in the next ECC result register on the list, and so forth, until the last ECC
computation. The value of the GPMC_ECCj_RESULT register value is valid only when the programmed
number of bytes or 16-bit words has been accumulated, which means that the same number of bytes or
16-bit words has been read from or written to the NAND device in sequence.
The GPMC_ECC_CONTROL[3-0] ECCPOINTER field must be set to the correct value to select the ECC
result register to be used first in the list for the incoming ECC computation process. The ECCPointer can
be read to determine which ECC register is used in the next ECC result storage for the ongoing ECC
computation. The value of the GPMC_ECCj_RESULT register (j = 1 to 9) can be considered valid when
ECCPOINTER equals j + 1. When the GPMC_ECCj_RESULT (where j = 9) is updated, ECCPOINTER is
frozen at 10, and ECC computing is stopped (ECCENABLE = 0).
The ECC accumulator must be reset before any ECC computation accumulation process. The
GPMC_ECC_CONTROL[8] ECCCLEAR bit must be set to 1 (nonpersistent bit) to clear the accumulator
and all ECC result registers.
For each ECC result (each register, j = 1 to 9), the number of bytes or 16-bit words used for ECC
computing accumulation can be selected from between two programmable values.
The ECCjRESULTSIZE bits (j = 1 to 9) in the GPMC_ECC_SIZE_CONFIG register select which
programmable size value (ECCSIZE0 or ECCSIZE1) must be used for this ECC result (stored in
GPMC_ECCj_RESULT register ).
The ECCSIZE0 and ECCSIZE1 fields allow selection of the number of bytes or 16-bit words used for ECC
computation accumulation. Any even values from 2 to 512 are allowed.
Flexibility in the number of ECCs computed and the number of bytes or 16-bit words used in the
successive ECC computations enables different NAND page error-correction strategies. Usually based on
256 or 512 bytes and on 128 or 256 16-bit word, the number of ECC results required is a function of the
NAND device page size. Specific ECC accumulation size can be used when computing the ECC on the
NAND spare byte.
For example, with a 2 Kbyte data page 8-bit wide NAND device, eight ECCs accumulated on 256 bytes
can be computed and added to one extra ECC computed on the 24 spare bytes area where the eight ECC
results used for comparison and correction with the computed data page ECC are stored. The GPMC then
provides nine GPMC_ECCj_RESULT registers (j= 1 to 9) to store the results. In this case, ECCSIZE0 is
set to 256, and ECCSIZE1 is set to 24; the ECC[1-8]RESULTSIZE bits are cleared to 0, and the
ECC9RESULTSIZE bit is set to 1.
7.1.2.3.12.3.1.2 ECC Enabling

The GPMC_ECC_CONFIG[3-1] ECCCS field selects the allocated chip-select. The
GPMC_ECC_CONFIG[0] ECCENABLE bit enables ECC computation on the next detected read or write
access to the selected chip-select.
The ECCPOINTER, ECCCLEAR, ECCSIZE, ECCjRESULTSIZE (where j = 1 to 9), ECC16B, and ECCCS
fields must not be changed or cleared while an ECC computation is in progress.
The ECC accumulator and ECC result register must not be changed or cleared while an ECC computation
is in progress.
ECC Enable Settings describes the ECC enable settings.

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ECC Enable Settings

ECCCS GPMC_ECC_CONFIG 0-3h Selects the chip-select where ECC is computed
ECC16B GPMC_ECC_CONFIG 0/1 Selects column number for ECC calculation
ECCCLEAR GPMC_ECC_CONTROL 0-7h Clears all ECC result registers
ECCPOINTER GPMC_ECC_CONTROL 0-7h A write to this bit field selects the ECC result register where
the first ECC computation is stored. Set to 1 by default.
ECCSIZE1 GPMC_ECC_SIZE_CONFIG 0-FFh Defines ECCSIZE1
ECCSIZE0 GPMC_ECC_SIZE_CONFIG 0-FFh Defines ECCSIZE0
ECCjRESULTSIZE GPMC_ECC_SIZE_CONFIG 0/1 Selects the size of ECCn result register
(j from 1 to 9)
ECCENABLE GPMC_ECC_CONFIG 1 Enables the ECC computation
7.1.2.3.12.3.1.3 ECC Computation

The ECC algorithm is a multiple parity bit accumulation computed on the odd and even bit streams
extracted from the byte or Word 16 streams. The parity accumulation is split into row and column
accumulations, as shown in Figure 7-31 and Figure 7-32. The intermediate row and column parities are
used to compute the upper level row and column parities. Only the final computation of each parity bit is
used for ECC comparison and correction.
P1o = bit7 XOR bit5 XOR bit3 XOR bit1 on each byte of the data stream
P1e = bit6 XOR bit4 XOR bit2 XOR bit0 on each byte of the data stream
Each column parity bit is XORed with the previous accumulated value.
Figure 7-31. Hamming Code Accumulation Algorithm (1 of 2)
Row 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Row 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
P1o P1o P1o P1o P1o P1o P1o P1o
P2o P2o

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For line parities, the bits of each new data are XORed together, and line parity bits are computed as:
P8e = row0 XOR row2 XOR row4 XOR ... XOR row254
P8o = row1 XOR row3 XOR row5 XOR ... XOR row255
P16e = row0 XOR row1 XOR row4 XOR row5 XOR ... XOR row252 XOR row 253
P16o = row2 XOR row3 XOR row6 XOR row7 XOR ... XOR row254 XOR row 255
Unused parity bits in the result registers are cleared to 0.
Figure 7-32. Hamming Code Accumulation Algorithm (2 of 2)
Row 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e Row 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e P16e
Row 2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e Row 2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e
Row 252 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e Row 252 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e P16e
Row 254 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e Row 254 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e
P1o P1o P1o P1o P1o P1o P1o P1o
P2o P2o P2o P2o
Figure 7-33 shows ECC computation for a 256-byte data stream (read or write). The result includes six
column parity bits (P1o-P2o-P4o for odd parities, and P1e-P2e-P4e for even parities) and sixteen row
parity bits (P8o-P16o-P32o--P1024o for odd parities, and P8e-P16e-P32e--P1024e for even parities).
Figure 7-33. ECC Computation for a 256-Byte Data Stream (Read or Write)
256 byte
Bytes input
input
Row 00
Row bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e P16e
Row 11
Row bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8o
P8o
P1024e
Row 22
Row bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e P16o
P16o
Row 33
Row bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8o
P8o
Row 252
Row 252 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e P16e
Row 253
Row 253 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8o
P8o
P1024o
P1024o
Row 254
Row 254 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e P16o
P16o
Row 255
P8o
P1o
P1o P1e P1o
P1o P1e P1o
P1o P1e P1o
P1o P1e
P2o
P2o P2e P2o
P2o P2e
P4o
P4o P4e

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Figure 7-34 shows ECC computation for a 512-byte data stream (read or write). The result includes six
column parity bits (P1o-P2o-P4o for odd parities, and P1e-P2e-P4e for even parities) and eighteen row
parity bits (P8o-P16o-P32o--P1024o- - P2048o for odd parities, and P8e-P16e-P32e--P1024e- P2048e for
even parities).
For a 2 Kbytes page, four 512 bytes ECC calculations plus one for the spare area are required. Results
are stored in the GPMC_ECCj_RESULT registers (j = 1 to 9).
Figure 7-34. ECC Computation for a 512-Byte Data Stream (Read or Write)
512 byte input
P2048e
Row 509 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8o P2048o
P1o P1e P1o P1e P1o P1e P1o P1e
P2o P2e P2o P2e
P4o P4e
7.1.2.3.12.3.1.4 ECC Comparison and Correction

To detect an error, the computed ECC result must be XORed with the parity value stored in the spare
area of the accessed page.
• If the result of this logical XOR is all 0s, no error is detected and the read data is correct.
• If every second bit in the parity result is a 1, one bit is corrupted and is located at bit address (P2048o,
P1024o, P512o, P256o, P128o, P64o, P32o, P16o, P8o, P4o, P2o, P1o). The software must correct
the corresponding bit.
• If only one bit in the parity result is 1, it is an ECC error and the read data is correct.
7.1.2.3.12.3.1.5 ECC Calculation Based on 8-Bit Word

The 8-bit based ECC computation is used for 8-bit wide NAND device interfacing.
The 8-bit based ECC computation can be used for 16-bit wide NAND device interfacing to get backward
compatibility on the error-handling strategy used with 8-bit wide NAND devices. In this case, the 16-bit
wide data read from or written to the NAND device is fragmented into 2 bytes. According to little-endian
access, the least significant bit (LSB) of the 16-bit wide data is ordered first in the byte stream used for 8-
bit based ECC computation.

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7.1.2.3.12.3.1.6 ECC Calculation Based on 16-Bit Word

ECC computation based on a 16-bit word is used for 16-bit wide NAND device interfacing. This ECC
computation is not supported when interfacing an 8-bit wide NAND device, and the
GPMC_ECC_CONFIG[7] ECC16B bit must be cleared to 0 when interfacing an 8-bit wide NAND device.
The parity computation based on 16-bit words affects the row and column parity mapping. The main
difference is that the odd and even parity bits P8o and P8e are computed on rows for an 8-bit based ECC
while there are computed on columns for a 16-bit based ECC. Figure 7-35 and Figure 7-36.
Figure 7-35. 128 Word16 ECC Computation
256 byte
256 Bytes input
input
st
1st
1 row
row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16e P32e
2ndt row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16o
P1024e
3rd row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16e P32o
4th row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16o
123th row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16e P32e
124th t row
124th bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16o
P1024o
125th row
125th bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16e P32o
th
128 row
128th bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16o
P1o P1e P1o P1e P1o P1e P1o P1e P1o P1e P1o P1e P1o P1e P1o P1e
P4o P4e P4o P4e
P8o P8e
Figure 7-36. 256 Word16 ECC Computation
512 Bytes
51-bytes input
input
st
1st
1 row
row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16e P32e
2ndt row
2nd row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16o P2048e
3rd
3rd row
row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16e P32o
4th
4th row
row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16o
253th row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16e P32e
th t P2048o
254
254th row
th
255
255throw
row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16e P32o
th
256
256th row
P1o P1e P1o P1e P1o P1e P1o P1e P1o P1e P1o P1e P1o P1e P1o P1e
P4o P4e P4o P4e
P8o P8e

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7.1.2.3.12.3.2 BCH Code (Bose-Chaudhurl-Hocquenghem)

All references to Error Code Correction (ECC) in this subsection refer to the 4- to 16-bit error correction
BCH code.
7.1.2.3.12.3.2.1 Requirements
Read and write accesses to a NAND flash take place by whole pages, in a predetermined sequence: first
the data byte page itself, then some spare bytes, including the BCH ECC (and other information). The
NAND IC can cache a full page, including spares, for read and write accesses.
Typical page write sequence:
• Sequential write to NAND cache of main data + spare data, for a page. ECC is calculated on the fly.
Calculated ECC may be inserted on the fly in the spares, or replaced by dummy accesses.
• When the calculated ECC is replaced by dummy accesses, it must be written to the cache in a second,
separate phase. The ECC module is disabled during that time.
• NAND writes its cache line (page) to the array
Typical page read sequence:
• Sequential read of a page. ECC is calculated on the fly.
• ECC module buffers status determines the presence of errors.
• Accesses to several memories may be interleaved by the GPMC, but only one of those memories can
be a NAND using the BCH engine at a time; in other words, only one BCH calculation (for example, for
a single page) can be on-going at any time. Note also that the sequential nature of NAND accesses
guarantees that the data is always written / read out in the same order. BCH-relevant accesses are
selected by the GPMCs chip-select.
• Each page may hold up to 4 Kbytes of data, spare bytes not included. This means up to 8 x 512-byte
BCH messages. Since all the data is written / read out first, followed by the BCH ECC, this means that
the BCH engine must be able to hold 8 104-bit remainders or syndromes (or smaller, 52-bit ones) at
the same time.
The BCH module has the capacity to store all remainders internally. After the page start, an internal
counter is used to detect the 512-byte sector boundaries. On those boundaries, the current remainder is
stored and the divider reset for the next calculation. At the end of the page, the BCH module contains all
remainders.
• NAND access cycles hold 8 or 16 bits of data each (1 or 2 bytes); Each NAND cycle takes at least 4
cycles of the GPMCs internal clock. This means the NAND flash timing parameters must define a
RDCYCLETIME and a WRCYCLETIME of at least 4 clock cycles after optimization when using the
BCH calculator.
• The spare area is assumed to be large enough to hold the BCH ECC, that is, to have at least a
message of 13 bytes available per 512-byte sector of data. The zone of unused spare area by the
ECC may or may not be protected by the same ECC scheme, by extending the BCH message beyond
512 bytes (maximum codeword is 1023-byte long, ECC included, which leaves a lot of space to cover
some spares bytes).

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7.1.2.3.12.3.2.2 Memory-Mapping of the BCH Codeword

BCH encoding considers a block of data to protect as a polynomial message M(x). In our standard case,
512 bytes of data (that is, 2 bits = 4096 bits) are seen as a polynomial of degree 2 - 1 = 4095, with
parameters ranging from M0 to M4095. For 512 bytes of data, 52 bits are required for 4-bit error
correction, and 104 bits are required for 8-bit error correction and 207 bits are required for 16-bit error
correction. The ECC is a remainder polynomial R(x) of degree 103 (or 51, depending on the selected
mode). The complete codeword C(x) is the concatenation of M(x) and R(x) as shown in Table 7-11.
Table 7-11. Flattened BCH Codeword Mapping (512 Bytes + 104 Bits)
Message M(x) ECC R(x)
Bit number M4095 ... M0 R103 ... R0
If the message is extended by the addition of spare bytes to be protected by the same ECC, the principle
is still valid. For example, a 3-byte extension of the message gives a polynomial message M(x) of degree
((512 + 3) × 8) - 1 = 4119, for a total of 3 + 13 = 16 spare bytes of spare, all protected as part of the same
codeword.
The message and the ECC bits are manipulated and mapped in the GPMC byte-oriented system. The
ECC bits are stored in:
• GPMC_BCH_RESULT0_i
7.1.2.3.12.3.2.3 Memory Mapping of the Data Message

The data message mapping shall follow the following rules:
• Bit endianness within a byte is little-endian, that is, the bytes LS bit is also the lowest-degree
polynomial parameter: a byte b7-b0 (with b0 the LS bit) represents a segment of polynomial b7 * x +
b6 * x + ... + b0 * x
• The message is mapped in the NAND starting with the highest-order parameters, that is, in the lowest
addresses of a NAND page.
• Byte endianness within the NANDs 16-bit words is big endian. This means that the same message
mapped in 8- and 16-bit memories has the same content at the same byte address.
The BCH module has no visibility over actual addresses. The most important point is the sequence of data
word the BCH sees. However, the NAND page is always scanned incrementally in read and write
accesses, and this produces the mapping patterns described in the following.
Table 7-12 and Table 7-13 show the mapping of the same 512-byte vector (typically a BCH message) in
the NAND memory space. Note that the byte 'address' is only an offset modulo 512 (200h), since the
same page may contain several contiguous 512-byte sectors (BCH blocks). The LSB and MSB are
respectively the bits M0 and M(2^12-1) of the codeword mapping given above. In both cases the data
vectors are aligned, that is, their boundaries coincide with the RAMs data word boundaries.
Table 7-12. Aligned Message Byte Mapping in 8-bit NAND

Byte Offset 8-Bit Word
0 (msb) Byte 511 (1FFh)
1h Byte 510 (1FEh)
⋮ ⋮
1FFh Byte 0 (0) (LSB)

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Table 7-13. Aligned Message Byte Mapping in 16-bit NAND

Byte Offset 16-Bit Words MSB 16-Bit Words LSB
0 Byte 510 (1FEh) (msb) Byte 511 (1FFh)
2h Byte 508 (1FCh) Byte 509 (1FDh)
⋮ ⋮ ⋮
1FEh Byte 0 (0) (lsb) Byte 1 (1)
Table 7-14 and Table 7-15 show the mapping in memory of arbitrarily-sized messages, starting on access
(byte or 16-bit word) boundaries for more clarity. Note that message may actually start and stop on
arbitrary nibbles. A nibble is a 4-bit entity. The unused nibbles are not discarded, and they can still be
used by the BCH module, but as part of the next message section (for example, on another sectors ECC).
Table 7-14. Aligned Nibble Mapping of Message in 8-bit NAND

8-Bit Word
Byte Offset
4-Bit Most Significant Nibble 4-Bit Less Significant Nibble
1 (MSB) Nibble S-1 Nibble S-2
2 Nibble S-3 Nibble S-4
⋮ ⋮ ⋮
S/2 - 2 Nibble 3 Nibble 2
S/2 - 1 Nibble 1 Nibble 0 (LSB)
Table 7-15. Misaligned Nibble Mapping of Message in 8-bit NAND

8-Bit Word
Byte Offset
1 (MSB) Nibble S-1 Nibble S-2
2 Nibble S-3 Nibble S-4
⋮ ⋮ ⋮
(S+1)/2 - 2 Nibble 2 Nibble 1
(S+1)/2 - 1 Nibble 0 (LSB)
Table 7-16. Aligned Nibble Mapping of Message in 16-bit NAND

16-Bit Word
Byte Offset
0 Nibble S-3 Nibble S-4 (MSB) Nibble S-1 Nibble S-2
2 Nibble S-7 Nibble S-8 Nibble S-5 Nibble S-6
⋮ ⋮ ⋮ ⋮ ⋮
S/2 - 4 Nibble 5 Nibble 4 Nibble 7 Nibble 6
S/2 - 2 Nibble 1 Nibble 0 (LSB) Nibble 3 Nibble 2

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Table 7-17. Misaligned Nibble Mapping of Message in 16-bit NAND (1 Unused Nibble)
16-Bit Word
Byte Offset
⋮ ⋮ ⋮ ⋮ ⋮
(S+1)/2 - 4 Nibble 4 Nibble 3 Nibble 6 Nibble 5
(S+1)/2 - 2 Nibble 0 (LSB) Nibble 2 Nibble 1
16-Bit Word
Byte Offset
⋮ ⋮ ⋮ ⋮ ⋮
(S+2)/2 - 2 Nibble 1 Nibble 0 (LSB)
16-Bit Word
Byte Offset
⋮ ⋮ ⋮ ⋮ ⋮
(S+3)/2 - 2 Nibble 0 (LSB)
Note that many other cases exist than the ones represented above, for example, where the message does
not start on a word boundary.
7.1.2.3.12.3.2.4 Memory Mapping of the ECC

The ECC (or remainder) is presented by the BCH module as a single 104-bit (or 52-bit), little-endian
vector. It is up to the software to fetch those 13 bytes (or 6 bytes) from the modules interface, then store
them to the NANDs spare area (page write) or to an intermediate buffer for comparison with the stored
ECC (page read). There are no constraints on the ECC mapping inside the spare area: it is a
softwarecontrolled operation.
However, it is advised to maintain a coherence in the respective formats of the message or the ECC
remainder once they have been read out of the NAND. The error correction algorithm works from the
complete codeword (concatenated message and remainder) once an error as been detected. The creation
of this codeword should be made as straightforward as possible.

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There are cases where the same NAND access contains both data and the ECC protecting that data. This
is the case when the data/ECC boundary (which can be on any nibble) does not coincide with an access
boundary. The ECC is calculated on-the-fly following the write. In that case, the write must also contain
part of the ECC because it is impossible to insert the ECC on-the-fly. Instead:
• During the initial page write (BCH encoding), the ECC is replaced by dummy bits. The BCH encoder is
by definition turned OFF during the ECC section, so the BCH result is unmodified.
• During a second phase, the ECC is written to the correct location, next to the actual data.
• The completed line buffer is then written to the NAND array.
7.1.2.3.12.3.2.5 Wrapping Modes

For a given wrapping mode, the module automatically goes through a specific number of sections, as data
is being fed into the module. For each section, the BCH core can be enabled (in which case the data is
fed to the BCH divider) or not (in which case the BCH simply counts to the end of the section). When
enabled, the data is added to the ongoing calculation for a given sector number (for example, number 0).
Wrapping modes are described below. To get a better understanding and see the real-life read and write
sequences implemented with each mode, see Section 7.1.2.3.12.3.3.
For each mode:
• A sequence describes the mode in pseudo-language, with for each section the size and the buffer
used for ECC processing (if ON). The programmable lengths are size, size0 and size1.
• A checksum condition is given. If the checksum condition is not respected for a given mode, the
modules behavior is unpredictable. S is the number of sectors in the page; size0 and size1 are the
section sizes programmed for the mode, in nibbles.
Note that wrapping modes 8, 9, 10, and 11 insert a 1-nibble padding where the BCH processing is OFF.
This is intended for t = 4 ECC, where ECC is 6 bytes long and the ECC area is expected to include (at
least) 1 unused nibble to remain byte-aligned.
7.1.2.3.12.3.2.6 Manual Mode (0x0)

This mode is intended for short sequences, added manually to a given buffer through the software data
port input. A complete page may be built out of several such sequences.
To process an arbitrary sequence of 4-bit nibbles, accesses to the software data port shall be made,
containing the appropriate data. If the sequence end does not coincide with an access boundary (for
example, to process 5 nibbles = 20 bits in 16-bit access mode) and those nibbles need to be skipped, a
number of unused nibbles shall be programmed in size1 (in the same example: 5 nibbles to process + 3 to
discard = 8 nibbles = exactly 2 x 16-bit accesses: we must program size0 = 5, size1 = 3).
Figure 7-37 shows the manual mode sequence and mapping. In this figure, size and size0 are the same
parameter.
Figure 7-37. Manual Mode Sequence and Mapping
M0
Manual mode
to ECC divider unused
Protected data Unused data
Mode Size 0 Size 1 P U
Rd/Wr/ 0 U bch_blk_ptr inactive

P
SW
size 0 size1

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Section processing sequence:

• One time with buffer
– size0 nibbles of data, processing ON
– size1 nibbles of unused data, processing OFF
Checksum: size0 + size1 nibbles must fit in a whole number of accesses.
In the following sections, S is the number of sectors in the page.
7.1.2.3.12.3.2.7 Mode 0x1

Page processing sequence:
• Repeat with buffer 0 to S-1
– 512-byte data, processing ON
– size0 nibbles spare, processing ON
– size1 nibbles spare, processing OFF
Checksum: Spare area size (nibbles) = S - (size0 + size1)
7.1.2.3.12.3.2.8 Mode 0xA (10)

– 1 nibble pad spare, processing OFF
Checksum: Spare area size (nibbles) = S - (size0 + 1 + size1)
7.1.2.3.12.3.2.9 Mode 0x2

7.1.2.3.12.3.2.10 Mode 0x3

• One time with buffer 0
Checksum: Spare area size (nibbles) = size0 + (S - size1)

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7.1.2.3.12.3.2.11 Mode 0x7

• Repeat S times (no buffer used)
7.1.2.3.12.3.2.12 Mode 0x8

– 1 nibble padding spare, processing OFF
Checksum: Spare area size (nibbles) = size0 + (S - (1+size1))
7.1.2.3.12.3.2.13 Mode 0x4

• One time (no buffer used)
7.1.2.3.12.3.2.14 Mode 0x9

• One time (no buffer used)
Checksum: Spare area size (nibbles) = size0 + (S - (1+size1))

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7.1.2.3.12.3.2.15 Mode 0x5

7.1.2.3.12.3.2.16 Mode 0xB (11)

Checksum: Spare area size (nibbles) = S - (size0 + 1 + size1)
7.1.2.3.12.3.2.17 Mode 0x6

• Repeat S times (no buffer used)

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7.1.2.3.12.3.3 Supported NAND Page Mappings and ECC Schemes

The following rules apply throughout the entire mapping description:
• Main data area (sectors) size is hardcoded to 512 bytes.
• Spare area size is programmable.
• All page sections (of main area data bytes, protected spare bytes, unprotected spare bytes, and ECC)
are defined as explained in Section 7.1.2.3.12.3.2.3.
Each one of the following sections shows a NAND page mapping example (per-sector spare mappings,
pooled spare mapping, per-sector spare mapping, with ECC separated at the end of the page).
In the mapping diagrams, sections that belong to the same BCH codeword have the same color (blue or
green); unprotected sections are not covered (orange) by the BCH scheme.
Below each mapping diagram, a write (encoding) and read (decoding: syndrome generation) sequence is
given, with the number of the active buffers at each point in time (yellow). In the inactive zones (grey), no
computing is taking place but the data counter is still active.
In Figure 7-38 to Figure 7-40, tables on the left summarize the mode, size0, size1 parameters to program
for respectively write and read processing of a page, with the given mapping, where:
• P is the size of spare byte section Protected by the ECC (in nibbles)
• U is the size of spare byte section Unprotected by the ECC (in nibbles)
• E is the size of the ECC itself (in nibbles)
• S is the number of Sectors per page (2 in the current diagrams)
Each time the processing of a BCH block is complete (ECC calculation for write/encoding, syndrome
generation for read/decoding, indicated by red arrows), the update pointer is pulsed. Note that the
processing for block 0 can be the first or the last to complete, depending on the NAND page mapping and
operation (read or write). All examples show a page size of 1kByte + spares, that is, S = 2 sectors of 512
bytes. The same principles can be extended to larger pages by adding more sectors.
The actual BCH codeword size is used during the error location work to restrict the search range: by
definition, errors can only happen in the codeword that was actually written to the NAND, and not in the
mathematical codeword of n = 2 - 1 = 8191 bits. That codeword (higher-order bits) is all-zero and implicit
during computations.
The actual BCH codeword size depends on the mode, on the programmed sizes and on the sector
number (all sizes in nibbles):
• Spares mapped and protected per sector (Figure 7-38: see M1-M2-M3-M9-M10):
– all sectors: (512) + P + E
• Spares pooled and protected by sector 0 (Figure 7-38: see M5-M6):
– sector 0 codeword: (512) + P + E
– other sectors: (512) + E
• Unprotected spares (Figure 7-38: see M4-M7-M8-M11-M12):
– all codewords (512) + E

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7.1.2.3.12.3.3.1 Per-Sector Spare Mappings

In these schemes (Figure 7-38), each 512-byte sector of the main area has its own dedicated section of
the spare area. The spare area of each sector is composed of:
• ECC, which must be located after the data it protects
• other data, which may or may not be protected by the sectors ECC
Figure 7-38. NAND Page Mapping and ECC: Per-Sector Schemes
M1
Per-sector spares
Spares covered by sector ECC Sector data Sector data Sector spares Sector spares
per sector ECC mapping.
Data0 Data1 Prot0 Ecc0 Prot1 Ecc1
Mode Size0 Size1 512 bytes 512 bytes P E P E
Write 1 P E 0 1 0 inactive 1 inactive

size0 size1 size0 size1
Read 1 P+E 0 0 1 0 1
size0 size0
M2
Per-sector spares
Spares covered by sector ECC Sector data Sector data Sector spares Sector spares
per sector, left-padded ECC.
Data0 Data1 Prot0 Pad Ecc0 Prot1 Pad Ecc1
Mode Size0 Size1 512 bytes 512 bytes P 1 E P 1 E
Write 1 P 1+E 0 1 0 inactive 1 inactive

Read 10 P E 0 1 0 i. 0 1 i. 1
size0 1 size1 size0 1 size1
M3
Per-sector spares
Spares covered by sector ECC, Sector data Sector data Sector spares Sector spares
ECC not right-aligned.
Data0 Data1 Prot0 Ecc0 U0 Prot1 Ecc1 U1
Mode Size0 Size1 512 bytes 512 bytes P E U P E U
Write 1 P E+U 0 1 0 inactive 1 inactive

Read 1 P+E U 0 1 0 i. 1 i.
size0 s1 size0 s1
M4
Per-sector spares
Spares not covered by ECC, Sector data Sector data Sector spares Sector spares
ECC right-aligned per sector.
Data0 Data1 Unprot0 Ecc0 Unprot1 Ecc1
Mode Size0 Size1 512 bytes 512 bytes U E U E
Write 2 U+E 0 0 1 inactive

size0 size0
Read 2 U E 0 1 inactive 0 inactive 1

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7.1.2.3.12.3.3.2 Pooled Spare Mapping

In these schemes (Figure 7-39), the spare area is pooled for the page.
• The ECC of each sector is aligned at the end of the spare area.
• The non-ECC spare data may or may not be covered by the ECC of sector 0
Figure 7-39. NAND Page Mapping and ECC: Pooled Spare Schemes
M5
Pooled spares
Spares covered by ECC0. Sector data Sector data Pooled page spares
All ECC at the end (of page).
Data0 Data1 Protected (pooled) Ecc0 Ecc1
Mode Size0 Size1 512 bytes 512 bytes P E E
Write 7 P E 0 1 0 inactive
size0 size1 size1
Read 3 P E 0 1 0 1
size0 size1 size1
M6
Pooled spares
Spares covered by ECC0. Sector data Sector data Pooled page spares
All ECC at the end, left-padded.
Data0 Data1 Protected (pooled) Pad Ecc0 Pad Ecc1
Mode Size0 Size1 512 bytes 512 bytes P 1 E 1 E
Write 7 P 1+E 0 1 0 inactive

size0 size1 size1
Read 8 P E 0 1 0 i. 0 i. 1
size0 1 size1 1 size1
M7
Pooled spares
Spares not covered by ECC. Sector data Sector data Pooled page spares
All ECC at the end.
Data0 Data1 Unprotected (pooled) Ecc0 Ecc1
Mode Size0 Size1 512 bytes 512 bytes U E E
U/S
Write 6 0 0 1 inactive
+E
size1 size1
Read 4 U E 0 1 inactive 0 1
size0 size1 size1
M8
Pooled spares
Spares not covered by ECC. Sector data Sector data Pooled page spares
Data0 Data1 Unprotected (pooled) Pad Ecc0 Pad Ecc1
Mode Size0 Size1 512 bytes 512 bytes U 1 E 1 E
U/S
Write 6 0 0 1 inactive
+1+E
size1 size1
Read 9 U E 0 1 inactive 0 i. 1

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7.1.2.3.12.3.3.3 Per-Sector Spare Mapping, With ECC Separated at the End of the Page
In these schemes (Figure 7-40), each 512-byte sector of the main area is associated with two sections of
the spare area.
• ECC section, all aligned at the end of the page
• other data section, aligned before the ECCs, each of which may or may not be protected by its sectors
ECC
Figure 7-40. NAND Page Mapping and ECC: Per-Sector Schemes, with Separate ECC
M9
Per-sector spares, separate ECC
Spares covered by sector ECC. Sector data Sector data non-ECC spares ECC
All ECC at the end.
Data0 Data1 Prot0 Prot1 Ecc0 Ecc1
Mode Size0 Size1 512 bytes 512 bytes P P E E
Write 6 P E 0 1 0 1 inactive
Read 5 P E 0 1 0 1 0 1
M
10
Spares covered by sector ECC. Sector data Sector data non-ECC spares ECC
Data0 Data1 Prot0 Prot1 Pad Ecc0 Pad Ecc1
Mode Size0 Size1 512 bytes 512 bytes P P 1 E 1 E
Write 6 P 1+E 0 1 0 1 inactive

Read 11 P E 0 1 0 1 i. 0 i. 1
size0 size0 1 size1 1 size1
M
11 Spares not covered by ECC. Sector data Sector data non-ECC spares ECC
All ECC at the end.
Data0 Data1 Unprot0 Unprot1 Ecc0 Ecc1
Mode Size0 Size1 512 bytes 512 bytes U U E E
Write 6 0 U+E 0 1 inactive

size1 size1
Read 4 SU E 0 1 inactive 0 1
size0 size1 size1
M
12
Spares not covered by ECC. Sector data Sector data non-ECC spares ECC
Data0 Data1 Unprot0 Unprot1 Pad Ecc0 Pad Ecc1
Mode Size0 Size1 512 bytes 512 bytes U U 1 E 1 E
Write 6 0 U+1+E 0 1 inactive

size1 size1
Read 9 SU E 0 1 inactive 0 i. 1

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7.1.2.3.12.4 Prefetch and Write-Posting Engine

NAND device data access cycles are usually much slower than the MPU system frequency; such NAND
read or write accesses issued by the processor will impact the overall system performance, especially
considering long read or write sequences required for NAND page loading or programming. To minimize
this effect on system performance, the GPMC includes a prefetch and write-posting engine, which can be
used to read from or write to any chip-select location in a buffered manner.
The prefetch and write-posting engine is a simplified embedded-access requester that presents requests
to the access engine on a user-defined chip-select target. The access engine interleaves these requests
with any request coming from the L3 interface; as a default the prefetch and write-posting engine has the
lowest priority.
The prefetch and write-posting engine is dedicated to data-stream access (as opposed to random data
access); thus, it is primarily dedicated to NAND support. The engine does not include an address
generator; the request is limited to chip-select target identification. It includes a 64-byte FIFO associated
with a DMA request synchronization line, for optimal DMA-based use.
The prefetch and write-posting engine uses an embedded 64 bytes (32 16-bit word) FIFO to prefetch data
from the NAND device in read mode (prefetch mode) or to store host data to be programmed into the
NAND device in write mode (write-posting mode). The FIFO draining and filling (read and write) can be
controlled either by the MPU through interrupt synchronization (an interrupt is triggered whenever a
programmable threshold is reached) or the sDMA through DMA request synchronization, with a
programmable request byte size in both prefetch or posting mode.
The prefetch and write-posting engine includes a single memory pool. Therefore, only one mode, read or
write, can be used at any given time. In other words, the prefetch and write-posting engine is a single-
context engine that can be allocated to only one chip-select at a time for a read prefetch or a write-posting
process.
The engine does not support atomic command and address phase programming and is limited to linear
memory read or write access. In consequence, it is limited to NAND data-stream access. The engine
relies on the MPU NAND software driver to control block and page opening with the correct data address
pointer initialization, before the engine can read from or write to the NAND memory device.
Once started, the engine data reads and writes sequencing is solely based on FIFO location availability
and until the total programmed number of bytes is read or written.
Any host-concurrent accesses to a different chip-select are correctly interleaved with ongoing engine
accesses. The engine has the lowest priority access so that host accesses to a different chip-select do not
suffer a large latency.
A round-robin arbitration scheme can be enabled to ensure minimum bandwidth to the prefetch and write-
posting engine in the case of back-to-back direct memory requests to a different chip-select. If the
GPMC_PREFETCH_CONFIG1[23] PFPWENROUNDROBIN bit is enabled, the arbitration grants the
prefetch and write posting engine access to the GPMC bus for a number of requests programmed in the
GPMC_PREFETCH_CONFIG1[19-16] PFPWWEIGHTEDPRIO field.
The prefetch/write-posting engine read or write request is routed to the access engine with the chip-select
destination ID. After the required arbitration phase, the access engine processes the request as a single
access with the data access size equal to the device size specified in the corresponding chip-select
configuration.
The destination chip-select configuration must be set to the NAND protocol-compatible configuration for
which address lines are not used (the address bus is not changed from its current value). Selecting a
different chip-select configuration can produce undefined behavior.

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7.1.2.3.12.4.1 General Facts About the Engine Configuration

The engine can be configured only if the GPMC_PREFETCH_CONTROL[0] STARTENGINE bit is de-
asserted.
The engine must be correctly configured in prefetch or write-posting mode and must be linked to a NAND
chip-select before it can be started. The chip-select is linked using the GPMC_PREFETCH_CONFIG1[26-
24] ENGINECSSELECTOR field.
In both prefetch and write-posting modes, the engine respectivelly uses byte or 16-bit word access
requests for an 8- or 16-bit wide NAND device attached to the linked chip-select. The FIFOTHRESHOLD
and TRANSFERCOUNT fields must be programmed accordingly as a number of bytes or a number of 16-
bit word.
When the GPMC_PREFETCH_CONFIG1[7] ENABLEENGINE bit is set, the FIFO entry on the L3
interconnect port side is accessible at any address in the associated chip-select memory region. When the
ENABLEENGINE bit is set, any host access to this chip-select is rerouted to the FIFO input. Directly
accessing the NAND device linked to this chip-select from the host is still possible through these registers:
• GPMC_NAND_COMMAND_i
• GPMC_NAND_ADDRESS_i
• GPMC_NAND_DATA_i
The FIFO entry on the L3 interconnect port can be accessed with Byte, 16-bit word, or 32-bit word access
size, according to little-endian format, even though the FIFO input is 32-bit wide.
The FIFO control is made easier through the use of interrupts or DMA requests associated with the
FIFOTHRESHOLD bit field. The GPMC_PREFETCH_STATUS[30-24] FIFOPOINTER field monitors the
number of available bytes to be read in prefetch mode or the number of free empty slots which can be
written in write-posting mode. The GPMC_PREFETCH_STATUS[13-0] COUNTVALUE field monitors the
number of remaining bytes to be read or written by the engine according to the TRANSFERCOUNT value.
The FIFOPOINTER and COUNTVALUE bit fields are always expressed as a number of bytes even if a
16-bit wide NAND device is attached to the linked chip-select.
In prefetch mode, when the FIFOPOINTER equals 0, that is, the FIFO is empty, a host read access
receives the byte last read from the FIFO as its response. In case of 32-bit word or 16-bit word read
accesses, the last byte read from the FIFO is copied the required number of times to fit the requested
word size. In write-posting mode, when the FIFOPOINTER equals 0, that is, the FIFO is full, a host write
overwrites the last FIFO byte location. There is no underflow or overflow error reporting in the GPMC.

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7.1.2.3.12.4.2 Prefetch Mode

The prefetch mode is selected when the GPMC_PREFETCH_CONFIG1[0] ACCESSMODE bit is cleared.
The MPU NAND software driver must issue the block and page opening (READ) command with the
correct data address pointer initialization before the engine can be started to read from the NAND memory
device. The engine is started by asserting the GPMC_PREFETCH_CONTROL[0] STARTENGINE bit. The
STARTENGINE bit automatically clears when the prefetch process completes.
If required, the ECC calculator engine must be initialized (i.e., reset, configured, and enabled) before the
prefetch engine is started, so that the ECC is correctly computed on all data read by the prefetch engine.
When the GPMC_PREFETCH_CONFIG1[3] SYNCHROMODE bit is cleared, the prefetch engine starts
requesting data as soon as the STARTENGINE bit is set. If using this configuration, the host must monitor
the NAND device-ready pin so that it only sets the STARTENGINE bit when the NAND device is in a
ready state, meaning data is valid for prefetching.
When the SYNCHROMODE bit is set, the prefetch engine starts requesting data when an active to
inactive wait signal transition is detected. The transition detector must be cleared before any transition
detection; see Section 7.1.2.3.12.2.2. The GPMC_PREFETCH_CONFIG1[5-4] WAITPINSELECTOR field
selects which gpmc_wait pin edge detector triggers the prefetch engine in this synchronized mode.
If the STARTENGINE bit is set after the NAND address phase (page opening command), the engine is
effectively started only after the actual NAND address phase completion. To prevent GPMC stall during
this NAND address phase, set the STARTENGINE bit field before NAND address phase completion when
in synchronized mode. The prefetch engine will start when an active to inactive wait signal transition is
detected. The STARTENGINE bit is automatically cleared on prefetch process completion.
The prefetch engine issues a read request to fill the FIFO with the amount of data specified by
GPMC_PREFETCH_CONFIG2[13-0] TRANSFERCOUNT field.
Table 7-20 describes the prefetch mode configuration.
Table 7-20. Prefetch Mode Configuration

STARTENGINE GPMC_PREFETCH_CONTROL 0 Prefetch engine can be configured only if
STARTENGINE is cleared to 0.
ENGINECSSELECTOR GPMC_PREFETCH_CONFIG1 0 to 3h Selects the chip-select associated with a
NAND device where the prefetch engine is
active.
ACCESSMODE GPMC_PREFETCH_CONFIG1 0 Selects prefetch mode
FIFOTHRESHOLD GPMC_PREFETCH_CONFIG1 Selects the maximum number of bytes read
or written by the host on DMA or interrupt
request
TRANSFERCOUNT GPMC_PREFETCH_CONFIG1 Selects the number of bytes to be read or
written by the engine to the selected chip-
select
SYNCHROMODE GPMC_PREFETCH_CONFIG1 0/1 Selects when the engine starts the access to
the chip-select
WAITPINSELECT GPMC_PREFETCH_CONFIG1 0 to 1 Selects wait pin edge detector (if
GPMC_PREFETCH_CONFIG1[3]
SYNCHROMODE = 1)
ENABLEOPTIMIZEDACCESS GPMC_PREFETCH_CONFIG1 0/1 See Section 7.1.2.3.12.4.6
CYCLEOPTIMIZATION GPMC_PREFETCH_CONFIG1 Number of clock cycle removed to timing
parameters
ENABLEENGINE GPMC_PREFETCH_CONFIG1 1 Engine enabled
STARTENGINE GPMC_PREFETCH_CONFIG1 1 Starts the prefetch engine

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7.1.2.3.12.4.3 FIFO Control in Prefetch Mode

The FIFO can be drained directly by the MPU or by an eDMA channel.
In MPU draining mode, the FIFO status can be monitored through the GPMC_PREFETCH_STATUS[30-
24] FIFOPOINTER field or through the GPMC_PREFETCH_STATUS[16] FIFOTHRESHOLDSTATUS bit.
The FIFOPOINTER indicates the current number of available data to be read; FIFOTHRESHOLDSTATUS
set to 1 indicates that at least FIFOTHRESHOLD bytes are available from the FIFO.
An interrupt can be triggered by the GPMC if the GPMC_IRQENABLE[0] FIFOEVENTENABLE bit is set.
The FIFO interrupt event is logged, and the GPMC_IRQSTATUS[0] FIFOEVENTSTATUS bit is set. To
clear the interrupt, the MPU must read all the available bytes, or at least enough bytes to get below the
programmed FIFO threshold, and the FIFOEVENTSTATUS bit must be cleared to enable further interrupt
events. The FIFOEVENTSTATUS bit must always be reset prior to asserting the FIFOEVENTENABLE bit
to clear any out-of-date logged interrupt event. This interrupt generation must be enabled after enabling
the STARTENGINE bit.
Prefetch completion can be monitored through the GPMC_PREFETCH_STATUS[13-0] COUNTVALUE
field. COUNTVALUE indicates the number of currently remaining data to be requested according to the
TRANSFERCOUNT value. An interrupt can be triggered by the GPMC when the prefetch process is
complete (that is, COUNTVALUE equals 0) if the GPMC_IRQENABLE[1]
TERMINALCOUNTEVENTENABLE bit is set. At prefetch completion, the TERMINALCOUNT interrupt
event is also logged, and the GPMC_IRQSTATUS[1] TERMINALCOUNTSTATUS bit is set. To clear the
interrupt, the MPU must clear the TERMINALCOUNTSTATUS bit. The TERMINALCOUNTSTATUS bit
must always be cleared prior to asserting the TERMINALCOUNTEVENTENABLE bit to clear any out-of-
date logged interrupt event.
NOTE: The COUNTVALUE value is only valid when the prefetch engine is active (started), and an
interrupt is only triggered when COUNTVALUE reaches 0, that is, when the prefetch engine
automatically goes from an active to an inactive state.
The number of bytes to be prefetched (programmed in TRANSFERCOUNT) must be a multiple of the

programmed FIFOTHRESHOLD to trigger the correct number of interrupts allowing a deterministic and
transparent FIFO control. If this guideline is respected, the number of ISR accesses is always required
and the FIFO is always empty after the last interrupt is trigerred. In other cases, the TERMINALCOUNT
interrupt must be used to read the remaining bytes in the FIFO (the number of remaining bytes being
lower than the FIFOTHRESHOLD value).
In DMA draining mode, the GPMC_PREFETCH_CONFIG1[2] DMAMODE bit must be set so that the
GPMC issues a DMA hardware request when at least FIFOTHRESHOLD bytes are ready to be read from
the FIFO. The DMA channel owning this DMA request must be programmed so that the number of bytes
programmed in FIFOTHRESHOLD is read from the FIFO during the DMA request process. The DMA
request is kept active until this number of bytes has effectively been read from the FIFO, and no other
DMA request can be issued until the ongoing active request is complete.
In prefetch mode, the TERMINALCOUNT event is also a source of DMA requests if the number of bytes
to be prefetched is not a multiple of FIFOTHRESHOLD, the remaining bytes in the FIFO can be read by
the DMA channel using the last DMA request. This assumes that the number of remaining bytes to be
read is known and controlled through the DMA channel programming model.
Any potentially active DMA request is cleared when the prefetch engine goes from inactive to active
prefetch (the STARTENGINE bit is set to 1). The associated DMA channel must always be enabled by the
MPU after setting the STARTENGINE bit so that the out-of-date active DMA request does not trigger
spurious DMA transfers.

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7.1.2.3.12.4.4 Write-Posting Mode

The write-posting mode is selected when the GPMC_PREFETCH_CONFIG1[0] ACCESSMODE bit is set.
The MPU NAND software driver must issue the correct address pointer initialization command (page
program) before the engine can start writing data into the NAND memory device. The engine starts when
the GPMC_PREFETCH_CONTROL[0] STARTENGINE bit is set to 1. The STARTENGINE bit clears
automatically when posting completes. When all data have been written to the NAND memory device, the
MPU NAND software driver must issue the second cycle program command and monitor the status for
programming process completion (adding ECC handling, if required).
If used, the ECC calculator engine must be started (configured, reset, and enabled) before the posting
engine is started so that the ECC parities are properly calculated on all data written by the prefetch engine
to the associated chip-select.
In write-posting mode, the GPMC_PREFETCH_CONFIG1[3] SYNCHROMODE bit must be cleared so that
posting starts as soon as the STARTENGINE bit is set and the FIFO is not empty.
If the STARTENGINE bit is set after the NAND address phase (page program command), the
STARTENGINE setting is effective only after the actual NAND command completion. To prevent GPMC
stall during this NAND command phase, set the STARTENGINE bit field before the NAND address
completion and ensure that the associated DMA channel is enabled after the NAND address phase.
The posting engine issues a write request when valid data are available from the FIFO and until the
programmed GPMC_PREFETCH_CONFIG2[13-0] TRANSFERCOUNT accesses have been completed.
The STARTENGINE bit clears automatically when posting completes. When all data have been written to
the NAND memory device, the MPU NAND software driver must issue the second cycle program
command and monitor the status for programming process completion. The closing program command
phase must only be issued when the full NAND page has been written into the NAND flash write buffer,
including the spare area data and the ECC parities, if used.
Write-Posting Mode Configuration

STARTENGINE GPMC_PREFETCH_CONTROL 0 Write-posting engine can be configured only if
STARTENGINE is cleared to 0.
ENGINECSSELECTOR GPMC_PREFETCH_CONFIG1 0 to 3h Selects the chip-select associated with a
NAND device where the prefetch engine is
active
ACCESSMODE GPMC_PREFETCH_CONFIG1 1 Selects write-posting mode
FIFOTHRESHOLD GPMC_PREFETCH_CONFIG1 Selects the maximum number of bytes read or
written by the host on DMA or interrupt request
TRANSFERCOUNT GPMC_PREFETCH_CONFIG2 Selects the number of bytes to be read or
written by the engine from/to the selected chip-
select
SYNCHROMODE GPMC_PREFETCH_CONFIG1 0 Engine starts the access to chip-select as soon
as STARTENGINE is set.
ENABLEOPTIMIZEDACCESS GPMC_PREFETCH_CONFIG1 0/1 See Section 7.1.2.3.12.4.6
CYCLEOPTIMIZATION GPMC_PREFETCH_CONFIG
ENABLEENGINE GPMC_PREFETCH_CONFIG1 1 Engine enabled
STARTENGINE GPMC_PREFETCH_CONTROL 1 Starts the prefetch engine

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7.1.2.3.12.4.5 FIFO Control in Write-Posting Mode

The FIFO can be filled directly by the MPU or by an sDMA channel.
In MPU filling mode, the FIFO status can be monitored through the FIFOPOINTER or through the
GPMC_PREFETCH_STATUS[16] FIFOTHRESHOLDSTATUS bit. FIFOPOINTER indicates the current
number of available free byte places in the FIFO, and the FIFOTHRESHOLDSTATUS bit, when set,
indicates that at least FIFOTHRESHOLD free byte places are available in the FIFO.
An interrupt can be issued by the GPMC if the GPMC_IRQENABLE[0] FIFOEVENTENABLE bit is set.
When the interrupt is fired, the GPMC_IRQSTATUS[0] FIFOEVENTSTATUS bit is set. To clear the
interrupt, the MPU must write enough bytes to fill the FIFO, or enough bytes to get below the programmed
threshold, and the FIFOEVENTSTATUS bit must be cleared to get further interrupt events. The
FIFOEVENTSTATUS bit must always be cleared prior to asserting the FIFOEVENTENABLE bit to clear
any out-of-date logged interrupt event. This interrupt must be enabled after enabling the STARTENGINE
bit
The posting completion can be monitored through the GPMC_PREFETCH_STATUS[13-0] COUNTVALUE
field. COUNTVALUE indicates the current number of remaining data to be written based on the
TRANSFERCOUNT value. An interrupt is issued by the GPMC when the write-posting process completes
(that is, COUNTVALUE equal to 0) if the GPMC_IRQENABLE[1] TERMINALCOUNTEVENTENABLE bit is
set. When the interrupt is fired, the GPMC_IRQSTATUS[1] TERMINALCOUNTSTATUS bit is set. To clear
the interrupt, the MPU must clear the TERMINALCOUNTSTATUS bit. The TERMINALCOUNTSTATUS bit
must always be cleared prior to asserting the TERMINALCOUNTEVENTENABLE bit to clear any out-of-
date logged interrupt event.
NOTE: The COUNTVALUE value is only valid if the write-posting engine is active and started, and
an interrupt is only issued when COUNTVALUE reaches 0, that is, when the posting engine
automatically goes from active to inactive.
In DMA filling mode, the DMAMode bit field in the GPMC_PREFETCH_CONFIG1[2] DMAMODE bit must
be set so that the GPMC issues a DMA hardware request when at least FIFOTHRESHOLD bytes-free
places are available in the FIFO. The DMA channel owning this DMA request must be programmed so
that a number of bytes equal to the value programmed in the FIFOTHRESHOLD bit field are written into
the FIFO during the DMA access. The DMA request remains active until the associated number of bytes
has effectively been written into the FIFO, and no other DMA request can be issued until the ongoing
active request has been completed.
Any potentially active DMA request is cleared when the prefetch engine goes from inactive to active
prefetch (STARTENGINE set to 1). The associated DMA channel must always be enabled by the MPU
after setting the STARTENGINE bit so that an out-of-date active DMA request does not trigger spurious
DMA transfers.
In write-posting mode, the DMA or the MPU fill the FIFO with no consideration to the associated byte
enables. Any byte stored in the FIFO is written into the memory device.

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7.1.2.3.12.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
Access time to a NAND memory device can be optimized for back-to-back accesses if the associated CSn
signal is not deasserted between accesses. The GPMC access engine can track prefetch engine
accesses to optimize the access timing parameter programmed for the allocated chip-select, if no
accesses to other chip-selects (that is, interleaved accesses) occur. Similarly, the access engine also
eliminates the CYCLE2CYCLEDELAY even if CYCLE2CYCLESAMECSEN is set. This capability is limited
to the prefetch and write-posting engine accesses, and MPU accesses to a NAND memory device
(through the defined chip-select memory region or through the GPMC_NAND_DATA_i are never
optimized.
The GPMC_PREFETCH_CONFIG1[27] ENABLEOPTIMIZEDACCESS bit must be set to enable optimized
accesses. To optimize access time, the GPMC_PREFETCH_CONFIG1[30-28] CYCLEOPTIMIZATION
field defines the number of GPMC_FCLK cycles to be suppressed from the RDCYCLETIME,
WRCYCLETIME, RDACCESSTIME, WRACCESSTIME, CSOFFTIME, ADVOFFTIME, OEOFFTIME, and
WEOFFTIME timing parameters.
NAND Read Cycle Optimization Timing Description, in the case of back-to-back accesses to the NAND
flash through the prefetch engine, CYCLE2CYCLESAMECSEN is forced to 0 when using optimized
accesses. The first access uses the regular timing settings for this chip-select. All accesses after this one
use settings reduced by x clock cycles, x being defined by the GPMC_PREFETCH_CONFIG1[30-28]
CYCLEOPTIMIZATION field.
NAND Read Cycle Optimization Timing Description
RDACCESSTIME RDACCESSTIME - x clk cycles
GPMC_FCLK
First read access
RDCYCLETIME
CSRDOFFTIME
CSONTIME = 0 Second read access
RDCYCLETIME − x clk cycles

CSRDOFFTIME − x clk cycles
CSONTIME = 0
nCS
nBE0/CLE
OEONTIME = 0 OEONTIME = 0
OEOFFTIME OEOFFTIME − x clk cycles

nOE/nRE
nADV/ALE
D[15:0] Data 0 Data 1

WAIT
x is the programmed value in the
GPMC_PREFETCH_CONFIG1[30:28]
CYCLEOPTIMIZATION field

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7.1.2.3.12.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
Any on-going read or write access from the prefetch and write-posting engine is completed before an
access to any other chip-select can be initiated. As a default, the arbiter uses a fixed-priority algorithm,
and the prefetch and write-posting engine has the lowest priority. The maximum latency added to access
starting time in this case equals the RDCYCLETIME or WRCYCLETIME (optimized or not) plus the
requested BUSTURNAROUND delay for bus turnaround completion programmed for the chip-select to
which the NAND device is connected to.
Alternatively, a round-robin arbitration can be used to prioritize accesses to the external bus. This
arbitration scheme is enabled by setting the GPMC_PREFETCH_CONFIG1[23] PFPWENROUNDROBIN
bit. When a request to another chip-select is received while the prefetch and write-posting engine is active,
priority is given to the new request. The request processed thereafter is the prefetch and write-posting
engine request, even if another interconnect request is passed in the mean time. The engine keeps
control of the bus for an additional number of requests programmed in the
GPMC_PREFETCH_CONFIG1[19-16] PFPWWEIGHTEDPRIO bit field. Control is then passed to the
direct interconnect request.
As an example, the round-robin arbitration scheme is selected with PFPWWEIGHTEDPRIO set to 2h.
Considering the prefetch and write-posting engine and the interconnect interface are always requesting
access to the external interface, the GPMC grants priority to the direct interconnect access for one
request. The GPMC then grants priority to the engine for three requests, and finnaly back to the direct
interconnect access, until the arbiter is reset when one of the two initiators stops initiating requests.

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7.1.3 GPMC High-Level Programming Model Overview

The high-level programming model introduces a top-down approach for users that need to configure the
GPMC module. Figure 7-41 shows a programming model top-level diagram for the GPMC. Each block of
the diagram is described in one of the following subsections through a set of registers to configure.
Table 7-21 and Table 7-22 list each step in the model.

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Figure 7-41. Programming Model Top-Level Diagram
Start
1. Enable GPMC clocks
initialization
GPMC
2. Enable GPMC pads
3. Reset GPMC
NOR What NAND

protocol?
7. NAND memory type

4. NOR memory type
8. NAND chip-select
configuration
5. NOR chip-select
configuration
9. Write operations
(asynchronous)
6. NOR timings
configuration
configuration
GPMC
9. Read operations
(asynchronous)
10. ECC engine *
11. Prefetch and

write posting
engine *
12. Wait pin

configuration *
13. Enable
chip-select
* Optional
End

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Table 7-21. GPMC Configuration in NOR Mode

Step Description
NOR Memory Type See Table 7-24
NOR Chip-Select Configuration See Table 7-25
NOR Timings Configuration See Table 7-26
Wait Pin Configuration See Table 7-27
Enable Chip-Select See Table 7-28
Table 7-22. GPMC Configuration in NAND Mode

Step Description
NAND Memory Type See Table 7-29
NAND Chip-Select Configuration See Table 7-30
Write Operations (Asynchronous) See Table 7-31
Read Operations (Asynchronous) See Table 7-31
ECC Engine See Table 7-32
Prefetch and Write-Posting Engine See Table 7-33
Wait Pin Configuration See Table 7-34
Enable Chip-Select See Table 7-35
7.1.3.1 GPMC Initialization

Table 7-23 describes the settings required to reset the GPMC.
Table 7-23. Reset GPMC

Sub-process Name Register / Bitfield Value
Start a software reset GPMC_SYSCONFIG[1] SOFTRESET 1
Wait until GPMC_SYSSTATUS[0] RESETDONE 1

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7.1.3.2 GPMC Configuration in NOR Mode

This section gives a generic configuration for parameters related to the NOR memory connected to the
GPMC. Table 7-24 through Table 7-28 list the steps to configure the GPMC in NOR mode.
NOTE: In the tables of this section, 'x' in Value column stands for 'depends on configuration'.
Table 7-24. NOR Memory Type

Set the NOR protocol GPMC_CONFIG1_i[11-10] DEVICETYPE 0
Set a device size GPMC_CONFIG1_i[13-12] DEVICESIZE x
Select an address and data multiplexing protocol GPMC_CONFIG1_i[9] MUXADDDATA x
GPMC_CONFIG1_i[24-23]
Set the attached device page length x
ATTACHEDDEVICEPAGELENGTH
Set the wrapping burst capabilities GPMC_CONFIG1_i[31] WRAPBURST x
Select a timing signals latencies factor GPMC_CONFIG1_i[4] TIMEPARAGRANULARITY x
Select an output clock frequency GPMC_CONFIG1_i[1-0] GPMCFCLKDIVIDER x
Choose an output clock activation time GPMC_CONFIG1_i[26-25] CLKACTIVATIONTIME x
Set a single or multiple access for read operations GPMC_CONFIG1_i[30] READMULTIPLE x
Set a synchronous or asynchronous mode for read
GPMC_CONFIG1_i[29] READTYPE x
operations
Set a single or multiple access for write operations GPMC_CONFIG1_i[28] WRITEMULTIPLE x
Set a synchronous or asynchronous mode for write
GPMC_CONFIG1_i[27] WRITETYPE x
operations
Table 7-25. NOR Chip-Select Configuration

Select the chip-select base address GPMC_CONFIG7_i[5-0] BASEADDRESS x
Select the chip-select mask address GPMC_CONFIG7_i[11-8] MASKADDRESS x
Table 7-26. NOR Timings Configuration

Configure adequate timing parameters in various memory
See Section 7.1.3.5
modes
Table 7-27. WAIT Pin Configuration

Enable or disable wait pin monitoring for read operations GPMC_CONFIG1_i[22] WAITREADMONITORING x
Enable or disable wait pin monitoring for write operations GPMC_CONFIG1_i[21] WAITWRITEMONITORING x
GPMC_CONFIG1_i[19-18]
Select a wait pin monitoring time x
WAITMONITORINGTIME
Choose the input wait pin for the chip-select GPMC_CONFIG1_i[17-16] WAITPINSELECT x

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Table 7-28. Enable Chip-Select

When all parameters are configured, enable the chip-select GPMC_CONFIG7_i[6] CSVALID x
7.1.3.3 GPMC Configuration in NAND Mode

This section gives a generic configuration for parameters related to NAND memory connected to the
GPMC.
Table 7-29. NAND Memory Type

Set the NAND protocol GPMC_CONFIG1_i[11-10] DEVICETYPE 2h
Set a device size GPMC_CONFIG1_i[13-12] DEVICESIZE x
Set the address and data multiplexing protocol to non-
GPMC_CONFIG1_i[9] MUXADDDATA 0
multiplexed attached device
Select a timing signals latencies factor GPMC_CONFIG1_i[4] TIMEPARAGRANULARITY x
Set a synchronous or asynchronous mode and a single or
See Section 7.1.3.4 x
multiple access for read and write operations
Table 7-30. NAND Chip-Select Configuration

Select the chip-select base address GPMC_CONFIG7_i[5-0] BASEADDRESS x
Select the chip-select minimum granularity (16M bytes) GPMC_CONFIG7_i[11-8] MASKADDRESS x
Table 7-31. Asynchronous Read and Write Operations

Configure adequate timing parameters in asynchronous
See Section 7.1.3.5
modes
Table 7-32. ECC Engine

Select the ECC result register where the first ECC
GPMC_ECC_CONTROL[3-0] ECCPOINTER x
computation is stored (Only applies to Hamming)
Write 1 to
Clear all ECC result registers GPMC_ECC_CONTROL[8] ECCCLEAR
clear
GPMC_ECC_SIZE_CONFIG[19-12] ECCSIZE0 and
Define ECCSIZE0 and ECCSIZE1 x
GPMC_ECC_SIZE_CONFIG[29-22] ECCSIZE1
Select the size of each of the 9 result registers (size GPMC_ECC_SIZE_CONFIG[j-1] ECCjRESULTSIZE
x
specified by ECCSIZE0 or ECCSIZE1) where j = 1 to 9
Select the chip-select where ECC is computed GPMC_ECC_SIZE_CONFIG[3-1] ECCCS x
Select the Hamming code or BCH code ECC algorithm in
GPMC_ECC_SIZE_CONFIG[16] ECCALGORITHM x
use
Select word size for ECC calculation GPMC_ECC_SIZE_CONFIG[7] ECC16B x
If the BCH code is used, GPMC_ECC_SIZE_CONFIG[13-12] ECCBCHTSEL
Set an error correction capability and and GPMC_ECC_SIZE_CONFIG[6-4] x
Select a number of sectors to process ECCTOPSECTOR
Enable the ECC computation GPMC_ECC_SIZE_CONFIG[0] ECCENABLE 1

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Table 7-33. Prefetch and Write-Posting Engine

Disable the engine before configuration GPMC_PREFETCH_CONTROL[0] STARTENGINE 0
Select the chip-select associated with a NAND device where the GPMC_PREFETCH_CONFIG1[26-24]
x
prefetch engine is active ENGINECSSELECTOR
Select access direction through prefetch engine, read or write. GPMC_PREFETCH_CONFIG1[0] ACCESSMODE x
GPMC_PREFETCH_CONFIG1[14-8]
Select the threshold used to issue a DMA request x
FIFOTHRESHOLD
Select either DMA synchronized mode or SW manual mode. GPMC_PREFETCH_CONFIG1[2] DMAMODE x
Select if the engine immediately starts accessing the memory
upon STARTENGINE assertion or if hardware synchronization GPMC_PREFETCH_CONFIG1[3] SYNCHROMODE x
based on a WAIT signal is used.
Select which wait pin edge detector should start the engine in GPMC_PREFETCH_CONFIG1[5-4]
x
synchronized mode WAITPINSELECTOR
Enter a number of clock cycles removed to timing parameters
GPMC_PREFETCH_CONFIG1[30-28]
(For all back-to-back accesses to the NAND flash but not the x
CYCLEOPTIMIZATION
first one)
Enable the prefetch postwite engine GPMC_PREFETCH_CONFIG1[7] ENABLEENGINE 1
Select the number of bytes to be read or written by the engine to GPMC_PREFETCH_CONFIG2[13-0]
x
the selected chip-select TRANSFERCOUNT
Start the prefetch engine GPMC_PREFETCH_CONTROL[0] STARTENGINE 1
Table 7-34. WAIT Pin Configuration

Selects when the engine starts the access to CS GPMC_PREFETCH_CONFIG1[3] SYNCHROMODE x
Select which wait pin edge detector should start the engine GPMC_PREFETCH_CONFIG1[5-4]
x
in synchronized mode WAITPINSELECTOR
Table 7-35. Enable Chip-Select

When all parameters are configured, enable the chip-select GPMC_CONFIG7_i[6] CSVALID x

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7.1.3.4 Set Memory Access

This section details the bit field to configure to set the GPMC in various memory modes.
Table 7-36. Mode Parameters Check List Table

Asynchronous Synchronous
Multiple Multiple Multiple Multiple
Register Bit Bit Field Name Single Single Single Single
Read Write Read Write
Read Write Read Write
(Page) (Page) (Burst) (Burst)
Access Access Access Access
Access Access Access Access
GPMC_CONFIG1_i 30 READMULTIPLE 0 - 1 N/S 0 - 1 -
GPMC_CONFIG1_i 29 READTYPE 0 - 0 N/S 1 - 1 -
GPMC_CONFIG1_i 28 WRITEMULTIPLE - 0 N/S - 0 - 1
GPMC_CONFIG1_i 27 WRITETYPE - 0 N/S - 1 - 1
Table 7-37. Access Type Parameters Check List Table

Access Type
Register Bit Bit Field Name
Non-Mux Address/Data Mux AAD Mux
GPMC_CONFIG1_i 9-8 MUXADDDATA 0 2h 1

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7.1.3.5 GPMC Timing Parameters

Figure 7-42 shows a programming model diagram for the NOR interfacing timing parameters.
Table 7-38 lists bit fields to configure adequate timing parameter in various memory modes.
Figure 7-42. NOR Interfacing Timing Parameters Diagram
Start
write Type write
of access?
No Write Access
Operational mode: NOR interfacing
write write
operation operation
Asynchronous
Synchronous read
read Type
of access?
No read access
Synchronous Asynchronous
read read
operation operation
End

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Table 7-38. Timing Parameters

Asynchronous Synchronous Access Type
Multiple Multiple Multiple
Register Bit Bit Field Name Single Single Single Single Address
Read Read Write Non- AAD-
Read Write Read Write /Data-
(Page) (Burst) (Burst) multiplexed multiplexed
Access Access Access Access multiplexed
access Access Access
GPMC_CONFIG1_i 9-8 MUXADDDATA y y y y y y y y y y
GPMC_CONFIG1_i 29 READTYPE y y y y y y y
GPMC_CONFIG1_i 30 READMULTIPLE y y y y y y y
GPMC_CONFIG1_i 27 WRITETYPE y y y y y y
GPMC_CONFIG1_i 28 WRITEMULTIPLE y y y y y y
GPMC_CONFIG1_i 31 WRAPBURST y y y y y
GPMC_CONFIG1_i 26-25 CLKACTIVATIONTIME y y y y y y y
GPMC_CONFIG1_i 19-18 WAITMONITORINGTIME y y y y y y y y y y
GPMC_CONFIG1_i 4 TIMEPARAGRANULARITY y y y y y y y y y y
GPMC_CONFIG2_i 20-16 CSWROFFTIME y y y y y y
GPMC_CONFIG2_i 12-8 CSRDOFFTIME y y y y y y y
GPMC_CONFIG2_i 7 CSEXTRADELAY y y y y y y y y y y
GPMC_CONFIG2_i 3-0 CSONTIME y y y y y y y y y y
GPMC_CONFIG3_i 30-28 ADVAADMUXWROFFTIME y y y y
GPMC_CONFIG3_i 26-24 ADVAADMUXRDOFFTIME y y y y y
GPMC_CONFIG3_i 6-4 ADVAADMUXONTIME y y y y y y y y
GPMC_CONFIG3_i 20-16 ADVWROFFTIME y y y y y y
GPMC_CONFIG3_i 12-8 ADVRDOFFTIME y y y y y y y
GPMC_CONFIG3_i 7 ADVEXTRADELAY y y y y y y y y y y
GPMC_CONFIG3_i 3-0 ADVONTIME y y y y y y y y y y
GPMC_CONFIG4_i 15-13 OEAADMUXOFFTIME y y y y y y y y
GPMC_CONFIG4_i 6-4 OEAADMUXONTIME y y y y y y y y
GPMC_CONFIG4_i 28-24 WEOFFTIME y y y y y y
GPMC_CONFIG4_i 23 WEEXTRADELAY y y y y y y
GPMC_CONFIG4_i 19-16 WEONTIME y y y y y y
GPMC_CONFIG4_i 12-8 OEOFFTIME y y y y y y y
GPMC_CONFIG4_i 7 OEEXTRADELAY y y y y y y y
GPMC_CONFIG4_i 3-0 OEONTIME y y y y y y y
GPMC_CONFIG5_i 27-24 PAGEBURSTACCESSTIME y y y y y y
GPMC_CONFIG5_i 20-16 RDACCESSTIME y y y y y y y
GPMC_CONFIG5_i 12-8 WRCYCLETIME y y y y y y
GPMC_CONFIG5_i 4-0 RDCYCLETIME y y y y y y y
GPMC_CONFIG6_i 28-24 WRACCESSTIME y y y y y y
GPMC_CONFIG6_i 19-16 WRDATAONADMUXBUS y y y y y

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Table 7-38. Timing Parameters (continued)

Asynchronous Synchronous Access Type
Multiple Multiple Multiple
Register Bit Bit Field Name Single Single Single Single Address
Read Read Write Non- AAD-
Read Write Read Write /Data-
(Page) (Burst) (Burst) multiplexed multiplexed
Access Access Access Access multiplexed
access Access Access
GPMC_CONFIG6_i 11-8 CYCLE2CYCLEDELAY y y y y y y y y y y
GPMC_CONFIG6_i 7 CYCLE2CYCLESAMECSEN y y y y y y y y y y
GPMC_CONFIG6_i 6 CYCLE2CYCLEDIFFCSEN y y y y y y y y y y
GPMC_CONFIG6_i 3-0 BUSTURNAROUND y y y y y y y y y y
GPMC_CONFIG7_i 6 CSVALID y y y y y y y y y y

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7.1.4 Use Cases
7.1.4.1 How to Set GPMC Timing Parameters for Typical Accesses
7.1.4.1.1 External Memory Attached to the GPMC Module

As discussed in the introduction to this chapter, the GPMC module supports the following external
memory types:
• Asynchronous or synchronous, 8-bit or 16-bit-width memory or device
• 16-bit address/data-multiplexed or not multiplexed NOR flash device
• 8- or 16-bit NAND flash device
The following examples show how to calculate GPMC timing parameters by showing a typical parameter
setup for the access to be performed.
The example is based on a 512-Mb multiplexed NOR flash memory with the following characteristics:
• Type: NOR flash (address/data-multiplexed mode)
• Size: 512M bits
• Data Bus: 16 bits wide
• Speed: 104 MHz clock frequency
• Read access time: 80 ns
7.1.4.1.2 Typical GPMC Setup

Table 7-39 lists some of the I/Os of the GPMC module.
Table 7-39. GPMC Signals

Signal Name I/O Description
GPMC_FCLK Internal Functional and interface clock. Acts as the time reference.
GPMC_CLK O External clock provided to the external device for synchronous operations
GPMC_A[27:17] O Address
GPMC_AD[15: 0] I/O Data-multiplexed with addresses A[16:1] on memory side
GPMC_CSxn O Chip-select (where x = 0, or 1)
GPMC_ADVn_ALE O Address valid enable
GPMC_OE_REn O Output enable (read access only)
GPMC_WEn O Write enable (write access only)
GPMC_WAIT[1:0] I Ready signal from memory device. Indicates when valid burst data is ready to be read

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Figure 7-43 shows the typical connection between the GPMC module and an attached NOR Flash
memory.
Figure 7-43. GPMC Connection to an External NOR Flash Memory
Device
GPMC module Nor Flash
gpmc_a[26:16] 11
A [27:17] A[26:16]
gpmc_d[15:0] 16
A [16:1] / D [15:0] A/D[15:0]
gpmc_ncs[7:0]
nCS [7:0] nCE
gpmc_nadv_ale
ADV /ALE nAVD
gpmc_noe_nre
OE / RE nOE
gpmc_nwe
WE nWE
gpmc_nwp
WP nWP
gpmc_wait [1:0]
WAIT [1:0] RDY
gpmc_clk
DEVICECLK CLK
The following sections demonstrate how to calculate GPMC parameters for three access types:
• Synchronous burst read
• Asynchronous read
• Asynchronous single write

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7.1.4.1.3 GPMC Configuration for Synchronous Burst Read Access

The clock runs at 104 MHz ( f = 104 MHz; T = 9, 615 ns).
Table 7-40 shows the timing parameters (on the memory side) that determine the parameters on the
GPMC side.
Table 7-41 shows how to calculate timings for the GPMC using the memory parameters.
Figure 7-44 shows the synchronous burst read access.
Table 7-40. Useful Timing Parameters on the Memory Side

AC Read Characteristics
Description Duration (ns)
on the Memory Side
tCES CSn setup time to clock 0
tACS Address setup time to clock 3
tIACC Synchronous access time 80
tBACC Burst access time valid clock to output delay 5,2
tCEZ Chip-select to High-Impedance 7
tOEZ Output enable to High-Impedance 7
tAVC ADVn setup time 6
tAVD AVDn pulse 6
tACH Address hold time from clock 3
The following terms, which describe the timing interface between the controller and its attached device,
are used to calculate the timing parameters on the GPMC side:
• Read Access time (GPMC side): Time required to activate the clock + read access time requested on
the memory side + data setup time required for optimal capture of a burst of data
• Data setup time (GPMC side): Ensures a good capture of a burst of data (as opposed to taking a burst
of data out). One word of data is processed in one clock cycle (T = 9,615 ns). The read access time
between 2 bursts of data is tBACC = 5,2 ns. Therefore, data setup time is a clock period - tBACC =
4,415 ns of data setup.
• Access completion (GPMC side): (Different from page burst access time) Time required between the
last burst access and access completion: CSn/OEn hold time (CSn and OEn must be released at the
end of an access. These signals are held to allow the access to complete).
• Read cycle time (GPMC side): Read Access time + access completion
• Write cycle time for burst access: Not supported for NOR flash memory

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Table 7-41. Calculating GPMC Timing Parameters

Number of
Parameter Name on Clock Cycles
GPMC Side Formula Duration (ns) (F = 104 MHz) GPMC Register Configurations
GPMC FCLK Divider - - - GPMCFCLKDIVIDER = 0
ClkActivationTime min ( tCES, tACS) 3 1 CLKACTIVATIONTIME = 1
roundmax (ClkActivationTime + 94,03: (9,615 + 10 : roundmax
RdAccessTime ACCESSTIME = Ah
tIACC + DataSetupTime) 80 + 4,415) (94,03 / 9,615)
PageBurstAccessTime roundmax (tBACC) roundmax (5,2) 1 PAGEBURSTACCESSTIME = 1
101, 03: (94, 03 +
RdCycleTime AccessTime + max ( tCEZ, tOEZ) 11 RDCYCLETIME = Bh
7)
CsOnTime tCES 0 0 CSONTIME = 0
CsReadOffTime RdCycleTime - 11 CSRDOFFTIME = Bh
AdvOnTime tAVC 0 0 ADVONTIME = 0
AdvRdOffTime tAVD + tAVC 12 2 ADVRDOFFTIME = 2h
(ClkActivationTime + tACH) <
OeOnTime OeOnTime < (ClkActivationTime + - 3, for instance OEONTIME = 3h
tIACC)
OeOffTime RdCycleTime - 11 OEOFFTIME = Bh
Figure 7-44. Synchronous Burst Read Access (Timing Parameters in Clock Cycles)
2nd burst access RdCycleTime = 11
AccessTime = 10 3rd last burst access
FCLK
ClkActivationTime = 1 Access Completion
Data Setup
CLK
tIACC (access time on memory side)
AdvRdOffTime = 2
nADV
CsReadOffTime = RdCycleTime
nCS
OeOffTime = RdCycleTime
OeOnTime = 3
nOE
A/D bus Valid Address D0 D1 D2 D3

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7.1.4.1.4 GPMC Configuration for Asynchronous Read Access

The clock runs at 104 MHz ( f = 104 MHz; T = 9, 615 ns).
GPMC side.
Figure 7-45 shows the asynchronous read access.
Table 7-42. AC Characteristics for Asynchronous Read Access

AC Read Characteristics
on the Memory Side
tCE Read Access time from CSn low 80
tAAVDS Address setup time to rising edge of ADVn 3
tAVDP ADVn low time 6
tCAS CSn setup time to ADVn 0
tOE Output enable to output valid 6
tOEZ Output enable to High-Impedance 7
Use the following formula to calculate the RdCycleTime parameter for this typical access:
RdCycleTime = RdAccessTime + AccessCompletion = RdAccessTime + 1 clock cycle + tOEZ
• First, on the memory side, the external memory makes the data available to the output bus. This is the
memory-side read access time defined in Table 7-43: the number of clock cycles between the address
capture (ADVn rising edge) and the data valid on the output bus.
The GPMC requires some hold time to allow the data to be captured correctly and the access to be
finished.
• To read the data correctly, the GPMC must be configure to meet the data setup time requirement of
the memory; the GPMC module captures the data on the next rising edge. This is access time on the
GPMC side.
• There must also be a data hold time for correctly reading the data (checking that there is no OEn/CSn
deassertion while reading the data). This data hold time is 1 clock cycle (that is, AccessTime + 1).
• To complete the access, OEn/CSn signals are driven to high-impedance. AccessTime + 1 + tOEZ is
the read cycle time.
• Addresses can now be relatched and a new read cycle begun.

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Table 7-43. GPMC Timing Parameters for Asynchronous Read Access

Number of Clock
Duration
Parameter Name on Cycles
(ns)
GPMC side Formula (F = 104 MHz) GPMC Register Configurations
ClkActivationTime n/a (asynchronous mode)
AccessTime round max (tCE) 80 9 ACCESSTIME = 9h
PageBurstAccessTime n/a (single access)
RdCycleTime AccessTime + 1cycle + tOEZ 96, 615 11 RDCYCLETIME = Bh
CsOnTime tCAS 0 0 CSONTIME = 0
CsReadOffTime AccessTime + 1 cycle 89, 615 10 CSRDOFFTIME = Ah
AdvOnTime tAAVDS 3 1 ADVONTIME = 1
AdvRdOffTime tAAVDS + tAVDP 9 1 ADVRDOFFTIME = 1
OeOnTime ≥ AdvRdOffTime
OeOnTime - 3, for instance OEONTIME = 3h
(multiplexed mode)
OeOffTime AccessTime + 1cycle 89, 615 10 OEOFFTIME = Ah
Figure 7-45. Asynchronous Single Read Access (Timing Parameters in Clock Cycles)
Data capture on GPMC side: RdAccessTime = 9 RdCycleTime = 11
FCLK
Data Setup time
CsReadOffTime = 10
nCS
AdvRdOffTime = 1
nADV
tOEZ
OeOffTime = 10
OeOnTime = 3
nOE
Memory-side access time Data Hold time
A/D bus Valid Address DATA Valid Address

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7.1.4.1.5 GPMC Configuration for Asynchronous Single Write Access

The clock runs at 104 MHz: (f = 104 MHz; T = 9, 615 ns).
GPMC side.
Figure 7-46 shows the synchronous burst write access.
Table 7-44. AC Characteristics for Asynchronous Single Write (Memory Side)

AC Characteristics on the
Memory Side
tWC Write cycle time 60
tAVDP ADVn low time 6
tWP Write pulse width 25
tWPH Write pulse width high 20
tCS CSn setup time to WEn 3
tCAS CSn setup time to ADVn 0
tAVSC ADVn setup time 3
For asynchronous single write access, write cycle time is WrCycleTime = WeOffTime + AccessCompletion
= WeOffTime + 1. For the AccesCompletion, the GPMC requires 1 cycle of data hold time (CSn de-
assertion).

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Table 7-45. GPMC Timing Parameters for Asynchronous Single Write

Number of Clock
Duration
Parameter Name on Cycles
(ns)
GPMC side Formula (F = 104 MHz) GPMC Register Configurations
ClkActivationTime n/a (asynchronous mode)
Applicable only to
AccessTime WAITMONITORING (the value is
the same as for read access)
PageBurstAccessTime n/a (single access)
WrCycleTime WeOffTime + AccessCompletion 57, 615 6 WRCYCLETIME = 6h
CsOnTime tCAS 0 0 CSONTIME = 0
CsWrOffTime WeOffTime + 1 57, 615 6 CSWROFFTIME = 6h
AdvOnTime tAVSC 3 1 ADVONTIME = 1
AdvWrOffTime tAVSC + tAVDP 9 1 ADVWROFFTIME = 1
WeOnTime tCS 3 1 WEONTIME = 1
WeOffTime tCS + tWP + tWPH 48 5 WEOFFTIME = 5h
Figure 7-46. Asynchronous Single Write Access (Timing Parameters in Clock Cycles)
WrCycleTime = 6
FCLK
CsWriteOffTime = 6
nCS
AdvWrOffTime = 1
nADV
Access Completion / Data Hold time
WeOffTime = 5
WeOnTime = 2 (at least 1)

nWE
At least > 20 ns (tWPH)

At least > 25 ns (tWP)
A/D bus ADDRESS DATA ADDRESS DATA

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7.1.4.2 How to Choose a Suitable Memory to Use With the GPMC

This section is intended to help the user select a suitable memory device to interface with the GPMC
controller.
7.1.4.2.1 Supported Memories or Devices

NAND flash and NOR flash architectures are the two flash technologies. The GPMC supports various
types of external memory or device, basically any one that supports NAND or NOR protocols:
• 8- and 16-bit width asynchronous or synchronous memory or device (8-bit: non burst device only)
• 16-bit address and data multiplexed NOR flash devices (pSRAM)
• 8- and 16-bit NAND flash device
7.1.4.2.2 NAND Interface Protocol

NAND flash architecture, introduced in 1989, is a flash technology. NAND is a page-oriented memory
device, that is, read and write accesses are done by pages. NAND achieves great density by sharing
common areas of the storage transistor, which creates strings of serially connected transistors (in NOR
devices, each transistor stands alone). Thanks to its high density NAND is best suited to devices requiring
high capacity data storage, such as pictures, music, or data files. NAND non-volatility, makes of it a good
storage solution for many applications where mobility, low power, and speed are key factors. Low pin
count and simple interface are other advantages of NAND.
Table 7-46 summarizes the NAND interface signals level applied to external device or memories.
Table 7-46. NAND Interface Bus Operations Summary

Bus Operation CLE ALE CEn WEn REn WPn
Read (cmd input) H L L RE H x
Read (add input) L H L RE H x
Write (cmd input) H L L RE H H
Write (add input) L H L RE H H
Data input L L L RE H H
Data output L L L H FE x
Busy (during read) x x H H H x
Busy (during program) x x x x x H
Busy (during erase) x x x x x H
Write protect x x x x x L
Stand-by x x H x x H/L
7.1.4.2.3 NOR Interface Protocol

NOR flash architecture, introduced in 1988, is a flash technology. Unlike NAND, which is a sequential
access device, NOR is directly addressable; i.e., it is designed to be a random access device. NOR is
best suited to devices used to store and run code or firmware, usually in small capacities. While NOR has
fast read capabilities it has slow write and erase functions compared to NAND architecture.
Table 7-47 summarizes the NOR interface signals level applied to external device or memories.
Table 7-47. NOR Interface Bus Operations Summary

Bus Operation CLK ADVn CSn OEn WEn WAIT DQ[15:0]
Read (asynchronous) x L L L H Asserted Output
Read (synchronous) Running L L L H Driven Output
Read (burst suspend) Halted x L H H Active Output
Write x L L H L Asserted Input

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Table 7-47. NOR Interface Bus Operations Summary (continued)

Bus Operation CLK ADVn CSn OEn WEn WAIT DQ[15:0]
Output disable x x L H H Asserted High-Z
Standby x x H x x High-Z High-Z

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7.1.4.2.4 Other Technologies

Other supported device type interact with the GPMC through the NOR interface protocol.
OneNAND Flash is a high-density and low-power memory device. It is based on single- or multi-level-cell
NAND core with SRAM and logic, and interfaces as a synchronous NOR Flash, plus has synchronous
write capability. It reads faster than conventional NAND and writes faster than conventionnal NOR flash.
Hence, it is appropriate for both mass storage and code storage.
pSRAM stands for pseudo-static random access memory. pSRAM is a low-power memory device for
mobile applications. pSRAM is based on the DRAM cell with internal refresh and address control features,
and interfaces as a synchronous NOR Flash, plus has synchronous write capability.
7.1.4.2.5 Supported Protocols

The GPMC supports the following interface protocols when communicating with external memory or
external devices:
• Asynchronous read/write access
• Asynchronous read page access (4-8-16 Word16)
• Synchronous read/write access
• Synchronous read burst access without wrap capability (4-8-16 Word16)
• Synchronous read burst access with wrap capability (4-8-16 Word16)
7.1.4.2.6 GPMC Features and Settings

This section lists GPMC features and settings:
• Supported device type: up to four NAND or NOR protocol external memories or devices
• Operating Voltage: 3.3V
• Maximum GPMC addressing capability: 512 MBytes divided into eight chip-selects
• Maximum supported memory size: 256 MBytes (must be a power-of-2)
• Minimum supported memory size: 16 MBytes (must be a power-of-2). Aliasing occurs when addressing
smaller memories.
• Data path to external memory or device: 8- and 16-bit wide
• Burst and page access: burst of 4-8-16 Word16
• Supports bus keeping
• Supports bus turn around
7.1.5 GPMC Registers

Table 7-48 lists the memory-mapped registers for the GPMC. All register offset addresses not listed in
Table 7-48. GPMC Registers

0h GPMC_REVISION Section 7.1.5.1
10h GPMC_SYSCONFIG Section 7.1.5.2
14h GPMC_SYSSTATUS Section 7.1.5.3
18h GPMC_IRQSTATUS Section 7.1.5.4
1Ch GPMC_IRQENABLE Section 7.1.5.5
40h GPMC_TIMEOUT_CONTROL Section 7.1.5.6
44h GPMC_ERR_ADDRESS Section 7.1.5.7
48h GPMC_ERR_TYPE Section 7.1.5.8
50h GPMC_CONFIG Section 7.1.5.9
54h GPMC_STATUS Section 7.1.5.10

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Table 7-48. GPMC Registers (continued)

60h GPMC_CONFIG1_0 Section 7.1.5.11
6Ch GPMC_CONFIG4_0 Section 7.1.5.14
7Ch GPMC_NAND_COMMAND_0 Section 7.1.5.18
80h GPMC_NAND_ADDRESS_0 Section 7.1.5.19
84h GPMC_NAND_DATA_0 Section 7.1.5.20
A0h GPMC_CONFIG5_1 Section 7.1.5.25
ACh GPMC_NAND_COMMAND_1 Section 7.1.5.28
B0h GPMC_NAND_ADDRESS_1 Section 7.1.5.29
B4h GPMC_NAND_DATA_1 Section 7.1.5.30
C0h GPMC_CONFIG1_2 Section 7.1.5.31
CCh GPMC_CONFIG4_2 Section 7.1.5.34
D0h GPMC_CONFIG5_2 Section 7.1.5.35
DCh GPMC_NAND_COMMAND_2 Section 7.1.5.38
E0h GPMC_NAND_ADDRESS_2 Section 7.1.5.39
E4h GPMC_NAND_DATA_2 Section 7.1.5.40
F0h GPMC_CONFIG1_3 Section 7.1.5.41
FCh GPMC_CONFIG4_3 Section 7.1.5.44

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1A0h GPMC_NAND_ADDRESS_6 Section 7.1.5.79
1A4h GPMC_NAND_DATA_6 Section 7.1.5.80
1E0h GPMC_PREFETCH_CONFIG1 Section 7.1.5.81
1E4h GPMC_PREFETCH_CONFIG2 Section 7.1.5.82
1ECh GPMC_PREFETCH_CONTROL Section 7.1.5.83
1F0h GPMC_PREFETCH_STATUS Section 7.1.5.84
1F4h GPMC_ECC_CONFIG Section 7.1.5.85
1F8h GPMC_ECC_CONTROL Section 7.1.5.86
1FCh GPMC_ECC_SIZE_CONFIG Section 7.1.5.87
200h GPMC_ECC1_RESULT Section 7.1.5.88
20Ch GPMC_ECC4_RESULT Section 7.1.5.91
21Ch GPMC_ECC8_RESULT Section 7.1.5.95
240h GPMC_BCH_RESULT0_0 Section 7.1.5.97
24Ch GPMC_BCH_RESULT3_0 Section 7.1.5.100

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2A0h GPMC_BCH_RESULT0_6 Section 7.1.5.121
2ACh GPMC_BCH_RESULT3_6 Section 7.1.5.124
2B0h GPMC_BCH_RESULT0_7 Section 7.1.5.125
2BCh GPMC_BCH_RESULT3_7 Section 7.1.5.128
2D0h GPMC_BCH_SWDATA Section 7.1.5.129

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7.1.5.1 GPMC_REVISION Register (offset = 0h) [reset = 0h]

GPMC_REVISION is shown in Figure 7-47 and described in Table 7-49.
The GPMC_REVISION register contains the IP revision code.
Figure 7-47. GPMC_REVISION Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED REV
R-0h R-0h
Table 7-49. GPMC_REVISION Register Field Descriptions

31-8 RESERVED R 0h
7-0 REV R 0h IP revision.
Major revision is
[7:4].
Minor revision is
[3:0].
Examples: 10h for revision 1.0, 21h for revision 2.1.

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7.1.5.2 GPMC_SYSCONFIG Register (offset = 10h) [reset = 0h]

GPMC_SYSCONFIG is shown in Figure 7-48 and described in Table 7-50.
The GPMC_SYSCONFIG register controls the various parameters of the OCP interface.
Figure 7-48. GPMC_SYSCONFIG Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED SIDLEMODE RESERVED SOFTRESET AUTOIDLE
R-0h R/W-0h R-0h R/W-0h R/W-0h
Table 7-50. GPMC_SYSCONFIG Register Field Descriptions

31-5 RESERVED R 0h
4-3 SIDLEMODE R/W 0h Idle mode
0h = Force-idle. An idle request is acknowledged unconditionally
1h = No-idle. An idle request is never acknowledged
2h = Smart-idle. Acknowledgment to an idle request is given based
on the internal activity of the module
3h = Reserved
2 RESERVED R 0h
1 SOFTRESET R/W 0h Software reset (Set 1 to this bit triggers a module reset.
This bit is automatically reset by hardware.
During reads, it always returns 0).
0h = Normal mode
1h = The module is reset
0 AUTOIDLE R/W 0h Internal OCP clock gating strategy.
0h = Interface clock is free-running
1h = Automatic interface clock gating strategy is applied based on
the interconnect activity.

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7.1.5.3 GPMC_SYSSTATUS Register (offset = 14h) [reset = 0h]

GPMC_SYSSTATUS is shown in Figure 7-49 and described in Table 7-51.
The GPMC_SYSSTATUS register provides status information about the module, excluding the interrupt
status information.
Figure 7-49. GPMC_SYSSTATUS Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RESETDONE
R-0h R-0h
Table 7-51. GPMC_SYSSTATUS Register Field Descriptions

31-1 RESERVED R 0h
0 RESETDONE R 0h Internal reset monitoring
0h (R) = Internal module reset in on-going
1h (R) = Reset completed

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7.1.5.4 GPMC_IRQSTATUS Register (offset = 18h) [reset = 0h]

GPMC_IRQSTATUS is shown in Figure 7-50 and described in Table 7-52.
The GPMC_IRQSTATUS interrupt status register regroups all the status of the module internal events that
can generate an interrupt.
Figure 7-50. GPMC_IRQSTATUS Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED WAIT1EDGED WAIT0EDGED
ETECTIONSTA ETECTIONSTA
TUS TUS
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED TERMINALCO FIFOEVENTST
UNTSTATUS ATUS
R-0h R/W-0h R/W-0h
Table 7-52. GPMC_IRQSTATUS Register Field Descriptions

31-10 RESERVED R 0h
9 WAIT1EDGEDETECTION R/W 0h Status of the Wait1 Edge Detection interrupt
STATUS
0h (W) = WAIT1EDGEDETECTIONSTATUS bit unchanged
0h (R) = A transition on WAIT1 input pin has not been detected
1h (W) = WAIT1EDGEDETECTIONSTATUS bit is reset
1h (R) = A transition on WAIT1 input pin has been detected
8 WAIT0EDGEDETECTION R/W 0h Status of the Wait0 Edge Detection interrupt
STATUS
0h (W) = WAIT0EDGEDETECTIONSTATUS bit unchanged
0h (R) = A transition on WAIT0 input pin has not been detected
1h (W) = WAIT0EDGEDETECTIONSTATUS bit is reset
1h (R) = A transition on WAIT0 input pin has been detected
7-2 RESERVED R 0h
1 TERMINALCOUNTSTAT R/W 0h Status of the TerminalCountEvent interrupt
US
0h = TERMINALCOUNTSTATUS bit unchanged
1h = Indicates that CountValue is equal to 0
0 FIFOEVENTSTATUS R/W 0h Status of the FIFOEvent interrupt
0h (W) = FIFOEVENTSTATUS bit unchanged
0h (R) = Indicates than less than GPMC_PREFETCH_STATUS[16]
FIFOTHRESHOLDSTATUS bytes are available in prefetch mode
and less than FIFOTHRESHOLD bytes free places are available in
write-posting mode.
1h (W) = FIFOEVENTSTATUS bit is reset
1h (R) = Indicates than at least GPMC_PREFETCH_STATUS[16]
FIFOTHRESHOLDSTATUS bytes are available in prefetch mode
and at least FIFOTHRESHOLD bytes free places are available in
write-posting mode.

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7.1.5.5 GPMC_IRQENABLE Register (offset = 1Ch) [reset = 0h]

GPMC_IRQENABLE is shown in Figure 7-51 and described in Table 7-53.
The GPMC_IRQENABLE interrupt enable register allows to mask/unmask the module internal sources of
interrupt, on a event-by-event basis.
Figure 7-51. GPMC_IRQENABLE Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED WAIT1EDGED WAIT0EDGED
ETECTIONENA ETECTIONENA
BLE BLE
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED TERMINALCO FIFOEVENTEN
UNTEVENTEN ABLE
ABLE
R-0h R/W-0h R/W-0h
Table 7-53. GPMC_IRQENABLE Register Field Descriptions

31-10 RESERVED R 0h
9 WAIT1EDGEDETECTION R/W 0h Enables the Wait1 Edge Detection interrupt
ENABLE
0h = Wait1EdgeDetection interrupt is masked
1h = Wait1EdgeDetection event generates an interrupt if occurs
8 WAIT0EDGEDETECTION R/W 0h Enables the Wait0 Edge Detection interrupt
ENABLE
0h = Wait0EdgeDetection interrupt is masked
1h = Wait0EdgeDetection event generates an interrupt if occurs
7-2 RESERVED R 0h
1 TERMINALCOUNTEVEN R/W 0h Enables TerminalCountEvent interrupt issuing in pre-fetch or write
TENABLE posting mode
0h = TerminalCountEvent interrupt is masked
1h = TerminalCountEvent interrupt is not masked
0 FIFOEVENTENABLE R/W 0h Enables the FIFOEvent interrupt
0h = FIFOEvent interrupt is masked
1h = FIFOEvent interrupt is not masked

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7.1.5.6 GPMC_TIMEOUT_CONTROL Register (offset = 40h) [reset = 0h]

GPMC_TIMEOUT_CONTROL is shown in Figure 7-52 and described in Table 7-54.
The GPMC_TIMEOUT_CONTROL register allows the user to set the start value of the timeout counter
Figure 7-52. GPMC_TIMEOUT_CONTROL Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED TIMEOUTSTARTVALUE
R-0h R/W-0h
7 6 5 4 3 2 1 0
TIMEOUTSTARTVALUE RESERVED TIMEOUTENA
BLE
R/W-0h R-0h R/W-0h
Table 7-54. GPMC_TIMEOUT_CONTROL Register Field Descriptions

31-13 RESERVED R 0h
12-4 TIMEOUTSTARTVALUE R/W 0h Start value of the time-out counter (000 corresponds to 0
GPMC.FCLK cycle, 1h corresponds to 1 GPMC.FCLK cycle, and
1FFh corresponds to 511 GPMC.FCLK cycles)
3-1 RESERVED R 0h
0 TIMEOUTENABLE R/W 0h Enable bit of the TimeOut feature
0h = TimeOut feature is disabled
1h = TimeOut feature is enabled

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7.1.5.7 GPMC_ERR_ADDRESS Register (offset = 44h) [reset = 0h]

GPMC_ERR_ADDRESS is shown in Figure 7-53 and described in Table 7-55.
The GPMC_ERR_ADDRESS register stores the address of the illegal access when an error occurs.
Figure 7-53. GPMC_ERR_ADDRESS Register

31 30 29 28 27 26 25 24
RESERVED ILLEGALADD
R-0h R/W-0h
23 22 21 20 19 18 17 16
ILLEGALADD
R/W-0h
15 14 13 12 11 10 9 8
ILLEGALADD
R/W-0h
7 6 5 4 3 2 1 0
ILLEGALADD
R/W-0h
Table 7-55. GPMC_ERR_ADDRESS Register Field Descriptions

31 RESERVED R 0h
30-0 ILLEGALADD R/W 0h Address of illegal access: A30 (0 for memory region, 1 for GPMC
register region) and A29 to A0 (1GByte maximum)

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7.1.5.8 GPMC_ERR_TYPE Register (offset = 48h) [reset = 0h]

GPMC_ERR_TYPE is shown in Figure 7-54 and described in Table 7-56.
The GPMC_ERR_TYPE register stores the type of error when an error occurs.
Figure 7-54. GPMC_ERR_TYPE Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED ILLEGALMCMD
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED ERRORNOTSU ERRORNOTSU ERRORTIMEO RESERVED ERRORVALID
PPADD PPMCMD UT
R-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h
Table 7-56. GPMC_ERR_TYPE Register Field Descriptions

31-11 RESERVED R 0h
10-8 ILLEGALMCMD R/W 0h System Command of the transaction that caused the error
7-5 RESERVED R 0h
4 ERRORNOTSUPPADD R/W 0h Not supported Address error
0h = No error occurs
1h = The error is due to a non supported Address
3 ERRORNOTSUPPMCMD R/W 0h Not supported Command error
1h = The error is due to a non supported Command
2 ERRORTIMEOUT R/W 0h Time-out error
1h = The error is due to a time out
1 RESERVED R 0h
0 ERRORVALID R/W 0h Error validity status - Must be explicitly cleared with a write 1
transaction
0h = All error fields no longer valid
1h = Error detected and logged in the other error fields

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7.1.5.9 GPMC_CONFIG Register (offset = 50h) [reset = 0h]

GPMC_CONFIG is shown in Figure 7-55 and described in Table 7-57.
The configuration register allows global configuration of the GPMC.
Figure 7-55. GPMC_CONFIG Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED WAIT1PINPOL WAIT0PINPOL
ARITY ARITY
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED WRITEPROTE RESERVED LIMITEDADDR NANDFORCEP
CT ESS OSTEDWRITE
Table 7-57. GPMC_CONFIG Register Field Descriptions

31-10 RESERVED R 0h
9 WAIT1PINPOLARITY R/W 0h Selects the polarity of input pin WAIT1.
0h = WAIT1 active low
1h = WAIT1 active high
8 WAIT0PINPOLARITY R/W 0h Selects the polarity of input pin WAIT0.
0h = WAIT0 active low
1h = WAIT0 active high
7-5 RESERVED R 0h
4 WRITEPROTECT R/W 0h Controls the WP output pin level.
0h = WP output pin is low
1h = WP output pin is high
3-2 RESERVED R 0h
1 LIMITEDADDRESS R/W 0h Limited Address device support.
0h = No effect. GPMC controls all addresses.
1h = A26-A11 are not modified during an external memory access.
0 NANDFORCEPOSTEDW R/W 0h
0h = Disables Force Posted Write
RITE
1h = Enables Force Posted Write

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7.1.5.10 GPMC_STATUS Register (offset = 54h) [reset = 0h]

GPMC_STATUS is shown in Figure 7-56 and described in Table 7-58.
The status register provides global status bits of the GPMC.
Figure 7-56. GPMC_STATUS Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED WAIT1STATUS WAIT0STATUS
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED EMPTYWRITE
BUFFERSTAT
US
R-0h R/W-0h
Table 7-58. GPMC_STATUS Register Field Descriptions

31-10 RESERVED R 0h
9 WAIT1STATUS R/W 0h Is a copy of input pin WAIT1.
(Reset value is WAIT1 input pin sampled at IC reset)
0h = WAIT1 asserted (inactive state)
1h = WAIT1 de-asserted
8 WAIT0STATUS R/W 0h Is a copy of input pin WAIT0.
(Reset value is WAIT0 input pin sampled at IC reset)
0h = WAIT0 asserted (inactive state)
1h = WAIT0 de-asserted
7-1 RESERVED R 0h
0 EMPTYWRITEBUFFERS R/W 0h Stores the empty status of the write buffer
TATUS
0h = Write Buffer is not empty
1h = Write Buffer is empty

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7.1.5.11 GPMC_CONFIG1_0 Register (offset = 60h) [reset = 0h]

GPMC_CONFIG1_0 is shown in Figure 7-57 and described in Table 7-59.
The configuration 1 register sets signal control parameters per chip select.
Figure 7-57. GPMC_CONFIG1_0 Register

31 30 29 28 27 26 25 24
WRAPBURST READMULTIPL READTYPE WRITEMULTIP WRITETYPE CLKACTIVATIONTIME ATTACHEDDE
E LE VICEPAGELEN
GTH
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
ATTACHEDDE WAITREADMO WAITWRITEM RESERVED WAITMONITORINGTIME WAITPINSELECT
VICEPAGELEN NITORING ONITORING
GTH
R/W-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED DEVICESIZE DEVICETYPE MUXADDDATA
7 6 5 4 3 2 1 0
RESERVED TIMEPARAGR RESERVED GPMCFCLKDIVIDER
ANULARITY
Table 7-59. GPMC_CONFIG1_0 Register Field Descriptions

31 WRAPBURST R/W 0h Enables the wrapping burst capability.
Must be set if the attached device is configured in wrapping burst
0h = Synchronous wrapping burst not supported
1h = Synchronous wrapping burst supported
30 READMULTIPLE R/W 0h Selects the read single or multiple access
0h = single access
1h = multiple access (burst if synchronous, page if asynchronous)
29 READTYPE R/W 0h Selects the read mode operation
0h = Read Asynchronous
1h = Read Synchronous
28 WRITEMULTIPLE R/W 0h Selects the write single or multiple access
0h = Single access
1h = Multiple access (burst if synchronous, considered as single if
asynchronous)
27 WRITETYPE R/W 0h Selects the write mode operation
0h = Write Asynchronous
1h = Write Synchronous
26-25 CLKACTIVATIONTIME R/W 0h Output GPMC.CLK activation time
0h = First rising edge of GPMC_CLK at start access time
1h = First rising edge of GPMC_CLK one GPMC_FCLK cycle after
start access time
2h = First rising edge of GPMC_CLK two GPMC_FCLK cycles after
start access time
3h = Reserved

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Table 7-59. GPMC_CONFIG1_0 Register Field Descriptions (continued)

24-23 ATTACHEDDEVICEPAG R/W 0h Specifies the attached device page (burst) length (1 Word =
ELENGTH Interface size)
0h = 4 Words
1h = 8 Words
2h = 16 Words
3h = Reserved
22 WAITREADMONITORING R/W 0h Selects the Wait monitoring configuration for Read accesses.
0h = WAIT pin is not monitored for read accesses
1h = WAIT pin is monitored for read accesses
21 WAITWRITEMONITORIN R/W 0h Selects the Wait monitoring configuration for Write accesses
G
0h = WAIT pin is not monitored for write accesses
1h = WAIT pin is monitored for write accesses
20 RESERVED R 0h
19-18 WAITMONITORINGTIME R/W 0h Selects input pin Wait monitoring time
0h = WAIT pin is monitored with valid data
1h = WAIT pin is monitored one GPMC_CLK cycle before valid data
2h = WAIT pin is monitored two GPMC_CLK cycle before valid data
3h = Reserved
17-16 WAITPINSELECT R/W 0h Selects the input WAIT pin for this chip select.
0h = WAIT input pin is WAIT0
2h = Reserved
3h = Reserved
15-14 RESERVED R 0h
13-12 DEVICESIZE R/W 0h Selects the device size attached (Reset value is SYSBOOT[8] input
pin sampled at IC reset for CS[0] (active low) and 01 for CS[1] to
CS[6] (active low)).
0h = 8 bit
1h = 16 bit
2h = Reserved
3h = Reserved
11-10 DEVICETYPE R/W 0h Selects the attached device type
0h = NOR Flash like, asynchronous and synchronous devices
1h = Reserved
2h = NAND Flash like devices, stream mode
3h = Reserved
9-8 MUXADDDATA R/W 0h Enables the Address and data multiplexed protocol (Reset value is
SYSBOOT[11] and SYSBOOT[10] input pins sampled at IC reset for
CS[0] (active low) and 0 for CS[1] to CS[6] (active low)).
0h = Non-multiplexed attached device
1h = AAD-multiplexed protocol device
2h = Address and data multiplexed attached device
3h = Reserved
7-5 RESERVED R 0h
4 TIMEPARAGRANULARIT R/W 0h Signals timing latencies scalar factor (Rd/WRCycleTime,
Y AccessTime, PageBurstAccessTime, CSOnTime, CSRd/WrOffTime,
ADVOnTime, ADVRd/WrOffTime, OEOnTime, OEOffTime,
WEOnTime, WEOffTime, Cycle2CycleDelay, BusTurnAround,
TimeOutStartValue)
0h = x1 latencies
1h = x2 latencies
3-2 RESERVED R 0h

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1-0 GPMCFCLKDIVIDER R/W 0h Divides the GPMC.FCLK clock
0h = GPMC_CLK frequency = GPMC_FCLK frequency
1h = GPMC_CLK frequency = GPMC_FCLK frequency/2

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Chip-select signal timing parameter configuration.

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED CSWROFFTIME
R-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED CSRDOFFTIME
R-0h R/W-0h
7 6 5 4 3 2 1 0
CSEXTRADEL RESERVED CSONTIME
AY
R/W-0h R-0h R/W-0h

31-21 RESERVED R 0h
20-16 CSWROFFTIME R/W 0h CS# de-assertion time from start cycle time for write accesses
0h = 0 GPMC_FCLK cycle
1Fh = 31 GPMC_FCLK cycles
15-13 RESERVED R 0h
12-8 CSRDOFFTIME R/W 0h CS# de-assertion time from start cycle time for read accesses
7 CSEXTRADELAY R/W 0h CS# Add Extra Half GPMC.FCLK cycle
0h = CS i Timing control signal is not delayed
1h = CS i Timing control signal is delayed of half GPMC_FCLK clock
cycle
6-4 RESERVED R 0h
3-0 CSONTIME R/W 0h CS# assertion time from start cycle time

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ADV# signal timing parameter configuration.

31 30 29 28 27 26 25 24
RESERVED ADVAADMUXWROFFTIME RESERVED ADVAADMUXRDOFFTIME
23 22 21 20 19 18 17 16
RESERVED ADVWROFFTIME
R-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED ADVRDOFFTIME
R-0h R/W-0h
7 6 5 4 3 2 1 0
ADVEXTRADE ADVAADMUXONTIME ADVONTIME
LAY

31 RESERVED R 0h
30-28 ADVAADMUXWROFFTIM R/W 0h ADV# de-assertion for first address phase when using the AAD-Mux
E protocol
7h = 7 GPMC_FCLK cycles
27 RESERVED R 0h
26-24 ADVAADMUXRDOFFTIM R/W 0h ADV# assertion for first address phase when using the AAD-Mux
E protocol
23-21 RESERVED R 0h
20-16 ADVWROFFTIME R/W 0h ADV# de-assertion time from start cycle time for write accesses
15-13 RESERVED R 0h
12-8 ADVRDOFFTIME R/W 0h ADV# de-assertion time from start cycle time for read accesses
7 ADVEXTRADELAY R/W 0h ADV# Add Extra Half GPMC.FCLK cycle
0h = ADV (active low) Timing control signal is not delayed
1h = ADV (active low) Timing control signal is delayed of half
GPMC_FCLK clock cycle
6-4 ADVAADMUXONTIME R/W 0h ADV# assertion for first address phase when using the AAD-
Multiplexed protocol

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3-0 ADVONTIME R/W 0h ADV# assertion time from start cycle time
Fh = 15 GPMC_FCLK cycles

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7.1.5.14 GPMC_CONFIG4_0 Register (offset = 6Ch) [reset = 0h]

WE# and OE# signals timing parameter configuration.

31 30 29 28 27 26 25 24
RESERVED WEOFFTIME
R-0h R/W-0h
23 22 21 20 19 18 17 16
WEEXTRADEL RESERVED WEONTIME
AY
R/W-0h R-0h R/W-0h
15 14 13 12 11 10 9 8
OEAADMUXOFFTIME OEOFFTIME
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OEEXTRADEL OEAADMUXONTIME OEONTIME
AY

31-29 RESERVED R 0h
28-24 WEOFFTIME R/W 0h WE# de-assertion time from start cycle time
23 WEEXTRADELAY R/W 0h WE# Add Extra Half GPMC.FCLK cycle
0h = WE (active low) Timing control signal is not delayed
1h = WE (active low) Timing control signal is delayed of half
22-20 RESERVED R 0h
19-16 WEONTIME R/W 0h WE# assertion time from start cycle time
15-13 OEAADMUXOFFTIME R/W 0h OE# de-assertion time for the first address phase in an AAD-
Multiplexed access
12-8 OEOFFTIME R/W 0h OE# de-assertion time from start cycle time
0h = (R/W) 0 GPMC_FCLK cycle
1Fh = (R/W) 31 GPMC_FCLK cycles
7 OEEXTRADELAY R/W 0h OE# Add Extra Half GPMC.FCLK cycle
0h = OE (active low) Timing control signal is not delayed
1h = OE (active low) Timing control signal is delayed of half

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6-4 OEAADMUXONTIME R/W 0h OE# assertion time for the first address phase in an AAD-Multiplexed
access
3-0 OEONTIME R/W 0h OE# assertion time from start cycle time

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RdAccessTime and CycleTime timing parameters configuration.

31 30 29 28 27 26 25 24
RESERVED PAGEBURSTACCESSTIME
R-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED RDACCESSTIME
R-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED WRCYCLETIME
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED RDCYCLETIME
R-0h R/W-0h

31-28 RESERVED R 0h
27-24 PAGEBURSTACCESSTI R/W 0h Delay between successive words in a multiple access
ME
23-21 RESERVED R 0h
20-16 RDACCESSTIME R/W 0h Delay between start cycle time and first data valid
15-13 RESERVED R 0h
12-8 WRCYCLETIME R/W 0h Total write cycle time
7-5 RESERVED R 0h
4-0 RDCYCLETIME R/W 0h Total read cycle time

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7.1.5.16 GPMC_CONFIG6_0 Register (offset = 74h) [reset = F070000h]

WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle, and BusTurnAround parameters configuration

31 30 29 28 27 26 25 24
RESERVED WRACCESSTIME
R-0h R/W-Fh
23 22 21 20 19 18 17 16
RESERVED WRDATAONADMUXBUS
R-0h R/W-7h
15 14 13 12 11 10 9 8
RESERVED CYCLE2CYCLEDELAY
R-0h R/W-0h
7 6 5 4 3 2 1 0
CYCLE2CYCL CYCLE2CYCL RESERVED BUSTURNAROUND
ESAMECSEN EDIFFCSEN
R/W-0h R/W-0h R-0h R/W-0h

31-29 RESERVED R 0h Reset value for bit 31 is 1.
28-24 WRACCESSTIME R/W Fh Delay from StartAccessTime to the GPMC.FCLK rising edge
corresponding the the GPMC.CLK rising edge used by the attached
memory for the first data capture.
Reset value is 0xF.
23-20 RESERVED R 0h
19-16 WRDATAONADMUXBUS R/W 7h Specifies on which GPMC.FCLK rising edge the first data of the
synchronous burst write is driven in the add/data multiplexed bus.
Reset value is 0x7.
15-12 RESERVED R 0h
11-8 CYCLE2CYCLEDELAY R/W 0h Chip select high pulse delay between two successive accesses
7 CYCLE2CYCLESAMECS R/W 0h Add Cycle2CycleDelay between two successive accesses to the
EN same chip-select (any access type)
0h = No delay between the two accesses
1h = Add CYCLE2CYCLEDELAY
6 CYCLE2CYCLEDIFFCSE R/W 0h Add Cycle2CycleDelay between two successive accesses to a
N different chip-select (any access type)
5-4 RESERVED R 0h
3-0 BUSTURNAROUND R/W 0h Bus turn around latency between two successive accesses to the
same chip-select (read to write) or to a different chip-select (read to
read and read to write)

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Chip-select address mapping configuration.

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED MASKADDRESS
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED CSVALID BASEADDRESS
R-0h R/W-0h R/W-0h

31-12 RESERVED R 0h
11-8 MASKADDRESS R/W 0h Chip-select mask address.
Values not listed must be avoided as they create holes in the chip-
select address space.
0h = Chip-select size of 256 Mbytes
Ch = Chip-select size of 64 Mbytes
Eh = Chip-select size of 32 Mbytes
Fh = Chip-select size of 16 Mbytes
7 RESERVED R 0h
6 CSVALID R/W 0h Chip-select enable (reset value is 1 for CS[0] (active low) and 0 for
CS[1] to CS[5] (active low)).
0h = CS (active low) disabled
1h = CS (active low) enabled
5-0 BASEADDRESS R/W 0h Chip-select base address.
CSi base address where i = 0 to 6 (16 Mbytes minimum granularity).
Bits 5 to 0 correspond to A29, A28, A27, A26, A25, and A24.

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7.1.5.18 GPMC_NAND_COMMAND_0 Register (offset = 7Ch) [reset = 0h]

GPMC_NAND_COMMAND_0 is shown in Figure 7-64 and described in Table 7-66.
This register is not a true register, just an address location.
Figure 7-64. GPMC_NAND_COMMAND_0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_COMMAND_0
W-0h
Table 7-66. GPMC_NAND_COMMAND_0 Register Field Descriptions

31-0 GPMC_NAND_COMMAN W 0h Writing data at the GPMC_NAND_COMMAND_0 location places the
D_0 data as the NAND command value on the bus, using a regular
asynchronous write access.

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7.1.5.19 GPMC_NAND_ADDRESS_0 Register (offset = 80h) [reset = 0h]

GPMC_NAND_ADDRESS_0 is shown in Figure 7-65 and described in Table 7-67.
Figure 7-65. GPMC_NAND_ADDRESS_0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_ADDRESS_0
W-0h
Table 7-67. GPMC_NAND_ADDRESS_0 Register Field Descriptions

31-0 GPMC_NAND_ADDRESS W 0h Writing data at the GPMC_NAND_ADDRESS_0 location places the
_0 data as the NAND partial address value on the bus, using a regular

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7.1.5.20 GPMC_NAND_DATA_0 Register (offset = 84h) [reset = 0h]

GPMC_NAND_DATA_0 is shown in Figure 7-66 and described in Table 7-68.
Figure 7-66. GPMC_NAND_DATA_0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_DATA_0
R/W-0h
Table 7-68. GPMC_NAND_DATA_0 Register Field Descriptions

31-0 GPMC_NAND_DATA_0 R/W 0h Reading data from the GPMC_NAND_DATA_0 location or from any
location in the associated chip-select memory region activates an
asynchronous read access.

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31 30 29 28 27 26 25 24
E LE VICEPAGELEN
GTH
23 22 21 20 19 18 17 16
GTH
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
ANULARITY

0h = single access
0h = Single access
asynchronous)
start access time
start access time
3h = Reserved

GPMC www.ti.com

0h = 4 Words
1h = 8 Words
2h = 16 Words
3h = Reserved
G
20 RESERVED R 0h
3h = Reserved
2h = Reserved
3h = Reserved
15-14 RESERVED R 0h
0h = 8 bit
1h = 16 bit
2h = Reserved
3h = Reserved
11-10 DEVICETYPE R/W 0h Selects the attached device type.
1h = Reserved
3h = Reserved
3h = Reserved
7-5 RESERVED R 0h
TimeOutStartValue)
0h = x1 latencies
1h = x2 latencies
3-2 RESERVED R 0h

www.ti.com GPMC

1-0 GPMCFCLKDIVIDER R/W 0h Divides the GPMC.FCLK clock.

GPMC www.ti.com


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
R-0h R/W-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
AY
R/W-0h R-0h R/W-0h

31-21 RESERVED R 0h
15-13 RESERVED R 0h
cycle
6-4 RESERVED R 0h

www.ti.com GPMC


31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
R-0h R/W-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
LAY

31 RESERVED R 0h
E protocol
27 RESERVED R 0h
E protocol
23-21 RESERVED R 0h
15-13 RESERVED R 0h

GPMC www.ti.com


www.ti.com GPMC


31 30 29 28 27 26 25 24
RESERVED WEOFFTIME
R-0h R/W-0h
23 22 21 20 19 18 17 16
AY
R/W-0h R-0h R/W-0h
15 14 13 12 11 10 9 8
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
AY

31-29 RESERVED R 0h
22-20 RESERVED R 0h
Multiplexed access

GPMC www.ti.com

access

www.ti.com GPMC
7.1.5.25 GPMC_CONFIG5_1 Register (offset = A0h) [reset = 0h]


31 30 29 28 27 26 25 24
R-0h R/W-0h
23 22 21 20 19 18 17 16
R-0h R/W-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
R-0h R/W-0h

31-28 RESERVED R 0h
ME
23-21 RESERVED R 0h
15-13 RESERVED R 0h
7-5 RESERVED R 0h

GPMC www.ti.com
7.1.5.26 GPMC_CONFIG6_1 Register (offset = A4h) [reset = F070000h]


31 30 29 28 27 26 25 24
R-0h R/W-Fh
23 22 21 20 19 18 17 16
R-0h R/W-7h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
ESAMECSEN EDIFFCSEN

Reset value is 0xF.
23-20 RESERVED R 0h
Reset value is 0x7.
15-12 RESERVED R 0h
5-4 RESERVED R 0h

www.ti.com GPMC
7.1.5.27 GPMC_CONFIG7_1 Register (offset = A8h) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
R-0h R/W-0h R/W-0h

31-12 RESERVED R 0h
7 RESERVED R 0h

GPMC www.ti.com
7.1.5.28 GPMC_NAND_COMMAND_1 Register (offset = ACh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_COMMAND_1
W-0h


www.ti.com GPMC
7.1.5.29 GPMC_NAND_ADDRESS_1 Register (offset = B0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_ADDRESS_1
W-0h


GPMC www.ti.com
7.1.5.30 GPMC_NAND_DATA_1 Register (offset = B4h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_DATA_1
R/W-0h


www.ti.com GPMC
7.1.5.31 GPMC_CONFIG1_2 Register (offset = C0h) [reset = 0h]


31 30 29 28 27 26 25 24
E LE VICEPAGELEN
GTH
23 22 21 20 19 18 17 16
GTH
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
ANULARITY

0h = single access
0h = Single access
asynchronous)
start access time
start access time
3h = Reserved

GPMC www.ti.com

0h = 4 Words
1h = 8 Words
2h = 16 Words
3h = Reserved
G
20 RESERVED R 0h
3h = Reserved
2h = Reserved
3h = Reserved
15-14 RESERVED R 0h
0h = 8 bit
1h = 16 bit
2h = Reserved
3h = Reserved
11-10 DEVICETYPE R/W 0h Selects the attached device type.
1h = Reserved
3h = Reserved
3h = Reserved
7-5 RESERVED R 0h
TimeOutStartValue).
0h = x1 latencies
1h = x2 latencies
3-2 RESERVED R 0h

www.ti.com GPMC


GPMC www.ti.com


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
R-0h R/W-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
AY
R/W-0h R-0h R/W-0h

31-21 RESERVED R 0h
15-13 RESERVED R 0h
cycle
6-4 RESERVED R 0h

www.ti.com GPMC


31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
R-0h R/W-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
LAY

31 RESERVED R 0h
E protocol
27 RESERVED R 0h
E protocol
23-21 RESERVED R 0h
15-13 RESERVED R 0h

GPMC www.ti.com


www.ti.com GPMC
7.1.5.34 GPMC_CONFIG4_2 Register (offset = CCh) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED WEOFFTIME
R-0h R/W-0h
23 22 21 20 19 18 17 16
AY
R/W-0h R-0h R/W-0h
15 14 13 12 11 10 9 8
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
AY

31-29 RESERVED R 0h
22-20 RESERVED R 0h
Multiplexed access

GPMC www.ti.com

access

www.ti.com GPMC
7.1.5.35 GPMC_CONFIG5_2 Register (offset = D0h) [reset = 0h]


31 30 29 28 27 26 25 24
R-0h R/W-0h
23 22 21 20 19 18 17 16
R-0h R/W-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
R-0h R/W-0h

31-28 RESERVED R 0h
ME
23-21 RESERVED R 0h
15-13 RESERVED R 0h
7-5 RESERVED R 0h

GPMC www.ti.com
7.1.5.36 GPMC_CONFIG6_2 Register (offset = D4h) [reset = F070000h]


31 30 29 28 27 26 25 24
R-0h R/W-Fh
23 22 21 20 19 18 17 16
R-0h R/W-7h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
ESAMECSEN EDIFFCSEN

Reset value is 0xF.
23-20 RESERVED R 0h
Reset value is 0x7.
15-12 RESERVED R 0h
5-4 RESERVED R 0h

www.ti.com GPMC
7.1.5.37 GPMC_CONFIG7_2 Register (offset = D8h) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
R-0h R/W-0h R/W-0h

31-12 RESERVED R 0h
7 RESERVED R 0h

GPMC www.ti.com
7.1.5.38 GPMC_NAND_COMMAND_2 Register (offset = DCh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_COMMAND_2
W-0h


www.ti.com GPMC
7.1.5.39 GPMC_NAND_ADDRESS_2 Register (offset = E0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_ADDRESS_2
W-0h


GPMC www.ti.com
7.1.5.40 GPMC_NAND_DATA_2 Register (offset = E4h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_DATA_2
R/W-0h


www.ti.com GPMC
7.1.5.41 GPMC_CONFIG1_3 Register (offset = F0h) [reset = 0h]


31 30 29 28 27 26 25 24
E LE VICEPAGELEN
GTH
23 22 21 20 19 18 17 16
GTH
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
ANULARITY

0h = single access
0h = Single access
asynchronous)
start access time
start access time
3h = Reserved

GPMC www.ti.com

0h = 4 Words
1h = 8 Words
2h = 16 Words
3h = Reserved
G
20 RESERVED R 0h
3h = Reserved
2h = Reserved
3h = Reserved
15-14 RESERVED R 0h
0h = 8 bit
1h = 16 bit
2h = Reserved
3h = Reserved
1h = Reserved
3h = Reserved
3h = Reserved
7-5 RESERVED R 0h
TimeOutStartValue).
0h = x1 latencies
1h = x2 latencies
3-2 RESERVED R 0h

www.ti.com GPMC


GPMC www.ti.com


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
R-0h R/W-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
AY
R/W-0h R-0h R/W-0h

31-21 RESERVED R 0h
15-13 RESERVED R 0h
cycle
6-4 RESERVED R 0h

www.ti.com GPMC


31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
R-0h R/W-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
LAY

31 RESERVED R 0h
E protocol
27 RESERVED R 0h
E protocol
23-21 RESERVED R 0h
15-13 RESERVED R 0h

GPMC www.ti.com


www.ti.com GPMC
7.1.5.44 GPMC_CONFIG4_3 Register (offset = FCh) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED WEOFFTIME
R-0h R/W-0h
23 22 21 20 19 18 17 16
AY
R/W-0h R-0h R/W-0h
15 14 13 12 11 10 9 8
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
AY

31-29 RESERVED R 0h
22-20 RESERVED R 0h
Multiplexed access

GPMC www.ti.com

access

www.ti.com GPMC


31 30 29 28 27 26 25 24
R-0h R/W-0h
23 22 21 20 19 18 17 16
R-0h R/W-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
R-0h R/W-0h

31-28 RESERVED R 0h
ME
23-21 RESERVED R 0h
15-13 RESERVED R 0h
7-5 RESERVED R 0h

GPMC www.ti.com


31 30 29 28 27 26 25 24
R-0h R/W-Fh
23 22 21 20 19 18 17 16
R-0h R/W-7h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
ESAMECSEN EDIFFCSEN

Reset value is 0xF.
23-20 RESERVED R 0h
Reset value is 0x7.
15-12 RESERVED R 0h
5-4 RESERVED R 0h

www.ti.com GPMC


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
R-0h R/W-0h R/W-0h

31-12 RESERVED R 0h
7 RESERVED R 0h

GPMC www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_COMMAND_3
W-0h


www.ti.com GPMC


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_ADDRESS_3
W-0h


GPMC www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_DATA_3
R/W-0h


www.ti.com GPMC


31 30 29 28 27 26 25 24
E LE VICEPAGELEN
GTH
23 22 21 20 19 18 17 16
GTH
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
ANULARITY

0h = single access
0h = Single access
asynchronous)
start access time
start access time
3h = Reserved

GPMC www.ti.com

0h = 4 Words
1h = 8 Words
2h = 16 Words
3h = Reserved
G
20 RESERVED R 0h
3h = Reserved
2h = Reserved
3h = Reserved
15-14 RESERVED R 0h
0h = 8 bit
1h = 16 bit
2h = Reserved
3h = Reserved
1h = Reserved
3h = Reserved
3h = Reserved
7-5 RESERVED R 0h
TimeOutStartValue).
0h = x1 latencies
1h = x2 latencies
3-2 RESERVED R 0h

www.ti.com GPMC


GPMC www.ti.com


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
R-0h R/W-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
AY
R/W-0h R-0h R/W-0h

31-21 RESERVED R 0h
15-13 RESERVED R 0h
cycle
6-4 RESERVED R 0h

www.ti.com GPMC


31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
R-0h R/W-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
LAY

31 RESERVED R 0h
E protocol
27 RESERVED R 0h
E protocol
23-21 RESERVED R 0h
15-13 RESERVED R 0h

GPMC www.ti.com


www.ti.com GPMC


31 30 29 28 27 26 25 24
RESERVED WEOFFTIME
R-0h R/W-0h
23 22 21 20 19 18 17 16
AY
R/W-0h R-0h R/W-0h
15 14 13 12 11 10 9 8
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
AY

31-29 RESERVED R 0h
22-20 RESERVED R 0h
Multiplexed access

GPMC www.ti.com

access

www.ti.com GPMC


31 30 29 28 27 26 25 24
R-0h R/W-0h
23 22 21 20 19 18 17 16
R-0h R/W-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
R-0h R/W-0h

31-28 RESERVED R 0h
ME
23-21 RESERVED R 0h
15-13 RESERVED R 0h
7-5 RESERVED R 0h

GPMC www.ti.com


31 30 29 28 27 26 25 24
R-0h R/W-Fh
23 22 21 20 19 18 17 16
R-0h R/W-7h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
ESAMECSEN EDIFFCSEN

Reset value is 0xF.
23-20 RESERVED R 0h
Reset value is 0x7.
15-12 RESERVED R 0h
5-4 RESERVED R 0h

www.ti.com GPMC


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
R-0h R/W-0h R/W-0h

31-12 RESERVED R 0h
7 RESERVED R 0h

GPMC www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_COMMAND_4
W-0h


www.ti.com GPMC


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_ADDRESS_4
W-0h


GPMC www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_DATA_4
R/W-0h


www.ti.com GPMC


31 30 29 28 27 26 25 24
E LE VICEPAGELEN
GTH
23 22 21 20 19 18 17 16
GTH
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
ANULARITY

0h = single access
0h = Single access
asynchronous)
start access time
start access time
3h = Reserved

GPMC www.ti.com

0h = 4 Words
1h = 8 Words
2h = 16 Words
3h = Reserved
G
20 RESERVED R 0h
3h = Reserved
2h = Reserved
3h = Reserved
15-14 RESERVED R 0h
0h = 8 bit
1h = 16 bit
2h = Reserved
3h = Reserved
1h = Reserved
3h = Reserved
3h = Reserved
7-5 RESERVED R 0h
TimeOutStartValue).
0h = x1 latencies
1h = x2 latencies
3-2 RESERVED R 0h

www.ti.com GPMC


GPMC www.ti.com


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
R-0h R/W-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
AY
R/W-0h R-0h R/W-0h

31-21 RESERVED R 0h
15-13 RESERVED R 0h
cycle
6-4 RESERVED R 0h

www.ti.com GPMC


31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
R-0h R/W-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
LAY

31 RESERVED R 0h
E protocol
27 RESERVED R 0h
E protocol
23-21 RESERVED R 0h
15-13 RESERVED R 0h

GPMC www.ti.com


www.ti.com GPMC


31 30 29 28 27 26 25 24
RESERVED WEOFFTIME
R-0h R/W-0h
23 22 21 20 19 18 17 16
AY
R/W-0h R-0h R/W-0h
15 14 13 12 11 10 9 8
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
AY

31-29 RESERVED R 0h
22-20 RESERVED R 0h
Multiplexed access

GPMC www.ti.com

access

www.ti.com GPMC


31 30 29 28 27 26 25 24
R-0h R/W-0h
23 22 21 20 19 18 17 16
R-0h R/W-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
R-0h R/W-0h

31-28 RESERVED R 0h
ME
23-21 RESERVED R 0h
15-13 RESERVED R 0h
7-5 RESERVED R 0h

GPMC www.ti.com


31 30 29 28 27 26 25 24
R-0h R/W-Fh
23 22 21 20 19 18 17 16
R-0h R/W-7h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
ESAMECSEN EDIFFCSEN

Reset value is 0xF.
23-20 RESERVED R 0h
Reset value is 0x7.
15-12 RESERVED R 0h
5-4 RESERVED R 0h

www.ti.com GPMC


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
R-0h R/W-0h R/W-0h

31-12 RESERVED R 0h
7 RESERVED R 0h

GPMC www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_COMMAND_5
W-0h


www.ti.com GPMC


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_ADDRESS_5
W-0h


GPMC www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_DATA_5
R/W-0h


www.ti.com GPMC


31 30 29 28 27 26 25 24
E LE VICEPAGELEN
GTH
23 22 21 20 19 18 17 16
GTH
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
ANULARITY

0h = single access
0h = Single access
asynchronous)
start access time
start access time
3h = Reserved

GPMC www.ti.com

0h = 4 Words
1h = 8 Words
2h = 16 Words
3h = Reserved
G
20 RESERVED R 0h
3h = Reserved
2h = Reserved
3h = Reserved
15-14 RESERVED R 0h
0h = 8 bit
1h = 16 bit
2h = Reserved
3h = Reserved
1h = Reserved
3h = Reserved
SYSBOOT[11] and SYSBOOT[10] input pin sampled at IC reset for
3h = Reserved
7-5 RESERVED R 0h
TimeOutStartValue).
0h = x1 latencies
1h = x2 latencies
3-2 RESERVED R 0h

www.ti.com GPMC


GPMC www.ti.com


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
R-0h R/W-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
AY
R/W-0h R-0h R/W-0h

31-21 RESERVED R 0h
15-13 RESERVED R 0h
cycle
6-4 RESERVED R 0h

www.ti.com GPMC


31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
R-0h R/W-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
LAY

31 RESERVED R 0h
E protocol
27 RESERVED R 0h
E protocol
23-21 RESERVED R 0h
15-13 RESERVED R 0h

GPMC www.ti.com


www.ti.com GPMC


31 30 29 28 27 26 25 24
RESERVED WEOFFTIME
R-0h R/W-0h
23 22 21 20 19 18 17 16
AY
R/W-0h R-0h R/W-0h
15 14 13 12 11 10 9 8
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
AY

31-29 RESERVED R 0h
22-20 RESERVED R 0h
Multiplexed access

GPMC www.ti.com

access

www.ti.com GPMC


31 30 29 28 27 26 25 24
R-0h R/W-0h
23 22 21 20 19 18 17 16
R-0h R/W-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
R-0h R/W-0h

31-28 RESERVED R 0h
ME
23-21 RESERVED R 0h
15-13 RESERVED R 0h
7-5 RESERVED R 0h

GPMC www.ti.com


31 30 29 28 27 26 25 24
R-0h R/W-Fh
23 22 21 20 19 18 17 16
R-0h R/W-7h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
ESAMECSEN EDIFFCSEN

Reset value is 0xF.
23-20 RESERVED R 0h
Reset value is 0x7.
15-12 RESERVED R 0h
5-4 RESERVED R 0h

www.ti.com GPMC


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
R-0h R/W-0h
7 6 5 4 3 2 1 0
R-0h R/W-0h R/W-0h

31-12 RESERVED R 0h
7 RESERVED R 0h

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_COMMAND_6
W-0h


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7.1.5.79 GPMC_NAND_ADDRESS_6 Register (offset = 1A0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_ADDRESS_6
W-0h


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7.1.5.80 GPMC_NAND_DATA_6 Register (offset = 1A4h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPMC_NAND_DATA_6
R/W-0h


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7.1.5.81 GPMC_PREFETCH_CONFIG1 Register (offset = 1E0h) [reset = 0h]

GPMC_PREFETCH_CONFIG1 is shown in Figure 7-127 and described in Table 7-129.
Figure 7-127. GPMC_PREFETCH_CONFIG1 Register

31 30 29 28 27 26 25 24
RESERVED CYCLEOPTIMIZATION ENABLEOPTIM ENGINECSSELECTOR
IZEDACCESS
23 22 21 20 19 18 17 16
PFPWENROU RESERVED PFPWWEIGHTEDPRIO
NDROBIN
R/W-0h R-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED FIFOTHRESHOLD
R-0h R/W-0h
7 6 5 4 3 2 1 0
ENABLEENGIN RESERVED WAITPINSELECTOR SYNCHROMO DMAMODE RESERVED ACCESSMODE
E DE
R/W-0h R-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h
Table 7-129. GPMC_PREFETCH_CONFIG1 Register Field Descriptions

31 RESERVED R 0h
30-28 CYCLEOPTIMIZATION R/W 0h Define the number of GPMC.FCLK cycles to be substracted from
RdCycleTime, WrCycleTime, AccessTime, CSRdOffTime,
CSWrOffTime, ADVRdOffTime, ADVWrOffTime, OEOffTime,
WEOffTime
27 ENABLEOPTIMIZEDACC R/W 0h Enables access cycle optimization
ESS
0h = Access cycle optimization is disabled
1h = Access cycle optimization is enabled
26-24 ENGINECSSELECTOR R/W 0h Selects the CS (active low) where Prefetch Postwrite engine is active
0h = CS0 (active low)
23 PFPWENROUNDROBIN R/W 0h
0h = Prefetch Postwrite engine round robin arbitration is disabled
1h = Prefetch Postwrite engine round robin arbitration is enabled
22-20 RESERVED R 0h
19-16 PFPWWEIGHTEDPRIO R/W 0h
0h = The next access is granted to the PFPW engine
1h = The two next accesses are granted to the PFPW engine
Fh = The 16 next accesses are granted to the PFPW engine
15 RESERVED R 0h
14-8 FIFOTHRESHOLD R/W 0h
0h = 0 byte
1h = 1 byte
40h = 64 bytes

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Table 7-129. GPMC_PREFETCH_CONFIG1 Register Field Descriptions (continued)

7 ENABLEENGINE R/W 0h
0h = Prefetch Postwrite engine is disabled
1h = Prefetch Postwrite engine is enabled
6 RESERVED R 0h
5-4 WAITPINSELECTOR R/W 0h
0h = Selects Wait0EdgeDetection
1h = Selects Wait1EdgeDetection
2h = Reserved
3h = Reserved
3 SYNCHROMODE R/W 0h
0h = Engine starts the access to CS as soon as STARTENGINE is
set
1h = Engine starts the access to CS as soon as STARTENGINE is
set AND wait to non wait edge detection on the selected wait pin
2 DMAMODE R/W 0h
0h = Interrupt synchronization is enabled. Only interrupt line will be
activated on FIFO threshold crossing.
1h = DMA request synchronization is enabled. A DMA request
protocol is used.
1 RESERVED R 0h
0 ACCESSMODE R/W 0h
0h = Prefetch read mode
1h = Write-posting mode

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7.1.5.82 GPMC_PREFETCH_CONFIG2 Register (offset = 1E4h) [reset = 0h]

GPMC_PREFETCH_CONFIG2 is shown in Figure 7-128 and described in Table 7-130.
Figure 7-128. GPMC_PREFETCH_CONFIG2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TRANSFERCOUNT
R-0h R/W-0h
Table 7-130. GPMC_PREFETCH_CONFIG2 Register Field Descriptions

31-14 RESERVED R 0h
13-0 TRANSFERCOUNT R/W 0h Selects the number of bytes to be read or written by the engine to
the selected CS (active low)
0h = 0 byte
1h = 1 byte
2000h = 8 Kbytes

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7.1.5.83 GPMC_PREFETCH_CONTROL Register (offset = 1ECh) [reset = 0h]

GPMC_PREFETCH_CONTROL is shown in Figure 7-129 and described in Table 7-131.
Figure 7-129. GPMC_PREFETCH_CONTROL Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED STARTENGINE
R-0h R/W-0h
Table 7-131. GPMC_PREFETCH_CONTROL Register Field Descriptions

31-1 RESERVED R 0h
0 STARTENGINE R/W 0h Resets the FIFO pointer and starts the engine
0h (W) = Stops the engine
0h (R) = Engine is stopped
1h (W) = Resets the FIFO pointer to 0 in prefetch mode and 40h in
postwrite mode and starts the engine
1h (R) = Engine is running

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7.1.5.84 GPMC_PREFETCH_STATUS Register (offset = 1F0h) [reset = 0h]

GPMC_PREFETCH_STATUS is shown in Figure 7-130 and described in Table 7-132.
Figure 7-130. GPMC_PREFETCH_STATUS Register

31 30 29 28 27 26 25 24
RESERVED FIFOPOINTER
R-0h R-0h
23 22 21 20 19 18 17 16
RESERVED FIFOTHRESH
OLDSTATUS
R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED COUNTVALUE
R-0h R-0h
7 6 5 4 3 2 1 0
COUNTVALUE
R-0h
Table 7-132. GPMC_PREFETCH_STATUS Register Field Descriptions

31 RESERVED R 0h
30-24 FIFOPOINTER R 0h FIFOPOINTER.
0h = 0 byte available to be read or 0 free empty place to be written
40h = 64 bytes available to be read or 64 empty places to be written
23-17 RESERVED R 0h
16 FIFOTHRESHOLDSTATU R 0h Set when FIFOPointer exceeds FIFOThreshold value.
S
0h = FIFOPointer smaller or equal to FIFOThreshold. Writing to this
bit has no effect
1h = FIFOPointer greater than FIFOThreshold. Writing to this bit has
no effect
15-14 RESERVED R 0h
13-0 COUNTVALUE R 0h Number of remaining bytes to be read or to be written by the engine
according to the TransferCount value.
0h = 0 byte remaining to be read or to be written
1h = 1 byte remaining to be read or to be writte
2000h = 8 Kbytes remaining to be read or to be written

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7.1.5.85 GPMC_ECC_CONFIG Register (offset = 1F4h) [reset = 0h]

GPMC_ECC_CONFIG is shown in Figure 7-131 and described in Table 7-133.
Figure 7-131. GPMC_ECC_CONFIG Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED ECCALGORIT
HM
R-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED ECCBCHTSEL ECCWRAPMODE
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
ECC16B ECCTOPSECTOR ECCCS ECCENABLE
Table 7-133. GPMC_ECC_CONFIG Register Field Descriptions

31-17 RESERVED R 0h
16 ECCALGORITHM R/W 0h ECC algorithm used
0h = Hamming code
1h = BCH code
15-14 RESERVED R 0h
13-12 ECCBCHTSEL R/W 0h Error correction capability used for BCH
0h = Up to 4 bits error correction (t = 4)
3h = Reserved
11-8 ECCWRAPMODE R/W 0h Spare area organization definition for the BCH algorithm.
See the BCH syndrome/parity calculator module functional
specification for more details
7 ECC16B R/W 0h Selects an ECC calculated on 16 columns
0h = ECC calculated on 8 columns
1h = ECC calculated on 16 columns
6-4 ECCTOPSECTOR R/W 0h Number of sectors to process with the BCH algorithm
0h = 1 sector (512kB page)
1h = 2 sectors
3h = 4 sectors (2kB page)
7h = 8 sectors (4kB page)
3-1 ECCCS R/W 0h Selects the Chip-select where ECC is computed
0h = Chip-select 0
1h = Chip-select 1
2h = Chip-select 2
3h = Chip-select 3
4h = Chip-select 4
5h = Chip-select 5
6h = Reserved
7h = Reserved

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Table 7-133. GPMC_ECC_CONFIG Register Field Descriptions (continued)

0 ECCENABLE R/W 0h Enables the ECC feature
0h = ECC disabled
1h = ECC enabled

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7.1.5.86 GPMC_ECC_CONTROL Register (offset = 1F8h) [reset = 0h]

GPMC_ECC_CONTROL is shown in Figure 7-132 and described in Table 7-134.
Figure 7-132. GPMC_ECC_CONTROL Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED ECCCLEAR
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED ECCPOINTER
R-0h R/W-0h
Table 7-134. GPMC_ECC_CONTROL Register Field Descriptions

31-9 RESERVED R 0h
8 ECCCLEAR R/W 0h Clear all ECC result registers
0h (W) = Ignored
0h (R) = All reads return 0
1h (W) = Clears all ECC result registers
7-4 RESERVED R 0h
3-0 ECCPOINTER R/W 0h Selects ECC result register (Reads to this field give the dynamic
position of the ECC pointer - Writes to this field select the ECC result
register where the first ECC computation will be stored).
Writing values not listed disables the ECC engine (ECCEnable bit of
GPMC_ECC_CONFIG cleared to 0).
0h = Writing 0 disables the ECC engine (ECCENABLE bit of
GPMC_ECC_CONFIG cleared to 0)
1h = ECC result register 1 selected

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7.1.5.87 GPMC_ECC_SIZE_CONFIG Register (offset = 1FCh) [reset = 0h]

GPMC_ECC_SIZE_CONFIG is shown in Figure 7-133 and described in Table 7-135.
Figure 7-133. GPMC_ECC_SIZE_CONFIG Register

31 30 29 28 27 26 25 24
RESERVED ECCSIZE1
R-0h R/W-0h
23 22 21 20 19 18 17 16
ECCSIZE1 RESERVED ECCSIZE0
R/W-0h R-0h R/W-0h
15 14 13 12 11 10 9 8
ECCSIZE0 RESERVED ECC9RESULT
SIZE
R/W-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
ECC8RESULT ECC7RESULT ECC6RESULT ECC5RESULT ECC4RESULT ECC3RESULT ECC2RESULT ECC1RESULT
SIZE SIZE SIZE SIZE SIZE SIZE SIZE SIZE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 7-135. GPMC_ECC_SIZE_CONFIG Register Field Descriptions

31-30 RESERVED R 0h
29-22 ECCSIZE1 R/W 0h Defines ECC size 1
0h = 2 Bytes
1h = 4 Bytes
2h = 6 Bytes
3h = 8 Bytes
FFh = 512 Bytes
21-20 RESERVED R 0h
19-12 ECCSIZE0 R/W 0h Defines ECC size 0
0h = 2 Bytes
1h = 4 Bytes
2h = 6 Bytes
3h = 8 Bytes
FFh = 512 Bytes
11-9 RESERVED R 0h
8 ECC9RESULTSIZE R/W 0h Selects ECC size for ECC 9 result register
0h = ECCSIZE0 selected

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Table 7-135. GPMC_ECC_SIZE_CONFIG Register Field Descriptions (continued)


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7.1.5.88 GPMC_ECC1_RESULT Register (offset = 200h) [reset = 0h]

GPMC_ECC1_RESULT is shown in Figure 7-134 and described in Table 7-136.
Figure 7-134. GPMC_ECC1_RESULT Register

31 30 29 28 27 26 25 24
RESERVED P2048O P1024O P512O P256O
23 22 21 20 19 18 17 16
P128O P64O P32O P16O P8O P4O P2O P1O
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED P2048E P1024E P512E P256E
7 6 5 4 3 2 1 0
P128E P64E P32E P16E P8E P4E P2E P1E
Table 7-136. GPMC_ECC1_RESULT Register Field Descriptions

31-28 RESERVED R 0h
27 P2048O R 0h Odd Row Parity bit 2048, only used for ECC computed on 512 Bytes
26 P1024O R 0h Odd Row Parity bit 1024
18 P4O R 0h Odd Column Parity bit 4
15-12 RESERVED R 0h
11 P2048E R 0h Even Row Parity bit 2048, only used for ECC computed on 512
Bytes
10 P1024E R 0h Even Row Parity bit 1024
2 P4E R 0h Even Column Parity bit 4

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Table 7-136. GPMC_ECC1_RESULT Register Field Descriptions (continued)


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31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

31-28 RESERVED R 0h
15-12 RESERVED R 0h
Bytes

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31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

31-28 RESERVED R 0h
15-12 RESERVED R 0h
Bytes

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7.1.5.91 GPMC_ECC4_RESULT Register (offset = 20Ch) [reset = 0h]


31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

31-28 RESERVED R 0h
15-12 RESERVED R 0h
Bytes

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31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

31-28 RESERVED R 0h
15-12 RESERVED R 0h
Bytes

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31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

31-28 RESERVED R 0h
15-12 RESERVED R 0h
Bytes

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31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

31-28 RESERVED R 0h
15-12 RESERVED R 0h
Bytes

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7.1.5.95 GPMC_ECC8_RESULT Register (offset = 21Ch) [reset = 0h]


31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

31-28 RESERVED R 0h
15-12 RESERVED R 0h
Bytes

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31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

31-28 RESERVED R 0h
15-12 RESERVED R 0h
Bytes

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7.1.5.97 GPMC_BCH_RESULT0_0 Register (offset = 240h) [reset = 0h]

GPMC_BCH_RESULT0_0 is shown in Figure 7-143 and described in Table 7-145.
Figure 7-143. GPMC_BCH_RESULT0_0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT0_0
R/W-0h
Table 7-145. GPMC_BCH_RESULT0_0 Register Field Descriptions

31-0 BCH_RESULT0_0 R/W 0h BCH ECC result, bits 0 to 31

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT1_0
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT2_0
R/W-0h


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7.1.5.100 GPMC_BCH_RESULT3_0 Register (offset = 24Ch) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT3_0
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT0_1
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT1_1
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT2_1
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT3_1
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT0_2
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT1_2
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT2_2
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT3_2
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT0_3
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT1_3
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT2_3
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT3_3
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT0_4
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT1_4
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT2_4
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT3_4
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT0_5
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT1_5
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT2_5
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT3_5
R/W-0h


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7.1.5.121 GPMC_BCH_RESULT0_6 Register (offset = 2A0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT0_6
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT1_6
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT2_6
R/W-0h


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7.1.5.124 GPMC_BCH_RESULT3_6 Register (offset = 2ACh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT3_6
R/W-0h


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7.1.5.125 GPMC_BCH_RESULT0_7 Register (offset = 2B0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT0_7
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT1_7
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT2_7
R/W-0h


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7.1.5.128 GPMC_BCH_RESULT3_7 Register (offset = 2BCh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT3_7
R/W-0h


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7.1.5.129 GPMC_BCH_SWDATA Register (offset = 2D0h) [reset = 0h]

GPMC_BCH_SWDATA is shown in Figure 7-175 and described in Table 7-177.
This register is used to directly pass data to the BCH ECC calculator without accessing the actual NAND
flash interface.
Figure 7-175. GPMC_BCH_SWDATA Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED BCH_DATA
R-0h R/W-0h
Table 7-177. GPMC_BCH_SWDATA Register Field Descriptions

31-16 RESERVED R 0h
15-0 BCH_DATA R/W 0h Data to be included in the BCH calculation.
Only bits 0 to 7 are taken into account, if the calculator is configured
to use 8 bits data (GPMC_ECC_CONFIG[7] ECC16B = 0).

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT4_0
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT5_0
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT6_0
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT4_1
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT5_1
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT6_1
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT4_2
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT5_2
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT6_2
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT4_3
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT5_3
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT6_3
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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7.2 OCMC-RAM
7.2.1 Introduction
7.2.1.1 OCMC-RAM Features

The on-chip memory controller consists of two separate modules that are OCP to memory wrappers. The
first wrapper is for a ROM; the second is for a RAM. Each wrapper has its own dedicated interface to the
L3 interconnect.
• 32- or 64-bit width
• Initial latency max 2 cycles (due to OCP to memory core wrapper).
• Multiple memory bank control based on address MSBs
• Full OCP IP 2.0 Burst support. No wait state.
7.2.1.2 Unsupported OCMC-RAM Features

For this device, the OCMC-RAM implementation does not support parity.

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7.2.2 Integration
This device includes a single instantiation of the on-chip memory controller interfacing to a single 64K
bank of RAM.
L3_FAST RAM Bank

OCMC0 (64K Total)
Interconnect
Control
Module
Figure 7-200. OCMC RAM Integration
7.2.2.1 OCMC RAM Connectivity Attributes

The general connectivity attributes for the OCMC RAM modules are summarized in Table 7-202.
Table 7-202. OCMC RAM Connectivity Attributes

Attributes Type
Clock Domain PD_PER_L3_GCLK
Interrupt Requests None
DMA Requests None
Physical Address L3 Fast slave port
7.2.2.2 OCMC RAM Clock and Reset Management

The OCMC module uses a single clock for the module and its OCP interface.
Table 7-203. OCMC RAM Clock Signals

prcm_ocmc_clock 200 MHz CORE_CLKOUTM4 pd_per_l3_gclk
Interface / Functional clock From PRCM
7.2.2.3 OCMC RAM Pin List

The OCMC RAM module does not include any external interface pins.

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7.3 EMIF
7.3.1 Introduction
7.3.1.1 Features
The general features of the EMIF module are as follows:
• 16-bit data path to external SDRAM memory
• One 128-bit OCPIP 2.2 interface
• Support for the following memory types:
– mDDR (LPDDR1)
– DDR2
– DDR3
External memory configurations supported:
• Memory device capacity
– Up to 1G Byte addressability
• Flexible bank/row/column/chip-select address multiplexing schemes
• Device driver strength feature for mobile DDR supported
• Supports following CAS latencies:
– DDR2 => 2, 3, 4, 5, 6, and 7
– DDR3 => 5, 6, 7, 8, 9, 10, and 11
– mDDR => 2, 3, and 4
• Supports following number of internal banks:
– DDR2 => 1, 2, 4, and 8
– DDR3 => 1, 2, 4, and 8
– mDDR => 1, 2, and 4
• Supports 256, 512, 1024, and 2048-word page sizes
• Supports burst length of 8 (sequential burst)
• Write/read leveling/calibration and data eye training in conjunction with DID
• Self Refresh and Power-Down modes for low power:
– Flexible OCP to DDR address mapping to support Partial Array Self Refresh in LPDDR1, DDR2
and DDR3.
– Temperature Controlled Self Refresh for LPDDR1 and DDR3 having on-chip temperature sensor.
• Periodic ZQ calibration for DDR3
• ODT on DDR2 and DDR3
• Prioritized refresh scheduling
• Programmable SDRAM refresh rate and backlog counter
• Programmable SDRAM timing parameters
• Big and little endian modes

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7.3.1.2 Unsupported EMIF Features

The following EMIF4DC module features are not supported in this device.
Table 7-204. Unsupported EMIF Features

Feature Reason
32-bit data Only 16 bits pinned out
Multiple DDR banks Only 1 CS/ODT pinned out
DDR2 CAS Latency 2 Not supported by DID
Hardware leveling Silicon bug. Must use software leveling procedure. See AM335x
ARM Cortex-A8 Microprocessors (MPUs) Silicon Errata
(literature number SPRZ360).

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7.3.2 Integration
7.3.2.1 EMIF Connectivity Attributes

The general connectivity attributes for the EMIF are shown in Table 7-205.
Table 7-205. EMIF Connectivity Attributes

Attributes Type
Clock Domain PD_PER_L3_GCLK (OCP)
PD_PER_EMIF_GCLK (Func)
Reset Signals POR_N
Interrupt Requests 1 interrupt to MPU Subsystem (DDRERR0)
DMA Requests None
Physical Address L3 Fast Slave Port
7.3.2.2 EMIF Clock Management

The EMIF4 OCP interface (ocp_clk) is clocked by the L3 Fast clock sourced from the Core PLL. The DDR
Command and Data macros are clocked by the DDR PLL. The PRCM divides this clock by two to create
the EMIF functional clock (m_clk).
The OCP and functional clocks may be asynchronous because synchronization is managed in the EMIF4
internal FIFO (EMIF4 is set in asynchronous mode).
Table 7-206. EMIF Clock Signals

Clock Signal Maximum Frequency Reference Source Comments
ocp_clk 200 MHz CORE_CLKOUTM4 pd_per_l3_gclk
(Interface clock) From PRCM
m_clk 200 MHz (1) DDR PLL CLKOUT / 2 pd_per_emif_gclk
(EMIF functional clock) From PRCM
cmd0_dfi_clk 400 MHz (1) DDR PLL CLKOUT clkout_po
From DDR PLL
cmd1_dfi_clk
cmd2_dfi_clk
data0_dfi_clk
data1_dfi_clk
(Macro clocks)
(1)
The maximum frequency depends on the type of DDR. See the maximum DDR frequency for your device in the device
datasheet AM335x Sitara Processors (literature number SPRS717).
7.3.2.3 EMIF Pin List

The EMIF/DDR external interface signals are shown in Table 7-207.
Table 7-207. EMIF Pin List

DDR_CK O Differential clock pair
DDR_NCK
DDR_CKE O Clock enable
DDR_CSn0 O Chip select
DDR_RASn O Row address strobe
DDR_CASn O Column address strobe
DDR_WEn O Write enable

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Table 7-207. EMIF Pin List (continued)

DDR_BA[2:0] O Bank address
DDR_A[15:0] O Row/column address
DDR_DQS[1:0] I/O Data strobes
DDR_DQSn[1:0] I/O Complimentary data strobes
DDR_DQM[1:0] O Data masks
DDR_D[15:0] I/O Data
DDR_ODT O On-die termination
DDR_RESETn O DDR device reset
DDR_VREF I I/O Voltage reference
DDR_VTP I VTP compensation pin

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7.3.3 Functional Description
7.3.3.1 Signal Descriptions

The DDR2/3/mDDR memory controller signals are shown in Figure 7-201 and described in Table 7-208.
The following features are included:
• The maximum width for the data bus (DDR_D[15:0]) is 16-bits
• The address bus (DDR_A[15:0]) is 16-bits wide with an additional 3 bank address pins (DDR_BA[2:0])
• Two differential output clocks (DDR_CK and DDR_nCK) driven by internal clock sources
• Command signals: Row and column address strobe (DDR_RASn and DDR_CASn), write enable
strobe
(DDR_WEn), data strobe (DDR_DQS[1:0] and DDR_DQSn[1:0]), and data mask (DDR_DQM[1:0]).
• One chip select signal (DDR_CSN0) and one clock enable signal (DDR_CKE)
• One on-die termination output signals (DDR_ODT).
Figure 7-201. DDR2/3/mDDR Memory Controller Signals
DDR_CLK
DDR_CLKn
DDR_CKE
DDR_WEn
DDR_CSN0
DDR_RASn
DDR_CASn
DDR_DQM[1:0]
DDR_DQS[1:0]
DDR_DQSn[1:0]
DDR_ODT
DDR_RST
DDR_BA[2:0]
DDR_A[15:0]
DDR_D[15:0]
DDR_VTP
DDR_RSTn
DDR_VREF
Table 7-208. DDR2/3/mDDR Memory Controller Signal Descriptions

Pin Description
DDR_D[15:0] Bidirectional data bus. Input for data reads and output for data writes.
DDR_A[15:0] External address output.
DDR_CSN0 Chip select output.
DDR_DQM[1:0] Active-low output data mask.
DDR_CLK/DDR_CLKn Differential clock outputs. All DDR2/3/mDDR interface signals are synchronous to these clocks.
DDR_CKE Clock enable. Used to select Power-Down and Self-Refresh operations.
DDR_CASn Active-low column address strobe.
DDR_RASn Active-low row address strobe.
DDR_WEn Active-low write enable.

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Table 7-208. DDR2/3/mDDR Memory Controller Signal Descriptions (continued)

Pin Description
DDR_DQS[1:0]/DDR_DQSn[1: Differential data strobe bidirectional signals. Edge-aligned inputs on reads and center-aligned
0] outputs on writes.
DDR_ODT On-die termination signal to external DDR2/3 SDRAM. ODT is not supported for mDDR.
DDR_BA[2:0] Bank-address control outputs.
Memory Controller reference voltage. This voltage must be supplied externally. See the device-
DDR_VREF
specific data manual for more details.
DDR_VTP DDR2/3/mDDR VTP Compensation Resistor Connection.
DDR_RESETn Reset output. Asynchronous reset for DDR3 devices.
7.3.3.2 Clock Control

DDR2/3/mDDR clock is derived directly from the DDR PLL’s VCO output. The frequency of DDR_CLK can
be determined by using the following formula:
DDR_CLK frequency = (DDRPLL input clock frequency x mulitplier)/((pre-divider+1)*post-divider)
The second output clock of the DDR2/3/mDDR memory controller DDR_CLKn, is the inverse of
DDR_CLK. You can change the muliplier, pre-divier and post-divider to get the desired DDR_CLK
frequency.
For detailed information on DDR PLL, see Section 8.1, Power Management and Clock Module (PRCM).
7.3.3.3 DDR2/3/mDDR Memory Controller Subsytem Overview

The DDR2/3/mDDR memory controller can gluelessly interface to most standard DDR2/3/mDDR SDRAM
devices and supports such features as self-refresh mode and prioritized refresh. In addition, it provides
flexibility through programmable parameters such as the refresh rate, CAS latency, and many SDRAM
timing parameters. The DDR2/3/mDDR subsystem consists of the following:
• DDR2/3/mDDR memory controller
• Command macro
• Data macro
• VTP controller macro
• IOs for DQS gate
The subsystem supports JEDEC standard compliant DDR2/DDR3 and mDDR(LPDRR1)devices. It does
not support CAS latency of 2 for DDR2 due to data and command macro limitations. It supports a 128-bit
wide OCP interface on the core side for programmability. The subsystem can be used to connect to 16-bit
memory devices.
Figure 7-202 shows the DDR2/3/mDDR subsystem block diagram.

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Figure 7-202. DDR2/3/mDDR Subsystem Block Diagram

cmd/addr
To DDR
Command Macros
128-bit
OCP DDR2/3/mDDR
Memory
data[15:8] to/from DDR
Controller data
fifo_we_out
Data Macro 1
fifo_we_in IO 1
data[7:0] to/from DDR

data
fifo_we_out
Data Macro 0
fifo_we_in IO 0
p/n
VTP Macro
Where
fifo_we_out = DQS enable output for timing match between DQS and system (Memory) clock.
fifo_we_in = DQS enable input for timing match between DQS and system (Memory) clock.
7.3.3.3.1 DDR2/3/mDDR Memory Controller Interface

To move data efficiently from on-chip resources to external DDR2/3/mDDR SDRAM device, the
DDR2/3/mDDR memory controller makes use of a command FIFO, a write data FIFO, a return command
FIFO, and two Read Data FIFOs. Purpose of each FIFO is described below.
Figure 7-203 shows the block diagram of the DDR2/3/mDDR memory controller FIFOs. Commands, write
data, and read data arrive at the DDR2 memory controller parallel to each other. The same peripheral bus
is used to write and read data from external memory as well as internal memory-mapped registers.

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Figure 7-203. DDR2/3/mDDR Memory Controller FIFO Block Diagram

Command FIFO
OCP Command to memory

Command
Command
Scheduler
Interface
Write Data FIFO
OCP Write data to memory

Data
Write Data
Scheduler
Interface
Return Command FIFO
Memory
Mapped
Registers
OCP
Register Read Data FIFO
Return
SDRAM Read Data FIFO

Interface
Read data from SDRAM
Control
Data
The command FIFO stores all the commands coming in on the OCP command interface.
The Write Data FIFO stores the write data for all the write transactions coming in on the OCP write data
interface.
The Return Command FIFO stores all the return transactions that are to be issued to the OCP return
interface. These include the write status return and the read data return commands.
There are two Read Data FIFOs that store the read data to be sent to the OCP return interface. One Read
Data FIFO stores read data from the memory mapped registers and other Read Data FIFO stores read
data from external memory.
7.3.3.3.2 Data Macro

The data macro consists of 8 data channels, one pair of complementary strobes (one pair for 8 bits of
data), and one data mask channel (one for 8 bits of data).
The data macros consists of PHY Data Macro, DLLs and IOs integrated into a macro.

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The data macro is a bidirectional interface. It is used to transmit data from the memory controller to the
external memory chip during a write operation and receive data from memory and transmit it to the
memory controller during a read operation.
During a write operation, the data macro translates 32/16-bit words from memory controller to 8-bit words
and transmits them at double the bit rate to the memory along with the strobe. The strobe is center-
aligned to the data. Data can be prevented from writing to the memory using data mask signal.
During a read operation, the data macro receives 8-bit DDR data along with the strobe and converts it to
32/16- bit words and transmits them to the memory controller along with the read-valid signals.
7.3.3.3.3 Command Macro

It consists of PHY Command Macro, DLLs and the IOs integrated together. The command macro acts as
a unidirectional macro that transmits address and control bits from memory controller to the memory chip.
The clocks DDR_CLK and DDR_CLKn are used by the memory to register the command and address
transmitted on the transmit channels. All address and control signals are transmitted clock-centered with
respect to DDR_CLK and DDR_CLKn. The memory, on the positive edge of DDR_CLK and the negative
edge of DDR_CLKn, samples all address and control signals.
7.3.3.3.4 VTP Controller Macro

The VTP controller macro evaluates silicon performance at current voltage, temperature, and process
(VTP) to enable IO drivers to set constant predetermined output driver impedance. The controller operates
by comparing driver impedances to the external reference resistor and adjusting driver impedance to
obtain an impedance match. VTP Controller supports the following features:
• The VTP controller generates information regarding the Voltage, temperature, and process(VTP) on a
chip to be shared with the device's IO drivers
• Requires a Clock input from the core running at 20MHz or less
• 56 Clock cycles are needed to guarantee the VTP outputs are initially set after reset is removed
• Can be used in static or dynamic update mode of operation
• The VTP controller has internal noise filtering which allows it to control spurious update requests due
to noise
Impedance of the drivers and terminations must be updated often even while in operation. In such
scenarios where Voltage and Temperature are variables VTP macro can be configured in dynamic update
mode. In contrast, static mode of operation does not allow dynamic calibration of IO impedance, and
hence consumes lesser power compared to dynamic update mode.
It is possible that under noisy conditions, dynamic update controller can generate too frequent update
requests. Noise can cause the controller to request a change in the impedance that can again be quickly
reversed on subsequent clock cycles. To prevent the controller from making excessive numbers of
impedance changes, a digital filter is included which can be configured to regulate the update rate. For
example if the user configures the filter value as F2=0,F1=1 and F0=1, then an impedance update will be
performed only if four successive update requests are generated from the VTP controller. It is
recommended to use a filter value of 011'b.
Table 7-209 shows the configuration details of the digital filter.
Table 7-209. Digital Filter Configuration

F2 F1 F0 Description
0 0 0 Off
0 0 1 Update on 2 consecutive update requests

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Table 7-209. Digital Filter Configuration (continued)

F2 F1 F0 Description
7.3.3.3.5 DQS-Gate IOs

To effectively model the I/O delay on the DQS gating signal during a read request (the DQS receiver and
the CLK driver I/Os), the signal is expected to be looped on a single I/O connecting fifo_we_in to
fifo_we_out. The board and memory delay, being fairly constant across PTV variations, are calibrated
within the IDID using a compensated delay line. The loop-back is done at the die level without bringing the
signals out to the package level. Each Data Macro supports delay compensation independent of each
other.
The data and command macros are responsible for System level flight time compensation. The following
controls are supported by the DDR2/3/mDDR controller Sub System.
• Aligning DDR_DQS w.r.t DDR_CLK during Write Cycle: For DDR3 operation, initiate the write leveling
state machine on each rank in turn to capture the proper delay settings to align DDR_DQS with
DDR_CLK clock for each memory chip. If one wants to do this in a manual way one can write to the
control register that controls the delay of DDR_DQS vs DDR_CLK Clock position. To produce a given
amount of skew to center the DDR_DQS vs. Clock at the SDRAM the following register can be
programmed.
Data Macro 0/1 Write DQS Slave Ratio Register=256 x ([command delay] – [DDR_DQS delay]) /
DDR_CLK Clock period.
• Aligning ADDR/CMD w.r.t DDR_CLK
• Aligning DDR_DQ[15:0] w.r.t DDR_DQS during Write Operation
• Offset DDR_D[15:0] w.r.t DDR_DQS during Read Operation
• Align FIFO WE Window
7.3.3.4 Address Mapping

The DDR2/3/mDDR memory controller views external DDR2/3/mDDR SDRAM as one continuous block of
memory. This statement is true regardless of the number of memory devices located on the chip select
space. The DDR2/3/mDDR memory controller receives DDR2/3/mDDR memory access requests along
with a 32-bit logical address from the rest of the system. In turn, DDR2/3/mDDR memory controller uses
the logical address to generate a row/page, column, and bank address for the DDR2/3/mDDR SDRAM.
The number of column, row and bank address bits used is determined by the IBANK, RSIZE and
PAGESIZE fields (see Table 7-210). The DDR2/3/mDDR memory controller uses up to 16 bits for the
row/page address.
Table 7-210. IBANK, RSIZE and PAGESIZE Fields Information

Bit Field Bit Value Bit Description
Defines the number of address lines to be connected to DDR2/3/mDDR memory device
0 9 row bits
1h 10 row bits
2h 11 row bits
RSIZE 3h 12 row bits
4h 13 row bits
5h 14 row bits
6h 15 row bits
7h 16 row bits

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Table 7-210. IBANK, RSIZE and PAGESIZE Fields Information (continued)

Bit Field Bit Value Bit Description
Defines the page size of each page of the external DDR2/3/mDDR memory device
0 256 words (requires 8 column address bits)
PAGESIZE 1h 512 words (requires 9 column address bits)
2h 1024 words (requires 10 column address bits)
3h 2048 words (requires 11 column address bits)
Defines the number of internal banks on the external DDR2/3/mDDR memory device
0 1 bank
IBANK 1h 2 banks
2h 4 banks
3h 8 banks
Defines the number of DDR2/3/mDDR memory controller chip selects
EBANK 0 CS0 only
1h Reserved
When addressing SDRAM, if the REG_IBANK_POS field in the SDRAM Config register is set to 0, and the
REG_EBANK_POS field in the SDRAM Config 2 register is also set to 0, the DDR2/3/mDDR memory
controller uses the three fields, IBANK, EBANK and PAGESIZE in the SDRAM Config register to
determine the mapping from source address to SDRAM row, column, bank, and chip select. If the
REG_IBANK_POS field in the SDRAM Config register is set to 1, 2, or 3, or the REG_EBANK_POS field
in the SDRAM Config 2 register is set to 1, the DDR2/3/mDDR memory controller uses the 4 fields -
IBANK, EBANK, PAGESIZE, and ROWSIZE in the SDRAM Config register to determine the mapping from
source address to SDRAM row, column, bank, and chip select. In all cases the DDR2/3/mDDR memory
controller considers its SDRAM address space to be a single logical block regardless of the number of
physical devices or whether the devices are mapped across 1 or 2 DDR2/3/mDDR memory controller chip
selects.
7.3.3.4.1 Address Mapping when REG_IBANK_POS=0 and REG_EBANK_POS=0

For REG_IBANK_POS=0 and REG_EBANK_POS=0, the effect of address mapping scheme is that as the
source address increments across DDR2/3/mDDR memory device page boundaries, the DDR2/3/mDDR
controller moves onto the same page in the next bank in the current device DDR_CSn[0]. This movement
along the banks of the current proceeds to the same page in the next device(if EBANK=1, DDR_CSn[1])
and proceeds through the same page in all its banks before moving over to the next page in the first
device(DDR_CSn[0]). The DDR2/3/mDDR controller exploits this traversal across internal banks and chip
selects while remaining on the same page to maximize the number of open DDR2/3/mDDR memory
device banks within the overall DDR2/3/mDDR memory device space.
Thus, the DDR2/3/mDDR controller can keep a maximum of 16 banks (8 internal banks across 2 chip
selects) open at a time, and can interleave among all of them.
Table 7-211. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=0 and
REG_EBANK_POS=0
Logical Address
Row Address Chip Select Bank Address Column Address
# of bits defined by EBANK of # of bits defined by IBANK of # of bits defined by PAGESIZE
SDRCR SDRCR of SDRCR
16 bits EBANK=0 => 0 bits IBANK=0 => 0 bits PAGESIZE=0 => 8 bits
EBANK=1 => 1 bit IBANK=1 => 1 bit PAGESIZE=1 => 9 bits
IBANK=2 => 2 bits PAGESIZE=2 => 10 bits
IBANK=3 => 3 bits PAGESIZE=3 => 11 bits

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7.3.3.4.2 Address Mapping when REG_IBANK_POS = 1 and REG_EBANK_POS = 0

For REG_IBANK_POS = 1 and REG_EBANK_POS = 0, the interleaving of banks within a device (per chip
select) is limited to 4 banks. However, it can still interleave banks between the two chip selects. Thus, the
DDR2/3/mDDR controller can keep a maximum of 16 banks (8 internal banks across 2 chip selects) open
at a time, but can only interleave among eight of them.
REG_EBANK_POS=0
Logical Address
Bank Address[2] Row Address Chip Select Bank Address[1:0] Column Address
# of bits defined by # of bits defined by # of bits defined by # of bits defined by # of bits defined by
IBANK of SDRCR RSIZE of SDRCR EBANK of SDRCR IBANK of SDRCR PAGESIZE of SDRCR
IBANK=0 => 0 bits RSIZE=0 => 9 bits EBANK=0 => 0 bits IBANK=0 => 0 bits PAGESIZE=0 => 8 bits
IBANK=1 => 0 bits RSIZE=1 => 10 bits EBANK=1 => 1 bit IBANK=1 => 1 bit PAGESIZE=1 => 9 bits
IBANK=2 => 0 bits RSIZE=2 => 11 bits IBANK=2 => 2 bits PAGESIZE=2 => 10 bits
IBANK=3 => 1 bit RSIZE=3 => 12 bits IBANK=3 => 3 bits PAGESIZE=3 => 11 bits
RSIZE=4 => 13 bits
RSIZE=5 => 14 bits
RSIZE=6 => 15 bits
RSIZE=7 => 16 bits
7.3.3.4.3 Address Mapping when REG_IBANK_POS=2 and REG_EBANK_POS = 0

For REG_IBANK_POS=2 and REG_EBANK_POS = 0, the interleaving of banks within a device (per chip
select) is limited to 2 banks. However, it can still interleave banks between the two chip selects. Thus, the
DDR2/3/mDDR controller can keep a maximum of 16 banks (eight internal banks across 2 chip selects)
open at a time, but can only interleave among four of them.
REG_EBANK_POS=0
Logical Address
Bank Address[2:1] Row Address Chip Select Bank Address[0] Column Address
IBANK of SDRCR RSIZE of SDRCR EBANK of SDRCR IBANK of SDRCR PAGESIZE of SDRCR
IBANK=0 => 0 bits RSIZE=0 => 9 bits EBANK=0 => 0 bits IBANK=0 => 0 bits PAGESIZE=0 => 8 bits
IBANK=1 => 0 bits RSIZE=1 => 10 bits EBANK=1 => 1 bit IBANK=1 => 1 bit PAGESIZE=1 => 9 bits
IBANK=2 => 1 bit RSIZE=2 => 11 bits IBANK=2 => 1 bit PAGESIZE=2 => 10 bits
IBANK=3 => 2 bits RSIZE=3 => 12 bits IBANK=3 => 1 bit PAGESIZE=3 => 11 bits
RSIZE=4 => 13 bits
RSIZE=5 => 14 bits
RSIZE=6 => 15 bits
RSIZE=7 => 16 bits
7.3.3.4.4 Address Mapping when REG_IBANK_POS= 3 and REG_EBANK_POS = 0

For REG_IBANK_POS= 3 and REG_EBANK_POS = 0, the DDR2/3/mDDR controller cannot interleave
banks within a device (per chip select). However, it can still interleave banks between the two chip selects.
Thus, the DDR2/3/mDDR controller can keep a maximum of 16 banks (8 internal banks across 2 chip
selects) open at a time, but can only interleave among two of them.

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REG_EBANK_POS=0
Logical Address
Bank Address Row Address Chip Select Column Address
# of bits defined by IBANK of # of bits defined by RSIZE of # of bits defined by EBANK of # of bits defined by PAGESIZE
SDRCR SDRCR SDRCR of SDRCR
IBANK=0 => 0 bits RSIZE=0 => 9 bits EBANK=0 => 0 bits PAGESIZE=0 => 8 bits
IBANK=1 => 1 bit RSIZE=1 => 10 bits EBANK=1 => 1 bit PAGESIZE=1 => 9 bits
IBANK=2 => 2 bits RSIZE=2 => 11 bits PAGESIZE=2 => 10 bits
RSIZE=4 => 13 bits
RSIZE=5 => 14 bits
RSIZE=6 => 15 bits
RSIZE=7 => 16 bits

For REG_IBANK_POS = 0 and REG_EBANK_POS = 1, the DDR2/3/mDDR memory controller interleaves
among all the banks within a device (per chip select). However, the DDR2/3/mDDR memory controller
cannot interleave banks between the two chip selects. Thus, the DDR2/3/mDDR memory controller can
keep a maximum of 16 banks (8 internal banks across 2 chip selects) open at a time, but can only
interleave among 8 of them.
REG_EBANK_POS=1
Logical Address
Chip Select Row Address Bank Address Column Address
# of bits defined by EBANK of # of bits defined by RSIZE of # of bits defined by IBANK of # of bits defined by PAGESIZE
EBANK=0 => 0 bits RSIZE=0 => 9 bits IBANK=0 => 0 bits PAGESIZE=0 => 8 bits
EBANK=1 => 1 bit RSIZE=1 => 10 bits IBANK=1 => 1 bit PAGESIZE=1 => 9 bits
RSIZE=2 => 11 bits IBANK=2 => 2 bits PAGESIZE=2 => 10 bits
RSIZE=3 => 12 bits IBANK=3 => 3 bits PAGESIZE=3 => 11 bits
RSIZE=4 => 13 bits
RSIZE=5 => 14 bits
RSIZE=6 => 15 bits
RSIZE=7 => 16 bits

select) is limited to 4 banks. Also, the DDR2/3/mDDR memory controller cannot interleave banks between
the two chip selects. Thus, the DDR2/3/mDDR memory controller can keep a maximum of 16 banks (8
internal banks across 2 chip selects) open at a time, but can only interleave among four of them.
REG_EBANK_POS = 1
Logical Address
Chip Select Bank Address[2] Row Address Bank Address[1:0] Column Address
EBANK of SDRCR IBANK of SDRCR RSIZE of SDRCR IBANK of SDRCR PAGESIZE of SDRCR
EBANK=0 => 0 bits IBANK=0 => 0 bits RSIZE=0 => 9 bits IBANK=0 => 0 bits PAGESIZE=0 => 8 bits

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REG_EBANK_POS = 1 (continued)
Logical Address
Chip Select Bank Address[2] Row Address Bank Address[1:0] Column Address
EBANK=1 => 1 bit IBANK=1 => 0 bits RSIZE=1 => 10 bits IBANK=1 => 1 bit PAGESIZE=1 => 9 bits
IBANK=2 => 0 bits RSIZE=2 => 11 bits IBANK=2 => 2 bits PAGESIZE=2 => 10 bits
IBANK=3 => 1 bit RSIZE=3 => 12 bits IBANK=3 => 2 bits PAGESIZE=3 => 11 bits
RSIZE=4 => 13 bits
RSIZE=5 => 14 bits
RSIZE=6 => 15 bits
RSIZE=7 => 16 bits

select) is limited to 2 banks. Also, the DDR2/3/mDDR memory controller cannot interleave banks between
the two chip selects. Thus, the DDR2/3/mDDR memory controller can keep a maximum of 16 banks (8
internal banks across 2 chip selects) open at a time, but can only interleave among two of them.
REG_EBANK_POS = 1
Logical Address
Chip Select Bank Address[2:1] Row Address Bank Address[0] Column Address
EBANK of SDRCR IBANK of SDRCR RSIZE of SDRCR IBANK of SDRCR PAGESIZE of SDRCR
EBANK=0 => 0 bits IBANK=0 => 0 bits RSIZE=0 => 9 bits IBANK=0 => 0 bits PAGESIZE=0 => 8 bits
EBANK=1 => 1 bit IBANK=1 => 0 bits RSIZE=1 => 10 bits IBANK=1 => 1 bit PAGESIZE=1 => 9 bits
IBANK=2 => 1 bit RSIZE=2 => 11 bits IBANK=2 => 1 bit PAGESIZE=2 => 10 bits
IBANK=3 => 2 bits RSIZE=3 => 12 bits IBANK=3 => 1 bit PAGESIZE=3 => 11 bits
RSIZE=4 => 13 bits
RSIZE=5 => 14 bits
RSIZE=6 => 15 bits
RSIZE=7 => 16 bits

For REG_IBANK_POS = 3 and REG_EBANK_POS = 1, the DDR2/3/mDDR memory controller cannot
interleave banks within a device (per chip select) or between the two chip selects. Thus, the
DDR2/3/mDDR memory controller can keep a maximum of 16 banks (8 internal banks across two chip
selects) open at a time, but cannot interleave among of them.
REG_EBANK_POS=1
Logical Address
Chip Select Bank Address Row Address Column Address
# of bits defined by EBANK of # of bits defined by IBANK of # of bits defined by RSIZE of # of bits defined by PAGESIZE
EBANK=0 => 0 bits IBANK=0 => 0 bits RSIZE=0 => 9 bits PAGESIZE=0 => 8 bits
EBANK=1 => 1 bit IBANK=1 => 1 bit RSIZE=1 => 10 bits PAGESIZE=1 => 9 bits

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REG_EBANK_POS=1 (continued)
Logical Address
Chip Select Bank Address Row Address Column Address
RSIZE=4 => 13 bits
RSIZE=5 => 14 bits
RSIZE=6 => 15 bits
RSIZE=7 => 16 bits
Since the DDR2/3/mDDR memory controller interleaves among less number of banks when
IBANK_POS!= 0 or EBANK_POS= 1, these cases are lower in performance than the IBANK_POS= 0
case. Thus these cases are only recommended to be used along with partial array self-refresh where
performance can be traded off for power savings.
7.3.3.5 Performance Management
7.3.3.5.1 Command Ordering and Scheduling

The DDR2/3/mDDR memory controller performs command re-ordering and scheduling in an attempt to
achieve efficient transfers with maximum throughput. The goal is to maximize the utilization of the data,
address, and command buses while hiding the overhead of opening and closing DDR2/3/mDDR SDRAM
rows. Command re-ordering takes place within the command FIFO.
The DDR2/3/mDDR memory controller examines all the commands stored in the command FIFO to
schedule commands to the external memory. All commands from same master will complete in order,
regardless of the master priority. The memory controller does not guarantee ordering between commands
from different masters. However, the memory controller will maintain data coherency. Therefore, the
memory controller will block a command, regardless of master priority, if that command is to the same
block address (2048 bytes) as an older command. Thus, the memory controller might have one or more
pending read or write for each master. Among all pending reads, the memory controller selects all reads
that have their corresponding SDRAM banks already open. Similarly, among all pending writes, the
memory controller selects all writes that have their corresponding SDRAM banks already open.
As a result of the above reordering, at any point of time the memory controller might have several pending
reads and writes that have their corresponding banks open. The memory controller then selects the
highest priority read from pending reads, and the highest priority write from pending writes. If two or more
commands have the highest priority, the memory controller selects the oldest command. As a result, the
memory controller might now have a final read and a final write command. The memory controller will pick
either the read or the write command depending on the value programmed in the Read Write Execution
Threshold register. The memory controller will keep executing reads until the read threshold is met and
then switch to executing writes. The memory controller will then keep executing writes until the write
threshold is met and then switch back to executing reads. The memory controller will satisfy meeting the
threshold values only if that type of command is available for execution, otherwise it will switch to the other
type. Similarly, the memory controller will satisfy meeting the threshold value only if the FIFOs for that type
have space (Read Data FIFO for reads and Write Status FIFO for writes), otherwise it will switch to the
other type.
The memory controller completes executing an OCP command before it switches to another command.
All the accesses to an SDRAM are pipe-lined to maximize the external bus utilization. In other words
accesses to an SDRAM are issued back to back such that there are minimum idle cycles between any two
accesses. This includes the scheduling listed above to minimize the overhead of opening and closing of
SDRAM banks. All of these is done while fulfilling the access timing requirements of an SDRAM.
Besides commands received from on-chip resources, the DDR2/3/mDDR memory controller also issues
refresh commands. The DDR2/3/mDDR memory controller attempts to delay refresh commands as long
as possible to maximize performance while meeting the SDRAM refresh requirements. As the
DDR2/3/mDDR memory controller issues read, write, and refresh commands to DDR2/3/mDDR SDRAM
device, it follows the following priority scheme:

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1. (Highest priority) SDRAM refresh request due to Refresh Must level of refresh urgency reached (see
Section 7.3.3.5.5).
2. Request for a read or a write.
3. SDRAM Activate commands.
4. SDRAM Deactivate commands.
5. SDRAM Deep Power-Down request.
6. SDRAM clock stop or Power-Down request.
7. SDRAM refresh request due to Refresh May or Release level of refresh urgency reached (Refer
Section Refresh Scheduling)
8. (Lowest priority) SDRAM self-refresh request.
7.3.3.5.2 Command Starvation

The reordering and scheduling rules listed above may lead to command starvation, which is the
prevention of certain commands from being processed by the DDR2/3/mDDR memory controller.
Command starvation results from the following conditions:
• A continuous stream of high-priority read commands can block a low-priority write command
• A continuous stream of DDR2/3/mDDR SDRAM commands to a row in an open bank can block
commands to the closed row in the same bank.
To avoid these conditions, the DDR2/3/mDDR memory controller can momentarily raise the priority of the
oldest command in the command FIFO after a set number of transfers have been made. The
REG_COS_COUNT_1,REG_COS_COUNT_2 field in the Interface Configuration Register
(OCP_CONFIG) sets the number of the transfers that must be made before the DDR2/3/mDDR memory
controller will raise the priority of the oldest command. See Class of Service (COS) section for more
details.
NOTE: Leaving the REG_COS bits at their default value (FFh) in the Interface Configuration register
(OCP_CONFIG) disables this feature of the DDR2/3/mDDR memory controller. This means
commands can stay in the command FIFO indefinitely. Therefore, these bits should be set to
FEh immediately following reset to enable this feature with the highest level of allowable
memory transfers. It is suggested that system-level prioritization be set to avoid placing high-
bandwidth masters on the highest priority levels. These bits can be left as FEh unless
advanced bandwidth/prioritization control is required.
7.3.3.5.3 Possible Race Condition

A race condition may exist when certain masters write data to the DDR2/3/mDDR memory controller. For
example, if master A passes a software message via a buffer in DDR2/3/mDDR memory and does not
wait for indication that the write completes, when master B attempts to read the software message it may
read stale data and therefore receive an incorrect message. In order to confirm that a write from master A
has landed before a read from master B is performed, master A must wait for the write completion status
from the DDR2/3/mDDR memory controller before indicating to master B that the data is ready to be read.
If master A does not wait for indication that a write is complete, it must perform the following workaround:
1. Perform the required write.
2. Perform a dummy write to the DDR2 memory controller module ID and revision register.
3. Perform a dummy read to the DDR2 memory controller module ID and revision register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3.
The completion of the read in step 3 ensures that the previous write was done.
For a list of the master peripherals that need this workaround, see the device-specific data sheet.

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7.3.3.5.4 Class of Service (COS)

The commands in the Command FIFO can be mapped to 2 classes of service namely 1 and 2. The
mapping of commands to a particular class of service can be done based on the priority or the connection
ID.
The mapping based on priority can be done by setting the appropriate values in the Priority to Class of
Service Mapping register (PRI_COS_MAP).
The mapping based on connection ID can be done by setting the appropriate values of connection ID and
the masks in the Connection ID to Class of Service Mapping registers(CONNID_COS_1_MAP and
CONNID_COS_2_MAP).
There are 3 connection ID and mask values that can be set for each class of service. In conjunction with
the masks, each class of service can have a maximum of 144 connection IDs mapped to it. For example,
a connection ID value of 0xFF along with a mask value of 0x3 will map all connection IDs from 0xF8 to
0xFF to that particular class of service.
Each class of service has an associated latency counter (REG_COS_COUNT). The value of this counter
can be set in the Interface Configuration Register (OCP_CONFIG). When the latency counter for a
command expires, i.e., reaches the value programmed for the class of service that the command belongs
to, that command will be the one that is executed next. If there are more than one commands that have
expired latency counters, the command with the highest priority will be executed first. One exception to
this rule is, if the oldest command in the queue has an expired reg_pr_old_count, that command will be
executed first irrespective of priority or class of service. This is done to prevent a continuous block effect.
The connection ID mapping allows the same connection ID to be put in both class of service 1 and 2.
Also, a transaction might belong to one class of service if viewed by connection ID and might belong to
another class of service if viewed by priority. In these cases, the command will belong to both class of
service. The DDR2/3/mDDR memory controller will try executing the command as soon as possible, when
the smaller of the two counters ( REG_COS_COUNT_1 OR REG_COS_COUNT_2) expire.
7.3.3.5.5 Refresh Scheduling

The DDR2/3/mDDR memory controller issues autorefresh (REFR) commands to DDR2/3/mDDR SDRAM
devices at a rate defined in the refresh rate (REFRESH_RATE) bit field in the SDRAM refresh control
register (SDRFC). A refresh interval counter is loaded with the value of the REFRESH_RATE bit field and
decrements by 1 each cycle until it reaches zero. Once the interval counter reaches zero, it reloads with
the value of the REFRESH_RATE bit. Each time the interval counter expires, a refresh backlog counter
increments by 1. Conversely, each time the DDR2/3/mDDR memory controller performs a REFR
command, the backlog counter decrements by 1. This means the refresh backlog counter records the
number of REFR commands the DDR2/3/mDDR memory controller currently has outstanding.
The DDR2/3/mDDR memory controller issues REFR commands based on the level of urgency. The level
of urgency is defined below. Whenever the refresh level of urgency is reached, the DDR2/3/mDDR
memory controller issues a REFR command before servicing any new memory access requests.
Following a REFR command, the DDR2/3/mDDR memory controller waits T_RFC cycles, defined in the
SDRAM timing 1 register (SDRTIM1), before rechecking the refresh urgency level.
The refresh counters do not operate when the SDRAM memory is in self-refresh mode.
Table 7-219. Refresh Modes

Urgency Level Description
Backlog count is greater than 0. Indicates there is a backlog of REFR commands, when the DDR2/3/mDDR
Refresh May
memory controller is not busy it will issue the REFR command.
Backlog count is greater than 4. Indicates that the refresh backlog of REFR commands is getting high and
Refresh Release
when DDR2/3/mDDR memory controller is not busy it should issue the REFR command.
Backlog count is greater than 7. Indicates that the refresh backlog of REFR commands is getting excessive
Refresh Must and DDR2/3/mDDR memory controller should perform an auto refresh cycle before servicing any new
memory access requests.

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The DDR2/3/mDDR memory controller starts servicing new memory accesses after Refresh Release level
is cleared. If any of the commands in the Command FIFO have class of service latency counters that are
expired, the DDR2/3/mDDR memory controller will not wait for Refresh Release level to be cleared but will
only perform one refresh command and exit the refresh state.
7.3.3.5.6 Performance Counter Configuration

Table 7-220 shows the possible filter configurations for the two performance counters (REG_CNTR1_CFG
and REG_CNTR2_CFG). These filter configurations can be used in conjunction with an OCP connection
ID and/or an external chip select to obtain performance statistics for a particular OCP master and/or an
external chip select.
Table 7-220. Filter Configurations for Performance Counters

cntrN_cfg (1) cntrN_region_en cntrN_mconnid_en Description
0x0 0x0 0x0 or 0x1 Count total SDRAM accesses.
0x1 0x0 0x0 or 0x1 Count total SDRAM activations.
0x2 0x0 or 0x1 0x0 or 0x1 Count total reads.
0x3 0x0 or 0x1 0x0 or 0x1 Count total writes.
Count number of DDR clock cycles OCP
0x4 0x0 0x0
Command FIFO is full.
0x5 0x0 0x0
Write Data FIFO is full.
0x6 0x0 0x0
Read Data FIFO is full.
0x7 0x0 0x0
Return Command FIFO is full.
0x8 0x0 or 0x1 0x0 or 0x1 Count number of priority elevations.
Count number of DDR clock cycles that a
0x9 0x0 0x0
command was pending.
Count number of DDR clock cycles for
0xA 0x0 0x0 which the memory data bus was
transferring data.
0xB - 0xF 0x0 0x0 Reserved for future use.
(1)
When MReqDebug is set to a 1 for a particular OCP command, the performance counters will not be incremented for that
particular command if the cntrN_cfg values are equal to 0x0, 0x1, 0x2, 0x3, or 0xA.
7.3.3.6 SDRAM Initialization
7.3.3.6.1 DDR2 Initialization

On coming out of reset, if the reg_sdram_type field in the SDRAM Config register is equal to 2 and the
reg_initref_dis bit in the SDRAM Refresh Control register is set to 0, the EMIF performs a DDR2 SDRAM
initialization sequence as follows:
1. Drives pad_cke_o low.
2. After 16 SDRAM refresh rate intervals, issues a NOP command with pad_cke_o held high. The
SDRAM refresh rate is as defined in the reg_refresh_rate field description (see description of SDRAM
Refresh Control register).
3. Issues a PRECHARGE command with pad_a_o[10] held high to indicate all banks.
4. Issues a LOAD MODE REGISTER command to the extended mode register 2 (pad_ba_o[2:0] = 0x2)
with pad_a_o[15:0] set as follows:
Bits Value Description

pad_a_o[15:8] 0x0 Reserved
pad_a_o[7] reg_srt Self-refresh temperature range from SDRAM Refresh Control register

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pad_a_o[3] 0x0 DCC disable
pad_a_o[2:0] reg_pasr Partial array self-refresh from SDRAM Refresh Control register
with pad_a_o[15:0] = 0x0.
with the pad_a_o bits set as follows:

pad_a_o[12] 0x0 Output buffer enabled
pad_a_o[11] 0x0 RDQS disable
pad_a_o[10] !reg_ddr2_ddqs Differential DQS enable value from SDRAM Config register
pad_a_o[9:7] 0x0 Exit OCD calibration mode
pad_a_o[6] reg_ddr_term[1] DDR2 termination resistor value from SDRAM Config register
pad_a_o[5:3] 0x0 Additive latency = 0
pad_a_o[1] reg_sdram_drive SDRAM drive strength from SDRAM Config register
pad_a_o[0] 0x0 Enable DLL
7. Issues a LOAD MODE REGISTER command to the mode register (pad_ba_o[2:0] = 0x0) with the
pad_a_o bits set as follows:

pad_a_o[12] 0x0 Fast exit active power-down exit time
pad_a_o[11:0] reg_t_wr Write recovery for auto precharge from SDRAM Timing 1 register
pad_a_o[8] 0x1 DLL reset
pad_a_o[7] 0x0 Normal mode
pad_a_o[6:4] reg_cl[2:0] CAS latency from SDRAM Config register
pad_a_o[3] 0x0 Sequential burst type
pad_a_o[2:0] 0x3 Burst length of 8
8. After 267 clock cycles, issues a PRECHARGE command with pad_a_o[10] held high to indicate all
banks.
9. After 2 AUTO REFRESH commands, issues a LOAD MODE REGISTER command to the mode
register (pad_ba_o[2:0] = 0x0) with the pad_a_o bits set as follows:

pad_a_o[15:9] Equal to step 7
pad_a_o[8] 0x0 DLL not reset

pad_a_o[9:7] 0x7 Default OCD calibration

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with the pad_a_o bits equal to step 6.
12. If the reg_ddr_disable_dll bit in the SDRAM Config register is 1, issues a LOAD MODE REGISTER
command to the extended mode register 1 (pad_ba_o[2:0] = 0x1) with the pad_a_o bits, set as follows:

pad_a_o[0] 0x1 Disable DLL
13. The EMIF enters its idle state.

The EMIF also performs the initialization sequence whenever the SDRAM Config register is written. In this
case, the EMIF starts at step 3.
The LOAD MODE REGISTER command may be referred to as MODE REGISTER SET command in
some DDR2 datasheets. The EMIF does not perform any transactions until the DDR2 initialization
sequence is complete.
The reg_refresh_rate value at reset is config_refresh_def_val port value. When the EMIF comes out of
reset, the delay time in step 2 resulting from the 16 refresh rate intervals + 8 cycles is approximately 16 *
reg_refresh_rate / input frequency. The user must tie off the config_refresh_def_val port with a correct
value to meet the typical DDR2 device specified delay time of 200 us between power-up and the
application of the PRECHARGE all command.
7.3.3.6.2 DDR3 Initialization

reg_initref_dis bit in the SDRAM Refresh Control register is set to 0, the EMIF performs a DDR3 SDRAM
initialization sequence as follows:
1. Drives pad_cke_o low.
2. After 16 SDRAM refresh rate intervals, issues a NOP command with pad_cke_o held high. The
SDRAM refresh rate is as defined in the reg_refresh_rate field description (see description of SDRAM
Refresh Control register).
with pad_a_o[15:0] set as follows:

pad_a_o[10:9] reg_dyn_odt Dynamic ODT value from SDRAM Config register
pad_a_o[8] 0x0 Reserved
pad_a_o[7] reg_srt Self-refresh temperature range from SDRAM Refresh Control register
pad_a_o[6] reg_asr Auto self-refresh enable from SDRAM Refresh Control register
pad_a_o[4:3] reg_cwl CAS write latency from SDRAM Config register
with pad_a_o[15:0] = 0x0.

pad_a_o[12] 0x0 Output buffer enabled
pad_a_o[11] 0x0 TDQS disable

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pad_a_o[7] 0x0 Write leveling disabled
reg_sdram_drive
pad_a_o[5] SDRAM drive strength from SDRAM Config register
[1]
pad_a_o[4:3] 0x0 Additive latency = 0
pad_a_o[1] reg_sdram_drive[0] SDRAM drive strength from SDRAM Config register
pad_a_o[0] 0x0 reg_ddr_disable_dll value from SDRAM Config register
6. Issues a LOAD MODE REGISTER command to the mode register (pad_ba_o[2:0] = 0x0) with the
pad_a_o bits set as follows:

pad_a_o[12] 0x0 Fast exit active power-down exit time
pad_a_o[11:9] reg_t_wr Write recovery for auto precharge from SDRAM Timing 1 register
pad_a_o[8] 0x1 DLL reset
pad_a_o[7] 0x0 Normal mode
pad_a_o[2] reg_cl[0] CAS latency from SDRAM Config register
7. Issues a ZQCL command to start long ZQ calibration.

8. Issues an AUTO REFRESH command.
some DDR3 datasheets. The EMIF does not perform any transactions until the DDR3 initialization
value to meet the typical DDR3 device specified delay time of 500 us between the deassertion of reset
and the assertion of CKE.
7.3.3.6.3 LPDDR1 Initialization

reg_initref_dis bit in the SDRAM Refresh Control register is set to 0, the EMIF performs a LPDDR1
SDRAM initialization sequence as follows:
1. Drives pad_cke_o high and starts to continuously issues NOP commands.
2. After 16 SDRAM refresh rate intervals, issues a PRECHARGE command with pad_a_o[10] held high
to indicate all banks. The SDRAM refresh rate is as defined in the reg_refresh_rate field description
(see description of SDRAM Refresh Control register).
3. After 2 AUTO REFRESH commands, issues a LOAD MODE REGISTER command to the mode
register (pad_ba_o[2:0] = 0x0) with the pad_a_o bits set as follows:

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pad_a_o[15:7] 0x0 Normal operation
4. Issues a LOAD MODE REGISTER command to the extended mode register (pad_ba_o[2:0] = 0x2)

pad_a_o[6:5] reg_sdram_drive Drive strength from SDRAM Config register
pad_a_o[4:3] 0x0 Internal temperature compensated self-refresh

some LPDDR1 datasheets. The EMIF does not perform any transactions until the LPDDR1 initialization
value to meet the typical LPDDR1 device specified delay time of 200 us between power-up and the
application of the PRECHARGE all command.
7.3.3.7 DDR3 Read-Write Leveling

The DDR2/3/mDDR memory controller supports read-write leveling in conjunction with the DDR PHY. The
DDR2/3/mDDR memory controller supports two types of write/read leveling:
1. Full leveling
2. Incremental leveling
NOTE: Please refer the device specific data sheet to know the type of leveling supported.
Each leveling type has three parts:

1. Write leveling
2. Read DQS gate training
3. Read data eye training
Read and write leveling is only supported to DDR3 memory.
The DDR2/3/mDDR memory controller does not perform full leveling after initialization upon reset
deassertion. Full leveling must be triggered by software after the DDR2/3/mDDR memory controller
registers are properly configured. The DDR2/3/mDDR memory controller supports triggering of full leveling
through software through the use of the REG_RDWRLVLFULL_START field in the Read-Write Leveling
Control register(RWLCR). Since full leveling takes considerable amount of time and refreshes cannot be
issued to DDR3 when DDR3 is put in leveling mode, refresh interval will be violated and data inside DDR3
can be lost. Although, this is not an issue at power-up, this might be an issue if full leveling is triggered
when DDR3 is functional.

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The memory controller supports incremental leveling to better track voltage and temperature changes
during normal operation. The incremental leveling can be enabled by writing a non-zero value to the
REG_WRLVLINC_INT, REG_RDLVLGATEINC_INT, and REG_RDLVLINC_INT fields in the Read-Write
Leveling Control register(RWLCR). The memory controller periodically triggers incremental write leveling
every time REG_WRLVLINC_INT expires. In other words, the REG_WRLVLINC_INT defines the interval
between successive incremental write leveling.
Similarly, the memory controller periodically triggers incremental read DQS gate training every time
REG_RDLVLGATEINC_INT expires, and triggers incremental read data eye training every time
REG_RDLVLINC_INT expires.
To minimize impact on bandwidth, the software can program these intervals such that these three
intervals do not expire at same time. The value of interval programmed is dependent on the slope of
voltage and temperature changes.
The memory controller supports increasing the rate of incremental leveling automatically for a defined
period of time. This can be achieved by programming the Read-Write Leveling Ramp Window
register(RDWR_LVL_RMP_WIN) and the Read-Write Leveling Ramp Control
register(RDWR_LVL_RMP_CTRL). Whenever a pulse is received, the memory controller would use the
intervals programmed in the Read-Write Leveling Ramp Control register until the
REG_RDWRLVLINC_RMP_WIN in the Read-Write Leveling Ramp Window register expires. After the
expiration of REG_RDWRLVLINC_RMP_WIN the memory controller switches back to use the intervals
programmed in the Read-Write Leveling Control register.
To guarantee none of the incremental leveling events are missed, the REG_RDWRLVLINC_RMP_WIN
must be programmed greater than the intervals in the Read-Write Leveling Ramp Control register.
If the memory controller is in Self-Refresh or Power-Down modes when any of the incremental leveling
intervals expire, the memory controller will exit Self-Refresh or Power-Down mode, perform the required
leveling, and then re-enter the Self-Refresh or Power-Down mode. The memory controller also triggers
incremental leveling on Self-Refresh exit.
7.3.3.8 PRCM Sequence for DDR2/3/mDDR Memory controller

The memory controller clock, reset and power are handled by the device PRCM module. Refer to the
Power Reset Clock Management (PRCM) chapter for the PRCM register details.
7.3.3.9 Interrupt Support

The DDR2/3/mDDR controller is compliant with Open Core Protocol Specification (OCP-IP 2.2). The
controller supports only Idle, Write, Read, and WriteNonPost command types. Also, the controller supports
only incrementing, wrapping, and 2-dimensional block addressing modes. The controller supports
generation of an error interrupt if an unsupported command or a command with unsupported addressing
mode is received.
7.3.3.10 EDMA Event Support

The DDR2/3/mDDR memory controller is a DMA slave peripheral and therefore does not generate EDMA
events. Data read and write requests may be made directly by masters including the EDMA controller.
7.3.3.11 Emulation Considerations

The DDR2/3/mDDR memory controller will remain fully functional during emulation halts to allow emulation
access to external memory.
7.3.3.12 Power Management

This section defines the power management capabilities and requirements.

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7.3.3.12.1 Clock Stop Mode

The memory controller supports Clock Stop mode for LPDDR1/mDDR. The memory controller
automatically stops the clocks to the memory, after the memory controller is idle for REG_CS_TIM number
of DDR clock cycles and the REG_LP_MODE field is set to 1. The REG_LP_MODE and REG_CS_TIM
fields can be programmed in the power management control register (PMCR).
When the clock to the memory is stopped, the memory controller services register accesses as normal. If
an SDRAM access is requested, or the Refresh Must level is reached while in the Clock Stop mode, the
memory controller will start the clocks. The memory controller now can issue any commands. If the power
saving mode is changed by changing REG_LP_MODE from 1 to some other value, the memory controller
will exit Clock Stop mode and enter the new power saving mode.
7.3.3.12.2 Self-Refresh Mode

The DDR2/3/mDDR memory controller supports self-refresh mode for low power. The memory controller
automatically puts the SDRAM into self-refresh after the memory controller is idle for REG_SR_TIM
number of DDR clock cycles and the REG_LP_MODE field is set to 2. The REG_LP_MODE and
REG_SR_TIM fields can be programmed in the Power Management Control register(PMCR). The memory
controller will complete all pending refreshes before it puts the SDRAM into self-refresh. Therefore, after
the expiration of REG_SR_TIM, the memory controller will start issuing refreshes to complete the refresh
backlog, and then issue a SELF-REFRESH command to the SDRAM.
In self-refresh mode, the memory controller automatically stops the clocks DDR_CLK to the SDRAM. The
memory controller maintains DDR_CKE low to maintain the self-refresh state. When the SDRAM is in self-
refresh, the memory controller services register accesses as normal. If the REG_LP_MODE field is set not
equal to 2, or an SDRAM access is requested while it is in self-refresh, and T_CKE + 1 cycles have
elapsed since the SELF-REFRESH command was issued, the memory controller will bring the SDRAM
out of self-refresh. The value of T_CKE is taken from SDRAM Timing 2 register. For DDR3, memory
controller will also exit self-refresh to perform incremental leveling.
Exit sequence of self-refresh mode for LPDDR1 device: The memory controller:
• Enables clocks.
• Drives DDR_CKE high.
• Waits for T_XSNR + 1 cycles. The value of T_XSNR is taken from SDRAM Timing 2 register.
• Starts an auto-refresh cycle in the next cycle.
• Enters its idle state and can issue any commands.
Exit sequence of self-refresh mode for DDR2 device: The memory controller:
• Enables clocks.
• If the REG_DDR_DISABLE_DLL bit in the SDRAM Config register is 1, issues a LOAD MODE
REGISTER command to the extended mode register 1 with the pad_a_o bits set as follows:

DDR_A[15:13] 0x0 !reg_ddr2_ddqs
DDR_A[12] 0x0 Output buffer enabled
DDR_A[11] 0x0 RDQS disable
DDR_A[10] !reg_ddr2_ddqs Differential DQS enable value from SDRAM Config register
DDR_A[9:7] 0x0 Exit OCD calibration mode
DDR_A[6] reg_ddr_term[1] DDR2 termination resistor value from SDRAM Config register
DDR_A[5:3] 0x0 Additive latency = 0
DDR_A[1] reg_sdram_drive SDRAM drive strength from SDRAM Config register
DDR_A[0] 0x1 Disable DLL

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• Enters its idle state and can issue any other commands except a write or a read. A write or a read will
only be issued after T_XSRD + 1 clock cycles have elapsed since DDR_CKE is driven high. The value
of T_XSRD is taken from SDRAM Timing 2 register.
Exit sequence of self-refresh mode for DDR3 device: The memory controller:
• Enables clocks.
• If the REG_DDR_DISABLE_DLL bit in the SDRAM Config register is 1, issues a LOAD MODE
REGISTER command to the extended mode register 1 with the pad_a_o bits set as follows:

DDR_A[15:13] 0x0 Reserved
DDR_A[12] 0x0 Output buffer enabled
DDR_A[11] 0x0 TDQS disable
DDR_A[10] 0x0 Reserved
DDR_A[8] 0x0 Reserved
DDR_A[7] 0x0 Write leveling disabled
DDR_A[5] reg_sdram_drive[1] SDRAM drive strength from SDRAM Config register
DDR_A[4:3] 0x0 Additive latency = 0
DDR_A[1] reg_sdram_drive[0] SDRAM drive strength from SDRAM Config register
DDR_A[0] 0x1 Disable DLL

• Performs one write incremental leveling.
• Performs read DQS incremental training.
• Performs read data-eye incremental training.
• Enters its idle state and can issue any other commands except a write or a read. A write or a read will
only be issued after T_XSRD + 1 clock cycles have elapsed since DDR_CKE is driven high. The value
of T_XSRD is taken from SDRAM Timing 2 register.
7.3.3.12.3 Power Down Mode

The memory controller also supports power-down mode for low power. The memory controller
automatically puts the SDRAM into power-sDown after the memory controller is idle for REG_PD_TIM
number of DDR clock cycles and the REG_LP_MODE field is set to 4. The REG_LP_MODE and
REG_PD_TIM fields can be programmed in the Power Management Control register (PMCR). If the
Refresh Must level is not reached before the entry into power-down, the memory controller will not
precharge all banks before issuing the POWER-DOWN command. This will result in SDRAM entering
active power-down mode.
If the Refresh Must level is reached before the entry into power-down, the memory controller will
precharge all banks and issue refreshes until the Refresh Release Level is reached before issuing the
POWER-DOWN command. This will result in SDRAM entering precharge power-down mode.
In power-down mode, the memory controller does not stop the clocks DDR_CLK to the SDRAM. The
memory controller maintains DDR_CKE low to maintain the power-down state.

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When the SDRAM is in power-down, the memory controller services register accesses as normal. If the
REG_LP_MODE field is set not equal to 4, or an SDRAM access is requested, or the Refresh Must level
is reached while the SDRAM is in power-down, the memory controller will bring the SDRAM out of power-
down. For DDR3, memory controller will also exit power-down to perform incremental leveling.
Exit sequence of power-down mode for DDR2, DDR3 and LPDDR1: The memory controller
• Drives DDR_CKE high after T_CKE + 1 cycles have elapsed since the POWER-DOWN command was
issued. The value of T_CKE is taken from SDRAM Timing 2 register.
• Waits for T_XP + 1 cycles. The value of T_XP is taken from SDRAM Timing 2 register.
7.3.3.12.4 Deep Power-Down Mode

For ultimate power savings, the memory controller supports deep power-down mode for LPDDR1.
The SDRAM can be forced into deep power-down through software by setting the reg_dpd_en field in the
Power Management Control register to 1. In this case, the memory controller will continue normal
operation until all SDRAM memory access requests have been serviced. At this point the memory
controller will issue a DEEP POWER-DOWN command. The memory controller then maintains pad_cke_o
low to maintain the Deep Power-Down state. In deep power-down mode, the memory controller
automatically stops the clocks to the SDRAM.
Setting the REG_DPD_EN field to 1 overrides the setting of REG_LP_MODE field. Therefore, if the
SDRAM is in Clock Stop, Self Refresh, or Power-Down mode, and REG_DPD_EN field is set to 1, the
memory controller will exit those modes and go into deep power-down mode.
When the SDRAM is in deep power-down, the memory controller services register accesses as normal.
If the REG_DPD_EN field is set to 0, or an SDRAM access is requested, the memory controller will bring
the SDRAM out of deep power-down.
Exit sequence for LPDDR1: The memory controller:
• Performs SDRAM initialization as specified in the LPDDR1(mDDR) SDRAM Memory Initialization
section.
Since the memory controller performs initialization upon deep power-down exit, the
REG_REFRESH_RATE field in the SDRAM Refresh Control register must be set appropriately to meet
the 200µs wait requirement for LPDDR1.
7.3.3.12.5 Save and Restore Mode

The DDR2/3/mDDR memory controller supports save and restore mechanism to completely switch off
power to the DDR2/3/mDDR memory controller. The following sequence of operations is followed to put
DDR2/3/mDDR memory controller in off mode:
An external master reads the following memory mapped registers and saves their value external to the
DDR2/3/mDDR memory controller.
1. SDRAM Config register (SDRCR)
2. SDRAM Config 2 register
3. SDRAM Refresh Control register (SDRRCR)
4. SDRAM Refresh Control Shadow register (SDRRCSR)
5. SDRAM Timing 1 register (SDRTIM1)
6. SDRAM Timing 1 Shadow register (SDRTIM1SR)
11. Power Management Control register (PMCR)

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12. Power Management Control Shadow register (PMCSR)

13. Interface Configuration register (OCP_CONFIG)
14. System OCP Interrupt Enable Set Register (SOIESR)
15. DDR PHY Control 1 register (DDRPHYCR)
16. DDR PHY Control 1 Shadow register (DDRPHYCSR)
• Memory controller completes all pending transactions and drains all its FIFOs.
• Memory controller puts the SDRAM in Self Refresh.
• Memory controller copies all shadow memory mapped registers to its main registers. It is assumed that
the shadow register always has the same value as its corresponding main register.
• Memory controller waits for all interrupts to be serviced.
• Memory controller acknowledges assertion of internal power down request.
• The internal module reset signal is asserted.
• The clocks and power to the memory controller can now be switched off.
To restore power to the memory controller, the following sequence of operations is followed:
• The power and clocks to the Memory controller are switched on.
• The internal module reset signal is deasserted, indicating to the Memory controller that it is waking up
from off mode.
• The memory controller does not perform SDRAM initialization and forces its state machine to be in
self-refresh.
• The external master restores all of the above memory mapped registers.
• The external master restores all of the above memory mapped registers.
• The system can now perform access to the external memory.
7.3.3.12.6 EMIF PHY Clock Gating

The clock to the DDR2/3/mDDR PHY can be gated off to achieve power saving. For more information, see
the EMIF0/1 Clock Gate Control register (EMIF_CLK_GATE).
7.3.4 Use Cases

For details on connecting this device to mDDR/DDR2/DDR3 devices, see the device-specific data sheet,
which will include specific instructions and routing guidelines for interfacing to mDDR (LPDDR), DDR2,
and DDR3 devices.
7.3.5 EMIF4D Registers

Table 7-221 lists the memory-mapped registers for the EMIF4D. All register offset addresses not listed in
Table 7-221. EMIF4D Registers

0h EMIF_MOD_ID_REV Section 7.3.5.1
4h STATUS Section 7.3.5.2
8h SDRAM_CONFIG Section 7.3.5.3
Ch SDRAM_CONFIG_2 Section 7.3.5.4
10h SDRAM_REF_CTRL Section 7.3.5.5
14h SDRAM_REF_CTRL_SHDW Section 7.3.5.6
18h SDRAM_TIM_1 Section 7.3.5.7
1Ch SDRAM_TIM_1_SHDW Section 7.3.5.8
24h SDRAM_TIM_2_SHDW Section 7.3.5.10

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Table 7-221. EMIF4D Registers (continued)

2Ch SDRAM_TIM_3_SHDW Section 7.3.5.12
38h PWR_MGMT_CTRL Section 7.3.5.13
3Ch PWR_MGMT_CTRL_SHDW Section 7.3.5.14
54h OCP_CONFIG Section 7.3.5.15
58h OCP_CFG_VAL_1 Section 7.3.5.16
5Ch OCP_CFG_VAL_2 Section 7.3.5.17
80h PERF_CNT_1 Section 7.3.5.18
84h PERF_CNT_2 Section 7.3.5.19
88h PERF_CNT_CFG Section 7.3.5.20
8Ch PERF_CNT_SEL Section 7.3.5.21
90h PERF_CNT_TIM Section 7.3.5.22
98h READ_IDLE_CTRL Section 7.3.5.23
9Ch READ_IDLE_CTRL_SHDW Section 7.3.5.24
A4h IRQSTATUS_RAW_SYS Section 7.3.5.25
ACh IRQSTATUS_SYS Section 7.3.5.26
B4h IRQENABLE_SET_SYS Section 7.3.5.27
BCh IRQENABLE_CLR_SYS Section 7.3.5.28
C8h ZQ_CONFIG Section 7.3.5.29
D4h Read-Write Leveling Ramp Window Section 7.3.5.30
D8h Read-Write Leveling Ramp Control Section 7.3.5.31
DCh Read-Write Leveling Control Section 7.3.5.32
E4h DDR_PHY_CTRL_1 Section 7.3.5.33
E8h DDR_PHY_CTRL_1_SHDW Section 7.3.5.34
100h Priority to Class of Service Mapping Section 7.3.5.35
104h Connection ID to Class of Service 1 Section 7.3.5.36
Mapping
108h Connection ID to Class of Service 2 Section 7.3.5.37
Mapping
120h Read Write Execution Threshold Section 7.3.5.38

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7.3.5.1 EMIF_MOD_ID_REV Register (offset = 0h) [reset = 40443403h]

EMIF_MOD_ID_REV is shown in Figure 7-204 and described in Table 7-222.
Figure 7-204. EMIF_MOD_ID_REV Register

31 30 29 28 27 26 25 24
reg_scheme RESERVED reg_module_id
R-1h R-0h R-44h
23 22 21 20 19 18 17 16
reg_module_id
R-44h
15 14 13 12 11 10 9 8
reg_rtl_version reg_major_revision
R-6h R-4h
7 6 5 4 3 2 1 0
RESERVED reg_minor_revision
R-0h R-3h
Table 7-222. EMIF_MOD_ID_REV Register Field Descriptions

31-30 reg_scheme R 1h Used to distinguish between old and current schemes.
29-28 RESERVED R 0h
27-16 reg_module_id R 44h EMIF module ID.
15-11 reg_rtl_version R 6h RTL Version.
10-8 reg_major_revision R 4h Major Revision.
7-6 RESERVED R 0h
5-0 reg_minor_revision R 3h Minor Revision.

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7.3.5.2 STATUS Register (offset = 4h) [reset = 40000000h]

STATUS is shown in Figure 7-205 and described in Table 7-223.
Figure 7-205. STATUS Register

31 30 29 28 27 26 25 24
reg_be reg_dual_clk_m reg_fast_init RESERVED
ode
R-0h R-1h R-0h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED reg_phy_dll_re RESERVED
ady
R-0h R-0h R-0h
Table 7-223. STATUS Register Field Descriptions

31 reg_be R 0h Big Endian.
Reflects the value on the config_big_endian port that defines
whether the EMIF is in big or little endian mode.
0 = Little endian.
1 = Big endian.
30 reg_dual_clk_mode R 1h Dual Clock mode.
Reflects the value on the config_dual_clk_mode port that defines
whether the ocp_clk and m_clk are asynchronous.
0 = ocp_clk = m_clk.
1 = Asynchronous ocp_clk and m_clk.
29 reg_fast_init R 0h Fast Init.
Reflects the value on the config_fast_init port that defines whether
the EMIF fast initialization mode has been enabled.
0 = Fast init disabled.
1 = Fast init enabled.
28-3 RESERVED R 0h
2 reg_phy_dll_ready R 0h DDR PHY Ready.
Reflects the value on the phy_ready port (active high) that defines
whether the DDR PHY is ready for normal operation.
1-0 RESERVED R 0h

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7.3.5.3 SDRAM_CONFIG Register (offset = 8h) [reset = 4104BAB2h]

SDRAM_CONFIG is shown in Figure 7-206 and described in Table 7-224.
Figure 7-206. SDRAM_CONFIG Register

31 30 29 28 27 26 25 24
reg_sdram_type reg_ibank_pos reg_ddr_term
23 22 21 20 19 18 17 16
reg_ddr2_ddqs reg_dyn_odt reg_ddr_disabl reg_sdram_drive reg_cwl
e_dll
15 14 13 12 11 10 9 8
reg_narrow_mode reg_cl reg_rowsize
R/W-2h R/W-Eh R/W-5h
7 6 5 4 3 2 1 0
reg_rowsize reg_ibank reg_ebank reg_pagesize
Table 7-224. SDRAM_CONFIG Register Field Descriptions

31-29 reg_sdram_type R/W 2h SDRAM Type selection.
Set to 0 for DDR1, set to 1 for LPDDR1, set to 2 for DDR2, set to 3
for DDR3.
All other values are reserved.
28-27 reg_ibank_pos R/W 0h Internal bank position.
Set to 0 to assign internal bank address bits from lower OCP
address bits, as shown in the tables for OCP Address to
DDR2/3/mDDR Address Mapping.
Set to 1, 2, or 3 to assign internal bank address bits from higher
OCP address, as shown in the tables for OCP Address to
26-24 reg_ddr_term R/W 1h DDR2 and DDR3 termination resistor value.
Set to 0 to disable termination.
For DDR2, set to 1 for 75 ohm, set to 2 for 150 ohm, and set to 3 for
50 ohm.
For DDR3, set to 1 for RZQ/4, set to 2 for RZQ/2, set to 3 for RZQ/6,
set to 4 for RZQ/12, and set to 5 for RZQ/8.
23 reg_ddr2_ddqs R/W 0h DDR2 differential DQS enable.
Set to 0 for single ended DQS.
Set to 1 for differential DQS.
22-21 reg_dyn_odt R/W 0h DDR3 Dynamic ODT.
Set to 0 to turn off dynamic ODT.
Set to 1 for RZQ/4 and set to 2 for RZQ/2.
20 reg_ddr_disable_dll R/W 0h Disable DLL select.
Set to 1 to disable DLL inside SDRAM.
19-18 reg_sdram_drive R/W 1h SDRAM drive strength.
For DDR1/DDR2, set to 0 for normal, and set to 1 for weak drive
strength.
For DDR3, set to 0 for RZQ/6 and set to 1 for RZQ/7.
For LPDDR1, set to 0 for full, set to 1 for 1/2, set to 2 for 1/4, and set
to 3 for 1/8 drive strength.
17-16 reg_cwl R/W 0h DDR3 CAS Write latency.
Value of 0, 1, 2, and 3 (CAS write latency of 5, 6, 7, and 8) are
supported.
Use the lowest value supported for best performance.

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Table 7-224. SDRAM_CONFIG Register Field Descriptions (continued)

15-14 reg_narrow_mode R/W 2h SDRAM data bus width.
Set to 0 for
32-bit and set to 1 for
16-bit.
13-10 reg_cl R/W Eh CAS Latency.
The value of this field defines the CAS latency to be used when
accessing connected SDRAM devices.
Value of 2, 3, 5, and 6 (CAS latency of 2, 3, 1.5, and 2.5) are
supported for DDR1.
Value of 2, 3, 4, and 5 (CAS latency of 2, 3, 4, and 5) are supported
for DDR2.
Value of 2, 4, 6, 8, 10, 12, and 14 (CAS latency of 5, 6, 7, 8, 9, 10,
and 11) are supported for DDR3.
Value of 2 and 3 (CAS latency of 2 and 3) are supported for
LPDDR1.
9-7 reg_rowsize R/W 5h Row Size.
Defines the number of row address bits of connected SDRAM
devices.
Set to 0 for 9 row bits, set to 1 for 10 row bits, set to 2 for 11 row
bits, set to 3 for 12 row bits, set to 4 for 13 row bits, set to 5 for 14
row bits, set to 6 for 15 row bits, and set to 7 for 16 row bits.
This field is only used when reg_ibank_pos field in SDRAM Config
register is set to 1, 2, or 3, or reg_ebank_pos field in SDRAM
Config_2 register is set to 1.
6-4 reg_ibank R/W 3h Internal Bank setup.
Defines number of banks inside connected SDRAM devices.
Set to 0 for 1 bank, set to 1 for 2 banks, set to 2 for 4 banks, and set
to 3 for 8 banks.
3 reg_ebank R/W 0h External chip select setup.
Defines whether SDRAM accesses will use 1 or 2 chip select lines.
Set to 0 to use pad_cs_o_n[0] only.
All other values reserved.
2-0 reg_pagesize R/W 2h Page Size.
Defines the internal page size of connected SDRAM devices.
Set to 0 for
256-word page (8 column bits), set to 1 for
512-word page (9 column bits), set to 2 for
1024-word page (10 column bits), and set to 3 for
2048-word page (11 column bits).

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7.3.5.4 SDRAM_CONFIG_2 Register (offset = Ch) [reset = 0h]

SDRAM_CONFIG_2 is shown in Figure 7-207 and described in Table 7-225.
Figure 7-207. SDRAM_CONFIG_2 Register

31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED reg_ebank_pos RESERVED
R-0h R/W-0h R-0h R/W-0h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED
Table 7-225. SDRAM_CONFIG_2 Register Field Descriptions

31 RESERVED R 0h
29-28 RESERVED R 0h
27 reg_ebank_pos R/W 0h External bank position.
Set to 0 to assign external bank address bits from lower OCP
address, as shown in the tables for OCP Address to DDR2/3/mDDR
Address Mapping.
Set to 1 to assign external bank address bits from higher OCP
address bits, as shown in the tables for OCP Address to
26-6 RESERVED R 0h
5-4 RESERVED R/W 0h Reserved.
3 RESERVED R 0h

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7.3.5.5 SDRAM_REF_CTRL Register (offset = 10h) [reset = 80001388h]

SDRAM_REF_CTRL is shown in Figure 7-208 and described in Table 7-226.
Figure 7-208. SDRAM_REF_CTRL Register

31 30 29 28 27 26 25 24
reg_initref_dis RESERVED reg_srt reg_asr RESERVED reg_pasr
R/W-1h R-0h R/W-0h R/W-0h R-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
reg_refresh_rate
R/W-1388h
7 6 5 4 3 2 1 0
reg_refresh_rate
R/W-1388h
Table 7-226. SDRAM_REF_CTRL Register Field Descriptions

31 reg_initref_dis R/W 1h Initialization and Refresh disable.
When set to 1, EMIF will disable SDRAM initialization and refreshes,
but will carry out SDRAM write/read transactions.
30 RESERVED R 0h
29 reg_srt R/W 0h DDR2 and DDR3 self-refresh temperature range.
Set to 0 for normal operating temperature range.
Set to 1 for extended operating temperature range.
For DDR3, this bit must be set to 0 if the reg_asr field is set to 1.
A write to this field will cause the EMIF to start the SDRAM
initialization sequence.
28 reg_asr R/W 0h DDR3 Auto Self Refresh enable.
Set to 1 for auto Self Refresh enable.
Set to 0 for manual Self Refresh reference indicated by the reg_srt
field.
27 RESERVED R 0h
26-24 reg_pasr R/W 0h Partial Array Self Refresh.
These bits get loaded into the Extended Mode Register of an
LPDDR1 or DDR3 during initialization.
For LPDDR1, set to 0 for full array, set to 1 for 1/2 array, set to 2 for
1/4 array, set to 5 for 1/8 array, and set to 6 for 1/16 array to be
refreshed.
For DDR3, set to 0 for full array, set to 1 or 5 for 1/2 array, set to 2
or 6 for 1/4 array, set to 3 or 7 for 1/8 array, and set to 4 for 3/4
array to be refreshed.
23-16 RESERVED R 0h
15-0 reg_refresh_rate R/W 1388h Refresh Rate.
Value in this field is used to define the rate at which connected
SDRAM devices will be refreshed.
SDRAM refresh rate = EMIF rate / reg_refresh_rate where EMIF rate
is equal to DDR clock rate.
If reg_refresh_rate < (8*reg_t_rfc)+reg_t_rp+reg_t_rcd+20 then it will
be loaded with (8*reg_t_rfc)+reg_t_rp+reg_t_rcd+20.
This is done to avoid lock-up situations when illegal values are
programmed.

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7.3.5.6 SDRAM_REF_CTRL_SHDW Register (offset = 14h) [reset = 00001388h]

SDRAM_REF_CTRL_SHDW is shown in Figure 7-209 and described in Table 7-227.
Figure 7-209. SDRAM_REF_CTRL_SHDW Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg_refresh_rate_shdw
R/W-1388h
Table 7-227. SDRAM_REF_CTRL_SHDW Register Field Descriptions

31-16 RESERVED R 0h
15-0 reg_refresh_rate_shdw R/W 1388h Shadow field for reg_refresh_rate.
This field is loaded into reg_refresh_rate field in SDRAM Refresh
Control register when SIdleAck is asserted.
This register is not auto corrected when the value is invalid.

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7.3.5.7 SDRAM_TIM_1 Register (offset = 18h) [reset = 08891599h]

SDRAM_TIM_1 is shown in Figure 7-210 and described in Table 7-228.
Figure 7-210. SDRAM_TIM_1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED reg_t_rp reg_t_rcd reg_t_wr reg_t_r
as
R-0h R/W-4h R/W-4h R/W-4h R/W-
11h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg_t_ras reg_t_rc reg_t_rrd reg_t_wtr
Table 7-228. SDRAM_TIM_1 Register Field Descriptions

31-29 RESERVED R 0h
28-25 reg_t_rp R/W 4h Minimum number of DDR clock cycles from Precharge to Activate or
Refresh, minus one.
24-21 reg_t_rcd R/W 4h Minimum number of DDR clock cycles from Activate to Read or
Write, minus one.
20-17 reg_t_wr R/W 4h Minimum number of DDR clock cycles from last Write transfer to
Pre-charge, minus one.
The SDRAM initialization sequence will be started when the value of
this field is changed from the previous value and the EMIF is in
DDR2 mode.
16-12 reg_t_ras R/W 11h Minimum number of DDR clock cycles from Activate to Pre-charge,
minus one.
reg_t_ras >= reg_t_rcd.
11-6 reg_t_rc R/W 16h Minimum number of DDR clock cycles from Activate to Activate,
minus one.
5-3 reg_t_rrd R/W 3h Minimum number of DDR clock cycles from Activate to Activate for a
different bank, minus one.
For an 8-bank DDR2 or DDR3, this field must be equal to
((tFAW/(4*tCK))-1). For 4-bank DDR2 or LPDDR1, the field must be
equal to (tRRD/tCK)-1.
2-0 reg_t_wtr R/W 1h Minimum number of DDR clock cycles from last Write to Read,
minus one.

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7.3.5.8 SDRAM_TIM_1_SHDW Register (offset = 1Ch) [reset = 08891599h]

SDRAM_TIM_1_SHDW is shown in Figure 7-211 and described in Table 7-229.
Figure 7-211. SDRAM_TIM_1_SHDW Register

31 30 29 28 27 26 25 24
RESERVED reg_t_rp_shdw reg_t_rcd_shdw
R-0h R/W-4h R/W-4h
23 22 21 20 19 18 17 16
reg_t_rcd_shdw reg_t_wr_shdw reg_t_ras_shdw
15 14 13 12 11 10 9 8
reg_t_ras_shdw reg_t_rc_shdw
R/W-11h R/W-16h
7 6 5 4 3 2 1 0
reg_t_rc_shdw reg_t_rrd_shdw reg_t_wtr_shdw
Table 7-229. SDRAM_TIM_1_SHDW Register Field Descriptions

31-29 RESERVED R 0h
28-25 reg_t_rp_shdw R/W 4h Shadow field for reg_t_rp.
This field is loaded into reg_t_rp field in SDRAM Timing 1 register
when SIdleAck is asserted.
24-21 reg_t_rcd_shdw R/W 4h Shadow field for reg_t_rcd.
This field is loaded into reg_t_rcd field in SDRAM Timing 1 register
20-17 reg_t_wr_shdw R/W 4h Shadow field for reg_t_wr.
This field is loaded into reg_t_wr field in SDRAM Timing 1 register
initialization sequence will be started when the value of this field is
changed from the previous value and the EMIF is in DDR2 mode.
16-12 reg_t_ras_shdw R/W 11h Shadow field for reg_t_ras.
This field is loaded into reg_t_ras field in SDRAM Timing 1 register
11-6 reg_t_rc_shdw R/W 16h Shadow field for reg_t_rc.
This field is loaded into reg_t_rc field in SDRAM Timing 1 register
5-3 reg_t_rrd_shdw R/W 3h Shadow field for reg_t_rrd.
This field is loaded into reg_t_rrd field in SDRAM Timing 1 register
2-0 reg_t_wtr_shdw R/W 1h Shadow field for reg_t_wtr.
This field is loaded into reg_t_wtr field in SDRAM Timing 1 register

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7.3.5.9 SDRAM_TIM_2 Register (offset = 20h) [reset = 148B31CAh]


31 30 29 28 27 26 25 24
RESERVED reg_t_xp RESERVED reg_t_xsnr
R-0h R/W-1h R/W-2h R/W-8Bh
23 22 21 20 19 18 17 16
reg_t_xsnr
R/W-8Bh
15 14 13 12 11 10 9 8
reg_t_xsrd
R/W-C7h
7 6 5 4 3 2 1 0
reg_t_xsrd reg_t_rtp reg_t_cke
R/W-C7h R/W-1h R/W-2h

31 RESERVED R 0h
30-28 reg_t_xp R/W 1h Minimum number of DDR clock cycles from Powerdown exit to any
command other than a Read command, minus one.
For DDR2 and LPDDR1, this field must satisfy greater of tXP or
tCKE.
24-16 reg_t_xsnr R/W 8Bh Minimum number of DDR clock cycles from Self-Refresh exit to any
command other than a Read command, minus one.
15-6 reg_t_xsrd R/W C7h Minimum number of DDR clock cycles from Self-Refresh exit to a
Read command, minus one.
5-3 reg_t_rtp R/W 1h Minimum number of DDR clock cycles from the last Read command
to a Pre-charge command for DDR2 and DDR3, minus one.
2-0 reg_t_cke R/W 2h Minimum number of DDR clock cycles between pad_cke_o changes,
minus one.

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7.3.5.10 SDRAM_TIM_2_SHDW Register (offset = 24h) [reset = 148B31CAh]


31 30 29 28 27 26 25 24
RESERVED reg_t_xp_shdw RESERVED reg_t_xsnr_shd
w
R-0h R/W-1h R/W-2h R/W-8Bh
23 22 21 20 19 18 17 16
reg_t_xsnr_shdw
R/W-8Bh
15 14 13 12 11 10 9 8
reg_t_xsrd_shdw
R/W-C7h
7 6 5 4 3 2 1 0
reg_t_xsrd_shdw reg_t_rtp_shdw reg_t_cke_shdw
R/W-C7h R/W-1h R/W-2h

31 RESERVED R 0h
30-28 reg_t_xp_shdw R/W 1h Shadow field for reg_t_xp.
This field is loaded into reg_t_xp field in SDRAM Timing 2 register
24-16 reg_t_xsnr_shdw R/W 8Bh Shadow field for reg_t_xsnr.
This field is loaded into reg_t_xsnr field in SDRAM Timing 2 register
15-6 reg_t_xsrd_shdw R/W C7h Shadow field for reg_t_xsrd.
This field is loaded into reg_t_xsrd field in SDRAM Timing 2 register
5-3 reg_t_rtp_shdw R/W 1h Shadow field for reg_t_rtp.
This field is loaded into reg_t_rtp field in SDRAM Timing 2 register
2-0 reg_t_cke_shdw R/W 2h Shadow field for reg_t_cke.
This field is loaded into reg_t_cke field in SDRAM Timing 2 register

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7.3.5.11 SDRAM_TIM_3 Register (offset = 28h) [reset = 00FFE82Fh]


31 30 29 28 27 26 25 24
reg_t_pdll_ul RESERVED
R/W-0h R-0h
23 22 21 20 19 18 17 16
RESERVED reg_zq_zqcs
R/W-7h R/W-3Fh
15 14 13 12 11 10 9 8
reg_zq_zqcs RESERVED reg_t_rfc
7 6 5 4 3 2 1 0
reg_t_rfc reg_t_ras_max
R/W-82h R/W-Fh

31-28 reg_t_pdll_ul R/W 0h Minimum number of DDR clock cycles for PHY DLL to unlock.
A value of N will be equal to N x 128 clocks.
27-24 RESERVED R 0h
20-15 reg_zq_zqcs R/W 3Fh Number of DDR clock clock cycles for a ZQCS command, minus
one.
12-4 reg_t_rfc R/W 82h Minimum number of DDR clock cycles from Refresh or Load Mode to
Refresh or Activate, minus one.
3-0 reg_t_ras_max R/W Fh Maximum number of reg_refresh_rate intervals from Activate to
Precharge command.
This field must be equal to ((tRASmax / tREFI)-1) rounded down to
the next lower integer.
This field is only applicable for mDDR.
This field must be programmed to 0xF for other SDRAM types.

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7.3.5.12 SDRAM_TIM_3_SHDW Register (offset = 2Ch) [reset = 00FFE82F 00000000 00000000h]


31 30 29 28 27 26 25 24
reg_t_pdll_ul_shdw RESERVED
R/W-0h R-0h
23 22 21 20 19 18 17 16
RESERVED reg_zq_zqcs_shdw
R/W-7h R/W-3Fh
15 14 13 12 11 10 9 8
reg_zq_zqcs_s RESERVED reg_t_rfc_shdw
hdw
7 6 5 4 3 2 1 0
reg_t_rfc_shdw reg_t_ras_max_shdw
R/W-82h R/W-Fh

31-28 reg_t_pdll_ul_shdw R/W 0h Shadow field for reg_t_pdll_ul.
This field is loaded into reg_t_pdll_ul field in SDRAM Timing 3
register when SIdleAck is asserted.
27-24 RESERVED R 0h
20-15 reg_zq_zqcs_shdw R/W 3Fh Shadow field for reg_zq_zqcs.
This field is loaded into reg_zq_zqcs field in SDRAM Timing 3
12-4 reg_t_rfc_shdw R/W 82h Shadow field for reg_t_rfc.
This field is loaded into reg_t_rfc field in SDRAM Timing 3 register
3-0 reg_t_ras_max_shdw R/W Fh Shadow field for reg_t_ras_max.
This field is loaded into reg_t_ras_max field in SDRAM Timing 3

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7.3.5.13 PWR_MGMT_CTRL Register (offset = 38h) [reset = 00000000h]

PWR_MGMT_CTRL is shown in Figure 7-216 and described in Table 7-234.
Figure 7-216. PWR_MGMT_CTRL Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
reg_pd_tim reg_dpd_en reg_lp_mode
7 6 5 4 3 2 1 0
reg_sr_tim reg_cs_tim
R/W-0h R/W-0h
Table 7-234. PWR_MGMT_CTRL Register Field Descriptions

31-16 RESERVED R 0h
15-12 reg_pd_tim R/W 0h Power Mangement timer for Power-Down.
The EMIF will put the external SDRAM in Power-Down mode after
the EMIF is idle for these number of DDR clock cycles and if
reg_lp_mode field is set to 4.
Set to 0 to immediately enter Power-Down mode.
Set to 1 for 16 clocks.
Note: After updating this field, at least one dummy read access to
SDRAM is required for the new value to take affect.
11 reg_dpd_en R/W 0h Deep Power Down enable.
Set to 0 for normal operation.
Set to 1 to enter deep power down mode.
This mode will override the reg_lp_mode field setting.
10-8 reg_lp_mode R/W 0h Automatic Power Management enable.
Set to 1 for Clock Stop, set to 2 for Self Refresh, and set to 4 for
Power-Down.
All other values will disable automatic power management.

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Table 7-234. PWR_MGMT_CTRL Register Field Descriptions (continued)

7-4 reg_sr_tim R/W 0h Power Mangement timer for Self Refresh.
The EMIF will put the external SDRAM in Self Refresh mode after
the EMIF is idle for these number of DDR clock cycles and if
Set to 0 to immediately enter Self Refresh mode.
3-0 reg_cs_tim R/W 0h Power Mangement timer for Clock Stop.
The EMIF will put the external SDRAM in Clock Stop mode after the
EMIF is idle for these number of DDR clock cycles and if
Set to 0 to immediately enter Clock Stop mode.

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7.3.5.14 PWR_MGMT_CTRL_SHDW Register (offset = 3Ch) [reset = 00000000 00000000 00000000

00000000 00000000 00000000h]
PWR_MGMT_CTRL_SHDW is shown in Figure 7-217 and described in Table 7-235.
Figure 7-217. PWR_MGMT_CTRL_SHDW Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED reg_pd_tim_shdw
R-0h R/W-0h
7 6 5 4 3 2 1 0
reg_sr_tim_shdw reg_cs_tim_shdw
R/W-0h R/W-0h
Table 7-235. PWR_MGMT_CTRL_SHDW Register Field Descriptions

31-12 RESERVED R 0h
11-8 reg_pd_tim_shdw R/W 0h Shadow field for reg_pd_tim.
This field is loaded into reg_pd_tim field in Power Management
7-4 reg_sr_tim_shdw R/W 0h Shadow field for reg_sr_tim.
This field is loaded into reg_sr_tim field in Power Management
3-0 reg_cs_tim_shdw R/W 0h Shadow field for reg_cs_tim.
This field is loaded into reg_cs_tim field in Power Management

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7.3.5.15 OCP_CONFIG Register (offset = 54h) [reset = 00FFFFFFh]

OCP_CONFIG (Interface Configuration) is shown in Figure 7-218 and described in Table 7-236.
Figure 7-218. OCP_CONFIG Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved REG_COS_COUNT_1
R-0h R/W-FFh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REG_COS_COUNT_2 REG_PR_OLD_COUNT
R/W-FFh R/W-FFh
Table 7-236. OCP_CONFIG Register Field Descriptions

31-24 Reserved R 0h Reserved for future use.
23-16 REG_COS_COUNT_1 R/W FFh Priority Raise Counter for class of service 1.
Number of m_clk cycles after which the EMIF momentarily raises the
priority of the class of service 1 commands in the Command FIFO.
15-8 REG_COS_COUNT_2 R/W FFh Priority Raise Counter for class of service 2.
priority of the class of service 2 commands in the Command FIFO.
7-0 REG_PR_OLD_COUNT R/W FFh Priority Raise Old Counter.
priority of the oldest command in the OCP Command FIFO.

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7.3.5.16 OCP_CFG_VAL_1 Register (offset = 58h) [reset = 8000140Ah]

OCP_CFG_VAL_1 (Interface Configuration Value 1) is shown in Figure 7-219 and described in Table 7-
237.
Figure 7-219. OCP_CFG_VAL_1 Register

31 30 29 28 27 26 25 24
REG_SYS_BUS_WIDTH RESERVED
R-2h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
REG_WR_FIFO_DEPTH
R-14h
7 6 5 4 3 2 1 0
REG_CMD_FIFO_DEPTH
R-Ah
Table 7-237. OCP_CFG_VAL_1 Register Field Descriptions

31-30 REG_SYS_BUS_WIDTH R 2h L3 OCP data bus width for a particular configuration.
0 = 32 bit wide.
1 = 64 bit wide.
2 = 128 bit wide.
3 = 256 bit wide.
29-16 RESERVED R 0h Reserved for future use.
15-8 REG_WR_FIFO_DEPTH R 14h Write Data FIFO depth for a particular configuration.
7-0 REG_CMD_FIFO_DEPTH R Ah Command FIFO depth for a particular configuration.

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7.3.5.17 OCP_CFG_VAL_2 Register (offset = 5Ch) [reset = 00021616 00002011 00000000 00000000
00000000h]
OCP_CFG_VAL_2 (Interface Configuration Value 2) is shown in Figure 7-220 and described in Table 7-
238.
Figure 7-220. OCP_CFG_VAL_2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED REG_RREG_FIFO_DEPTH
R-0h R-2h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REG_RSD_FIFO_DEPTH REG_RCMD_FIFO_DEPTH
R-16h R-16h
Table 7-238. OCP_CFG_VAL_2 Register Field Descriptions

31-24 RESERVED R 0h Reserved for future use.
23-16 REG_RREG_FIFO_DEPT R 2h Register Read Data FIFO depth for a particular configuration.
H
15-8 REG_RSD_FIFO_DEPTH R 16h SDRAM Read Data FIFO depth for a particular configuration.
7-0 REG_RCMD_FIFO_DEPT R 16h Read Command FIFO depth for a particular configuration.
H

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7.3.5.18 PERF_CNT_1 Register (offset = 80h) [reset = 00592A49h]

PERF_CNT_1 is shown in Figure 7-221 and described in Table 7-239.
Figure 7-221. PERF_CNT_1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg_counter1
R-00592A49h
Table 7-239. PERF_CNT_1 Register Field Descriptions

31-0 reg_counter1 R 00592A49h 32-bit counter that can be configured as specified in the
Performance Counter Config Register and Performance Counter
Master Region Select Register.

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7.3.5.19 PERF_CNT_2 Register (offset = 84h) [reset = 0001FEB9h]

PERF_CNT_2 is shown in Figure 7-222 and described in Table 7-240.
Figure 7-222. PERF_CNT_2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg_counter2
R-0001FEB9h
Table 7-240. PERF_CNT_2 Register Field Descriptions

31-0 reg_counter2 R 0001FEB9h 32-bit counter that can be configured as specified in the
Performance Counter Config Register and Performance Counter
Master Region Select Register.

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7.3.5.20 PERF_CNT_CFG Register (offset = 88h) [reset = 10000h]

PERF_CNT_CFG is shown in Figure 7-223 and described in Table 7-241.
Figure 7-223. PERF_CNT_CFG Register

31 30 29 28 27 26 25 24
reg_cntr2_mco reg_cntr2_regio RESERVED
nnid_en n_en
R/W-0h R/W-0h R-0h
23 22 21 20 19 18 17 16
RESERVED reg_cntr2_cfg
R-0h R/W-1h
15 14 13 12 11 10 9 8
reg_cntr1_mco reg_cntr1_regio RESERVED
nnid_en n_en
R/W-0h R/W-0h R-0h
7 6 5 4 3 2 1 0
RESERVED reg_cntr1_cfg
R-0h R/W-0h
Table 7-241. PERF_CNT_CFG Register Field Descriptions

31 reg_cntr2_mconnid_en R/W 0h MConnID filter enable for Performance Counter 2 register.
30 reg_cntr2_region_en R/W 0h Chip Select filter enable for Performance Counter 2 register.
29-20 RESERVED R 0h
19-16 reg_cntr2_cfg R/W 1h Filter configuration for Performance Counter 2.
Refer to table for details.
15 reg_cntr1_mconnid_en R/W 0h MConnID filter enable for Performance Counter 1 register.
14 reg_cntr1_region_en R/W 0h Chip Select filter enable for Performance Counter 1 register.
13-4 RESERVED R 0h
3-0 reg_cntr1_cfg R/W 0h Filter configuration for Performance Counter 1.
For details, see the table titled "Filter Configurations for Performance
Counters".

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7.3.5.21 PERF_CNT_SEL Register (offset = 8Ch) [reset = 0h]

PERF_CNT_SEL is shown in Figure 7-224 and described in Table 7-242.
Figure 7-224. PERF_CNT_SEL Register

31 30 29 28 27 26 25 24
reg_mconnid2
R/W-0h
23 22 21 20 19 18 17 16
RESERVED reg_region_sel2
R-0h R/W-0h
15 14 13 12 11 10 9 8
reg_mconnid1
R/W-0h
7 6 5 4 3 2 1 0
RESERVED reg_region_sel1
R-0h R/W-0h
Table 7-242. PERF_CNT_SEL Register Field Descriptions

31-24 reg_mconnid2 R/W 0h MConnID for Performance Counter 2 register.
23-18 RESERVED R 0h
17-16 reg_region_sel2 R/W 0h MAddrSpace for Performance Counter 2 register.
15-8 reg_mconnid1 R/W 0h MConnID for Performance Counter 1 register.
7-2 RESERVED R 0h
1-0 reg_region_sel1 R/W 0h MAddrSpace for Performance Counter 1 register.

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7.3.5.22 PERF_CNT_TIM Register (offset = 90h) [reset = A484D432 00000000h]

PERF_CNT_TIM is shown in Figure 7-225 and described in Table 7-243.
Figure 7-225. PERF_CNT_TIM Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg_total_time
R-A484D432h
Table 7-243. PERF_CNT_TIM Register Field Descriptions

31-0 reg_total_time R A484D432h 32-bit counter that continuously counts number for m_clk cycles
elapsed after EMIF is brought out of reset.

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7.3.5.23 READ_IDLE_CTRL Register (offset = 98h) [reset = 50000h]

READ_IDLE_CTRL is shown in Figure 7-226 and described in Table 7-244.
Figure 7-226. READ_IDLE_CTRL Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED reg_read_idle_len
R-0h R/W-5h
15 14 13 12 11 10 9 8
RESERVED reg_read_idle_i
nterval
R-0h R/W-0h
7 6 5 4 3 2 1 0
reg_read_idle_interval
R/W-0h
Table 7-244. READ_IDLE_CTRL Register Field Descriptions

31-20 RESERVED R 0h
19-16 reg_read_idle_len R/W 5h The Read Idle Length field determines the minimum size
(reg_read_idle_len-1 clock cycles) of Read Idle window for the read
idle detection as well as the force read idle time.
15-9 RESERVED R 0h
8-0 reg_read_idle_interval R/W 0h The Read Idle Interval field determines the maximum interval
((reg_read_idle_interval-1)*64 clock cycles) between read idle
detections or force.
A value of zero disables the read idle function.

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7.3.5.24 READ_IDLE_CTRL_SHDW Register (offset = 9Ch) [reset = 0050000 00000000h]

READ_IDLE_CTRL_SHDW is shown in Figure 7-227 and described in Table 7-245.
Figure 7-227. READ_IDLE_CTRL_SHDW Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED reg_read_idle_len_shdw
R-0h R/W-5h
15 14 13 12 11 10 9 8
RESERVED reg_read_idle_i
nterval_shdw
R-0h R/W-0h
7 6 5 4 3 2 1 0
reg_read_idle_interval_shdw
R/W-0h
Table 7-245. READ_IDLE_CTRL_SHDW Register Field Descriptions

31-20 RESERVED R 0h
19-16 reg_read_idle_len_shdw R/W 5h Shadow field for reg_read_idle_len.
This field is loaded into reg_read_idle_len field in Read Idle Control
register when SIdleAck is asserted
15-9 RESERVED R 0h
8-0 reg_read_idle_interval_sh R/W 0h Shadow field for reg_read_idle_interval.
dw This field is loaded into reg_read_idle_interval field in Read Idle

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7.3.5.25 IRQSTATUS_RAW_SYS Register (offset = A4h) [reset = 0h]

IRQSTATUS_RAW_SYS is shown in Figure 7-228 and described in Table 7-246.
Figure 7-228. IRQSTATUS_RAW_SYS Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED reg_ta_sys reg_err_sys
Table 7-246. IRQSTATUS_RAW_SYS Register Field Descriptions

31-3 RESERVED R 0h
1 reg_ta_sys R/W 0h Raw status of system OCP interrupt.
Write 1 to set the (raw) status, mostly for debug.
0 reg_err_sys R/W 0h Raw status of system OCP interrupt.
Write 1 to set the (raw) status, mostly for debug.

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7.3.5.26 IRQSTATUS_SYS Register (offset = ACh) [reset = 0h]

IRQSTATUS_SYS is shown in Figure 7-229 and described in Table 7-247.
Figure 7-229. IRQSTATUS_SYS Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED reg_ta_sys reg_err_sys
Table 7-247. IRQSTATUS_SYS Register Field Descriptions

31-3 RESERVED R 0h
1 reg_ta_sys R/W 0h Enabled status of system OCP interrupt.
Write 1 to clear the status after interrupt has been serviced (raw
status gets cleared, i.e.
even if not enabled).
0 reg_err_sys R/W 0h Enabled status of system OCP interrupt.
Write 1 to clear the status after interrupt has been serviced (raw
status gets cleared, i.e.
even if not enabled).

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7.3.5.27 IRQENABLE_SET_SYS Register (offset = B4h) [reset = 0h]

IRQENABLE_SET_SYS is shown in Figure 7-230 and described in Table 7-248.
Figure 7-230. IRQENABLE_SET_SYS Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED reg_en_ta_sys reg_en_err_sys
Table 7-248. IRQENABLE_SET_SYS Register Field Descriptions

31-3 RESERVED R 0h
1 reg_en_ta_sys R/W 0h Enable set for system OCP interrupt.
Writing a 1 will enable the interrupt, and set this bit as well as the
corresponding Interrupt Enable Clear Register.
0 reg_en_err_sys R/W 0h Enable set for system OCP interrupt.
Writing a 1 will enable the interrupt, and set this bit as well as the
corresponding Interrupt Enable Clear Register.

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7.3.5.28 IRQENABLE_CLR_SYS Register (offset = BCh) [reset = 0h]

IRQENABLE_CLR_SYS is shown in Figure 7-231 and described in Table 7-249.
Figure 7-231. IRQENABLE_CLR_SYS Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED reg_en_ta_sys reg_en_err_sys
Table 7-249. IRQENABLE_CLR_SYS Register Field Descriptions

31-3 RESERVED R 0h
1 reg_en_ta_sys R/W 0h Enable clear for system OCP interrupt.
Writing a 1 will disable the interrupt, and clear this bit as well as the
corresponding Interrupt Enable Set Register.
0 reg_en_err_sys R/W 0h Enable clear for system OCP interrupt.
Writing a 1 will disable the interrupt, and clear this bit as well as the
corresponding Interrupt Enable Set Register.

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7.3.5.29 ZQ_CONFIG Register (offset = C8h) [reset = 0h]

ZQ_CONFIG is shown in Figure 7-232 and described in Table 7-250.
Figure 7-232. ZQ_CONFIG Register

31 30 29 28 27 26 25 24
reg_zq_cs1en reg_zq_cs0en reg_zq_dualcal reg_zq_sfexiten RESERVED
en
R/W-0h R/W-0h R/W-0h R/W-0h R-0h
23 22 21 20 19 18 17 16
RESERVED reg_zq_zqinit_mult reg_zq_zqcl_mult
R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
reg_zq_refinterval
R/W-0h
7 6 5 4 3 2 1 0
reg_zq_refinterval
R/W-0h
Table 7-250. ZQ_CONFIG Register Field Descriptions

31 reg_zq_cs1en R/W 0h Writing a 1 enables ZQ calibration for CS1.
30 reg_zq_cs0en R/W 0h Writing a 1 enables ZQ calibration for CS0.
29 reg_zq_dualcalen R/W 0h ZQ Dual Calibration enable.
Allows both ranks to be ZQ calibrated simultaneously.
Setting this bit requires both chip selects to have a seerate
calibration resistor per device.
28 reg_zq_sfexiten R/W 0h ZQCL on Self Refresh, Active Power-Down, and Precharge Power-
Down exit enable.
Writing a 1 enables the issuing of ZQCL on Self-Refresh, Active
Power-Down, and Precharge Power-Down exit.
27-20 RESERVED R 0h
19-18 reg_zq_zqinit_mult R/W 0h Indicates the number of ZQCL intervals that make up a ZQINIT
interval, minus one.
17-16 reg_zq_zqcl_mult R/W 0h Indicates the number of ZQCS intervals that make up a ZQCL
interval, minus one.
ZQCS interval is defined by reg_zq_zqcs in SDRAM Timing 3
Register.
15-0 reg_zq_refinterval R/W 0h Number of refresh periods between ZQCS commans.
This field supports between one refresh period to 256 ms between
ZQCS calibration commands.
Refresh period is defined by reg_refresh_rate in SDRAM Refresh
Control register.

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7.3.5.30 Read-Write Leveling Ramp Window Register (offset = D4h) [reset = 0h]
Read-Write Leveling Ramp Window is shown in Figure 7-233 and described in Table 7-251.
Figure 7-233. Read-Write Leveling Ramp Window Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED REG_RDWRLVLINC_RMP_WIN
R- R-
Table 7-251. Read-Write Leveling Ramp Window Register Field Descriptions

31-13 RESERVED R Reserved.
12-0 REG_RDWRLVLINC_RM R Incremental leveling ramp window in number of refresh periods.
P_WIN The value programmed is minus one the required value.
Control register.

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7.3.5.31 Read-Write Leveling Ramp Control Register (offset = D8h) [reset = 0h]
Read-Write Leveling Ramp Control is shown in Figure 7-234 and described in Table 7-252.
Figure 7-234. Read-Write Leveling Ramp Control Register

31 30 29 28 27 26 25 24
REG_RDWRLV REG_RDWRLVLINC_RMP_PRE
L_EN
R/W-
23 22 21 20 19 18 17 16
REG_RDLVLINC_RMP_INT
R/W-
15 14 13 12 11 10 9 8
REG_RDLVLGATEINC_RMP_INT
R/W-
7 6 5 4 3 2 1 0
REG_WRLVLINC_RMP_INT
Table 7-252. Read-Write Leveling Ramp Control Register Field Descriptions

31 REG_RDWRLVL_EN R/W Read-Write Leveling enable.
Set 1 to enable leveling.
Set 0 to disable leveling.
30-24 REG_RDWRLVLINC_RM Incremental leveling pre-scalar in number of refresh periods during
P_PRE ramp window.
The value programmed is minus one the required value.
Control register.
23-16 REG_RDLVLINC_RMP_I R/W Incremental read data eye training interval during ramp window.
NT Number of reg_rdwrlvlinc_rmp_pre intervals between incremental
read data eye training.
A value of 0 will disable incremental read data eye training during
ramp window.
15-8 REG_RDLVLGATEINC_R R/W Incremental read DQS gate training interval during ramp window.
MP_INT Number of reg_rdwrlvlinc_rmp_pre intervals between incremental
read DQS gate training.
A value of 0 will disable incremental read DQS gate training during
ramp window.
7-0 REG_WRLVLINC_RMP_I Incremental write leveling interval during ramp window.
NT Number of reg_rdwrlvlinc_rmp_pre intervals between incremental
write leveling.
A value of 0 will disable incremental write leveling during ramp
window.

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7.3.5.32 Read-Write Leveling Control Register (offset = DCh) [reset = 0h]

Read-Write Leveling Control is shown in Figure 7-235 and described in Table 7-253.
Read-Write Leveling Control Register
Figure 7-235. Read-Write Leveling Control Register

31 30 29 28 27 26 25 24
REG_RDWRLV REG_RDWRLVLINC_PRE
LFULL_START
R/W- R/W-
23 22 21 20 19 18 17 16
REG_RDLVLINC_INT
R/W-
15 14 13 12 11 10 9 8
REG_RDLVLGATEINC_INT
R/W-
7 6 5 4 3 2 1 0
REG_WRLVLINC_INT
R/W-
Table 7-253. Read-Write Leveling Control Register Field Descriptions

31 REG_RDWRLVLFULL_S R/W Full leveling trigger.
TART Writing a 1 to this field triggers full read and write leveling.
This bit will self-clear to 0.
30-24 REG_RDWRLVLINC_PR R/W Incremental leveling pre-scalar in number of refresh periods.
E The value programmed is minus one the required value.
Control register.
23-16 REG_RDLVLINC_INT R/W Incremental read data eye training interval.
Number of reg_rdwrlvlinc_pre intervals between incremental read
data eye training.
A value of 0 will disable incremental read data eye training.
15-8 REG_RDLVLGATEINC_I R/W Incremental read DQS gate training interval.
NT Number of reg_rdwrlvlinc_pre intervals between incremental read
DQS gate training.
A value of 0 will disable incremental read DQS gate training.
7-0 REG_WRLVLINC_INT R/W Incremental write leveling interval.
Number of reg_rdwrlvlinc_pre intervals between incremental write
leveling.
A value of 0 will disable incremental write leveling.

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7.3.5.33 DDR_PHY_CTRL_1 Register (offset = E4h) [reset = 0h]

DDR_PHY_CTRL_1 is shown in Figure 7-236 and described in Table 7-254.
A write to the DDR PHY Control 1 register must be followed by a write to the SDRAM_CONFIG register to
ensure that the control update/acknowledge protocol is performed on the DID. If CAS latency = 5, the
minimum read latency = 5 + 2 = 7 and reg_read_latency must be programmed as 7 - 1 = 6. The maximum
read latency = 5 + 7 = 12 and reg_read_latency must be programmed as 12 - 1 = 11.
Figure 7-236. DDR_PHY_CTRL_1 Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED reg_phy_enabl RESERVED
e_dynamic_pwr
dn
15 14 13 12 11 10 9 8
reg_phy_rst_n RESERVED reg_phy_idle_local_odt reg_phy_wr_local_odt reg_phy_rd_local_odt
7 6 5 4 3 2 1 0
RESERVED reg_read_latency
R/W-0h R/W-0h
Table 7-254. DDR_PHY_CTRL_1 Register Field Descriptions

20 reg_phy_enable_dynamic R/W 0h Dynamically enables powering down the IO receiver when not
_pwrdn performing a read.
0 = IO receivers always powered up.
1 = IO receives only powered up during a read.
15 reg_phy_rst_n R/W 0h Writing a 1 to this bit will hold the PHY macros in reset.
Writing a 0 will bring PHY macros out of reset.
13-12 reg_phy_idle_local_odt R/W 0h Value to drive on the
2-bit local_odt (On-Die Termination) PHY outputs when
reg_phy_dynamic_pwrdn_enable is asserted and a read is not in
progress and reg_phy_dynamic_pwrdn_enable.
Typically this is the value required to disable termination (00) to save
power when idle.
11-10 reg_phy_wr_local_odt R/W 0h This bit controls the value assigned to the reg_phy_wr_local_odt
input on the data macros.
Always set to 00.

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Table 7-254. DDR_PHY_CTRL_1 Register Field Descriptions (continued)

9-8 reg_phy_rd_local_odt R/W 0h Value to drive on the
2-bit local_odt (On-Die Termination) PHY outputs when output
enable is not asserted and a read is in progress (where in progress
is defined as after a read command is issued and until all read data
has been returned all the way to the controller.) Typically this is set
to the value required to enable termination at the desired strength for
read usage.
00 = ODT off.
01 = ODT off.
10 = Full thevenin load
Effective ODT is equivalent to 1x the output driver impedance setting
in DDR_DATAx_IOCTRL.io_config_i register bits.
11 = Half thevenin load
Effective ODT is equivalent to 2x the output driver impedance setting
in DDR_DATAx_IOCTRL.io_config_i register bits..
4-0 reg_read_latency R/W 0h This field defines the latency for read data from DDR SDRAM in
number of DDR clock cycles.
The value applied should be equal to the required value minus one.
The maximum read latency supported by the DDR PHY is equal to
CAS latency plus 7 clock cycles.
The minimum read latency must be equal to CAS latency plus 2
clock cycle.

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7.3.5.34 DDR_PHY_CTRL_1_SHDW Register (offset = E8h) [reset = 0h]

DDR_PHY_CTRL_1_SHDW is shown in Figure 7-237 and described in Table 7-255.
A write to the DDR PHY Control 1 register must be followed by a write to the SDRAM_CONFIG register to
ensure that the control update/acknowledge protocol is performed on the DID. If CAS latency = 5, the
minimum read latency = 5 + 2 = 7 and reg_read_latency must be programmed as 7 - 1 = 6. The maximum
read latency = 5 + 7 = 12 and reg_read_latency must be programmed as 12 - 1 = 11.
Figure 7-237. DDR_PHY_CTRL_1_SHDW Register

31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED reg_phy_enabl RESERVED
e_dynamic_pwr
dn
15 14 13 12 11 10 9 8
reg_phy_rst_n RESERVED reg_phy_idle_local_odt reg_phy_wr_local_odt reg_phy_rd_local_odt
7 6 5 4 3 2 1 0
RESERVED reg_read_latency
R/W-0h R/W-0h
Table 7-255. DDR_PHY_CTRL_1_SHDW Register Field Descriptions

20 reg_phy_enable_dynamic R/W 0h Dynamically enables powering down the IO receiver when not
_pwrdn performing a read.
0 = IO receivers always powered up.
1 = IO receives only powered up during a read.
15 reg_phy_rst_n R/W 0h Writing a 1 to this bit will hold the PHY macros in reset.
Writing a 0 will bring PHY macros out of reset.
13-12 reg_phy_idle_local_odt R/W 0h Value to drive on the
2-bit local_odt PHY outputs when reg_phy_dynamic_pwrdn_enable
is asserted and a read is not in progress and
reg_phy_dynamic_pwrdn_enable.
Typically this is the value required to disable termination (00) to save
power when idle.
11-10 reg_phy_wr_local_odt R/W 0h This bit controls the value assigned to the reg_phy_wr_local_odt
input on the data macros.
Always set to 00.
9-8 reg_phy_rd_local_odt R/W 0h Value to drive on the
2-bit local_odt PHY outputs when output enable is not asserted and
a read is in progress (where in progress is defined as after a read
command is issued and until all read data has been returned all the
way to the controller.) Typically this is set to the value required to
enable termination at the desired strength for read usage.
00 = ODT off.
01 = ODT off.
10 = Full thevenin load.
11 = Half thevenin load.

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Table 7-255. DDR_PHY_CTRL_1_SHDW Register Field Descriptions (continued)

4-0 reg_read_latency R/W 0h This field defines the latency for read data from DDR SDRAM in
number of DDR clock cycles.
The value applied should be equal to the required value minus one.
The maximum read latency supported by the DDR PHY is equal to
CAS latency plus 7 clock cycles.
The minimum read latency must be equal to CAS latency plus 2
clock cycle.

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7.3.5.35 Priority to Class of Service Mapping Register (offset = 100h) [reset = 0h]
Priority to Class of Service Mapping is shown in Figure 7-238 and described in Table 7-256.
Figure 7-238. Priority to Class of Service Mapping Register

31 30 29 28 27 26 25 24
REG_PRI_COS RESERVED
_MAP_EN
R/W- R-
23 22 21 20 19 18 17 16
RESERVED
R-
15 14 13 12 11 10 9 8
REG_PRI_7_COS REG_PRI_6_COS REG_PRI_5_COS REG_PRI_4_COS
R/W- R/W- R/W- R/W-
7 6 5 4 3 2 1 0
REG_PRI_3_COS REG_PRI_2_COS REG_PRI_1_COS REG_PRI_0_COS
R/W- R/W- R/W- R/W-
Table 7-256. Priority to Class of Service Mapping Register Field Descriptions

31 REG_PRI_COS_MAP_EN R/W Set 1 to enable priority to class of service mapping.
Set 0 to disable mapping.
15-14 REG_PRI_7_COS R/W Class of service for commands with priority of 7.
Value can be 1 or 2.
Setting a value of 0 or 3 will not assign any class of service.

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7.3.5.36 Connection ID to Class of Service 1 Mapping Register (offset = 104h) [reset = 0h]
Connection ID to Class of Service 1 Mapping is shown in Figure 7-239 and described in Table 7-257.
Figure 7-239. Connection ID to Class of Service 1 Mapping Register

31 30 29 28 27 26 25 24
REG_CONNID REG_CONNID_1_COS_1
_COS_1_MAP_
EN
R/W- R/W-
23 22 21 20 19 18 17 16
REG_CONNID REG_MSK_1_COS_1 REG_CONNID_2_COS_1
_1_COS_1
R/W- R/W- R/W-
15 14 13 12 11 10 9 8
REG_CONNID_2_COS_1 REG_MSK_2_COS_1 REG_CONNID_3_COS_1
R/W- R/W- R/W-
7 6 5 4 3 2 1 0
REG_CONNID_3_COS_1 REG_MSK_3_COS_1
R/W- R/W-
Table 7-257. Connection ID to Class of Service 1 Mapping Register Field Descriptions

31 REG_CONNID_COS_1_ R/W Set 1 to enable connection ID to class of service 1 mapping.
MAP_EN Set 0 to disable mapping.
30-23 REG_CONNID_1_COS_1 R/W Connection ID value 1 for class of service 1.
22-20 REG_MSK_1_COS_1 R/W Mask for connection ID value 1 for class of service 1.
0 = disable masking.
1 = mask connection ID bit 0.
2 = mask connection ID bits
1:0.
2:0.
3:0.
4:0.
5:0.
6:0.
11-10 REG_MSK_2_COS_1 R/W Mask for connection ID value 2 for class of service 1.
1:0.
2:0.
1-0 REG_MSK_3_COS_1 R/W Mask for connection ID.
Value 3 for class of service 1.
1:0.
2:0.

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7.3.5.37 Connection ID to Class of Service 2 Mapping Register (offset = 108h) [reset = 0h]
Connection ID to Class of Service 2 Mapping is shown in Figure 7-240 and described in Table 7-258.
Figure 7-240. Connection ID to Class of Service 2 Mapping Register

31 30 29 28 27 26 25 24
REG_CONNID REG_CONNID_1_COS_2
_COS_2_MAP_
EN
R/W- R/W-
23 22 21 20 19 18 17 16
REG_CONNID REG_MSK_1_COS_2 REG_CONNID_2_COS_2
_1_COS_2
R/W- R/W- R/W-
15 14 13 12 11 10 9 8
REG_CONNID_2_COS_2 REG_MSK_2_COS_2 REG_CONNID_3_COS_2
R/W- R/W- R/W-
7 6 5 4 3 2 1 0
REG_CONNID_3_COS_2 REG_MSK_3_COS_2
R/W- R/W-
Table 7-258. Connection ID to Class of Service 2 Mapping Register Field Descriptions

31 REG_CONNID_COS_2_ R/W Set 1 to enable connection ID to class of service 2 mapping.
MAP_EN Set 0 to disable mapping.
2= mask connection ID bits
1:0.
3= mask connection ID bits
2:0.
3:0.
4:0.
5:0.
6:0.
1:0.
2:0.
1:0.
2:0.

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7.3.5.38 Read Write Execution Threshold Register (offset = 120h) [reset = 00000305h]
Read Write Execution Threshold is shown in Figure 7-241 and described in Table 7-259.
Figure 7-241. Read Write Execution Threshold Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED REG_WR_THRSH RESERVED REG_RD_THRSH
R- R/W- R- R/W-
Table 7-259. Read Write Execution Threshold Register Field Descriptions

12-8 REG_WR_THRSH R/W Write Threshold.
Number of SDRAM write bursts after which the EMIF arbitration will
switch to executing read commands.
The value programmed is always minus one the required number.
4-0 REG_RD_THRSH R/W Read Threshold.
Number of SDRAM read bursts after which the EMIF arbitration will
switch to executing write commands.
The value programmed is always minus one the required number.

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7.3.6 DDR2/3/mDDR PHY Registers

Table 7-260 lists the memory-mapped registers for the DDR2/3 mDDR PHY. Configure the DDR PHY
Control Register for calibration of board delay and other parameters to get the SDRAM device working at
a different speed.
Note: These registers are write-only due to a silicon bug. The contents of these registers cannot be read.
Table 7-260. Memory-Mapped Registers for DDR2/3/mDDR PHY

Register Name Type Register Register Address
Description Reset Offset
CMD0_REG_PHY_CTRL_SLAVE_RATIO_0 W DDR PHY Command 0x80 0x01C
0 Address/Command
Slave Ratio Register
CMD0_REG_PHY_DLL_LOCK_DIFF_0 W DDR PHY Command 0x4 0x028
0 Address/Command
DLL Lock Difference
Register
CMD0_REG_PHY_INVERT_CLKOUT_0 W DDR PHY Command 0x0 0x02C
0 Invert Clockout
Selection Register
CMD1_REG_PHY_CTRL_SLAVE_RATIO_0 W DDR PHY Command 0x80 0x050
1 Address/Command
CMD1_REG_PHY_DLL_LOCK_DIFF_0 W DDR PHY Command 0x4 0x05C
1 Address/Command
DLL Lock Difference
Register
CMD1_REG_PHY_INVERT_CLKOUT_0 W DDR PHY Command 0x0 0x060
1 Invert Clockout
Selection Register
CMD2_REG_PHY_CTRL_SLAVE_RATIO_0 W DDR PHY Command 0x80 0x084
2 Address/Command
CMD2_REG_PHY_DLL_LOCK_DIFF_0 W DDR PHY Command 0x4 0x090
2 Address/Command
DLL Lock Difference
Register
CMD2_REG_PHY_INVERT_CLKOUT_0 W DDR PHY Command 0x0 0x094
2 Invert Clockout
Selection Register
DATA0_REG_PHY_RD_DQS_SLAVE_RATIO W DDR PHY Data Macro 0x04010040 0x0C8
_0 0 Read DQS Slave
Ratio Register
DATA0_REG_PHY_WR_DQS_SLAVE_RATI W DDR PHY Data Macro 0x0 0x0DC
O_0 0 Write DQS Slave
Ratio Register
DATA0_REG_PHY_WRLVL_INIT_RATIO_0 W DDR PHY Data Macro 0x0 0x0F0
0 Write Leveling Init
Ratio Register
DATA0_REG_PHY_WRLVL_INIT_MODE_0 W DDR PHY Data Macro 0x0 0x0F8
Mode Ratio Selection
Register
DATA0_REG_PHY_GATELVL_INIT_RATIO_0 W DDR PHY Data Macro 0x0 0x0FC
0 DQS Gate Training
Init Ratio Register
DATA0_REG_PHY_GATELVL_INIT_MODE_0 W DDR PHY Data Macro 0x0 0x104
0 DQS Gate Training
Init Mode Ratio
Selection Register

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Table 7-260. Memory-Mapped Registers for DDR2/3/mDDR PHY (continued)

Register Name Type Register Register Address
DATA0_REG_PHY_FIFO_WE_SLAVE_RATI W DDR PHY Data Macro 0x0 0x108
O_0 0 DQS Gate Slave
Ratio Register
DATA0_REG_PHY_DQ_OFFSET_0 W Offset value from 0x40 0x11C
DQS to DQ for Data
Macro 0
DATA0_REG_PHY_WR_DATA_SLAVE_RATI W DDR PHY Data Macro 0x04010040 0x120
O_0 0 Write Data Slave
Ratio Register
DATA0_REG_PHY_USE_RANK0_DELAYS W DDR PHY Data Macro 0x0 0x134
0 Delay Selection
Register
DATA0_REG_PHY_DLL_LOCK_DIFF_0 W DDR PHY Data Macro 0x4 0x138
0 DLL Lock Difference
Register
DATA1_REG_PHY_RD_DQS_SLAVE_RATIO W DDR PHY Data Macro 0x04010040 0x16C
_0 1 Read DQS Slave
Ratio Register
DATA1_REG_PHY_WR_DQS_SLAVE_RATI W DDR PHY Data Macro 0x0 0x180
O_0 1 Write DQS Slave
Ratio Register
DATA1_REG_PHY_WRLVL_INIT_RATIO_0 W DDR PHY Data Macro 0x0 0x194
Ratio Register
DATA1_REG_PHY_WRLVL_INIT_MODE_0 W DDR PHY Data Macro 0x0 0x19C
Mode Ratio Selection
Register
DATA1_REG_PHY_GATELVL_INIT_RATIO_0 W DDR PHY Data Macro 0x0 0x1A0
1 DQS Gate Training
Init Ratio Register
DATA1_REG_PHY_GATELVL_INIT_MODE_0 W DDR PHY Data Macro 0x0 0x1A8
1 DQS Gate Training
Init Mode Ratio
Selection Register
DATA1_REG_PHY_FIFO_WE_SLAVE_RATI W DDR PHY Data Macro 0x0 0x1AC
O_0 1 DQS Gate Slave
Ratio Register
DATA1_REG_PHY_DQ_OFFSET_0 W Offset value from 0x40 0x1C0
DQS to DQ for Data
Macro 1
DATA1_REG_PHY_WR_DATA_SLAVE_RATI W DDR PHY Data Macro 0x04010040 0x1C4
O_0 1 Write Data Slave
Ratio Register
DATA1_REG_PHY_USE_RANK0_DELAYS W DDR PHY Data Macro 0x0 0x1D8
1 Delay Selection
Register
DATA1_REG_PHY_DLL_LOCK_DIFF_0 W DDR PHY Data Macro 0x4 0x1DC
1 DLL Lock Difference
Register

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7.3.6.1 DDR PHY Command 0/1/2 Address/Command Slave Ratio Register

(CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0)
The DDR PHY Command 0/1/2 Address/Command Slave Ratio Register
(CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0) is shown in the figure and table below.
Figure 7-242. DDR PHY Command 0/1/2 Address/Command Slave Ratio Register
(CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0)
31 16
Reserved
R-0
15 10 9 0
Reserved CMD_SLAVE_RATIO
R-0 W-100h
Table 7-261. DDR PHY Command 0/1/2 Address/Command Slave Ratio Register
(CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0) Field Descriptions
9-0 CMD_SLAVE_RATIO 0-100h Ratio value for address/command launch timing in DDR PHY macro. This is the fraction of a
clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other
words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to
get the delay value for the slave delay line.
7.3.6.2 DDR PHY Command 0/1/2 Address/Command DLL Lock Difference

Register(CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0)
The DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register
(CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0) is shown in the figure and table below. This register should
be left at its default value and should not be altered for proper operation.
Figure 7-243. DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register
(CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0)
31 16
Reserved
R-0
15 4 3 0
Reserved DLL_LOCK_DIFF
R-0 W-4h
Table 7-262. DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register
(CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0) Field Descriptions
3-0 DLL_LOCK_DIFF 0-4h The max number of delay line taps variation allowed while maintaining the master DLL lock.This is
calculated as total jitter/ delay line tap size, where total jitter is half of (incoming clock jitter (pp) +
delay line jitter (pp)).

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7.3.6.3 DDR PHY Command 0/1/2 Invert Clockout Selection Register(

CMD0/1/2_REG_PHY_INVERT_CLKOUT_0)
The CDDR PHY Command 0/1/2 Invert Clockout Selection Register(
CMD0/1/2_REG_PHY_INVERT_CLKOUT_0) is shown in the figure and table below.
Figure 7-244. DDR PHY Command 0/1/2 Invert Clockout Selection Register(
CMD0/1/2_REG_PHY_INVERT_CLKOUT_0)
31 16
Reserved
R-0
15 1 0
Reserved INVERT_CLK_SEL
R-0 W-0
Table 7-263. DDR PHY Command 0/1/2 Invert Clockout Selection Register(
CMD0/1/2_REG_PHY_INVERT_CLKOUT_0) Field Descriptions
0 INVERT_CLK_SE Inverts the polarity of DRAM clock.
L
0 Core clock is passed on to DRAM
1 inverted core clock is passed on to DRAM
7.3.6.4 DDR PHY Data Macro 0/1 Read DQS Slave Ratio Register
(DATA0/1_REG_PHY_RD_DQS_SLAVE_RATIO_0)
The DDR PHY Data Macro 0/1 Read DQS Slave Ratio
Register(DATA0/1_REG_PHY_RD_DQS_SLAVE_RATIO_0) is shown in the figure and table below.
Figure 7-245. DDR PHY Data Macro 0/1 Read DQS Slave Ratio Register
(DATA0/1_REG_PHY_RD_DQS_SLAVE_RATIO_0))
31 i 19 16
Reserved Reserved
R-0h R-0h
15 10 9 0
Reserved RD_DQS_SLAVE_RATIO_CS0
R-0h W-40h
Table 7-264. DDR PHY Data Macro 0/1 Read DQS Slave Ratio Register
(DATA0/1_REG_PHY_RD_DQS_SLAVE_RATIO_0) Field Descriptions
19-10 Reserved 0h Reserved
9-0 RD_DQS_SLAVE Ratio value for Read DQS slave DLL for CS0.
_RATIO_CS0
40h This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of
256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number
over 256 to get the delay value for the slave delay line.

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7.3.6.5 DDR PHY Data Macro 0/1 Write DQS Slave Ratio Register
(DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0)
The DDR PHY Data Macro 0/1 Write DQS Slave Ratio
Register(DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0) is shown in the figure and table below.
Table 7-265. DDR PHY Data Macro 0/1 Write DQS Slave Ratio Register
(DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0)
31 20 19 16
Reserved Reserved
R-0 R-0h
15 10 9 0
Reserved WR_DQS_SLAVE_RATIO_CS0
R-0 W-0h
Table 7-266. DDR PHY Data Macro 0/1 Write DQS Slave Ratio Register(
DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0) Field Descriptions
9-0 WR_DQS_SLAVE_R Ratio value for Write DQS slave DLL for CS0.
ATIO_CS0
This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in
units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by
this number over 256 to get the delay value for the slave delay line.
7.3.6.6 DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0)
The DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0) is showin in the figure and table below.
Figure 7-246. DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0)
31 20 19 16
Reserved Reserved
R-0 R-0
15 10 9 0
Reserved WRLVL_INIT_RATIO_CS0
R-0 W-0
Table 7-267. DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0) Field Descriptions
9-0 WRLVL_INIT_RATIO 0h The user programmable init ratio used by Write Leveling FSM when
_CS0 DATA0/1_REG_PHY_WRLVL_INIT_MODE_0 register value set to 1

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7.3.6.7 DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_WRLVL_INIT_MODE_0)
The DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_WRLVL_INIT_MODE_0) is shown in the figure and table below..
Figure 7-247. DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
31 16
Reserved
R-0
15 1 0
Reserved WRLVL_INIT_MODE_S
EL
R-0 W-0
Table 7-268. DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
0 WRLVL_INIT_MO The user programmable init ratio selection mode for Write Leveling FSM.
DE_SEL
0 Selects a starting ratio value based on Write Leveling of previous data slice.
1 Selects a starting ratio value based in register DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0 value
programmed by the user.
7.3.6.8 DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0)
The DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0) is shown in the figure and table below.
Figure 7-248. DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0)
31 20 19 16
Reserved Reserved
R-0 R-0
15 10 9 0
Reserved GATELVL_INIT_RATIO_CS0
R-0 W-0
Table 7-269. DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0) Field Descriptions
9-0 GATELVL_INIT_RATIO_CS0 0h The user programmable init ratio used by DQS Gate Training FSM when
DATA0/1/_REG_PHY_GATELVL_INIT_MODE_0 register value set to 1.

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7.3.6.9 DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_GATELVL_INIT_MODE_0)
The DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection
Register(DATA0/1_REG_PHY_GATELVL_INIT_MODE_0) is shown in the figure and table below.
Figure 7-249. DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_GATELVL_INIT_MODE_0)
31 16
Reserved
R-0
15 1 0
Reserved GATELVL _INIT _MODE_SEL
R-0 W-0
Table 7-270. DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_GATELVL_INIT_MODE_0) Field Descriptions
0 GATELVL_INIT_MODE_SEL User programmable init ratio selection mode for DQS Gate Training FSM.
0 Selects a starting ratio value based on Write Leveling of the same data slice.
1 selects a starting ratio value based on
DATA0/1_REG_PHY_GATELVL_INIT_RATIO_0 value programmed by the user.
7.3.6.10 DDR PHY Data Macro 0/1 DQS Gate Slave Ratio Register
(DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0)
The DDR PHY Data Macro 0/1 DQS Gate Slave Ratio Register
(DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) is shown in the figure and table below.
Figure 7-250. DDR PHY Data Macro 0/1 DQS Gate Slave Ratio
Register(DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0)
31 20 19 16
Reserved Reserved
R-0 R-0
15 10 9 0
Reserved FIFO_WE_SLAVE_RATIO_CS0
R-0 W-0
Table 7-271. DDR PHY Data Macro 0/1 DQS Gate Slave Ratio Register
(DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) Field Descriptions
9-0 RD_DQS_GATE _SLAVE_RATIO_CS0 0h Ratio value for fifo we for CS0.

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7.3.6.11 DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0)
The DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0) is shown in the figure and table below.
Figure 7-251. DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0)
31 20 19 16
Reserved Reserved
R-40h R-0h
15 10 9 0
Reserved WR_DATA_SLAVE_RATIO_CS0
R-0h W-40h
Table 7-272. DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0) Field Descriptions
19-10 Reserved 0
9-0 WR_DATA_SLAVE_RATIO_CS0 40h Ratio value for write data slave DLL for CS0.
This is the fraction of a clock cycle represented by the shift to be applied to
the write DQ muxes in units of 256ths. In other words, the full-cycle tap
value from the master DLL will be scaled by this number over 256 to get the
delay value for the slave delay line.

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7.3.6.12 DDR PHY Data Macro 0/1 Delay Selection Register (DATA0/1_REG_PHY_USE_RANK0_DELAYS)
The DATA0/1_REG_PHY_USE_RANK0_DELAYS is shown in Figure 7-252 and described in Table 7-273.
Figure 7-252. DDR PHY Data Macro 0/1 Delay Selection Register
(DATA0/1_REG_PHY_USE_RANK0_DELAYS)
31 16
Reserved
R-0
15 1 0
Reserved RANK0 _DELAY
R-0 W-0
Table 7-273. DDR PHY Data Macro 0/1 Delay Selection Register
(DATA0/1_REG_PHY_USE_RANK0_DELAYS) Field Descriptions
0 PHY_USE_RANK Delay Selection
0_DELAYS_0
0 Each Rank uses its own delay. (Recommended). This is applicable only in case of DDR3
1 Rank 0 delays are used for all ranks. This must be set to 1 for DDR2 and mDDR.
7.3.6.13 DDR PHY Data 0/1 DLL Lock Difference Register (DATA0/1_REG_PHY_DLL_LOCK_DIFF_0)
The DDR PHY Data 0/1 DLL Lock Difference Register (DATA0/1_REG_PHY_DLL_LOCK_DIFF_0) is
shown in the figure and table below. This register should be left at its default value and should not be
altered for proper operation.
Figure 7-253. DDR PHY Data 0/1 DLL Lock Difference Register
(DATA0/1_REG_PHY_DLL_LOCK_DIFF_0)
31 16
Reserved
R-0
15 4 3 0
Reserved DLL_LOCK_DIFF
R-0 W-4h
Table 7-274. DDR PHY Data 0/1 DLL Lock Difference Register
(DATA0/1_REG_PHY_DLL_LOCK_DIFF_0) Field Descriptions
3-0 DLL_LOCK_DIFF 0-4h The max number of delay line taps variation allowed while maintaining the master DLL lock.This is
calculated as total jitter/ delay line tap size, where total jitter is half of (incoming clock jitter (pp) +
delay line jitter (pp)).
7.3.6.14 Offset value from DQS to DQ for Data Macro Register (DATA0/DATA1
_REG_PHY_DQ_OFFSET_0)
The Offset value from DQS to DQ for Data Macro Register (DATA0/DATA1 _REG_PHY_DQ_OFFSET_0)
is shown in the figure and table below.

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Figure 7-254. Offset value from DQS to DQ for Data Macro Register (DATA0/DATA1
_REG_PHY_DQ_OFFSET_0)
31 16
Reserved
R-0
15 7 6 0
Reserved Offset value from DQS to DQ
R-0 RW-4h
Table 7-275. Offset value from DQS to DQ for Data Macro Register (DATA0/DATA1
_REG_PHY_DQ_OFFSET_0) Field Descriptions
6-0 Offset value from 0h Default value 40 equates to a 90 degree shift.
DQS to DQ

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7.4 ELM
7.4.1 Introduction
Non-managed NAND flash memories can be dense and nonvolatile in their own nature, but error-prone.
When reading from NAND flash memories, some level of error-correction is required. In the case of NAND
modules with no internal correction capability, sometimes referred to as bare NANDs, the correction
process is delegated to the memory controller.
The general-purpose memory controller (GPMC) probes data read from an external NAND flash and uses
this to compute checksum-like information, called syndrome polynomials, on a per-block basis. Each
syndrome polynomial gives a status of the read operations for a full block, including 512 bytes of data,
parity bits, and an optional spare-area data field, with a maximum block size of 1023 bytes. Computation
is based on a Bose-ChaudhurI-Hocquenghem (BCH) algorithm. The error-location module (ELM) extracts
error addresses from these syndrome polynomials.
Based on the syndrome polynomial value, the ELM can detect errors, compute the number of errors, and
give the location of each error bit. The actual data is not required to complete the error-correction
algorithm. Errors can be reported anywhere in the NAND flash block, including in the parity bits.
The maximum acceptable number of errors that can be corrected depends on a programmable
configuration parameter. 4-, 8-, and 16-bit error-correction levels are supported. The ELM relies on a static
and fixed definition of the generator polynomial for each error-correction level that corresponds to the
generator polynomials defined in the GPMC (there are three fixed polynomial for the three correction error
levels). A larger number of errors than the programmed error-correction level may be detected, but the
ELM cannot correct them all. The offending block is then tagged as uncorrectable in the associated
computation exit status register. If the computation is successful, that is, if the number of errors detected
does not exceed the maximum value authorized for the chosen correction capability, the exit status
register contains the information on the number of detected errors.
When the error-location process completes, an interrupt is triggered to inform the central processing unit
(CPU) that its status can be checked. The number of detected errors and their locations in the NAND
block can be retrieved from the module through register accesses.
7.4.1.1 ELM Features

The ELM has the following features:
• 4, 8, and 16 bits per 512-byte block error-location based on BCH algorithms
• Eight simultaneous processing contexts
• Page-based and continuous modes
• Interrupt generation on error-location process completion:
– When the full page has been processed in page mode
– For each syndrome polynomial in continuous mode
7.4.1.2 Unsupported ELM Features

There are no unsupported ELM features in this device.

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7.4.2 Integration
The error location module (ELM) is used to extract error addresses from syndrome polynomials generated
using a BCH algorithm. Each of these polynomials gives a status of the read operations for a 512 bytes
block from a NAND flash and its associated BCH parity bits, plus optionally some spare area information.
The ELM is intended to be used in conjunction with the GPMC. Syndrome polynomials generated on-the-
fly when reading a NAND Flash page and stored in GPMC registers are passed to the ELM module. The
MPU can then easily correct the data block by flipping the bits pointed to by the ELM error locations
outputs.
L4 Peripheral Error Location

Interconnect Module
MPU Subsystem POROCPSINTERRUPT
PORSIDLEACK[1:0]
PIMIDLEREQ
Figure 7-255. ELM Integration
7.4.2.1 ELM Connectivity Attributes

The general connectivity for the ELM module in this device is summarized in Table 7-276.
Table 7-276. ELM Connectivity Attributes

Attributes Type
Clock Domain L4PER_L4LS_GCLK
Interrupt Requests 1 interrupt to MPU Subsystem
DMA Requests None
Physical Address L4 Peripheral slave port
7.4.2.2 ELM Clock and Reset Management

The ELM operates from a single OCP interface clock.
Table 7-277. ELM Clock Signals

Functional/interface clock 100 MHz CORE_CLKOUTM4 / 2 pd_per_l4ls_gclk
From PRCM
7.4.2.3 ELM Pin List

The ELM module does not include any external interface pins.

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7.4.3 Functional Description

The ELM is designed around the error-location engine, which handles the computation based on the input
syndrome polynomials.
The ELM maps the error-location engine to a standard interconnect interface by using a set of registers to
control inputs and outputs.
7.4.3.1 ELM Software Reset

To perform a software reset, write a 1 to the ELM_SYSCONFIG[1] SOFTRESET bit. The
ELM_SYSSTATUS[0] RESETDONE bit indicates that the software reset is complete when its value is 1.
When the software reset completes, the ELM_SYSCONFIG[1] SOFTRESET bit is automatically reset.
7.4.3.2 ELM Power Management

Table 7-278 describes the power-management features available to the ELM module.
Table 7-278. Local Power Management Features

Feature Registers Description
Clock autogating ELM_SYSCONFIG[0] This bit allows a local power optimization inside the module by
AUTOGATING bit gating the ELM_FCLK clock upon the interface activity.
Slave idle modes ELM_SYSCONFIG[4:3] Force-idle, No-idle, and Smart-idle modes are available.
SIDLEMODE bit field
Clock activity ELM_SYSCONFIG[8] The clock can be switched-off or maintained during the wake-up
CLOCKACTIVITY bit period.
Master Standby modes N/A
Global Wake-up Enable N/A
Wake-up Sources Enable N/A
CAUTION
The PRCM module has no hardware means of reading CLOCKACTIVITY
settings. Thus, software must ensure consistent programming between the
ELM CLOCKACTIVITY and ELM clock PRCM control bits.
7.4.3.3 ELM Interrupt Requests

Table 7-279 lists the event flags, and their masks, that can cause module interrupts.
Table 7-279. Events

Event Flag Event Mask Map to Description
ELM_IRQSTATUS[8] ELM_IRQENABLE[8] ELM_IRQ Page interrupt
PAGE_VALID PAGE_MASK
ELM_IRQSTATUS[7] ELM_IRQENABLE[7] ELM_IRQ Error-location interrupt for syndrome polynomial 7
LOC_VALID_7 LOCATION_MASK_7

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Table 7-279. Events (continued)

Event Flag Event Mask Map to Description
7.4.3.4 Processing Initialization

ELM_LOCATION_CONFIG global setting parameters must be set before using the error-location engine.
The ELM_LOCATION_CONFIG[1:0] ECC_BCH_LEVEL bit defines the error-correction level used (4-,8-,
or 16-bit error-correction). The ELM_LOCATION_CONFIG[26:16] ECC_SIZE bit field defines the
maximum buffer length beyond which the engine processing no longer looks for errors.
The CPU can choose to use the ELM in continuous mode or page mode. If all ELM_PAGE_CTRL[i]
SECTOR_i bits are reset (i is the syndrome polynomial number, i = 0 to 7), continuous mode is used. In
any other case, page mode is implicitly selected.
• Continuous mode: Each syndrome polynomial is processed independently – results for a syndrome
can be retrieved and acknowledged at any time, whatever the status of the other seven processing
contexts.
• Page mode: Syndrome polynomials are grouped into atomic entities – only one page can be
processed at any given time, even if all eight contexts are not used for this page. Unused contexts are
lost and cannot be affected to any other processing. The full page must be acknowledged and cleared
before moving to the next page.
For completion interrupts to be generated correctly, all ELM_IRQENABLE[i] LOCATION_MASK_i bits (i =
0 to 7) must be forced to 0 when in page mode, and set to 1 in continuous mode. Additionally, the
ELM_IRQENABLE[8] PAGE_MASK bit must be set to 1 when in page mode.
The CPU initiates error-location processing by writing a syndrome polynomial into one of the eight
possible register sets. Each of these register sets includes seven registers:
ELM_SYNDROME_FRAGMENT_0_i to ELM_SYNDROME_FRAGMENT_6_i. The first six registers can
be written in any order, but ELM_SYNDROME_FRAGMENT_6_i must be written last because it includes
the validity bit, which instructs the ELM that this syndrome polynomial must be processed (the
ELM_SYNDROME_FRAGMENT_6_i[16] SYNDROME_VALID bit).
As soon as one validity bit is asserted (ELM_SYNDROME_FRAGMENT_6_i[16] SYNDROME_VALID =
0x1, with i = 0 to 7), error-location processing can start for the corresponding syndrome polynomial. The
associated ELM_LOCATION_STATUS_i and ELM_ERROR_LOCATION_0_i to
ELM_ERROR_LOCATION_15_i registers are not reset (i = 0 to 7). The software must not consider them
until the corresponding ELM_IRQSTATUS[i] LOC_VALID_i bit is set.
7.4.3.5 Processing Sequence

While the error-location engine is busy processing one syndrome polynomial, further syndrome
polynomials can be written. They are processed when the current processing completes.
The engine completes early when:
• No error is detected; that is, when the ELM_LOCATION_STATUS_i[8] ECC_CORRECTABLE bit is set
to 1 and the ELM_LOCATION_STATUS_i[4:0] ECC_NB_ERRORS bit field is set to 0x0.
• Too many errors are detected; that is, when the ELM_LOCATION_STATUS_i[8]
ECC_CORRECTABLE bit is set to 0 while the ELM_LOCATION_STATUS_i[4:0] ECC_NB_ERRORS
bit field is set with the value output by the error-location engine. The reported number of errors is not
ensured if ECC_CORRECTABLE is 0.
If the engine completes early, the associated error-location registers ELM_ERROR_LOCATION_0_i to
ELM_ERROR_LOCATION_15_i are not updated (i = 0 to 7).

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In all other cases, the engine goes through the entire error-location process. Each time an error-location is
found, it is logged in the associated ECC_ERROR_LOCATION bit field. The first error detected is logged
in the ELM_ERROR_LOCATION_0_i[12:0] ECC_ERROR_LOCATION bit field; the second in the
ELM_ERROR_LOCATION_1_i[12:0] ECC_ERROR_LOCATION bit field, and so on.
Table 7-280. ELM_LOCATION_STATUS_i Value Decoding Table

ECC_CORRECT ECC_NB_ERRORS Status Number of Errors Action Required
ABLE Value Value Detected
1 0 OK 0 None
1 ≠0 OK ECC_NB_ERRORS Correct the data buffer read based on the
ELM_ERROR_LOCATION_0_i to
ELM_ERROR_LOCATION_15_i results.
0 Any Failed Unknown Software-dependant
7.4.3.6 Processing Completion

When the processing for a given syndrome polynomial completes, its
ELM_SYNDROME_FRAGMENT_6_i[16] SYNDROME_VALID bit is reset. It must not be set again until
the exit status registers, ELM_LOCATION_STATUS_i (i = 0 to 7), for this processing are checked. Failure
to comply with this rule leads to potential loss of the first polynomial process data output.
The error-location engine signals the process completion to the ELM. When this event is detected, the
corresponding ELM_IRQSTATUS[i] LOC_VALID_i bit is set (i = 0 to 7). The processing-exit status is
available from the associated ELM_LOCATION_STATUS_i register, and error locations are stored in order
in the ECC_ERROR_LOCATION fields. The software must only read valid error-location registers based
on the number of errors detected and located.
Immediately after the error-location engine completes, a new syndrome polynomial can be processed, if
any is available, as reported by the ELM_SYNDROME_FRAGMENT_6_i[16] SYNDROME_VALID validity
bit, depending on the configured error-correction level. If several syndrome polynomials are available, a
round-robin arbitration is used to select one for processing.
In continuous mode (that is, all bits in ELM_PAGE_CTRL are reset), an interrupt is triggered whenever a
ELM_IRQSTATUS[i] LOC_VALID_i bit is asserted. The CPU must read the ELM_IRQSTATUS register to
determine which polynomial is processed and retrieve the exit status and error locations
(ELM_LOCATION_STATUS_i and ELM_ERROR_LOCATION_0_i to ELM_ERROR_LOCATION_15_i).
When done, the CPU must clear the corresponding ELM_IRQSTATUS[i] LOC_VALID_i bit by writing it to
1. Other status bits must be written to 0 so that other interrupts are not unintentionally cleared. When
using this mode, the ELM_IRQSTATUS[8] PAGE_VALID interrupt is never triggered.
In page mode, the module does not trigger interrupts for the processing completion of each polynomial
because the ELM_IRQENABLE[i] LOCATION_MASK_i bits are cleared. A page is defined using the
ELM_PAGE_CTRL register. Each SECTOR_i bit set means the corresponding polynomial i is part of the
page processing. A page is fully processed when all tagged polynomials have been processed, as logged
in the ELM_IRQSTATUS[i] LOC_VALID_i bit fields. The module triggers an ELM_IRQSTATUS[8]
PAGE_VALID interrupt whenever it detects that the full page has been processed. To make sure the next
page can be correctly processed, all status bits in the ELM_IRQSTATUS register must be cleared by
using a single atomic-write access.
NOTE: Do not modify page setting parameters in the ELM_PAGE_CTRL register unless the engine
is idle, no polynomial input is valid, and all interrupts have been cleared.
Because no polynomial-level interrupt is triggered in page mode, polynomials cleared in the

ELM_PAGE_CTRL[i] SECTOR_i bit fields (i = 0 to 7) are processed as usual, but are essentially ignored.
The CPU must manually poll the ELM_IRQSTATUS bits to check for their status.

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7.4.4 Basic Programming Model
7.4.4.1 ELM Low Level Programming Model
7.4.4.1.1 Processing Initialization
Table 7-281. ELM Processing Initialization

Step Register/ Bit Field / Programming Model Value
Resets the module ELM_SYSCONFIG[1] SOFTRESET 0x1
Wait until reset is done. ELM_SYSSTATUS[0] RESETDONE 0x1
Configure the slave interface power management. ELM_SYSCONFIG[4:3] SIDLEMODE Set value
Defines the error-correction level used ELM_LOCATION_CONFIG[1:0] ECC_BCH_LEVEL Set value
Defines the maximum buffer length ELM_LOCATION_CONFIG[26:16] ECC_SIZE Set value
Sets the ELM in continuous mode or page mode ELM_PAGE_CTRL Set value
If continuous mode is used All ELM_PAGE_CTRL[i] SECTOR_i (i = 0 to 7) 0x0
Enables interrupt for syndrome polynomial i ELM_IRQENABLE[i] LOCATION_MASK_i 0x1
else (page mode is used) One syndrome polynomial i is set ELM_PAGE_CTRL[i] 0x1
SECTOR_i (i = 0 to 7)
Disable all interrupts for syndrome polynomial and All ELM_IRQENABLE[i] LOCATION_MASK_i = 0x0 and Set value
enable PAGE_MASK interrupt. ELM_IRQENABLE[8] PAGE_MASK = 0x1
endif Set value
Set the input syndrome polynomial i. ELM_SYNDROME_FRAGMENT_0_i Set value
ELM_SYNDROME_FRAGMENT_1_i Set value
Initiates the computation process ELM_SYNDROME_FRAGMENT_6_i[16] 0x1
SYNDROME_VALID
7.4.4.1.2 Read Results

The engine goes through the entire error-location process and results can be read. Table 7-282 and
Table 7-283 describe the processing completion for continuous and page modes, respectively.
Table 7-282. ELM Processing Completion for Continuous Mode

Wait until process is complete for syndrome
polynomial i:
Wait until the ELM_IRQ interrupt is generated, or
poll the status register.
Read for which i the error-location process is ELM_IRQSTATUS[i] LOC_VALID_i 0x1
complete.
if the process fails (too many errors) ELM_LOCATION_STATUS_i[8] ECC_CORRECTABLE 0x0
It is software dependant.
else (process successful, the engine completes) ELM_LOCATION_STATUS_i[8] ECC_CORRECTABLE 0x1
Read the number of errors. ELM_LOCATION_STATUS_i[4:0] ECC_NB_ERRORS
Read the error-location bit addresses for syndrome ELM_ERROR_LOCATION_0_i[12:0]
polynomial i of the ECC_NB_ERRORS first ECC_ERROR_LOCATION
registers.
ELM_ERROR_LOCATION_1_i[12:0]
It is the software responsibility to correct errors in
ECC_ERROR_LOCATION
the data buffer.
...
ECC_ERROR_LOCATION

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Table 7-282. ELM Processing Completion for Continuous Mode (continued)

endif
Clear the corresponding i interrupt. ELM_IRQSTATUS[i] LOC_VALID_i 0x1
A new syndrome polynomial can be processed after the end of processing

(ELM_SYNDROME_FRAGMENT_6_i[16] SYNDROME_VALID = 0x0) and after the exit status register
check (ELM_LOCATION_STATUS_i).
Table 7-283. ELM Processing Completion for Page Mode

polynomial i:
Wait until the ELM_IRQ interrupt is generated, or
Wait for page completed interrupt: ELM_IRQSTATUS[8] PAGE_VALID 0x1
All error locations are valid.
Repeat the following actions the necessary number of times. That is, once for each valid defined block in the page.
Read the process exit status. ELM_LOCATION_STATUS_i[8] ECC_CORRECTABLE
if the process fails (too many errors) ELM_LOCATION_STATUS_i[8] ECC_CORRECTABLE 0x0
It is software dependant.
else (process successful, the engine completes) ELM_LOCATION_STATUS_i[8] ECC_CORRECTABLE 0x1
Read the number of errors. ELM_LOCATION_STATUS_i[4:0] ECC_NB_ERRORS
Read the error-location bit addresses for syndrome ELM_ERROR_LOCATION_0_i[12:0]
polynomial i of the ECC_NB_ERRORS first ECC_ERROR_LOCATION
registers.
ECC_ERROR_LOCATION
...
ECC_ERROR_LOCATION
endif
End Repeat
Clear the ELM_IRQSTATUS register. ELM_IRQSTATUS 0x1FF
Next page can be correctly processed after a page is fully processed, when all tagged polynomials have
been processed (ELM_IRQSTATUS[i] LOC_VALID_i = 0x1 for all syndrome polynomials i used in the
page).
7.4.4.2 Use Case: ELM Used in Continuous Mode

In this example, the ELM module is programmed for an 8-bit error-correction capability in continuous
mode. After reading a 528-byte NAND flash sector (512B data plus 16B spare area) with a 16-bit
interface, a non-zero polynomial syndrome is reported from the GPMC (Polynomial syndrome 0 is used in
the ELM):
• P = 0x0A16ABE115E44F767BFB0D0980
Table 7-284. Use Case: Continuous Mode

Configure the slave interface power management: ELM_SYSCONFIG[4:3] SIDLEMODE 0x2
Smart idle is used.

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Table 7-284. Use Case: Continuous Mode (continued)

Defines the error-correction level used: 8 bits ELM_LOCATION_CONFIG[1:0] ECC_BCH_LEVEL 0x1
Defines the maximum buffer length: 528 bytes ELM_LOCATION_CONFIG[26:16] ECC_SIZE 0x420
(2x528 = 1056)
Sets the ELM in continuous mode ELM_PAGE_CTRL 0
Enables interrupt for syndrome polynomial 0 ELM_IRQENABLE[0] LOCATION_MASK_0 0x1
Set the input syndrome polynomial 0. ELM_SYNDROME_FRAGMENT_0_i (i=0) 0xFB0D0980
ELM_SYNDROME_FRAGMENT_1_i (i=0) 0xE44F767B
ELM_SYNDROME_FRAGMENT_2_i (i=0) 0x16ABE115
ELM_SYNDROME_FRAGMENT_3_i (i=0) 0x0000000A
Initiates the computation process ELM_SYNDROME_FRAGMENT_6_i[16] 0x1
SYNDROME_VALID (i=0)
polynomial 0:
IRQ_ELM is generated or poll the status register.
Read that error-location process is complete for ELM_IRQSTATUS[0] LOC_VALID_0 0x1
syndrome polynomial 0.
Read the process exit status: ELM_LOCATION_STATUS_i[8] ECC_CORRECTABLE 0x1
All errors were successfully located. (i=0)
Read the number of errors: ELM_LOCATION_STATUS_i[4:0] ECC_NB_ERRORS (i=0) 0x4
Four errors detected.
Read the error-location bit addresses for syndrome ELM_ERROR_LOCATION_0_i (i=0) 0x1AF
polynomial 0 of the 4 first registers:
ELM_ERROR_LOCATION_1_i (i=0) 0x426
Errors are located in the data buffer at decimal
addresses 431, 1062, 1909, 3452. ELM_ERROR_LOCATION_2_i (i=0) 0x775
ELM_ERROR_LOCATION_3_i (i=0) 0xD7C
Clear the corresponding interrupt for polynomial 0. ELM_IRQSTATUS[0] LOC_VALID_0 0x1
The NAND flash data in the sector are seen as a polynomial of degree 4223 (number of bits in a 528 byte
buffer minus 1), with each data bit being a coefficient in the polynomial. When reading from a NAND flash
using the GPMC module, computation of the polynomial syndrome assumes that the first NAND word read
at address 0x0 contains the highest-order coefficient in the message. Furthermore, in the 16-bit NAND
word, bits are ordered from bit 7 to bit 0, then from bit 15 to bit 8. Based on this convention, an address
table of the data buffer can be built. NAND memory addresses in Table 7-285 are given in decimal format.

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Table 7-285. 16-bit NAND Sector Buffer Address Map

NAND Message bit addresses in the memory word
Memory
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address
0 4215 4214 4213 4212 4211 4210 4209 4208 4223 4222 4221 4220 4219 4218 4217 4216
1 4175 4174 4173 4172 4171 4170 4169 4168 4183 4182 4181 4180 4179 4178 4177 4176
...
47 3463 3462 3461 3460 3459 3458 3457 3456 3471 3470 3469 3468 3467 3466 3465 3464
48 3447 3446 3445 3444 3443 3442 3441 3440 3455 3454 3453 3452 3451 3450 3449 3448
49 3431 3430 3429 3428 3427 3426 3425 3424 3439 3438 3437 3436 3435 3434 3433 3432
50 3415 3414 3413 3412 3411 3410 3409 3408 3423 3422 3421 3420 3419 3418 3417 3416
...
255 135 134 133 132 131 130 129 128 143 142 141 140 139 138 137 136
256 119 118 117 116 115 114 113 112 127 126 125 124 123 122 121 120
257 103 102 101 100 99 98 97 96 111 110 109 108 107 106 105 104
258 87 86 85 84 83 82 81 80 95 94 93 92 91 90 89 88
259 71 70 69 68 67 66 65 64 79 78 77 76 75 74 73 72
260 55 54 53 52 51 50 49 48 63 62 61 60 59 58 57 56
261 39 38 37 36 35 34 33 32 47 46 45 44 43 42 41 40
262 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
263 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
The table can now be used to determine which bits in the buffer were incorrect and must be flipped. In this
example, the first bit to be flipped is bit 4 from the 49th byte read from memory. It is up to the processor to
correctly map this word to the copied buffer and to flip this bit. The same process must be repeated for all
detected errors.
7.4.4.3 Use Case: ELM Used in Page Mode

In this example, the ELM module is programmed for an 16-bit error-correction capability in page mode.
After reading a 528-byte NAND flash sector (512B data plus 16B spare area) with a 16-bit interface, four
non-zero polynomial syndromes are reported from the GPMC (Polynomial syndrome 0, 1, 2, and 3 are
used in the ELM):
• P0 = 0xE8B0 12ADDB5A318E05BE B0693DB28330B5CC A329AA05E0B718EF
• P1 = 0xBAD0 49A0D932C22E6669 0948DF08BE093336 79C6BA10E5F935EB
• P2 = 0x69D9 B86ABCD5EC3697FA A6498FEE54556EA0 1579EF7D60BA3189
• P3 = 0x0
Table 7-286. Use Case: Page Mode

Configure the slave interface power management: ELM_SYSCONFIG[4:3] SIDLEMODE 0x2
Smart idle is used.
Defines the error-correction level used: 16 bits ELM_LOCATION_CONFIG[1:0] ECC_BCH_LEVEL 0x2
Defines the maximum buffer length: 528 bytes ELM_LOCATION_CONFIG[26:16] ECC_SIZE 0x420
Sets the ELM in page mode (4 blocks in a page) ELM_PAGE_CTRL[0] SECTOR_0 0x1
ELM_PAGE_CTRL[1] SECTOR_1 0x1

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Table 7-286. Use Case: Page Mode (continued)

Disable all interrupts for syndrome polynomial and ELM_IRQENABLE 0x100
enable PAGE_MASK interrupt.
Set the input syndrome polynomial 0. ELM_SYNDROME_FRAGMENT_0_i (i=0) 0xE0B718EF
ELM_SYNDROME_FRAGMENT_1_i (i=0) 0xA329AA05
ELM_SYNDROME_FRAGMENT_2_i (i=0) 0x8330B5CC
ELM_SYNDROME_FRAGMENT_3_i (i=0) 0xB0693DB2
ELM_SYNDROME_FRAGMENT_4_i (i=0) 0x318E05BE
ELM_SYNDROME_FRAGMENT_5_i (i=0) 0x12ADDB5A
ELM_SYNDROME_FRAGMENT_6_i (i=0) 0xE8B0
Set the input syndrome polynomial 1. ELM_SYNDROME_FRAGMENT_0_i (i=1) 0xE5F935EB
ELM_SYNDROME_FRAGMENT_1_i (i=1) 0x79C6BA10
ELM_SYNDROME_FRAGMENT_2_i (i=1) 0xBE093336
ELM_SYNDROME_FRAGMENT_3_i (i=1) 0x0948DF08
ELM_SYNDROME_FRAGMENT_4_i (i=1) 0xC22E6669
ELM_SYNDROME_FRAGMENT_5_i (i=1) 0x49A0D932
ELM_SYNDROME_FRAGMENT_6_i (i=1) 0xBAD0
Set the input syndrome polynomial 2. ELM_SYNDROME_FRAGMENT_0_i (i=2) 0x60BA3189
ELM_SYNDROME_FRAGMENT_1_i (i=2) 0x1579EF7D
ELM_SYNDROME_FRAGMENT_2_i (i=2) 0x54556EA0
ELM_SYNDROME_FRAGMENT_3_i (i=2) 0xA6498FEE
ELM_SYNDROME_FRAGMENT_4_i (i=2) 0xEC3697FA
ELM_SYNDROME_FRAGMENT_5_i (i=2) 0xB86ABCD5
ELM_SYNDROME_FRAGMENT_6_i (i=2) 0x69D9
Set the input syndrome polynomial 3. ELM_SYNDROME_FRAGMENT_0_i (i=3) 0x0
ELM_SYNDROME_FRAGMENT_1_i (i=3) 0x0
Initiates the computation process for syndrome ELM_SYNDROME_FRAGMENT_6_i[16] 0x1
polynomial 0 SYNDROME_VALID (i=0)
polynomial 0, 1, 2, and 3:
Wait until the ELM_IRQ interrupt is generated or
Wait for page completed interrupt: ELM_IRQSTATUS[8] PAGE_VALID 0x1
All error locations are valid.
Read the process exit status for syndrome ELM_LOCATION_STATUS_i[8] ECC_CORRECTABLE 0x1
polynomial 0: (i=0)
All errors were successfully located.
polynomial 1: (i=1)

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Table 7-286. Use Case: Page Mode (continued)

polynomial 2: (i=2)
polynomial 3: (i=3)
Read the number of errors for syndrome ELM_LOCATION_STATUS_i[4:0] ECC_NB_ERRORS 0x4
polynomial 0: (i=0)
4 errors detected.
polynomial 1: (i=1)
2 errors detected.
polynomial 2: (i=2)
1 error detected.
polynomial 3: (i=3)
0 errors detected.
Read the error-location bit addresses for syndrome ELM_ERROR_LOCATION_0_i (i=0) 0x1FE
ELM_ERROR_LOCATION_3_i (i=0) 0xA83
Read the error-location bit addresses for syndrome ELM_ERROR_LOCATION_0_i (i=1) 0x4
Read the errors location bit addresses for ELM_ERROR_LOCATION_0_i (i=1) 0x3E8
syndrome polynomial 2 of the first registers:
Clear the ELM_IRQSTATUS register. ELM_IRQSTATUS 0x1FF
7.4.5 ELM Registers

Table 7-287 lists the memory-mapped registers for the ELM. All register offset addresses not listed in
Table 7-287. ELM Registers

0h ELM_REVISION ELM Revision Register Section 7.4.5.1
10h ELM_SYSCONFIG ELM System Configuration Register Section 7.4.5.2
14h ELM_SYSSTATUS ELM System Status Register Section 7.4.5.3
18h ELM_IRQSTATUS ELM Interrupt Status Register Section 7.4.5.4
1Ch ELM_IRQENABLE ELM Interrupt Enable Register Section 7.4.5.5
20h ELM_LOCATION_CONFIG ELM Location Configuration Register Section 7.4.5.6
80h ELM_PAGE_CTRL ELM Page Definition Register Section 7.4.5.7
400h ELM_SYNDROME_FRAGMENT_0_0 ELM_SYNDROME_FRAGMENT_0_0 Register Section 7.4.5.8
40Ch ELM_SYNDROME_FRAGMENT_3_0 ELM_SYNDROME_FRAGMENT_3_0 Register Section 7.4.5.11

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Table 7-287. ELM Registers (continued)

4C0h ELM_SYNDROME_FRAGMENT_0_3 ELM_SYNDROME_FRAGMENT_0_3 Register Section 7.4.5.29
4CCh ELM_SYNDROME_FRAGMENT_3_3 ELM_SYNDROME_FRAGMENT_3_3 Register Section 7.4.5.32
4D0h ELM_SYNDROME_FRAGMENT_4_3 ELM_SYNDROME_FRAGMENT_4_3 Register Section 7.4.5.33
5CCh ELM_SYNDROME_FRAGMENT_3_7 ELM_SYNDROME_FRAGMENT_3_7 Register Section 7.4.5.60
800h ELM_LOCATION_STATUS_0 ELM_LOCATION_STATUS_0 Register Section 7.4.5.64

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880h ELM_ERROR_LOCATION_0_0 ELM_ERROR_LOCATION_0_0 Register Section 7.4.5.65
88Ch ELM_ERROR_LOCATION_3_0 ELM_ERROR_LOCATION_3_0 Register Section 7.4.5.68
8A0h ELM_ERROR_LOCATION_8_0 ELM_ERROR_LOCATION_8_0 Register Section 7.4.5.73
8ACh ELM_ERROR_LOCATION_11_0 ELM_ERROR_LOCATION_11_0 Register Section 7.4.5.76
8B0h ELM_ERROR_LOCATION_12_0 ELM_ERROR_LOCATION_12_0 Register Section 7.4.5.77
8BCh ELM_ERROR_LOCATION_15_0 ELM_ERROR_LOCATION_15_0 Register Section 7.4.5.80
900h ELM_LOCATION_STATUS_1 ELM_LOCATION_STATUS_1 Register Section 7.4.5.81
9ACh ELM_ERROR_LOCATION_11_1 ELM_ERROR_LOCATION_11_1 Register Section 7.4.5.93
9BCh ELM_ERROR_LOCATION_15_1 ELM_ERROR_LOCATION_15_1 Register Section 7.4.5.97
A00h ELM_LOCATION_STATUS_2 ELM_LOCATION_STATUS_2 Register Section 7.4.5.98
A80h ELM_ERROR_LOCATION_0_2 ELM_ERROR_LOCATION_0_2 Register Section 7.4.5.99
A8Ch ELM_ERROR_LOCATION_3_2 ELM_ERROR_LOCATION_3_2 Register Section 7.4.5.102
A9Ch ELM_ERROR_LOCATION_7_2 ELM_ERROR_LOCATION_7_2 Register Section 7.4.5.106
AA0h ELM_ERROR_LOCATION_8_2 ELM_ERROR_LOCATION_8_2 Register Section 7.4.5.107
AACh ELM_ERROR_LOCATION_11_2 ELM_ERROR_LOCATION_11_2 Register Section 7.4.5.110
AB0h ELM_ERROR_LOCATION_12_2 ELM_ERROR_LOCATION_12_2 Register Section 7.4.5.111

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ABCh ELM_ERROR_LOCATION_15_2 ELM_ERROR_LOCATION_15_2 Register Section 7.4.5.114
B80h ELM_ERROR_LOCATION_0_3 ELM_ERROR_LOCATION_0_3 Register Section 7.4.5.115
B8Ch ELM_ERROR_LOCATION_3_3 ELM_ERROR_LOCATION_3_3 Register Section 7.4.5.118
B9Ch ELM_ERROR_LOCATION_7_3 ELM_ERROR_LOCATION_7_3 Register Section 7.4.5.122
BA0h ELM_ERROR_LOCATION_8_3 ELM_ERROR_LOCATION_8_3 Register Section 7.4.5.123
BACh ELM_ERROR_LOCATION_11_3 ELM_ERROR_LOCATION_11_3 Register Section 7.4.5.126
BB0h ELM_ERROR_LOCATION_12_3 ELM_ERROR_LOCATION_12_3 Register Section 7.4.5.127
BBCh ELM_ERROR_LOCATION_15_3 ELM_ERROR_LOCATION_15_3 Register Section 7.4.5.130
B00h ELM_LOCATION_STATUS_3 ELM_LOCATION_STATUS_3 Register Section 7.4.5.131
C80h ELM_ERROR_LOCATION_0_4 ELM_ERROR_LOCATION_0_4 Register Section 7.4.5.132
C8Ch ELM_ERROR_LOCATION_3_4 ELM_ERROR_LOCATION_3_4 Register Section 7.4.5.135
C9Ch ELM_ERROR_LOCATION_7_4 ELM_ERROR_LOCATION_7_4 Register Section 7.4.5.139
CA0h ELM_ERROR_LOCATION_8_4 ELM_ERROR_LOCATION_8_4 Register Section 7.4.5.140
CACh ELM_ERROR_LOCATION_11_4 ELM_ERROR_LOCATION_11_4 Register Section 7.4.5.143
CB0h ELM_ERROR_LOCATION_12_4 ELM_ERROR_LOCATION_12_4 Register Section 7.4.5.144
CBCh ELM_ERROR_LOCATION_15_4 ELM_ERROR_LOCATION_15_4 Register Section 7.4.5.147
D80h ELM_ERROR_LOCATION_0_5 ELM_ERROR_LOCATION_0_5 Register Section 7.4.5.148
D8Ch ELM_ERROR_LOCATION_3_5 ELM_ERROR_LOCATION_3_5 Register Section 7.4.5.151
D9Ch ELM_ERROR_LOCATION_7_5 ELM_ERROR_LOCATION_7_5 Register Section 7.4.5.155
DA0h ELM_ERROR_LOCATION_8_5 ELM_ERROR_LOCATION_8_5 Register Section 7.4.5.156

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DACh ELM_ERROR_LOCATION_11_5 ELM_ERROR_LOCATION_11_5 Register Section 7.4.5.159
DB0h ELM_ERROR_LOCATION_12_5 ELM_ERROR_LOCATION_12_5 Register Section 7.4.5.160
DBCh ELM_ERROR_LOCATION_15_5 ELM_ERROR_LOCATION_15_5 Register Section 7.4.5.163
C00h ELM_LOCATION_STATUS_4 ELM_LOCATION_STATUS_4 Register Section 7.4.5.164
E80h ELM_ERROR_LOCATION_0_6 ELM_ERROR_LOCATION_0_6 Register Section 7.4.5.165
E8Ch ELM_ERROR_LOCATION_3_6 ELM_ERROR_LOCATION_3_6 Register Section 7.4.5.168
E9Ch ELM_ERROR_LOCATION_7_6 ELM_ERROR_LOCATION_7_6 Register Section 7.4.5.172
EA0h ELM_ERROR_LOCATION_8_6 ELM_ERROR_LOCATION_8_6 Register Section 7.4.5.173
EACh ELM_ERROR_LOCATION_11_6 ELM_ERROR_LOCATION_11_6 Register Section 7.4.5.176
EB0h ELM_ERROR_LOCATION_12_6 ELM_ERROR_LOCATION_12_6 Register Section 7.4.5.177
EBCh ELM_ERROR_LOCATION_15_6 ELM_ERROR_LOCATION_15_6 Register Section 7.4.5.180
F80h ELM_ERROR_LOCATION_0_7 ELM_ERROR_LOCATION_0_7 Register Section 7.4.5.181
F8Ch ELM_ERROR_LOCATION_3_7 ELM_ERROR_LOCATION_3_7 Register Section 7.4.5.184
F9Ch ELM_ERROR_LOCATION_7_7 ELM_ERROR_LOCATION_7_7 Register Section 7.4.5.188
FA0h ELM_ERROR_LOCATION_8_7 ELM_ERROR_LOCATION_8_7 Register Section 7.4.5.189
FACh ELM_ERROR_LOCATION_11_7 ELM_ERROR_LOCATION_11_7 Register Section 7.4.5.192
FB0h ELM_ERROR_LOCATION_12_7 ELM_ERROR_LOCATION_12_7 Register Section 7.4.5.193
FBCh ELM_ERROR_LOCATION_15_7 ELM_ERROR_LOCATION_15_7 Register Section 7.4.5.196
D00h ELM_LOCATION_STATUS_5 ELM_LOCATION_STATUS_5 Register Section 7.4.5.197
E00h ELM_LOCATION_STATUS_6 ELM_LOCATION_STATUS_6 Register Section 7.4.5.198
F00h ELM_LOCATION_STATUS_7 ELM_LOCATION_STATUS_7 Register Section 7.4.5.199

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7.4.5.1 ELM_REVISION Register (offset = 0h) [reset = 0h]

ELM_REVISION is shown in Figure 7-256 and described in Table 7-288.
This register contains the IP revision code.
Figure 7-256. ELM_REVISION Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REVISION
R-0h
Table 7-288. ELM_REVISION Register Field Descriptions

31-0 REVISION R 0h IP Revision, value 0 to FFFF FFFFh.

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7.4.5.2 ELM_SYSCONFIG Register (offset = 10h) [reset = 11h]

ELM_SYSCONFIG is shown in Figure 7-257 and described in Table 7-289.
This register allows controlling various parameters of the OCP interface.
Figure 7-257. ELM_SYSCONFIG Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED CLOCKACTIVI
TYOCPz
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED SIDLEMODE RESERVED SOFTRESET AUTOGATING
Table 7-289. ELM_SYSCONFIG Register Field Descriptions

31-9 RESERVED R 0h
8 CLOCKACTIVITYOCPz R/W 0h OCP Clock activity when module is in IDLE mode (during wake up
mode period).
0h = OCP Clock can be switch-off
1h = OCP Clock is maintained during wake up period
7-5 RESERVED R 0h
4-3 SIDLEMODE R/W 2h Slave interface power management (IDLE req/ack control).
0h = FORCE Idle. IDLE request is acknowledged unconditionally and
immediately. (Default Dumb mode for safety)
1h = NO idle. IDLE request is never acknowledged.
2h = SMART Idle. The acknowledgment to an IDLE request is given
based on the internal activity.
3h = Reserved - do not use
2 RESERVED R 0h
1 SOFTRESET R/W 0h Module software reset.
This bit is automatically reset by hardware (During reads, it always
returns 0.).
It has same effect as the OCP hardware reset.
0h = Normal mode.
1h = Start soft reset sequence.
0 AUTOGATING R/W 1h Internal OCP clock gating strategy.
(No module visible impact other than saving power.)
0h = OCP clock is free-running.
1h = Automatic internal OCP clock gating strategy is applied based
on the OCP interface activity.

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7.4.5.3 ELM_SYSSTATUS Register (offset = 14h) [reset = 0h]

ELM_SYSSTATUS is shown in Figure 7-258 and described in Table 7-290.
Figure 7-258. ELM_SYSSTATUS Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RESETDONE
R-0h R-0h
Table 7-290. ELM_SYSSTATUS Register Field Descriptions

31-1 RESERVED R 0h
0 RESETDONE R 0h Internal reset monitoring (OCP domain).
Undefined since: From hardware perspective, the reset state is 0.
From software user perspective, when the accessible module is 1.
0h = Reset is on-going
1h = Reset is done (completed)

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7.4.5.4 ELM_IRQSTATUS Register (offset = 18h) [reset = 0h]

ELM_IRQSTATUS is shown in Figure 7-259 and described in Table 7-291.
This register doubles as a status register for the error-location processes.
Figure 7-259. ELM_IRQSTATUS Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED PAGE_VALID
R-0h R/W-0h
7 6 5 4 3 2 1 0
LOC_VALID_7 LOC_VALID_6 LOC_VALID_5 LOC_VALID_4 LOC_VALID_3 LOC_VALID_2 LOC_VALID_1 LOC_VALID_0
Table 7-291. ELM_IRQSTATUS Register Field Descriptions

31-9 RESERVED R 0h
8 PAGE_VALID R/W 0h Error-location status for a full page, based on the mask definition.
0h (W) = Write: No effect.
0h (R) = Read: Error locations invalid for all polynomials enabled in
the ECC_INTERRUPT_MASK register.
1h (W) = Write: Clear interrupt.
1h (R) = Read: All error locations valid.
7 LOC_VALID_7 R/W 0h Error-location status for syndrome polynomial 7.
0h (R) = Read: No syndrome processed or process in progress.
1h (R) = Read: Error-location process completed.

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Table 7-291. ELM_IRQSTATUS Register Field Descriptions (continued)

0h (W) = No effect.
0h (R) = No syndrome processed or process in progress.
1h (W) = Clear interrupt.
1h (R) = Error-location process completed.

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7.4.5.5 ELM_IRQENABLE Register (offset = 1Ch) [reset = 0h]

ELM_IRQENABLE is shown in Figure 7-260 and described in Table 7-292.
Figure 7-260. ELM_IRQENABLE Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED PAGE_MASK
R-0h R/W-0h
7 6 5 4 3 2 1 0
LOCATION_M LOCATION_M LOCATION_M LOCATION_M LOCATION_M LOCATION_M LOCATION_M LOCATION_M
ASK_7 ASK_6 ASK_5 ASK_4 ASK_3 ASK_2 ASK_1 ASK_0
Table 7-292. ELM_IRQENABLE Register Field Descriptions

31-9 RESERVED R 0h
8 PAGE_MASK R/W 0h Page interrupt mask bit
0h = Disable interrupt.
1h = Enable interrupt.
7 LOCATION_MASK_7 R/W 0h Error-location interrupt mask bit for syndrome polynomial 7.

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7.4.5.6 ELM_LOCATION_CONFIG Register (offset = 20h) [reset = 0h]

ELM_LOCATION_CONFIG is shown in Figure 7-261 and described in Table 7-293.
Figure 7-261. ELM_LOCATION_CONFIG Register

31 30 29 28 27 26 25 24
RESERVED ECC_SIZE
R-0h R/W-0h
23 22 21 20 19 18 17 16
ECC_SIZE
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ECC_BCH_LEVEL
R-0h R/W-0h
Table 7-293. ELM_LOCATION_CONFIG Register Field Descriptions

31-27 RESERVED R 0h
26-16 ECC_SIZE R/W 0h Maximum size of the buffers for which the error-location engine is
used, in number of nibbles (4 bits entities), value 0 to 7FFh.
15-2 RESERVED R 0h
1-0 ECC_BCH_LEVEL R/W 0h Error correction level.
0h = 4 bits.
1h = 8 bits.
2h = 16 bits.
3h = Reserved.

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7.4.5.7 ELM_PAGE_CTRL Register (offset = 80h) [reset = 0h]

ELM_PAGE_CTRL is shown in Figure 7-262 and described in Table 7-294.
Figure 7-262. ELM_PAGE_CTRL Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
SECTOR_7 SECTOR_6 SECTOR_5 SECTOR_4 SECTOR_3 SECTOR_2 SECTOR_1 SECTOR_0
Table 7-294. ELM_PAGE_CTRL Register Field Descriptions

31-8 RESERVED R 0h
7 SECTOR_7 R/W 0h Set to 1 if syndrome polynomial 7 is part of the page in page mode.
Must be 0 in continuous mode.

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7.4.5.8 ELM_SYNDROME_FRAGMENT_0_0 Register (offset = 400h) [reset = 0h]

ELM_SYNDROME_FRAGMENT_0_0 is shown in Figure 7-263 and described in Table 7-295.
Figure 7-263. ELM_SYNDROME_FRAGMENT_0_0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_0
R/W-0h
Table 7-295. ELM_SYNDROME_FRAGMENT_0_0 Register Field Descriptions

31-0 SYNDROME_0 R/W 0h Syndrome bits 0 to 31, value 0 to FFFF FFFFh.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_1
R/W-0h


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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_2
R/W-0h


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7.4.5.11 ELM_SYNDROME_FRAGMENT_3_0 Register (offset = 40Ch) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_3
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_4
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_5
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED SYNDROME_V
ALID
R-0h R/W-0h
15 14 13 12 11 10 9 8
SYNDROME_6
R/W-0h
7 6 5 4 3 2 1 0
SYNDROME_6
R/W-0h

31-17 RESERVED R 0h
16 SYNDROME_VALID R/W 0h Syndrome valid bit.
0h = This syndrome polynomial should not be processed.
1h = This syndrome polynomial must be processed.
15-0 SYNDROME_6 R/W 0h Syndrome bits 192 to 207, value 0 to FFFFh.

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_0
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_1
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_2
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_3
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_4
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_5
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED SYNDROME_V
ALID
R-0h R/W-0h
15 14 13 12 11 10 9 8
SYNDROME_6
R/W-0h
7 6 5 4 3 2 1 0
SYNDROME_6
R/W-0h

31-17 RESERVED R 0h

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_0
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_1
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_2
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_3
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_4
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_5
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED SYNDROME_V
ALID
R-0h R/W-0h
15 14 13 12 11 10 9 8
SYNDROME_6
R/W-0h
7 6 5 4 3 2 1 0
SYNDROME_6
R/W-0h

31-17 RESERVED R 0h

ELM www.ti.com
7.4.5.29 ELM_SYNDROME_FRAGMENT_0_3 Register (offset = 4C0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_0
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_1
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_2
R/W-0h


www.ti.com ELM
7.4.5.32 ELM_SYNDROME_FRAGMENT_3_3 Register (offset = 4CCh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_3
R/W-0h


ELM www.ti.com
7.4.5.33 ELM_SYNDROME_FRAGMENT_4_3 Register (offset = 4D0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_4
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_5
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED SYNDROME_V
ALID
R-0h R/W-0h
15 14 13 12 11 10 9 8
SYNDROME_6
R/W-0h
7 6 5 4 3 2 1 0
SYNDROME_6
R/W-0h

31-17 RESERVED R 0h

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_0
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_1
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_2
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_3
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_4
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_5
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED SYNDROME_V
ALID
R-0h R/W-0h
15 14 13 12 11 10 9 8
SYNDROME_6
R/W-0h
7 6 5 4 3 2 1 0
SYNDROME_6
R/W-0h

31-17 RESERVED R 0h

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_0
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_1
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_2
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_3
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_4
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_5
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED SYNDROME_V
ALID
R-0h R/W-0h
15 14 13 12 11 10 9 8
SYNDROME_6
R/W-0h
7 6 5 4 3 2 1 0
SYNDROME_6
R/W-0h

31-17 RESERVED R 0h

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_0
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_1
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_2
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_3
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_4
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_5
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED SYNDROME_V
ALID
R-0h R/W-0h
15 14 13 12 11 10 9 8
SYNDROME_6
R/W-0h
7 6 5 4 3 2 1 0
SYNDROME_6
R/W-0h

31-17 RESERVED R 0h

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_0
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_1
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_2
R/W-0h


www.ti.com ELM
7.4.5.60 ELM_SYNDROME_FRAGMENT_3_7 Register (offset = 5CCh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_3
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_4
R/W-0h


www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNDROME_5
R/W-0h


ELM www.ti.com


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED SYNDROME_V
ALID
R-0h R/W-0h
15 14 13 12 11 10 9 8
SYNDROME_6
R/W-0h
7 6 5 4 3 2 1 0
SYNDROME_6
R/W-0h

31-17 RESERVED R 0h

www.ti.com ELM
7.4.5.64 ELM_LOCATION_STATUS_0 Register (offset = 800h) [reset = 0h]

ELM_LOCATION_STATUS_0 is shown in Figure 7-319 and described in Table 7-351.
Figure 7-319. ELM_LOCATION_STATUS_0 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED ECC_CORREC
TABL
R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED ECC_NB_ERRORS
R-0h R-0h
Table 7-351. ELM_LOCATION_STATUS_0 Register Field Descriptions

31-9 RESERVED R 0h
8 ECC_CORRECTABL R 0h Error-location process exit status.
0h = ECC error-location process failed. Number of errors and error
locations are invalid.
1h = All errors were successfully located. Number of errors and error
locations are valid.
7-5 RESERVED R 0h
4-0 ECC_NB_ERRORS R 0h Number of errors detected and located, value 0 to 1Fh.

ELM www.ti.com
7.4.5.65 ELM_ERROR_LOCATION_0_0 Register (offset = 880h) [reset = 0h]

ELM_ERROR_LOCATION_0_0 is shown in Figure 7-320 and described in Table 7-352.
Figure 7-320. ELM_ERROR_LOCATION_0_0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ECC_ERROR_LOCATION
R-0h R-0h
Table 7-352. ELM_ERROR_LOCATION_0_0 Register Field Descriptions

31-13 RESERVED R 0h
12-0 ECC_ERROR_LOCATIO R 0h Error-location bit address, 0 to 1FFFh.
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.68 ELM_ERROR_LOCATION_3_0 Register (offset = 88Ch) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.73 ELM_ERROR_LOCATION_8_0 Register (offset = 8A0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.76 ELM_ERROR_LOCATION_11_0 Register (offset = 8ACh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.77 ELM_ERROR_LOCATION_12_0 Register (offset = 8B0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.80 ELM_ERROR_LOCATION_15_0 Register (offset = 8BCh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.81 ELM_LOCATION_STATUS_1 Register (offset = 900h) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED ECC_CORREC
TABL
R-0h R-0h
7 6 5 4 3 2 1 0
R-0h R-0h

31-9 RESERVED R 0h
7-5 RESERVED R 0h

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.93 ELM_ERROR_LOCATION_11_1 Register (offset = 9ACh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.97 ELM_ERROR_LOCATION_15_1 Register (offset = 9BCh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.98 ELM_LOCATION_STATUS_2 Register (offset = A00h) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED ECC_CORREC
TABL
R-0h R-0h
7 6 5 4 3 2 1 0
R-0h R-0h

31-9 RESERVED R 0h
7-5 RESERVED R 0h

ELM www.ti.com
7.4.5.99 ELM_ERROR_LOCATION_0_2 Register (offset = A80h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.102 ELM_ERROR_LOCATION_3_2 Register (offset = A8Ch) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.106 ELM_ERROR_LOCATION_7_2 Register (offset = A9Ch) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.107 ELM_ERROR_LOCATION_8_2 Register (offset = AA0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.110 ELM_ERROR_LOCATION_11_2 Register (offset = AACh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.111 ELM_ERROR_LOCATION_12_2 Register (offset = AB0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.114 ELM_ERROR_LOCATION_15_2 Register (offset = ABCh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.115 ELM_ERROR_LOCATION_0_3 Register (offset = B80h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.118 ELM_ERROR_LOCATION_3_3 Register (offset = B8Ch) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.122 ELM_ERROR_LOCATION_7_3 Register (offset = B9Ch) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.123 ELM_ERROR_LOCATION_8_3 Register (offset = BA0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.126 ELM_ERROR_LOCATION_11_3 Register (offset = BACh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.127 ELM_ERROR_LOCATION_12_3 Register (offset = BB0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.130 ELM_ERROR_LOCATION_15_3 Register (offset = BBCh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.131 ELM_LOCATION_STATUS_3 Register (offset = B00h) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED ECC_CORREC
TABL
R-0h R-0h
7 6 5 4 3 2 1 0
R-0h R-0h

31-9 RESERVED R 0h
7-5 RESERVED R 0h

www.ti.com ELM
7.4.5.132 ELM_ERROR_LOCATION_0_4 Register (offset = C80h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.135 ELM_ERROR_LOCATION_3_4 Register (offset = C8Ch) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.139 ELM_ERROR_LOCATION_7_4 Register (offset = C9Ch) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.140 ELM_ERROR_LOCATION_8_4 Register (offset = CA0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.143 ELM_ERROR_LOCATION_11_4 Register (offset = CACh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.144 ELM_ERROR_LOCATION_12_4 Register (offset = CB0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.147 ELM_ERROR_LOCATION_15_4 Register (offset = CBCh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.148 ELM_ERROR_LOCATION_0_5 Register (offset = D80h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.151 ELM_ERROR_LOCATION_3_5 Register (offset = D8Ch) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.155 ELM_ERROR_LOCATION_7_5 Register (offset = D9Ch) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.156 ELM_ERROR_LOCATION_8_5 Register (offset = DA0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.159 ELM_ERROR_LOCATION_11_5 Register (offset = DACh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.160 ELM_ERROR_LOCATION_12_5 Register (offset = DB0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.163 ELM_ERROR_LOCATION_15_5 Register (offset = DBCh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.164 ELM_LOCATION_STATUS_4 Register (offset = C00h) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED ECC_CORREC
TABL
R-0h R-0h
7 6 5 4 3 2 1 0
R-0h R-0h

31-9 RESERVED R 0h
7-5 RESERVED R 0h

ELM www.ti.com
7.4.5.165 ELM_ERROR_LOCATION_0_6 Register (offset = E80h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.168 ELM_ERROR_LOCATION_3_6 Register (offset = E8Ch) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.172 ELM_ERROR_LOCATION_7_6 Register (offset = E9Ch) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.173 ELM_ERROR_LOCATION_8_6 Register (offset = EA0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.176 ELM_ERROR_LOCATION_11_6 Register (offset = EACh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.177 ELM_ERROR_LOCATION_12_6 Register (offset = EB0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.180 ELM_ERROR_LOCATION_15_6 Register (offset = EBCh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.181 ELM_ERROR_LOCATION_0_7 Register (offset = F80h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.184 ELM_ERROR_LOCATION_3_7 Register (offset = F8Ch) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.188 ELM_ERROR_LOCATION_7_7 Register (offset = F9Ch) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.189 ELM_ERROR_LOCATION_8_7 Register (offset = FA0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.192 ELM_ERROR_LOCATION_11_7 Register (offset = FACh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.193 ELM_ERROR_LOCATION_12_7 Register (offset = FB0h) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

www.ti.com ELM
7.4.5.196 ELM_ERROR_LOCATION_15_7 Register (offset = FBCh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R-0h R-0h

31-13 RESERVED R 0h
N

ELM www.ti.com
7.4.5.197 ELM_LOCATION_STATUS_5 Register (offset = D00h) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED ECC_CORREC
TABL
R-0h R-0h
7 6 5 4 3 2 1 0
R-0h R-0h

31-9 RESERVED R 0h
7-5 RESERVED R 0h

www.ti.com ELM
7.4.5.198 ELM_LOCATION_STATUS_6 Register (offset = E00h) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED ECC_CORREC
TABL
R-0h R-0h
7 6 5 4 3 2 1 0
R-0h R-0h

31-9 RESERVED R 0h
7-5 RESERVED R 0h

ELM www.ti.com
7.4.5.199 ELM_LOCATION_STATUS_7 Register (offset = F00h) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED ECC_CORREC
TABL
R-0h R-0h
7 6 5 4 3 2 1 0
R-0h R-0h

31-9 RESERVED R 0h
7-5 RESERVED R 0h

Chapter 8
Power, Reset, and Clock Management (PRCM)
This chapter describes the PRCM of the device.
Topic ........................................................................................................................... Page
8.1 Power, Reset, and Clock Management ............................................................... 1198
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1197
Power, Reset, and Clock Management www.ti.com
8.1 Power, Reset, and Clock Management
8.1.1 Introduction
The device power-management architecture ensures maximum performance and operation time for user
satisfaction (audio/video support) while offering versatile power-management techniques for maximum
design flexibility, depending on application requirements. This introduction contains the following
information:
• Power-management architecture building blocks for the device
• State-of-the-art power-management techniques supported by the power-management architecture of
the device
8.1.2 Device Power-Management Architecture Building Blocks

To provide a versatile architecture supporting multiple power-management techniques, the power-
management framework is built with three levels of resource management: clock, power, and voltage
management.
These management levels are enforced by defining the managed entities or building blocks of the power-
management architecture, called the clock, power, and voltage domains. A domain is a group of modules
or subsections of the device that share a common entity (for example, common clock source, common
voltage source, or common power switch). The group forming the domain is managed by a policy
manager. For example, a clock for a clock domain is managed by a dedicated clock manager within the
power, reset, and clock management (PRCM) module. The clock manager considers the joint clocking
constraints of all the modules belonging to that clock domain (and, hence, receiving that clock).
8.1.3 Clock Management

The PRCM module along with the control module manages the gating (that is, switching off) and enabling
of the clocks to the device modules. The clocks are managed based on the requirement constraints of the
associated modules. The following sections identify the module clock characteristics, management policy,
clock domains, and clock domain management
8.1.3.1 Module Interface and Functional Clocks

Each module within the device has specific clock input characteristic requirements. Based on the
characteristics of the clocks delivered to the modules, the clocks are divided into two categories: interface
clocks and functional clocks
Figure 8-1. Functional and Interface Clocks
Device interconnect
Interface clock X_ICLK
Registers Interconnect
PRCM interface
Clock generator Module X
Functional clock
X_FCLK
prcm-001
The interface clocks have the following characteristics:

• They ensure proper communication between any module/subsystem and interconnect.
• In most cases, they supply the system interconnect interface and registers of the module.
• A typical module has one interface clock, but modules with multiple interface clocks may also exist
(that is, when connected to multiple interconnect buses).
1198 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
www.ti.com Power, Reset, and Clock Management
• Interface clock management is done at the device level.

• From the standpoint of the PRCM module, an interface clock is identified by an _ICLK suffix.
Functional clocks have the following characteristics:

• They supply the functional part of a module or subsystem.
• A module can have one or more functional clocks. Some functional clocks are mandatory, while others
are optional. A module needs its mandatory clock(s) to be operational. The optional clocks are used for
specific features and can be shut down without stopping the module activity
• From the standpoint of the PRCM module, a functional clock is distributed directly to the related
modules through a dedicated clock tree. It is identified with an _FCLK suffix
8.1.3.2 Module-Level Clock Management

Each module in the device may also have specific clock requirements. Certain module clocks must be
active when operating in specific modes, or may be gated otherwise. Globally, the activation and gating of
the module clocks are managed by the PRCM module. Hence, the PRCM module must be aware of when
to activate and when to gate the module clocks. The PRCM module differentiates the clock-management
behavior for device modules based on whether the module can initiate transactions on the device
interconnect (called master module or initiators) or cannot initiate transactions and only responds to the
transactions initiated by the master (called slave module or targets). Thus, two hardware-based power-
management protocols are used:
• Master standby protocol: Clock-management protocol between the PRCM and master modules.
• Slave idle protocol: Clock-management protocol between the PRCM and slave modules.
8.1.3.2.1 Master Standby Protocol

Master standby protocol is used to indicate that a master module must initiate a transaction on the device
interconnect and requests specific (functional and interface) clocks for the purpose. The PRCM module
ensures that the required clocks are active when the master module requests the PRCM module to enable
them. This is called a module wake-up transition and the module is said to be functional after this
transition completes. Similarly, when the master module no longer requires the clocks, it informs the
PRCM module, which can then gate the clocks to the module. The master module is then said to be in
standby mode. Although the protocol is completely hardware-controlled, software must configure the
clock-management behavior for the module. This is done by setting the module register bit field
<Module>_SYSCONFIG.MIDLEMODE or <Module>_SYSCONFIG.STANDBYMODE. The behavior,
identified by standby mode values, must be configured.
Table 8-1. Master Module Standby-Mode Settings

Standby Mode Value Selected Mode Description
The module unconditionally asserts the
standby request to the PRCM module,
regardless of its internal operations. The
PRCM module may gate the functional
0x0 Force-standby
and interface clocks to the module. This
mode must be used carefully because it
does not prevent the loss of data at the
time the clocks are gated.
The module never asserts the standby
request to the PRCM module. This mode
is safe from a module point of view
because it ensures that the clocks remain
0x1 No-standby
active. However, it is not efficient from a
power-saving perspective because it
never allows the output clocks of the
PRCM module to be gated
Table 8-1. Master Module Standby-Mode Settings (continued)

Standby Mode Value Selected Mode Description
The module asserts the standby request
based on its internal activity status. The
standby signal is asserted only when all
0x2 Smart-standby
ongoing transactions are complete and
the module is idled. The PRCM module
can then gate the clocks to the module.
The module asserts the standby request
based on its internal activity status. The
standby signal is asserted only when all
ongoing transactions are complete and
the module is idle. The PRCM module can
0x3 Smart-standbywakeup-capable mode then gate the clocks to the module. The
module may generate (master-related)
wake-up events when in STANDBY state.
The mode is relevant only if the
appropriate module mwakeup output is
implemented.
The standby status of a master module is indicated by the

CM_<Power_domain>_<Module>_CLKCTRL[x]. STBYST bit in the PRCM module.
Table 8-2. Master Module Standby Status

STBYST Bit Value Description
0x0 The module is functional.
0x1 The module is in standby mode
8.1.3.2.2 Slave Idle Protocol

This hardware protocol allows the PRCM module to control the state of a slave module. The PRCM
module informs the slave module, through assertion of an idle request, when its clocks (interface and
functional) can be gated. The slave can then acknowledge the request from the PRCM module and the
PRCM module is then allowed to gate the clocks to the module. A slave module is said to be in IDLE state
when its clocks are gated by the PRCM module. Similarly, an idled slave module may need to be
wakened because of a service request from a master module or as a result of an event (called a wake-up
event; for example, interrupt or DMA request) received by the slave module. In this situation the PRCM
module enables the clocks to the module and then deasserts the idle request to signal the module to wake
up. Although the protocol is completely hardware-controlled, software must configure the clock-
management behavior for the slave module. This is done by setting the module register bit field
<Module>_SYSCONFIG. SIDLEMODE or <Module>_SYSCONFIG. IDLEMODE. The behavior, listed in
the Idle Mode Value column, must be configured by software.
Table 8-3. Module Idle Mode Settings

Idle Mode Value Selected Mode Description
The module unconditionally acknowledges
the idle request from the PRCM module,
regardless of its internal operations. This
0x0 Force-idle
mode must be used carefully because it
does not prevent the loss of data at the
time the clock is switched off.
The module never acknowledges any idle
request from the PRCM module. This
mode is safe from a module point of view
because it ensures that the clocks remain
0x1 No-idle active. However, it is not efficient from a
power-saving perspective because it does
not allow the PRCM module output clock
to be shut off, and thus the power domain
to be set to a lower power state.
1200Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
Table 8-3. Module Idle Mode Settings (continued)

Idle Mode Value Selected Mode Description
The module acknowledges the idle
request basing its decision on its internal
activity. Namely, the acknowledge signal
is asserted only when all pending
0x2 Smart-idle
transactions, interrupts, or direct memory
access (DMA) requests are processed.
This is the best approach to efficient
system power management.
The module acknowledges the idle
request basing its decision on its internal
wakeup-capable mode activity. Namely,
the acknowledge signal is asserted only
when all pending transactions, interrupts,
or DMA requests are processed. This is
0x3 Smart-idle wakeup-capable mode the best approach to efficient system
power management. The module may
generate (IRQ- or DMA-request-related)
wake-up events when in IDLE state. The
mode is relevant only if the appropriate
module swakeup output(s) is
implemented.
The idle status of a slave module is indicated by the CM_<Powerdomain>_<Module>_CLKCTRL[x]

IDLEST bit field in the PRCM module.
Table 8-4. Idle States for a Slave Module

IDLEST Bit VALUE Idle Status Description
The module is fully functional.The
0x0 Functional
interface and functional clocks are active.
The module is performing a wake-up or a
0x1 In transition
sleep transition.
The module interface clock is idled. The
0x2 Interface idle module may remain functional if using a
separate functional clock.
The module is fully idle. The interface and
0x3 Full idle
functional clocks are gated in the module.
For the idle protocol management on the PRCM module side, the behavior of the PRCM module is
configured in the CM_<Power domain>_<module>_CLKCTRL[x] MODULEMODE bit field. Based on the
configured behavior, the PRCM module asserts the idle request to the module unconditionally (that is,
immediately when the software requests).
Table 8-5. Slave Module Mode Settings in PRCM

MODULEMODE Bit VALUE Selected Mode Description
The PRCM module unconditionally asserts
the module idle request. This request
applies to the gating of the functional and
interface clocks to the module. If
0x0 Disabled
acknowledged by the module, the PRCM
module can gate all clocks to the module
(that is, the module is completely
disabled)..
0x1 Reserved NA
Table 8-5. Slave Module Mode Settings in PRCM (continued)

MODULEMODE Bit VALUE Selected Mode Description
This mode applies to a module when the
PRCM module manages its interface and
functional clocks. The functional clock to
the module remains active unconditionally,
while the PRCM module automatically
0x2 Enabled
asserts/deasserts the module idle request
based on the clock-domain transitions. If
acknowledged by the module, the PRCM
module can gate only the interface clock
to the module.
0x3 Reserved NA
In addition to the IDLE and STANDBY protocol, PRCM offers also the possibility to manage optional
clocks, through a direct SW control: “OptFclken” bit from programming register.
Table 8-6. Module Clock Enabling Condition

Clock Enabling
Clock Domain is ready
Clock associated with
AND MStandby is de-asserted
STANDBY protocol OR
Mwakeup is asserted
Clock associated with IDLE Idle status = FUNCT
AND
protocol, as interface clock OR Idle status = TRANS
SWakeup is asserted
Idle status = FUNCT
Clock associated with IDLE
AND Idle status = IDLE
protocol, as functional clock OR
Idle status = TRANS
SWakeup is asserted
Clock domain is ready
Optional clock AND
OptFclken=Enabled ('1')
8.1.3.3 Clock Domain

A clock domain is a group of modules fed by clock signals controlled by the same clock manager in the
PRCM module By gating the clocks in a clock domain, the clocks to all the modules belonging to that
clock domain can be cut to lower their active power consumption (that is, the device is on and the clocks
to the modules are dynamically switched to ACTIVE or INACTIVE (GATED) states). Thus, a clock domain
allows control of the dynamic power consumption of the device. The device is partitioned into multiple
clock domains, and each clock domain is controlled by an associated clock manager within the PRCM
module. This allows the PRCM module to individually activate and gate each clock domain of the device
Figure 8-2. Generic Clock Domain
CM_a PRCM CM_b
FCLK2
ICLK1
CLK1
Module 1 Module 22
Module
prcm-002
Figure above is an example of two clock managers: CM_a and CM_b. Each clock manager manages a
clock domain. The clock domain of CM_b is composed of two clocks: a functional clock (FCLK2) and an
interface clock (ICLK1), while the clock domain of CM_a consists of a clock (CLK1) that is used by the
module as a functional and interface clock. The clocks to Module 2 can be gated independently of the
clock to Module 1, thus ensuring power savings when Module 2 is not in use. The PRCM module lets
software check the status of the clock domain functional clocks. The CM_<Clock domain>_CLKSTCTRL[x]
CLKACTIVITY_<FCLK/Clock name_FCLK> bit in the PRCM module identifies the state of the functional
clock(s) within the clock domain. Table shows the possible states of the functional clock.
Table 8-7. Clock Domain Functional Clock States

CLKACTIVITY BIT Value Status Description
The functional clock of the clock domain is
0x0 Gated
inactive
The functional clock of the clock domain is
0x1 Active
running
8.1.3.3.1 Clock Domain-Level Clock Management

The domain clock manager can automatically (that is, based on hardware conditions) and jointly manage
the interface clocks within the clock domain. The functional clocks within the clock domain are managed
through software settings. A clock domain can switch between three possible states: ACTIVE,
IDLE_TRANSITION, and INACTIVE. Figure 8-3 shows the sleep and wake-up transitions of the clock
domain between ACTIVE and INACTIVE states.
Figure 8-3. Clock Domain State Transitions
All modules IDLE/STANDBY

Sleep condition All domain clocks gated
IDLE_TRANSITION
ACTIVE Domain sleep conditions not satisfied INACTIVE
A wake-up request is received
prcm-003
Table 8-8. Clock Domain States

State Description
Every nondisabled slave module (that is, those whose
MODULEMODE value is not set to disabled) is put out of IDLE
state.
ACTIVE All interface clocks to the nondisabled slave modules in the
clock domain are provided. All functional and interface clocks to
the active master modules (that is, not in STANDBY) in the clock
domain are provided. All enabled optional clocks to the modules
in the clock domain are provided.
This is a transitory state.
Every master module in the clock domain is in STANDBY state.
Every idle request to all the slave modules in the clock domain is
IDLE_TRANSITION asserted. The functional clocks to the slave module in enabled
state (that is, those whose MODULEMODE values are set to
enabled) remain active.
All enabled optional clocks to the modules in the clock domain
are provided.
All clocks within the clock domain are gated.
Every slave module in the clock is in IDLE state and set to
disabled.
INACTIVE Every slave module in the clock domain (that is, those whose
MODULEMODE is set to disabled) is in IDLE state and set to
disabled.
Every optional functional clock in the clock domain is gated
Each clock domain transition behavior is managed by an associated register bit field in the CM_<Clock
domain>_CLKSTCTRL[x] CLKTRCTRL PRCM module
Table 8-9. Clock Transition Mode Settings

CLKTRCTRL Bit Value Selected Mode Description
Sleep transition cannot be initiated.
0x0 NO_SLEEP
Wakeup transition may however occur.
A software-forced sleep transition. The
0x1 SW_SLEEP transition is initiated when the associated
hardware conditions are satisfied
A software-forced clock domain wake-up
0x2 SW_WKUP
transition is initiated
0x3 Reserved NA
8.1.4 Power Management

The PRCM module manages the switching on and off of the power supply to the device modules. To
minimize device power consumption, the power to the modules can be switched off when they are not in
use. Independent power control of sections of the device allows the PRCM module to turn on and off
specific sections of the device without affecting the others.
8.1.4.1 Power Domain

A power domain is a section (that is, a group of modules) of the device with an independent and dedicated
power manager (see Figure). A power domain can be turned on and off without affecting the other parts of
the device.
Figure 8-4. Generic Power Domain Architecture
PRCM
PM
Vdd
Varray
Memory array
Logic power
Logic power
Memory logic
power switch
power switch
switch
switch
Memory Memory Memory Flip-flop Flip-flop
array array logic logic logic
Memory bank Memory Logic

Power domain
prcm-008
To minimize device power consumption, the modules are grouped into power domains. A power domain
can be split into a logic area and a memory area.
Table 8-10. States of a Memory Area in a Power Domain

State Description
ON The memory array is powered and fully functional
OFF The memory array is powered down
Table 8-11. States of a Logic Area in a Power Domain

State Description
ON Logic is fully powered
OFF Logic power switches are off. All the logic (DFF) is lost
8.1.4.2 Power Domain Management

The power manager associated with each power domain is assigned the task of managing the domain
power transitions. It ensures that all hardware conditions are satisfied before it can initiate a power domain
transition from a source to a target power state
Table 8-12. Power Domain Control and Status Registers

Register/Bit Field Type Description
Selects the target power state of the
PM_<Power domain>_PWRSTCTRL[1:0]
Control power domain among OFF, ON, or
POWERSTATE
RETENTION.
Identifies the current state of the power
PM_<Power domain>_PWRSTST[1:0]
Status domain. It can be OFF, ON, or
POWERSTATEST
RETENTION.
Identifies the current state of the logic
PM_<Power domain>_PWRSTST[2]
Status area in the power domain. It can be OFF
LOGICSTATEST
or ON.
Identifies the current state of the memory
PM_<Power domain>_PWRSTST[5:4]
Status area in the power domain. It can be OFF,
MEMSTATEST
ON, or RETENTION
8.1.4.2.1 Power-Management Techniques

The following section describes the state-of-the-art power-management techniques supported by the
device.
8.1.4.2.1.1 Adaptive Voltage Scaling

AVS is a power-management technique based in Smart Reflex that is used for automatic control of the
operating voltages of the device to reduce active power consumption. With Smart Reflex, power-supply
voltage is adapted to silicon performance, either statically (based on performance points predefined in the
manufacturing process of a given device) or dynamically (based on the temperature-induced real-time
performance of the device). A comparison of these predefined performance points to the real-time on-chip
measured performance determines whether to raise or lower the power-supply voltage. AVS achieves the
optimal performance/power trade-off for all devices across the technology process spectrum and across
temperature variation. The device voltage is automatically adapted to maintain performance of the device
8.1.4.3 Power Modes

The following is a high-level description of the different power modes of the device. They are listed in
order from highest power consumption, lowest wakeup latency (Standby), to lowest power consumption,
highest wakeup latency (RTC-only). If your application requires some sort of power management, you
must determine which power mode level described below satisfies your requirements. Each level must be
evaluated based on power consumed and latency (the time it takes to wakeup to Active mode). Specific
values are detailed in the device-specific data sheet. Note that not all modes are supported by software
packages supplied by Texas Instruments.
Table 8-13. Typical Power Modes

Power Modes Application State Power Domains, Clocks, and Voltage
Supply States
Active All Features Power supplies:
All power supplies are ON.
VDD_MPU = 1.1 V (nom)
VDD_CORE = 1.1 V (nom)
Clocks:
Main Oscillator (OSC0) = ON
All DPLLs are locked.
Power domains:
PD_PER = ON
PD_MPU = ON
PD_GFX = ON or OFF (depending on
use case)
PD_WKUP = ON
DDR is active.
Standby DDR memory is in self-refresh and Power supplies:
contents are preserved. Wakeup from any
GPIO. CortexA8 context/register contents
are lost and must be saved before VDD_MPU = 0.95 V (nom)
entering standby. On exit, context must be VDD_CORE = 0.95 V (nom)
restored from DDR. For wakeup, boot Clocks:
ROM executes and branches to system
Main Oscillator (OSC0) = ON
resume.
All DPLLs are in bypass.
Power domains:
PD_PER = ON
PD_MPU = OFF
PD_GFX = OFF
PD_WKUP = ON
DDR is in self-refresh.
Deepsleep1 On-chip peripheral registers are Power supplies:
preserved. Cortex-A8 context/registers are
lost, so the application needs to save
them to the L3 OCMC RAM or DDR VDD_MPU = 0.95 V (nom)
before entering DeepSleep. DDR is in VDD_CORE = 0.95 V (nom)
self-refresh. For wakeup, boot ROM Clocks:
executes and branches to system resume.
Main Oscillator (OSC0) = OFF
All DPLLs are in bypass.
Power domains:
PD_PER = ON
PD_MPU = OFF
PD_GFX = OFF
PD_WKUP = ON
Table 8-13. Typical Power Modes (continued)

Power Modes Application State Power Domains, Clocks, and Voltage
Supply States
Deepsleep0 PD_PER peripheral and Cortex-A8/MPU Power supplies:
register information will be lost. On-chip
peripheral register (context) information of
PD-PER domain needs to be saved by VDD_MPU = 0.95 V (nom)
application to SDRAM before entering this VDD_CORE = 0.95 V (nom)
mode. DDR is in self-refresh. For wakeup, Clocks:
boot ROM executes and branches to
peripheral context restore followed by
system resume. All DPLLs are in bypass.
Power domains:
PD_PER = OFF
PD_MPU = OFF
PD_GFX = OFF
PD_WKUP = ON
RTC-Only RTC timer remains active and all other Power supplies:
device functionality is disabled.
All power supplies are OFF except
VDDS_RTC.
VDD_MPU = 0 V
VDD_CORE = 0 V
Clocks:
Power domains:
All power domains are OFF.
8.1.4.3.1 Active
In Active mode, the supply to all voltage rails must be maintained. All power domains come up in ON state
and the device is fully functional.
8.1.4.3.2 Standby
The device can be placed in Standby mode to reduce power consumption during low activity levels. This
first level of power management allows you to maintain the device context for fast resume times. The main
characteristics of this mode which distinguish it from Active mode are:
• All modules are clock gated except GPIOs
• PLLs may be placed in bypass mode if downstream clocking does not require full performance
• Voltage domains VDD_MPU and VDD_CORE voltage levels can be reduced to OPP50 levels because
the required performance of the entire device is reduced
• MPU power domain (PD_MPU) is in OFF state
• DDR memory is in low power self-refresh mode.
Further power reduction can be achieved in this mode if the RTC function is not required. See
Section 8.1.4.3.6, Internal RTC LDO.
The above conditions result in lower power consumption than Active mode but require the user to save the
MPU context to OCMC RAM or DDR to resume properly upon wakeup. Contents of the internal SRAM are
lost because PD_MPU is turned OFF. Wakeup in Standby mode is achieved using any GPIO. GPIO
wakeup is possible by switching the pad to GPIO mode and configuring the corresponding GPIO bank for
generating an interrupt to the MPUSS. Note that pads that do not have a GPIO muxmode (for example,
ADC or USB), cannot cause these wakeups. If additional or other wakeup sources are required, the
associated peripheral module clock and interconnect clock domain should remain enabled (this may
require the associated PLL to remain locked) and the module must be configured appropriately for wakeup
by configuring it to generate an interrupt to the MPUSS.
8.1.4.3.3 DeepSleep1
DeepSleep1 mode enables lower power consumption than Standby mode. The main characteristic of this
mode which distinguish it from Standby mode is the main oscillator (OSC0) is disabled.
DeepSleep1 is the lowest sleep mode required for certain USB wakeup modes. See Section 8.1.4.3.7,
Supported Low Power USB Wakeup Scenarios, for more information.
Similar to Standby mode, the contents of the internal SRAM are lost because PD_MPU is turned OFF. In
addition, the contents of the SDRAM are preserved by placing the SDRAM in self-refresh. Activity on
wakeup peripherals via wake-up events enables the master crystal oscillator using the oscillator control
circuit. The wakeup events also interrupt Cortex-M3. See Section 8.1.4.5, Wakeup Sources/Events, for
details on wakeup sources.
8.1.4.3.4 DeepSleep0
DeepSleep0 mode enables lower power consumption than DeepSleep1. The main characteristics of the
mode which distinguish it from other higher power modes are:
• All on-chip power domains are shut off (except PD_WKUP and PD_RTC remain ON) to reduce power
leakage
• VDD_CORE power (except VDDA analog) to DPLLs is turned OFF using dpll_pwr_sw_ctrl register (PG
2.x only)
• VDDS_SRAM_CORE_BG is in retention using SMA2.vsldo_core_auto_ramp_en (PG2.x only)
DeepSleep0 mode is typically used during periods of inactivity when the user requires very low power
while waiting for an event that requires processing or higher performance. This is the lowest power mode
which still includes DDR in self-refresh, so wakeup events do not require a full cold boot, which greatly
reduces wakeup latencies over RTC-only mode.
Similar to DeepSleep1 mode, the contents of the internal SRAM are lost because PD_MPU is turned OFF.
Before entering DeepSleep0 mode, peripheral and MPU context must be saved in the DDR. Upon
wakeup, the boot ROM executes and checks to see if it has resumed from a DeepSleep0 state. If so, it
redirects to the DDR to continue the resume process. Because power to PD_WKUP is ON throughout
DeepSleep0, power to key modules such as GPIO0, I2C, and others is maintained to allow wakeup events
to exit out of this mode. In addition, power to OCMC RAM is maintained to preserve information internally
during DeepSleep0.
Activity on wakeup peripherals via wakeup events enables the master crystal oscillator using the oscillator
control circuit. The wakeup events also interrupt Cortex M3 which controls proper enabling of power
domains and clocks in the PRCM. See Section 8.1.4.5, Wakeup Sources/Events, for details on wakeup
sources during DeepSleep0 and other low power modes mentioned.
8.1.4.3.5 RTC-Only
RTC-only mode is an ultra-low power mode which allows the user to maintain power and clocks to the
real-time clock (RTC) domain while the rest of the device is powered down. All context and memories will
be lost, and the only portion of the chip that will be maintained is the RTC. Only the RTC power supply
must be ON. All the remaining supplies must be OFF. The RTC battery backup domain consists of the
RTC subsystem (RTCSS), a dedicated, on-chip 32.768 Hz crystal oscillator and I/Os associated with the
RTCSS: pmic_power_en and ext_wakeup.
Figure 8-5 gives a high level view of system which implements the RTC-only mode.
Figure 8-5. High Level System View for RTC-only Mode
Internal FSM/control
SoC-Power-on-reset
Main supply
SoC-Power-on-supplies
Wakeup
AM335x
Enable/NSleep
Pushbutton
ext_wakeup0 PMIC
RTC/
Backup
battery pmic_pwr_enable
domain
RTC-Power-on-reset
Backup supply
RTC Power supply
Wakeup from RTC-only mode can only be achieved using the ext_wakeup0 signal or RTC Alarm
(ALARM). Once a wakeup is triggered using either of these sources, the device drives pmic_pwr_enable
to initiate a power-up sequence by the PMIC. The device must go through a full cold boot upon wakeup
from RTC-only mode.
8.1.4.3.6 Internal RTC LDO

The device contains an internal LDO (low dropout) regulator which powers the RTC digital core.
Depending on your application, you may be able to disable this regulator to save power in low power use
cases.
If your application never uses the RTC functionality, connect RTC_KALDO_ENn to VDDS_RTC,
CAP_VDD_RTC to VDD_CORE, and RTC_PWRONRSTn to ground. These connections disable the
internal RTC LDO because RTC_KALDO_ENn is high, and they use the external VDD_CORE supply to
power the RTC digital core. The RTC LDO must be disabled for internal power sequencing even though
the RTC is not used. Grounding the reset signal will ensure the RTC stays in reset. Disabling the internal
LDO will allow the application to achieve lower power consumption in all the low power modes.
If your application uses the RTC functionality and never needs RTC-only mode, the hardware scenario is
similar to the previous description, but the RTC reset signal can be connected to the device
PWRONRSTn. Note that PWRONRSTn and RTC_PWRONRSTn may be at different voltage levels, so
PWRONRSTn may require level shifting before connecting to RTC_PWRONRSTn. This connection allows
full functionality of the RTC subsystem without the internal RTC LDO consuming power.
If your application uses the RTC functionality and requires RTC-only mode, the internal LDO is required to
enable proper wakeup signaling from the RTC domain. The proper wakeup signaling requires the following
connections:
• RTC_KALDO_ENn is grounded
• CAP_VDD_RTC is connected to 1uF decoupling capacitor to ground
• RTC_PWRONRSTn is connected to 1.8V RTC power on reset
• PMIC_POWER_EN is connected to power input of PMIC
• EXT_WAKEUP0 is connected to a wakeup source
See the device datasheet for more information on these signals.
8.1.4.3.7 Supported Low Power USB Wakeup Scenarios

Table 8-14 summarizes different USB wakeup use cases which are supported in each system sleep state
(DeepSleep0, DeepSleep1, or Standby). Three use case scenarios exist:
• USB Connect: Wakeup is cause by physically inserting the USB cable.
• USB Disconnect: Wakeup is caused by physically removing the USB cable.
• USB Suspend/Resume: Wakeup is caused by a USB suspend or resume command. For example, a
USB mouse click can cause a USB resume command.
Within each wakeup use case, each row describes whether or not that type of wakeup is supported in
each system sleep mode. USB mode (host or device) is also considered.
There are two possible Wakeup events that are generated:
• PHY WKUP: this is an internal wakeup signal to the Cortex M3 that is generated by the USB PHY
based off of USB signaling.
• VBUS2GPIO: this is an external wakeup signal coming from a level change on VBUS voltage. This
event requires an external board solution which routes VBUS to a GPIO on the device. Ensure you
level shift the voltage to conform to the I/O requirements. When VBUS transitions from 0V to 5V (or
vice versa), the transition on a GPIO will trigger a wakeup.
Table 8-14. USB Wakeup Use Cases Supported in System Sleep States
No. USB Wakeup System Sleep USB Controller USB Mode Supported USB Wakeup
Use Case State State Event
1 USB Connect DS0 POWER OFF Host No N/A
2 DS0 POWER OFF Device Yes VBUS2GPIO
3 DS1/ Standby Clock Gated Host Yes PHY WKUP
4 DS1/ Standby Clock Gated Device Yes VBUS2GPIO
5 USB Suspend / DS0 POWER OFF Host No N/A
Resume
6 DS0 POWER OFF Device No N/A
8 DS1/ Standby Clock Gated Device Yes PHY WKUP
9 USB Disconnect DS0 POWER OFF Host No N/A
10 DS0 POWER OFF Device No N/A
12 DS1/ Standby Clock Gated Device Yes VBUS2GPIO
8.1.4.4 Main Oscillator Control During Deep Sleep

The Deepsleep oscillator circuit is used to control the main oscillator by disabling it during deep sleep and
enabling during active/wakeup. By default during reset, the oscillator is enabled and the oscillator control
circuit comes up disabled (in-active).In order to activate the oscillator control circuit for deepsleep,
DSENABLE bit of DEEPSLEEP_CTRL register must set. Once this is set and whenever wake M3 enters
standby, the oscillator control will disable the oscillator causing the clock to be shut OFF. Any async event
from the wakeup sources will cause the oscillator control to re-enable the oscillator after a period of
DSCOUNT configured in DEEPSLEEP_CTRL register.
8.1.4.5 Wakeup Sources/Events

Following events will wake up the device from Deep sleep(low power) modes. These are part of the
Wakeup Power domain and remain always ON.
Note: For differences in operation based on AM335x silicon revision, see Section 1.2, Silicon Revision
Functional Differences and Enhancements.
• GPIO0 bank
• dmtimer1_1ms (timer based wakeup)
• USB2PHY (USB resume signaling from suspend) – Both USB ports supported.
• TSC (touch screen controller, ADC monitor functions )
• UART0 (Infra-red support)
• I2C0
• RTC alarm
These wake events apply on any of the deep sleep modes and standby mode.
8.1.4.6 Functional Sequencing for Power Management with Cortex M3

The AM335x device contains a dedicated Cortex M3 processor to handle the power management
transitions. It is part of the Wake up Power domain (PD_WKUP). Implementing the Power modes are part
of the MPU and Cortex A8 processors.
The power management sequence kicks off with Cortex A8 MPU executing a WFI instruction with the
following steps:
1. During Active power mode, the Cortex A8 MPU executes a WFI instruction to enter IDLE mode.
2. Cortex M3 gets an interrupts and gets active, It powers down the MPU power domain( if required).
3. Registers interrupt for the Wake up peripheral(which is listed in Wake up sources in previous section).
4. Executes WFI and goes into idle state.
5. The wake up event triggers an interrupt to Cortex M3 system and it wakes up the Cortex A8 MPU.
Generally, A8 and Cortex M3 are not expected to be active at the same time Cortex M3 along with PRCM
is the power manager primarily for PD_MPU and PD_PER. Other power domains (e.g., PD_GFX) may be
handled directly using Cortex A8 MPU software. Figure 8-6 gives a system level view of the Power
management system between Cortex A8 MPU and Cortex M3.
Figure 8-6. System Level View of Power Management of Cortex A8 MPU and Cortex M3
PD_PER
PD_GFX
IP/Peripherals
Power
Bus connect/
disconnect
PD_MPU
(Cortex-A8)
Power
Interconnect
Idle
WKUP
MBX
Power
Bus
Idle
INTR2
MSG3 INTR3
MSG1
TXEV RXEV
PRCM
INTR1
16KB unified RAM
Cortex-
M3
8KB DRAM
Control
MSG3
Cortex-M3 subsystem
System power clock manager
Interrupt
Alternate Interrupt/Event
Legend: s/w message
Alternate s/w message
Data flow
The Cortex-M3 handles all of the low-level power management control of the AM335x. A firmware binary
is provided by Texas Instruments that includes all of the necessary functions to achieve low power modes.
Inter-Processor Communication (IPC) registers (ipc_msg_regx, located in the Control Module Registers)
are available to communicate with the Cortex-M3 so the user can provide certain configuration parameters
based on the level of low power that is required. Figure 8-7 provides a mapping of these registers.
Figure 8-7. IPC Mechanism

31 16 15 0
IPC_MSG_REG0 Reserved
IPC_MSG_REG1 CMD_STAT CMD_ID
IPC_MSG_REG2 CMD param1

R/W MPU R/W
IPC_MSG_REG3 CMD param2 H/W Mailbox

SEV instruction
Notification only
IPC_MSG_REG4 Reserved for future use
R/W CM3
IPC_MSG_REG7 Customer Use
MPU has write permission,

CM3 has read-only permission
CM3 has write permission, Not enforced by h/w
MPU has read-only permission
IPC_MSG_REG1 contains the CMD_STAT and CMD_ID parameters as described in Table 8-15 and
Table 8-16.
Table 8-15. CMD_STAT Field

CMD_STAT Value Description
In the initialization phase, PASS (0x1) denotes that the CM3 was successfully
PASS 0x0
initialized.
In the initialization phase, 0x2 denotes CM3 could not properly initialize. When
other tasks are to be done, FAIL (0x3) indicates some error in carrying out the
FAIL 0x1
task.
Check trace vector for details.
CM3 INTC will catch the next WFI of A8 and continue with the pre-defined
WAIT4OK 0x2
sequence.
Table 8-16. CMD_ID Field

CMD_ID Value Description
1. Initiates force_sleep on interconnect clocks.

CMD_RTC 0x1 2. Turns off MPU and PER power domains.
3. Programs the RTC alarm register for deasserting pmic_pwr_enable.
CMD_RTC_FAST 0x2 Programs the RTC alarm register for deasserting pmic_pwr_enable.

CMD_DS0 0x3 2. Turns off the MPU and PER power domains.
3. Configures the system for disabling MOSC when CM3 executes WFI.

CMD_DS1 0x5 2. Turns off the MPU power domains.
3. Configures the system for disabling MOSC when CM3 executes WFI.
8.1.4.6.1 Periodic Idling of Cortex A8 MPU

To implement Cortex A8 MPU periodic ON/OFF in the use case, the control flow could be implemented
according to the following steps:
1. Cortex A8 MPU executes WFI instruction
2. Any peripheral interrupt in any of the next steps will trigger a wake interrupt to Cortex M3 via MPU
Subsystem’s WKUP signal (INTR2 shown on the diagram). Cortex M3 powers down the
MPU(PD_MPU)
3. On receiving an interrupt Cortex M3 switches ON the MPU power domain by turning on PD_MPU
4. Cortex M3 goes into idle mode using WFI instruction
8.1.4.6.2 Sleep Sequencing

This section gives the system level guidelines for sleep sequencing. The guidelines can serve as an
example for implementing the sleep mode sequencing. The user can opt to implement a sequence with
certain steps interchanged between the MPU and Cortex M3 processor.
1. Application saves context of peripherals to memories supporting retention and DDR – this step is only
required for Deepsleep0.
2. MPU OCMC_RAM remains in retention
3. Unused power domains are turned OFF - program clock/power domains PWRSTCTRL, save contexts
etc
4. Software populates L3_OCMC_RAM for wakeup restoration viz Save EMIF settings, public/secure
restoration pointers, etc.
5. Execute WFI from SRAM
6. Any peripheral interrupt will trigger a wake interrupt to Cortex M3 via Cortex A8 MPU’s WKUP signal
(INTR2 shown on the diagram).
7. After MPU power domain is clock gated PRCM will provide an interrupt to Cortex M3 (using INTR1
shown in the block diagram)
8. Cortex M3 starts execution and performs low level power sequencing to turn off certain power domain,
and eventually executes WFI.
9. Hardware oscillator control circuit disables the oscillator once Cortex M3 goes into WFI
8.1.4.6.3 Wakeup Sequencing

This section gives the guidelines for Wakeup sequencing.
1. One of the wakeup event triggers (which was configured during the sleep sequencing) will initiate a
wakeup sequence
2. The wake up event will switch on the oscillator (if it was configured to go OFF during sleep)
3. The wake up event will also trigger interrupt to Cortex M3
4. On the wakeup event due to interrupt Cortex M3 execute the following
• Restore the voltages to normal Operating voltage
• Enable PLL locking
• Cortex M3 will switch ON the power domains and/or enable clocks for PD_PER
• Cortex M3 will switch ON the power domains and/or enable clocks for PD_MPU
• Executes WFI
5. Cortex A8 MPU starts executing from ROM reset vector
6. Restore the application context(only for Deep sleep 0)
8.1.5 PRCM Module Overview

The PRCM is structured using the architectural concepts presented in the 5000x Power Management
Framework. This framework provides:
A set of modular, re-usable FSM blocks to be assembled into the full clock and power management
mechanism. A register set and associated programming model. Functional sub-block definitions for clock
management, power management, system clock source generation, and master clock generation.
The device supports an enhanced power management scheme based on four functional power domains:
Generic Domains
• WAKEUP
• MPU
• PER
• RTC
The PRCM provides the following functional features:
• Software configurable for direct, automatic, or a combination thereof, functional power domain state
transition control
• Device power-up sequence control
• Device sleep / wake-up sequence control
• Centralized reset generation and management
• Centralized clock generation and management
The PRCM modules implement these general functional interfaces:
• OCP configuration ports
• Direct interface to device boundary
• Power switch control signals
• Device control signals
• Clocks control signals
• Resets signals
• A set of power management protocol signals for each module to control and monitor standby, idle and
wake-up modes (CM and PRM)
• Emulation signals
8.1.5.1 Interface Descriptions

This section lists and shortly describes the different interfaces that allow PRCM to communicate with other
modules or external devices.
8.1.5.1.1 OCP Interfaces

The PRCM has 1 target OCP interfaces, compliant with respect to the OCP/IP2 standard. The OCP port,
for the PRCM module is used to control power, reset and wake-up Management.
8.1.5.1.2 OCP Slave Interfaces

PRCM implements a 32-bit OCP target interface compliant to the OCP/IP2.0 standard.
8.1.5.1.3 Power Control Interface

The Device does has power domain switches over the device, this interface provides PRCM control over
power domain switches and receives responses from the power domains which indicate the switch status.
It also controls the isolation signals. The control for power domain switches will be latched in PRCM
Status Registers
8.1.5.1.4 Device Control Interface

This interface provides PRM management of several device-level features which are not specific to any
single power domain. This PRM interface controls signals to/from the device for global control:
• Device Type coding

• IOs isolation control
8.1.5.1.5 Clocks Interface

This interface gathers all clock inputs and outputs managed by PRCM modules.
8.1.5.1.6 Resets Interface

This interface gathers all resets inputs and outputs managed by PRCM module.
8.1.5.1.7 Modules Power Management Control Interface

Modules or subsystems in the device are split over 2 categories:
• Initiator: an initiator is a module able to generate traffic on the device interconnects (typically:
processors, MMU, EDMA).
• Target: a target is a module that cannot generate traffic on the device interconnects, but that can
generate interrupts or DMA request to the system (typically: peripherals). PRCM handles a power
management handshake protocol with each module or sub-system. This protocol allows performing
proper clock and power transition taking into account each module activity or state.
8.1.5.1.8 Initiator Modules Interface

PRCM module handle all initiator modules power management interfaces: MStandby signal MWait signal
8.1.5.1.9 Targets Modules Interface

PRCM module handle all target modules power management interfaces: SIdleReq signal SIdleAck signal
FCLKEN signal
Note: USB Support for SWakeUp
8.1.6 Clock Generation and Management

PRCM provides a centralized control for the generation, distribution and gating of most clocks in the
device. PRCM gathers external clocks and internally generated clocks for distribution to the other modules
in the device. PRCM manages the system clock generation
8.1.6.1 Terminology
The PRCM produces 2 types of clock:
Interface clocks: these clocks primarily provide clocking for the system interconnect modules and the
portions of device's functional modules which interface to the system interconnect modules. In most
cases, the interface clock supplies the functional module's system interconnect interface and registers. For
some modules, interface clock is also used as functional clock. In this document, interface clocks are
represented by blue lines.
Functional clock: this clock supplies the functional part of a module or a sub-system. In some cases, a
module or a subsystem may require several functional clocks: 1 or several main functional clock(s), 1 or
several optional clock(s). A module needs its main clock(s) to be operational. Optional clocks are used for
specific features and can be shutdown without stopping the module
8.1.6.2 Clock Structure

To generate high-frequency clocks, the device supports multiple on-chip DPLLs controlled directly by the
PRCM module. They are of two types of PLLs, referred to ADPLLS and ADPLLLJ throughout this
document.
The ADPLLS module is used for the Core, Display, ARM Subsystem and DDR PLLs
The ADPLLLJ module is used for the peripheral functional clocks
The device has two reference clocks which are generated by on-chip oscillators or externally. These are
for the main clock tree and RTC block, respectively.
In the case of an external oscillator, a clock can directly be connected to XTALIN pin and the oscillator will
be put in bypass mode. The 32-Khz crystal oscillator is controlled and configurable by RTC IP. This device
also contains an on-chip RC oscillator. This oscillator is not configurable and is always on.
The main oscillator on the device (see Chapter 26, Initialization, for possible frequencies) produces the
master high frequency clock CLK_M_OSC.
8.1.6.3 ADPLLS
The ADPLLS is a high resolution frequency synthesizer PLL with built in level shifters which allows the
generation of PLL locked frequencies up to 2 GHz. ADPLLS has a predivide feature which allows user to
divide, for instance, a 24- or 26-MHz reference clock to 1-MHz and then multiply up to 2-GHz maximum.
All PLLs will come-up in bypass mode at reset. SW needs to program all the PLL settings appropriately
and then wait for PLL to be locked. For more details, see the configuration procedure for each PLL.
The following PLLs are:
• MPU PLL
• Core PLL
• Display PLL
• DDR PLL
Figure 8-8. ADPLLS

CLKINP
ULOWCLKEN
1/(N2+1)
(4 bits)
CLKOUTX2
1/(N+1) CLKINPULOW
7 bits
BYPASS_INT
REFCLK
1/M2 ½ CLKOUT
PFD Multiplier DAC (5 bits) (1 bit)
FBCLK CLKDCOLDO
½
1/M.f
(1 bit)
1/M3 CLKOUTHIF
(5 bits)
CLKINPHIF
SSC sigmadelta
CLKINPHIFSEL
The ADPLLS has three input clocks:

• CLKINP: Reference input clock
• CLKINPULOW: Low frequency input clock for bypass mode only.
• CLKINPHIF: High Frequency Input Clock for post-divider M3
The ADPLLS has four output clocks:
• CLKOUTHIF: High Frequency Output Clock from Post divider M3
• CLKOUTX2: Secondary 2x Output
• CLKOUT: Primary output clock
• CLKDCOLDO: Oscillator (DCO) output clock with no bypass
The DPLL has two internal clocks:

• REFCLK (Internal reference clock): This is generated by dividing the input clock CLKINP by the
programmed value N+1. The entire loop of the PLL runs on the REFCLK.
Here, REFCLK = CLKINP/(N+1).
• BCLK: Bus clock which is used for programming the various settings using registers
The ADPLLS lock frequency is defined as follows: fDPLL = CLKDCOLDO
8.1.6.3.1 Clock Functions
Table 8-17. Output Clocks in Locked Condition

Pin Name Frequency Comments
REGM4XEN='0'
CLKOUT [M / (N+1)] * CLKINP * [1/M2]
CLKOUTX2 2 * [M / (N+1)] * CLKINP * [1/M2]
CLKDCOLDO 2 * [M / (N+1)] * CLKINP
CLKINPHIF / M3 CLKINPHIFSEL='1'
CLKOUTHIF
2 * [M / (N+1)] * CLKINP * [1/M3] CLKINPHIFSEL='0'
REGM4XEN='1'
CLKOUT [4M / (N+1)] * CLKINP * [1/M2]
CLKOUTX2 2 * [4M / (N+1)] * CLKINP * [1/M2]
CLKDCOLDO 2 * [4M / (N+1)] * CLKINP
CLKINPHIF / M3 CLKINPHIFSEL='1'
CLKOUTHIF
2 * [4M / (N+1)] * CLKINP * [1/M3] CLKINPHIFSEL='0'
Table 8-18. Output Clocks Before Lock and During Relock Modes
CLKINP / (N2+1) ULOWCLKEN='0'
CLKOUT
CLKINPULOW ULOWCLKEN='1'
CLKINP / (N2+1) ULOWCLKEN='0'
CLKOUTX2
CLKINPULOW ULOWCLKEN='1'
CLKDCOLDO Low
CLKINPHIF/M3 ULOWCLKEN='1'
CLKOUTHIF
Low ULOWCLKEN='0'
Note: Since M3 divider is running on the internal LDO domain, in the case when CLKINPHIFSEL=’1’,
CLKOUTHIF could be active only when internal LDO is ON. Hence, whenever LDOPWDN goes low to
high to powerdown LDO (happens when TINITZ activated / when entering slow relock bypass mode),
output CLKOUTHIF will glitch and stop. To avoid this glitch, it is recommended to gate CLKOUTHIF using
control CLKOUTHIFEN before asserting TINITZ / entering any slow relock bypass mode Frequency
Range (MHz)
See the device-specific data manual for details on operating performance points (OPPs) supported by
your device.
8.1.6.4 ADPLLLJ (Low Jitter DPLL)

The ADPLLLJ is a low jitter PLL with a 2-GHz maximum output. ADPLLLJ has a predivide feature which
allows user to divide, for instance, a 24-MHz or 26-MHz reference clock to 1 MHz and then multiply up to
2 GHz maximum.
All PLLs will come-up in bypass mode at reset. SW needs to program all the PLL settings appropriately
and then wait for PLL to be locked. For more details, see the configuration procedure for each PLL.
Figure 8-9. Basic Structure of the ADPLLLJ

CLKINP
1/(N+1)
8 bits
SELFREQDCO
CLKOUTLDO
REFCLK
HS1: 2–1 GHz
HS1 1/M2
PFD Multiplier DAC
HS2 7 bits
HS2: 1–0.5 GHz CLKOUT
ULOWCLKEN
FBCLK
SDCLK
Sigma 1/(SD) 1/(N2 + 1) CLKINPULOW
delta 8 bits 4 bits
CLKINP CLKDCOLDO
1/M.f
8 bits
SSC
The Peripheral PLL belongs to type ADPLLLJ:

The DPLL has two input clocks:
• CLKINP: Reference input clock
• CLKINPULOW: Bypass input clock.
The DPLL has two internal clocks:
• REFCLK (Internal reference clock): This is generated by dividing the input clock CLKINP by the
programmed value N+1. The entire loop of the PLL runs on the REFCLK.
Here, REFCLK = CLKINP/(N+1).
• CLKDCOLDO (Internal Oscillator clock.):This is the raw clock directly out of the digitally controlled
oscillator (DCO) before the post-divider. The PLL output clock is synthesized by an internal oscillator
which is phase locked to the refclk. There are two oscillators built within ADPLLLJ. The oscillators are
user selectable based on the synthesized output clock frequency requirement. In locked condition,
CLKDCOLDO = CLKINP *[M/(N+1)].
The ADPLLLJ lock frequency is defined as follows: fDPLL = CLKDCOLDO
The DPLL has three external output clocks:
• CLKOUTLDO: Primary output clock in VDDLDOOUT domain. Bypass option not available on this
output.
CLKOUTLDO = (M / (N+1))*CLKINP*(1/M2)
• CLKOUT: Primary output clock on digital core domain
CLKOUT = (M / (N+1))*CLKINP*(1/M2)
• CLKDCOLDO: Oscillator (DCO) output clock before post-division in VDDLDOOUT domain. Bypass
option is not available on this output.
CLKDCOLDO = (M / (N+1))*CLKINP.
All clock outputs of the DPLL can be gated. The Control module provides the DPLL with a clock gating
control signal to enable or disable the clock, and the DPLL provides the PRCM module with a clock
activity status signal to let the PRCM module hardware know when the clock is effectively running or
effectively gated. Output clock gating control for various clockouts:
CLKOUTEN/CLKOUTLDOEN/CLKDCOLDOEN.
8.1.6.4.1 Clock Functions
Table 8-19. Output Clocks in Locked Condition

Pin Name Frequency
CLKOUT [M /(N+1)] * CLKINP * [1/M2]
CLKOUTLDO [M /(N+1)] * CLKINP * [1/M2]
CLKDCOLDO [M /(N+1)] * CLKINP
Table 8-20. Output Clocks Before Lock and During Relock Modes
CLKINP/(N2+1) ULOWCLKEN=’0’
CLKOUT
CLKINPLOW ULOWCLKEN=’1’
CLKDCOLDO LOW
CLKOUTLDO LOW
8.1.6.5 M2 Change On-the-Fly

The divider M2 is designed to change on the fly and provide a glitch-free frequency switch from the old to
new frequencies. It can be changed while the PLL is in a locked condition without having to switch to
bypass mode. A status toggle bit will give an indication if the new divisor was accepted. The divider M2
can also be changed in bypass mode, and the new divisor value will be reflected on output after the PLL
relocks. For more details, see the PLL configuration procedures for each PLL.
8.1.6.6 Spread Spectrum Clocking (SSC)
NOTE: Spread spectrum clock is only supported for the DISP/LCD and MPU PLLs on this device.
Spread spectrum clocking is not supported for DDR, PER, and CORE PLLs. When enabling
SSC on MPU PLL, ensure the maximum MPU frequency remains below the maximum rated
frequency for the chosen OPP (see the device-specific Data Manual for more details).
The module supports spread spectrum clocking (SSC) on its output clocks. SSC is used to spread the
spectral peaking of the clock to reduce any electromagnetic interference (EMI) that may be caused due to
the clock’s fundamental or any of its harmonics. When SSC is enabled the clock’s spectrum is spread by
the amount of frequency spread, and the attenuation is given by the ratio of the frequency spread (Δf) and
the modulation frequency (fm), i.e., [{10*log10(Df/fm)}-10] dB.
8.1.6.6.1 Definition
The aim of SSC is to add a variation in the frequency of an original clock, which spreads the generated
interferences over a larger band of frequency.
In theory, SSC means that the clock signal is varied around the desired frequency. For example, for a 1-
GHz clock, the frequency may be 999.5 MHz at one moment and 1.0005 GHz at another. When SSC is
enabled the clock spectrum is spread by the amount of frequency spread. Doing this constantly causes
the power of the tone to be spread out more over a broader band of tight frequencies (centered at the
desired tone). To realize this constant variation on the original signal, a modulation with an additional
signal (called spreading waveform) is realized.
Creating an SSC by spreading the initial clock frequency is done by defining the following parameters:
• The spreading frequency (deviation), which is the ratio of the range of spreading frequency over the
original clock frequency
• The modulation rate (fm), which is used to determine the clock-frequency spreading-cycling rate and is
the time during which the generated clock frequency varies through Δf and returns to the original
frequency
• The modulation waveform, which describes the variation curve in terms of time
The spectral power reduction in the DPLL clocks is dependent on the modulation index (K), which is a
ratio of spreading frequency calculated from the frequency deviation (Δf) and the modulation rate (fm) .
8.1.6.6.2 Effect on the Clock Signal

Figure 8-10 is an example of the effect of a triangular spreading on a clock signal.
Figure 8-10. Effect of the SSC in Frequency
Spectrum of signal without spreading Spectrum of signal with triangular spreading

scm-038
Figure 8-10 shows not only the power reduction of the main peak, but also the flatter aspect of the
modulated signal. The minimum level of the second signal is higher than the minimum level of the first
signal. This effect is normal and is due to the noise added for the modulation.
NOTE: The spreading technique scatters the energy of the peaks on the other frequencies, which
reduces the power of the peaks but increases the global noise of the signal.
Figure 8-11 shows the effect of triangular spreading on a clock signal in the time domain.
Figure 8-11. Effect of the SSC in the Time Domain
Initial clock signal Spreading signal
Clock signal with spreading

scm-039
8.1.6.6.3 Estimation of the EMI Reduction Level

Figure 8-12 shows the effect of spreading on a clock and its harmonics.
Figure 8-12. Peak Reduction Caused by Spreading

Spectrum
dB
Reduction
Freq/Hz
Clock signal without spreading

Clock signal with spreading
scm-037
The electromagnetic interference reduction can be estimated with the following equation:
Peak_power_reduction = 10 * log ((Deviation * fc) / fm
With:
• Peak_power_reduction in dB
• Deviation in % of the initial clock frequency (fc), equals Δf / fc
• fc is the original clock frequency, in MHz
• fm is the spreading frequency, in MHz
According to equation (1), it is also possible to compute the deviation, and then Δf, for a required peak
power reduction:
Deviation = (fm / fc) * 10(Peak_power_reduction / 10)
Example:
For fc=400 MHz, deviation =1% peak from fc(Δf = 4MHz) and fm=400kHz; the estimated peak power
reduction is 10dB.
8.1.6.6.4 Bandwidth Calculation (Carson Bandwidth Rule)

The Carson bandwidth rule defines the approximate bandwidth requirements of communications system
components for a carrier signal that is frequency-modulated by a continuous or broad spectrum of
frequencies rather than a single frequency.
The Carson bandwidth rule is expressed by the relation CBR = 2 * (Δf + fm), where CBR is the bandwidth
requirement, Δf is the peak frequency deviation, and fm is the highest frequency in the modulating signal.
For example, an FM signal with a 5-kHz peak deviation and a maximum audio frequency of 3 kHz, would
require an approximate bandwidth 2*(5 3) = 16 kHz.
Theoretically, any FM signal has an infinite number of sidebands and hence an infinite bandwidth, but in
practice all significant sideband energy (98% or more) is concentrated within the bandwidth defined by the
Carson bandwidth rule.
8.1.6.6.5 SSC Generation Control in the Device

SSC is performed by changing the feedback divider (M) in a triangular pattern. Implying, the frequency of
the output clock would vary in a triangular pattern. The frequency of this pattern would be modulation
frequency (fm). The peak (ΔM) or the amplitude of the triangular pattern as a percent of M would be equal
to the percent of the output frequency spread (Δf); that is, ΔM/M= Δf / fc. Next mark with Finp the
frequency of the clock signal at the input of the DPLL. Because it is divided to N+1 before entering the
phase detector, so the internal reference frequency is Fref = Finp / (N + 1).
Assume the central frequency fc to be equal to the DPLL output frequency Fout, or fc= Fout = (Finp / (N +
1)) * (M / M2). Since this is in band modulation for the DPLL, the modulation frequency is required to be
within the DPLL's loop bandwidth (lowest BW of Fref / 70). A higher modulation frequency would result in
lesser spreading in the output clock.
SSC can be enabled/disabled using bit CM_CLKMODE_DPLL_xxx.DPLL_SSC_EN (where xxx can be
any one of the following DPLLs: MPU, DDR, DISP, CORE, PER). An acknowledge signal
CM_CLKMODE_DPLL_xxx.DPLL SSC_ACK notifies the exact start and end of SSC. When SSC_EN is
de-asserted, SSC is disabled only after completion of one full cycle of the triangular pattern given by the
modulation frequency. This is done in order to maintain the average frequency.
Modulation frequency (fm) can be programmed as a ratio of Fref / 4; that is, the value that needs to be
programmed ModFreqDivider = Fref / (4*fm). The ModFreqDivider is split into Mantissa and 2^Exponent
(ModFreqDivider = ModFreqDividerMantissa * 2^ModFreqDividerExponent). The mantissa is controlled by
7-bit signal ModFreqDividerMantissa through
CM_SSC_MODFREQDIV_DPLL_xxx.MODFREQDEV_MANTISSA bit field. The exponent is controlled by
3bit signal ModFreqDividerExponent through the
CM_SSC_MODFREQDIV_DPLL_xxx.MODFREQDEV_EXPONENT bit field.
NOTE: Although the same value of ModFreqDivider can be obtained by different combinations of
mantissa and exponent values, it is recommended to get the target ModFreqDivider by
programming maximum mantissa and a minimum exponent.
To define the Frequency spread (Δf), ΔM must be controlled as explained previously. To define ΔM, the
step size of M for each Fref during the triangular pattern must be programmed; that is,
ΔM = (2^ModFreqDividerExponent) * ModFreqDividerMantissa * DeltaMStep IF
ModFreqDividerExponent ≤ 3ΔM = 8 * ModFreqDividerMantissa * DeltaMStep IF
ModFreqDividerExponent > 3
DeltaMStep is split into integer part and fractional part. Integer part is controlled by 2-bit signal
DeltaMStepInteger through the CM_SSC_DELTAMSTEP_DPLL_xxx.DELTAMSTEP_INTEGER bit field.
Fractional part is controlled by 18-bit signal DeltaMStepFraction through the
CM_SSC_DELTAMSTEP_DPLL_xxx.DELTAMSTEP_FRACTION bit field.
The frequency spread achieved has an overshoot of 20 percent or an inaccuracy of +20 percent. If the
CM_CLKMODE_DPLL.DPLL_SSC_DOWNSPREADis set to 1, the frequency spread on lower side is
twice the programmed value. The frequency spread on higher side is 0 (except for the overshoot as
described previously).
There is restriction of range of M values. The restriction is M-ΔM should be ≥ 20. Also, M+ΔM should be ≤
2045. In case the downspread feature is enabled, M-2*ΔM should be ≥ 20 and M ≤ 2045.
8.1.6.6.6 SSC Generation

The configuration of the spreading feature is not mandatory when programming the DPLL. This feature is
usually enabled when the DPLL clocks generate harmonics that can potentially interfere with the GSM
carrier frequencies.
Let's take the SSC featured Display ADPLL and try to set the output frequency to Fout = fc = 11 MHz.
Software most likely sets the DPLL higher to clock the DSS module at a higher functional clock, and then
sets the DISPC_DIVISOR to achieve an 11 MHz pixel clock. But in this example, the PLL is set to output
11 MHz. The frequency of the input clock source for Display ADPLL is Finp = 25 MHz.
1. The desired output frequency can be achieved with the following ratio of the divider coefficients: (M /
M2) * 1 / (N + 1) = Fout / Finp = 11 / 25. The dividers used in the Display ADPLL can be set within the
following ranges: N = 0..127; M = 0..2047; M2 = 1;2. The desired output frequency is achieved through
the following choice of possible divider values: M = 22; N = 4; and M2 = 10. In that case the reference
clock Fref = Finp / (N + 1) = 25 / (4 + 1) = 5 MHz.
The feedback divider value M = 22 is chosen to satisfy the restriction from Section 8.1.6.6. If, for
example, the deviation ΔM / M = Δf fc= 0.05 (5%) is chosen, we have M + ΔM < 2045 and at the same
time M + ΔM > 20
Once the clock generation control registers are configured, it is possible to configure the spreading on
the clock signal.
2. Calculate the ratio between central(output) frequency and modulation frequency on the base of the
desired peak power reduction (PPR) and chosen relative deviation Δf / Fout, where Δf / Fout = fm / fc* 10 ^
(PPR / 10). To achieve PPR = 10dB with SSC deviation (Δf / fc) chosen to be equal to 5 percent, fm =
Δf / 10(PPR/10) = 55 kHz. To check whether the modulation frequency has the appropriate value, check
whether it is within the DPLL loop bandwidth or if fm < Fref / 70 = 5 / 70 = 71.4 KHz, which is true.
3. Calculate the contents of the MODFREQDEV_MANTISSA and MODFREQDEV_EXPONENT bit fields
on the base of ModFreqDivider value: ModFreqDivider = Fref / (4 * fm) = 5 / (4 * 0.055) = 22.73. The
resulting value needs to be put in the form MODFREQDEV_MANTISSA * 2MODFREQDEV_EXPONENT. Thus,
we can approximate 23 = 23 * 20. The approximation will just slightly affect the PPR.
This means we should write MODFREQDEV_EXPONENT = 0x0 and MODFREQDEV_MANTISSA =
0x17.
4. The DeltaMStep parameter is calculated according to the formula: DeltaMStep = ΔM / ModFreqDivider.
Since ΔM = M * (Δf / fc), DeltaMStep = M * (Δf / fc) / ModFreqDivider. Thus in this example, DeltaMStep
= 22 * 0.05 / 23 = 0.047826.
In this case, write 0x0 in DELTAMSTEP_INTEGER (bits 19:18). To express the fractional part 0.05 as
a binary, calculate: 0.047826 * 2^18 = 12537.3, then round to 12537, convert the integer part to binary
and write it into the field: DELTAMSTEP_FRACTIONAL (bits 17:0) = 0x30F9.
5. The spreading must be enabled using the SSC_EN bit.
NOTE: It is necessary to configure the spreading on a clock carefully to avoid adding noise on
frequencies that are used by another module. For example, adding spreading on a clock to
reduce noise on GSM frequencies can "move" the generated noise to the frequency of the
memory controller and degrade its performance.
The state of the modulation feature can be monitored with the DPLL_SSC_ACK bit of the
corresponding register.
8.1.6.7 Core PLL Description

The Core PLL provides the source for a majority of the device infrastructure and peripheral clocks. The
Core PLL comprises an ADPLLS with HSDIVIDER and additional dividers and muxes located in the
PRCM as shown in Figure 8-13.
Figure 8-13. Core PLL
HSDIVIDER To DDR,
CORE_CLKOUTM6
M6 Display, MPU
A PLLs
Core PLL
(ADPLLS) PRCM B
PER_CLKOUTM2
1 /1, /2
(192 MHz) SGX CORECLK
0 (0) (1)
CLKINPULOW L3S_CLK
ULOWCLKEN L4_PER_CLK
/2 L4_WKUP_CLK
CLKDCOLDO CLKINPHIFLDO
L3F_CLK
CORE_CLKOUTM4 L4F_CLK
(CLK_M_OSC)
M4
(200 MHz) C PRU-ICSS_IEP_CLK,
CLKOUT 0
Master
Debugss_clka
Osc
CLKOUTx2 DISP_CLKOUT 1 PRU-ICSS OCP_CLKL

CLKINP D
CLKOUTHIF CPTS_RFT_CLK
0
(Enet switch
CORE_CLKOUTM5 1
M5 IEEE1588v2)
(250 MHz)
0
ALT_CLK1 1 CLKINBYPASS MHZ_250_CLK
(RGMII gigabit)
ALT_CLK2 2
/2 MHZ_125_CLK
Test.CDR (via P1500) (Enet switch bus
Reset default = 0 interface)
/2, /5 MHZ_50_CLK
(RGMII 100 Mbps
and RMII)
/10
MHZ_5_CLK
(RGMII 10 Mbps)
ALT_CLK3
E
ALT_CLKs are to be used for internal test purpose and should not be used in functional mode.
Table 8-21. PLL and Clock Frequences

Mux Select Register BitSection 9.2.4.4
A PRCM.CLKSEL_GFX_FCLK[1]
B PRCM.CLKSEL_GFX_FCLK[0]
C PRCM.CLKSEL_PRU-ICSS_OCP_CLK[0]
D PRCM.CM_CPTS_RFT_CLKSEL[0]
E TEST.CDR (via P1500)
Table 8-22 gives the typical PLL and clock frequencies. The HSDIVIDER is used to generate three divided
clocks M4, M5 & M6. M4 & M5 are nominally 200 & 250 MHz, respectively.
Table 8-22. Core PLL Typical Frequencies (MHz)

Power-On-Reset /
OPP100 OPP50 (1) (2)
CLOCK Source HSDIVIDER Bypass
DIV Freq DIV Value Freq (MHz) DIV Value Freq (MHz)
CLKDCOLDO (PLL
APLLS - - - 2000 - 100
Lock frequency)
HSDIVIDER-
CORE_CLKOUTM4 - Mstr Xtal 10 200 1 100
M4
L3F_CLK, L4F_CLK,
PRU-ICSS IEP CLK,
CORE_CLKO
DebugSS clka, - Mstr Xtal - 200 - 100
UTM4
SGX.MEMCLK,
SGX.SYSCLK
CORE_CLKO
L4_PER, L4_WKUP 2 Mstr Xtal / 2 2 100 2 50
UTM4
CORE_CLKO 1 Mstr Xtal 1 200 1 100
SGX CORECLK
UTM4 2 100 2 50
HSDIVIDER-
M5
MHZ_250_CLK (Gigabit CORE_CLKO
- NA - 250 - NA
RGMII) UTM5
MHZ_125_CLK
CORE_CLKO
(Ethernet Switch Bus 2 Mstr Xtal / 2 2 125 2 50
UTM5
Clk)
MHZ_50_CLK (100
CORE_CLKO
mbps RGMII or 10/100 5 Mstr Xtal / 5 5 50 2 50
UTM5
RMII)
MHZ_5_CLK (10 mbps
MHZ_50_CLK 10 Mstr Xtal / 50 10 5 10 5
RGMII)
HSDIVIDER
M6
(1)
Not all interfaces and peripheral modules are available in OPP50. For more information, see the device specific datasheet.
(2)
For limitations using OPP50, see AM335x ARM Cortex-A8 Microprocessors (MPUs) Silicon Errata (literature number SPRZ360).
The ADPLLS module supports two different bypass modes via their internal MNBypass mode and their
external Low Power Idle bypass mode. The PLLs are in the MNBypass mode after power-on reset and
can be configured by software to enter Low Power Idle bypass mode for power-down.
When the Core PLL is configured in bypass mode, the HSDIVIDER enters bypass mode and the
CLKINBYPASS input is driven on the M4, M5, and M6 outputs. CLKINBYPASS defaults to the master
oscillator input (typically 24 MHz).
Table 8-23. Bus Interface Clocks

SGX530 (MEMCLK & SYSCLK), LCDC, MPU Subsystem, GEMAC
L3F_CLK Switch (Ethernet), DAP, PRU-ICSS, EMIF, TPTC, TPCC, OCMC
RAM, DEBUGSS, AES, SHA
L3S_CLK USB, TSC, GPMC, MMCHS2, McASP0, McASP1
DCAN0, DCAN1, DES
DMTIMER2, DMTIMER3, DMTIMER4, DMTIMER5, DMTIMER6,
DMTIMER7
eCAP/eQEP/ePWM0, eCAP/eQEP/ePWM1, eCAP/eQEP/ePWM2,
eFuse
L4_PER_CLK ELM, GPIO1, GPIO2, GPIO3
I2C1, I2C2, IEEE1500, LCD, Mailbox0
McASP0, McASP1
MMCHS0, MMCHS1, OCP Watchpoint, PKARNG
SPI0, SPI1, Spinlock
UART1, UART2, UART3, UART4, UART5
ADC_TSC, Clock Manager, Control Module
DMTIMER0, DMTIMER1_1MS, GPIO0
L4_WKUP_CLK
I2C0, M3UMEM, M3DMEM, SmartReflex0, SmartReflex1
UART0, WDT0, WDT1
8.1.6.7.1 Core PLL Configuration
1. Switch PLL to bypass mode by setting CM_CLKMODE_DPLL_CORE.DPLL_EN to 0x4.

2. Wait for CM_IDLEST_DPLL_CORE.ST_MN_BYPASS = 1 to ensure PLL is in bypass
(CM_IDLEST_DPLL_CORE.ST_DPLL_CLK should also change to 0 to denote the PLL is unlocked).
3. Configure Multiply and Divide values by setting CM_CLKSEL_DPLL_CORE.DPLL_MULT and
DPLL_DIV to the desired values.
4. Configure M4, M5 and M6 dividers by setting HSDIVIDER_CLKOUT1_DIV bits in
CM_DIV_M4_DPLL_CORE,CM_DIV_M5_DPLL_CORE, and CM_DIV_M6_DPLL_CORE to the
desired values.
5. Switch over to lock mode by setting CM_CLKMODE_DPLL_CORE.DPLL_EN to 0x7.
6. Wait for CM_IDLEST_DPLL_CORE.ST_DPLL_CLK = 1 to ensure PLL is locked
(CM_IDLEST_DPLL_CORE.ST_MN_BYPASS should also change to 0 to denote the PLL is out of
bypass mode).
Note: M4, M5, and M6 dividers can also be changed on-the-fly so that there is no need to put the PLL in
bypass and back to lock mode. After changing CM_DIV_Mx_DPLL_CORE.DPLL_CLKOUT_DIV, check
CM_DIV_Mx_DPLL_CORE.DPLL_HSDIVIDER_CLKOUT1_DIVCHACK for a toggle (a change from 0 to 1
or 1 to 0) to see if the change was acknowledged by the PLL.
8.1.6.8 Peripheral PLL Description

The Per PLL provides the source for peripheral functional clocks. The Per PLL comprises an ADPLLLJ
and additional dividers and muxes located in the PRCM as shown
Figure 8-14. Peripheral PLL Structure
Master
Osc
(CLK_M_OSC)
Per PLL
(ADPLLLJ)
0
USB_PHY_CLK (960 MHz)
ALT_CLK1 1 CLKINP CLKDCOLDO To USB PHY
ALT_CLK2 2
PER_CLKOUTM2 PRCM
TEST.CDR (via P1500) (192 MHz)
CLKOUT PRU_ICSS_UART_CLK
Reset default = 0
(96 MHz)
/2 MMC_CLK
(48 MHz) SPI_CLK

/4 CONTROL_CLK32K
UART_CLK
Controls CLK_48 DIVRATIO_CTRL[0]*
I2C_CLK
CLKINPULOW
/2 /732.4219 0
ULOWCLKEN CLK_24
ULOWPRIORITY
/366.2109 1
(32,768 Hz)
CLK_32KHZ
To DDR, Disp, MPU PLLs bypass
clocking PRCM SGX clock mux
*Reset default zero
ALT_CLKs are to be used for internal test purpose and should not be used in functional mode.
The PLL is locked at 960 MHz. The PLL output is divided by the M2 divider to generate a 192-MHz
CLKOUT. This clock is gated in the PRCM to form the PRU-ICSS UART clock. There is a /2 divider to
create 96 MHz for MMC_CLK. The clock is also divided within the PRCM by a fixed /4 divider to create a
48-MHz clock for the SPI, UART and I2C modules. The 48-MHz clock is further divided by a fixed /2
divider and a fixed /732.4219 divider to create an accurate 32.768-KHz clock for Timer and debounce use.
Table 8-24. Per PLL Typical Frequencies (MHz)

Power-On-Reset / PLL
OPP100 OPP50 (1) (2)
Bypass
Clock Source
Freq Freq
DIV Value Freq DIV Value DIV Value
(MHz) (MHz)
PLL Lock frequency PLL - - - 960 - 960
USB_PHY_CLK CLKDCOLDO - Held Low - 960 - 960
CLKOUT of
ADPLLLJ
CLKOUT uses PLL’s
N2 is 0 on Mstr Xtal/
PER_CLKOUTM2 M2 Divider when PLL 5 192 10 96
power-on-reset (N2+1)
is locked and PLL’s
N2 divider when PLL
Bypass
Mstr Xtal/
MMC_CLK PER_CLKOUTM2 2 2 96 2 48
((N2+1)*2)
SPI_CLK,
Mstr Xtal/
UART_CLK, PER_CLKOUTM2 4 4 48 4 24
((N2+1)*4)
I2C_CLK
CLK_24 CLK_48 2 CLK_48 /2 2 24 2 12
CLK_24 CLK_24 /
CLK_32KHZ 732.4219 732.4219 0.032768 366.2109 0.032768
(output of CLK_48/2) <CLK32_DIV>
(1)
For limitations using OPP50, see AM335x ARM Cortex-A8 Microprocessors (MPUs) Silicon Errata (literature number SPRZ360).
(2)
Not all interfaces and peripheral modules are available in OPP50. For more information, see AM335x ARM Cortex-A8
Microprocessors (MPUs) Silicon Errata (literature number SPRZ360).
The ADPLLLJ module supports two different bypass modes via their internal MNBypass mode and their
external Low Power Idle bypass mode. The PLLs are in the MNBypass mode after power-on reset and
can be configured by software to enter Low Power Idle bypass mode for power-down.
The PER PLL can use the Low Power Idle bypass mode. When the internal bypass mode is selected, the
CLKOUT output is driven by CLKINP/(N2+1) where N2 is driven by the PRCM. CLKINP defaults to the
master oscillator input (typically 24 MHz)
8.1.6.8.1 Configuring the Peripheral PLL

The following steps detail how to configure the peripheral PLL.
1. Switch PLL to bypass mode by setting CM_CLKMODE_DPLL_PER.DPLL_EN to 0x4.
2. Wait for CM_IDLEST_DPLL_PER.ST_MN_BYPASS = 1 to ensure PLL is in bypass
(CM_IDLEST_DPLL_PER.ST_DPLL_CLK should also change to 0 to denote the PLL is unlocked).
3. Configure Multiply and Divide values by setting CM_CLKSEL_DPLL_PER.DPLL_MULT and DPLL_DIV
to the desired values.
4. Configure M2 divider by setting CM_DIV_M2_DPLL_PER.DPLL_CLKOUT_DIV to the desired value.
5. Switch over to lock mode by setting CM_CLKMODE_DPLL_PER.DPLL_EN to 0x7.
6. Wait for CM_IDLEST_DPLL_PER.ST_DPLL_CLK = 1 to ensure PLL is locked
(CM_IDLEST_DPLL_PER.ST_MN_BYPASS should also change to 0 to denote the PLL is out of
bypass mode).
Note: M2 divider can also be changed on-the-fly (ie., there is no need to put the PLL in bypass and back
to lock mode). After changing CM_DIV_M2_DPLL_PER.DPLL_CLKOUT_DIV, check
CM_DIV_M2_DPLL_PER.DPLL_CLKOUT_DIVCHACK for a toggle (a change from 0 to 1 or 1 to 0) to see
if the change was acknowledged by the PLL.
8.1.6.9 MPU PLL Description

The Cortex A8 MPU subsystem includes an internal ADPLLS for generating the required Cortex A8 MPU
clocks. This PLL is driven by the master oscillator output with control provided by PRCM registers.
Figure 8-15. MPU Subsystem PLL Structure
PRCM
Control
Master
Osc
(CLK_M_OSC) MPU PLL
(ADPLLS)
0
ALT_CLK1 1 CLKINP
ALT_CLK2 2
CLKOUT A8 clock
TEST.CDR (via P1500)
CORE_CLKOUTM6 0
CLKINPULOW
PER_CLKOUTM2 1
CONTROL.PLL_CLKINPULOW_CTRL.MPU_PLL_CLKINPULOW_SEL
(Reset default = 0)
ULOWCLKEN
PRCM.CM_CLKSEL_DPLL_MPU.DPLL_BYP_CLKSEL 0: CLKINP
(Reset default = 0) 1: CLKINPULOW
ULOWPRIORITY
MPU subsystem
For example:
For a frequency for MPU, say 600 MHz, the ADPLLS is configured (PLL locked at 1200 MHz and M2
Divider =1) so as to expect CLKOUT = 600 MHz .
The ULOWCLKEN input from a programmable PRCM register selects whether CLKINP or CLKINPULOW
is the bypass clock source. This is a glitch free switch. When CLKINP is selected it is sourced through the
ADPLLS 1/(N2+1) divider. The PRCM register defaults to 0 on power-up to select the CLKINP source.
The CLKINPULOW input may be sourced from the CORE_CLKOUTM6 from the Core PLL, or
PER_CLKOUTM2 from the Per PLL. These PLL output clocks can be used as alternate clock sources in
low power active use cases for the MPU Subsystem clock when the PLL is in bypass mode.
8.1.6.9.1 Configuring the MPU PLL

The following steps detail how to configure the MPU PLL.
1. Switch PLL to bypass mode by setting CM_CLKMODE_DPLL_MPU.DPLL_EN to 0x4.
2. Wait for CM_IDLEST_DPLL_MPU.ST_MN_BYPASS = 1 to ensure PLL is in bypass
(CM_IDLEST_DPLL_MPU.ST_DPLL_CLK should also change to 0 to denote the PLL is unlocked).
3. Configure Multiply and Divide values by setting CM_CLKSEL_DPLL_MPU.DPLL_MULT and
4. Configure M2 divider by setting CM_DIV_M2_DPLL_MPU.DPLL_CLKOUT_DIV to the desired value.
5. Switch over to lock mode by setting CM_CLKMODE_DPLL_MPU.DPLL_EN to 0x7.
6. Wait for CM_IDLEST_DPLL_MPU.ST_DPLL_CLK = 1 to ensure PLL is locked
(CM_IDLEST_DPLL_MPU.ST_MN_BYPASS should also change to 0 to denote the PLL is out of
bypass mode).
to lock mode). After changing CM_DIV_M2_DPLL_MPU.DPLL_CLKOUT_DIV, check
CM_DIV_M2_DPLL_MPU.DPLL_CLKOUT_DIVCHACK for a toggle (a change from 0 to 1 or 1 to 0) to see
8.1.6.10 Display PLL Description

The Display PLL provides the pixel clock required for the LCD display and is independent from the other
peripheral and infrastructure clocks. The PLL is clocked from the Master Oscillator. The ADPLLS M2
divider determines the output clock frequency which is clock gated by the PRCM as shown in Figure 8-16.
Figure 8-16. Display PLL Structure

PRCM.CLKSEL_LCDC_PIXEL_CLK
(Reset default = 0)
Master Display PLL PRCM

Osc
(CLK_M_OSC) (ADPLLS)
0
ALT_CLK1 1 CLKINP
2 CLKOUT 0
ALT_CLK2
CLKOUTx2 1 LCD_CLK
CLKOUTHIF
2
CORE_CLKOUTM6 0 CLKDCOLDO
CLKINPULOW
PER_CLKOUTM2 1
CONTROL.PLL_CLKINPULOW_CTRL.DISP_
PLL_CLKINPULOW_SEL (Reset default = 0)
ULOWCLKEN
PRCM.CM_CLKSEL_DPLL_DISP. 0: CLKINP
DPLL_BYP_CLKSEL (Reset default = 0) 1: CLKINPULOW
ULOWPRIORITY
CORE_CLKOUTM5
PER_CLKOUTM2
For example: say frequency for pixel clock 100 MHz, the ADPLLS is configured (PLL locked at 200 MHz
and M2 Divider =1) so as to expect CLKOUT = 100 MHz.
The CLKINPULOW input is sourced from the CORE_CLKOUTM6 from the Core PLL or PER_CLKOUTM2
from the Per PLL. This PLL output clock can be used as an alternate clock source in low power active use
cases for the pixel clock when the Display PLL is in bypass mode.
8.1.6.10.1 Configuring the Display PLL

The following steps detail how to configure the display PLL.
1. Switch PLL to bypass mode by setting CM_CLKMODE_DPLL_DISP.DPLL_EN to 0x4.
2. Wait for CM_IDLEST_DPLL_DISP.ST_MN_BYPASS = 1 to ensure PLL is in bypass
(CM_IDLEST_DPLL_DISP.ST_DPLL_CLK should also change to 0 to denote the PLL is unlocked).
3. Configure Multiply and Divide values by setting CM_CLKSEL_DPLL_DISP.DPLL_MULT and
4. Configure M2 divider by setting CM_DIV_M2_DPLL_DISP.DPLL_CLKOUT_DIV to the desired value.
5. Switch over to lock mode by setting CM_CLKMODE_DPLL_DISP.DPLL_EN to 0x7.
6. Wait for CM_IDLEST_DPLL_DISP.ST_DPLL_CLK = 1 to ensure PLL is locked
(CM_IDLEST_DPLL_DISP.ST_MN_BYPASS should also change to 0 to denote the PLL is out of
bypass mode).
to lock mode). After changing CM_DIV_M2_DPLL_DISP.DPLL_CLKOUT_DIV, check
CM_DIV_M2_DPLL_DISP.DPLL_CLKOUT_DIVCHACK for a toggle (a change from 0 to 1 or 1 to 0) to
see if the change was acknowledged by the PLL.
8.1.6.11 DDR PLL Description

The DDR PLL provides the clocks required by the DDR macros and the EMIF and is independent from the
other peripheral and infrastructure clocks. The PLL is clocked from the Master Oscillator. The ADPLLS M2
divider determines the output clock frequency which is connected directly to the DDR Macros. The clock is
also routed through the PRCM where a fixed /2 divider is used to create the M_CLK used by the EMIF as
shown in Figure 8-17.
Figure 8-17. DDR PLL Structure
Master DDR PLL

Osc
(CLK_M_OSC) (ADPLLS) IDID
CLKOUT IDID
0 IDID
ALT_CLK1 1 CLKINP PRCM macros
ALT_CLK2 2
CLKOUTx2
CLKOUTHIF
/2 EMIF M_CLK
CORE_CLKOUTM6 0 CLKDCOLDO
CLKINPULOW
PER_CLKOUTM2 1
CONTROL.PLL_CLKINPULOW_CTRL.DDR_
PLL_CLKINPULOW_SEL (Reset default = 0)
ULOWCLKEN
PRCM.CM_CLKSEL_DPLL_DDR. 0: CLKINP
DPLL_BYP_CLKSEL (Reset default = 0) 1: CLKINPULOW
ULOWPRIORITY
For OPP information, see the device-specific data manual.

Example frequency for DDR clock, say 266 MHz, the ADPLLS is configured (PLL locked at 532 MHz and
M2 Divider =1) so as to expect CLKOUT = 266 MHz.
The CLKINPULOW input may be sourced from the CORE_CLKOUTM6 from the Core PLL, or
PER_CLKOUTM2 from the Per PLL. These PLL output clocks can be used as alternate clock sources in
low power active use cases for the DDR clocks when PLL is in bypass mode
8.1.6.11.1 Configuring the DDR PLL

The following steps detail how to configure the DDR PLL.
1. Switch PLL to bypass mode by setting CM_CLKMODE_DPLL_DDR.DPLL_EN to 0x4.
2. Wait for CM_IDLEST_DPLL_DDR.ST_MN_BYPASS = 1 to ensure PLL is in bypass
(CM_IDLEST_DPLL_DDR.ST_DPLL_CLK should also change to 0 to denote the PLL is unlocked).
3. Configure Multiply and Divide values by setting CM_CLKSEL_DPLL_DDR.DPLL_MULT and
4. Configure M2 divider by setting CM_DIV_M2_DPLL_DDR.DPLL_CLKOUT_DIV to the desired value.
5. Switch over to lock mode by setting CM_CLKMODE_DPLL_DDR.DPLL_EN to 0x7.
6. Wait for CM_IDLEST_DPLL_DDR.ST_DPLL_CLK = 1 to ensure PLL is locked
(CM_IDLEST_DPLL_DDR.ST_MN_BYPASS should also change to 0 to denote the PLL is out of
bypass mode).
Note: M2 divider can also be changed on-the-fly (i.e., there is no need to put the PLL in bypass and back
to lock mode). After changing CM_DIV_M2_DPLL_DDR.DPLL_CLKOUT_DIV, check
CM_DIV_M2_DPLL_DDR.DPLL_CLKOUT_DIVCHACK for a toggle (a change from 0 to 1 or 1 to 0) to see
8.1.6.12 CLKOUT Signals

The CLKOUT1 and CLKOUT2 signals go device pads and should mainly be used as debug testpoints.
Using these signals for time-critical external circuits is discouraged because of unpredictable jitter
performance. For more information, see the device datasheet, AM335x Sitara Processors (literature
number SPRS717). CLKOUT1 is created from the master oscillator. CLKOUT2 can be sourced from the
32-KHz crystal oscillator or any of the PLL (except MPU PLL) outputs. The selected output can be further
modified by a programmable divider to create the desired output frequency.
Figure 8-18. CLKOUT Signals
Master PRCM
Osc CLKOUT1
(CLK_M_OSC)
32K Osc 1/1(0)

(CLK_32K_RTC) 0 1/2(1)
1/3(2)
L3F_CLK 1 1/4(3)
1/5(4)
DDR_PHY_CLK 2 1/6(5)
CLKOUT2
1/7(6)
PER_CLKOUT_M2 3
4
PIXEL_CLK
PRCM.CM_CLKOUT_CTRL.CLKOUT2SOURCE PRCM.CM_CLKOUT_CTRL.CLKOUT2DIV
(Default = 0) (Default = 0)
8.1.6.13 Timer Clock Structure

The CLK_32KHZ clock is an accurate 32.768-kHz clock derived from the PER PLL and can also be
selected for the WDT1. The DMTIMER0 can only be clocked from the internal RC oscillator
(CLK_RC32K). The clock options are shown in Figure 8-19.
Figure 8-19. Watchdog Timer Clock Selection
Device
PRCM
On-Chip ~32 kHz
32K RC Osc 0
(CLK_RC32K)
To WDT1
CLK_32KHZ 32 kHz
1
From PRCM PRCM.CLKSEL_WDT1_
CLK.CLKSEL
To DMTIMER0
Figure 8-20. Watchdog and Secure Timer Clock Selection (For Secure Devices only)
Device
PRCM
On-Chip ~32,768 Hz
32K RC Osc 0
(CLK_RC32K)
To WDT0
(Secure)
CLK_32KHZ 32,768 Hz
1
From PRCM CONTROL.SEC_CLK_
CTRL.SECWDCLKSEL
0 (Default: 0)
To WDT1
1
PRCM.CLKSEL_WDT1_
CLK.CLKSEL
(Default: 0)
0
1
To DMTIMER0
Master
Xtal Osc 2
(CLK_M_OSC)
TCLKIN 3 CONTROL.SEC_CLK_CTRL.
SECTIMERCLKSEL
(Default: 0)
All mux selections are in PRCM unless explicitly shown otherwise in the diagrams.
The clock selections for the other device Timer modules are shown in Figure 8-21. CLK_32KHZ, the
master oscillator, and the external pin (TCLKIN) are optional clocks available for timers which may be
selected based on end use application.
DMTIMER1 is implemented using the DMTimer_1ms module which is capable of generating an accurate
1ms tick using a 32.768 KHz clock. During low power modes, the Master Oscillator is disabled.
CLK_32KHZ also would not be available in this scenario since it is sourced from the Master Osc based
PER PLL. Hence, in low power modes DMTIMER1 in the WKUP domain can use the 32K RC oscillator for
generating the OS (operating system) 1ms tick generation and timer based wakeup. Since most
applications expect an accurate 1ms OS tick which the inaccurate 32K RC (16-60 KHz) oscillator cannot
provide, a separate 32768 Hz oscillator (32K Osc) is provided as another option.
Figure 8-21. Timer Clock Selection
Device
PRCM
32K
32,768 Hz 32,768 Hz
Osc 4
Xtal (CLK_32K_RTC)
On-Chip
~32,768 Hz
32K RC Osc 3
(CLK_RC32K)
CLK_32KHZ 32,768 Hz
1 To
From PLL DMTIMER1_1ms
Master
Osc 0
Xtal
(CLK_M_OSC)
TCLKIN 2
PRCMCLKSEL_TIME
R1MS_CLK.CLKSEL
(Default: 0)
2
6
1 x6 To
6 6 DMTIMER{2-7}
0 PRCMCLKSEL_TIME
6 Rn_CLK.CLKSEL
(Default: 1)
The RTC, Debounce and VTP clock options are shown in Figure 8-22. In low power modes, the debounce
for GPIO0 in WKUP domain can use the accurate 32768 Hz crystal oscillator or the inaccurate (16 KHz to
60 KHz) 32K RC oscillator when the Master Osc is powered down.
The 32K Osc requires an external 32768-Hz crystal.
Figure 8-22. RTC, VTP, and Debounce Clock Selection
Device
RTC.OSC_REG.SEL_32KCLK_SRC
32K 32,768 Hz
32,768 Hz 1 (Reset default = 0)
Osc
Xtal (CLK_32K_RTC)
RTC clock
PRCM
CLK_32KHZ 32,768 Hz
0
From PLL
RTC IP
1
2 To GPIO0 debounce
On-Chip
~32,768 Hz PRCM.CLKSEL_GPIO0_DBCLK.
32K RC Osc 0
(CLK_RC32K) CLKSEL (Reset default = 0)
To GPIO{1-6}, MMC, etc.

Debounce
Master
Osc To VTP
Xtal /2 control
(CLK_M_OSC)
8.1.7 Reset Management
8.1.7.1 Overview
The PRCM manages the resets to all power domains inside device and generation of a single reset output
signal through device pin, WARMRSTn, for external use. The PRCM has no knowledge of or control over
resets generated locally within a module, e.g., via the OCP configuration register bit
IPName_SYSCONFIG.SoftReset.
All PRM reset outputs are asynchronously asserted. These outputs are active-low except for the PLL
resets. Deassertion is synchronous to the clock which runs a counter used to stall, or delay, reset de-
assertion upon source deactivation. This clock will be CLK_M_OSC used by all the reset managers. All
modules receiving a PRCM generated reset are expected to treat the reset as asynchronous and
implement local re-synchronization upon de-activation as needed.
One or more Reset Managers are required per power domain. Independent management of multiple reset
domains is required to meet the reset sequencing requirements of all modules in the power domain
8.1.7.2 Reset Concepts and Definitions

The PRCM collects many sources of reset. Here below is a list of qualifiers of the source of reset:
• Cold reset: it affects all the logic in a given entity
• Warm reset: it is a partial reset which doesn’t affect all the logic in a given entity
• Global reset: it affects the entire device
• Local reset: it affects part of the device (1 power domain for example)
• S/W reset: it is initiated by software
• H/W reset: it is hardware driven
Each reset source is specified as being a cold or warm type. Cold types are synonymous with power-on-
reset (POR) types. Such sources are applied globally within each receiving entity (i.e., sub-system,
module, macro-cell) upon assertion. Cold reset events include: device power-up, power-domain power-up,
and eFuse programming failures.
Warm reset types are not necessarily applied globally within each receiving entity. A module may use a
warm reset to reset a subset of its logic. This is often done to speed-up reset recovery time, i.e., the time
to transition to a safe operating state, compared to the time required upon receipt of a cold reset. Warm
reset events include: software initiated per power-domain, watch-dog time-out, security violation, externally
triggered, and emulation initiated.
Reset sources, warm or cold types, intended for device-wide effect are classified as global sources. Reset
sources intended for regional effect are classified as local sources.
Each Reset Manager provides two reset outputs. One is a cold reset generated from the group of global
and local cold reset sources it receives. The other is a warm+cold reset generated from the combined
groups of, global and local, cold and warm reset sources it receives.
The Reset Manager asserts one, or both, of its reset outputs asynchronously upon reset source assertion.
Reset deassertion is extended beyond the time the source gets de-asserted. The reset manager will then
extend the active period of the reset outputs beyond the release of the reset source, according to the
PRCM’s internal constraints and device’s constraints. Some reset durations can be software-configured.
Most (but not all) reset sources are logged by PRCM’s reset status registers. The same reset output can
generally be activated by several reset sources and the same reset source can generally activate several
reset outputs. All the reset signals output of the PRCM are active low. Several conventions are used in
this document for signal and port names. They include:
• "_RST" in a signal or port name is used to denote reset signal.
• "_PWRON_RST" in a signal or port name is used to denote a cold reset source
8.1.7.3 Global Power On Reset (Cold Reset)

There are several cold reset sources. See Table 8-25 for a summary of the different reset sources.
8.1.7.3.1 Power On Reset (PORz)

The source of power on reset is PORz signal on the device. Everything on device is reset with assertion of
power on reset. This reset is non-blockable. PORz can be driven by external power management devices
or power supervisor circuitry. During power-up, when power supplies to the device are ramping up, PORz
needs to be driven Low. When the ramp-up is complete and supplies reach their steady-state values,
PORz need to be driven High. During normal operation when any of the device power supplies are turned
OFF, PORz must be driven Low.
8.1.7.3.2 PORz Sequence

• PORz pin at chip boundary gets asserted (goes low). Note: The state of nRESETIN_OUT during
PORz assertion should be a don’t care, it should not affect PORz (only implication is if they are both
asserted and nRESETIN_OUT is deasserted after PORz you will get re-latching of boot config pins
and may see warm nRESETIN_OUT flag set in PRCM versus POR).
• All IOs will go to a known state, as defined in the device datasheet, AM335x Sitara Processors
(literature number SPRS717)
• When power comes-up, PORz value will propagate to the PRCM.
• PRCM will fan out reset to the complete chip and all logic which uses async reset will get reset.
nRESETIN_OUT will go low to indicate reset-in-progress.
• External clocks will start toggling and PRCM will propagate these clocks to the chip keeping PLLs in
bypass mode.
• All logic using sync reset will get reset.
• When power and clocks to the chip are stable, PORz must be de-asserted.
• Boot configuration pins are latched upon de-assertion of PORz pin
• IO cell controls from IPs for all the IOs with a few exceptions (see datasheet for details) are driven by
GPIO module. GPIO puts all IOs in input mode.
• FuseFarm reset will be de-asserted to start eFuse scanning.
• Once eFuse scanning is complete, reset to the host processor and to all other peripherals (peripherals
without local processor) will be de-asserted.
• nRESETIN_OUT will be de-asserted after time defined by PRM_RSTTIME.RSTTIME1.

• Once host processors finish booting then all remaining peripherals will see reset de-assertion.
Note that all modules with local CPUs will have local reset asserted by default at PORz and reset de-
assertion would require host processor to write to respective registers in PRCM.
Figure 8-23. PORz

(1)
All supplies stable Duration defined by Duration defined by
PRCM.PRM_RSTTIME [9:0] PRCM.PRM_RSTTIME [14:10]
RSTTIME1 RSTTIME2
(2)
greater than t sx
High frequency system input clock
CLK_M_OSC
PORz
Tri-stated with weak

external pullup
nRESETIN_OUT
Internal Chip Resetn
CLKOUT1 (If SYSBOOT5 = 1)
(1) nRESETIN_OUT is not defined (can either be driven low or pulled up high) until all supplies are fully ramped
up. For nRESETIN_OUT to maintain a valid low state until the supples are ramped, an external buffer should
be implemented, as shown in Figure 8-24.
(2) For information on tsx, see AM335x Sitara Processors (literature number SPRS717).
Figure 8-24. External Buffer for nRESETIN_OUT

VDDSHV3 Warm reset to other devices
4.7K on the board
nRESETIN_OUT
VIN of PMIC
Device
Open-drain
buffer
PORz PORz from external PMIC
8.1.7.3.3 Bad Device Reset

This reset is asserted whenever the DEVICE_TYPE encodes an unsupported device type, such as the
code for a "bad" device.
8.1.7.3.4 ICEPICK Power On Reset

The internal emulation module, ICE-Pick, generates ICEPICK_POR_RST. This reset is used in emulation
mode only. The PRCM is required to provide an output port, ACT_LIKE_SECURE, which is
asynchronously set to logic high upon ICEPICK_POR_RST assertion. This state must be maintained until
a normal system POR occurs.
8.1.7.3.5 Global Cold Software Reset (GLOBAL_COLD_SW_RST)

The source for GLOBAL_COLD_SW_RST is generated internally by the PRM. It is activated upon setting
the PRM_RSTCTRL.RST_GLOBAL_COLD_SW bit in the PRM memory map. This bit is self-clearing, i.e.,
it is automatically cleared by the hardware.
8.1.7.4 Global Warm Reset
8.1.7.4.1 External Warm Reset

nRESETIN_OUT is a bidirectional warm reset signal. As an input, it is typically used by an external source
as a device reset. Refer to Table 8-24 for a summary of the differences between a warm reset and cold
reset. Some of these differences are:
• The warm reset can be blocked to the EMAC switch and its reference clock source PLL using the
RESET_ISO register in the Control Module.
• The warm reset assumes that clocks and power to the chip are stable from assertion through
deassertion, whereas during the cold reset, the power supplies can become stable during assertion
• Some PRCM and Control module registers are warm reset insensitive and maintain their value
throughout a warm reset
• SYSBOOT pins are not latched with a warm reset. The device will boot with the SYSBOOT values
from the previous cold reset.
• Most debug subsystem logic is not affected by warm reset. This allows you to maintain any debug
sessions throughout a warm reset event.
• PLLs are not affected by warm reset
As an output, nRESETIN_OUT can be used to reset external devices. nRESET_OUT will drive low during
a cold reset or an internally generated warm reset. After completion of a cold or warm reset,
nRESETIN_OUT will continue to drive low for a period defined by PRM_RSTTIME.RSTTIME1. RSTTIME1
is a timer that counts down to zero at a rate equal to the high frequency system input clock CLK_M_OSC.
This allows external devices to be held in reset for some time after the AM335x comes out of reset.
Caution must be used when implementing the nRESETIN_OUT as an bi-directional reset signal. Because
of the short maximum time allowed using RSTTIME1, it does not supply an adequate debounce time for
an external push button circuit. The processor could potentially start running while external components
are still in reset. It is recommended that this signal be used as input only (do not connect to other devices
as a reset) to implement a push button reset circuit to the AM335x, or an output only to be able to reset
other devices after an AM335x reset completes.
8.1.7.4.1.1 Warm Reset Input/Reset Output (nRESETIN_OUT)

Any global reset source (internal or external) causes nRESETIN_OUT to be driven and maintained at the
boundary of the device for at least the amount of time configured in the PRCM.PRM_RSTTIME.
RSTTIME1 bit field. This ensures that the device and its related peripherals are reset together. The
nRESETIN_OUT output buffer is configured as an open-drain; consequently, an external pull-up resistor is
required.
After the de-assertion, the bi-directional pin nRESETIN_OUT is tri-stated to allow for assertion from off
chip source (externally).
Figure 8-25. External System Reset
Device VDDSHV6
1.8 or 3.3 V
PRCM
nRESETOUT
nRESET_IN_OUT Pullup RESET to
PRM peripherals on
nRESETIN board
Global reset source

Reset
button
Note: It is recommended to implement warm reset as an input only (for example, push button) or an output only (to
reset external peripherals), not both.
The device will have one pin nRESETIN_OUT which reflects chip reset status. This output will always
assert asynchronously when any chip watchdog timer reset occurs if any of the following reset events
occurs:
• POR (only internal stretched portion of reset event after bootstrap is latched)
• External Warm reset (nRESETIN_OUT pin, only internal stretched portion of reset event after
bootstrap is latched)
• Emulation reset (Cold or warm from ICEPICK)
• Reset requestor
• SW cold/warm reset
This output will remain asserted as long as PRCM keeps reset to the host processor asserted.
Note: TRST does not cause RSTOUTn assertion
8.1.7.4.1.2 Warm Reset Sequence

1. nRESETIN_OUT pin at chip boundary gets asserted (goes low). NOTE: For Warm Reset sequence to
work as described, it is expected that PORz pin is always inactive, otherwise you will get PORz
functionality as described in previous section.
2. All IOs (except test and emulation) will go to tri-state immediately.
3. Chip clocks are not affected as both PLL and dividers are intact.
4. nRESETIN_OUT gets de-asserted after 30 cycles
5. PRCM de-asserts reset to the host processor and all other peripherals without local CPUs.
6. Note that all IPs with local CPUs will have local reset asserted by default at Warm Reset and reset de-
assertion would require host processor to write to respective registers in PRCM.
Figure 8-26 shows the nRESETIN_OUT waveform when using nRESETIN_OUT as warm reset source.
For the duration when external warm reset switch is closed, both the device and chip will be driving zero.
Figure 8-26. Warm Reset Sequence (External Warm Reset Source)

Warm reset source
assertion
Duration defined by Duration defined by
PRCM.PRM_RSTTIME[7:0] PRCM.PRM_RSTTIME [12:8]
RSTTIME1 RSTTIME2
Maximum
50 cycles
CLK_M_OSC
PORz
EMIF FIFO
drains and
DRAM is put
External warm reset assertion in self-refresh
detected on the nRESETIN_OUT pin
Tri-stated with
weak pullup
Warm reset out driven
on nRESETIN_OUT pin
Figure 8-27 shows the nRESETIN_OUT waveform when any one of the warm reset sources captured
except using nRESETIN_OUT itself as warm reset source.
Figure 8-27. Warm Reset Sequence (Internal Warm Reset Source)

Warm reset source
assertion
Duration defined by Duration defined by
PRCM.PRM_RSTTIME[7:0] PRCM.PRM_RSTTIME [12:8]
RSTTIME1 RSTTIME2
Maximum
50 cycles
CLK_M_OSC
PORz
EMIF FIFO
drains and
DRAM is put
Internal warm reset assertion in self-refresh
Tri-stated with
Tri-stated with
weak pullup
weak pullup
Warm reset out driven
on nRESETIN_OUT pin
8.1.7.4.2 Watchdog Timer

There is one watchdog timer on the device. There is a chip level register in control module register space
which contains a sticky bit (cleared only by PORz) for each reset. The reset is not blockable. For more
information, see section 20.4 Watchdog.
8.1.7.4.3 Global Warm Software Reset (GLOBAL_SW_WARM_RST)

GLOBAL_WARM_SW_RST is internally generated by the PRCM. Activation is triggered upon setting the
memory-mapped register bit, PRM_RSTCTRL. RST_GLOBAL_WARM_SW. This bit is self-clearing, and
automatically cleared by the hardware.
8.1.7.4.4 Test Reset (TRSTz)

This reset is triggered from TRSTz pin on JTAG interface. This is a non-blockable reset and it resets test
and emulation logic.
NOTE: A PORz reset assertion should cause entire device to reset including all test and emulation logic
regardless of the state of TRSTz Therefore, PORz assertion will achieve full reset of the device even if
TRSTz pin is pulled permanently high and no special toggling of TRSTz pin is required during power ramp
to achieve full POR reset to the device. Further, it is acceptable for TRSTz input to be pulled permanently
low during normal functional usage of the device in the end-system to ensure that all test and emulation
logic is kept in reset.
8.1.7.5 Reset Characteristics

The following table shows characteristic of each reset source.
Table 8-25. Reset Sources

Cold Reset Sources Warm Reset sources
Characteristic Pin PORz SW Cold Reset Bad Device Pin Warm Reset Watchdog Timer SW Warm Reset TRSTz
Boot pins latched Y N N N N N N
Resets Standard Y N N N N N N
Efuses
Resets Customer Y Y Y Y Y Y N
Efuses
DRAM contents N N N Y (1) Y (1) Y (1) Y
preserved
Resets PLLs (2) Y Y Y N N N N
Resets Clock Y Y Y N N N N
Dividers (2)
PLLs enter bypass Y Y Y Y Y Y N
mode (2)
Reset source N N N Y Y Y Y
blockable by
emulation
Resets test and Y Y Y N N N N
emulation logic
Resets GMAC switch Y N (3) Y N (3) N (3) N (3)
and related chip logic
Resets Chip Y Y Y Y Y Y N
Functional Logic (4)
Puts IOs in Tri-state Y Y Y Y Y Y N
(5) (5) (5) (5)
Resets Pinmux Y Y Y Y Y Y N
Registers
Reset out Assertion Y Y Y (5) Y (5) Y (5) Y (5) N
(nRESETIN_OUT
Pin)
Resets RTC N N N N N N N
(1)
The ROM software does not utilize this feature of DRAM content preservation. Hence, the AM335x re-boots like a cold boot for warm reset as well.
(2)
CORE PLL is an exception when EMAC switch reset isolation is enabled
(3)
Only true if GMAC switch reset isolation is enabled in control registers, otherwise will be reset.
(4)
There are exception details in control module & PRCM registers which are captured in the register specifications in Chapter 8 and Chapter 9. This includes some pinmux registers which
are warm reset in-sensitive.
(5)
Some special IOs/Muxing registers like test, emulation, GEMAC Switch (When under reset isolation mode), etc related will not be affected under warm reset conditions.
Note: The Bandgap macros for the LDOs will be reset on PORz only.
Table 8-26. Reset Sources

Cold Reset Sources Warm Reset sources
Characteristic Pin PORz SW Cold Reset EMU Cold Bad Device Pin Warm EMU Warm Watchdog SW Warm Security TRSTz
Reset Reset Reset Timer Reset Violation
Boot pins Y N N N N N N N N N
latched
Resets Y N N N N N N N N N
Standard
Efuses
Resets Y Y Y Y Y Y Y Y Y N
Customer
Efuses
DRAM N N N N Y (1) Y (1) Y (1) Y (1) Y (1) Y
contents
preserved
Resets PLLs (2) Y Y Y Y N N N N N N
Resets Clock Y Y Y Y N N N N N N
Dividers (2)
PLLs enter Y Y Y Y Y Y Y Y Y N
bypass mode (2)
Reset source N N N N Y Y Y (3) Y N Y
blockable by
emulation
Resets test and Y Y Y Y N N N N N N
emulation logic
Resets GMAC Y N (4) Y Y N (4) N (4) N (4) N (4) N
switch and
related chip
logic
Resets Chip Y Y Y Y Y Y Y Y Y N
Functional
Logic (5) (6)
Puts IOs in Tri- Y Y Y Y Y Y Y Y Y N
state
Resets Pinmux Y Y Y (7) Y (7) Y (7) Y (7) Y (7) Y (7) Y (7) N
Registers
(1)
The ROM software does not utilize this feature of DRAM content preservation. Hence, the AM335x re-boots like a cold boot for warm reset as well.
(2)
CORE PLL is an exception when EMAC switch reset isolation is enabled
(3)
Watchdog0 (secure watchdog) reset is not block-able by emulation
(4)
Only true if GMAC switch reset isolation is enabled in control registers, otherwise will be reset.
(5)
There are exception details in control module & PRCM registers which are captured in the register specifications in Chapter 8 and Chapter 9. This includes some pinmux registers which
are warm reset in-sensitive.
(6)
Exception details for debugss logic are captured in debugss specification.
(7)
Some special IOs/Muxing registers like test, emulation, GEMAC Switch (When under reset isolation mode), etc related will not be affected under warm reset conditions.
Table 8-26. Reset Sources (continued)

(7)
Reset out Y Y Y Y (7) Y (7) Y (7) Y (7) Y (7) Y (7) N
Assertion
(nRESETIN_O
UT Pin)
Resets RTC N N N N N N N N N N
8.1.7.6 EMAC Switch Reset Isolation

The device will support reset isolation for the Ethernet Switch IP. This allows the device to undergo a
warm reset without disrupting the switch or traffic being routed through the switch during the reset
condition.
If configured by registers in control module that EMAC reset isolation is active, then behavior is as follows:
Any “Warm” reset source(except the software warm reset) will be blocked to the EMAC switch logic in the
IP (the IP has two reset inputs to support such isolation) and to PLL (and it’s control bits) which is
sourcing the EMAC switch clocks as required by the IP (50- or 125-MHz reference clocks). Also, the
EMAC switch related IO pins must retain their pin muxing and not glitch (continuously controlled by the
EMAC switch IP) by blocking reset to the controlling register bits.
If configured by registers in control module that EMAC reset isolation is NOT active (default state), then
the warm reset sources are allowed to propagate as normal including to the EMAC Switch IP (both reset
inputs to the IP).
All cold or POR resets will always propagate to the EMAC switch IP as normal (as otherwise defined in
this document).
8.1.7.7 Reset Priority

If more than one of these reset sources are asserted simultaneously then the following priority order
should be used:
1. POR
2. TRSTz
3. External warm reset
4. Emulation
5. Reset requestors
6. Software resets
8.1.7.8 Trace Functionality Across Reset

Other than POR, TRSTz and SW cold reset, none of the other resets will affect trace functionality. This
requires that Debug_SS has required reset isolation for the trace logic. Also the Ios and muxing control (if
any) for trace Ios should not get affected by any other reset. Since none of the PLLs getting reset with
other resets, clocks will be any way stable.
8.1.7.9 RTC PORz

AM335x supports RTC only mode by supplying dedicated power to RTC module. The RTC module has a
dedicated PORz signal (RTC_PORz) to reset RTC logic and circuitry during powerup. RTC_PORz is
expected to be driven low when the RTC power supply is ramping up. After the power supply reaches its
stable value, the RTC_PORz can be de-asserted. The RTC module is not affected by the device PORz.
Similarly RTC_PORz does not affect the device reset.
For power-up sequencing with respect to RTC_PORz, see the device specific datasheet.
8.1.8 Power-Up/Down Sequence

Each power domain has dedicated warm and cold reset.
Warm reset gets asserted each time there is any warm reset source requesting reset. Warm reset is also
asserted when power domain moves from ON to OFF state.
Cold reset for the domain is asserted in response to cold reset sources. When domain moves from OFF to
ON state then also cold reset gets asserted as this is similar to power-up condition for that domain.
8.1.9 IO State
All IOs except for JTAG i/f and Reset output (and any special cases mentioned in pinlist) should have their
output drivers tri-state and internal pulls enabled during assertion of all reset sources. JTAG i/f IO is
affected only by TRSTz.
Note: The PRUs and Cortex M3 processor are held under reset after global warm reset by assertion of
software source of reset. Other domains are held under reset after global warm reset until the MPU
software enables their respective interface clock.
8.1.10 Voltage and Power Domains

The following table shows how the device core logic is partitioned into two core logic voltage domains and
four power domains. The table lists which voltage and power domain a functional module belongs.
Table 8-27. Core Logic Voltage and Power Domains

Logic Voltage Domain Name Module
CORE All Core Modules
RTC RTC
8.1.10.1 Voltage Domains

The core logic is divided into two voltage domains: VDD_CORE and VDD_RTC.
8.1.10.2 Power Domains

In order to reduce power due to leakage, the core logic supply voltage to 4 of these power domains can
be turned OFF with internal power switches. The internal power switches are controlled through memory
mapped registers in Control Module.
In a use case whereby all the modules within a power domain are not used that power domain can be
placed in the OFF state.
Error: Reference source not found shows the allowable combination power domain ON/OFF states and
which power domains are switched via internal power switches. At power-on-reset, all domains except
always-on will be in the power domain OFF state.
Table 8-28. Power Domain State Table

POWER DOMAIN
MODE WAKEUP MPU GFX PER RTC EFUSE
No Voltage
N/A N/A N/A N/A N/A N/A
Supply
Power On Reset ON OFF OFF OFF OFF OFF
ALL OTHER
FUNCTIONAL ON DON’T CARE DON’T CARE DON’T CARE DON’T CARE DON'T CARE
MODES
Internal Power
NO YES YES YES YES YES
Switch
8.1.11 Device Modules and Power Management Attributes List
Table 8-29. Power Domain of Various Modules

Power Supply Power Domain Modules OR Supply Destinations
(sinks)
Wake-Cortex M3 Subsystem
L4_WKUP peripherals
PRCM
Control Module
GPIO0
DMTIMER0_dmc
DMTIMER1
UART0
I2C0
TSC
WDT0
WDT1
VDD_CORE PD_WKUP SmartReflex_c2_0
This is non-switchable and cannot be shut
SmartReflex_c2_1
OFF
L4_WKUP
Top level: Pinmux gates/logic,
oscillator wake logic
DDR PHY (DIDs)
WKUP_DFTSS
Debugs
Digital section (VDD) of CORE PLL, PER
PLL, Display PLL and DDR PLL
Emulation sections of MPU
VDD of all IOs including crystal oscillators
RC Oscillator
Table 8-29. Power Domain of Various Modules (continued)

Power Supply Power Domain Modules OR Supply Destinations
(sinks)
Infrastructure
L3
L4_PER, L4_Fast
EMIF4
EDMA
GPMC
OCMC controller
L3 / L4_PER / L4_Fast Peripherals
PRU-ICSS
LCD controller
Ethernet Switch
USB Controller
VDD_CORE PD_PER GPMC
MMC0-2
DMTIMER2-7
UART1-5
SPI0, 1
I2C1, 2
DCAN0, 1
McASP0, 1
ePWM0-2
eCAP0-2
eQEP0,1
GPIO1-3
ELM
AES0, 1, SHA, PKA, RNG
Mailbox0, Spinlock
OCP_WP
Others
USB2PHYCORE (VDD/digital section)
USB2PHYCM (VDD/digital section)
PD_GFX SGX530
PD_MPU CPU, L1, L2 of MPU
VDD_MPU Interrupt controller of MPU Subsystem
PD_WKUP
Digital Portion (VDD) of MPU PLL
1. RTC
VDD_RTC PD_RTC VDD for 32 768 Hz Crystal Osc
VDD for IO for the alarm pin
8.1.11.1 Power Domain Power Down Sequence

The following sequence of steps happen during the power down of a power domain
All IPs (belonging to a power domain) with STANDBY interface will assert STANDBY. STANDBY assertion
should get triggered by IP based on its activity on OCP initiator port. IP should assert STANDBY
whenever initiator port is IDLE. Some of the IPs may not have this feature and they will require SW write
to standby-mode register to get STANDBY assertion from IP.
1. SW will request all modules in given power domain to go to disable state by programming module
control register inside PRCM.
2. PRCM will start and wait for completion of power management handshake with IPs (IdleReq/IdleAck).
3. PRCM will gate-off all the clocks to the power domain.
4. SW will request all clock domains in given power domain to go to “force sleep” mode by programming
functional clock domain register in PRCM. Note that PRCM has already gated-off clocks and this
register programming may look redundant.
5. SW will request PRCM to take this power domain to OFF state by programming PWRSTCTRL register.
Note that this step can be skipped if PWRSTCTRL is permanently programmed to OFF state. When
this is done, functional clock domain register decides when power domain will be taken to OFF state.
Only reason not to have OFF state in PWRSTCTRL is to take power domain to just clock gate state
without power gating.
6. PSCON specific to this power domain will assert isolation enable for the domain.
7. PRCM will assert warm and cold reset to the power domain.
8. PSCON will assert control signals to switch-off power using on-die switches.
9. On-die switches will send acknowledge back to PSCON.
8.1.11.2 Power Domain Power-Up Sequence

The following sequence of steps occurs during power-up of a power domain. This sequence is not
relevant to always-on domain as this domain will never go to OFF state as long as the device is powered.
This sequence will be repeated each time a domain is taken to ON state from OFF (including first time
power-up). Note that some of the details are intentionally taken out here to simplify things.
There can be multiple reasons to start power-up sequence for a domain. For example it can be due to an
interrupt from one of the IPs which is powered-up.
1. SW will request required clock domains inside this power domain to go to force wake-up state by
programming functional clock domain register.
2. PRCM will enable clocks to the required clock domains.
3. PSCON specific to this power domain will assert control signal to un-gate the power.
4. Once power is un-gated, on die switches will send acknowledge back to PSCON.
5. PRCM will de-assert cold and warm reset to the power domain.
6. PRCM will turn-off isolation cells.
7. SW will request PRCM to enable required module in the power domain by programming module
control register.
8. PRCM will initiate and wait for completion of PM protocol to enable the modules (IdleReq/IdleAck).
8.1.12 Clock Module Registers
8.1.12.1 CM_PER Registers

Table 8-30 lists the memory-mapped registers for the CM_PER. All register offset addresses not listed in
Table 8-30. CM_PER REGISTERS

0h CM_PER_L4LS_CLKSTCTRL Section 8.1.12.1.1
4h CM_PER_L3S_CLKSTCTRL Section 8.1.12.1.2
Ch CM_PER_L3_CLKSTCTRL Section 8.1.12.1.3
14h CM_PER_CPGMAC0_CLKCTRL Section 8.1.12.1.4
18h CM_PER_LCDC_CLKCTRL Section 8.1.12.1.5
1Ch CM_PER_USB0_CLKCTRL Section 8.1.12.1.6
24h CM_PER_TPTC0_CLKCTRL Section 8.1.12.1.7
28h CM_PER_EMIF_CLKCTRL Section 8.1.12.1.8
2Ch CM_PER_OCMCRAM_CLKCTRL Section 8.1.12.1.9
30h CM_PER_GPMC_CLKCTRL Section 8.1.12.1.10
34h CM_PER_MCASP0_CLKCTRL Section 8.1.12.1.11
38h CM_PER_UART5_CLKCTRL Section 8.1.12.1.12
3Ch CM_PER_MMC0_CLKCTRL Section 8.1.12.1.13
40h CM_PER_ELM_CLKCTRL Section 8.1.12.1.14
44h CM_PER_I2C2_CLKCTRL Section 8.1.12.1.15
48h CM_PER_I2C1_CLKCTRL Section 8.1.12.1.16
4Ch CM_PER_SPI0_CLKCTRL Section 8.1.12.1.17
50h CM_PER_SPI1_CLKCTRL Section 8.1.12.1.18
60h CM_PER_L4LS_CLKCTRL Section 8.1.12.1.19
68h CM_PER_MCASP1_CLKCTRL Section 8.1.12.1.20
6Ch CM_PER_UART1_CLKCTRL Section 8.1.12.1.21
7Ch CM_PER_TIMER7_CLKCTRL Section 8.1.12.1.25
80h CM_PER_TIMER2_CLKCTRL Section 8.1.12.1.26
ACh CM_PER_GPIO1_CLKCTRL Section 8.1.12.1.29
B0h CM_PER_GPIO2_CLKCTRL Section 8.1.12.1.30
B4h CM_PER_GPIO3_CLKCTRL Section 8.1.12.1.31
BCh CM_PER_TPCC_CLKCTRL Section 8.1.12.1.32
C0h CM_PER_DCAN0_CLKCTRL Section 8.1.12.1.33
C4h CM_PER_DCAN1_CLKCTRL Section 8.1.12.1.34
CCh CM_PER_EPWMSS1_CLKCTRL Section 8.1.12.1.35
D4h CM_PER_EPWMSS0_CLKCTRL Section 8.1.12.1.36
D8h CM_PER_EPWMSS2_CLKCTRL Section 8.1.12.1.37
DCh CM_PER_L3_INSTR_CLKCTRL Section 8.1.12.1.38
E0h CM_PER_L3_CLKCTRL Section 8.1.12.1.39
E4h CM_PER_IEEE5000_CLKCTRL Section 8.1.12.1.40
E8h CM_PER_PRU_ICSS_CLKCTRL Section 8.1.12.1.41
ECh CM_PER_TIMER5_CLKCTRL Section 8.1.12.1.42
Table 8-30. CM_PER REGISTERS (continued)

F0h CM_PER_TIMER6_CLKCTRL Section 8.1.12.1.43
F4h CM_PER_MMC1_CLKCTRL Section 8.1.12.1.44
F8h CM_PER_MMC2_CLKCTRL Section 8.1.12.1.45
FCh CM_PER_TPTC1_CLKCTRL Section 8.1.12.1.46
100h CM_PER_TPTC2_CLKCTRL Section 8.1.12.1.47
10Ch CM_PER_SPINLOCK_CLKCTRL Section 8.1.12.1.48
110h CM_PER_MAILBOX0_CLKCTRL Section 8.1.12.1.49
11Ch CM_PER_L4HS_CLKSTCTRL Section 8.1.12.1.50
120h CM_PER_L4HS_CLKCTRL Section 8.1.12.1.51
12Ch CM_PER_OCPWP_L3_CLKSTCT Section 8.1.12.1.52
RL
130h CM_PER_OCPWP_CLKCTRL Section 8.1.12.1.53
140h CM_PER_PRU_ICSS_CLKSTCTR Section 8.1.12.1.54
L
144h CM_PER_CPSW_CLKSTCTRL Section 8.1.12.1.55
148h CM_PER_LCDC_CLKSTCTRL Section 8.1.12.1.56
14Ch CM_PER_CLKDIV32K_CLKCTRL Section 8.1.12.1.57
150h CM_PER_CLK_24MHZ_CLKSTCT Section 8.1.12.1.58
RL
8.1.12.1.1 CM_PER_L4LS_CLKSTCTRL Register (offset = 0h) [reset = C0102h]

CM_PER_L4LS_CLKSTCTRL is shown in Figure 8-28 and described in Table 8-31.
This register enables the domain power state transition. It controls the SW supervised clock domain state
transition between ON-PER and ON-INPER states. It also hold one status bit per clock input of the
domain.
Figure 8-28. CM_PER_L4LS_CLKSTCTRL Register

31 30 29 28 27 26 25 24
Reserved CLKACTIVITY_ CLKACTIVITY_ Reserved CLKACTIVITY_ CLKACTIVITY_
TIMER6_GCLK TIMER5_GCLK SPI_GCLK I2C_FCLK
R-0h R-0h R-0h R-0h R-0h R-0h
23 22 21 20 19 18 17 16
Reserved Reserved CLKACTIVITY_ CLKACTIVITY_ CLKACTIVITY_ Reserved CLKACTIVITY_ CLKACTIVITY_
GPIO_3_GDBC GPIO_2_GDBC GPIO_1_GDBC LCDC_GCLK TIMER4_GCLK
LK LK LK
15 14 13 12 11 10 9 8
CLKACTIVITY_ CLKACTIVITY_ CLKACTIVITY_ Reserved CLKACTIVITY_ CLKACTIVITY_ Reserved CLKACTIVITY_
TIMER3_GCLK TIMER2_GCLK TIMER7_GCLK CAN_CLK UART_GFCLK L4LS_GCLK
7 6 5 4 3 2 1 0
Reserved CLKTRCTRL
R-0h R/W-2h
Table 8-31. CM_PER_L4LS_CLKSTCTRL Register Field Descriptions

31-29 Reserved R 0h
28 CLKACTIVITY_TIMER6_ R 0h This field indicates the state of the TIMER6 CLKTIMER clock in the
GCLK domain.
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
GCLK domain.
26 Reserved R 0h Reserved.
25 CLKACTIVITY_SPI_GCL R 0h This field indicates the state of the SPI_GCLK clock in the domain.
K
24 CLKACTIVITY_I2C_FCLK R 0h This field indicates the state of the I2C _FCLK clock in the domain.
23 Reserved R 0h
21 CLKACTIVITY_GPIO_3_ R 0h This field indicates the state of the GPIO3_GDBCLK clock in the
GDBCLK domain.
Table 8-31. CM_PER_L4LS_CLKSTCTRL Register Field Descriptions (continued)

20 CLKACTIVITY_GPIO_2_ R 0h This field indicates the state of the GPIO2_ GDBCLK clock in the
GDBCLK domain.
19 CLKACTIVITY_GPIO_1_ R 1h This field indicates the state of the GPIO1_GDBCLK clock in the
GDBCLK domain.
17 CLKACTIVITY_LCDC_GC R 0h This field indicates the state of the LCD clock in the domain.
LK
GCLK domain.
GCLK domain.
GCLK domain.
GCLK domain.
12 Reserved R 0h
11 CLKACTIVITY_CAN_CLK R 0h This field indicates the state of the CAN_CLK clock in the domain.
10 CLKACTIVITY_UART_GF R 0h This field indicates the state of the UART_GFCLK clock in the
CLK domain.
9 Reserved R 0h
8 CLKACTIVITY_L4LS_GC R 1h This field indicates the state of the L4LS_GCLK clock in the domain.
LK
7-2 Reserved R 0h
1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the L4 SLOW clock domain in
PER power domain.
0x0 = NO_SLEEP : NO_SLEEP: Sleep transition cannot be initiated.
0x1 = SW_SLEEP : SW_SLEEP: Start a software forced sleep
transition on the domain.
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up
0x3 = Reserved : Reserved.
8.1.12.1.2 CM_PER_L3S_CLKSTCTRL Register (offset = 4h) [reset = Ah]

CM_PER_L3S_CLKSTCTRL is shown in Figure 8-29 and described in Table 8-32.
transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the
domain.
Figure 8-29. CM_PER_L3S_CLKSTCTRL Register

31 30 29 28 27 26 25 24
Reserved Reserved
R-0h R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved Reserved Reserved Reserved
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
Reserved Reserved CLKACTIVITY_ Reserved CLKTRCTRL
L3S_GCLK
R-0h R-0h R-1h R-0h R/W-2h
Table 8-32. CM_PER_L3S_CLKSTCTRL Register Field Descriptions

31-26 Reserved R 0h
25-11 Reserved R 0h
10 Reserved R 0h
9 Reserved R 0h
8 Reserved R 0h
7-5 Reserved R 0h
4 Reserved R 0h
3 CLKACTIVITY_L3S_GCL R 1h This field indicates the state of the L3S_GCLK clock in the domain.
K
0x0 = Inact
0x1 = Act
2 Reserved R 0h
1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the L3 Slow clock domain.
8.1.12.1.3 CM_PER_L3_CLKSTCTRL Register (offset = Ch) [reset = 12h]

CM_PER_L3_CLKSTCTRL is shown in Figure 8-30 and described in Table 8-33.
domain.
Figure 8-30. CM_PER_L3_CLKSTCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
CLKACTIVITY_ CLKACTIVITY_ Reserved CLKACTIVITY_ CLKACTIVITY_ CLKACTIVITY_ CLKTRCTRL
MCASP_GCLK CPTS_RFT_G L3_GCLK MMC_FCLK EMIF_GCLK
CLK
R-0h R-0h R-0h R-1h R-0h R-0h R/W-2h
Table 8-33. CM_PER_L3_CLKSTCTRL Register Field Descriptions

31-8 Reserved R 0h
7 CLKACTIVITY_MCASP_ R 0h This field indicates the state of the MCASP_GCLK clock in the
GCLK domain.
0x0 = Inact
0x1 = Act
6 CLKACTIVITY_CPTS_RF R 0h This field indicates the state of the
T_GCLK CLKACTIVITY_CPTS_RFT_GCLK clock in the domain.
0x0 = Inact
0x1 = Act
5 Reserved R 0h
4 CLKACTIVITY_L3_GCLK R 1h This field indicates the state of the L3_GCLK clock in the domain.
0x0 = Inact
0x1 = Act
3 CLKACTIVITY_MMC_FCL R 0h This field indicates the state of the MMC_GCLK clock in the domain.
K
0x0 = Inact
0x1 = Act
2 CLKACTIVITY_EMIF_GC R 0h This field indicates the state of the EMIF_GCLK clock in the domain.
LK
0x0 = Inact
0x1 = Act
1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the L3 clock domain.
8.1.12.1.4 CM_PER_CPGMAC0_CLKCTRL Register (offset = 14h) [reset = 70000h]

CM_PER_CPGMAC0_CLKCTRL is shown in Figure 8-31 and described in Table 8-34.
This register manages the CPSW clocks.
Figure 8-31. CM_PER_CPGMAC0_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved STBYST IDLEST
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-34. CM_PER_CPGMAC0_CLKCTRL Register Field Descriptions

31-19 Reserved R 0h
18 STBYST R 1h Module standby status.
This bit is warm reset insensitive when CPSW RESET_ISO is
enabled
0x0 = Func : Module is functional (not in standby)
0x1 = Standby : Module is in standby
17-16 IDLEST R 3h Module idle status.
enabled
0x0 = Func : Module is fully functional, including OCP
0x1 = Trans : Module is performing transition: wakeup, or sleep, or
sleep abortion
0x2 = Idle : Module is in Idle mode (only OCP part). It is functional if
using separate functional clock
0x3 = Disable : Module is disabled and cannot be accessed
15-2 Reserved R 0h
1-0 MODULEMODE R/W 0h Control the way mandatory clocks are managed.
enabled
0x0 = DISABLED : Module is disable by SW. Any OCP access to
module results in an error, except if resulting from a module wakeup
(asynchronous wakeup).
0x1 = RESERVED_1 : Reserved
0x2 = ENABLE : Module is explicitly enabled. Interface clock (if not
used for functions) may be gated according to the clock domain
state. Functional clocks are guarantied to stay present. As long as in
this configuration, power domain sleep transition cannot happen.
0x3 = RESERVED : Reserved
8.1.12.1.5 CM_PER_LCDC_CLKCTRL Register (offset = 18h) [reset = 70000h]

CM_PER_LCDC_CLKCTRL is shown in Figure 8-32 and described in Table 8-35.
This register manages the LCD clocks.
Figure 8-32. CM_PER_LCDC_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-35. CM_PER_LCDC_CLKCTRL Register Field Descriptions

31-19 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.6 CM_PER_USB0_CLKCTRL Register (offset = 1Ch) [reset = 70000h]

CM_PER_USB0_CLKCTRL is shown in Figure 8-33 and described in Table 8-36.
This register manages the USB clocks.
Figure 8-33. CM_PER_USB0_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-36. CM_PER_USB0_CLKCTRL Register Field Descriptions

31-19 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.7 CM_PER_TPTC0_CLKCTRL Register (offset = 24h) [reset = 70000h]

CM_PER_TPTC0_CLKCTRL is shown in Figure 8-34 and described in Table 8-37.
This register manages the TPTC clocks.
Figure 8-34. CM_PER_TPTC0_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-37. CM_PER_TPTC0_CLKCTRL Register Field Descriptions

31-19 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.8 CM_PER_EMIF_CLKCTRL Register (offset = 28h) [reset = 30000h]

CM_PER_EMIF_CLKCTRL is shown in Figure 8-35 and described in Table 8-38.
This register manages the EMIF clocks.
Figure 8-35. CM_PER_EMIF_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-38. CM_PER_EMIF_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.9 CM_PER_OCMCRAM_CLKCTRL Register (offset = 2Ch) [reset = 30000h]

CM_PER_OCMCRAM_CLKCTRL is shown in Figure 8-36 and described in Table 8-39.
This register manages the OCMC clocks.
Figure 8-36. CM_PER_OCMCRAM_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-39. CM_PER_OCMCRAM_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.10 CM_PER_GPMC_CLKCTRL Register (offset = 30h) [reset = 30002h]

CM_PER_GPMC_CLKCTRL is shown in Figure 8-37 and described in Table 8-40.
This register manages the GPMC clocks.
Figure 8-37. CM_PER_GPMC_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
Table 8-40. CM_PER_GPMC_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.11 CM_PER_MCASP0_CLKCTRL Register (offset = 34h) [reset = 30000h]

CM_PER_MCASP0_CLKCTRL is shown in Figure 8-38 and described in Table 8-41.
This register manages the MCASP0 clocks.
Figure 8-38. CM_PER_MCASP0_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-41. CM_PER_MCASP0_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.12 CM_PER_UART5_CLKCTRL Register (offset = 38h) [reset = 30000h]

CM_PER_UART5_CLKCTRL is shown in Figure 8-39 and described in Table 8-42.
This register manages the UART5 clocks.
Figure 8-39. CM_PER_UART5_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-42. CM_PER_UART5_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.13 CM_PER_MMC0_CLKCTRL Register (offset = 3Ch) [reset = 30000h]

CM_PER_MMC0_CLKCTRL is shown in Figure 8-40 and described in Table 8-43.
This register manages the MMC0 clocks.
Figure 8-40. CM_PER_MMC0_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved Reserved IDLEST
R-0h R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-43. CM_PER_MMC0_CLKCTRL Register Field Descriptions

31-19 Reserved R 0h
18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.14 CM_PER_ELM_CLKCTRL Register (offset = 40h) [reset = 30000h]

CM_PER_ELM_CLKCTRL is shown in Figure 8-41 and described in Table 8-44.
This register manages the ELM clocks.
Figure 8-41. CM_PER_ELM_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-44. CM_PER_ELM_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.15 CM_PER_I2C2_CLKCTRL Register (offset = 44h) [reset = 30000h]

CM_PER_I2C2_CLKCTRL is shown in Figure 8-42 and described in Table 8-45.
This register manages the I2C2 clocks.
Figure 8-42. CM_PER_I2C2_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-45. CM_PER_I2C2_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.16 CM_PER_I2C1_CLKCTRL Register (offset = 48h) [reset = 30000h]

CM_PER_I2C1_CLKCTRL is shown in Figure 8-43 and described in Table 8-46.
Figure 8-43. CM_PER_I2C1_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-46. CM_PER_I2C1_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.17 CM_PER_SPI0_CLKCTRL Register (offset = 4Ch) [reset = 30000h]

CM_PER_SPI0_CLKCTRL is shown in Figure 8-44 and described in Table 8-47.
This register manages the SPI0 clocks.
Figure 8-44. CM_PER_SPI0_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-47. CM_PER_SPI0_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.18 CM_PER_SPI1_CLKCTRL Register (offset = 50h) [reset = 30000h]

CM_PER_SPI1_CLKCTRL is shown in Figure 8-45 and described in Table 8-48.
This register manages the SPI1 clocks.
Figure 8-45. CM_PER_SPI1_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-48. CM_PER_SPI1_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.19 CM_PER_L4LS_CLKCTRL Register (offset = 60h) [reset = 2h]

CM_PER_L4LS_CLKCTRL is shown in Figure 8-46 and described in Table 8-49.
This register manages the L4LS clocks.
Figure 8-46. CM_PER_L4LS_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
Table 8-49. CM_PER_L4LS_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.20 CM_PER_MCASP1_CLKCTRL Register (offset = 68h) [reset = 30000h]

CM_PER_MCASP1_CLKCTRL is shown in Figure 8-47 and described in Table 8-50.
This register manages the MCASP1 clocks.
Figure 8-47. CM_PER_MCASP1_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-50. CM_PER_MCASP1_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.21 CM_PER_UART1_CLKCTRL Register (offset = 6Ch) [reset = 30000h]


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.25 CM_PER_TIMER7_CLKCTRL Register (offset = 7Ch) [reset = 30000h]

CM_PER_TIMER7_CLKCTRL is shown in Figure 8-52 and described in Table 8-55.
This register manages the TIMER7 clocks.
Figure 8-52. CM_PER_TIMER7_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-55. CM_PER_TIMER7_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.26 CM_PER_TIMER2_CLKCTRL Register (offset = 80h) [reset = 30000h]


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.29 CM_PER_GPIO1_CLKCTRL Register (offset = ACh) [reset = 30000h]

CM_PER_GPIO1_CLKCTRL is shown in Figure 8-56 and described in Table 8-59.
This register manages the GPIO1 clocks.
Figure 8-56. CM_PER_GPIO1_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved OPTFCLKEN_ IDLEST
GPIO_1_GDBC
LK
R-0h R/W-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-59. CM_PER_GPIO1_CLKCTRL Register Field Descriptions

31-19 Reserved R 0h
18 OPTFCLKEN_GPIO_1_G R/W 0h Optional functional clock control.
DBCLK
0x0 = FCLK_DIS : Optional functional clock is disabled
0x1 = FCLK_EN : Optional functional clock is enabled
sleep abortion
15-2 Reserved R 0h
state. Functional clocks are guaranteed to stay present. As long as
in this configuration, power domain sleep transition cannot happen.
8.1.12.1.30 CM_PER_GPIO2_CLKCTRL Register (offset = B0h) [reset = 30000h]


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
GPIO_2_GDBC
LK
R-0h R/W-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h

31-19 Reserved R 0h
DBCLK
sleep abortion
15-2 Reserved R 0h
8.1.12.1.31 CM_PER_GPIO3_CLKCTRL Register (offset = B4h) [reset = 30000h]


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
GPIO_3_GDBC
LK
R-0h R/W-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h

31-19 Reserved R 0h
DBCLK
sleep abortion
15-2 Reserved R 0h
8.1.12.1.32 CM_PER_TPCC_CLKCTRL Register (offset = BCh) [reset = 30000h]

CM_PER_TPCC_CLKCTRL is shown in Figure 8-59 and described in Table 8-62.
This register manages the TPCC clocks.
Figure 8-59. CM_PER_TPCC_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-62. CM_PER_TPCC_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.33 CM_PER_DCAN0_CLKCTRL Register (offset = C0h) [reset = 30000h]

CM_PER_DCAN0_CLKCTRL is shown in Figure 8-60 and described in Table 8-63.
This register manages the DCAN0 clocks.
Figure 8-60. CM_PER_DCAN0_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
R-0h R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-63. CM_PER_DCAN0_CLKCTRL Register Field Descriptions

31-19 Reserved R 0h
18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.34 CM_PER_DCAN1_CLKCTRL Register (offset = C4h) [reset = 30000h]

CM_PER_DCAN1_CLKCTRL is shown in Figure 8-61 and described in Table 8-64.
This register manages the DCAN1 clocks.
Figure 8-61. CM_PER_DCAN1_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
R-0h R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-64. CM_PER_DCAN1_CLKCTRL Register Field Descriptions

31-19 Reserved R 0h
18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.35 CM_PER_EPWMSS1_CLKCTRL Register (offset = CCh) [reset = 30000h]

CM_PER_EPWMSS1_CLKCTRL is shown in Figure 8-62 and described in Table 8-65.
This register manages the PWMSS1 clocks.
Figure 8-62. CM_PER_EPWMSS1_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-65. CM_PER_EPWMSS1_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.36 CM_PER_EPWMSS0_CLKCTRL Register (offset = D4h) [reset = 30000h]


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.37 CM_PER_EPWMSS2_CLKCTRL Register (offset = D8h) [reset = 30000h]


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.38 CM_PER_L3_INSTR_CLKCTRL Register (offset = DCh) [reset = 2h]

CM_PER_L3_INSTR_CLKCTRL is shown in Figure 8-65 and described in Table 8-68.
This register manages the L3 INSTR clocks.
Figure 8-65. CM_PER_L3_INSTR_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
Table 8-68. CM_PER_L3_INSTR_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.39 CM_PER_L3_CLKCTRL Register (offset = E0h) [reset = 2h]

CM_PER_L3_CLKCTRL is shown in Figure 8-66 and described in Table 8-69.
This register manages the L3 Interconnect clocks.
Figure 8-66. CM_PER_L3_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
Table 8-69. CM_PER_L3_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.40 CM_PER_IEEE5000_CLKCTRL Register (offset = E4h) [reset = 70002h]

CM_PER_IEEE5000_CLKCTRL is shown in Figure 8-67 and described in Table 8-70.
This register manages the IEEE1500 clocks.
Figure 8-67. CM_PER_IEEE5000_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
Table 8-70. CM_PER_IEEE5000_CLKCTRL Register Field Descriptions

31-19 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.41 CM_PER_PRU_ICSS_CLKCTRL Register (offset = E8h) [reset = 70000h]

CM_PER_PRU_ICSS_CLKCTRL is shown in Figure 8-68 and described in Table 8-71.
This register manages the PRU-ICSS clocks.
Figure 8-68. CM_PER_PRU_ICSS_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-71. CM_PER_PRU_ICSS_CLKCTRL Register Field Descriptions

31-19 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.42 CM_PER_TIMER5_CLKCTRL Register (offset = ECh) [reset = 30000h]


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.43 CM_PER_TIMER6_CLKCTRL Register (offset = F0h) [reset = 30000h]


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.44 CM_PER_MMC1_CLKCTRL Register (offset = F4h) [reset = 30000h]


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
R-0h R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h

31-19 Reserved R 0h
18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.45 CM_PER_MMC2_CLKCTRL Register (offset = F8h) [reset = 30000h]


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
R-0h R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h

31-19 Reserved R 0h
18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.46 CM_PER_TPTC1_CLKCTRL Register (offset = FCh) [reset = 70000h]

This register manages the TPTC1 clocks.

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h

31-19 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.47 CM_PER_TPTC2_CLKCTRL Register (offset = 100h) [reset = 70000h]

This register manages the TPTC2 clocks.

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h

31-19 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.48 CM_PER_SPINLOCK_CLKCTRL Register (offset = 10Ch) [reset = 30000h]

CM_PER_SPINLOCK_CLKCTRL is shown in Figure 8-75 and described in Table 8-78.
This register manages the SPINLOCK clocks.
Figure 8-75. CM_PER_SPINLOCK_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-78. CM_PER_SPINLOCK_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.49 CM_PER_MAILBOX0_CLKCTRL Register (offset = 110h) [reset = 30000h]

CM_PER_MAILBOX0_CLKCTRL is shown in Figure 8-76 and described in Table 8-79.
This register manages the MAILBOX0 clocks.
Figure 8-76. CM_PER_MAILBOX0_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-79. CM_PER_MAILBOX0_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.50 CM_PER_L4HS_CLKSTCTRL Register (offset = 11Ch) [reset = 7Ah]

CM_PER_L4HS_CLKSTCTRL is shown in Figure 8-77 and described in Table 8-80.
domain.
Figure 8-77. CM_PER_L4HS_CLKSTCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKACTIVITY_ CLKACTIVITY_ CLKACTIVITY_ CLKACTIVITY_ Reserved CLKTRCTRL
CPSW_5MHZ_ CPSW_50MHZ CPSW_250MH L4HS_GCLK
GCLK _GCLK Z_GCLK
R-0h R-1h R-1h R-1h R-1h R-0h R/W-2h
Table 8-80. CM_PER_L4HS_CLKSTCTRL Register Field Descriptions

31-7 Reserved R 0h
6 CLKACTIVITY_CPSW_5 R 1h This field indicates the state of the CPSW_5MHZ_GCLK clock in the
MHZ_GCLK domain.
0x0 = Inact
0x1 = Act
5 CLKACTIVITY_CPSW_50 R 1h This field indicates the state of the CPSW_50MHZ_GCLK clock in
MHZ_GCLK the domain.
0x0 = Inact
0x1 = Act
4 CLKACTIVITY_CPSW_25 R 1h This field indicates the state of the CPSW_250MHZ_GCLK clock in
0MHZ_GCLK the domain.
0x0 = Inact
0x1 = Act
3 CLKACTIVITY_L4HS_GC R 1h This field indicates the state of the L4HS_GCLK clock in the domain.
LK
0x0 = Inact
0x1 = Act
2 Reserved R 0h
1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the L4 Fast clock domain.
8.1.12.1.51 CM_PER_L4HS_CLKCTRL Register (offset = 120h) [reset = 2h]

CM_PER_L4HS_CLKCTRL is shown in Figure 8-78 and described in Table 8-81.
This register manages the L4 Fast clocks.
Figure 8-78. CM_PER_L4HS_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
Table 8-81. CM_PER_L4HS_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.52 CM_PER_OCPWP_L3_CLKSTCTRL Register (offset = 12Ch) [reset = 2h]

CM_PER_OCPWP_L3_CLKSTCTRL is shown in Figure 8-79 and described in Table 8-82.
domain.
Figure 8-79. CM_PER_OCPWP_L3_CLKSTCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKACTIVITY_ CLKACTIVITY_ Reserved CLKTRCTRL
OCPWP_L4_G OCPWP_L3_G
CLK CLK
Table 8-82. CM_PER_OCPWP_L3_CLKSTCTRL Register Field Descriptions

31-6 Reserved R 0h
5 CLKACTIVITY_OCPWP_ R 0h This field indicates the state of the OCPWP L4 clock in the domain.
L4_GCLK
0x0 = Inact
0x1 = Act
4 CLKACTIVITY_OCPWP_ R 0h This field indicates the state of the OCPWP L3 clock in the domain.
L3_GCLK
0x0 = Inact
0x1 = Act
3-2 Reserved R 0h
1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the OCPWP clock domain.
8.1.12.1.53 CM_PER_OCPWP_CLKCTRL Register (offset = 130h) [reset = 70002h]

CM_PER_OCPWP_CLKCTRL is shown in Figure 8-80 and described in Table 8-83.
This register manages the OCPWP clocks.
Figure 8-80. CM_PER_OCPWP_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
Table 8-83. CM_PER_OCPWP_CLKCTRL Register Field Descriptions

31-19 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.54 CM_PER_PRU_ICSS_CLKSTCTRL Register (offset = 140h) [reset = 2h]

CM_PER_PRU_ICSS_CLKSTCTRL is shown in Figure 8-81 and described in Table 8-84.
This register enables the clock domain state transition. It controls the SW supervised clock domain state
domain.
Figure 8-81. CM_PER_PRU_ICSS_CLKSTCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKACTIVITY_ CLKACTIVITY_ CLKACTIVITY_ Reserved CLKTRCTRL
PRU_ICSS_UA PRU_ICSS_IE PRU_ICSS_OC
RT_GCLK P_GCLK P_GCLK
R-0h R-0h R-0h R-0h R-0h R/W-2h
Table 8-84. CM_PER_PRU_ICSS_CLKSTCTRL Register Field Descriptions

31-7 Reserved R 0h
6 CLKACTIVITY_PRU_ICS R 0h This field indicates the state of the PRU-ICSS UART clock in the
S_UART_GCLK domain.
0x0 = Inact
0x1 = Act
5 CLKACTIVITY_PRU_ICS R 0h This field indicates the state of the PRU-ICSS IEP clock in the
S_IEP_GCLK domain.
0x0 = Inact
0x1 = Act
4 CLKACTIVITY_PRU_ICS R 0h This field indicates the state of the PRU-ICSS OCP clock in the
S_OCP_GCLK domain.
0x0 = Inact
0x1 = Act
3-2 Reserved R 0h
1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the PRU-ICSS OCP clock
domain.
8.1.12.1.55 CM_PER_CPSW_CLKSTCTRL Register (offset = 144h) [reset = 2h]

CM_PER_CPSW_CLKSTCTRL is shown in Figure 8-82 and described in Table 8-85.
domain.
Figure 8-82. CM_PER_CPSW_CLKSTCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKACTIVITY_ Reserved CLKTRCTRL
CPSW_125MH
z_GCLK
R-0h R-0h R-0h R/W-2h
Table 8-85. CM_PER_CPSW_CLKSTCTRL Register Field Descriptions

31-5 Reserved R 0h
4 CLKACTIVITY_CPSW_12 R 0h This field indicates the state of the CPSW 125 MHz OCP clock in the
5MHz_GCLK domain.
0x0 = Inact
0x1 = Act
3-2 Reserved R 0h
1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the CPSW OCP clock domain.
8.1.12.1.56 CM_PER_LCDC_CLKSTCTRL Register (offset = 148h) [reset = 2h]

CM_PER_LCDC_CLKSTCTRL is shown in Figure 8-83 and described in Table 8-86.
domain.
Figure 8-83. CM_PER_LCDC_CLKSTCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKACTIVITY_ CLKACTIVITY_ Reserved CLKTRCTRL
LCDC_L4_OCP LCDC_L3_OCP
_GCLK _GCLK
Table 8-86. CM_PER_LCDC_CLKSTCTRL Register Field Descriptions

31-6 Reserved R 0h
5 CLKACTIVITY_LCDC_L4 R 0h This field indicates the state of the LCDC L4 OCP clock in the
_OCP_GCLK domain.
0x0 = Inact
0x1 = Act
4 CLKACTIVITY_LCDC_L3 R 0h This field indicates the state of the LCDC L3 OCP clock in the
_OCP_GCLK domain.
0x0 = Inact
0x1 = Act
3-2 Reserved R 0h
1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the LCDC OCP clock domain.
8.1.12.1.57 CM_PER_CLKDIV32K_CLKCTRL Register (offset = 14Ch) [reset = 30000h]

CM_PER_CLKDIV32K_CLKCTRL is shown in Figure 8-84 and described in Table 8-87.
This register manages the CLKDIV32K clocks.
Figure 8-84. CM_PER_CLKDIV32K_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-87. CM_PER_CLKDIV32K_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.1.58 CM_PER_CLK_24MHZ_CLKSTCTRL Register (offset = 150h) [reset = 2h]

CM_PER_CLK_24MHZ_CLKSTCTRL is shown in Figure 8-85 and described in Table 8-88.
domain.
Figure 8-85. CM_PER_CLK_24MHZ_CLKSTCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKACTIVITY_ Reserved CLKTRCTRL
CLK_24MHZ_G
CLK
Table 8-88. CM_PER_CLK_24MHZ_CLKSTCTRL Register Field Descriptions

31-5 Reserved R 0h
4 CLKACTIVITY_CLK_24M R 0h This field indicates the state of the 24MHz clock in the domain.
HZ_GCLK
0x0 = Inact
0x1 = Act
3-2 Reserved R 0h
1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the 24MHz clock domain.
8.1.12.2 CM_WKUP Registers

Table 8-89 lists the memory-mapped registers for the CM_WKUP. All register offset addresses not listed
in Table 8-89 should be considered as reserved locations and the register contents should not be
modified.
Table 8-89. CM_WKUP Registers

0h CM_WKUP_CLKSTCTRL Section 8.1.12.2.1
4h CM_WKUP_CONTROL_CLKCTRL Section 8.1.12.2.2
8h CM_WKUP_GPIO0_CLKCTRL Section 8.1.12.2.3
Ch CM_WKUP_L4WKUP_CLKCTRL Section 8.1.12.2.4
10h CM_WKUP_TIMER0_CLKCTRL Section 8.1.12.2.5
Table 8-89. CM_WKUP Registers (continued)

14h CM_WKUP_DEBUGSS_CLKCTRL Section 8.1.12.2.6
18h CM_L3_AON_CLKSTCTRL Section 8.1.12.2.7
1Ch CM_AUTOIDLE_DPLL_MPU Section 8.1.12.2.8
20h CM_IDLEST_DPLL_MPU Section 8.1.12.2.9
24h CM_SSC_DELTAMSTEP_DPLL_MPU Section
8.1.12.2.10
28h CM-SSC_MODFREQDIV_DPLL_MPU Section
8.1.12.2.11
2Ch CM_CLKSEL_DPLL_MPU Section
8.1.12.2.12
30h CM_AUTOIDLE_DPLL_DDR Section
8.1.12.2.13
34h CM_IDLEST_DPLL_DDR Section
8.1.12.2.14
38h CM_SSC_DELTAMSTEP_DPLL_DDR Section
8.1.12.2.15
3Ch CM_SSC_MODFREQDIV_DPLL_DDR Section
8.1.12.2.16
40h CM_CLKSEL_DPLL_DDR Section
8.1.12.2.17
44h CM_AUTOIDLE_DPLL_DISP Section
8.1.12.2.18
48h CM_IDLEST_DPLL_DISP Section
8.1.12.2.19
4Ch CM_SSC_DELTAMSTEP_DPLL_DISP Section
8.1.12.2.20
50h CM_SSC_MODFREQDIV_DPLL_DISP Section
8.1.12.2.21
54h CM_CLKSEL_DPLL_DISP Section
8.1.12.2.22
58h CM_AUTOIDLE_DPLL_CORE Section
8.1.12.2.23
5Ch CM_IDLEST_DPLL_CORE Section
8.1.12.2.24
60h CM_SSC_DELTAMSTEP_DPLL_CORE Section
8.1.12.2.25
64h CM_SSC_MODFREQDIV_DPLL_CORE Section
8.1.12.2.26
68h CM_CLKSEL_DPLL_CORE Section
8.1.12.2.27
6Ch CM_AUTOIDLE_DPLL_PER Section
8.1.12.2.28
70h CM_IDLEST_DPLL_PER Section
8.1.12.2.29
74h CM_SSC_DELTAMSTEP_DPLL_PER Section
8.1.12.2.30
78h CM_SSC_MODFREQDIV_DPLL_PER Section
8.1.12.2.31
7Ch CM_CLKDCOLDO_DPLL_PER Section
8.1.12.2.32
80h CM_DIV_M4_DPLL_CORE Section
8.1.12.2.33
84h CM_DIV_M5_DPLL_CORE Section
8.1.12.2.34
88h CM_CLKMODE_DPLL_MPU Section
8.1.12.2.35
Table 8-89. CM_WKUP Registers (continued)

8Ch CM_CLKMODE_DPLL_PER Section
8.1.12.2.36
90h CM_CLKMODE_DPLL_CORE Section
8.1.12.2.37
94h CM_CLKMODE_DPLL_DDR Section
8.1.12.2.38
98h CM_CLKMODE_DPLL_DISP Section
8.1.12.2.39
9Ch CM_CLKSEL_DPLL_PERIPH Section
8.1.12.2.40
A0h CM_DIV_M2_DPLL_DDR Section
8.1.12.2.41
A4h CM_DIV_M2_DPLL_DISP Section
8.1.12.2.42
A8h CM_DIV_M2_DPLL_MPU Section
8.1.12.2.43
ACh CM_DIV_M2_DPLL_PER Section
8.1.12.2.44
B0h CM_WKUP_WKUP_M3_CLKCTRL Section
8.1.12.2.45
B4h CM_WKUP_UART0_CLKCTRL Section
8.1.12.2.46
B8h CM_WKUP_I2C0_CLKCTRL Section
8.1.12.2.47
BCh CM_WKUP_ADC_TSC_CLKCTRL Section
8.1.12.2.48
C0h CM_WKUP_SMARTREFLEX0_CLKCT Section
RL 8.1.12.2.49
C4h CM_WKUP_TIMER1_CLKCTRL Section
8.1.12.2.50
C8h CM_WKUP_SMARTREFLEX1_CLKCT Section
RL 8.1.12.2.51
CCh CM_L4_WKUP_AON_CLKSTCTRL Section
8.1.12.2.52
D4h CM_WKUP_WDT1_CLKCTRL Section
8.1.12.2.53
D8h CM_DIV_M6_DPLL_CORE Section
8.1.12.2.54
8.1.12.2.1 CM_WKUP_CLKSTCTRL Register (offset = 0h) [reset = 6h]

CM_WKUP_CLKSTCTRL is shown in Figure 8-86 and described in Table 8-90.
domain.
Figure 8-86. CM_WKUP_CLKSTCTRL Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED CLKACTIVITY_ CLKACTIVITY_ CLKACTIVITY_ CLKACTIVITY_ CLKACTIVITY_ RESERVED CLKACTIVITY_
ADC_FCLK TIMER1_GCLK UART0_GFCL I2C0_GFCLK TIMER0_GCLK GPIO0_GDBCL
K K
Rreturns0s-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED CLKACTIVITY_ CLKACTIVITY_ CLKACTIVITY_ CLKTRCTRL
WDT1_GCLK SR_SYSCLK L4_WKUP_GC
LK
Rreturns0s-0h R-0h R-0h R-1h R/W-2h
Table 8-90. CM_WKUP_CLKSTCTRL Register Field Descriptions

31-15 RESERVED Rreturns0s 0h
14 CLKACTIVITY_ADC_FCL R 0h This field indicates the state of the ADC clock in the domain.
K
0h (R) = Corresponding clock is gated
1h (R) = Corresponding clock is active
13 CLKACTIVITY_TIMER1_ R 0h This field indicates the state of the TIMER1 clock in the domain.
GCLK
12 CLKACTIVITY_UART0_G R 0h This field indicates the state of the UART0 clock in the domain.
FCLK
11 CLKACTIVITY_I2C0_GFC R 0h This field indicates the state of the I2C0 clock in the domain.
LK
10 CLKACTIVITY_TIMER0_ R 0h This field indicates the state of the WKUPTIMER_GCLK clock in the
GCLK domain.
9 RESERVED R 0h
8 CLKACTIVITY_GPIO0_G R 0h This field indicates the state of the WKUPGPIO_DBGICLK clock in
DBCLK the domain.
Table 8-90. CM_WKUP_CLKSTCTRL Register Field Descriptions (continued)

4 CLKACTIVITY_WDT1_G R 0h This field indicates the state of the WDT1_GCLK clock in the
CLK domain.
3 CLKACTIVITY_SR_SYSC R 0h This field indicates the state of the SMARTREFGLEX SYSCLK clock
LK in the domain.
2 CLKACTIVITY_L4_WKUP R 1h This field indicates the state of the L4_WKUP clock in the domain.
_GCLK
1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the always on clock domain.
0h (R/W) = NO_SLEEP: Sleep transition cannot be initiated. Wakeup
transition may however occur.
1h (R/W) = SW_SLEEP: Start a software forced sleep transition on
the domain.
2h (R/W) = SW_WKUP: Start a software forced wake-up transition
on the domain.
3h (R/W) = Reserved.
8.1.12.2.2 CM_WKUP_CONTROL_CLKCTRL Register (offset = 4h) [reset = 30000h]

CM_WKUP_CONTROL_CLKCTRL is shown in Figure 8-87 and described in Table 8-91.
This register manages the Control Module clocks.
Figure 8-87. CM_WKUP_CONTROL_CLKCTRL Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED RESERVED IDLEST
Rreturns0s-0h Rreturns0s-0h R-3h
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
RESERVED MODULEMODE
Rreturns0s-0h R/W-0h
Table 8-91. CM_WKUP_CONTROL_CLKCTRL Register Field Descriptions

18 RESERVED Rreturns0s 0h
0h (R) = Module is fully functional, including OCP
1h (R) = Module is performing transition: wakeup, or sleep, or sleep
abortion
2h (R) = Module is in Idle mode (only OCP part). It is functional if
3h (R) = Module is disabled and cannot be accessed
0h (R/W) = Module is disable by SW. Any OCP access to module
results in an error, except if resulting from a module wakeup
1h (R/W) = Reserved
2h (R/W) = Module is explicitly enabled. Interface clock (if not used
for functions) may be gated according to the clock domain state.
Functional clocks are guarantied to stay present. As long as in this
configuration, power domain sleep transition cannot happen.
3h (R) = Reserved
8.1.12.2.3 CM_WKUP_GPIO0_CLKCTRL Register (offset = 8h) [reset = 30000h]

CM_WKUP_GPIO0_CLKCTRL is shown in Figure 8-88 and described in Table 8-92.
Figure 8-88. CM_WKUP_GPIO0_CLKCTRL Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED OPTFCLKEN_ IDLEST
GPIO0_GDBCL
K
Rreturns0s-0h R/W-0h R-3h
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
RESERVED MODULEMODE
Table 8-92. CM_WKUP_GPIO0_CLKCTRL Register Field Descriptions

18 OPTFCLKEN_GPIO0_GD R/W 0h Optional functional clock control.
BCLK
0h (R/W) = Optional functional clock is disabled
1h (R/W) = Optional functional clock is enabled
abortion
1h (R/W) = Reserved
3h (R) = Reserved
8.1.12.2.4 CM_WKUP_L4WKUP_CLKCTRL Register (offset = Ch) [reset = 2h]

CM_WKUP_L4WKUP_CLKCTRL is shown in Figure 8-89 and described in Table 8-93.
This register manages the L4WKUP clocks.
Figure 8-89. CM_WKUP_L4WKUP_CLKCTRL Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
RESERVED MODULEMODE
Rreturns0s-0h R-2h
Table 8-93. CM_WKUP_L4WKUP_CLKCTRL Register Field Descriptions

abortion
1-0 MODULEMODE R 2h Control the way mandatory clocks are managed.
8.1.12.2.5 CM_WKUP_TIMER0_CLKCTRL Register (offset = 10h) [reset = 30002h]

CM_WKUP_TIMER0_CLKCTRL is shown in Figure 8-90 and described in Table 8-94.
Figure 8-90. CM_WKUP_TIMER0_CLKCTRL Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
RESERVED MODULEMODE
Table 8-94. CM_WKUP_TIMER0_CLKCTRL Register Field Descriptions

abortion
1h (R/W) = Reserved
3h (R) = Reserved
8.1.12.2.6 CM_WKUP_DEBUGSS_CLKCTRL Register (offset = 14h) [reset = 52580002h]

CM_WKUP_DEBUGSS_CLKCTRL is shown in Figure 8-91 and described in Table 8-95.
This register manages the DEBUGSS clocks.
Figure 8-91. CM_WKUP_DEBUGSS_CLKCTRL Register

31 30 29 28 27 26 25 24
RESERVED OPTCLK_DEB STM_PMD_CLKDIVSEL TRC_PMD_CLKDIVSEL
UG_CLKA
Rreturns0s-0h R/W-1h R/W-2h R/W-2h
23 22 21 20 19 18 17 16
STM_PMD_CLKSEL TRC_PMD_CLKSEL OPTFCLKEN_ STBYST IDLEST
DBGSYSCLK
R/W-1h R/W-1h R/W-1h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
RESERVED MODULEMODE
Table 8-95. CM_WKUP_DEBUGSS_CLKCTRL Register Field Descriptions

30 OPTCLK_DEBUG_CLKA R/W 1h Optional functional clock control.
0h = Optional functional clock is disabled.
1h = Optional functional clock is enabled.
29-27 STM_PMD_CLKDIVSEL R/W 2h
26-24 TRC_PMD_CLKDIVSEL R/W 2h
23-22 STM_PMD_CLKSEL R/W 1h
21-20 TRC_PMD_CLKSEL R/W 1h
19 OPTFCLKEN_DBGSYSC R/W 1h Optional functional clock control.
LK
0h (R/W) = Optional functional clock is disabled
1h (R/W) = Optional functional clock is enabled
0h (R) = Module is functional (not in standby)
1h (R) = Module is in standby
abortion
Table 8-95. CM_WKUP_DEBUGSS_CLKCTRL Register Field Descriptions (continued)

1h (R/W) = Reserved
3h (R) = Reserved
8.1.12.2.7 CM_L3_AON_CLKSTCTRL Register (offset = 18h) [reset = 1Ah]

CM_L3_AON_CLKSTCTRL is shown in Figure 8-92 and described in Table 8-96.
domain.
Figure 8-92. CM_L3_AON_CLKSTCTRL Register

31 30 29 28 27 26 25 24
RESERVED RESERVED
Rreturns0s-0h Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED RESERVED
7 6 5 4 3 2 1 0
RESERVED CLKACTIVITY_ CLKACTIVITY_ CLKACTIVITY_ CLKTRCTRL
DEBUG_CLKA L3_AON_GCLK DBGSYSCLK
Rreturns0s-0h R-1h R-1h R-0h R/W-2h
Table 8-96. CM_L3_AON_CLKSTCTRL Register Field Descriptions

4 CLKACTIVITY_DEBUG_C R 1h This field indicates the state of the Debugss CLKA clock in the
LKA domain.
0h (R) = Corresponding clock is gated.
1h (R) = Corresponding clock is active.
3 CLKACTIVITY_L3_AON_ R 1h This field indicates the state of the L3_AON clock in the domain.
GCLK
2 CLKACTIVITY_DBGSYS R 0h This field indicates the state of the Debugss sysclk clock in the
CLK domain.
1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the L3 AON clock domain.
0h (R/W) = NO_SLEEP: Sleep transition cannot be initiated. Wakeup
transition may however occur.
1h (R/W) = SW_SLEEP: Start a software forced sleep transition on
the domain.
2h (R/W) = SW_WKUP: Start a software forced wake-up transition
on the domain.
8.1.12.2.8 CM_AUTOIDLE_DPLL_MPU Register (offset = 1Ch) [reset = 0h]

CM_AUTOIDLE_DPLL_MPU is shown in Figure 8-93 and described in Table 8-97.
This register provides automatic control over the DPLL activity.
Figure 8-93. CM_AUTOIDLE_DPLL_MPU Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
RESERVED AUTO_DPLL_MODE
Table 8-97. CM_AUTOIDLE_DPLL_MPU Register Field Descriptions

2-0 AUTO_DPLL_MODE R/W 0h This feature is not supported.
8.1.12.2.9 CM_IDLEST_DPLL_MPU Register (offset = 20h) [reset = 0h]

CM_IDLEST_DPLL_MPU is shown in Figure 8-94 and described in Table 8-98.
This register allows monitoring the master clock activity. This register is read only and automatically
updated.[warm reset insensitive]
Figure 8-94. CM_IDLEST_DPLL_MPU Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED ST_MN_BYPA
SS
Rreturns0s-0h R-0h
7 6 5 4 3 2 1 0
RESERVED ST_DPLL_CLK
Rreturns0s-0h R-0h
Table 8-98. CM_IDLEST_DPLL_MPU Register Field Descriptions

8 ST_MN_BYPASS R 0h DPLL MN_BYPASS status
0h (R) = DPLL is not in MN_Bypass
1h (R) = DPLL is in MN_Bypass
0 ST_DPLL_CLK R 0h DPLL clock activity
0h (R) = DPLL is either in bypass mode or in stop mode.
1h (R) = DPLL is LOCKED
8.1.12.2.10 CM_SSC_DELTAMSTEP_DPLL_MPU Register (offset = 24h) [reset = 0h]

CM_SSC_DELTAMSTEP_DPLL_MPU is shown in Figure 8-95 and described in Table 8-99.
Control the DeltaMStep parameter for Spread Spectrum Clocking technique DeltaMStep is split into
fractional and integer part. [warm reset insensitive]
Figure 8-95. CM_SSC_DELTAMSTEP_DPLL_MPU Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED DELTAMSTEP_INTEGER DELTAMSTEP_FRACTION
Rreturns0s-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
DELTAMSTEP_FRACTION
R/W-0h
7 6 5 4 3 2 1 0
DELTAMSTEP_FRACTION
R/W-0h
Table 8-99. CM_SSC_DELTAMSTEP_DPLL_MPU Register Field Descriptions

19-18 DELTAMSTEP_INTEGER R/W 0h Integer part for DeltaM coefficient
17-0 DELTAMSTEP_FRACTIO R/W 0h Fractional part for DeltaM coefficient
N
8.1.12.2.11 CM-SSC_MODFREQDIV_DPLL_MPU Register (offset = 28h) [reset = 0h]

CM-SSC_MODFREQDIV_DPLL_MPU is shown in Figure 8-96 and described in Table 8-100.
Control the Modulation Frequency (Fm) for Spread Spectrum Clocking technique by defining it as a ratio
of DPLL_REFCLK/4 Fm = [DPLL_REFCLK/4]/MODFREQDIV MODFREQDIV =
MODFREQDIV_MANTISSA * 2^MODFREQDIV_EXPONENT [warm reset insensitive]
Figure 8-96. CM-SSC_MODFREQDIV_DPLL_MPU Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED MODFREQDIV_EXPONENT
7 6 5 4 3 2 1 0
RESERVED MODFREQDIV_MANTISSA
Table 8-100. CM-SSC_MODFREQDIV_DPLL_MPU Register Field Descriptions

10-8 MODFREQDIV_EXPONE R/W 0h Set the Exponent component of MODFREQDIV factor
NT
6-0 MODFREQDIV_MANTISS R/W 0h Set the Mantissa component of MODFREQDIV factor
A
8.1.12.2.12 CM_CLKSEL_DPLL_MPU Register (offset = 2Ch) [reset = 0h]

CM_CLKSEL_DPLL_MPU is shown in Figure 8-97 and described in Table 8-101.
This register provides controls over the DPLL.
Figure 8-97. CM_CLKSEL_DPLL_MPU Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
DPLL_BYP_CL RESERVED DPLL_MULT
KSEL
R/W-0h Rreturns0s-0h R/W-0h
15 14 13 12 11 10 9 8
DPLL_MULT
R/W-0h
7 6 5 4 3 2 1 0
RESERVED DPLL_DIV
Table 8-101. CM_CLKSEL_DPLL_MPU Register Field Descriptions

23 DPLL_BYP_CLKSEL R/W 0h Selects CLKINP or CLKINPULOW as Bypass Clock
0h (R/W) = Selects CLKINP Clock as BYPASS Clock
1h (R/W) = Selects CLKINPULOW as Bypass Clock
18-8 DPLL_MULT R/W 0h DPLL multiplier factor (2 to 2047).
This register is automatically cleared to 0 when the DPLL_EN field in
the *CLKMODE_DPLL* register is set to select MN Bypass mode.
(equal to input M of DPLL
M=2 to
2047 => DPLL multiplies by M).
0h (R/W) = 0 : Reserved
6-0 DPLL_DIV R/W 0h DPLL divider factor (0 to 127) (equal to input N of DPLL
actual division factor is N+1).
8.1.12.2.13 CM_AUTOIDLE_DPLL_DDR Register (offset = 30h) [reset = 0h]

CM_AUTOIDLE_DPLL_DDR is shown in Figure 8-98 and described in Table 8-102.
Figure 8-98. CM_AUTOIDLE_DPLL_DDR Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
Table 8-102. CM_AUTOIDLE_DPLL_DDR Register Field Descriptions

2-0 AUTO_DPLL_MODE R/W 0h AUTO_DPLL_MODE is not supported.
8.1.12.2.14 CM_IDLEST_DPLL_DDR Register (offset = 34h) [reset = 0h]

CM_IDLEST_DPLL_DDR is shown in Figure 8-99 and described in Table 8-103.
updated. [warm reset insensitive]
Figure 8-99. CM_IDLEST_DPLL_DDR Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED ST_MN_BYPA
SS
Rreturns0s-0h R-0h
7 6 5 4 3 2 1 0
Rreturns0s-0h R-0h
Table 8-103. CM_IDLEST_DPLL_DDR Register Field Descriptions

8.1.12.2.15 CM_SSC_DELTAMSTEP_DPLL_DDR Register (offset = 38h) [reset = 0h]

CM_SSC_DELTAMSTEP_DPLL_DDR is shown in Figure 8-100 and described in Table 8-104.
Figure 8-100. CM_SSC_DELTAMSTEP_DPLL_DDR Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
DELTAMSTEP_FRACTION
R/W-0h
7 6 5 4 3 2 1 0
DELTAMSTEP_FRACTION
R/W-0h
Table 8-104. CM_SSC_DELTAMSTEP_DPLL_DDR Register Field Descriptions

17-0 DELTAMSTEP_FRACTIO R/W 0h Fractional setting for DeltaMStep parameter
N
8.1.12.2.16 CM_SSC_MODFREQDIV_DPLL_DDR Register (offset = 3Ch) [reset = 0h]

CM_SSC_MODFREQDIV_DPLL_DDR is shown in Figure 8-101 and described in Table 8-105.
Figure 8-101. CM_SSC_MODFREQDIV_DPLL_DDR Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
Table 8-105. CM_SSC_MODFREQDIV_DPLL_DDR Register Field Descriptions

NT
A
8.1.12.2.17 CM_CLKSEL_DPLL_DDR Register (offset = 40h) [reset = 0h]

CM_CLKSEL_DPLL_DDR is shown in Figure 8-102 and described in Table 8-106.
Figure 8-102. CM_CLKSEL_DPLL_DDR Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
KSEL
15 14 13 12 11 10 9 8
DPLL_MULT
R/W-0h
7 6 5 4 3 2 1 0
RESERVED DPLL_DIV
Table 8-106. CM_CLKSEL_DPLL_DDR Register Field Descriptions

23 DPLL_BYP_CLKSEL R/W 0h Select CLKINP orr CLKINPULOW as bypass clock
M=2 to
8.1.12.2.18 CM_AUTOIDLE_DPLL_DISP Register (offset = 44h) [reset = 0h]

CM_AUTOIDLE_DPLL_DISP is shown in Figure 8-103 and described in Table 8-107.
Figure 8-103. CM_AUTOIDLE_DPLL_DISP Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
Table 8-107. CM_AUTOIDLE_DPLL_DISP Register Field Descriptions

8.1.12.2.19 CM_IDLEST_DPLL_DISP Register (offset = 48h) [reset = 0h]

CM_IDLEST_DPLL_DISP is shown in Figure 8-104 and described in Table 8-108.
Figure 8-104. CM_IDLEST_DPLL_DISP Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED ST_MN_BYPA
SS
Rreturns0s-0h R-0h
7 6 5 4 3 2 1 0
Rreturns0s-0h R-0h
Table 8-108. CM_IDLEST_DPLL_DISP Register Field Descriptions

8.1.12.2.20 CM_SSC_DELTAMSTEP_DPLL_DISP Register (offset = 4Ch) [reset = 0h]

CM_SSC_DELTAMSTEP_DPLL_DISP is shown in Figure 8-105 and described in Table 8-109.
Figure 8-105. CM_SSC_DELTAMSTEP_DPLL_DISP Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
DELTAMSTEP_FRACTION
R/W-0h
7 6 5 4 3 2 1 0
DELTAMSTEP_FRACTION
R/W-0h
Table 8-109. CM_SSC_DELTAMSTEP_DPLL_DISP Register Field Descriptions

N
8.1.12.2.21 CM_SSC_MODFREQDIV_DPLL_DISP Register (offset = 50h) [reset = 0h]

CM_SSC_MODFREQDIV_DPLL_DISP is shown in Figure 8-106 and described in Table 8-110.
Figure 8-106. CM_SSC_MODFREQDIV_DPLL_DISP Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
Table 8-110. CM_SSC_MODFREQDIV_DPLL_DISP Register Field Descriptions

NT
A
8.1.12.2.22 CM_CLKSEL_DPLL_DISP Register (offset = 54h) [reset = 0h]

CM_CLKSEL_DPLL_DISP is shown in Figure 8-107 and described in Table 8-111.
Figure 8-107. CM_CLKSEL_DPLL_DISP Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
KSEL
15 14 13 12 11 10 9 8
DPLL_MULT
R/W-0h
7 6 5 4 3 2 1 0
RESERVED DPLL_DIV
Table 8-111. CM_CLKSEL_DPLL_DISP Register Field Descriptions

23 DPLL_BYP_CLKSEL R/W 0h Select CLKINP or CLKINPULOW as bypass clock
M=2 to
8.1.12.2.23 CM_AUTOIDLE_DPLL_CORE Register (offset = 58h) [reset = 0h]

CM_AUTOIDLE_DPLL_CORE is shown in Figure 8-108 and described in Table 8-112.
Figure 8-108. CM_AUTOIDLE_DPLL_CORE Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
Table 8-112. CM_AUTOIDLE_DPLL_CORE Register Field Descriptions

2-0 AUTO_DPLL_MODE R/W 0h This feature is not supported.
8.1.12.2.24 CM_IDLEST_DPLL_CORE Register (offset = 5Ch) [reset = 0h]

CM_IDLEST_DPLL_CORE is shown in Figure 8-109 and described in Table 8-113.
Figure 8-109. CM_IDLEST_DPLL_CORE Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED ST_MN_BYPA
SS
Rreturns0s-0h R-0h
7 6 5 4 3 2 1 0
Rreturns0s-0h R-0h
Table 8-113. CM_IDLEST_DPLL_CORE Register Field Descriptions

8.1.12.2.25 CM_SSC_DELTAMSTEP_DPLL_CORE Register (offset = 60h) [reset = 0h]

CM_SSC_DELTAMSTEP_DPLL_CORE is shown in Figure 8-110 and described in Table 8-114.
Figure 8-110. CM_SSC_DELTAMSTEP_DPLL_CORE Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
DELTAMSTEP_FRACTION
R/W-0h
7 6 5 4 3 2 1 0
DELTAMSTEP_FRACTION
R/W-0h
Table 8-114. CM_SSC_DELTAMSTEP_DPLL_CORE Register Field Descriptions

N
8.1.12.2.26 CM_SSC_MODFREQDIV_DPLL_CORE Register (offset = 64h) [reset = 0h]

CM_SSC_MODFREQDIV_DPLL_CORE is shown in Figure 8-111 and described in Table 8-115.
Figure 8-111. CM_SSC_MODFREQDIV_DPLL_CORE Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
Table 8-115. CM_SSC_MODFREQDIV_DPLL_CORE Register Field Descriptions

NT
A
8.1.12.2.27 CM_CLKSEL_DPLL_CORE Register (offset = 68h) [reset = 0h]

CM_CLKSEL_DPLL_CORE is shown in Figure 8-112 and described in Table 8-116.
Figure 8-112. CM_CLKSEL_DPLL_CORE Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED RESERVED DPLL_MULT
Rreturns0s-0h Rreturns0s-0h R/W-0h
15 14 13 12 11 10 9 8
DPLL_MULT
R/W-0h
7 6 5 4 3 2 1 0
RESERVED DPLL_DIV
Table 8-116. CM_CLKSEL_DPLL_CORE Register Field Descriptions

M=2 to
2047 => DPLL multiplies by M)
0h (R/W) = Reserved
1h (R/W) = Reserved
8.1.12.2.28 CM_AUTOIDLE_DPLL_PER Register (offset = 6Ch) [reset = 0h]

CM_AUTOIDLE_DPLL_PER is shown in Figure 8-113 and described in Table 8-117.
Figure 8-113. CM_AUTOIDLE_DPLL_PER Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
Table 8-117. CM_AUTOIDLE_DPLL_PER Register Field Descriptions

8.1.12.2.29 CM_IDLEST_DPLL_PER Register (offset = 70h) [reset = 0h]

CM_IDLEST_DPLL_PER is shown in Figure 8-114 and described in Table 8-118.
Figure 8-114. CM_IDLEST_DPLL_PER Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED ST_MN_BYPA
SS
Rreturns0s-0h R-0h
7 6 5 4 3 2 1 0
Rreturns0s-0h R-0h
Table 8-118. CM_IDLEST_DPLL_PER Register Field Descriptions

8.1.12.2.30 CM_SSC_DELTAMSTEP_DPLL_PER Register (offset = 74h) [reset = 0h]

CM_SSC_DELTAMSTEP_DPLL_PER is shown in Figure 8-115 and described in Table 8-119.
Figure 8-115. CM_SSC_DELTAMSTEP_DPLL_PER Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
DELTAMSTEP_FRACTION
R/W-0h
7 6 5 4 3 2 1 0
DELTAMSTEP_FRACTION
R/W-0h
Table 8-119. CM_SSC_DELTAMSTEP_DPLL_PER Register Field Descriptions

N
8.1.12.2.31 CM_SSC_MODFREQDIV_DPLL_PER Register (offset = 78h) [reset = 0h]

CM_SSC_MODFREQDIV_DPLL_PER is shown in Figure 8-116 and described in Table 8-120.
Figure 8-116. CM_SSC_MODFREQDIV_DPLL_PER Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
Table 8-120. CM_SSC_MODFREQDIV_DPLL_PER Register Field Descriptions

NT
A
8.1.12.2.32 CM_CLKDCOLDO_DPLL_PER Register (offset = 7Ch) [reset = 0h]

CM_CLKDCOLDO_DPLL_PER is shown in Figure 8-117 and described in Table 8-121.
This register provides controls over the digitally controlled oscillator output of the PER DPLL.
Figure 8-117. CM_CLKDCOLDO_DPLL_PER Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED DPLL_CLKDC RESERVED ST_DPLL_CLK DPLL_CLKDC
OLDO_PWDN DCOLDO OLDO_GATE_
CTRL
Rreturns0s-0h R/W-0h Rreturns0s-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
Rreturns0s-0h
Table 8-121. CM_CLKDCOLDO_DPLL_PER Register Field Descriptions

12 DPLL_CLKDCOLDO_PW R/W 0h Automatic power down for CLKDCOLDO o/p when it is gated
DN
0h (R/W) = Keep CLKDCOLDO o/p powered on even when it is
gated
1h (R/W) = Automatically power down CLKDCOLDO o/p when it is
gated.
9 ST_DPLL_CLKDCOLDO R 0h DPLL CLKDCOLDO status
0h (R) = The clock output is gated
1h (R) = The clock output is enabled
8 DPLL_CLKDCOLDO_GA R/W 0h Control gating of DPLL CLKDCOLDO
TE_CTRL
0h (R/W) = Automatically gate this clock when there is no
dependency for it
1h (R/W) = Force this clock to stay enabled even if there is no
request
8.1.12.2.33 CM_DIV_M4_DPLL_CORE Register (offset = 80h) [reset = 4h]

CM_DIV_M4_DPLL_CORE is shown in Figure 8-118 and described in Table 8-122.
This register provides controls over the CLKOUT1 o/p of the HSDIVIDER.
Figure 8-118. CM_DIV_M4_DPLL_CORE Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED HSDIVIDER_C RESERVED ST_HSDIVIDE HSDIVIDER_C
LKOUT1_PWD R_CLKOUT1 LKOUT1_GAT
N E_CTRL
7 6 5 4 3 2 1 0
RESERVED HSDIVIDER_C HSDIVIDER_CLKOUT1_DIV
LKOUT1_DIVC
HACK
Rreturns0s-0h R-0h R/W-4h
Table 8-122. CM_DIV_M4_DPLL_CORE Register Field Descriptions

12 HSDIVIDER_CLKOUT1_P R/W 0h Automatic power down for HSDIVIDER M4 divider and hence
WDN CLKOUT1 output when the o/p clock is gated.
0h (R/W) = Keep M4 divider powered on even when CLKOUT1 is
gated.
1h (R/W) = Automatically power down M4 divider when CLKOUT1 is
gated.
9 ST_HSDIVIDER_CLKOU R 0h HSDIVIDER CLKOUT1 status
T1
8 HSDIVIDER_CLKOUT1_ R/W 0h Control gating of HSDIVIDER CLKOUT1
GATE_CTRL
dependency for it
request
5 HSDIVIDER_CLKOUT1_ R 0h Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV
DIVCHACK indicates that the change in divider value has taken effect
4-0 HSDIVIDER_CLKOUT1_ R/W 4h DPLL post-divider factor, M4, for internal clock generation.
DIV Divide values from 1 to 31.
0h (R/W) = Reserved
8.1.12.2.34 CM_DIV_M5_DPLL_CORE Register (offset = 84h) [reset = 4h]

This register provides controls over the CLKOUT2 o/p of the HSDIVIDER.

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
N E_CTRL
7 6 5 4 3 2 1 0
LKOUT2_DIVC
HACK

gated.
gated.
T2
GATE_CTRL
dependency for it
request
0h (R/W) = Reserved
8.1.12.2.35 CM_CLKMODE_DPLL_MPU Register (offset = 88h) [reset = 4h]

CM_CLKMODE_DPLL_MPU is shown in Figure 8-120 and described in Table 8-124.
This register allows controlling the DPLL modes.
Figure 8-120. CM_CLKMODE_DPLL_MPU Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
DPLL_SSC_TY DPLL_SSC_D DPLL_SSC_AC DPLL_SSC_EN DPLL_REGM4 DPLL_LPMOD DPLL_RELOC DPLL_DRIFTG
PE OWNSPREAD K XEN E_EN K_RAMP_EN UARD_EN
R/W-0h R/W-0h R-0h R/W-0h Rreturns0s-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
DPLL_RAMP_RATE DPLL_RAMP_LEVEL DPLL_EN
Table 8-124. CM_CLKMODE_DPLL_MPU Register Field Descriptions

15 DPLL_SSC_TYPE R/W 0h Select Triangular Spread Spectrum clocking.
Always write 0.
0 = Triangular Spread Spectrum Clocking is selected.
1 = Reserved.
14 DPLL_SSC_DOWNSPRE R/W 0h Control if only low frequency spread is required
AD
0h (R/W) = When SSC is enabled, clock frequency is spread on both
sides of the programmed frequency
1h (R/W) = When SSC is enabled, clock frequency is spread only on
the lower side of the programmed frequency
13 DPLL_SSC_ACK R 0h Acknowledgement from the DPLL regarding start and stop of Spread
Spectrum Clocking feature
0h (R) = SSC has been turned off on PLL o/ps
1h (R) = SSC has been turned on on PLL o/ps
12 DPLL_SSC_EN R/W 0h Enable or disable Spread Spectrum Clocking
0h (R/W) = SSC disabled
1h (R/W) = SSC enabled
11 DPLL_REGM4XEN Rreturns0s 0h Enable the REGM4XEN mode of the DPLL.
Please check the DPLL documentation to check when this mode can
be enabled.
0h (R) = REGM4XEN mode of the DPLL is disabled
10 DPLL_LPMODE_EN R/W 0h Set the DPLL in Low Power mode.
Check the DPLL documentation to see when this can be enabled.
0h (R/W) = Low power mode of the DPLL is disabled
1h (R/W) = Low power mode of the DPLL is enabled
9 DPLL_RELOCK_RAMP_E R/W 0h If enabled, the clock ramping feature is used applied during the lock
N process, as well as the relock process.
If disabled, the clock ramping feature is used only during the first
lock.
Table 8-124. CM_CLKMODE_DPLL_MPU Register Field Descriptions (continued)

8 DPLL_DRIFTGUARD_EN R/W 0h This bit allows to enable or disable the automatic recalibration
feature of the DPLL.
The DPLL will automatically start a recalibration process upon
assertion of the DPLL's RECAL flag if this bit is set.
0h (R/W) = DRIFTGUARD feature is disabled
1h (R/W) = DRIFTGUARD feature is enabled
7-5 DPLL_RAMP_RATE R/W 0h Selects the time in terms of DPLL REFCLKs spent at each stage of
the clock ramping process
0h (R/W) = 2 REFCLKs
4-3 DPLL_RAMP_LEVEL R/W 0h The DPLL provides an output clock frequency ramping feature when
switching from bypass clock to normal clock during lock and re-lock.
The frequency ramping will happen in a maximum of 4 steps in
frequency before the DPLL's frequency lock indicator is asserted.
This register is used to enable/disable the DPLL ramping feature.
If enabled, it is also used to select the algorithm used for clock
ramping
0h (R/W) = CLKOUT => No ramping CLKOUTX2 => No ramping
1h (R/W) = CLKOUT => Bypass clk -> Fout/8 -> Fout/4 -> Fout/2 ->
Fout CLKOUTX2 => Bypass clk -> Foutx2/8 -> Foutx2/4 -> Foutx2/2
-> Foutx2
2h (R/W) = CLKOUT => Bypass clk -> Fout/4 -> Fout/2 -> Fout/1.5 -
> Fout CLKOUTX2 => Bypass clk -> Foutx2/4 -> Foutx2/2 ->
Foutx2/1.5 -> Foutx2
3h (R/W) = Reserved
2-0 DPLL_EN R/W 4h DPLL control.
Upon Warm Reset, the PRCM DPLL control state machine updates
this register to reflect MN Bypass mode.
0h (R/W) = Reserved
1h (R/W) = Reserved
2h (R/W) = Reserved
3h (R/W) = Reserved
4h (R/W) = Put the DPLL in MN Bypass mode. The DPLL_MULT
register bits are reset to 0 automatically by putting the DPLL in this
mode.
5h (R/W) = Put the DPLL in Idle Bypass Low Power mode.
6h (R/W) = Put the DPLL in Idle Bypass Fast Relock mode.
7h (R/W) = Enables the DPLL in Lock mode
8.1.12.2.36 CM_CLKMODE_DPLL_PER Register (offset = 8Ch) [reset = 4h]

CM_CLKMODE_DPLL_PER is shown in Figure 8-121 and described in Table 8-125.
Figure 8-121. CM_CLKMODE_DPLL_PER Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
DPLL_SSC_TY DPLL_SSC_D DPLL_SSC_AC DPLL_SSC_EN RESERVED
PE OWNSPREAD K
R/W-0h R/W-0h R-0h R/W-0h Rreturns0s-0h
7 6 5 4 3 2 1 0
RESERVED DPLL_EN
Table 8-125. CM_CLKMODE_DPLL_PER Register Field Descriptions

Always write 0.
1 = Reserved.
AD
this register to reflect DPLL Low Power Stop mode.
0h (R/W) = Reserved
1h (R/W) = Put the DPLL in Low Power Stop mode
2h (R/W) = Reserved2
3h (R/W) = Reserved
mode.
6h (R/W) = Reserved
8.1.12.2.37 CM_CLKMODE_DPLL_CORE Register (offset = 90h) [reset = 4h]

CM_CLKMODE_DPLL_CORE is shown in Figure 8-122 and described in Table 8-126.
Figure 8-122. CM_CLKMODE_DPLL_CORE Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
Table 8-126. CM_CLKMODE_DPLL_CORE Register Field Descriptions

Always write 0.
1 = Reserved.
AD
be enabled.
lock.
Table 8-126. CM_CLKMODE_DPLL_CORE Register Field Descriptions (continued)

ramping
-> Foutx2
3h (R/W) = Reserved
0h (R/W) = Reserved
1h (R/W) = Reserved
2h (R/W) = Reserved
3h (R/W) = Reserved
mode.
8.1.12.2.38 CM_CLKMODE_DPLL_DDR Register (offset = 94h) [reset = 4h]

CM_CLKMODE_DPLL_DDR is shown in Figure 8-123 and described in Table 8-127.
Figure 8-123. CM_CLKMODE_DPLL_DDR Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
Table 8-127. CM_CLKMODE_DPLL_DDR Register Field Descriptions

Always write 0.
1 = Reserved.
AD
be enabled.
lock.
Table 8-127. CM_CLKMODE_DPLL_DDR Register Field Descriptions (continued)

ramping
-> Foutx2
3h (R/W) = Reserved
0h (R/W) = Reserved
1h (R/W) = Reserved
2h (R/W) = Reserved
3h (R/W) = Reserved
mode.
8.1.12.2.39 CM_CLKMODE_DPLL_DISP Register (offset = 98h) [reset = 4h]

CM_CLKMODE_DPLL_DISP is shown in Figure 8-124 and described in Table 8-128.
Figure 8-124. CM_CLKMODE_DPLL_DISP Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
Table 8-128. CM_CLKMODE_DPLL_DISP Register Field Descriptions

Always write 0.
1 = Reserved.
AD
be enabled.
lock.
Table 8-128. CM_CLKMODE_DPLL_DISP Register Field Descriptions (continued)

ramping
-> Foutx2
3h (R/W) = Reserved
0h (R/W) = Reserved
1h (R/W) = Reserved
2h (R/W) = Reserved
3h (R/W) = Reserved
mode.
8.1.12.2.40 CM_CLKSEL_DPLL_PERIPH Register (offset = 9Ch) [reset = 0h]

CM_CLKSEL_DPLL_PERIPH is shown in Figure 8-125 and described in Table 8-129.
Figure 8-125. CM_CLKSEL_DPLL_PERIPH Register

31 30 29 28 27 26 25 24
DPLL_SD_DIV
R/W-0h
23 22 21 20 19 18 17 16
RESERVED RESERVED DPLL_MULT
Rreturns0s-0h Rreturns0s-0h R/W-0h
15 14 13 12 11 10 9 8
DPLL_MULT
R/W-0h
7 6 5 4 3 2 1 0
DPLL_DIV
R/W-0h
Table 8-129. CM_CLKSEL_DPLL_PERIPH Register Field Descriptions

31-24 DPLL_SD_DIV R/W 0h Sigma-Delta divider select (
2-255).
This factor must be set by s/w to ensure optimum jitter performance.
DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)] * CLKINP
/ 250), where CLKINP is the input clock of the DPLL in MHz).
Must be set with M and N factors, and must not be changed once
DPLL is locked.
0h (R/W) = Reserved
1h (R/W) = Reserved
M=2 to
8.1.12.2.41 CM_DIV_M2_DPLL_DDR Register (offset = A0h) [reset = 1h]

CM_DIV_M2_DPLL_DDR is shown in Figure 8-126 and described in Table 8-130.
This register provides controls over the M2 divider of the DPLL.
Figure 8-126. CM_DIV_M2_DPLL_DDR Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED ST_DPLL_CLK DPLL_CLKOUT
OUT _GATE_CTRL
7 6 5 4 3 2 1 0
RESERVED DPLL_CLKOUT DPLL_CLKOUT_DIV
_DIVCHACK
Table 8-130. CM_DIV_M2_DPLL_DDR Register Field Descriptions

9 ST_DPLL_CLKOUT R 0h DPLL CLKOUT status
8 DPLL_CLKOUT_GATE_C R/W 0h Control gating of DPLL CLKOUT
TRL
dependency for it
request
5 DPLL_CLKOUT_DIVCHA R 0h Toggle on this status bit after changing DPLL_CLKOUT_DIV
CK indicates that the change in divider value has taken effect
4-0 DPLL_CLKOUT_DIV R/W 1h DPLL M2 post-divider factor (1 to 31).
0h (R/W) = Reserved
8.1.12.2.42 CM_DIV_M2_DPLL_DISP Register (offset = A4h) [reset = 1h]

CM_DIV_M2_DPLL_DISP is shown in Figure 8-127 and described in Table 8-131.
Figure 8-127. CM_DIV_M2_DPLL_DISP Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
OUT _GATE_CTRL
7 6 5 4 3 2 1 0
_DIVCHACK
Table 8-131. CM_DIV_M2_DPLL_DISP Register Field Descriptions

TRL
dependency for it
request
0h (R/W) = Reserved
8.1.12.2.43 CM_DIV_M2_DPLL_MPU Register (offset = A8h) [reset = 1h]

CM_DIV_M2_DPLL_MPU is shown in Figure 8-128 and described in Table 8-132.
Figure 8-128. CM_DIV_M2_DPLL_MPU Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
OUT _GATE_CTRL
7 6 5 4 3 2 1 0
_DIVCHACK
Table 8-132. CM_DIV_M2_DPLL_MPU Register Field Descriptions

TRL
dependency for it
request
0h (R/W) = Reserved
8.1.12.2.44 CM_DIV_M2_DPLL_PER Register (offset = ACh) [reset = 1h]

CM_DIV_M2_DPLL_PER is shown in Figure 8-129 and described in Table 8-133.
Figure 8-129. CM_DIV_M2_DPLL_PER Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
OUT _GATE_CTRL
7 6 5 4 3 2 1 0
DPLL_CLKOUT DPLL_CLKOUT_DIV
_DIVCHACK
R-0h R/W-1h
Table 8-133. CM_DIV_M2_DPLL_PER Register Field Descriptions

TRL
dependency for it
request
0h (R/W) = Reserved
8.1.12.2.45 CM_WKUP_WKUP_M3_CLKCTRL Register (offset = B0h) [reset = 2h]

CM_WKUP_WKUP_M3_CLKCTRL is shown in Figure 8-130 and described in Table 8-134.
This register manages the WKUP M3 clocks.
Figure 8-130. CM_WKUP_WKUP_M3_CLKCTRL Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED STBYST RESERVED
Rreturns0s-0h R-0h Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
RESERVED MODULEMODE
Rreturns0s-0h R-2h
Table 8-134. CM_WKUP_WKUP_M3_CLKCTRL Register Field Descriptions

0h (R) = Module is functional (not in standby)
1h (R) = Module is in standby
1-0 MODULEMODE R 2h Control the way mandatory clocks are managed.
8.1.12.2.46 CM_WKUP_UART0_CLKCTRL Register (offset = B4h) [reset = 30000h]

CM_WKUP_UART0_CLKCTRL is shown in Figure 8-131 and described in Table 8-135.
Figure 8-131. CM_WKUP_UART0_CLKCTRL Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED IDLEST
Rreturns0s-0h R-3h
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
RESERVED MODULEMODE
Table 8-135. CM_WKUP_UART0_CLKCTRL Register Field Descriptions

abortion
1h (R/W) = Reserved
3h (R) = Reserved
8.1.12.2.47 CM_WKUP_I2C0_CLKCTRL Register (offset = B8h) [reset = 30000h]

CM_WKUP_I2C0_CLKCTRL is shown in Figure 8-132 and described in Table 8-136.
Figure 8-132. CM_WKUP_I2C0_CLKCTRL Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED IDLEST
Rreturns0s-0h R-3h
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
RESERVED MODULEMODE
Table 8-136. CM_WKUP_I2C0_CLKCTRL Register Field Descriptions

abortion
1h (R/W) = Reserved
3h (R) = Reserved
8.1.12.2.48 CM_WKUP_ADC_TSC_CLKCTRL Register (offset = BCh) [reset = 30000h]

CM_WKUP_ADC_TSC_CLKCTRL is shown in Figure 8-133 and described in Table 8-137.
This register manages the ADC clocks.
Figure 8-133. CM_WKUP_ADC_TSC_CLKCTRL Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED IDLEST
Rreturns0s-0h R-3h
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
RESERVED MODULEMODE
Table 8-137. CM_WKUP_ADC_TSC_CLKCTRL Register Field Descriptions

abortion
1h (R/W) = Reserved
3h (R) = Reserved
8.1.12.2.49 CM_WKUP_SMARTREFLEX0_CLKCTRL Register (offset = C0h) [reset = 30000h]

CM_WKUP_SMARTREFLEX0_CLKCTRL is shown in Figure 8-134 and described in Table 8-138.
This register manages the SmartReflex0 clocks.
Figure 8-134. CM_WKUP_SMARTREFLEX0_CLKCTRL Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED IDLEST
Rreturns0s-0h R-3h
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
RESERVED MODULEMODE
Table 8-138. CM_WKUP_SMARTREFLEX0_CLKCTRL Register Field Descriptions

abortion
1h (R/W) = Reserved
3h (R) = Reserved
8.1.12.2.50 CM_WKUP_TIMER1_CLKCTRL Register (offset = C4h) [reset = 30000h]

CM_WKUP_TIMER1_CLKCTRL is shown in Figure 8-135 and described in Table 8-139.
Figure 8-135. CM_WKUP_TIMER1_CLKCTRL Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
RESERVED MODULEMODE
Table 8-139. CM_WKUP_TIMER1_CLKCTRL Register Field Descriptions

abortion
1h (R/W) = Reserved
3h (R) = Reserved
8.1.12.2.51 CM_WKUP_SMARTREFLEX1_CLKCTRL Register (offset = C8h) [reset = 30000h]

CM_WKUP_SMARTREFLEX1_CLKCTRL is shown in Figure 8-136 and described in Table 8-140.
This register manages the SmartReflex1 clocks.
Figure 8-136. CM_WKUP_SMARTREFLEX1_CLKCTRL Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED IDLEST
Rreturns0s-0h R-3h
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
RESERVED MODULEMODE
Table 8-140. CM_WKUP_SMARTREFLEX1_CLKCTRL Register Field Descriptions

abortion
1h (R/W) = Reserved
3h (R) = Reserved
8.1.12.2.52 CM_L4_WKUP_AON_CLKSTCTRL Register (offset = CCh) [reset = 6h]

CM_L4_WKUP_AON_CLKSTCTRL is shown in Figure 8-137 and described in Table 8-141.
domain.
Figure 8-137. CM_L4_WKUP_AON_CLKSTCTRL Register

31 30 29 28 27 26 25 24
RESERVED RESERVED
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED RESERVED
7 6 5 4 3 2 1 0
RESERVED RESERVED CLKACTIVITY_ CLKTRCTRL
L4_WKUP_AO
N_GCLK
Rreturns0s-0h Rreturns0s-0h R-1h R-2h
Table 8-141. CM_L4_WKUP_AON_CLKSTCTRL Register Field Descriptions

2 CLKACTIVITY_L4_WKUP R 1h This field indicates the state of the L4_WKUP clock in the domain.
_AON_GCLK
1-0 CLKTRCTRL R 2h Controls the clock state transition of the always on L4 clock domain.
0h (R/W) = Sleep transition cannot be initiated. Wakeup transition
may however occur.
1h (R/W) = Start a software forced sleep transition on the domain.
2h (R/W) = Start a software forced wake-up transition on the domain.
8.1.12.2.53 CM_WKUP_WDT1_CLKCTRL Register (offset = D4h) [reset = 30002h]

CM_WKUP_WDT1_CLKCTRL is shown in Figure 8-138 and described in Table 8-142.
This register manages the WDT1 clocks.
Figure 8-138. CM_WKUP_WDT1_CLKCTRL Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
RESERVED MODULEMODE
Table 8-142. CM_WKUP_WDT1_CLKCTRL Register Field Descriptions

abortion
1h (R/W) = Reserved
3h (R) = Reserved
8.1.12.2.54 CM_DIV_M6_DPLL_CORE Register (offset = D8h) [reset = 4h]

This register provides controls over the CLKOUT3 o/p of the HSDIVIDER. [warm reset insensitive]

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
N E_CTRL
7 6 5 4 3 2 1 0
LKOUT3_DIVC
HACK

gated.
gated.
T3
GATE_CTRL
dependency for it
request
0h (R/W) = Reserved
8.1.12.3 CM_DPLL Registers

Table 8-144 lists the memory-mapped registers for the CM_DPLL. All register offset addresses not listed
modified.
Table 8-144. CM_DPLL REGISTERS

4h CLKSEL_TIMER7_CLK Selects the Mux select line for TIMER7 clock [warm Section 8.1.12.3.1
reset insensitive]
reset insensitive]
Ch CLKSEL_TIMER3_CLK Selects the Mux select line for TIMER3 clock [warm Section 8.1.12.3.3
reset insensitive]
reset insensitive]
14h CM_MAC_CLKSEL Selects the clock divide ration for MII clock [warm reset Section 8.1.12.3.5
insensitive]
reset insensitive]
1Ch CLKSEL_TIMER6_CLK Selects the Mux select line for TIMER6 clock [warm Section 8.1.12.3.7
reset insensitive]
20h CM_CPTS_RFT_CLKSEL Selects the Mux select line for CPTS RFT clock [warm Section 8.1.12.3.8
reset insensitive]
28h CLKSEL_TIMER1MS_CLK Selects the Mux select line for TIMER1 clock [warm Section 8.1.12.3.9
reset insensitive]
2Ch CLKSEL_GFX_FCLK Selects the divider value for GFX clock [warm reset Section 8.1.12.3.10
insensitive]
30h CLKSEL_PRU_ICSS_OCP_CLK Controls the Mux select line for PRU-ICSS OCP clock Section 8.1.12.3.11
[warm reset insensitive]
34h CLKSEL_LCDC_PIXEL_CLK Controls the Mux select line for LCDC PIXEL clock Section 8.1.12.3.12
38h CLKSEL_WDT1_CLK Selects the Mux select line for Watchdog1 clock [warm Section 8.1.12.3.13
reset insensitive]
3Ch CLKSEL_GPIO0_DBCLK Selects the Mux select line for GPIO0 debounce clock Section 8.1.12.3.14
8.1.12.3.1 CLKSEL_TIMER7_CLK Register (offset = 4h) [reset = 1h]

CLKSEL_TIMER7_CLK is shown in Figure 8-140 and described in Table 8-145.
Selects the Mux select line for TIMER7 clock [warm reset insensitive]
Figure 8-140. CLKSEL_TIMER7_CLK Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-1h
Table 8-145. CLKSEL_TIMER7_CLK Register Field Descriptions

31-2 Reserved R 0h
1-0 CLKSEL R/W 1h Selects the Mux select line for TIMER7 clock [warm reset insensitive]
0x0 = SEL1 : Select TCLKIN clock
0x1 = SEL2 : Select CLK_M_OSC clock
0x2 = SEL3 : Select CLK_32KHZ clock
0x3 = SEL4 : Reserved


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-1h

31-2 Reserved R 0h
8.1.12.3.3 CLKSEL_TIMER3_CLK Register (offset = Ch) [reset = 1h]


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-1h

31-2 Reserved R 0h


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-1h

31-2 Reserved R 0h
8.1.12.3.5 CM_MAC_CLKSEL Register (offset = 14h) [reset = 4h]

CM_MAC_CLKSEL is shown in Figure 8-144 and described in Table 8-149.
Selects the clock divide ration for MII clock [warm reset insensitive]
Figure 8-144. CM_MAC_CLKSEL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MII_CLK_SEL Reserved
R-0h R/W-1h R-0h
Table 8-149. CM_MAC_CLKSEL Register Field Descriptions

31-3 Reserved R 0h
2 MII_CLK_SEL R/W 1h MII Clock Divider Selection.
enabled
0x0 = SEL0 : Selects 1/2 divider of SYSCLK2
0x1 = SEL1 : Selects 1/5 divide ratio of SYSCLK2
1-0 Reserved R 0h


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-1h

31-2 Reserved R 0h
8.1.12.3.7 CLKSEL_TIMER6_CLK Register (offset = 1Ch) [reset = 1h]


31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-1h

31-2 Reserved R 0h
8.1.12.3.8 CM_CPTS_RFT_CLKSEL Register (offset = 20h) [reset = 0h]

CM_CPTS_RFT_CLKSEL is shown in Figure 8-147 and described in Table 8-152.
Selects the Mux select line for CPTS RFT clock [warm reset insensitive]
Figure 8-147. CM_CPTS_RFT_CLKSEL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved Reserved Reserved CLKSEL
Table 8-152. CM_CPTS_RFT_CLKSEL Register Field Descriptions

31-3 Reserved R 0h
2 Reserved R 0h
1 Reserved R 0h
0 CLKSEL R/W 0h Selects the Mux select line for cpgmac rft clock [warm reset
insensitive]
0x0 = SEL1 : Selects CORE_CLKOUTM5
0x1 = SEL2 : Selects CORE_CLKOUTM4
8.1.12.3.9 CLKSEL_TIMER1MS_CLK Register (offset = 28h) [reset = 0h]

CLKSEL_TIMER1MS_CLK is shown in Figure 8-148 and described in Table 8-153.
Figure 8-148. CLKSEL_TIMER1MS_CLK Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-0h
Table 8-153. CLKSEL_TIMER1MS_CLK Register Field Descriptions

31-3 Reserved R 0h
2-0 CLKSEL R/W 0h Selects the Mux select line for DMTIMER_1MS clock [warm reset
insensitive]
0x3 = SEL4 : Select CLK_RC32K clock
0x4 = SEL5 : Selects the CLK_32768 from 32KHz Crystal Osc
8.1.12.3.10 CLKSEL_GFX_FCLK Register (offset = 2Ch) [reset = 0h]

CLKSEL_GFX_FCLK is shown in Figure 8-149 and described in Table 8-154.
Selects the divider value for GFX clock [warm reset insensitive]
Figure 8-149. CLKSEL_GFX_FCLK Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL_GFX_ CLKDIV_SEL_
FCLK GFX_FCLK
R-0h R/W-0h R/W-0h
Table 8-154. CLKSEL_GFX_FCLK Register Field Descriptions

31-2 Reserved R 0h
1 CLKSEL_GFX_FCLK R/W 0h Selects the clock on gfx fclk [warm reset insensitive]
0x0 = SEL0 : SGX FCLK is from CORE PLL (same as L3 clock)
0x1 = SEL1 : SGX FCLK is from PER PLL (192 MHz clock)
0 CLKDIV_SEL_GFX_FCLK R/W 0h Selects the divider value on gfx fclk [warm reset insensitive]
0x0 = DIV1 : SGX FCLK is same as L3 Clock or 192MHz Clock
0x1 = DIV2 : SGX FCLK is L3 clock/2 or 192Mhz/2
8.1.12.3.11 CLKSEL_PRU_ICSS_OCP_CLK Register (offset = 30h) [reset = 0h]

CLKSEL_PRU_ICSS_OCP_CLK is shown in Figure 8-150 and described in Table 8-155.
Controls the Mux select line for PRU-ICSS OCP clock [warm reset insensitive]
Figure 8-150. CLKSEL_PRU_ICSS_OCP_CLK Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-0h
Table 8-155. CLKSEL_PRU_ICSS_OCP_CLK Register Field Descriptions

31-1 Reserved R 0h
0 CLKSEL R/W 0h Controls Mux Select of PRU-ICSS OCP clock mux
0x0 = SEL1 : Select L3F clock as OCP Clock of PRU-ICSS
0x1 = SEL2 : Select DISP DPLL clock as OCP clock of PRU-ICSS
8.1.12.3.12 CLKSEL_LCDC_PIXEL_CLK Register (offset = 34h) [reset = 0h]

CLKSEL_LCDC_PIXEL_CLK is shown in Figure 8-151 and described in Table 8-156.
Controls the Mux select line for LCDC PIXEL clock [warm reset insensitive]
Figure 8-151. CLKSEL_LCDC_PIXEL_CLK Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-0h
Table 8-156. CLKSEL_LCDC_PIXEL_CLK Register Field Descriptions

31-2 Reserved R 0h
1-0 CLKSEL R/W 0h Controls the Mux Select of LCDC PIXEL clock
0x0 = SEL1 : Select DISP PLL CLKOUTM2
0x1 = SEL2 : Select CORE PLL CLKOUTM5
0x2 = SEL3 : Select PER PLL CLKOUTM2
8.1.12.3.13 CLKSEL_WDT1_CLK Register (offset = 38h) [reset = 1h]

CLKSEL_WDT1_CLK is shown in Figure 8-152 and described in Table 8-157.
Selects the Mux select line for Watchdog1 clock [warm reset insensitive]
Figure 8-152. CLKSEL_WDT1_CLK Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-1h
Table 8-157. CLKSEL_WDT1_CLK Register Field Descriptions

31-1 Reserved R 0h
0 CLKSEL R/W 1h Selects the Mux select line for WDT1 clock [warm reset insensitive]
0x0 = SEL1 : Select 32KHZ clock from RC Oscillator
0x1 = SEL2 : Select 32KHZ from 32K Clock divider
8.1.12.3.14 CLKSEL_GPIO0_DBCLK Register (offset = 3Ch) [reset = 0h]

CLKSEL_GPIO0_DBCLK is shown in Figure 8-153 and described in Table 8-158.
Selects the Mux select line for GPIO0 debounce clock [warm reset insensitive]
Figure 8-153. CLKSEL_GPIO0_DBCLK Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-0h
Table 8-158. CLKSEL_GPIO0_DBCLK Register Field Descriptions

31-2 Reserved R 0h
1-0 CLKSEL R/W 0h Selects the Mux select line for GPIO0 debounce clock [warm reset
insensitive]
0x0 = SEL1 : Select 32KHZ clock from RC Oscillator
0x1 = SEL2 : Select 32KHZ from 32K Crystal Oscillator
0x2 = SEL3 : Select 32KHz from Clock Divider
8.1.12.4 CM_MPU Registers

Table 8-159 lists the memory-mapped registers for the CM_MPU. All register offset addresses not listed in
Table 8-159. CM_MPU REGISTERS

0h CM_MPU_CLKSTCTRL This register enables the domain power state transition. Section 8.1.12.4.1
It controls the SW supervised clock domain state
transition between ON-ACTIVE and ON-INACTIVE
states.
It also hold one status bit per clock input of the domain.
4h CM_MPU_MPU_CLKCTRL This register manages the MPU clocks. Section 8.1.12.4.2
8.1.12.4.1 CM_MPU_CLKSTCTRL Register (offset = 0h) [reset = 6h]

CM_MPU_CLKSTCTRL is shown in Figure 8-154 and described in Table 8-160.
domain.
Figure 8-154. CM_MPU_CLKSTCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKACTIVITY_ CLKTRCTRL
MPU_CLK
R-0h R-1h R/W-2h
Table 8-160. CM_MPU_CLKSTCTRL Register Field Descriptions

31-3 Reserved R 0h
2 CLKACTIVITY_MPU_CLK R 1h This field indicates the state of the MPU Clock
1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the MPU clock domains.
8.1.12.4.2 CM_MPU_MPU_CLKCTRL Register (offset = 4h) [reset = 2h]

CM_MPU_MPU_CLKCTRL is shown in Figure 8-155 and described in Table 8-161.
This register manages the MPU clocks.
Figure 8-155. CM_MPU_MPU_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
Table 8-161. CM_MPU_MPU_CLKCTRL Register Field Descriptions

31-19 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.5 CM_DEVICE Registers

Table 8-162 lists the memory-mapped registers for the CM_DEVICE. All register offset addresses not
modified.
Table 8-162. CM_DEVICE REGISTERS

0h CM_CLKOUT_CTRL This register provides the control over CLKOUT2 output Section 8.1.12.5.1
8.1.12.5.1 CM_CLKOUT_CTRL Register (offset = 0h) [reset = 0h]

CM_CLKOUT_CTRL is shown in Figure 8-156 and described in Table 8-163.
This register provides the control over CLKOUT2 output
Figure 8-156. CM_CLKOUT_CTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
CLKOUT2EN Reserved CLKOUT2DIV CLKOUT2SOURCE
R/W-0h R-0h R/W-0h R/W-0h
Table 8-163. CM_CLKOUT_CTRL Register Field Descriptions

31-8 Reserved R 0h
7 CLKOUT2EN R/W 0h This bit controls the external clock activity
0x0 = DIS : SYS_CLKOUT2 is disabled
0x1 = EN : SYS_CLKOUT2 is enabled
6 Reserved R 0h
5-3 CLKOUT2DIV R/W 0h THis field controls the external clock divison factor
0x0 = DIV1 : SYS_CLKOUT2/1
0x7 = Reserved
2-0 CLKOUT2SOURCE R/W 0h This field selects the external output clock source
0x0 = SEL0 : Select 32KHz Oscillator O/P
0x1 = SEL1 : Select L3 Clock
0x2 = SEL2 : Select DDR PHY Clock
0x3 = SEL4 : Select 192Mhz clock from PER PLL
0x4 = SEL5 : Select LCD Pixel Clock
8.1.12.6 CM_RTC Registers

Table 8-164 lists the memory-mapped registers for the CM_RTC. All register offset addresses not listed in
Table 8-164. CM_RTC REGISTERS

0h CM_RTC_RTC_CLKCTRL This register manages the RTC clocks. Section 8.1.12.6.1
4h CM_RTC_CLKSTCTRL This register enables the domain power state transition. Section 8.1.12.6.2
states.
8.1.12.6.1 CM_RTC_RTC_CLKCTRL Register (offset = 0h) [reset = 30002h]

CM_RTC_RTC_CLKCTRL is shown in Figure 8-157 and described in Table 8-165.
This register manages the RTC clocks.
Figure 8-157. CM_RTC_RTC_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
R-0h R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
Table 8-165. CM_RTC_RTC_CLKCTRL Register Field Descriptions

31-19 Reserved R 0h
18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.6.2 CM_RTC_CLKSTCTRL Register (offset = 4h) [reset = 102h]

CM_RTC_CLKSTCTRL is shown in Figure 8-158 and described in Table 8-166.
domain.
Figure 8-158. CM_RTC_CLKSTCTRL Register

31 30 29 28 27 26 25 24
Reserved Reserved
R-0h R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved Reserved CLKACTIVITY_ CLKACTIVITY_
RTC_32KCLK L4_RTC_GCLK
R-0h R-0h R-0h R-1h
7 6 5 4 3 2 1 0
Reserved CLKTRCTRL
R-0h R/W-2h
Table 8-166. CM_RTC_CLKSTCTRL Register Field Descriptions

31-26 Reserved R 0h
25-11 Reserved R 0h
10 Reserved R 0h
9 CLKACTIVITY_RTC_32K R 0h This field indicates the state of the 32K RTC clock in the domain.
CLK
0x0 = Inact
0x1 = Act
8 CLKACTIVITY_L4_RTC_ R 1h This field indicates the state of the L4 RTC clock in the domain.
GCLK
7-2 Reserved R 0h
1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the RTC clock domains.
8.1.12.7 CM_GFX Registers

Table 8-167 lists the memory-mapped registers for the CM_GFX. All register offset addresses not listed in
Table 8-167. CM_GFX REGISTERS

0h CM_GFX_L3_CLKSTCTRL This register enables the domain power state transition. Section 8.1.12.7.1
states.
4h CM_GFX_GFX_CLKCTRL This register manages the GFX clocks. Section 8.1.12.7.2
Ch CM_GFX_L4LS_GFX_CLKSTCTR This register enables the domain power state transition. Section 8.1.12.7.3
L It controls the SW supervised clock domain state
states.
10h CM_GFX_MMUCFG_CLKCTRL This register manages the MMU CFG clocks. Section 8.1.12.7.4
14h CM_GFX_MMUDATA_CLKCTRL This register manages the MMU clocks. Section 8.1.12.7.5
8.1.12.7.1 CM_GFX_L3_CLKSTCTRL Register (offset = 0h) [reset = 2h]

CM_GFX_L3_CLKSTCTRL is shown in Figure 8-159 and described in Table 8-168.
domain.
Figure 8-159. CM_GFX_L3_CLKSTCTRL Register

31 30 29 28 27 26 25 24
Reserved Reserved
R-0h R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved CLKACTIVITY_ CLKACTIVITY_
GFX_FCLK GFX_L3_GCLK
R-0h R-0h R-0h
7 6 5 4 3 2 1 0
Reserved CLKTRCTRL
R-0h R/W-2h
Table 8-168. CM_GFX_L3_CLKSTCTRL Register Field Descriptions

31-26 Reserved R 0h
25-10 Reserved R 0h
9 CLKACTIVITY_GFX_FCL R 0h This field indicates the state of the GFX_GCLK clock in the domain.
K
8 CLKACTIVITY_GFX_L3_ R 0h This field indicates the state of the GFX_L3_GCLK clock in the
GCLK domain.
7-2 Reserved R 0h
1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the GFX clock domain in GFX
power domain.
8.1.12.7.2 CM_GFX_GFX_CLKCTRL Register (offset = 4h) [reset = 70000h]

CM_GFX_GFX_CLKCTRL is shown in Figure 8-160 and described in Table 8-169.
This register manages the GFX clocks.
Figure 8-160. CM_GFX_GFX_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-169. CM_GFX_GFX_CLKCTRL Register Field Descriptions

31-19 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.7.3 CM_GFX_L4LS_GFX_CLKSTCTRL Register (offset = Ch) [reset = 102h]

CM_GFX_L4LS_GFX_CLKSTCTRL is shown in Figure 8-161 and described in Table 8-170.
domain.
Figure 8-161. CM_GFX_L4LS_GFX_CLKSTCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved CLKACTIVITY_
L4LS_GFX_GC
LK
R-0h R-1h
7 6 5 4 3 2 1 0
Reserved CLKTRCTRL
R-0h R/W-2h
Table 8-170. CM_GFX_L4LS_GFX_CLKSTCTRL Register Field Descriptions

31-9 Reserved R 0h
8 CLKACTIVITY_L4LS_GF R 1h This field indicates the state of the L4_LS clock in the domain.
X_GCLK
0x0 = Inact
0x1 = Act
7-2 Reserved R 0h
1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the L4LS clock domain in GFX
power domain.
8.1.12.7.4 CM_GFX_MMUCFG_CLKCTRL Register (offset = 10h) [reset = 30000h]

CM_GFX_MMUCFG_CLKCTRL is shown in Figure 8-162 and described in Table 8-171.
This register manages the MMU CFG clocks.
Figure 8-162. CM_GFX_MMUCFG_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-171. CM_GFX_MMUCFG_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.7.5 CM_GFX_MMUDATA_CLKCTRL Register (offset = 14h) [reset = 30000h]

CM_GFX_MMUDATA_CLKCTRL is shown in Figure 8-163 and described in Table 8-172.
This register manages the MMU clocks.
Figure 8-163. CM_GFX_MMUDATA_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-172. CM_GFX_MMUDATA_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.12.8 CM_CEFUSE Registers

Table 8-173 lists the memory-mapped registers for the CM_CEFUSE. All register offset addresses not
modified.
Table 8-173. CM_CEFUSE REGISTERS

0h CM_CEFUSE_CLKSTCTRL This register enables the domain power state transition. Section 8.1.12.8.1
It controls the HW supervised domain power state
states.
Table 8-173. CM_CEFUSE REGISTERS (continued)

20h CM_CEFUSE_CEFUSE_CLKCTR This register manages the CEFUSE clocks. Section 8.1.12.8.2
L
8.1.12.8.1 CM_CEFUSE_CLKSTCTRL Register (offset = 0h) [reset = 2h]

CM_CEFUSE_CLKSTCTRL is shown in Figure 8-164 and described in Table 8-174.
This register enables the domain power state transition. It controls the HW supervised domain power state
domain.
Figure 8-164. CM_CEFUSE_CLKSTCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved CLKACTIVITY_ CLKACTIVITY_
CUST_EFUSE L4_CEFUSE_G
_SYS_CLK ICLK
R-0h R-0h R-0h
7 6 5 4 3 2 1 0
Reserved CLKTRCTRL
R-0h R/W-2h
Table 8-174. CM_CEFUSE_CLKSTCTRL Register Field Descriptions

31-10 Reserved R 0h
9 CLKACTIVITY_CUST_EF R 0h This field indicates the state of the Cust_Efuse_SYSCLK clock input
USE_SYS_CLK of the domain.
0x0 = Inact : Corresponding clock is definitely gated
0x1 = Act : Corresponding clock is running or gating/ungating
transition is on-going
8 CLKACTIVITY_L4_CEFU R 0h This field indicates the state of the L4_CEFUSE_GCLK clock input of
SE_GICLK the domain.
0x0 = Inact : Corresponding clock is definitely gated
0x1 = Act : Corresponding clock is running or gating/ungating
transition is on-going
7-2 Reserved R 0h
1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the clock domain in customer
efuse power domain.
8.1.12.8.2 CM_CEFUSE_CEFUSE_CLKCTRL Register (offset = 20h) [reset = 30000h]

CM_CEFUSE_CEFUSE_CLKCTRL is shown in Figure 8-165 and described in Table 8-175.
This register manages the CEFUSE clocks.
Figure 8-165. CM_CEFUSE_CEFUSE_CLKCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
Table 8-175. CM_CEFUSE_CEFUSE_CLKCTRL Register Field Descriptions

31-18 Reserved R 0h
sleep abortion
15-2 Reserved R 0h
8.1.13 Power Management Registers
8.1.13.1 PRM_IRQ Registers

Table 8-176 lists the memory-mapped registers for the PRM_IRQ. All register offset addresses not listed
modified.
Table 8-176. PRM_IRQ REGISTERS

0h REVISION_PRM This register contains the IP revision code for the PRCM Section 8.1.13.1.1
4h PRM_IRQSTATUS_MPU This register provides status on MPU interrupt events. Section 8.1.13.1.2
An event is logged whether interrupt generation for the
event is enabled or not.
SW is required to clear a set bit by writing a '1' into the
bit-position to be cleared.
8h PRM_IRQENABLE_MPU This register is used to enable and disable events used Section 8.1.13.1.3
to trigger MPU interrupt activation.
Ch PRM_IRQSTATUS_M3 This register provides status on MPU interrupt events. Section 8.1.13.1.4
An event is logged whether interrupt generation for the
event is enabled or not.
SW is required to clear a set bit by writing a '1' into the
bit-position to be cleared.
10h PRM_IRQENABLE_M3 This register is used to enable and disable events used Section 8.1.13.1.5
to trigger MPU interrupt activation.
8.1.13.1.1 REVISION_PRM Register (offset = 0h) [reset = 0h]

REVISION_PRM is shown in Figure 8-166 and described in Table 8-177.
This register contains the IP revision code for the PRCM
Figure 8-166. REVISION_PRM Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Rev
R-0h
Table 8-177. REVISION_PRM Register Field Descriptions

31-8 Reserved R 0h Reads returns 0.
7-0 Rev R 0h IP revision [
7:4] Major revision [
3:0] Minor revision Examples: 0x10 for 1.0, 0x21 for 2.1
8.1.13.1.2 PRM_IRQSTATUS_MPU Register (offset = 4h) [reset = 0h]

PRM_IRQSTATUS_MPU is shown in Figure 8-167 and described in Table 8-178.
This register provides status on MPU interrupt events. An event is logged whether interrupt generation for
the event is enabled or not. SW is required to clear a set bit by writing a '1' into the bit-position to be
cleared.
Figure 8-167. PRM_IRQSTATUS_MPU Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
dpll_per_recal_ dpll_ddr_recal_ dpll_disp_recal dpll_core_recal dpll_mpu_recal ForceWkup_st Reserved Transition_st
st st _st _st _st
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved
R-0h
Table 8-178. PRM_IRQSTATUS_MPU Register Field Descriptions

31-16 Reserved R 0h
15 dpll_per_recal_st R/W 0h interrupt status for usb dpll recaliberation
0 = DIS : Disables dpll recaliberation
1 = EN : ENAbles dpll recaliberation
14 dpll_ddr_recal_st R/W 0h interrupt status for ddr dpll recaliberation
13 dpll_disp_recal_st R/W 0h interrupt status for disp dpll recaliberation
12 dpll_core_recal_st R/W 0h interrupt status for core dpll recaliberation
11 dpll_mpu_recal_st R/W 0h interrupt status for mpu dpll recaliberation
10 ForceWkup_st R/W 0h Software supervised wakeup completed event interrupt status
0 = IRQ_fal : No interrupt
1 = IRQ_tru : Interrupt is pending
9 Reserved R 0h
8 Transition_st R/W 0h Software supervised transition completed event interrupt status (any
domain)
7-0 Reserved R 0h
8.1.13.1.3 PRM_IRQENABLE_MPU Register (offset = 8h) [reset = 0h]

PRM_IRQENABLE_MPU is shown in Figure 8-168 and described in Table 8-179.
This register is used to enable and disable events used to trigger MPU interrupt activation.
Figure 8-168. PRM_IRQENABLE_MPU Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
dpll_disp_recal dpll_ddr_recal_ dpll_per_recal_ dpll_core_recal dpll_mpu_recal ForceWkup_en Reserved Transition_en
_en en en _en _en
7 6 5 4 3 2 1 0
Reserved Reserved Reserved
R-0h R-0h R-0h
Table 8-179. PRM_IRQENABLE_MPU Register Field Descriptions

31-16 Reserved R 0h
15 dpll_disp_recal_en R/W 0h Interrupt enable for disp dpll recaliberation
14 dpll_ddr_recal_en R/W 0h Interrupt enable for ddr dpll recaliberation
13 dpll_per_recal_en R/W 0h Interrupt enable for usb dpll recaliberation
12 dpll_core_recal_en R/W 0h Interrupt enable for core dpll recaliberation
11 dpll_mpu_recal_en R/W 0h Interrupt enable for mpu dpll recaliberation
10 ForceWkup_en R/W 0h Software supervised Froce Wakeup completed event interrupt
enable
0 = irq_msk : Interrupt is masked
1 = irq_en : Interrupt is enabled
9 Reserved R 0h
8 Transition_en R/W 0h Software supervised transition completed event interrupt enable (any
domain)
7-6 Reserved R 0h
5-1 Reserved R 0h
0 Reserved R 0h
8.1.13.1.4 PRM_IRQSTATUS_M3 Register (offset = Ch) [reset = 0h]

PRM_IRQSTATUS_M3 is shown in Figure 8-169 and described in Table 8-180.
This register provides status on MPU interrupt events. An event is logged whether interrupt generation for
the event is enabled or not. SW is required to clear a set bit by writing a '1' into the bit-position to be
cleared.
Figure 8-169. PRM_IRQSTATUS_M3 Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
dpll_per_recal_ dpll_ddr_recal_ dpll_disp_recal dpll_core_recal dpll_mpu_recal ForceWkup_st Reserved Transition_st
st st _st _st _st
7 6 5 4 3 2 1 0
Reserved
R-0h
Table 8-180. PRM_IRQSTATUS_M3 Register Field Descriptions

31-16 Reserved R 0h
15 dpll_per_recal_st R/W 0h interrupt status for usb dpll recaliberation
14 dpll_ddr_recal_st R/W 0h interrupt status for ddr dpll recaliberation
13 dpll_disp_recal_st R/W 0h interrupt status for disp dpll recaliberation
12 dpll_core_recal_st R/W 0h interrupt status for core dpll recaliberation
11 dpll_mpu_recal_st R/W 0h interrupt status for mpu dpll recaliberation
10 ForceWkup_st R/W 0h Software supervised wakeup completed event interrupt status
9 Reserved R 0h
8 Transition_st R/W 0h Software supervised transition completed event interrupt status (any
domain)
7-0 Reserved R 0h
8.1.13.1.5 PRM_IRQENABLE_M3 Register (offset = 10h) [reset = 0h]

PRM_IRQENABLE_M3 is shown in Figure 8-170 and described in Table 8-181.
This register is used to enable and disable events used to trigger MPU interrupt activation.
Figure 8-170. PRM_IRQENABLE_M3 Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
dpll_disp_recal dpll_ddr_recal_ dpll_per_recal_ dpll_core_recal dpll_mpu_recal ForceWkup_en Reserved Transition_en
_en en en _en _en
7 6 5 4 3 2 1 0
Reserved Reserved Reserved
R-0h R-0h R-0h
Table 8-181. PRM_IRQENABLE_M3 Register Field Descriptions

31-16 Reserved R 0h
15 dpll_disp_recal_en R/W 0h Interrupt enable for disp dpll recaliberation
14 dpll_ddr_recal_en R/W 0h Interrupt enable for ddr dpll recaliberation
13 dpll_per_recal_en R/W 0h Interrupt enable for usb dpll recaliberation
12 dpll_core_recal_en R/W 0h Interrupt enable for core dpll recaliberation
11 dpll_mpu_recal_en R/W 0h Interrupt enable for mpu dpll recaliberation
10 ForceWkup_en R/W 0h Software supervised Froce Wakeup completed event interrupt
enable
9 Reserved R 0h
8 Transition_en R/W 0h Software supervised transition completed event interrupt enable (any
domain)
7-6 Reserved R 0h
5-1 Reserved R 0h
0 Reserved R 0h
8.1.13.2 PRM_PER Registers

Table 8-182 lists the memory-mapped registers for the PRM_PER. All register offset addresses not listed
modified.
Table 8-182. PRM_PER REGISTERS

0h RM_PER_RSTCTRL This register controls the release of the PER Domain Section 8.1.13.2.1
resets.
8h PM_PER_PWRSTST This register provides a status on the current PER power Section 8.1.13.2.2
domain state.
Ch PM_PER_PWRSTCTRL Controls the power state of PER power domain Section 8.1.13.2.3
8.1.13.2.1 RM_PER_RSTCTRL Register (offset = 0h) [reset = 2h]

RM_PER_RSTCTRL is shown in Figure 8-171 and described in Table 8-183.
This register controls the release of the PER Domain resets.
Figure 8-171. RM_PER_RSTCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved Reserved Reserved PRU_ICSS_LR Reserved
ST
R-0h R-0h R-0h R/W-1h R-0h
Table 8-183. RM_PER_RSTCTRL Register Field Descriptions

31-6 Reserved R 0h
5-3 Reserved R 0h
2 Reserved R 0h
1 PRU_ICSS_LRST R/W 1h PER domain PRU-ICSS local reset control
0x0 = CLEAR : Reset is cleared for the PRU-ICSS
0x1 = ASSERT : Reset is asserted for the PRU-ICSS
0 Reserved R 0h
8.1.13.2.2 PM_PER_PWRSTST Register (offset = 8h) [reset = 1E60007h]

PM_PER_PWRSTST is shown in Figure 8-172 and described in Table 8-184.
This register provides a status on the current PER power domain state. [warm reset insensitive]
Figure 8-172. PM_PER_PWRSTST Register

31 30 29 28 27 26 25 24
Reserved pru_icss_mem_
statest
R-0h R-3h
23 22 21 20 19 18 17 16
pru_icss_mem_ ram_mem_statest InTransition Reserved PER_mem_statest Reserved
statest
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved LogicStateSt PowerStateSt
R-0h R-1h R-3h
Table 8-184. PM_PER_PWRSTST Register Field Descriptions

31-25 Reserved R 0h
24-23 pru_icss_mem_statest R 3h PRU-ICSS memory state status
0x0 = Mem_off : Memory is OFF
0x1= Memory is in RETENTION
0x2 = Reserved : Reserved
0x3 = Mem_on : Memory is ON
22-21 ram_mem_statest R 3h OCMC RAM memory state status
20 InTransition R 0h Domain transition status
0x0 = No : No on-going transition on power domain
0x1 = Ongoing : Power domain transition is in progress.
19 Reserved R 0h
18-17 PER_mem_statest R 3h PER domain memory state status
16-3 Reserved R 0h
2 LogicStateSt R 1h Logic state status
0x0 = OFF : Logic in domain is OFF
0x1 = ON : Logic in domain is ON
Table 8-184. PM_PER_PWRSTST Register Field Descriptions (continued)

1-0 PowerStateSt R 3h Current Power State Status
0x0 = OFF : OFF State
0x1 = RET
0x2 = Reserved1
0x3 = ON : ON State
8.1.13.2.3 PM_PER_PWRSTCTRL Register (offset = Ch) [reset = EE0000EBh]

PM_PER_PWRSTCTRL is shown in Figure 8-173 and described in Table 8-185.
Controls the power state of PER power domain
Figure 8-173. PM_PER_PWRSTCTRL Register

31 30 29 28 27 26 25 24
ram_mem_ONState PER_mem_RE Reserved ram_mem_RET PER_mem_ONState Reserved
TState State
R/W-3h R/W-1h R-0h R/W-1h R/W-3h R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
pru_icss_mem_ pru_icss_mem_ONState LowPowerState LogicRETState Reserved PowerState
RETState Change
R/W-1h R/W-3h R/W-0h R/W-1h R-0h R/W-3h
Table 8-185. PM_PER_PWRSTCTRL Register Field Descriptions

31-30 ram_mem_ONState R/W 3h OCMC RAM memory on state
0x0 = OFF : Memory is OFF
0x1 = RET : Memory is in retention state
0x2 = RESERVED
0x3 = ON : Memory is ON
29 PER_mem_RETState R/W 1h Other memories in PER Domain RET state
0x0 = OFF
0x1 = RET
28 Reserved R 0h
27 ram_mem_RETState R/W 1h OCMC RAM memory RET state
0x0 = OFF : Memory is in off state
26-25 PER_mem_ONState R/W 3h Other memories in PER Domain ON state
0x0 = Reserved2
0x1 = Reserved1
24-8 Reserved R 0h
7 pru_icss_mem_RETState R/W 1h PRU-ICSS memory RET state
0x0 = OFF : Memory is in off state
6-5 pru_icss_mem_ONState R/W 3h PRU-ICSS memory ON state
0x0 = Reserved2
0x1 = Reserved1
Table 8-185. PM_PER_PWRSTCTRL Register Field Descriptions (continued)

4 LowPowerStateChange R/W 0h Power state change request when domain has already performed a
sleep transition.
Allows going into deeper low power state without waking up the
power domain.
0x0 = DIS : Do not request a low power state change.
0x1 = EN : Request a low power state change. This bit is
automatically cleared when the power state is effectively changed or
when power state is ON.
3 LogicRETState R/W 1h Logic state when power domain is RETENTION
0x0 = logic_off : Only retention registers are retained and remaing
logic is off when the domain is in RETENTION state.
0x1 = logic_ret : Whole logic is retained when domain is in
RETENTION state.
2 Reserved R 0h
1-0 PowerState R/W 3h PER domain power state control
0x0 = OFF
0x1 = RET
0x2 = Reserved
0x3 = ON
8.1.13.3 PRM_WKUP Registers

Table 8-186 lists the memory-mapped registers for the PRM_WKUP. All register offset addresses not
modified.
Table 8-186. PRM_WKUP REGISTERS

0h RM_WKUP_RSTCTRL This register controls the release of the ALWAYS ON Section 8.1.13.3.1
Domain resets.
4h PM_WKUP_PWRSTCTRL Controls power state of WKUP power domain Section 8.1.13.3.2
8h PM_WKUP_PWRSTST This register provides a status on the current WKUP Section 8.1.13.3.3
power domain state.
Ch RM_WKUP_RSTST This register logs the different reset sources of the Section 8.1.13.3.4
ALWON domain.
Each bit is set upon release of the domain reset signal.
Must be cleared by software.
8.1.13.3.1 RM_WKUP_RSTCTRL Register (offset = 0h) [reset = 8h]

RM_WKUP_RSTCTRL is shown in Figure 8-174 and described in Table 8-187.
This register controls the release of the ALWAYS ON Domain resets.
Figure 8-174. RM_WKUP_RSTCTRL Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved Reserved WKUP_M3_LR Reserved
ST
R-0h R-0h R/W-1h R-0h
Table 8-187. RM_WKUP_RSTCTRL Register Field Descriptions

31-6 Reserved R 0h
5-4 Reserved R 0h
3 WKUP_M3_LRST R/W 1h Assert Reset to WKUP_M3
0x0 = CLEAR : Reset is cleared for the M3
0x1 = ASSERT : Reset is asserted for the M3 by A8
2-0 Reserved R 0h
8.1.13.3.2 PM_WKUP_PWRSTCTRL Register (offset = 4h) [reset = 8h]

PM_WKUP_PWRSTCTRL is shown in Figure 8-175 and described in Table 8-188.
Controls power state of WKUP power domain
Figure 8-175. PM_WKUP_PWRSTCTRL Register

31 30 29 28 27 26 25 24
Reserved Reserved Reserved Reserved Reserved Reserved
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved LowPowerState LogicRETState Reserved Reserved
Change
R-0h R/W-0h R/W-1h R-0h R-0h
Table 8-188. PM_WKUP_PWRSTCTRL Register Field Descriptions

31-30 Reserved R 0h
29 Reserved R 0h
28 Reserved R 0h
27 Reserved R 0h
26-25 Reserved R 0h
24-5 Reserved R 0h
sleep transition.
power domain.
RETENTION state.
2 Reserved R 0h
1-0 Reserved R 0h
8.1.13.3.3 PM_WKUP_PWRSTST Register (offset = 8h) [reset = 60004h]

PM_WKUP_PWRSTST is shown in Figure 8-176 and described in Table 8-189.
This register provides a status on the current WKUP power domain state. [warm reset insensitive]
Figure 8-176. PM_WKUP_PWRSTST Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved Reserved InTransition Reserved Debugss_mem_statest Reserved
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved LogicStateSt Reserved
R-0h R-1h R-0h
Table 8-189. PM_WKUP_PWRSTST Register Field Descriptions

31-23 Reserved R 0h
22-21 Reserved R 0h
19 Reserved R 0h
18-17 Debugss_mem_statest R 3h WKUP domain memory state status
16-3 Reserved R 0h
1-0 Reserved R 0h
8.1.13.3.4 RM_WKUP_RSTST Register (offset = Ch) [reset = 0h]

RM_WKUP_RSTST is shown in Figure 8-177 and described in Table 8-190.
This register logs the different reset sources of the ALWON domain. Each bit is set upon release of the
domain reset signal. Must be cleared by software. [warm reset insensitive]
Figure 8-177. RM_WKUP_RSTST Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
ICECRUSHER EMULATION_ WKUP_M3_LR Reserved
_M3_RST M3_RST ST
R/W-0h R/W-0h R/W-0h R-0h
Table 8-190. RM_WKUP_RSTST Register Field Descriptions

31-8 Reserved R 0h
7 ICECRUSHER_M3_RST R/W 0h M3 Processor has been reset due to M3 ICECRUSHER1 reset event
0x0 = RESET_NO : No reset
0x1 = RESET_YES : M3 Processor has been reset
6 EMULATION_M3_RST R/W 0h M3 Processor has been reset due to emulation reset source e.g.
assert reset command initiated by the icepick module
5 WKUP_M3_LRST R/W 0h M3 Processor has been reset
4-0 Reserved R 0h
8.1.13.4 PRM_MPU Registers

Table 8-191 lists the memory-mapped registers for the PRM_MPU. All register offset addresses not listed
modified.
Table 8-191. PRM_MPU REGISTERS

0h PM_MPU_PWRSTCTRL This register controls the MPU power state to reach Section 8.1.13.4.1
upon mpu domain sleep transition
4h PM_MPU_PWRSTST This register provides a status on the current MPU Section 8.1.13.4.2
power domain state0.
Table 8-191. PRM_MPU REGISTERS (continued)

8h RM_MPU_RSTST This register logs the different reset sources of the Section 8.1.13.4.3
ALWON domain.
Each bit is set upon release of the domain reset signal.
Must be cleared by software.
8.1.13.4.1 PM_MPU_PWRSTCTRL Register (offset = 0h) [reset = 1FF0007h]

PM_MPU_PWRSTCTRL is shown in Figure 8-178 and described in Table 8-192.
This register controls the MPU power state to reach upon mpu domain sleep transition
Figure 8-178. PM_MPU_PWRSTCTRL Register

31 30 29 28 27 26 25 24
Reserved Reserved mpu_ram_RET
State
R-0h R-0h R/W-1h
23 22 21 20 19 18 17 16
mpu_l2_RETSt mpu_l1_RETSt MPU_L2_ONState MPU_L1_ONState MPU_RAM_ONState
ate ate
R/W-1h R/W-1h R-3h R-3h R/W-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved LowPowerState Reserved LogicRETState PowerState
Change
Table 8-192. PM_MPU_PWRSTCTRL Register Field Descriptions

31-26 Reserved R 0h
25 Reserved R 0h
24 mpu_ram_RETState R/W 1h Default power domain memory(ram) retention state when power
domain is in retention
23 mpu_l2_RETState R/W 1h Default power domain memory(L2) retention state when power
22 mpu_l1_RETState R/W 1h Default power domain memory(L1) retention state when power
21-20 MPU_L2_ONState R 3h Default power domain memory state when domain is ON.
19-18 MPU_L1_ONState R 3h Default power domain memory state when domain is ON.
17-16 MPU_RAM_ONState R/W 3h Default power domain memory state when domain is ON.
0x0 = Mem_off
0x2 = Reserved
0x3 = Mem_on : Memory bank is on when the domain is ON.
15-5 Reserved R 0h
sleep transition.
power domain.
3 Reserved R 0h
RETENTION state.
Table 8-192. PM_MPU_PWRSTCTRL Register Field Descriptions (continued)

1-0 PowerState R/W 3h Power state control
0x0 = OFF : OFF State
0x1 = RET
0x2 = Reserved
0x3 = ON : ON State
8.1.13.4.2 PM_MPU_PWRSTST Register (offset = 4h) [reset = 157h]

PM_MPU_PWRSTST is shown in Figure 8-179 and described in Table 8-193.
This register provides a status on the current MPU power domain state0. [warm reset insensitive]
Figure 8-179. PM_MPU_PWRSTST Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved InTransition Reserved
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
Reserved MPU_L2_StateSt
R-0h R-1h
7 6 5 4 3 2 1 0
MPU_L1_StateSt MPU_RAM_StateSt Reserved LogicStateSt PowerStateSt
Table 8-193. PM_MPU_PWRSTST Register Field Descriptions

31-21 Reserved R 0h
19-10 Reserved R 0h
9-8 MPU_L2_StateSt R 1h MPU L2 memory state status
7-6 MPU_L1_StateSt R 1h MPU L1 memory state status
5-4 MPU_RAM_StateSt R 1h MPU_RAM memory state status
3 Reserved R 0h
1-0 PowerStateSt R 3h Current Power State Status
0x0 = OFF : OFF State [warm reset insensitive]
0x1 = RET : RET State
0x3 = ON : ON State [warm reset insensitive]
8.1.13.4.3 RM_MPU_RSTST Register (offset = 8h) [reset = 0h]

RM_MPU_RSTST is shown in Figure 8-180 and described in Table 8-194.
This register logs the different reset sources of the ALWON domain. Each bit is set upon release of the
domain reset signal. Must be cleared by software. [warm reset insensitive]
Figure 8-180. RM_MPU_RSTST Register

31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved Reserved
R-0h R-0h
7 6 5 4 3 2 1 0
Reserved ICECRUSHER EMULATION_ Reserved Reserved Reserved Reserved
_MPU_RST MPU_RST
R-0h R/W-0h R/W-0h R-0h R-0h R-0h R-0h
Table 8-194. RM_MPU_RSTST Register Field Descriptions

31-15 Reserved R 0h
14-8 Reserved R 0h
7 Reserved R 0h
6 ICECRUSHER_MPU_RS R/W 0h MPU Processor has been reset due to MPU ICECRUSHER1 reset
T event
0x0 = RESET_NO : No icecrusher reset
0x1 = RESET_YES : MPU Processor has been reset upon
icecursher reset
5 EMULATION_MPU_RST R/W 0h MPU Processor has been reset due to emulation reset source e.g.
assert reset command initiated by the icepick module
0x0 = RESET_NO : No emulation reset
0x1 = RESET_YES : MPU Processor has been reset upon emulation
reset
4 Reserved R 0h
3 Reserved R 0h
2 Reserved R 0h
1-0 Reserved R 0h
8.1.13.5 PRM_DEVICE Registers

Table 8-195 lists the memory-mapped registers for the PRM_DEVICE. All register offset addresses not
modified.
Table 8-195. PRM_DEVICE Registers

0h PRM_RSTCTRL Section 8.1.13.5.1
4h PRM_RSTTIME Section 8.1.13.5.2
8h PRM_RSTST Section 8.1.13.5.3
Table 8-195. PRM_DEVICE Registers (continued)

Ch PRM_SRAM_COUNT Section 8.1.13.5.4
10h PRM_LDO_SRAM_CORE_SETUP Section 8.1.13.5.5
14h PRM_LDO_SRAM_CORE_CTRL Section 8.1.13.5.6
18h PRM_LDO_SRAM_MPU_SETUP Section 8.1.13.5.7
1Ch PRM_LDO_SRAM_MPU_CTRL Section 8.1.13.5.8
8.1.13.5.1 PRM_RSTCTRL Register (offset = 0h) [reset = 0h]

PRM_RSTCTRL is shown in Figure 8-181 and described in Table 8-196.
Global software cold and warm reset control. This register is auto-cleared. Only write 1 is possible. A read
returns 0 only.
Figure 8-181. PRM_RSTCTRL Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED
Rreturns0s-0h
7 6 5 4 3 2 1 0
RESERVED RST_GLOBAL_ RST_GLOBAL_
COLD_SW WARM_SW
Rreturns0s-0h Rreturns0s/W- Rreturns0s/W-
0h 0h
Table 8-196. PRM_RSTCTRL Register Field Descriptions

1 RST_GLOBAL_COLD_S Rreturns0s/ 0h Global COLD software reset control.
W W This bit is reset only upon a global cold source of reset.
Read returns 0.
0h = 0x0 : Global COLD software reset is cleared.
1h = 0x1 : Asserts a global COLD software reset. The software must
ensure the SDRAM is properly put in sef-refresh mode before
applying this reset.
0 RST_GLOBAL_WARM_S Rreturns0s/ 0h Global WARM software reset control.
W W This bit is reset upon any global source of reset (warm and cold).
Read returns 0.
0h = 0x0 : Global warm software reset is cleared.
1h = 0x1 : Asserts a global warm software reset.
8.1.13.5.2 PRM_RSTTIME Register (offset = 4h) [reset = 1006h]

PRM_RSTTIME is shown in Figure 8-182 and described in Table 8-197.
Reset duration control. [warm reset insensitive]
Figure 8-182. PRM_RSTTIME Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RSTTIME2 RSTTIME1
Table 8-197. PRM_RSTTIME Register Field Descriptions

12-8 RSTTIME2 R/W 10h (Power domain) reset duration 2 (number of CLK_M_OSC clock
cycles)
7-0 RSTTIME1 R/W 6h (Global) reset duration 1 (number of CLK_M_OSC clock cycles)
8.1.13.5.3 PRM_RSTST Register (offset = 8h) [reset = 1h]

PRM_RSTST is shown in Figure 8-183 and described in Table 8-198.
This register logs the global reset sources. Each bit is set upon release of the domain reset signal. Must
be cleared by software. [warm reset insensitive]
Figure 8-183. PRM_RSTST Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED ICEPICK_RST RESERVED
Rreturns0s-0h R/W1toClr-0h Rreturns0s-0h
7 6 5 4 3 2 1 0
RESERVED EXTERNAL_W WDT1_RST RESERVED RESERVED GLOBAL_WAR GLOBAL_COL
ARM_RST M_SW_RST D_RST
Rreturns0s-0h R/W1toClr-0h R/W1toClr-0h R/W1toClr-0h R/W1toClr-0h R/W1toClr-0h R/W1toClr-1h
Table 8-198. PRM_RSTST Register Field Descriptions

9 ICEPICK_RST R/W1toClr 0h IcePick reset event.
This is a source of global warm reset initiated by the emulation.
0h = 0x0 : No ICEPICK reset.
1h = 0x1 : IcePick reset has occurred.
5 EXTERNAL_WARM_RST R/W1toClr 0h External warm reset event [warm reset insensitive]
0h = 0x0 : No global warm reset.
1h = 0x1 : Global external warm reset has occurred.
4 WDT1_RST R/W1toClr 0h Watchdog1 timer reset event.
This is a source of global WARM reset.
0h = 0x0 : No watchdog reset.
1h = 0x1 : watchdog reset has occurred.
3 RESERVED R/W1toClr 0h Reserved.
2 RESERVED R/W1toClr 0h Reserved.
1 GLOBAL_WARM_SW_RS R/W1toClr 0h Global warm software reset event [warm reset insensitive]
T
0h = 0x0 : No global warm SW reset
1h = 0x1 : Global warm SW reset has occurred.
0 GLOBAL_COLD_RST R/W1toClr 1h Power-on (cold) reset event [warm reset insensitive]
0h = 0x0 : No power-on reset.
1h = 0x1 : Power-on reset has occurred.
8.1.13.5.4 PRM_SRAM_COUNT Register (offset = Ch) [reset = 78000017h]

PRM_SRAM_COUNT is shown in Figure 8-184 and described in Table 8-199.
Common setup for SRAM LDO transition counters. Applies to all voltage domains. [warm reset insensitive]
Figure 8-184. PRM_SRAM_COUNT Register

31 30 29 28 27 26 25 24
StartUp_Count
R/W-78h
23 22 21 20 19 18 17 16
SLPCNT_VALUE
R/W-0h
15 14 13 12 11 10 9 8
VSETUPCNT_VALUE
R/W-0h
7 6 5 4 3 2 1 0
RESERVED PCHARGECNT_VALUE
Table 8-199. PRM_SRAM_COUNT Register Field Descriptions

31-24 StartUp_Count R/W 78h Determines the start-up duration of SRAM and ABB LDO.
The duration is computed as 16 x NbCycles of system clock cycles.
Target is 50us.
23-16 SLPCNT_VALUE R/W 0h Delay between retention/off assertion of last SRAM bank and
SRAMALLRET signal to LDO is driven high.
Counting on system clock.
Target is 2us.
15-8 VSETUPCNT_VALUE R/W 0h SRAM LDO rampup time from retention to active mode.
The duration is computed as 8 x NbCycles of system clock cycles.
Target is 30us.
5-0 PCHARGECNT_VALUE R/W 17h Delay between de-assertion of standby_rta_ret_on and
standby_rta_ret_good.
Counting on system clock.
Target is 600ns.
8.1.13.5.5 PRM_LDO_SRAM_CORE_SETUP Register (offset = 10h) [reset = 0h]

PRM_LDO_SRAM_CORE_SETUP is shown in Figure 8-185 and described in Table 8-200.
Setup of the SRAM LDO for CORE voltage domain. [warm reset insensitive]
Figure 8-185. PRM_LDO_SRAM_CORE_SETUP Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED AIPOFF
7 6 5 4 3 2 1 0
ENFUNC5 ENFUNC4 ENFUNC3_EX ENFUNC2_EX ENFUNC1_EX ABBOFF_SLEE ABBOFF_ACT_ DISABLE_RTA
PORT PORT PORT P_EXPORT EXPORT _EXPORT
R/W-0h R/W-0h R/WSpecial-0h R/WSpecial-0h R/WSpecial-0h R/WSpecial-0h R/WSpecial-0h R/WSpecial-0h
Table 8-200. PRM_LDO_SRAM_CORE_SETUP Register Field Descriptions

8 AIPOFF R/W 0h Override on AIPOFF input of SRAM LDO.
0h = No_Override : AIPOFF signal is not overriden
1h = Override : AIPOFF signal is overriden to '1'. Corresponding
SRAM LDO is disabled and in HZ mode.
7 ENFUNC5 R/W 0h ENFUNC5 input of SRAM LDO.
0h = One_step : Active to retention is a one step transfer
1h = Two_step : Active to retention is a two steps transfer
6 ENFUNC4 R/W 0h ENFUNC4 input of SRAM LDO.
0h = Ext_clock : One external clock is supplied
1h = No_ext_clock : No external clock is supplied
5 ENFUNC3_EXPORT R/WSpecial 0h ENFUNC3 input of SRAM LDO.
After PowerOn reset and Efuse sensing, this bitfield is automatically
loaded with an Efuse value from control module.
Bitfield remains writable after this.
0h = Sub_regul_disabled : Sub regulation is disabled
1h = Sub_regul_enabled : Sub regulation is enabled
0h = Ext_cap : External cap is used
1h = No_ext_cap : External cap is not used
0h = Short_prot_disabled : Short circuit protection is disabled
1h = Short_prot_enabled : Short circuit protection is enabled
Table 8-200. PRM_LDO_SRAM_CORE_SETUP Register Field Descriptions (continued)

2 ABBOFF_SLEEP_EXPOR R/WSpecial 0h Determines whether SRAMNWA is supplied by VDDS or VDDAR
T during deep-sleep.
0h = SRAMNW_SLP_VDDS : SRAMNWA supplied with VDDS
1h(Read) = SRAMNW_SLP_VDDASRAMNWA supplied with
VDDAR
1 ABBOFF_ACT_EXPORT R/WSpecial 0h Determines whether SRAMNWA is supplied by VDDS or VDDAR
during active mode.
0h = SRAMNW_ACT_VDDS : SRAMNWA supplied with VDDS
1h(Read) = SRAMNW_ACT_VDDASRAMNWA supplied with
VDDAR
0 DISABLE_RTA_EXPORT R/WSpecial 0h Control for HD memory RTA feature.
0h = RTA_ENABLED : HD memory RTA feature is enabled
1h = RTA_DISABLED : HD memory RTA feature is disabled
8.1.13.5.6 PRM_LDO_SRAM_CORE_CTRL Register (offset = 14h) [reset = 0h]

PRM_LDO_SRAM_CORE_CTRL is shown in Figure 8-186 and described in Table 8-201.
Control and status of the SRAM LDO for CORE voltage domain. [warm reset insensitive]
Figure 8-186. PRM_LDO_SRAM_CORE_CTRL Register

31 30 29 28 27 26 25 24
RESERVED
Rreturns0s-0h
23 22 21 20 19 18 17 16
RESERVED
Rreturns0s-0h
15 14 13 12 11 10 9 8
RESERVED SRAM_IN_TRA SRAMLDO_ST
NSITION ATUS
Rreturns0s-0h R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED RETMODE_EN
ABLE
Table 8-201. PRM_LDO_SRAM_CORE_CTRL Register Field Descriptions

9 SRAM_IN_TRANSITION R 0h Status indicating SRAM LDO state machine state.
0h = IDLE : SRAM LDO state machine is stable
1h = IN_TRANSITION : SRAM LDO state machine is in transition
state
8 SRAMLDO_STATUS R 0h

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AM335x and AMIC110 Sitara™ Processors

Technical Reference Manual

Literature Number: SPRUH73Q

Preface ..................................................................................................................................... 173

2 Contents SPRUH73Q – October 2011 – Revised December 2019

4.4.3 Industrial Ethernet Peripheral (IEP) ........................................................................... 233

SPRUH73Q – October 2011 – Revised December 2019 Contents 3

7.2.1 Introduction ....................................................................................................... 900

4 Contents SPRUH73Q – October 2011 – Revised December 2019

11.2.2 Third-Party Transfer Controller (TPTC) Integration ....................................................... 1572

SPRUH73Q – October 2011 – Revised December 2019 Contents 5

13.2 Integration ................................................................................................................ 1927

6 Contents SPRUH73Q – October 2011 – Revised December 2019

14.5.1 CPSW_ALE Registers ........................................................................................ 2078

SPRUH73Q – October 2011 – Revised December 2019 Contents 7

16.4.3 USB1_CTRL Registers ....................................................................................... 2725

8 Contents SPRUH73Q – October 2011 – Revised December 2019

19.3 Functional Description .................................................................................................. 4325

SPRUH73Q – October 2011 – Revised December 2019 Contents 9

10 Contents SPRUH73Q – October 2011 – Revised December 2019

23.3.5 Registers and Message Object Access .................................................................... 4777

SPRUH73Q – October 2011 – Revised December 2019 Contents 11

25.3.4 General-Purpose Interface Basic Programming Model .................................................. 4985

12 Contents SPRUH73Q – October 2011 – Revised December 2019

SPRUH73Q – October 2011 – Revised December 2019 List of Figures 13

4-43. RX Error Detection........................................................................................................ 260

14 List of Figures SPRUH73Q – October 2011 – Revised December 2019

4-92. GPREG27 Register ....................................................................................................... 313

SPRUH73Q – October 2011 – Revised December 2019 List of Figures 15

4-141. SRSR1 Register .......................................................................................................... 363

16 List of Figures SPRUH73Q – October 2011 – Revised December 2019

4-190. HINLR9 Register .......................................................................................................... 412

SPRUH73Q – October 2011 – Revised December 2019 List of Figures 17

4-239. IEP_DIGIO_EXP Register ............................................................................................... 464

18 List of Figures SPRUH73Q – October 2011 – Revised December 2019

6-2. IRQ/FIQ Processing Sequence ......................................................................................... 537

SPRUH73Q – October 2011 – Revised December 2019 List of Figures 19

7-4. GPMC to 16-Bit Non-multiplexed Memory ............................................................................ 605

20 List of Figures SPRUH73Q – October 2011 – Revised December 2019

7-51. GPMC_IRQENABLE Register .......................................................................................... 711

SPRUH73Q – October 2011 – Revised December 2019 List of Figures 21

7-100. GPMC_CONFIG4_4 Register ........................................................................................... 779

22 List of Figures SPRUH73Q – October 2011 – Revised December 2019

7-149. GPMC_BCH_RESULT2_1 Register ................................................................................... 849

SPRUH73Q – October 2011 – Revised December 2019 List of Figures 23

7-198. GPMC_BCH_RESULT5_7 Register ................................................................................... 898

24 List of Figures SPRUH73Q – October 2011 – Revised December 2019

SPRUH73Q – October 2011 – Revised December 2019 List of Figures 25

7-289. ELM_SYNDROME_FRAGMENT_5_3 Register ..................................................................... 1031

26 List of Figures SPRUH73Q – October 2011 – Revised December 2019

7-338. ELM_ERROR_LOCATION_1_1 Register ............................................................................ 1080

SPRUH73Q – October 2011 – Revised December 2019 List of Figures 27

7-387. ELM_ERROR_LOCATION_0_4 Register ............................................................................ 1129

28 List of Figures SPRUH73Q – October 2011 – Revised December 2019

7-436. ELM_ERROR_LOCATION_0_7 Register ............................................................................ 1178

SPRUH73Q – October 2011 – Revised December 2019 List of Figures 29

8-31. CM_PER_CPGMAC0_CLKCTRL Register .......................................................................... 1259

30 List of Figures SPRUH73Q – October 2011 – Revised December 2019

8-80. CM_PER_OCPWP_CLKCTRL Register ............................................................................. 1308