ATtiny25-45-85 (Doc2586)
ATtiny25-45-85 (Doc2586)
ATtiny25-45-85 (Doc2586)
PDIP/SOIC/TSSOP
QFN/MLF
DNC
DNC
DNC
DNC
DNC
20
19
18
17
16
1.1.1 VCC
Supply voltage.
1.1.2 GND
Ground.
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ATtiny25/45/85
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny25/45/85 as listed in
“Alternate Functions of Port B” on page 62.
On ATtiny25, the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged in
ATtiny15 Compatibility Mode for supporting the backward compatibility with ATtiny15.
1.1.4 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running and provided the reset pin has not been disabled. The min-
imum pulse length is given in Table 21-4 on page 170. Shorter pulses are not guaranteed to
generate a reset.
The reset pin can also be used as a (weak) I/O pin.
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2. Overview
The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
CALIBRATED
INTERNAL
OSCILLATOR
CONTROL UNIVERSAL
LINES ALU SERIAL
INTERFACE
STATUS INTERRUPT
REGISTER UNIT
PROGRAMMING DATA
LOGIC OSCILLATORS
EEPROM
PORT B DRIVERS
RESET
PB[0:5]
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
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ATtiny25/45/85
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATtiny25/45/85 provides the following features: 2/4/8K bytes of In-System Programmable
Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32
general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high
speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel,
10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software select-
able power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter,
ADC, Analog Comparator, and Interrupt system to continue functioning. Power-down mode
saves the register contents, disabling all chip functions until the next Interrupt or Hardware
Reset. ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize
switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits.
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3. About
3.1 Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
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4.1 Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
Program Status
Flash
Counter and Control
Program
Memory
32 x 8
Instruction General
Register Purpose Interrupt
Registrers Unit
Instruction Watchdog
Decoder Timer
Indirect Addressing
Direct Addressing
ALU Analog
Control Lines Comparator
I/O Module1
I/O Module n
EEPROM
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the Program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the Program memory. This concept enables instructions to be executed
in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.
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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash Program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic opera-
tion, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word for-
mat, but there are also 32-bit instructions.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-
tion. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F.
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4.5 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically imple-
mented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
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15 XH XL 0
X-register 7 0 7 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 0 7 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 7 0 7 0
R31 (0x1F) R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
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4.7 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
clkCPU
Total Execution Time
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ATtiny25/45/85
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-
tor in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
cuted before any pending interrupts, as shown in this example.
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5. AVR Memories
This section describes the different memories in the ATtiny25/45/85. The AVR architecture has
two main memory spaces, the Data memory and the Program memory space. In addition, the
ATtiny25/45/85 features an EEPROM Memory for data storage. All three memory spaces are lin-
ear and regular.
0x03FF/0x07FF/0x0FFF
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When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter-
nal data SRAM in the ATtiny25/45/85 are all accessible through all these addressing modes.
The Register File is described in “General Purpose Register File” on page 10.
Data Memory
32 Registers 0x0000 - 0x001F
64 I/O Registers 0x0020 - 0x005F
0x0060
Internal SRAM
(128/256/512 x 8)
0x0DF/0x015F/0x025F
clkCPU
Address Compute Address Address valid
Data
Write
WR
Data
Read
RD
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ATtiny25/45/85
The write access times for the EEPROM are given in Table 5-1 on page 21. A self-timing func-
tion, however, lets the user software detect when the next byte can be written. If the user code
contains instructions that write the EEPROM, some precautions must be taken. In heavily fil-
tered power supplies, VCC is likely to rise or fall slowly on Power-up/down. This causes the
device for some period of time to run at a voltage lower than specified as minimum for the clock
frequency used. See “Preventing EEPROM Corruption” on page 19 for details on how to avoid
problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to “Atomic Byte Programming” on page 17 and “Split Byte Programming” on page 17 for
details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
5.3.4 Erase
To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the
EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (program-
ming time is given in Table 5-1 on page 21). The EEPE bit remains set until the erase operation
completes. While the device is busy programming, it is not possible to do any other EEPROM
operations.
5.3.5 Write
To write a location, the user must write the address into EEAR and the data into EEDR. If the
EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger
the write operation only (programming time is given in Table 5-1 on page 21). The EEPE bit
remains set until the write operation completes. If the location to be written has not been erased
before write, the data that is stored must be considered as lost. While the device is busy with
programming, it is not possible to do any other EEPROM operations.
The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator fre-
quency is within the requirements described in “OSCCAL – Oscillator Calibration Register” on
page 32.
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The following code examples show one assembly and one C function for erase, write, or atomic
write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling
interrupts globally) so that no interrupts will occur during execution of these functions.
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ATtiny25/45/85
The next code examples show assembly and C functions for reading the EEPROM. The exam-
ples assume that interrupts are controlled so that no interrupts will occur during execution of
these functions.
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5.4 I/O Memory
The I/O space definition of the ATtiny25/45/85 is shown in “Register Summary” on page 205.
All ATtiny25/45/85 I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32
general purpose working registers and the I/O space. I/O Registers within the address range
0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the
instruction set section for more details. When using the I/O specific commands IN and OUT, the
I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using
LD and ST instructions, 0x20 must be added to these addresses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers contain-
ing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and Peripherals Control Registers are explained in later sections.
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• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the cor-
rect address is set up in the EEAR Register, the EERE bit must be written to one to trigger the
EEPROM read. The EEPROM read access takes one instruction, and the requested data is
available immediately. When the EEPROM is read, the CPU is halted for four cycles before the
next instruction is executed. The user should poll the EEPE bit before starting the read opera-
tion. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change
the EEAR Register.
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clkPCK
clkADC clkFLASH
Watchdog clock
System Clock
clkPCK
Prescaler
Calibrated
Crystal RC Low-Frequency Calibrated RC
External Clock
Oscillator Crystal Oscillator Oscillator
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6.1.4 ADC Clock – clkADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
LOCK
DETECTOR
PLOCK
1/2
4 MHz
8.0 MHz PCK
OSCILLATOR 8 MHz PLL
8x
1/4
64 / 32 MHz 16 MHz
PRESCALER
XTAL1 8 MHz
SYSTEM
XTAL2 OSCILLATORS CLOCK
The PLL is locked on the RC oscillator and adjusting the RC oscillator via OSCCAL register will
adjust the fast peripheral clock at the same time. However, even if the RC oscillator is taken to a
higher frequency than 8 MHz, the fast peripheral clock frequency saturates at 85 MHz (worst
case) and remains oscillating at the maximum frequency. It should be noted that the PLL in this
case is not locked any longer with the RC oscillator clock. Therefore, it is recommended not to
take the OSCCAL adjustments to a higher frequency than 8 MHz in order to keep the PLL in the
correct operating range.
The internal PLL is enabled when:
• The PLLE bit in the register PLLCSR is set.
• The CKSEL fuse is programmed to ‘0001’.
• The CKSEL fuse is programmed to ‘0011’.
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In the ATtiny15 compatibility mode the frequency of the internal RC oscillator is calibrated down
to 6.4 MHz and the multiplication factor of the PLL is set to 4x. See Figure 6-3. With these
adjustments the clocking system is ATtiny15-compatible and the resulting fast peripheral clock
has a frequency of 25.6 MHz (same as in ATtiny15).
1/4
1.6 MHz
SYSTEM
CLOCK
Note that low speed mode is not implemented in ATtiny15 compatibility mode.
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.
2. The device is shipped with this option selected.
3. This will select ATtiny15 Compatibility Mode, where system clock is divided by four, resulting in
a 1.6 MHz clock frequency. For more inormation, see “Calibrated Internal Oscillator” on page
27.
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down, the selected clock source is used to time the start-up, ensuring sta-
ble Oscillator operation before instruction execution starts. When the CPU starts from reset,
there is an additional delay allowing the power to reach a stable level before commencing nor-
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mal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time.
The number of WDT Oscillator cycles used for each time-out is shown in Table 6-2.
EXTERNAL
CLOCK CLKI
SIGNAL
GND
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table 6-3.
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the
MCU is kept in Reset during such changes in the clock frequency.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page
31 for details.
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ATtiny25/45/85
a system clock source, by programming the CKSEL fuses to ‘0001’, it is divided by four like
shown in Table 6-4.
When this clock source is selected, start-up times are determined by the SUT fuses as shown in
Table 6-5.
Table 6-5. Start-up Times for the High Frequency PLL Clock
Start-up Time from Additional Delay from Recommended
SUT[1:0] Power Down Power-On Reset (VCC = 5.0V) usage
00 14CK + 1K (1024) CK + 4 ms 4 ms BOD enabled
01 14CK + 16K (16384) CK + 4 ms 4 ms Fast rising power
10 14CK + 1K (1024) CK + 64 ms 4 ms Slowly rising power
11 14CK + 16K (16384) CK + 64 ms 4 ms Slowly rising power
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Mode” on page 98). Note that in this mode of operation the 6.4 MHz clock signal is always
divided by four, providing a 1.6 MHz system clock.
When the calibrated 8 MHz internal oscillator is selected as clock source the start-up times are
determined by the SUT Fuses as shown in Table 6-7 below.
Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to
ensure programming mode can be entered.
2. The device is shipped with this option selected.
In ATtiny15 Compatibility Mode start-up times are determined by SUT fuses as shown in Table
6-8 below.
Table 6-8. Start-up Times for Internal Calibrated RC Oscillator Clock (in ATtiny15 Mode)
Start-up Time Additional Delay from
SUT[1:0] from Power-down Reset (VCC = 5.0V) Recommended Usage
00 6 CK 14CK + 64 ms
01 6 CK 14CK + 64 ms
10 6 CK 14CK + 4 ms
11 1 CK 14CK(1)
Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to
ensure programming mode can be entered.
In summary, more information on ATtiny15 Compatibility Mode can be found in sections “Port B
(PB5:PB0)” on page 2, “Internal PLL in ATtiny15 Compatibility Mode” on page 24, “8-bit
Timer/Counter1 in ATtiny15 Mode” on page 98, “Limitations of debugWIRE” on page 144, “Cali-
bration Bytes” on page 154 and in table “Clock Prescaler Select” on page 34.
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Table 6-9. Start-up Times for the 128 kHz Internal Oscillator
Start-up Time from Additional Delay from
SUT[1:0] Power-down Reset Recommended Usage
00 6 CK 14CK(1) BOD enabled
01 6 CK 14CK + 4 ms Fast rising power
10 6 CK 14CK + 64 ms Slowly rising power
11 Reserved
Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to
ensure programming mode can be entered.
Table 6-10. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection
Start-up Time from Additional Delay from
SUT[1:0] Power Down Reset (VCC = 5.0V) Recommended usage
(1)
00 1K (1024) CK 4 ms Fast rising power or BOD enabled
(1)
01 1K (1024) CK 64 ms Slowly rising power
10 32K (32768) CK 64 ms Stable frequency at start-up
11 Reserved
Note: 1. These options should be used only if frequency stability at start-up is not important.
The Low-frequency Crystal Oscillator provides an internal load capacitance, see Table 6-11 at
each TOSC pin.
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6.2.6 Crystal Oscillator / Ceramic Resonator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be con-
figured for use as an On-chip Oscillator, as shown in Figure 6-5. Either a quartz crystal or a
ceramic resonator may be used.
C2
XTAL2
C1
XTAL1
GND
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the
capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the
electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for
use with crystals are given in Table 6-12 below. For ceramic resonators, the capacitor values
given by the manufacturer should be used.
Notes: 1. This option should not be used with crystals, only with ceramic resonators.
The Oscillator can operate in three different modes, each optimized for a specific frequency
range. The operating mode is selected by the fuses CKSEL[3:1] as shown in Table 6-12.
The CKSEL0 Fuse together with the SUT[1:0] Fuses select the start-up times as shown in Table
6-13.
Table 6-13. Start-up Times for the Crystal Oscillator Clock Selection
Start-up Time from Additional Delay
CKSEL0 SUT[1:0] Power-down from Reset Recommended Usage
Ceramic resonator,
0 00 258 CK(1) 14CK + 4 ms
fast rising power
Ceramic resonator,
0 01 258 CK(1) 14CK + 64 ms
slowly rising power
Ceramic resonator,
0 10 1K (1024) CK(2) 14CK
BOD enabled
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Table 6-13. Start-up Times for the Crystal Oscillator Clock Selection (Continued)
Start-up Time from Additional Delay
CKSEL0 SUT[1:0] Power-down from Reset Recommended Usage
Ceramic resonator,
0 11 1K (1024)CK(2) 14CK + 4 ms
fast rising power
Ceramic resonator,
1 00 1K (1024)CK(2) 14CK + 64 ms
slowly rising power
Crystal Oscillator,
1 01 16K (16384) CK 14CK
BOD enabled
Crystal Oscillator,
1 10 16K (16384) CK 14CK + 4 ms
fast rising power
Crystal Oscillator,
1 11 16K (16384) CK 14CK + 64 ms
slowly rising power
Notes: 1. These options should only be used when not operating close to the maximum frequency of the
device, and only if frequency stability at start-up is not important for the application. These
options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability
at start-up. They can also be used with crystals when not operating close to the maximum fre-
quency of the device, and if frequency stability at start-up is not important for the application.
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6.4 Clock Output Buffer
The device can output the system clock on the CLKO pin (when not used as XTAL2 pin). To
enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip
clock is used to drive other circuits on the system. Note that the clock will not be output during
reset and that the normal operation of the I/O pin will be overridden when the fuse is pro-
grammed. Internal RC Oscillator, WDT Oscillator, PLL, and external clock (CLKI) can be
selected when the clock is output on CLKO. Crystal oscillators (XTAL1, XTAL2) can not be used
for clock output on CLKO. If the System Clock Prescaler is used, it is the divided system clock
that is output.
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Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,
the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to
“0011”, giving a division factor of eight at start up. This feature should be used if the selected
clock source has a higher frequency than the maximum frequency of the device at the present
operating conditions. Note that any value can be written to the CLKPS bits regardless of the
CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is
chosen if the selcted clock source has a higher frequency than the maximum frequency of the
33
2586N–AVR–04/11
device at the present operating conditions. The device is shipped with the CKDIV8 Fuse
programmed.
Note: The prescaler is disabled in ATtiny15 compatibility mode and neither writing to CLKPR, nor pro-
gramming the CKDIV8 fuse has any effect on the system clock (which will always be 1.6 MHz).
34 ATtiny25/45/85
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ATtiny25/45/85
Table 7-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Active Clock Domains Oscillators Wake-up Sources
SPM/EEPROM
Pin Change
Main Clock
Watchdog
Other I/O
INT0 and
Interrupt
clkFLASH
Ready
clkCPU
clkADC
clkPCK
ADC
clkIO
Sleep Mode
Idle X X X X X X X X X X
ADC Noise
X X X(1) X X X X
Reduction
Power-down X(1) X X
To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a
SLEEP instruction must be executed. The SM[1:0] bits in the MCUCR Register select which
sleep mode (Idle, ADC Noise Reduction or Power-down) will be activated by the SLEEP instruc-
tion. See Table 7-2 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
Note that if a level triggered interrupt is used for wake-up the changed level must be held for
some time to wake up the MCU (and for the MCU to enter the interrupt service routine). See
“External Interrupts” on page 51 for details.
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2586N–AVR–04/11
the Analog Comparator can be powered down by setting the ACD bit in “ACSR – Analog Com-
parator Control and Status Register” on page 124. This will reduce power consumption in Idle
mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.
36 ATtiny25/45/85
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ATtiny25/45/85
7.2.1 Limitations
BOD disable functionality has been implemented in the following devices, only:
• ATtiny25, revision E, and newer
• ATtiny45, revision D, and newer
• ATtiny85, revision C, and newer
Revisions are marked on the device package and can be located as follows:
• Bottom side of packages 8P3 and 8S2
• Top side of package 20M1
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7.4.3 Brown-out Detector
If the Brown-out Detector is not needed in the application, this module should be turned off. If the
Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes,
and hence, always consume power. In the deeper sleep modes, this will contribute significantly
to the total current consumption. See “Brown-out Detection” on page 43 and “Software BOD Dis-
able” on page 36 for details on how to configure the Brown-out Detector.
38 ATtiny25/45/85
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ATtiny25/45/85
In order to disable BOD during sleep (see Table 7-1 on page 35) the BODS bit must be written to
logic one. This is controlled by a timed sequence and the enable bit, BODSE in MCUCR. First,
both BODS and BODSE must be set to one. Second, within four clock cycles, BODS must be
set to one and BODSE must be set to zero. The BODS bit is active three clock cycles after it is
set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for
the actual sleep mode. The BODS bit is automatically cleared after three clock cycles.
In devices where Sleeping BOD has not been implemented this bit is unused and will always
read zero.
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• Bit 2 – PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0
is enabled, operation will continue like before the shutdown.
40 ATtiny25/45/85
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ATtiny25/45/85
MCU Status
Register (MCUSR)
WDRF
BORF
PORF
EXTRF
Power-on Reset
VCC
Circuit
Brown-out
BODLEVEL[2:0] Reset Circuit
Pull-up Resistor
INTERNAL RESET
SPIKE Q
RESET Reset Circuit S
FILTER
COUNTER RESET
Watchdog
Timer
Watchdog
Oscillator
CKSEL[3:0]
SUT[1:0]
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-
ferent selections for the delay period are presented in “Clock Sources” on page 25.
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8.2.1 Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in “System and Reset Characteristics” on page 170. The POR is activated whenever
VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as
well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay,
when VCC decreases below the detection level.
VRST
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
VRST
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
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ATtiny25/45/85
VCC VBOT+
VBOT-
RESET
TIME-OUT tTOUT
INTERNAL
RESET
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Figure 8-6. Watchdog Reset During Operation
CC
CK
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
44 ATtiny25/45/85
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ATtiny25/45/85
“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 45 for
details.
OSC/1024K
OSC/512K
OSC/128K
OSC/256K
OSC/16K
OSC/32K
OSC/64K
OSC/2K
OSC/4K
OSC/8K
WATCHDOG
RESET
WDP0
WDP1
WDP2
WDP3
WDE
MCU RESET
8.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer
The sequence for changing configuration differs slightly between the two safety levels. Separate
procedures are described for each level.
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8.4.2 Code Example
The following code example shows one assembly and one C function for turning off the WDT.
The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that
no interrupts will occur during execution of these functions.
46 ATtiny25/45/85
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ATtiny25/45/85
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• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure. This bit must also be set when
changing the prescaler bits. See “Timed Sequences for Changing the Configuration of the
Watchdog Timer” on page 45.
48 ATtiny25/45/85
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ATtiny25/45/85
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9. Interrupts
This section describes the specifics of the interrupt handling as performed in ATtiny25/45/85.
For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling”
on page 12.
If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular
program code can be placed at these locations.
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ATtiny25/45/85
A typical and general setup for interrupt vector addresses in ATtiny25/45/85 is shown in the pro-
gram example below.
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Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
in “System Clock and Clock Options” on page 23.
If the low level on the interrupt pin is removed before the device has woken up then program
execution will not be diverted to the interrupt service routine but continue from the instruction fol-
lowing the SLEEP command.
clk
PCINT(0)
pin_lat
pin_sync
pcint_in_(0)
pcint_syn
pcint_setflag
PCIF
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ATtiny25/45/85
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9.3.3 GIFR – General Interrupt Flag Register
Bit 7 6 5 4 3 2 1 0
0x3A – INTF0 PCIF – – – – – GIFR
Read/Write R R/W R/W R R R R R
Initial Value 0 0 0 0 0 0 0 0
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ATtiny25/45/85
10.1 Introduction
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.
This means that the direction of one port pin can be changed without unintentionally changing
the direction of any other pin with the SBI and CBI instructions. The same applies when chang-
ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as
input). Each output buffer has symmetrical drive characteristics with both high sink and source
capability. The pin driver is strong enough to drive LED displays directly. All port pins have indi-
vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have
protection diodes to both VCC and Ground as indicated in Figure 10-1. Refer to “Electrical Char-
acteristics” on page 166 for a complete list of parameters.
Rpu
Pxn Logic
See Figure
"General Digital I/O" for
Details
All registers and bit references in this section are written in general form. A lower case “x” repre-
sents the numbering letter for the port, and a lower case “n” represents the bit number. However,
when using the register or bit defines in a program, the precise form must be used. For example,
PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Regis-
ters and bit locations are listed in “Register Description” on page 66.
Three I/O memory address locations are allocated for each port, one each for the Data Register
– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins
I/O location is read only, while the Data Register and the Data Direction Register are read/write.
However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-
ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the
pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page
56. Most port pins are multiplexed with alternate functions for the peripheral features on the
device. How each alternate function interferes with the port pin is described in “Alternate Port
Functions” on page 59. Refer to the individual module sections for a full description of the alter-
nate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
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10.2 Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a func-
tional description of one I/O-port pin, here generically called Pxn.
PUD
Q D
DDxn
Q CLR
WDx
RESET
RDx
DATA BUS
1
Pxn Q D
PORTxn 0
Q CLR
RESET
WRx WPx
SLEEP RRx
SYNCHRONIZER
RPx
D Q D Q
PINxn
L Q Q
clk I/O
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports.
56 ATtiny25/45/85
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ATtiny25/45/85
SYSTEM CLK
SYNC LATCH
PINxn
t pd, max
t pd, min
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Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in Figure 10-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of
the clock. In this case, the delay tpd through the synchronizer is one system clock period.
SYSTEM CLK
r16 0xFF
SYNC LATCH
PINxn
t pd
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define
the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values
are read back again, but as previously discussed, a nop instruction is included to be able to read
back the value recently assigned to some of the pins.
Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-
ups are set on pins 0, 1 and 4, until the direction bits are correctly set, defining bit 2 and 3 as
low and redefining bits 0 and 1 as strong high drivers.
58 ATtiny25/45/85
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ATtiny25/45/85
C Code Example
unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB4)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
_NOP();
/* Read port pins */
i = PINB;
...
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Figure 10-5. Alternate Port Functions(1)
PUOExn
PUOVxn
1
0
PUD
DDOExn
DDOVxn
1
0 Q D
DDxn
Q CLR
WDx
PVOExn RESET
RDx
PVOVxn
DATA BUS
1 1
Pxn
0 Q D 0
PORTxn
PTOExn
Q CLR
DIEOExn
WPx
DIEOVxn RESET
1 WRx
RRx
0 SLEEP
SYNCHRONIZER
RPx
SET
D Q D Q
PINxn
L CLR Q CLR Q
clk I/O
DIxn
AIOxn
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
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ATtiny25/45/85
Table 10-2 summarizes the function of the overriding signals. The pin and port indexes from Fig-
ure 10-5 are not shown in the succeeding tables. The overriding signals are generated internally
in the modules having the alternate function.
The following subsections shortly describe the alternate functions for each port, and relate the
overriding signals to the alternate function. Refer to the alternate function description for further
details.
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10.3.1 Alternate Functions of Port B
The Port B pins with alternate function are shown in Table 10-3.
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ATtiny25/45/85
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set (one)) to serve this function. The OC0B pin is also the output pin for the PWM mode timer
function.
• OC1A: Output Compare Match output: The PB1 pin can serve as an external output for the
Timer/Counter1 Compare Match B when configured as an output (DDB1 set). The OC1A pin
is also the output pin for the PWM mode timer function.
• DO: Three-wire mode Universal Serial Interface Data output. Three-wire mode Data output
overrides PORTB1 value and it is driven to the port when data direction bit DDB1 is set (one).
PORTB1 still enables the pull-up, if the direction is input and PORTB1 is set (one).
• PCINT1: Pin Change Interrupt source 1.
Table 10-4 and Table 10-5 relate the alternate functions of Port B to the overriding signals
shown in Figure 10-5 on page 60.
64 ATtiny25/45/85
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ATtiny25/45/85
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10.4 Register Description
66 ATtiny25/45/85
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ATtiny25/45/85
11.1 Features
• Two Independent Output Compare Units
• Double Buffered Output Compare Registers
• Clear Timer on Compare Match (Auto Reload)
• Glitch Free, Phase Correct Pulse Width Modulator (PWM)
• Variable PWM Period
• Frequency Generator
• Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
11.2 Overview
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output
Compare Units, and with PWM support. It allows accurate program execution timing (event man-
agement) and wave generation.
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 11-1. For the actual
placement of I/O pins, refer to “Pinout ATtiny25/45/85” on page 2. CPU accessible I/O Registers,
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-
tions are listed in the “Register Description” on page 80.
Edge
Tn
Detector
TOP BOTTOM
( From Prescaler )
Timer/Counter
TCNTn
= =0
OCnA
(Int.Req.)
Waveform
= Generation
OCnA
OCRnA
Fixed
OCnB
TOP
(Int.Req.)
Value
DATA BUS
Waveform
= Generation
OCnB
OCRnB
TCCRnA TCCRnB
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11.2.1 Registers
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit
registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the
Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Inter-
rupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0).
The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-
erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and
OC0B). See “Output Compare Unit” on page 71. for details. The Compare Match event will also
set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare
interrupt request.
11.2.2 Definitions
Many register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-
pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or
bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing
Timer/Counter0 counter value and so on.
The definitions in Table 11-1 are also used extensively throughout the document.
68 ATtiny25/45/85
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ATtiny25/45/85
of the prescaler will have implications for situations where a prescaled clock is used. One exam-
ple of a prescaling artifact is when the timer/counter is enabled and clocked by the prescaler (6 >
CS0[2:0] > 1). The number of system clock cycles from when the timer is enabled to the first
count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8,
64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program
execution.
Tn D Q D Q D Q Tn_sync
(To Clock
Select Logic)
LE
clk I/O
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T0 has been stable for at least one
system clock cycle, otherwise it is a risk that a false timer/counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (following the Nyquist sampling theorem). However, due to variation of the system clock
frequency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) toler-
ances, it is recommended that maximum frequency of an external clock source is less than
fclk_I/O/2.5.
An external clock source can not be prescaled.
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Figure 11-3. Timer/Counter0 Prescaler
clk I/O
Clear
PSR10
T0
Synchronization
clkT0
The synchronization logic on the input pins (T0) in Figure 11-3 is shown in Figure 11-2 on page
69.
Clock Select
count Edge
Tn
clear clkTn Detector
TCNTn Control Logic
direction
( From Prescaler )
bottom top
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ATtiny25/45/85
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source,
selected by the Clock Select bits (CS0[2:0]). When no clock source is selected (CS0[2:0] = 0)
the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter
Control Register B (TCCR0B). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare output OC0A. For more
details about advanced counting sequences and waveform generation, see “Modes of Opera-
tion” on page 73.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by
the WGM0[1:0] bits. TOV0 can be used for generating a CPU interrupt.
OCRnx TCNTn
= (8-bit Comparator )
OCFnx (Int.Req.)
top
bottom
Waveform Generator OCnx
FOCn
WGMn[1:0] COMnX[1:0]
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The OCR0x Registers are double buffered when using any of the Pulse Width Modulation
(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou-
ble buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare
Registers to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR0x Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is dis-
abled the CPU will access the OCR0x directly.
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ATtiny25/45/85
COMnx1
COMnx0 Waveform
D Q
FOCn Generator
1
OCn
OCnx Pin
0
D Q
DATA BUS
PORT
D Q
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform
Generator if either of the COM0x[1:0] bits are set. However, the OC0x pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visi-
ble on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0x state before the out-
put is enabled. Note that some COM0x[1:0] bit settings are reserved for certain modes of
operation. See “Register Description” on page 80.
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sequence, while the Waveform Generation mode bits do. The COM0x[1:0] bits control whether
the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-
PWM modes the COM0x[1:0] bits control whether the output should be set, cleared, or toggled
at a Compare Match (See “Compare Match Output Unit” on page 72.).
For detailed timing information refer to Figure 11-10, Figure 11-11, Figure 11-12 and Figure 11-
13 in “Timer/Counter Timing Diagrams” on page 78.
TCNTn
OCn
(COMnx[1:0] = 1)
(Toggle)
Period 1 2 3 4
An interrupt can be generated each time the counter value reaches the TOP value by using the
OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-
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ATtiny25/45/85
ning with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR0A is lower than the current
value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can
occur.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical
level on each Compare Match by setting the Compare Output mode bits to toggle mode
(COM0A[1:0] = 1). The OC0A value will not be visible on the port pin unless the data direction
for the pin is set to output. The waveform generated will have a maximum frequency of fOC0 =
fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following
equation:
f clk_I/O
f OCnx = --------------------------------------------------
2 ⋅ N ⋅ ( 1 + OCRnx )
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the
counter counts from MAX to 0x00.
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Figure 11-8. Fast PWM Mode, Timing Diagram
TCNTn
OCn (COMnx[1:0] = 2)
OCn (COMnx[1:0] = 3)
Period 1 2 3 4 5 6 7
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the inter-
rupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
Setting the COM0x[1:0] bits to two will produce a non-inverted PWM and an inverted PWM out-
put can be generated by setting the COM0x[1:0] to three: Setting the COM0A[1:0] bits to one
allowes the AC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not
available for the OC0B pin (See Table 11-3 on page 81). The actual OC0x value will only be vis-
ible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by setting (or clearing) the OC0x Register at the Compare Match between OCR0x
and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is
cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnxPWM = ------------------
N ⋅ 256
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result
in a constantly high or low output (depending on the polarity of the output set by the COM0A[1:0]
bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC0x to toggle its logical level on each Compare Match (COM0x[1:0] = 1). The waveform
generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero. This
feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out-
put Compare unit is enabled in the fast PWM mode.
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OCRnx Update
TCNTn
OCn (COMnx[1:0] = 2)
OCn (COMnx[1:0] = 3)
Period 1 2 3
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0x pins. Setting the COM0x[1:0] bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM0x[1:0] to three: Setting the COM0A0 bits to
one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is
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not available for the OC0B pin (See Table 11-4 on page 81). The actual OC0x value will only be
visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x
and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Com-
pare Match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for
the output when using phase correct PWM can be calculated by the following equation:
f clk_I/O
f OCnxPCPWM = ------------------
N ⋅ 510
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in Figure 11-9 OCn has a transition from high to low even though
there is no Compare Match. The point of this transition is to guaratee symmetry around BOT-
TOM. There are two cases that give a transition without Compare Match, as follows:
• OCR0A changes its value from MAX, like in Figure 11-9. When the OCR0A value is MAX the
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-
counting Compare Match.
• The timer starts counting from a value higher than the one in OCR0A, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up.
clkI/O
clkTn
(clkI/O /1)
TOVn
Figure 11-11 shows the same timing data, but with the prescaler enabled.
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clkI/O
clkTn
(clkI/O /8)
TOVn
Figure 11-12 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC
mode and PWM mode, where OCR0A is TOP.
Figure 11-12. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
OCFnx
Figure 11-13 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast
PWM mode where OCR0A is TOP.
Figure 11-13. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
caler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
TOP - 1 TOP BOTTOM BOTTOM + 1
(CTC)
OCRnx TOP
OCFnx
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11.9 Register Description
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Table 11-3 shows the COM0x[1:0] bit functionality when the WGM0[2:0] bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR0A or OCR0B equals TOP and COM0A1/COM0B1 is set. In
this case, the compare match is ignored, but the set or clear is done at BOTTOM. See “Fast
PWM Mode” on page 75 for more details.
Table 11-4 shows the COM0x[1:0] bit functionality when the WGM0[2:0] bits are set to phase
correct PWM mode.
Note: 1. A special case occurs when OCR0A or OCR0B equals TOP and COM0A1/COM0B1 is set. In
this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Cor-
rect PWM Mode” on page 77 for more details.
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unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 73).
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A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0B as TOP.
The FOC0B bit is always read as zero.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0A pin.
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11.9.6 OCR0B – Output Compare Register B
Bit 7 6 5 4 3 2 1 0
0x28 OCR0B[7:0] OCR0B
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0B pin.
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the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),
and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
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12. 8-bit Timer/Counter1
The Timer/Counter1 is a general purpose 8-bit Timer/Counter module that has a separate pres-
caling selection from the separate prescaler.
CK
T1CK 14-BIT
PCK 64/32 MHz T/C PRESCALER
T1CK/16384
T1CK/1024
T1CK/2048
T1CK/4096
T1CK/8192
T1CK/128
T1CK/256
T1CK/512
T1CK/16
T1CK/32
T1CK/64
T1CK/2
T1CK/4
T1CK/8
T1CK
CS10
CS11
CS12
CS13
In the asynchronous clocking mode the clock selections are from PCK to PCK/16384 and stop,
and in the synchronous clocking mode the clock selections are from CK to CK/16384 and stop.
The clock options are described in Table 12-5 on page 92 and the Timer/Counter1 Control Reg-
ister, TCCR1. Setting the PSR1 bit in GTCCR register resets the prescaler. The PCKE bit in the
PLLCSR register enables the asynchronous mode. The frequency of the fast peripheral clock is
64 MHz (or 32 MHz in Low Speed Mode).
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Timer/Counter1 and the output compare registers serve as dual stand-alone PWMs with non-
overlapping non-inverted and inverted outputs. Refer to page 89 for a detailed description on
this function. Similarly, the high prescaling opportunities make this unit useful for lower speed
functions or exact timing functions with infrequent actions.
OCR1C OCR1C_SI
TCCR1 TCCR1_SI
OCF1A
OCF1A_SO
GTCCR GTCCR_SI
TCNT1
TCNT1 TCNT1_SI
OCF1B
OCF1B_SO
OCF1A OCF1A_SI
OCF1B OCF1B_SI
TOV1
TOV1 TOV1_SI TOV1_SO
PCKE
CK
S
A
S
PCK A
Timer/Counter1 and the prescaler allow running the CPU from any clock source while the pres-
caler is operating on the fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock in the
asynchronous mode.
Note that the system clock frequency must be lower than one third of the PCK frequency. The
synchronization mechanism of the asynchronous Timer/Counter1 needs at least two edges of
the PCK when the system clock is high. If the frequency of the system clock is too high, it is a
risk that data or control values are lost.
The following Figure 12-3 shows the block diagram for Timer/Counter1.
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Figure 12-3. Timer/Counter1 Block Diagram
T/C1 OVER- T/C1 COMPARE T/C1 COMPARE OC1A OC1A OC1B OC1B
FLOW IRQ MATCH A IRQ MATCH B IRQ (PB1) (PB0) (PB4) (PB3)
OCIE1A
OCIE1B
OCF1B
OCF1A
TOIE1
TOIE0
TOV1
TOV0
TIMER INT. MASK TIMER INT. FLAG T/C CONTROL GLOBAL T/C CONTROL
REGISTER (TIMSK) REGISTER (TIFR) REGISTER 1 (TCCR1) REGISTER (GTCCR)
PSR1
PWM1B
COM1B1
COM1B0
FOC1B
FOC1A
CS12
CS11
CS10
PWM1A
CTC1
COM1A0
COM1A1
CS13
TOV1
OCF1A
OCF1B
TIMER/COUNTER1
8-BIT DATABUS
Three status flags (overflow and compare matches) are found in the Timer/Counter Interrupt
Flag Register - TIFR. Control signals are found in the Timer/Counter Control Registers TCCR1
and GTCCR. The interrupt enable/disable settings are found in the Timer/Counter Interrupt
Mask Register - TIMSK.
The Timer/Counter1 contains three Output Compare Registers, OCR1A, OCR1B, and OCR1C
as the data source to be compared with the Timer/Counter1 contents. In normal mode the Out-
put Compare functions are operational with all three output compare registers. OCR1A
determines action on the OC1A pin (PB1), and it can generate Timer1 OC1A interrupt in normal
mode and in PWM mode. Likewise, OCR1B determines action on the OC1B pin (PB4) and it can
generate Timer1 OC1B interrupt in normal mode and in PWM mode. OCR1C holds the
Timer/Counter maximum value, i.e. the clear on compare match value. In the normal mode an
overflow interrupt (TOV1) is generated when Timer/Counter1 counts from $FF to $00, while in
the PWM mode the overflow interrupt is generated when Timer/Counter1 counts either from $FF
to $00 or from OCR1C to $00. The inverted PWM outputs OC1A and OC1B are not connected in
normal mode.
In PWM mode, OCR1A and OCR1B provide the data values against which the Timer Counter
value is compared. Upon compare match the PWM outputs (OC1A, OC1A, OC1B, OC1B) are
generated. In PWM mode, the Timer Counter counts up to the value specified in the output com-
pare register OCR1C and starts again from $00. This feature allows limiting the counter “full”
value to a specified value, lower than $FF. Together with the many prescaler options, flexible
PWM frequency selection is provided. Table 12-3 on page 91 lists clock selection and OCR1C
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values to obtain PWM frequencies from 20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to
500 kHz in 50 kHz steps. Higher PWM frequencies can be obtained at the expense of resolution.
PWM1x
PWM1x
t non-overlap =0 t non-overlap =0 x = A or B
When the counter value match the contents of OCR1A or OCR1B, the OC1A and OC1B outputs
are set or cleared according to the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the
Timer/Counter1 Control Register A - TCCR1, as shown in Table 12-1.
Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the output
compare register OCR1C, and starting from $00 up again. A compare match with OC1C will set
an overflow interrupt flag (TOV1) after a synchronization delay following the compare event.
Note that in PWM mode, writing to the Output Compare Registers OCR1A or OCR1B, the data
value is first transferred to a temporary location. The value is latched into OCR1A or OCR1B
when the Timer/Counter reaches OCR1C. This prevents the occurrence of odd-length PWM
pulses (glitches) in the event of an unsynchronized OCR1A or OCR1B. See Figure 12-5 for an
example.
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Figure 12-5. Effects of Unsynchronized OCR Latching
Compare Value changes
Counter Value
Compare Value
During the time between the write and the latch operation, a read from OCR1A or OCR1B will
read the contents of the temporary location. This means that the most recently written value
always will read out of OCR1A or OCR1B.
When OCR1A or OCR1B contain $00 or the top value, as specified in OCR1C register, the out-
put PB1(OC1A) or PB4(OC1B) is held low or high according to the settings of
COM1A1/COM1A0. This is shown in Table 12-2.
In PWM mode, the Timer Overflow Flag - TOV1 is set when the TCNT1 counts to the OCR1C
value and the TCNT1 is reset to $00. The Timer Overflow Interrupt1 is executed when TOV1 is
set provided that Timer Overflow Interrupt and global interrupts are enabled. This also applies to
the Timer Output Compare flags and interrupts.
The frequency of the PWM will be Timer Clock 1 Frequency divided by (OCR1C value + 1). See
the following equation:
f TCK1
f PWM = -----------------------------------
-
( OCR1C + 1 )
Resolution shows how many bits are required to express the value in the OCR1C register and
can be calculated using the following equation:
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R = log 2(OCR1C + 1)
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12.3 Register Description
In PWM mode, these bits have different functions. Refer to Table 12-1 on page 89 for a detailed
description.
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In PWM mode, these bits have different functions. Refer to Table 12-1 on page 89 for a detailed
description.
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• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is
executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the
Timer/Counter Interrupt Flag Register - TIFR.
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13. 8-bit Timer/Counter1 in ATtiny15 Mode
The ATtiny15 compatibility mode is selected by writing the code “0011” to the CKSEL fuses (if
any other code is written, the Timer/Counter1 is working in normal mode). When selected the
ATtiny15 compatibility mode provides an ATtiny15 backward compatible prescaler and
Timer/Counter. Furthermore, the clocking system has same clock frequencies as in ATtiny15.
CK (1.6 MHz)
CK/1024
CK/128
CK/256
CK/512
PCK/2
PCK/4
PCK/8
CK/16
CK/32
CK/64
0
CK/2
CK/4
CK/8
PCK
CK
CS10
CS11
CS12
CS13
The same clock selections as in ATtiny15 can be chosen for Timer/Counter1 from the output
multiplexer, because the frequency of the fast peripheral clock is 25.6 MHz and the prescaler is
similar in the ATtiny15 compatibility mode. The clock selections are PCK, PCK/2, PCK/4, PCK/8,
CK, CK/2, CK/4, CK/8, CK/16, CK/32, CK/64, CK/128, CK/256, CK/512, CK/1024 and stop.
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101 for a detailed description on this function. Similarly, the high prescaling opportunities make
this unit useful for lower speed functions or exact timing functions with infrequent actions.
TCNT1
OCR1C OCR1C_SI TCNT_SO
TCCR1 TCCR1_SI
GTCCR GTCCR_SI
TCNT1
TCNT1 TCNT1_SI
OCF1A
OCF1A_SO
OCF1A OCF1A_SI
TOV1
TOV1 TOV1_SI TOV1_SO
PCKE
CK
S
A
S
PCK A
Timer/Counter1 and the prescaler allow running the CPU from any clock source while the pres-
caler is operating on the fast 25.6 MHz PCK clock in the asynchronous mode.
The following Figure 13-3 shows the block diagram for Timer/Counter1.
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Figure 13-3. Timer/Counter1 Block Diagram
T/C1 OVER- T/C1 COMPARE OC1A
FLOW IRQ MATCH A IRQ (PB1)
OCIE1A
OCF1A
TOIE1
TOIE0
TOV1
TOV0
TIMER INT. MASK TIMER INT. FLAG T/C CONTROL GLOBAL T/C CONTROL
REGISTER (TIMSK) REGISTER (TIFR) REGISTER 1 (TCCR1) REGISTER 2 (GTCCR)
CS12
CS11
CS10
CTC1
COM1A1
PWM1A
CS13
FOC1A
COM1A0
PSR1
TOV1
OCF1A
TIMER/COUNTER1
8-BIT DATABUS
Two status flags (overflow and compare match) are found in the Timer/Counter Interrupt Flag
Register - TIFR. Control signals are found in the Timer/Counter Control Registers TCCR1 and
GTCCR. The interrupt enable/disable settings are found in the Timer/Counter Interrupt Mask
Register - TIMSK.
The Timer/Counter1 contains two Output Compare Registers, OCR1A and OCR1C as the data
source to be compared with the Timer/Counter1 contents. In normal mode the Output Compare
functions are operational with OCR1A only. OCR1A determines action on the OC1A pin (PB1),
and it can generate Timer1 OC1A interrupt in normal mode and in PWM mode. OCR1C holds
the Timer/Counter maximum value, i.e. the clear on compare match value. In the normal mode
an overflow interrupt (TOV1) is generated when Timer/Counter1 counts from $FF to $00, while
in the PWM mode the overflow interrupt is generated when the Timer/Counter1 counts either
from $FF to $00 or from OCR1C to $00.
In PWM mode, OCR1A provides the data values against which the Timer Counter value is com-
pared. Upon compare match the PWM outputs (OC1A) is generated. In PWM mode, the Timer
Counter counts up to the value specified in the output compare register OCR1C and starts again
from $00. This feature allows limiting the counter “full” value to a specified value, lower than $FF.
Together with the many prescaler options, flexible PWM frequency selection is provided. Table
12-3 on page 91 lists clock selection and OCR1C values to obtain PWM frequencies from
20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to 500 kHz in 50 kHz steps. Higher PWM
frequencies can be obtained at the expense of resolution.
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Note that in PWM mode, writing to the Output Compare Register OCR1A, the data value is first
transferred to a temporary location. The value is latched into OCR1A when the Timer/Counter
reaches OCR1C. This prevents the occurrence of odd-length PWM pulses (glitches) in the event
of an unsynchronized OCR1A. See Figure 13-4 for an e xample.
During the time between the write and the latch operation, a read from OCR1A will read the con-
tents of the temporary location. This means that the most recently written value always will read
out of OCR1A.
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When OCR1A contains $00 or the top value, as specified in OCR1C register, the output
PB1(OC1A) is held low or high according to the settings of COM1A1/COM1A0. This is shown in
Table 13-2.
In PWM mode, the Timer Overflow Flag - TOV1 is set when the TCNT1 counts to the OCR1C
value and the TCNT1 is reset to $00. The Timer Overflow Interrupt1 is executed when TOV1 is
set provided that Timer Overflow Interrupt and global interrupts are enabled. This also applies to
the Timer Output Compare flags and interrupts.
The PWM frequency can be derived from the timer/counter clock frequency using the following
equation:
f TCK1
f = -----------------------------------
-
( OCR1C + 1 )
The duty cycle of the PWM waveform can be calculated using the following equation:
...where TPCK is the period of the fast peripheral clock (1/25.6 MHz = 39.1 ns).
Resolution indicates how many bits are required to express the value in the OCR1C register. It
can be calculated using the following equation:
R = log 2(OCR1C + 1)
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Table 13-3. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode (Continued)
PWM Frequency Clock Selection CS1[3:0] OCR1C RESOLUTION
80 kHz PCK/4 0011 199 7.6
90 kHz PCK/4 0011 177 7.5
100 kHz PCK/4 0011 159 7.3
110 kHz PCK/4 0011 144 7.2
120 kHz PCK/4 0011 132 7.1
130 kHz PCK/2 0010 245 7.9
140 kHz PCK/2 0010 228 7.8
150 kHz PCK/2 0010 212 7.7
160 kHz PCK/2 0010 199 7.6
170 kHz PCK/2 0010 187 7.6
180 kHz PCK/2 0010 177 7.5
190 kHz PCK/2 0010 167 7.4
200 kHz PCK/2 0010 159 7.3
250 kHz PCK 0001 255 8.0
300 kHz PCK 0001 212 7.7
350 kHz PCK 0001 182 7.5
400 kHz PCK 0001 159 7.3
450 kHz PCK 0001 141 7.1
500 kHz PCK 0001 127 7.0
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• Bits 5:4 – COM1A[1:0]: Comparator A Output Mode, Bits 1 and 0
The COM1A1 and COM1A0 control bits determine any output pin action following a compare
match with compare register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A).
Since this is an alternative function to an I/O port, the corresponding direction control bit must be
set (one) in order to control an output pin.
In PWM mode, these bits have different functions. Refer to Table 13-1 on page 101 for a
detailed description.
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13.3.5 OCR1C – Timer/Counter1 Output Compare Register C
Bit 7 6 5 4 3 2 1 0
0x2D MSB LSB OCR1C
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 1 1 1 1 1 1 1 1
The Output Compare Register B - OCR1B from ATtiny15 is replaced with the output compare
register C - OCR1C that is an 8-bit read/write register. This register has the same function as the
Output Compare Register B in ATtiny15.
The Timer/Counter Output Compare Register C contains data to be continuously compared with
Timer/Counter1. A compare match does only occur if Timer/Counter1 counts to the OCR1C
value. A software write that sets TCNT1 and OCR1C to the same value does not generate a
compare match. If the CTC1 bit in TCCR1 is set, a compare match will clear TCNT1.
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14. Dead Time Generator
The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving
external power control switches safely. The Dead Time Generator is a separate block that can
be connected to Timer/Counter1 and it is used to insert dead times (non-overlapping times) for
the Timer/Counter1 complementary output pairs (OC1A-OC1A and OC1B-OC1B). The sharing
of tasks is as follows: the timer/counter generates the PWM output and the Dead Time Genera-
tor generates the non-overlapping PWM output pair from the timer/counter PWM signal. Two
Dead Time Generators are provided, one for each PWM output. The non-overlap time is adjust-
able and the PWM output and it’s complementary output are adjusted separately, and
independently for both PWM outputs.
PCKE
TIMER/COUNTER1
T15M
CK
PWM GENERATOR
PWM1A PWM1B
PCK
DT1AH DT1BH
DEAD TIME GENERATOR DEAD TIME GENERATOR
DT1AL DT1BL
The dead time generation is based on the 4-bit down counters that count the dead time, as
shown in Figure 46. There is a dedicated prescaler in front of the Dead Time Generator that can
divide the Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8. This provides for large range of
dead times that can be generated. The prescaler is controlled by two control bits DTPS1[1:0]
from the I/O register at address 0x23. The block has also a rising and falling edge detector that
is used to start the dead time counting period. Depending on the edge, one of the transitions on
the rising edges, OC1x or OC1x is delayed until the counter has counted to zero. The compara-
tor is used to compare the counter with zero and stop the dead time insertion when zero has
been reached. The counter is loaded with a 4-bit DT1xH or DT1xL value from DT1x I/O register,
depending on the edge of the PWM generator output when the dead time insertion is started.
DEAD TIME
CLOCK CONTROL 4-BIT COUNTER
PRESCALER
OC1x
DT1xH
DT1xL
DT1x
I/O REGISTER
PWM1x
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ATtiny25/45/85
The length of the counting period is user adjustable by selecting the dead time prescaler setting
in 0x23 register, and selecting then the dead time value in I/O register DT1x. The DT1x register
consists of two 4-bit fields, DT1xH and DT1xL that control the dead time periods of the PWM
output and its’ complementary output separately. Thus the rising edge of OC1x and OC1x can
have different dead time periods. The dead time is adjusted as the number of prescaled dead
time generator clock cycles.
PWM1x
OC1x
OC1x
x = A or B
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14.1.2 DT1A – Timer/Counter1 Dead Time A
Bit 7 6 5 4 3 2 1 0
0x25 DT1AH3 DT1AH2 DT1AH1 DT1AH0 DT1AL3 DT1AL2 DT1AL1 DT1AL0 DT1A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
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ATtiny25/45/85
15.1 Features
• Two-wire Synchronous Data Transfer (Master or Slave)
• Three-wire Synchronous Data Transfer (Master or Slave)
• Data Received Interrupt
• Wakeup from Idle Mode
• Wake-up from All Sleep Modes In Two-wire Mode
• Two-wire Start Condition Detector with Interrupt Capability
15.2 Overview
The Universal Serial Interface (USI), provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load.
A simplified block diagram of the USI is shown in Figure 15-1 For actual placement of I/O pins
refer to “Pinout ATtiny25/45/85” on page 2. Device-specific I/O Register and bit locations are
listed in the “Register Descriptions” on page 118.
3
2
USIDR
1 TIM0 COMP
0
USIBR
3 0
2 USCK/SCL (Input/Open Drain)
4-bit Counter 1
USIOIF
USISIF
USIDC
USIPF
DATA BUS
1
0 CLOCK
HOLD
[1] Two-wire
USISR Clock
Control Unit
2
USIWM1
USIWM0
USICS1
USICS0
USICLK
USIOIE
USISIE
USITC
USICR
The 8-bit USI Data Register (USIDR) contains the incoming and outgoing data. It is directly
accessible via the data bus but a copy of the contents is also placed in the USI Buffer Register
(USIBR) where it can be retrieved later. If reading the USI Data Register directly, the register
must be read as quickly as possible to ensure that no data is lost.
The most significant bit of the USI Data Register is connected to one of two output pins (depend-
ing on the mode configuration, see “USICR – USI Control Register” on page 120). There is a
transparent latch between the output of the USI Data Register and the output pin, which delays
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the change of data output to the opposite clock edge of the data input sampling. The serial input
is always sampled from the Data Input (DI) pin independent of the configuration.
The 4-bit counter can be both read and written via the data bus, and it can generate an overflow
interrupt. Both the USI Data Register and the counter are clocked simultaneously by the same
clock source. This allows the counter to count the number of bits received or transmitted and
generate an interrupt when the transfer is complete. Note that when an external clock source is
selected the counter counts both clock edges. This means the counter registers the number of
clock edges and not the number of data bits. The clock can be selected from three different
sources: The USCK pin, Timer/Counter0 Compare Match or from software.
The two-wire clock control unit can be configured to generate an interrupt when a start condition
has been detected on the two-wire bus. It can also be set to generate wait states by holding the
clock pin low after a start condition is detected, or after the counter overflows.
DO
DI
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
USCK
SLAVE
DO
DI
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
USCK
PORTxn
MASTER
Figure 15-2 shows two USI units operating in three-wire mode, one as Master and one as Slave.
The two USI Data Registers are interconnected in such way that after eight USCK clocks, the
data in each register has been interchanged. The same clock also increments the USI’s 4-bit
counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine
when a transfer is completed. The clock is generated by the Master device software by toggling
the USCK pin via the PORTB register or by writing a one to bit USITC bit in USICR.
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ATtiny25/45/85
USCK
USCK
DO MSB 6 5 4 3 2 1 LSB
DI MSB 6 5 4 3 2 1 LSB
A B C D E
The three-wire mode timing is shown in Figure 15-3 At the top of the figure is a USCK cycle ref-
erence. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The
USCK timing is shown for both external clock modes. In external clock mode 0 (USICS0 = 0), DI
is sampled at positive edges, and DO is changed (USI Data Register is shifted by one) at nega-
tive edges. In external clock mode 1 (USICS0 = 1) the opposite edges with respect to mode 0
are used. In other words, data is sampled at negative and changes the output at positive edges.
The USI clock modes corresponds to the SPI data mode 0 and 1.
Referring to the timing diagram (Figure 15-3), a bus transfer involves the following steps:
1. The slave and master devices set up their data outputs and, depending on the protocol
used, enable their output drivers (mark A and B). The output is set up by writing the
data to be transmitted to the USI Data Register. The output is enabled by setting the
corresponding bit in the Data Direction Register of Port B. Note that there is not a pre-
ferred order of points A and B in the figure, but both must be at least one half USCK
cycle before point C, where the data is sampled. This is in order to ensure that the data
setup requirement is satisfied. The 4-bit counter is reset to zero.
2. The master software generates a clock pulse by toggling the USCK line twice (C and
D). The bit values on the data input (DI) pins are sampled by the USI on the first edge
(C), and the data output is changed on the opposite edge (D). The 4-bit counter will
count both edges.
3. Step 2. is repeated eight times for a complete register (byte) transfer.
4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that
the transfer has been completed. If USI Buffer Registers are not used the data bytes
that have been transferred must now be processed before a new transfer can be initi-
ated. The overflow interrupt will wake up the processor if it is set to Idle mode.
Depending of the protocol used the slave device can now set its output to high
impedance.
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sbrs r16, USIOIF
rjmp SPITransfer_loop
in r16,USIDR
ret
The code is size optimized using only eight instructions (plus return). The code example
assumes that the DO and USCK pins have been enabled as outputs in DDRB. The value stored
in register r16 prior to the function is called is transferred to the slave device, and when the
transfer is completed the data received from the slave is stored back into the register r16.
The second and third instructions clear the USI Counter Overflow Flag and the USI counter
value. The fourth and fifth instructions set three-wire mode, positive edge clock, count at USITC
strobe, and toggle USCK. The loop is repeated 16 times.
The following code demonstrates how to use the USI as an SPI master with maximum speed
(fSCK = fCK/2):
SPITransfer_Fast:
out USIDR,r16
ldi r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)
ldi r17,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK)
in r16,USIDR
ret
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ATtiny25/45/85
...
SlaveSPITransfer:
out USIDR,r16
ldi r16,(1<<USIOIF)
out USISR,r16
SlaveSPITransfer_loop:
in r16, USISR
sbrs r16, USIOIF
rjmp SlaveSPITransfer_loop
in r16,USIDR
ret
The code is size optimized using only eight instructions (plus return). The code example
assumes that the DO and USCK pins have been enabled as outputs in DDRB. The value stored
in register r16 prior to the function is called is transferred to the master device, and when the
transfer is completed the data received from the master is stored back into the register r16.
Note that the first two instructions is for initialization, only, and need only be executed once.
These instructions set three-wire mode and positive edge clock. The loop is repeated until the
USI Counter Overflow Flag is set.
SDA
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCL
HOLD
SCL
Two-wire Clock
Control Unit
SLAVE
SDA
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCL
PORTxn
MASTER
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Figure 15-4 shows two USI units operating in two-wire mode, one as master and one as slave. It
is only the physical layer that is shown since the system operation is highly dependent of the
communication scheme used. The main differences between the master and slave operation at
this level is the serial clock generation which is always done by the master. Only the slave uses
the clock control unit.
Clock generation must be implemented in software, but the shift operation is done automatically
in both devices. Note that clocking only on negative edges for shifting data is of practical use in
this mode. The slave can insert wait states at start or end of transfer by forcing the SCL clock
low. This means that the master must always check if the SCL line was actually released after it
has generated a positive edge.
Since the clock also increments the counter, a counter overflow can be used to indicate that the
transfer is completed. The clock is generated by the master by toggling the USCK pin via the
PORTB register.
The data direction is not given by the physical layer. A protocol, like the one used by the TWI-
bus, must be implemented to control the data flow.
SDA
A B C D E F
Referring to the timing diagram (Figure 15-5), a bus transfer involves the following steps:
1. The start condition is generated by the master by forcing the SDA low line while keep-
ing the SCL line high (A). SDA can be forced low either by writing a zero to bit 7 of the
USI Data Register, or by setting the corresponding bit in the PORTB register to zero.
Note that the Data Direction Register bit must be set to one for the output to be
enabled. The start detector logic of the slave device (see Figure 15-6 on page 117)
detects the start condition and sets the USISIF Flag. The flag can generate an interrupt
if necessary.
2. In addition, the start detector will hold the SCL line low after the master has forced a
negative edge on this line (B). This allows the slave to wake up from sleep or complete
other tasks before setting up the USI Data Register to receive the address. This is done
by clearing the start condition flag and resetting the counter.
3. The master set the first bit to be transferred and releases the SCL line (C). The slave
samples the data and shifts it into the USI Data Register at the positive edge of the SCL
clock.
4. After eight bits containing slave address and data direction (read or write) have been
transferred, the slave counter overflows and the SCL line is forced low (D). If the slave
is not the one the master has addressed, it releases the SCL line and waits for a new
start condition.
5. When the slave is addressed, it holds the SDA line low during the acknowledgment
cycle before holding the SCL line low again (i.e., the USI Counter Register must be set
to 14 before releasing SCL at (D)). Depending on the R/W bit the master or slave
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enables its output. If the bit is set, a master read operation is in progress (i.e., the slave
drives the SDA line) The slave can hold the SCL line low after the acknowledge (E).
6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is
given by the master (F), or a new start condition is given.
If the slave is not able to receive more data it does not acknowledge the data byte it has last
received. When the master does a read operation it must terminate the operation by forcing the
acknowledge bit low after the last byte transmitted.
CLOCK
D Q D Q
HOLD
SDA
CLR CLR
SCL
Write( USISIF)
The start condition detector is working asynchronously and can therefore wake up the processor
from power-down sleep mode. However, the protocol used might have restrictions on the SCL
hold time. Therefore, when using this feature the oscillator start-up time (set by CKSEL fuses,
see “Clock Systems and their Distribution” on page 23) must also be taken into consideration.
Refer to the description of the USISIF bit on page 119 for further details.
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15.4.3 12-Bit Timer/Counter
Combining the 4-bit USI counter with one of the 8-bit timer/counters creates a 12-bit counter.
The USI Data Register can be accessed directly but a copy of the data can also be found in the
USI Buffer Register.
Depending on the USICS[1:0] bits of the USI Control Register a (left) shift operation may be per-
formed. The shift operation can be synchronised to an external clock edge, to a Timer/Counter0
Compare Match, or directly to software via the USICLK bit. If a serial clock occurs at the same
cycle the register is written, the register will contain the value written and no shift is performed.
Note that even when no wire mode is selected (USIWM[1:0] = 0) both the external data input
(DI/SDA) and the external clock input (USCK/SCL) can still be used by the USI Data Register.
The output pin (DO or SDA, depending on the wire mode) is connected via the output latch to
the most significant bit (bit 7) of the USI Data Register. The output latch ensures that data input
is sampled and data output is changed on opposite clock edges. The latch is open (transparent)
during the first half of a serial clock cycle when an external clock source is selected (USICS1 =
1) and constantly open when an internal clock source is used (USICS1 = 0). The output will be
changed immediately when a new MSB is written as long as the latch is open.
Note that the Data Direction Register bit corresponding to the output pin must be set to one in
order to enable data output from the USI Data Register.
Instead of reading data from the USI Data Register the USI Buffer Register can be used. This
makes controlling the USI less time critical and gives the CPU more time to handle other pro-
gram tasks. USI flags as set similarly as when reading the USIDR register.
The content of the USI Data Register is loaded to the USI Buffer Register when the transfer has
been completed.
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The Status Register contains interrupt flags, line status flags and the counter value.
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15.5.4 USICR – USI Control Register
Bit 7 6 5 4 3 2 1 0
0x0D USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC USICR
Read/Write R/W R/W R/W R/W R/W R/W W W
Initial Value 0 0 0 0 0 0 0 0
The USI Control Register includes bits for interrupt enable, setting the wire mode, selecting the
clock and clock strobe.
Two-wire mode. Uses SDA (DI) and SCL (USCK) pins (1).
The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and use open-
collector output drives. The output drivers are enabled by setting the corresponding bit for
SDA and SCL in the DDRB register.
When the output driver is enabled for the SDA pin it will force the line SDA low if the output
of the USI Data Register or the corresponding bit in the PORTB register is zero.
1 0 Otherwise, the SDA line will not be driven (i.e., it is released). When the SCL pin output
driver is enabled the SCL line will be forced low if the corresponding bit in the PORTB
register is zero, or by the start detector. Otherwise the SCL line will not be driven.
The SCL line is held low when a start detector detects a start condition and the output is
enabled. Clearing the Start Condition Flag (USISIF) releases the line. The SDA and SCL
pin inputs is not affected by enabling this mode. Pull-ups on the SDA and SCL port pin are
disabled in Two-wire mode.
Note: 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively
to avoid confusion between the modes of operation.
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ATtiny25/45/85
Basically only the function of the outputs are affected by these bits. Data and clock inputs are
not affected by the mode selected and will always have the same function. The counter and USI
Data Register can therefore be clocked externally and data input sampled, even when outputs
are disabled.
• Bits 3:2 – USICS[1:0]: Clock Source Select
These bits set the clock source for the USI Data Register and counter. The data output latch
ensures that the output is changed at the opposite edge of the sampling of the data input
(DI/SDA) when using external clock source (USCK/SCL). When software strobe or
Timer/Counter0 Compare Match clock option is selected, the output latch is transparent and
therefore the output is changed immediately.
Clearing the USICS[1:0] bits enables software strobe option. When using this option, writing a
one to the USICLK bit clocks both the USI Data Register and the counter. For external clock
source (USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects between external
clocking and software clocking by the USITC strobe bit.
Table 15-2 shows the relationship between the USICS[1:0] and USICLK setting and clock
source used for the USI Data Register and the 4-bit counter.
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When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writ-
ing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of
when the transfer is done when operating as a master device.
The bit will read as zero.
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ATtiny25/45/85
ACBG
ACD
ACIE
AIN0
+ ANALOG
INTERRUPT COMPARATOR
_ SELECT IRQ
ACI
AIN1
ACIS1 ACIS0
ACME
ADEN
ACO
ADC MULTIPLEXER
OUTPUT (1)
See Figure 1-1 on page 2 and Table 10-5 on page 65 for Analog Comparator pin placement.
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16.2 Register Description
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ATtiny25/45/85
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the
bits are changed.
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17. Analog to Digital Converter
17.1 Features
• 10-bit Resolution
• 1 LSB Integral Non-linearity
• ± 2 LSB Absolute Accuracy
• 65 - 260 µs Conversion Time
• Up to 15 kSPS at Maximum Resolution
• Four Multiplexed Single Ended Input Channels
• Two differential input channels with selectable gain
• Temperature sensor input channel
• Optional Left Adjustment for ADC Result Readout
• 0 - VCC ADC Input Voltage Range
• Selectable 1.1V / 2.56V ADC Voltage Reference
• Free Running or Single Conversion Mode
• ADC Start Conversion by Auto Triggering on Interrupt Sources
• Interrupt on ADC Conversion Complete
• Sleep Mode Noise Cancele
• Unipolar / Bibilar Input Mode
• Input Polarity Reversal Mode
17.2 Overview
The ATtiny25/45/85 features a 10-bit successive approximation Analog to Digital Converter
(ADC). The ADC is connected to a 4-channel Analog Multiplexer which allows one differential
voltage input and four single-ended voltage inputs constructed from the pins of Port B. The dif-
ferential input (PB3, PB4 or PB2, PB5) is equipped with a programmable gain stage, providing
amplification step of 26 dB (20x) on the differential input voltage before the A/D conversion. The
single-ended voltage inputs refer to 0V (GND).
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is
held at a constant level during conversion. A block diagram of the ADC is shown in Figure 17-1
on page 127.
Internal reference voltages of nominally 1.1V / 2.56V are provided on-chip. Alternatively, VCC
can be used as reference voltage for single ended channels. There is also an option to use an
external voltage reference and turn-off the internal voltage reference.
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ATtiny25/45/85
INTERRUPT
FLAGS
ADTS[2:0]
ADIE
ADIF
15 0
ADC CTRL. & STATUS B ADC MULTIPLEXER ADC CTRL. & STATUS A ADC DATA REGISTER
REGISTER (ADCSRB) SELECT (ADMUX) REGISTER (ADCSRA) (ADCH/ADCL)
ADLAR
MUX2
MUX1
MUX0
ADATE
ADPS2
ADPS1
ADPS0
ADEN
ADSC
BIN
ADIF
ADC[9:0]
IPR
TRIGGER
SELECT
REFS[2:0]
MUX DECODER
VCC PRESCALER
START
CHANNEL SELECTION
GAIN SELECTION
AREF
10-BIT DAC -
ADC4
+
ADC0
GAIN
AMPLIFIER
+
NEG.
INPUT
MUX
17.3 Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-
mation. The minimum value represents GND and the maximum value represents the voltage on
VCC, the voltage on the AREF pin or an internal 1.1V / 2.56V voltage reference.
The voltage reference for the ADC may be selected by writing to the REFS[2:0] bits in ADMUX.
The VCC supply, the AREF pin or an internal 1.1V / 2.56V voltage reference may be selected as
the ADC voltage reference. Optionally the internal 2.56V voltage reference may be decoupled
by an external capacitor at the AREF pin to improve noise immunity.
The analog input channel and differential gain are selected by writing to the MUX[3:0] bits in
ADMUX. Any of the four ADC input pins ADC[3:0] can be selected as single ended inputs to the
ADC. ADC2 or ADC0 can be selected as positive input and ADC0, ADC1, ADC2 or ADC3 can
be selected as negative input to the differential gain amplifier.
If differential channels are selected, the differential gain stage amplifies the voltage difference
between the selected input pair by the selected gain factor, 1x or 20x, according to the setting of
the MUX[3:0] bits in ADMUX. This amplified value then becomes the analog input to the ADC. If
single ended channels are used, the gain amplifier is bypassed altogether.
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If ADC0 or ADC2 is selected as both the positive and negative input to the differential gain
amplifier (ADC0-ADC0 or ADC2-ADC2), the remaining offset in the gain stage and conversion
circuitry can be measured directly as the result of the conversion. This figure can be subtracted
from subsequent conversions with the same gain setting to reduce offset error to below 1 LSW.
The on-chip temperature sensor is selected by writing the code “1111” to the MUX[3:0] bits in
ADMUX register when the ADC4 channel is used as an ADC input.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and
input channel selections will not go into effect until ADEN is set. The ADC does not consume
power when ADEN is cleared, so it is recommended to switch off the ADC before entering power
saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right adjusted, but can optionally be presented left
adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data
registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is
blocked. This means that if ADCL has been read, and a conversion completes before ADCH is
read, neither register is updated and the result from the conversion is lost. When ADCH is read,
ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When ADC
access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will
trigger even if the result is lost.
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ATtiny25/45/85
ADTS[2:0]
PRESCALER
START CLKADC
ADIF ADATE
SOURCE 1
. CONVERSION
. LOGIC
.
. EDGE
SOURCE n DETECTOR
ADSC
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to
one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be
read as one during a conversion, independently of how the conversion was started.
ADEN
START Reset
7-BIT ADC PRESCALER
CK
CK/128
CK/64
CK/32
CK/16
CK/2
CK/4
CK/8
ADPS0
ADPS1
ADPS2
By default, the successive approximation circuitry requires an input clock frequency between
50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the
input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate. It is
not recommended to use a higher input clock frequency than 1 MHz.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency
from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.
The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit
in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously
reset when ADEN is low.
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When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched
on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry,
as shown in Figure 17-4 below.
Figure 17-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Next
First Conversion Conversion
Cycle Number 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3
ADC Clock
ADEN
ADSC
ADIF
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-
sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion
mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new
conversion will be initiated on the first rising ADC clock edge.
Cycle Number 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3
ADC Clock
ADSC
ADIF
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures
a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold
takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-
tional CPU clock cycles are used for synchronization logic.
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ATtiny25/45/85
Cycle Number 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2
ADC Clock
Trigger
Source
ADATE
ADIF
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high.
11 12 13 1 2 3 4
Cycle Number
ADC Clock
ADSC
ADIF
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17.6 Changing Channel or Reference Selection
The MUX[3:0] and REFS[2:0] bits in the ADMUX Register are single buffered through a tempo-
rary register to which the CPU has random access. This ensures that the channels and voltage
reference selection only takes place at a safe point during the conversion. The channel and volt-
age reference selection is continuously updated until a conversion is started. Once the
conversion starts, the channel and voltage reference selection is locked to ensure a sufficient
sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the
conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following
rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel
or voltage reference selection values to ADMUX until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX Register, in order to control which conversion
will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot tell if the next conversion is based
on the old or the new settings. ADMUX can be safely updated in the following ways:
a. When ADATE or ADEN is cleared.
b. During conversion, minimum one ADC clock cycle after the trigger event.
c. After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC
conversion.
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ATtiny25/45/85
Noise Reduction and Idle mode. To make use of this feature, the following procedure should be
used:
• Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must
be selected and the ADC conversion complete interrupt must be enabled.
• Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the
CPU has been halted.
• If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake
up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt
wakes up the CPU before the ADC conversion is complete, that interrupt will be executed,
and an ADC Conversion Complete interrupt request will be generated when the ADC
conversion completes. The CPU will remain in active mode until a new sleep command is
executed.
Note that the ADC will not be automatically turned off when entering other sleep modes than Idle
mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-
ing such sleep modes to avoid excessive power consumption.
IIH
ADCn
1..100 kΩ
CS/H= 14 pF
IIL
VCC/2
The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or
less. If such a source is used, the sampling time will be negligible. If a source with higher imped-
ance is used, the sampling time will depend on how long time the source needs to charge the
S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources
with slowly varying signals, since this minimizes the required charge transfer to the S/H
capacitor.
Signal components higher than the Nyquist frequency (fADC/2) should not be present to avoid
distortion from unpredictable signal convolution. The user is advised to remove high frequency
components with a low-pass filter before applying the signals as inputs to the ADC.
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17.9 Noise Canceling Techniques
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of
analog measurements. If conversion accuracy is critical, the noise level can be reduced by
applying the following techniques:
• Keep analog signal paths as short as possible.
• Make sure analog tracks run over the analog ground plane.
• Keep analog tracks well away from high-speed switching digital tracks.
• If any port pin is used as a digital output, it mustn’t switch while a conversion is in progress.
• Place bypass capacitors as close to VCC and GND pins as possible.
Where high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode, as
described in Section 17.7 on page 132. This is especially the case when system clock frequency
is above 1 MHz, or when the ADC is used for reading the internal temperature sensor, as
described in Section 17.12 on page 137. A good system design with properly placed, external
bypass capacitors does reduce the need for using ADC Noise Reduction Mode
• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition
(at 0.5 LSB). Ideal value: 0 LSB.
Ideal ADC
Actual ADC
Offset
Error
VREF Input Voltage
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ATtiny25/45/85
• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last
transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).
Ideal value: 0 LSB
Ideal ADC
Actual ADC
• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum
deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0
LSB.
Ideal ADC
Actual ADC
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• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval
between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.
1 LSB
DNL
0x000
• Quantization Error: Due to the quantization of the input voltage into a finite number of codes,
a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB.
V IN ⋅ 1024
ADC = --------------------------
V REF
where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see
Table 17-3 on page 138 and Table 17-4 on page 139). 0x000 represents analog ground, and
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ATtiny25/45/85
0x3FF represents the selected voltage reference minus one LSB. The result is presented in one-
sided form, from 0x3FF to 0x000.
where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin,
and VREF the selected voltage reference (see Table 17-3 on page 138 and Table 17-4 on page
139). The voltage on the positive pin must always be larger than the voltage on the negative pin
or otherwise the voltage difference is saturated to zero. The result is presented in one-sided
form, from 0x000 (0d) to 0x3FF (+1023d). The GAIN is either 1x or 20x.
where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin,
and VREF the selected voltage reference. The result is presented in two’s complement form, from
0x200 (-512d) through 0x000 (+0d) to 0x1FF (+511d). The GAIN is either 1x or 20x.
However, if the signal is not bipolar by nature (9 bits + sign as the 10th bit), this scheme loses
one bit of the converter dynamic range. Then, if the user wants to perform the conversion with
the maximum dynamic range, the user can perform a quick polarity check of the result and use
the unipolar differential conversion with selectable differential input pairs (see the Input Polarity
Reversal mode ie. the IPR bit in the “ADCSRB – ADC Control and Status Register B” on page
141). When the polarity check is performed, it is sufficient to read the MSB of the result (ADC9 in
ADCH). If the bit is one, the result is negative, and if this bit is zero, the result is positive.
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assuming calibration at room temperature. Better accuracies are achieved by using two
temperature points for calibration.
The values described in Table 17-2 are typical values. However, due to process variation the
temperature sensor output voltage varies from one chip to another. To be capable of achieving
more accurate results the temperature measurement can be calibrated in the application soft-
ware. The sofware calibration can be done using the formula:
T = k * [(ADCH << 8) | ADCL] + TOS
where ADCH and ADCL are the ADC data registers, k is the fixed slope coefficient and TOS is the
temperature sensor offset. Typically, k is very close to 1.0 and in single-point calibration the
coefficient may be omitted. Where higher accuracy is required the slope coefficient should be
evaluated based on measurements at two temperatures.
Note: 1. The device requries a supply voltage of 3V in order to generate 2.56V reference voltage.
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17.13.2 ADCSRA – ADC Control and Status Register A
Bit 7 6 5 4 3 2 1 0
0x06 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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17.13.3.1 ADLAR = 0
Bit 15 14 13 12 11 10 9 8
0x05 – – – – – – ADC9 ADC8 ADCH
0x04 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL
7 6 5 4 3 2 1 0
Read/Write R R R R R R R R
R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
17.13.3.2 ADLAR = 1
Bit 15 14 13 12 11 10 9 8
0x05 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH
0x04 ADC1 ADC0 – – – – – – ADCL
7 6 5 4 3 2 1 0
Read/Write R R R R R R R R
R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
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are supported and the voltage on the positive input must always be larger than the voltage on
the negative input. Otherwise the result is saturated to the voltage reference. In the bipolar mode
two-sided conversions are supported and the result is represented in the two’s complement
form. In the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits +
1 sign bit.
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ATtiny25/45/85
18.1 Features
• Complete Program Flow Control
• Emulates All On-chip Functions, Both Digital and Analog , except RESET Pin
• Real-time Operation
• Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs)
• Unlimited Number of Program Break Points (Using Software Break Points)
• Non-intrusive Operation
• Electrical Characteristics Identical to Real Device
• Automatic Configuration System
• High-Speed Operation
• Programming of Non-volatile Memories
18.2 Overview
The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the
program flow, execute AVR instructions in the CPU and to program the different non-volatile
memories.
VCC
dW dW(RESET)
GND
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When designing a system where debugWIRE will be used, the following must be observed:
• Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the
pull-up resistor is optional.
• Connecting the RESET pin directly to VCC will not work.
• Capacitors inserted on the RESET pin must be disconnected when using debugWire.
• All external reset sources must be disconnected.
The DWDR Register provides a communication channel from the running program in the MCU
to the debugger. This register is only accessible by the debugWIRE and can therefore not be
used as a general purpose register in the normal operations.
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ATtiny25/45/85
If only a part of the page needs to be changed, the rest of the page must be stored (for example
in the temporary page buffer) before the erase, and then be re-written. When using alternative 1,
the Boot Loader provides an effective Read-Modify-Write feature which allows the user software
to first read the page, do the necessary changes, and then write back the modified data. If alter-
native 2 is used, it is not possible to read the old data while loading since the page is already
erased. The temporary page buffer can be accessed in a random sequence. It is essential that
the page address used in both the Page Erase and Page Write operation is addressing the same
page.
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If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be
lost.
Since the Flash is organized in pages (see Table 20-8 on page 154), the Program Counter can
be treated as having two different sections. One section, consisting of the least significant bits, is
addressing the words within a page, while the most significant bits are addressing the pages.
This is shown in Figure 19-1. Note that the Page Erase and Page Write operations are
addressed independently. Therefore it is of major importance that the software addresses the
same page in both the Page Erase and Page Write operation.
The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the
Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.
PCMSB PAGEMSB
PROGRAM
PCPAGE PCWORD
COUNTER
01
02
PAGEEND
Note: 1. The different variables used in Figure 19-1 are listed in Table 20-8 on page 154.
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ATtiny25/45/85
See section “Program And Data Memory Lock Bits” on page 151 for more information.
Refer to Table 20-5 on page 153 for a detailed description and mapping of the Fuse Low Byte.
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To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and
repeat the procedure above. If successful, the contents of the destination register are as follows.
Bit 7 6 5 4 3 2 1 0
Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0
Refer to Table 20-4 on page 152 for detailed description and mapping of the Fuse High Byte.
To read the Fuse Extended Byte (FEB), replace the address in the Z-pointer with 0x0002 and
repeat the previous procedure. If successful, the contents of the destination register are as
follows.
Bit 7 6 5 4 3 2 1 0
Rd FEB7 FEB6 FEB5 FEB4 FEB3 FEB2 FEB1 FEB0
Refer to Table 20-3 on page 152 for detailed description and mapping of the Fuse Extended
Byte.
If successful, the contents of the destination register are as described in section “Device Signa-
ture Imprint Table” on page 153.
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ATtiny25/45/85
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• Bit 4 – CTPB: Clear Temporary Page Buffer
If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be
cleared and the data will be lost.
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Notes: 1. Program the Fuse bits before programming the LB1 and LB2.
2. “1” means unprogrammed, “0” means programmed
Lock bits can also be read by device firmware. See section “Reading Lock, Fuse and Signature
Data from Software” on page 147.
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20.2 Fuse Bytes
ATtiny25/45/85 has three fuse bytes, as described in Table 20-3, Table 20-4, and Table 20-5.
Note that fuses are read as logical zero, “0”, when programmed.
Notes: 1. Enables SPM instruction. See “Self-Programming the Flash” on page 145.
Notes: 1. Controls use of RESET pin. See “Alternate Functions of Port B” on page 62.
2. After this fuse has been programmed device can be programmed via high-voltage serial mode,
only.
3. Must be unprogrammed when lock bit security is required. See “Program And Data Memory
Lock Bits” on page 151.
4. This fuse is not accessible in SPI programming mode.
5. See “WDTCR – Watchdog Timer Control Register” on page 47 for details.
6. See table “BODLEVEL Fuse Coding. TA = -40°C to +85°C” on page 171.
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ATtiny25/45/85
Note that fuse bits are locked if Lock Bit 1 (LB1) is programmed. Fuse bits should be pro-
grammed before lock bits. The status of fuse bits is not affected by chip erase.
Lock bits can also be read by device firmware. See section “Reading Lock, Fuse and Signature
Data from Software” on page 147.
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20.3.1 Signature Bytes
All Atmel microcontrollers have a three-byte signature code which identifies the device. This
code can be read in both serial and high-voltage programming mode, even when the device is
locked.
Signature bytes can also be read by the device firmware. See section “Reading Lock, Fuse and
Signature Data from Software” on page 147.
The three signature bytes reside in a separate address space called the device signature imprint
table. The signature data for ATtiny25/45/85 is given in Table 20-7.
Table 20-8. No. of Words in a Page and No. of Pages in the Flash
Device Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB
1K words
ATtiny25 16 words PC[3:0] 64 PC[9:4] 9
(2K bytes)
2K words
ATtiny45 32 words PC[4:0] 64 PC[10:5] 10
(4K bytes)
4K words
ATtiny85 32 words PC[4:0] 128 PC[11:5] 11
(8K bytes)
Table 20-9. No. of Words in a Page and No. of Pages in the EEPROM
EEPROM
Device Size Page Size PCWORD No. of Pages PCPAGE EEAMSB
ATtiny25 128 bytes 4 bytes EEA[1:0] 32 EEA[6:2] 6
ATtiny45 256 bytes 4 bytes EEA[1:0] 64 EEA[7:2] 7
ATtiny85 512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8
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ATtiny25/45/85
VCC
MOSI
MISO
SCK
RESET
GND
Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
CLKI pin.
After RESET is set low, the Programming Enable instruction needs to be executed first before
program/erase operations can be executed.
Note: In Table 20-10 above, the pin mapping for SPI programming is listed. Not all parts use the SPI
pins dedicated for the internal SPI interface.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
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20.5.1 Serial Programming Algorithm
When writing serial data to the ATtiny25/45/85, data is clocked on the rising edge of SCK.
When reading data from the ATtiny25/45/85, data is clocked on the falling edge of SCK. See
Figure 21-4 and Figure 21-5 for timing details.
To program and verify the ATtiny25/45/85 in the Serial Programming mode, the following
sequence is recommended (see four byte instruction formats in Table 20-12):
1. Power-up sequence: apply power between VCC and GND while RESET and SCK are
set to “0”
– In some systems, the programmer can not guarantee that SCK is held low during
power-up. In this case, RESET must be given a positive pulse after SCK has been
set to '0'. The duration of the pulse must be at least tRST plus two CPU clock cycles.
See Table 21-4 on page 170 for minimum pulse width on RESET pin, tRST
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of syn-
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
a time by supplying the 5 LSB of the address and data together with the Load Program
memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program memory
Page is stored by loading the Write Program memory Page instruction with the 6 MSB
of the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH
before issuing the next page. (See Table 20-11.) Accessing the serial programming
interface before the Flash write operation completes can result in incorrect
programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling (RDY/BSY) is not used,
the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 20-11.)
In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one byte at a time by supplying the 2 LSB of the address and data together with the
Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by
loading the Write EEPROM Memory Page Instruction with the 6 MSB of the address.
When using EEPROM page access only byte locations loaded with the Load EEPROM
Memory Page instruction is altered. The remaining locations remain unchanged. If poll-
ing (RDY/BSY) is not used, the used must wait at least tWD_EEPROM before issuing the
next page (See Table 20-9). In a chip erased device, no 0xFF in the data file(s) need to
be programmed.
6. Any memory location can be verified by using the Read instruction which returns the
content at the selected address at serial output MISO.
7. At the end of the programming session, RESET can be set high to commence normal
operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.
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Table 20-11. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol Minimum Wait Delay
tWD_FLASH 4.5 ms
tWD_EEPROM 4.0 ms
tWD_ERASE 9.0 ms
tWD_FUSE 4.5 ms
Table 20-12 on page 157 and Figure 20-2 on page 158 describes the Instruction set.
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Notes: 1. Not all instructions are applicable for all parts.
2. a = address
3. Bits are programmed ‘0’, unprogrammed ‘1’.
4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .
5. Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size.
6. Instructions accessing program memory use a word address. This address may be random within the page range.
7. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers.
If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until
this bit returns ‘0’ before the next instruction is carried out.
Within the same page, the low data byte must be loaded prior to the high data byte.
After data is loaded to the page buffer, program the EEPROM page, see Figure 20-2 on page
158.
Page Buffer
Page Offset
Page 0
Page 1
Page 2
Page Number
Page N-1
Program Memory/
EEPROM Memory
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ATtiny25/45/85
PB1 SII
The minimum period for the Serial Clock Input (SCI) during High-voltage Serial Programming is
220 ns.
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20.7.1 Enter High-voltage Serial Programming Mode
The following algorithm puts the device in High-voltage Serial Programming mode:
1. Set Prog_enable pins listed in Table 20-14 to “000”, RESET pin and VCC to 0V.
2. Apply 4.5 - 5.5V between VCC and GND. Ensure that VCC reaches at least 1.8V within
the next 20 µs.
3. Wait 20 - 60 µs, and apply 11.5 - 12.5V to RESET.
4. Keep the Prog_enable pins unchanged for at least 10 µs after the High-voltage has
been applied to ensure the Prog_enable Signature has been latched.
5. Release the Prog_enable[2] pin to avoid drive contention on the Prog_enable[2]/SDO
pin.
6. Wait at least 300 µs before giving any serial instructions on SDI/SII.
7. Exit Programming mode by power the device down or by bringing RESET pin to 0V.
If the rise time of the VCC is unable to fulfill the requirements listed above, the following alterna-
tive algorithm can be used:
1. Set Prog_enable pins listed in Table 20-14 to “000”, RESET pin and VCC to 0V.
2. Apply 4.5 - 5.5V between VCC and GND.
3. Monitor VCC, and as soon as VCC reaches 0.9 - 1.1V, apply 11.5 - 12.5V to RESET.
4. Keep the Prog_enable pins unchanged for at least 10 µs after the High-voltage has
been applied to ensure the Prog_enable Signature has been latched.
5. Release the Prog_enable[2] pin to avoid drive contention on the Prog_enable[2]/SDO
pin.
6. Wait until VCC actually reaches 4.5 - 5.5V before giving any serial instructions on
SDI/SII.
7. Exit Programming mode by power the device down or by bringing RESET pin to 0V.
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01
02
PAGEEND
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Figure 20-5. High-voltage Serial Programming Waveforms
SCI 0 1 2 3 4 5 6 7 8 9 10
PB3
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ATtiny25/45/85
SDI 0_bbbb_bbbb _00 0_eeee_eeee_00 0_dddd_dddd_00 0_0000_0000_00 Repeat after Instr. 1 - 5 until
the entire page buffer is filled
SII 0_0000_1100_00 0_0010_1100_00 0_0011_1100_00 0_0111_1101_00
or until all data within the
Load Flash SDO x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx page is filled.(2)
Page Buffer
SDI 0_0000_0000_00
SII 0_0111_1100_00 Instr 5.
SDO x_xxxx_xxxx_xx
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Table 20-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 (Continued)
Instruction Format
Instruction Instr.1/5 Instr.2/6 Instr.3 Instr.4 Operation Remarks
SDI 0_bbbb_bbbb_00 0_aaaa_aaaa_00 0_eeee_eeee_00 0_0000_0000_00 Repeat Instr. 1 - 6 for each
SII 0_0000_1100_00 0_0001_1100_00 0_0010_1100_00 0_0110_1101_00 new address. Wait after Instr.
Write SDO x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx 6 until SDO goes high.(4)
EEPROM
Byte SDI 0_0000_0000_00 0_0000_0000_00
SII 0_0110_0100_00 0_0110_1100_00 Instr. 6
SDO x_xxxx_xxxx_xx x_xxxx_xxxx_xx
Read SDI 0_bbbb_bbbb_00 0_aaaa_aaaa_00 0_0000_0000_00 0_0000_0000_00 Repeat Instr. 1, 3 - 4 for each
EEPROM SII 0_0000_1100_00 0_0001_1100_00 0_0110_1000_00 0_0110_1100_00 new address. Repeat Instr. 2
Byte SDO x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx q_qqqq_qqq0_00 for a new 256 byte page.
SDI 0_0100_0000_00 0_A987_6543_00 0_0000_0000_00 0_0000_0000_00 Wait after Instr. 4 until SDO
Write Fuse
SII 0_0100_1100_00 0_0010_1100_00 0_0110_0100_00 0_0110_1100_00 goes high. Write A - 3 = “0” to
Low Bits
SDO x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx program the Fuse bit.
SDI 0_0100_0000_00 0_IHGF_EDCB_00 0_0000_0000_00 0_0000_0000_00 Wait after Instr. 4 until SDO
Write Fuse
SII 0_0100_1100_00 0_0010_1100_00 0_0111_0100_00 0_0111_1100_00 goes high. Write I - B = “0” to
High Bits
SDO x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx program the Fuse bit.
SDI 0_0100_0000_00 0_0000_000J_00 0_0000_0000_00 0_0000_0000_00 Wait after Instr. 4 until SDO
Write Fuse
SII 0_0100_1100_00 0_0010_1100_00 0_0110_0110_00 0_0110_1110_00 goes high. Write J = “0” to
Extended Bits
SDO x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx program the Fuse bit.
SDI 0_0010_0000_00 0_0000_0021_00 0_0000_0000_00 0_0000_0000_00 Wait after Instr. 4 until SDO
Write Lock
SII 0_0100_1100_00 0_0010_1100_00 0_0110_0100_00 0_0110_1100_00 goes high. Write 2 - 1 = “0” to
Bits
SDO x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx program the Lock bit.
164 ATtiny25/45/85
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Notes: 1. a = address high bits, b = address low bits, d = data in high bits, e = data in low bits, p = data out high bits, q = data out low
bits, x = don’t care, 1 = Lock Bit1, 2 = Lock Bit2, 3 = CKSEL0 Fuse, 4 = CKSEL1 Fuse, 5 = CKSEL2 Fuse, 6 = CKSEL3
Fuse, 7 = SUT0 Fuse, 8 = SUT1 Fuse, 9 = CKOUT Fuse, A = CKDIV8 Fuse, B = BODLEVEL0 Fuse, C = BODLEVEL1
Fuse, D = BODLEVEL2 Fuse, E = EESAVE Fuse, F = WDTON Fuse, G = SPIEN Fuse, H = DWEN Fuse, I = RSTDISBL
Fuse, J = SELFPRGEN Fuse
2. For page sizes less than 256 words, parts of the address (bbbb_bbbb) will be parts of the page address.
3. For page sizes less than 256 bytes, parts of the address (bbbb_bbbb) will be parts of the page address.
4. The EEPROM is written page-wise. But only the bytes that are loaded into the page are actually written to the EEPROM.
Page-wise EEPROM access is more efficient when multiple bytes are to be written to the same page. Note that auto-erase
of EEPROM is not available in High-voltage Serial Programming, only in SPI Programming.
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21. Electrical Characteristics
Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or
Voltage on any Pin except RESET other conditions beyond those indicated in the
with respect to Ground ................................-0.5V to VCC+0.5V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Voltage on RESET with respect to Ground......-0.5V to +13.0V conditions for extended periods may affect
device reliability.
Maximum Operating Voltage ............................................ 6.0V
21.2 DC Characteristics
166 ATtiny25/45/85
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21.3 Speed
10 MHz
20 MHz
10 MHz
Safe Operating Area
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Notes: 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage).
2. ATtiny25/V, only: 6.4 MHz in ATtiny15 Compatibility Mode.
3. Voltage range for ATtiny25V/45V/85V.
4. Voltage range for ATtiny25/45/85.
V IH1
V IL1
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21.5 System and Reset Characteristics
Note: Revisions are marked on the package (packages 8P3 and 8S2: bottom, package 20M1: top)
170 ATtiny25/45/85
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Note: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where
this is the case, the device is tested down to VCC = VBOT during the production test. This guar-
antees that a Brown-out Reset will occur before VCC drops to a voltage where correct
operation of the microcontroller is no longer guaranteed.
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21.7 ADC Characteristics
Table 21-8. ADC Characteristics, Single Ended Channels. TA = -40°C to +85°C
Symbol Parameter Condition Min Typ Max Units
Resolution 10 Bits
VREF = 4V, VCC = 4V,
2 LSB
ADC clock = 200 kHz
VREF = 4V, VCC = 4V,
3 LSB
Absolute accuracy ADC clock = 1 MHz
(Including INL, DNL, and VREF = 4V, VCC = 4V,
Quantization, Gain and ADC clock = 200 kHz 1.5 LSB
Offset errors) Noise Reduction Mode
VREF = 4V, VCC = 4V,
ADC clock = 1 MHz 2.5 LSB
Noise Reduction Mode
Integral Non-linearity (INL)
VREF = 4V, VCC = 4V,
(Accuracy after offset and gain 1 LSB
ADC clock = 200 kHz
calibration)
VREF = 4V, VCC = 4V,
Differential Non-linearity (DNL) 0.5 LSB
ADC clock = 200 kHz
VREF = 4V, VCC = 4V,
Gain Error 2.5 LSB
ADC clock = 200 kHz
VREF = 4V, VCC = 4V,
Offset Error 1.5 LSB
ADC clock = 200 kHz
Conversion Time Free Running Conversion 14 280 µs
Clock Frequency 50 1000 kHz
VIN Input Voltage GND VREF V
Input Bandwidth 38.4 kHz
AREF External Reference Voltage 2.0 VCC V
Internal Voltage Reference 1.0 1.1 1.2 V
VINT
(1)
Internal 2.56V Reference VCC > 3.0V 2.3 2.56 2.8 V
RREF 32 kΩ
RAIN Analog Input Resistance 100 MΩ
ADC Output 0 1023 LSB
Note: 1. Values are guidelines only.
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Table 21-9. ADC Characteristics, Differential Channels (Unipolar Mode). TA = -40°C to +85°C
Symbol Parameter Condition Min Typ Max Units
Gain = 1x 10 Bits
Resolution
Gain = 20x 10 Bits
Gain = 1x
Absolute accuracy VREF = 4V, VCC = 5V 10.0 LSB
(Including INL, DNL, and ADC clock = 50 - 200 kHz
Quantization, Gain and Offset Gain = 20x
Errors) VREF = 4V, VCC = 5V 20.0 LSB
ADC clock = 50 - 200 kHz
Gain = 1x
VREF = 4V, VCC = 5V 4.0 LSB
Integral Non-Linearity (INL) ADC clock = 50 - 200 kHz
(Accuracy after Offset and
Gain Calibration) Gain = 20x
VREF = 4V, VCC = 5V 10.0 LSB
ADC clock = 50 - 200 kHz
Gain = 1x 10.0 LSB
Gain Error
Gain = 20x 15.0 LSB
Gain = 1x
VREF = 4V, VCC = 5V 3.0 LSB
ADC clock = 50 - 200 kHz
Offset Error
Gain = 20x
VREF = 4V, VCC = 5V 4.0 LSB
ADC clock = 50 - 200 kHz
Conversion Time Free Running Conversion 70 280 µs
Clock Frequency 50 200 kHz
VIN Input Voltage GND VCC V
VDIFF Input Differential Voltage VREF/Gain V
Input Bandwidth 4 kHz
AREF External Reference Voltage 2.0 VCC - 1.0 V
Internal Voltage Reference 1.0 1.1 1.2 V
VINT
Internal 2.56V Reference (1) VCC > 3.0V 2.3 2.56 2.8 V
RREF Reference Input Resistance 32 kΩ
RAIN Analog Input Resistance 100 MΩ
ADC Conversion Output 0 1023 LSB
Note: 1. Values are guidelines only.
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Table 21-10. ADC Characteristics, Differential Channels (Bipolar Mode). TA = -40°C to +85°C
Symbol Parameter Condition Min Typ Max Units
Gain = 1x 10 Bits
Resolution
Gain = 20x 10 Bits
Gain = 1x
Absolute accuracy VREF = 4V, VCC = 5V 8.0 LSB
(Including INL, DNL, and ADC clock = 50 - 200 kHz
Quantization, Gain and Offset Gain = 20x
Errors) VREF = 4V, VCC = 5V 8.0 LSB
ADC clock = 50 - 200 kHz
Gain = 1x
VREF = 4V, VCC = 5V 4.0 LSB
Integral Non-Linearity (INL) ADC clock = 50 - 200 kHz
(Accuracy after Offset and
Gain Calibration) Gain = 20x
VREF = 4V, VCC = 5V 5.0 LSB
ADC clock = 50 - 200 kHz
Gain = 1x 4.0 LSB
Gain Error
Gain = 20x 5.0 LSB
Gain = 1x
VREF = 4V, VCC = 5V 3.0 LSB
ADC clock = 50 - 200 kHz
Offset Error
Gain = 20x
VREF = 4V, VCC = 5V 4.0 LSB
ADC clock = 50 - 200 kHz
Conversion Time Free Running Conversion 70 280 µs
Clock Frequency 50 200 kHz
VIN Input Voltage GND VCC V
VDIFF Input Differential Voltage VREF/Gain V
Input Bandwidth 4 kHz
AREF External Reference Voltage 2.0 VCC - 1.0 V
Internal Voltage Reference 1.0 1.1 1.2 V
VINT
Internal 2.56V Reference (1) VCC > 3.0V 2.3 2.56 2.8 V
RREF Reference Input Resistance 32 kΩ
RAIN Analog Input Resistance 100 MΩ
ADC Conversion Output -512 511 LSB
Note: 1. Values are guidelines only.
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SAMPLE
MOSI
tOVSH tSHOX tSLSH
SCK
tSHSL
MISO
tSLIV
Table 21-11. Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 - 5.5V
(Unless Otherwise Noted)
Symbol Parameter Min Typ Max Units
1/tCLCL Oscillator Frequency (VCC = 1.8 - 5.5V) 0 4 MHz
tCLCL Oscillator Period (VCC = 1.8 - 5.5V) 250 ns
1/tCLCL Oscillator Frequency (VCC = 2.7 - 5.5V) 0 10 MHz
tCLCL Oscillator Period (VCC = 2.7 - 5.5V) 100 ns
1/tCLCL Oscillator Frequency (VCC = 4.5V - 5.5V) 0 20 MHz
tCLCL Oscillator Period (VCC = 4.5V - 5.5V) 50 ns
tSHSL SCK Pulse Width High 2 tCLCL* ns
tSLSH SCK Pulse Width Low 2 tCLCL* ns
tOVSH MOSI Setup to SCK High tCLCL ns
tSHOX MOSI Hold after SCK High 2 tCLCL ns
tSLIV SCK Low to MISO Valid 100 ns
Note: 1. 2 tCLCL for fck < 12 MHz, 3 tCLCL for fck >= 12 MHz
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21.9 High-voltage Serial Programming Characteristics
SCI (PB3)
tSHSL
SDO (PB2)
tSHOV
Table 21-12. High-voltage Serial Programming Characteristics TA = 25°C ± 10%, VCC = 5.0V ±
10% (Unless otherwise noted)
Symbol Parameter Min Typ Max Units
tSHSL SCI (PB3) Pulse Width High 125 ns
tSLSH SCI (PB3) Pulse Width Low 125 ns
tIVSH SDI (PB0), SII (PB1) Valid to SCI (PB3) High 50 ns
tSHIX SDI (PB0), SII (PB1) Hold after SCI (PB3) High 50 ns
tSHOV SCI (PB3) High to SDO (PB2) Valid 16 ns
tWLWH_PFB Wait after Instr. 3 for Write Fuse Bits 2.5 ms
176 ATtiny25/45/85
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Figure 22-1. Active Supply Current vs. Low frequency (0.1 - 1.0 MHz)
ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY
0.1 -1.0 MHz
1,2
5.5 V
1
5.0 V
0,8
4.5 V
4.0 V
I CC (mA)
0,6
3.3 V
0,4
2.7 V
1.8 V
0,2
0
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency (MHz)
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Figure 22-2. Active Supply Current vs. Frequency (1 - 20 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz
14
5.5 V
12
5.0 V
10 4.5 V
ICC (mA)
8
4.0V
6
4
3.3V
2.7V
2
1.8V
0
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
Figure 22-3. Active Supply Current vs. VCC (Internal RC oscillator, 8 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz
7
-40 ˚C
6
25 ˚C
5 85 ˚C
ICC (mA)
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
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ATtiny25/45/85
Figure 22-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
ICC (mA)
0,8
0,6
0,4
0,2
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Figure 22-5. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)
-40 ˚C
0,2
25 ˚C
85 ˚C
0,15
ICC (mA)
0,1
0,05
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
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22.2 Idle Supply Current
Figure 22-6. Idle Supply Current vs. low Frequency (0.1 - 1.0 MHz)
IDLE SUPPLY CURRENT vs. LOW FREQUENCY
0.1 - 1.0 MHz
0,25
5.5 V
5.0 V
0,2
4.5 V
4.0 V
0,15
ICC (mA)
3.3 V
2.7 V
0,1
1.8 V
0,05
0
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency (MHz)
3,5 5.5 V
3 5.0 V
2,5 4.5 V
ICC (mA)
2
4.0V
1,5
3.3V
1
2.7V
0,5
1.8V
0
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
180 ATtiny25/45/85
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ATtiny25/45/85
Figure 22-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)I
ICC (mA)
1
0,8
0,6
0,4
0,2
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Figure 22-9. Idle Supply Current vs. VCC (Internal RC Oscilllator, 1 MHz)
0,3
ICC (mA)
0,25
0,2
0,15
0,1
0,05
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
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Figure 22-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 128 kHz
0,1
-40 ˚C
0,09 25 ˚C
0,08 85 ˚C
0,07
0,06
ICC (mA)
0,05
0,04
0,03
0,02
0,01
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Table 22-1. Additional Current Consumption for the different I/O modules (absolute values)
PRR bit Typical numbers
VCC = 2V, f = 1 MHz VCC = 3V, f = 4 MHz VCC = 5V, f = 8 MHz
PRTIM1 45 uA 300 uA 1100 uA
PRTIM0 5 uA 30 uA 110 uA
PRUSI 5 uA 25 uA 100 uA
PRADC 15 uA 85 uA 340 uA
Table 22-2. Additional Current Consumption (percentage) in Active and Idle mode
Additional Current consumption Additional Current consumption
compared to Active with external clock compared to Idle with external clock
PRR bit (see Figure 22-1 and Figure 22-2) (see Figure 22-6 and Figure 22-7)
PRTIM1 20 % 80 %
PRTIM0 2% 10 %
PRUSI 2% 10 %
PRADC 5% 25 %
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It is possible to calculate the typical current consumption based on the numbers from Table 22-2
for other VCC and frequency settings that listed in Table 22-1.
22.3.1 Example
Calculate the expected current consumption in idle mode with USI, TIMER0, and ADC enabled
at VCC = 2.0V and f = 1 MHz. From Table 22-2 on page 182, third column, we see that we need
to add 10% for the USI, 25% for the ADC, and 10% for the TIMER0 module. Reading from Figure
22-9, we find that the idle current consumption is ~0,18 mA at VCC = 2.0V and f = 1 MHz. The
total current consumption in idle mode with USI, TIMER0, and ADC enabled, gives:
Figure 22-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled)
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER DISABLED
1.4
1.2 85 ˚C
1
I CC(uA)
0.8
-40 ˚C
0.6 25 ˚C
0.4
0.2
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
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Figure 22-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled)
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER ENABLED
14
12
10
-40 ˚C
ICC (uA)
8 25 ˚C
85 ˚C
6
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Figure 22-13. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
VCC = 1.8V
60
50
40
IOP (uA)
30
20
25 ˚C
10
85 ˚C
0 -40 ˚C
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
VOP (V)
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ATtiny25/45/85
Figure 22-14. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
70
60
50
IOP (uA) 40
30
20
25 ˚C
10
85 ˚C
-40 ˚C
0
0 0,5 1 1,5 2 2,5 3
VOP (V)
Figure 22-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
140
120
100
IOP (uA)
80
60
25 ˚C
40
85 ˚C
20
-40 ˚C
0
0 1 2 3 4 5 6
VOP (V)
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Figure 22-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC = 1.8V
40
35
30
25
IRESET(uA) 20
15
10
5
25 ˚C
-40 ˚C
85 ˚C
0
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
VRESET (V)
Figure 22-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC =2.7V
60
50
40
IRESET (uA)
30
20
25 ˚C
10
-40 ˚C
85 ˚C
0
0 0,5 1 1,5 2 2,5 3
VRESET(V)
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ATtiny25/45/85
Figure 22-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC = 5V
120
100
80
IRESET(uA)
60
40
25 ˚C
20
-40 ˚C
85 ˚C
0
0 1 2 3 4 5 6
VRESET(V)
Figure 22-19. I/O Pin Output Voltage vs. Sink Current (VCC = 3V)
I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 3V
1,2
0,8
85
VOL (V)
25
0,6
-40
0,4
0,2
0
0 5 10 15 20 25
IOL (mA)
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Figure 22-20. I/O Pin Output Voltage vs. Sink Current (VCC = 5V)
I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 5V
0,6
85
0,5
25
0,4
-40
VOL (V) 0,3
0,2
0,1
0
0 5 10 15 20 25
IOL (mA)
Figure 22-21. I/O Pin Output Voltage vs. Source Current (VCC = 3V)
I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
VCC = 3V
3,5
2,5 -40
25
2
VOH (V)
85
1,5
0,5
0
0 5 10 15 20 25
IOH (mA)
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Figure 22-22. I/O Pin Output Voltage vs. Source Current (VCC = 5V)
I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
VCC = 5V
5,1
4,9
4,8
VOH (V)
4,7
4,6
-40
4,5 25
85
4,4
0 5 10 15 20 25
IOH (mA)
Figure 22-23. Reset Pin Output Voltage vs. Sink Current (VCC = 3V)
RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 3V
1.5
85 °C
1
VOL (V)
0 °C
-45 °C
0.5
0
0 0.5 1 1.5 2 2.5 3
IOL (mA)
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Figure 22-24. Reset Pin Output Voltage vs. Sink Current (VCC = 5V)
RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 5V
0.8
0.6
VOL (V)
85 °C
0.4 0 °C
-45 °C
0.2
0
0 0.5 1 1.5 2 2.5 3
IOL (mA)
Figure 22-25. Reset Pin Output Voltage vs. Source Current (VCC = 3V)
RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
VCC = 3V
3.5
2.5
2
VOH (V)
1.5
-45 °C
1 25 °C
85 °C
0.5
0
0 0.5 1 1.5 2
IOH (mA)
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ATtiny25/45/85
Figure 22-26. Reset Pin Output Voltage vs. Source Current (VCC = 5V)
RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
VCC = 5V
4.5
VOH (V)
3.5
3
-45 °C
25 °C
2.5 85 °C
0 0.5 1 1.5 2
IOH (mA)
Figure 22-27. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’)
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIH, IO PIN READ AS '1'
3
-40 ˚C
85 ˚C
2,5
25 ˚C
Threshold (V)
1,5
0,5
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
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2586N–AVR–04/11
Figure 22-28. I/O Pin Input Threshold Voltage vs. VCC (VIL, IO Pin Read as ‘0’)
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0'
3
85 ˚C
2,5 25 ˚C
-40 ˚C
Threshold (V)
2
1,5
0,5
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
0,6
0,5
0,4
Input Hysteresis (V)
0,3 -40 °C
85 °C
0,2
25 °C
0,1
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
V CC (V)
192 ATtiny25/45/85
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ATtiny25/45/85
Figure 22-30. Reset Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’)
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIH, IO PIN READ AS '1'
2,5 85 °C
25 °C
-40 °C
2
Threshold (V)
1,5
0,5
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Figure 22-31. Reset Input Threshold Voltage vs. VCC (VIL, IO Pin Read as ‘0’)
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0'
2,5
85 °C
25 °C
-40 °C
2
Threshold (V)
1,5
0,5
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
193
2586N–AVR–04/11
Figure 22-32. Reset Pin Input Hysteresis vs. VCC
RESET PIN INPUT HYSTERESIS vs. VCC
0,5
0,45
0,4
0,35
0,25
0,2
0,15
0,1 -40 °C
0,05 25 °C
85 °C
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
4,4
4,36
Threshold (V)
4,34
4,32
Falling VCC
4,3
4,28
4,26
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (C)
194 ATtiny25/45/85
2586N–AVR–04/11
ATtiny25/45/85
2,8
Rising VCC
2,78
2,76
Threshold (V)
2,74
2,72
Falling VCC
2,7
2,68
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (C)
1,85
1,84
1,835
1,83
Threshold (V)
1,825
1,82
1,815
Falling VCC
1,81
1,805
1,8
1,795
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (C)
195
2586N–AVR–04/11
Figure 22-36. Bandgap Voltage vs. Supply Voltage
BANDGAP VOLTAGE vs. VCC
1,2
1,18
1,16
1,14
Bandgap Voltage (V)
1,12
1,1
85 °C
1,08 25 °C
1,06
1,04
-40 °C
1,02
1
1,5 2 2,5 3 3,5 4 4,5 5 5,5
Vcc (V)
1,2
1,18
1,16
1,14
Bandgap Voltage (V)
1,12 1.8 V
3V
1,1 5V
1,08
1,06
1,04
1,02
1
-40 -20 0 20 40 60 80 100
Temperature
196 ATtiny25/45/85
2586N–AVR–04/11
ATtiny25/45/85
0,128
0,126
0,124 -40 ˚C
0,122
FRC (MHz)
0,12 25 ˚C
0,118
0,116
0,114 85 ˚C
0,112
2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
0,12
0,118
0,116
FRC (MHz)
0,114
1.8 V
0,112
2.7 V
0,11 3.3 V
4.0 V
5.5 V
0,108
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature
197
2586N–AVR–04/11
Figure 22-40. Calibrated 8 MHz RC Oscillator Frequency vs. VCC
8,2
8,1 85 ˚C
25 ˚C
FRC (MHz)
7,9
7,8
7,7 -40 ˚C
7,6
7,5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
8,15
3.0 V
8,1
8,05
5.0 V
8
FRC (MHz)
7,95
7,9
7,85
7,8
7,75
7,7
-60 -40 -20 0 20 40 60 80 100
Temperature
198 ATtiny25/45/85
2586N–AVR–04/11
ATtiny25/45/85
18
85 ˚C
16
25 ˚C
14
-40 ˚C
12
FRC (MHz)
10
0
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
OSCCAL (X1)
1,65
85 ˚C
1,6
25 ˚C
FRC (MHz)
1,55
-40 ˚C
1,5
1,45
1,4
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
199
2586N–AVR–04/11
Figure 22-44. Calibrated 1.6 MHz RC Oscillator Frequency vs. Temperature
CALIBRATED 1.6MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
1,64
3.0 V
1,62
5.0 V
1,6
FRC (MHz)
1,58
1,56
1,54
1,52
1,5
-60 -40 -20 0 20 40 60 80 100
Temperature
Figure 22-45. Calibrated 1.6 MHz RC Oscillator Frequency vs. OSCCAL Value
CALIBRATED 1.6 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
4,5
85 ˚C
4
25 ˚C
3,5
-40 ˚C
3
FRC (MHz)
2,5
1,5
0,5
0
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
OSCCAL (X1)
200 ATtiny25/45/85
2586N–AVR–04/11
ATtiny25/45/85
30
85 °C
25
25 °C
-40 °C
20
ICC (uA)
15
10
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
250
200 85 °C
25 °C
-40 °C
150
ICC (uA)
100
50
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
201
2586N–AVR–04/11
Figure 22-48. Analog Comparator Current vs. VCC
50
45
85 °C
40 25 °C
-40 °C
35
30
ICC (uA)
25
20
15
10
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
12
-40 °C
10
25 °C
8
ICC (mA)
6
85 °C
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
202 ATtiny25/45/85
2586N–AVR–04/11
ATtiny25/45/85
Figure 22-50. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The
Reset Pull-up)
0,14 5.5 V
0,12 5.0 V
4.5 V
0,1
ICC (mA)
4.0 V
0,08
3.3 V
0,06
2.7 V
0,04
1.8 V
0,02
0
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency (MHz)
Figure 22-51. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current Through The Reset
Pull-up)
2
5.0 V
4.5 V
1,5
ICC (mA)
4.0V
1
3.3V
0,5
2.7V
1.8V
0
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
203
2586N–AVR–04/11
Figure 22-52. Minimum Reset Pulse Width vs. VCC
MINIMUM RESET PULSE WIDTH vs. VCC
2500
2000
Pulsewidth (ns)
1500
1000
85 ˚C
500
25 ˚C
-40 ˚C
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
204 ATtiny25/45/85
2586N–AVR–04/11
ATtiny25/45/85
205
2586N–AVR–04/11
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
206 ATtiny25/45/85
2586N–AVR–04/11
ATtiny25/45/85
207
2586N–AVR–04/11
Mnemonics Operands Description Operation Flags #Clocks
ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1
BSET s Flag Set SREG(s) ← 1 SREG(s) 1
BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1
BST Rr, b Bit Store from Register to T T ← Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) ← T None 1
SEC Set Carry C←1 C 1
CLC Clear Carry C←0 C 1
SEN Set Negative Flag N←1 N 1
CLN Clear Negative Flag N←0 N 1
SEZ Set Zero Flag Z←1 Z 1
CLZ Clear Zero Flag Z←0 Z 1
SEI Global Interrupt Enable I←1 I 1
CLI Global Interrupt Disable I←0 I 1
SES Set Signed Test Flag S←1 S 1
CLS Clear Signed Test Flag S←0 S 1
SEV Set Twos Complement Overflow. V←1 V 1
CLV Clear Twos Complement Overflow V←0 V 1
SET Set T in SREG T←1 T 1
CLT Clear T in SREG T←0 T 1
SEH Set Half Carry Flag in SREG H←1 H 1
CLH Clear Half Carry Flag in SREG H←0 H 1
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Move Between Registers Rd ← Rr None 1
MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1
LDI Rd, K Load Immediate Rd ← K None 1
LD Rd, X Load Indirect Rd ← (X) None 2
LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2
LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2
LD Rd, Y Load Indirect Rd ← (Y) None 2
LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2
LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2
LD Rd, Z Load Indirect Rd ← (Z) None 2
LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2
LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2
LDS Rd, k Load Direct from SRAM Rd ← (k) None 2
ST X, Rr Store Indirect (X) ← Rr None 2
ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2
ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2
ST Y, Rr Store Indirect (Y) ← Rr None 2
ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2
ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2
STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2
ST Z, Rr Store Indirect (Z) ← Rr None 2
ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2
STS k, Rr Store Direct to SRAM (k) ← Rr None 2
LPM Load Program Memory R0 ← (Z) None 3
LPM Rd, Z Load Program Memory Rd ← (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3
SPM Store Program Memory (z) ← R1:R0 None
IN Rd, P In Port Rd ← P None 1
OUT P, Rr Out Port P ← Rr None 1
PUSH Rr Push Register on Stack STACK ← Rr None 2
POP Rd Pop Register from Stack Rd ← STACK None 2
MCU CONTROL INSTRUCTIONS
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 1
WDR Watchdog Reset (see specific descr. for WDR/Timer) None 1
BREAK Break For On-chip Debug Only None N/A
208 ATtiny25/45/85
2586N–AVR–04/11
ATtiny25/45/85
8P3 ATtiny25V-10PU
ATtiny25V-10SU
8S2 ATtiny25V-10SUR
ATtiny25V-10SH
Industrial
(-40°C to +85°C) (4) ATtiny25V-10SSU
S8S1 ATtiny25V-10SSUR
10 1.8 – 5.5 ATtiny25V-10SSH
ATtiny25V-10MU
20M1
ATtiny25V-10MUR
ATtiny25V-10SN
8S2
Industrial ATtiny25V-10SNR
(-40°C to +105°C) (5) ATtiny25V-10SSN
S8S1
ATtiny25V-10SSNR
8P3 ATtiny25-20PU
ATtiny25-20SU
8S2 ATtiny25-20SUR
ATtiny25-20SH
Industrial
(-40°C to +85°C) (4) ATtiny25-20SSU
S8S1 ATtiny25-20SSUR
20 2.7 – 5.5 ATtiny25-20SSH
ATtiny25-20MU
20M1
ATtiny25-20MUR
ATtiny25-20SN
8S2
Industrial ATtiny25-20SNR
(-40°C to +105°C) (5) ATtiny25-20SSN
S8S1
ATtiny25-20SSNR
Notes: 1. For speed vs. supply voltage, see section 21.3 “Speed” on page 168.
2. All packages are Pb-free, halide-free and fully green, and they comply with the European directive for Restriction of Hazard-
ous Substances (RoHS).
3. Code indicators:
– H: NiPdAu lead finish
– U or N: matte tin
– R: tape & reel
4. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities.
5. For Typical and Electrical characteristics for this device please consult Appendix A, ATtiny25/V Specification at 105°C.
Package Types
8S2 8-lead, 0.208" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
S8S1 8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC)
20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
209
2586N–AVR–04/11
25.2 ATtiny45
Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3)
8P3 ATtiny45V-10PU
ATtiny45V-10SU
8S2 ATtiny45V-10SUR
Industrial ATtiny45V-10SH
10 1.8 – 5.5
(-40°C to +85°C) (4) ATtiny45V-10XU
8X
ATtiny45V-10XUR
ATtiny45V-10MU
20M1
ATtiny45V-10MUR
8P3 ATtiny45-20PU
ATtiny45-20SU
8S2 ATtiny45-20SUR
Industrial ATtiny45-20SH
20 2.7 – 5.5
(-40°C to +85°C) (4) ATtiny45-20XU
8X
ATtiny45-20XUR
ATtiny45-20MU
20M1
ATtiny45-20MUR
Notes: 1. For speed vs. supply voltage, see section 21.3 “Speed” on page 168.
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-
ous Substances (RoHS).
3. Code indicators:
– H: NiPdAu lead finish
– U: matte tin
– R: tape & reel
4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-
tion and minimum quantities.
Package Types
8S2 8-lead, 0.208" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
8X 8-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline Package (TSSOP)
20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
210 ATtiny25/45/85
2586N–AVR–04/11
ATtiny25/45/85
25.3 ATtiny85
Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3)
8P3 ATtiny85V-10PU
ATtiny85V-10SU
Industrial 8S2 ATtiny85V-10SUR
10 1.8 – 5.5
(-40°C to +85°C) (4) ATtiny85V-10SH
ATtiny85V-10MU
20M1
ATtiny85V-10MUR
8P3 ATtiny85-20PU
ATtiny85-20SU
Industrial 8S2 ATtiny85-20SUR
20 2.7 – 5.5
(-40°C to +85°C) (4) ATtiny85-20SH
ATtiny85-20MU
20M1
ATtiny85-20MUR
Notes: 1. For speed vs. supply voltage, see section 21.3 “Speed” on page 168.
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-
ous Substances (RoHS).
3. Code indicators:
– H: NiPdAu lead finish
– U: matte tin
– R: tape & reel
4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-
tion and minimum quantities.
Package Types
20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
211
2586N–AVR–04/11
26. Packaging Information
26.1 8P3
1
E
E1
Top View c
eA
End View
COMMON DIMENSIONS
D (Unit of Measure = inches)
e
D1 SYMBOL MIN NOM MAX NOTE
A2 A
A 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
b2 L D1 0.005 3
b3 E 0.300 0.310 0.325 4
4 PLCS b E1 0.240 0.250 0.280 3
e 0.100 BSC
Side View
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE DRAWING NO. REV.
2325 Orchard Parkway 8P3, 8-lead, 0.300" Wide Body, Plastic Dual
8P3 B
R San Jose, CA 95131 In-line Package (PDIP)
212 ATtiny25/45/85
2586N–AVR–04/11
ATtiny25/45/85
26.2 8S2
E E1
L
N
TOP VIEW θ
END VIEW
e b COMMON DIMENSIONS
A (Unit of Measure = mm)
4/15/08
TITLE GPC DRAWING NO. REV.
Package Drawing Contact: 8S2, 8-lead, 0.208” Body, Plastic Small
[email protected] Outline Package (EIAJ) STN 8S2 F
213
2586N–AVR–04/11
26.3 S8S1
E1 E
Top View
e
b
A COMMON DIMENSIONS
(Unit of Measure = mm)
L b 0.31 0.51
L 0.4 1.27
End View e 1.27 BSC
0o 8o
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc.
7/28/03
214 ATtiny25/45/85
2586N–AVR–04/11
ATtiny25/45/85
26.4 8X
End View
E1 E
Top View Ø
e b
A COMMON DIMENSIONS
(Unit of Measure = mm)
Note: These drawings are for general information only. Refer to JEDEC Drawing MO-153AC.
4/14/05
TITLE DRAWING NO. REV.
2325 Orchard Parkway 8X, 8-lead, 4.4 mm Body Width, Plastic Thin Shrink
San Jose, CA 95131 8X A
R Small Outline Package (TSSOP)
215
2586N–AVR–04/11
26.5 20M1
1
Pin 1 ID
2
3 E SIDE VIEW
TOP VIEW
A2
D2
A1
1 0.08 C
Pin #1 2
Notch COMMON DIMENSIONS
(0.20 R) 3 E2 (Unit of Measure = mm)
10/27/04
TITLE DRAWING NO. REV.
2325 Orchard Parkway 20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm,
R
San Jose, CA 95131 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) 20M1 A
216 ATtiny25/45/85
2586N–AVR–04/11
ATtiny25/45/85
27. Errata
1. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in
invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below
2V. If operating frequency can not be raised above 1MHz then supply voltage should be
more than 2V. Similarly, if supply voltage can not be raised above 2V then operating fre-
quency should be more than 1MHz.
This feature is known to be temperature dependent but it has not been characterised.
Guidelines are given for room temperature, only.
27.1.3 Rev A
Not sampled.
1. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in
invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below
2V. If operating frequency can not be raised above 1MHz then supply voltage should be
more than 2V. Similarly, if supply voltage can not be raised above 2V then operating fre-
quency should be more than 1MHz.
This feature is known to be temperature dependent but it has not been characterised.
Guidelines are given for room temperature, only.
217
2586N–AVR–04/11
27.2.3 Rev B and C
• PLL not locking
• EEPROM read from application code does not work in Lock Bit Mode 3
• EEPROM read may fail at low supply voltage / low clock frequency
• Timer Counter 1 PWM output generation on OC1B- XOC1B does not work correctly
2. EEPROM read from application code does not work in Lock Bit Mode 3
When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does
not work from the application code.
Problem Fix/Work around
Do not set Lock Bit Protection Mode 3 when the application code needs to read from
EEPROM.
3. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in
invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below
2V. If operating frequency can not be raised above 1MHz then supply voltage should be
more than 2V. Similarly, if supply voltage can not be raised above 2V then operating fre-
quency should be more than 1MHz.
This feature is known to be temperature dependent but it has not been characterised.
Guidelines are given for room temperature, only.
4. Timer Counter 1 PWM output generation on OC1B – XOC1B does not work correctly
Timer Counter1 PWM output OC1B-XOC1B does not work correctly. Only in the case when
the control bits, COM1B1 and COM1B0 are in the same mode as COM1A1 and COM1A0,
respectively, the OC1B-XOC1B output works correctly.
Problem Fix/Work around
The only workaround is to use same control setting on COM1A[1:0] and COM1B[1:0] control
bits, see table 14-4 in the data sheet. The problem has been fixed for Tiny45 rev D.
27.2.4 Rev A
• Too high power down power consumption
• DebugWIRE looses communication when single stepping into interrupts
• PLL not locking
• EEPROM read from application code does not work in Lock Bit Mode 3
• EEPROM read may fail at low supply voltage / low clock frequency
218 ATtiny25/45/85
2586N–AVR–04/11
ATtiny25/45/85
4. EEPROM read from application code does not work in Lock Bit Mode 3
When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does
not work from the application code.
Problem Fix/Work around
Do not set Lock Bit Protection Mode 3 when the application code needs to read from
EEPROM.
5. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in
invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below
2V. If operating frequency can not be raised above 1MHz then supply voltage should be
more than 2V. Similarly, if supply voltage can not be raised above 2V then operating fre-
quency should be more than 1MHz.
This feature is known to be temperature dependent but it has not been characterised.
Guidelines are given for room temperature, only.
219
2586N–AVR–04/11
27.3 Errata ATtiny85
The revision letter in this section refers to the revision of the ATtiny85 device.
27.3.2 Rev A
• EEPROM read may fail at low supply voltage / low clock frequency
1. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in
invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below
2V. If operating frequency can not be raised above 1MHz then supply voltage should be
more than 2V. Similarly, if supply voltage can not be raised above 2V then operating fre-
quency should be more than 1MHz.
This feature is known to be temperature dependent but it has not been characterised.
Guidelines are given for room temperature, only.
220 ATtiny25/45/85
2586N–AVR–04/11
ATtiny25/45/85
221
2586N–AVR–04/11
– Table 20-16, “High-voltage Serial Programming Instruction Set for ATtiny25/45/85,”
on page 163
– Table 21-1, “DC Characteristics. TA = -40°C to +85°C,” on page 166, notes adjusted
– Table 21-11, “Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 -
5.5V (Unless Otherwise Noted),” on page 175, added tSLIV
– Bit syntax throughout the datasheet, e.g. from CS02:0 to CS0[2:0].
222 ATtiny25/45/85
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223
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14. Updated “Bit 0” in “PRR – Power Reduction Register” on page 39.
15. Added footnote to Table 8-3 on page 48.
16. Updated Table 10-5 on page 65.
17. Deleted “Bits 7, 2” in “MCUCR – MCU Control Register” on page 66.
18. Updated and moved section “Timer/Counter0 Prescaler and Clock Sources”, now
located on page 68.
19. Updated “Timer/Counter1 Initialization for Asynchronous Mode” on page 89.
20. Updated bit description in “PLLCSR – PLL Control and Status Register” on page 97
and “PLLCSR – PLL Control and Status Register” on page 107.
21. Added recommended maximum frequency in“Prescaling and Conversion Timing” on
page 129.
22. Updated Figure 17-8 on page 133 .
23. Updated “Temperature Measurement” on page 137.
24. Updated Table 17-3 on page 138.
25. Updated bit R/W descriptions in:
“TIMSK – Timer/Counter Interrupt Mask Register” on page 84,
“TIFR – Timer/Counter Interrupt Flag Register” on page 84,
“TIMSK – Timer/Counter Interrupt Mask Register” on page 95,
“TIFR – Timer/Counter Interrupt Flag Register” on page 96,
“PLLCSR – PLL Control and Status Register” on page 97,
“TIMSK – Timer/Counter Interrupt Mask Register” on page 106,
“TIFR – Timer/Counter Interrupt Flag Register” on page 106,
“PLLCSR – PLL Control and Status Register” on page 107 and
“DIDR0 – Digital Input Disable Register 0” on page 142.
26. Added limitation to “Limitations of debugWIRE” on page 144.
27. Updated “DC Characteristics” on page 166.
28. Updated Table 21-7 on page 171.
29. Updated Figure 21-6 on page 176.
30. Updated Table 21-12 on page 176.
31. Updated Table 22-1 on page 182.
32. Updated Table 22-2 on page 182.
33. Updated Table 22-30, Table 22-31 and Table 22-32, starting on page 193.
34. Updated Table 22-33, Table 22-34 and Table 22-35, starting on page 194.
35. Updated Table 22-39 on page 197.
36. Updated Table 22-46, Table 22-47, Table 22-48 and Table 22-49.
224 ATtiny25/45/85
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1. Updated “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24.
2. Updated “Default Clock Source” on page 31.
3. Updated “Low-Frequency Crystal Oscillator” on page 29.
4. Updated “Calibrated Internal Oscillator” on page 27.
5. Updated “Clock Output Buffer” on page 32.
6. Updated “Power Management and Sleep Modes” on page 35.
7. Added “Software BOD Disable” on page 36.
8. Updated Figure 16-1 on page 123.
9. Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 124.
10. Added note for Table 17-2 on page 129.
11. Updated “Register Summary” on page 205.
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2586N–AVR–04/11
28.11 Rev. 2586D-02/06
1. Updated Table 6-13 on page 30, Table 6-10 on page 29, Table 6-3 on page 26,
Table 6-9 on page 29, Table 6-5 on page 27, Table 9-1 on page 50,Table 17-4 on
page 139, Table 20-16 on page 163, Table 21-8 on page 172.
2. Updated “Timer/Counter1 in PWM Mode” on page 89.
3. Updated text “Bit 2 – TOV1: Timer/Counter1 Overflow Flag” on page 96.
4. Updated values in “DC Characteristics” on page 166.
5. Updated “Register Summary” on page 205.
6. Updated “Ordering Information” on page 209.
7. Updated Rev B and C in “Errata ATtiny45” on page 217.
8. All references to power-save mode are removed.
9. Updated Register Adresses.
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Table of Contents
Features ..................................................................................................... 1
2 Overview ................................................................................................... 4
2.1 Block Diagram ...................................................................................................4
3 About ......................................................................................................... 6
3.1 Resources .........................................................................................................6
3.2 Code Examples .................................................................................................6
3.3 Capacitive Touch Sensing .................................................................................6
3.4 Data Retention ...................................................................................................6
i
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7.1 Sleep Modes ....................................................................................................35
7.2 Software BOD Disable .....................................................................................36
7.3 Power Reduction Register ...............................................................................37
7.4 Minimizing Power Consumption ......................................................................37
7.5 Register Description ........................................................................................38
9 Interrupts ................................................................................................ 50
9.1 Interrupt Vectors in ATtiny25/45/85 .................................................................50
9.2 External Interrupts ...........................................................................................51
9.3 Register Description ........................................................................................53
ii ATtiny25/45/85
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iii
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18.5 Limitations of debugWIRE .............................................................................144
18.6 Register Description ......................................................................................144
iv ATtiny25/45/85
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v
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28.11 Rev. 2586D-02/06 .........................................................................................226
28.12 Rev. 2586C-06/05 .........................................................................................226
28.13 Rev. 2586B-05/05 ..........................................................................................226
28.14 Rev. 2586A-02/05 ..........................................................................................226
vi ATtiny25/45/85
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ATtiny25/45/85
vii
2586N–AVR–04/11
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2586N–AVR–04/11