Microprocessor Programming

and Interfacing
Basic Digital Devices

Dr. Suvadip Batabyal

Dept. of CSIS
BITS Pilani, Hyderabad

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Objective
• Review digital electronics needed for MP hardware
design.

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 Analog and Digital Signal

V
V
+5 +5
1 0 1

Time Time

–5 –5

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Binary Logic

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Binary Variables
 Binary values
 High and Low
 True and False
 1 and 0
 Yes or No
• Basic binary
operations
 AND
 OR
 NOT

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Binary Logic
Binary Logic - Binary variables & set of logical operations

Binary variables represented by alphabets

Three basic logical operations

AND A B Y
0 0 0
0 1 0
1 0 0
1 1 1
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Binary Logic
Digital Design
Binary Logic - Binary variables & set of logical operations

Binary variables represented by alphabets

Three basic logical operations

A B Y
AND 0 0 0
0 1 1

OR 1 0 1
1 1 1

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
 Binary Logic
Binary Logic - Binary variables & set of logical operations

Binary variables represented by alphabets

Three basic logical operations

AND
A Y
0 1
OR 1 0

NOT
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Binary Logic
Digital Design
Binary Logic - Binary variables & set of logical operations

Binary variables represented by alphabets

Three basic logical operations Logic Gates

AND

OR
Realised ?

NOT
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Masking

0 1 1 0 1 0 1 1
0 0 1 1 1 1 0 0
0 0 1 0 0

0 0 1 0 1 0 0 0

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Concatenation
0 0 1 1

1 0 1 1
0 0 0 0

0 0 0 0

0 0 1 1 1 0 1 1

0 0 1 1
Shift &
0 0 1 1 1 01 1
OR
1 0 1 1

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 NAND-NOR Implementations
NAND gate realization

A A’

(A’B’)’

B = (A’)’ + (B’)’
B’
=A+B
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 NAND-NOR Implementations
NOR gate realization

A A’
(A’ + B’)’

= (A’)’ . (B’)’
B B’ =A.B

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 XOR
x y z
0 0 0
0 1 1 0 0 1 1
1 0 1
1 1 0
1 0 0 0
Comparator

1 0 1 1

Z  X .Y  X .Y

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 Inverter

x z
0 1
1 0

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 Timing Diagram

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 Three-State Gate
ENB

X Y X

ENB X Y
0 X High imp (Z)

1 0 0
1 1 1

The Output is Low The Output is High High Impedance

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 Tri-state bus

Active low Active high

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Tri-state bus
1
0

D0
D0

Data-in
1

D1 D0
D1

D2
D2

D3
D3

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Example
• The output of below block is driven by 4 inputs. All the inputs
and output are 1 bit width. The selection of the input is done by D0
the two address bits A0 and A1 and En’ as per truth table given D1
below. Design the block using logic gates Output
D2
2

D3

A0 A1 En/

A1 A0 En/ Output
x x 1 High Imp
0 0 0 D0
0 1 0 D1
1 0 0 D2
1 1 0 D3

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Fan-out
 I OH I OL 
min 
Fan _ out  max  I , I 
 IH IL 
 max(
min Logic H output fanout, Logic L output fanout )

• This means that each gate can drive 10 other gates in the same family
without getting out of its guaranteed range of operation.

• In cases where more than 10 gates are connected to the output of a

single gate of this family, the output voltage levels will degrade and the
gate will slow down.

• Modern MOS logic families have a fan-out of about 50, since each gate
must source or sink a current only during the transition from H to L
or L to H.

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 Multiplexer (2-to-1)

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 Multiplexer (4-to-1)

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 Multiplexer (8-to-1)

Note the
Enable
input

This is
Active Low
Output

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 De-multiplexer

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 1-to-8 Demultiplexer

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 Registers

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 Thank You.

Questions???

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