Spider - Tle7238Gs: 8 Channel High-Side and Low-Side Relay Switch With Limp Home Mode
Spider - Tle7238Gs: 8 Channel High-Side and Low-Side Relay Switch With Limp Home Mode
Spider - Tle7238Gs: 8 Channel High-Side and Low-Side Relay Switch With Limp Home Mode
0, October 2008
SPIDER - TLE7238GS
Automotive Power
TLE7238GS
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 l Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Limp Home Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Channels 4 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3 Inductive Output Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.6 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2 Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.3 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.4 Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.5 Loss of Vbb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8 Diagnostic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.2 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.1 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.2 Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.3 SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.4 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.5 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1 Overview
Features
• 8 bit SPI for diagnostics and control, providing daisy chain capability
• Very wide range for digital supply voltage
• Two configurable input pins offer complete flexibility for
PWM operation
• Stable behavior at under voltage
• Green Product (RoHS compliant)
• AEC Qualified
PG-SSOP-24-5
Description
The TLE7238GS is an eight channel high-side and low-side power switch in PG-SSOP-24-5 package providing
embedded protective functions. It is especially designed for standard relays and LEDs in automotive applications.
The output stages incorporate two low-side, four high-side and two auto configuring high-side or low-side
switches.
A serial peripheral interface (SPI) is utilized for control and diagnosis of the device and the load. For direct control,
there are two input pins available.
The power transistors are built by N-channel power MOSFETs. The device is monolithically integrated in
Smart Power Technology.
Overview
Protective Functions
• Over load and short circuit protection
• Thermal shutdown
• Electrostatic discharge protection (ESD)
Diagnostic Functions
• Latched diagnostic information via SPI
• Open load detection in OFF-state
• Over load detection in ON-state
• Over temperature
Applications
• Especially designed for driving relays and LEDs in automotive applications
• All types of resistive and inductive loads
• Suitable to switch 5 V power supply lines by auto configuring channels
Overview
Detailed Description
The TLE7238GS is an eight channel high-side and low-side relay switch providing embedded protective functions.
The output stages incorporate two low-side switches (0.9 Ω per channel), four high-side switches (two channels
with 0.9 Ω and two channels with 1.6 Ω) and two auto-configuring high-side or low-side switches (0.9 Ω per
channel). The auto-configuring switches can be utilized in high-side or low-side configuration just by connecting
the load accordingly. They are also suitable to switch a 5 V supply line in high-side configuration. Protective and
diagnostic functions adjust automatically to the chosen configuration.
The 8 bit serial peripheral interface (SPI) is utilized for control and diagnosis of the device and the loads. The SPI
interface provides daisy chain capability in order to assemble multiple devices in one SPI chain by using the same
number of micro-controller pins.
Furthermore, the TLE7238GS is equipped with two input pins that can be individually routed to the output control
of each channel thus offering complete flexibility in design and PCB-layout. The input multiplexer is controlled via
SPI.
In limp home mode (fail-safe mode), the input pins are directly routed to the configurable output channels 4 and
5. The limp home mode operates independently of digital power supply and is activated via pin LHI.
The device provides full diagnosis of the load via open load, over load and short circuit detection. SPI diagnosis
flags indicate latched fault conditions that may have occurred.
Each output stage is protected against short circuit. In case of over load, the affected channel switches off. There
are temperature sensors available for each channel to protect the device against over temperature.
The device protects itself with a build in reverse polarity protection which prohibits intrinsic current flow through
the logic during reverse polarity. However the output stages still incorporate a reverse diode where current can
flow through during reverse polarity.
The power transistors are built by N-channel power MOSFETs. The inputs are ground referenced CMOS
compatible. The device is monolithically integrated in Smart Power Technology.
Block Diagram
2 Block Diagram
VBB
temperature
power supply
sensor
low-side
diagnosis register gate control
SUB
Overview _5_GS.emf
Block Diagram
2.1 Terms
Figure 2 shows all terms used in this data sheet.
Vbat
IS
IOUT_S0 VDS0
VBB
OUT0
I OUT_S 1 VS 0 VDS1
OUT1
ILHI I OUT_S 2 VS1 V DS2
LHI OUT2
VLHI IIN1 I OUT_S 3 VS 2 VDS3
IN1 OUT3
VIN1 IIN2 I OUT_D4 V S3
IN2 TLE7238GS D4
VIN 2 IDD I OUT_S 4 VDS4 V D4
VDD S4
VDD I CS I OUT_D5 VS 4
CS D5
V CS ISCLK I OUT_S 5 VDS5 VD5
SCLK S5
VSCLK ISI I OUT_D6 VS 5
SI OUT6
VSI ISO I OUT_D7 VDS6
SO OUT7
VSO SUB GND VDS 7
I GND
Terms_5_GS.emf
Figure 2 Terms
In all tables of the electrical characteristics is valid:
Channel related symbols without channel number are valid for each channel separately (e.g. VDS specification is
valid for VDS0 … VDS7). In order to make the description of output currents easier, the load current IOut is equivalent
to the drain current IOUT_D in low-side configuration and the source current IOUT_S in high-side configuration.
All SPI register bits are marked as follows: ADDR.PARAMETER (e.g. ICR01.INX1). In SPI register description,
the values in bold letters (e.g. 0) are default values.
Pin Configuration
3 Pin Configuration
(top view )
Sub 1 24 VBB
Sub 2 23 OUT0
OUT1 3 22 OUT2
OUT3 4 21 VDD
LHI 5 20 CS
IN1 6 19 SCLK
IN2 7 18 SI
D5 8 17 SO
OUT7 9 16 D4
S5 10 15 OUT6
Sub 11 14 S4
Sub 12 13 GND
PG-SSOP -24-5.emf
Pin Configuration
Electrical Characteristics
4 Electrical Characteristics
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Absolute Maximum Ratings1)
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. max.
Power Supply
4.1.1 Power supply voltage Vbb -16 40 V -16V max. 2 minutes
4.1.2 Digital supply voltage VDD -0.3 5.5 V –
4.1.3 Power supply voltage for full short circuit Vbat(SC) 0 28 V –
protection (single pulse)
(Tj = -40 °C … 150 °C)
Power Stages
4.1.4 Load current IL A –
channel 0, 1, 4, 5, 6, 7 -0.5 0.5
channel 2, 3 -0.25 0.25
4.1.5 Voltage at power transistor VDS – 41 V –
4.1.6 Power transistor’s source voltage VOut_S -16 – V –
4.1.7 Power transistor’s drain voltage VOut_D – 41 V –
2)
4.1.8 Max. energy dissipation one channel single EAS mJ
pulse for ch. 0, 1, 4, 5, 6, 7
– 65 Tj(0) = 105 °C
ID(0) = 0.35 A
– 50 Tj(0) = 150 °C
ID(0)= 0.250 A
2)
4.1.9 Maximum energy dissipation one channel EAR mJ
repetitive pulses for ch. 0, 1, 4, 5, 6, 7
1 · 104 cycles – 18 Tj(0) = 105 °C
ID(0) = 0.250 A
1 · 106 cycles – 13 Tj(0) = 105 °C
ID(0) = 0.220 A
2)
4.1.10 Max. energy dissipation one channel single EAS mJ
pulse for ch. 2,3
– 50 Tj(0) = 105 °C
ID(0) = 0.250 A
– 30 Tj(0) = 150 °C
ID(0)= 0.250 A
Electrical Characteristics
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Absolute Maximum Ratings1)
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. max.
2)
4.1.11 Maximum energy dissipation one channel EAR mJ
repetitive pulses for ch. 2,3
1 · 104 cycles – 12 Tj(0) = 105 °C
ID(0) = 0.180 A
1 · 106 cycles – 11 Tj(0) = 105 °C
ID(0) = 0.180 A
Logic Pins
3)
4.1.12 Voltage at input pins VIN -0.3 VDD + 0.3 V
4.1.13 Voltage at LHI pin VLHI -0.3 5.5 V –
3)
4.1.14 Voltage at chip select pin VCS -0.3 VDD + 0.3 V
3)
4.1.15 Voltage at serial clock pin VSCLK -0.3 VDD + 0.3 V
3)
4.1.16 Voltage at serial input pin VSI -0.3 VDD + 0.3 V
3)
4.1.17 Voltage at serial output pin VSO -0.3 VDD + 0.3 V
Temperatures
4.1.18 Junction Temperature Tj -40 150 °C –
4.1.19 Storage Temperature Tstg -55 150 °C –
ESD Susceptibility
4.1.20 ESD susceptibility on all pins VESD -2 2 kV HBM4)
1) not subject to production test
2) Pulse shape represents inductive switch off: IL(t) = IL(0) * (1 - t / tpulse); 0 < t < tpulse
3) VDD + 0.3 V < 5.5 V
4) ESD susceptibility, HBM according to EIA/JESD 22-A114
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
Electrical Characteristics
Thermal Resistance1)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
2)
4.3.1 Junction to Case, bottom RthJC,back – – 25 K/W
2)
4.3.2 Junction to Case, top RthJC,top – – 25 K/W
2)
4.3.3 Junction to Pin (1,2,11 or 12) RthJPin – – 17 K/W
3)
4.3.4 Junction to Ambient RthJA,min – 90 – K/W
(1s0p, min. footprint)
4)
4.3.5 Junction to Ambient RthJA,300 – 70 – K/W
(1s0p+300mm2Cu)
5)
4.3.6 Junction to Ambient RthJA,600 – 65 – K/W
(1s0p+600mm2Cu)
6)
4.3.7 Junction to Ambient (2s2p) RthJA,2s2p – 55 – K/W
Power Supply
5 Power Supply
The TLE7238GS is supplied by two supply voltages Vbb and VDD. The Vbb supply line is connected to a battery
feed and used by the power switches and by an integrated power supply for the register banks. There is an under
voltage reset function implemented for the Vbb power supply. After start-up of the power supply, all SPI registers
are reset to their default values and the device is in sleep mode (standby). The SPI command CMD.WAKE = 1 is
switching the device to operation mode (ON), while a command CMD.STB = 1 send the device to sleep mode
(standby) again.
The VDD supply line is used by the SPI shift register related circuitry and for driving the SO line. As a result, the
daisy chain function is available as soon as VDD is provided in the specified range independent of Vbb. A capacitor
between pins VDD and GND is recommended (especially in case of EMI).
Operation Modes
VBB 0V 0V 0V 12 V 12 V 12 V 12 V
VDD 0V 5V 5V 0V 0V 5V 5V
LHI X 0V 5V 0V 5V 0V 5V
Switches operating - - - ✓ ✓ ✓ ✓
Limp Home - - - - ✓ - ✓
SPI & daisy-chain - ✓ ✓ - - ✓ ✓
Register Banks reset reset reset ✓ reset ✓ reset
Diagnostic functions - - - ✓ - ✓ -
5.3 Reset
There are several reset trigger implemented in the device. A reset switches off all channels and sets the registers
to default values. After any kind of reset, the transmission error flag (TER) is set.
Under Voltage Reset:
During this device condition a read on SPI always delivers the Standard Diagnostic Frame with a TER flag.
This under voltage reset is released when all the supply voltages levels are above under voltage threshold.
Power Supply
Reset Command: There is a reset command available to reset all register bits of the register bank and the
diagnosis registers. As soon as CMD.RST = 1, a reset is triggered.
Limp Home Mode: In limp home mode, the SPI write-registers are reset. The SPI interface is operating normally,
so the limp home bit LHI as well as the diagnosis flags can be read, but no command is accepted until the device
leaves the Limp home operation.
Power Supply
1)
– – 12 mA Vbb = 16 V
all diagnosis off
5.4.4 Sleep mode current with IS(Sleep) µA Vbb = 16 V
disconnected loads (stand by) VLHI = 0 V
AWK= 0
– – 10 Tj = 25 °C1)
– – 13 Tj = 85 °C 1)
– – 20 Tj = 150 °C
Digital Power Supply VDD
5.4.5 Logic supply voltage VDD 3.0 – 5.5 V
5.4.6 Under voltage reset threshold VDD(PO) – – 3.0 V
voltage
5.4.7 Logic supply current IDD – – 0.2 mA fSCLK = 0 Hz
VCS = 0 V
AWK= 1
VCS = 0V
5.4.8 Logic supply sleep mode current IDD(Sleep) µA VCS = VDD
AWK = 0
– – 20 Tj = 25 °C1)
– – 20 Tj = 85 °C 1)
– – 40 Tj = 150 °C
Timings
1)
5.4.9 Sleep mode wake-up time twu(Sleep) – – 200 µs
1)
5.4.10 Vbb under voltage reset delay time tbb(UVR) – – 1 µs
1)
5.4.11 VDD under voltage reset delay time tDD(UVR) – – 1 µs
1) Not subject to production test, specified by design.
Note: Characteristics show the deviation of parameter at the given supply voltage and junction temperature.
Typical values show the typical parameters expected at Vbb = 13.5 V, VDD = 5.0 V, Tj = 25 °C.
Power Stages
6 Power Stages
The TLE7238GS is an eight channel high-side and low-side relay switch. The power stages are built by N-channel
vertical power MOSFET transistors. The gates of the high-side switches are controlled by charge pumps.
Channel 7
Channel 6
Channel 5
Channel 4
IN1 Channel 3
Channel 2
IIN1 Channel 1
Channel 0
0
IN2
1
IIN2
INX0
InputLogic.emf
Power Stages
V bb
high side low side
VBB L,
channel channel IL RL
OUT ID
VD
V DS(CL)
VDS(CL)
OUT IS
V S(CL) VS
L,
GND IL GND
RL
OutputClamp.emf
V bb – V D(CL) RL ⋅ IL L
E = V D(CL) ⋅ ------------------------------- - + I L ⋅ ------
- ⋅ ln 1 – ------------------------------- Low-side (1)
RL V bb – V D(CL)
R L
V S(CL) R L ⋅ I L L
E = ( V bb – V S(CL) ) ⋅ --------------- - + I L ⋅ ------
- ⋅ ln 1 – --------------- High-side (2)
RL V S(CL) RL
1 2 V bb
E = --- LI L ⋅ 1 – -------------------------------
- Low-side (3)
2 V bb – V D(CL)
1 2 V bb
E = --- LI L ⋅ 1 – ---------------
- High-side (4)
2 V S(CL)
The maximum energy, which is converted into heat, is limited by the thermal design of the component.
Power Stages
IN
tON tOFF t
VDS
80%
20%
t
SwitchOn .emf
Power Stages
Unless otherwise specified: VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 °C to +150 °C
typical values: VDD = 5.0 V, VBAT = 13.5 V, Tj = 25 °C
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Output Characteristics
6.5.1 On-State resistance RDS(ON) Ω
channel 0, 1, 4, 5, 6, 7 – IL = 220 mA
0.9 – Tj = 25 °C
– 1.4 1.9 Tj = 150 °C
channel 2, 3 – IL = 110 mA
1.6 – Tj = 25 °C
– 2.6 3.9 Tj = 150 °C
6.5.2 Nominal load current IOut(nom) mA all channels on
Ta = 100 °C
Tj,max = 150 °C
based on Rthja
1)
channel 0, 1, 4, 5, 6, 7 260 380 –
1)
channel 2, 3 130 175 –
6.5.3 Output leakage current in sleep mode IOut(Sleep) µA VDS = 13.5 V
– – 1 Tj = 25 °C1)
– – 2 Tj = 85 °C 1)
– – 5 Tj = 150 °C
6.5.4 Output clamping voltage VOUT_S(CL) – – -16 V –
VOUT_DS(CL) 41 – – V –
Input Characteristics
6.5.5 L level of pin IN & LHI VIN(L) 0 – 0.6 V –
6.5.6 H level of pin IN & LHI VIN(H) 1.8 – 5.5 V –
1)
6.5.7 Input voltage hysteresis at pin IN ∆VIN – 0.1 – V
6.5.8 L-input pull-down current through pin IN IIN(L) 1.5 – – µA VIN = 0.6 V 1)
6.5.9 H-input pull-down current through pin IN IIN(H) 10 40 80 µA VIN = 5 V
Timings
6.5.10 Turn-on time tON µs Vbb = 13.5 V
VDS = 20% Vbat resistive load
channel 0, 1,4,5 – – 100 IDS= 250 mA
channel 2, 3 – – 100 IDS= 120 mA
channel 6,7 – – 100 IDS = 250 mA
6.5.11 Turn-off time tOFF µs Vbb = 13.5 V
VDS = 80% Vbb resistive load
channel 0, 1, 4, 5 – – 100 IDS = 250 mA
channel 2, 3 (HS) – – 100 IDS = 120 mA
channel 6, 7 (LS) – – 100 IDS = 250 mA
1) Not subject to production test, specified by design.
Power Stages
ICR01 000B
3 2 1 0
INX1 INX0
rw rw
ICR23 001B
3 2 1 0
INX3 INX2
rw rw
ICR45 010B
3 2 1 0
INX5 INX4
rw rw
ICR67 011B
3 2 1 0
INX7 INX6
rw rw
Protection Functions
7 Protection Functions
The device provides embedded protective functions. Integrated protection functions are designed to prevent IC
destruction under fault conditions described in this data sheet. Fault conditions are considered as “outside” normal
operating range. Protection functions are not designed for continuous repetitive operation.
IN
t
ID0
I D0(OV L)
tOFF(OV L)
CPL = 1b t
D0 = 1b D0 = 00b
OverLoad.emf
Protection Functions
Diagnostic Features
8 Diagnostic Features
The SPI of TLE7238GS provides diagnosis information about the device and about the load. The diagnosis
information of the protective functions of channel n is latched in the diagnosis flags Dn. It is cleared by the SPI
command CMD.CPL = 1. The CPL command clears itself with the next valid SPI communication frame.
The open load diagnosis of channel n is latched in the diagnosis flag OLn. This flag is cleared by reading the
according diagnosis register.
Following table shows possible failure modes and the according protective and diagnostic action.
Diagnostic Features
Diagnostic Features
DR01 00B
3 2 1 0
OL1 D1 OL0 D0
r r r r
DR23 01B
3 2 1 0
OL3 D3 OL2 D2
r r r r
DR45 10B
3 2 1 0
OL5 D5 OL4 D4
r r r r
DR67 11B
3 2 1 0
OL7 D7 OL6 D6
r r r r
CMD
Command Register 110B
3 2 1 0
Diagnostic Features
DCCR0 100B
3 2 1 0
DCCR1 101B
3 2 1 0
SO CS MSB 6 5 4 3 2 1 LSB
SI MSB 6 5 4 3 2 1 LSB
CS
SCLK
time
SPI.emf
TER
SI OR 1 SO
0
SO
SI SPI
S
CS
SCLK
S
TER.emf
SI SO SI SO SI SO
MO SPI SPI SPI
CS
SCLK
CS
SCLK
CS
SCLK
MI
MCS
MCLK
SPI_DasyChain.emf
MCS
MCLK
time
SPI_DasyChain2.emf
CS1) 7 6 5 4 3 2 1 0
Write Register Command
SI 1 ADDR DATA
Read Register Command
SI 0 ADDR x x 0 RB
Read Standard Diagnosis
SI 0 x x x x x 1 x
Standard Diagnosis
S TER 0 0 AWK LH D67 D45 D23 D01
O
Second Frame of Read Command
S TER 0 1 ADDR (Diagnosis) DATA
O
S TER 1 ADDR (Control) DATA
O
1) This bit is valid between CS hi -> lo and first SCLK lo -> hi transition.
Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame,
the output at SPI signal SO will contain the requested information. Any command can be executed in the
second frame.
Standard Diagnosis:
0.7Vcc
SCLK
0.2Vcc
tSI(su) tSI(h)
0.7Vcc
SI
0.2Vcc
0.7Vcc
SO
0.2Vcc
SPI Timing.emf
Unless otherwise specified: VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 °C to +150 °C
typical values: VDD = 5.0 V, VBAT = 13.5 V, Tj = 25 °C
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Input Characteristics (CS, SCLK, SI)
9.6.1 L level of pin 0 – 0.2*VDD V –
CS VCS(L)
SCLK VSCLK(L)
SI VSI(L)
9.6.2 H level of pin 0.5*VDD – VDD V –
CS VCS(H)
SCLK VSCLK(H)
SI VSI(H)
9.6.3 L-input pull-up current through CS ICS(L) 5 40 90 µA VCS = 0 V
VDD = 5 V
1)
9.6.4 H-input pull-up current through CS ICS(H) 2.5 – – µA
VDD = 5 V
VCS = 0.5*VDD
1)
9.6.5 L-input pull-down current through pin ISCLK(L) 1.5 – – µA
SCLK ISI(L) VDD = 5 V
SI VSCLK = VSI = 0.2*VDD
1)
9.6.6 H-input pull-down current through pin ISCLK(H) µA
SCLK ISI(H) 10 40 80 VDD= 5 V
SI VSCLK = VSI = VDD
Output Characteristics (SO)
9.6.7 L level output voltage VSO(L) 0 – 0.4 V ISO = +2 mA
9.6.8 H level output voltage VSO(H) VDD - – VDD ISO = -1.5 mA
0.4 V
9.6.9 Output tristate leakage current ISO(OFF) -10 – 10 µA VCS = VDD
Timings
9.6.10 Serial clock frequency fSCLK 0 – 5 MHz –
9.6.11 Serial clock period tSCLK(P) 200 – – ns –
1)
9.6.12 Serial clock high time tSCLK(H) 50 – – ns
1)
9.6.13 Serial clock low time tSCLK(L) 50 – – ns
1)
9.6.14 Enable lead time (falling CS to rising tCS(lead) 250 – – ns
SCLK)
1)
9.6.15 Enable lag time (falling SCLK to rising tCS(lag) 250 – – ns
CS )
1)
9.6.16 Transfer delay time (rising CS to tCS(td) 250 – – ns
falling CS )
1)
9.6.17 Data setup time (required time SI to tSI(su) 20 – – ns
falling SCLK)
1)
9.6.18 Data hold time (falling SCLK to SI) tSI(h) 20 – – ns
Unless otherwise specified: VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 °C to +150 °C
typical values: VDD = 5.0 V, VBAT = 13.5 V, Tj = 25 °C
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
9.6.19 Output enable time (falling CS to SO tSO(en) – – 200 ns CL = 20 pF 1)
valid)
9.6.20 Output disable time (rising CS to SO tSO(dis) – – 200 ns CL = 20 pF 1)
tri-state)
9.6.21 Output data valid time with capacitive tSO(v) – – 100 ns CL = 20 pF 1)
load
1) Not subject to production test, specified by design.
Package Outlines
10 Package Outlines
0.35 x 45˚
3.9 ±0.11) C
1.75 MAX.
0.19 +0.06
0.2 -0.1
(1.47)
8˚ MAX. 8˚ MAX.
0.2 -0.1
8˚ MAX.
0˚...8˚
0.65 B 0.1 B
0˚...8˚ 0.64 ±0.25
Seating Plane
0.25 ±0.05 2) 6 ±0.2
0.17 M C A B 24x 0.2 M C
24 13
1 12
A
8.65 ±0.11)
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.13 max.
3) JEDEC registration MO-137 variation AE GPS01214
Application Information
11 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
Figure 14 shows a simplified application circuit. Vdd need to be externally reverse polarity protected.
D1
Vbat
C1 Lowside
Loads
OUT2
D2
PWM IN1 OUT3
PWM IN2
D3
LHO LHI D4
S4
D5
S5
CS
SCLK
SPI uC
SI
SO
OUT6
OUT7
SUB GND
Cooling area
Highside
Loads
Application_LGS.emf
Revision History
12 Revision History
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.