Nexperia LOGIC Handbook 201029

LOGIC
APPLICATION
HANDBOOK
PRODUCT
FEATURES &
APPLICATION
INSIGHTS
Design Engineer’s Guide
Logic Application Handbook
Product Features and Application Insights

Copyright © Nexperia
October 2020
www.nexperia.com
ISBN 978-0-9934854-6-6
All rights reserved.

No part of this publication may be reproduced or
distributed in any form or by any means without
the prior written permission of the author.
Contributors
Christian Backhaus
Burkhard Laue
Michael Lyons
Thomas Wolf
Ashish Jha
Ghislaine Jilisen Janssen
Sven Walczyk
Vikram Singh Parihar
Robby Ferdinandus
Roland Peters
Olaf Vogt
Introduction 1
Logic basics, Generic Logic product properties 2
Power considerations for CMOS and BiCMOS logic devices 3
Timing aspects of discrete devices 4
Interfacing aspects of logic devices 5
Analog and Logic Product Segmentation 6
Packages 7
Automotive Quality 8
Logic Families 9
FAQ 10
Appendix
Abbreviations
Index
Legal information
Preface
Nexperia is a leading expert in diodes, bipolar transistors, ESD protection devices,
MOSFETs, GaN FETs and analog & logic ICs.
With an absolute focus on efficiency, Nexperia consistently produces

the essential semiconductors required by every electronic design in the world:
more than 90 billion annually. Products that are benchmarks in efficiency —
in process, size, power and performance — with industry-leading small packages
that save valuable energy and space.
Our extensive portfolio of standard functions meets both the demands of today’s
state-of-the art applications and the stringent standards set by the Automotive
Industry. Through our continued efforts in innovation, reliability and support,
we maintain the leading position in all our key product segments: Diodes and
Transistors, ESD protection, MOSFETs, and Analog and Logic ICs. We develop and
deliver benchmark solutions for today’s and tomorrow’s market requirements,
drawing on a heritage of over 60 years’ expertise in Semiconductors as the former
Standard Products divisions of NXP and Philips.
Our successful record in innovation is the result of varied yet streamlined R&D.
We combine the latest technologies with efficient processes, helping us to serve
the world’s most demanding industries with world-class products.
Nexperia Design Engineer’s Guides:

Our program of Design Engineer’s Guides has one key goal: We want to share our
Expertise with you and help you to optimize your electronic designs. It is a
collection of technical and application insights “from Engineer to Engineer”.
The first Nexperia Design Engineers Guide, released in 2017, is our MOSFET
Application Handbook. In this handbook, our engineers focus on how to use
MOSFETs in specific applications and what the key and critical MOSFET parameters
are, considering aspects like thermal conditions etc.
The Second Technical Guide of this series was launched in 2018: Our ESD Application
Handbook. This ESD Application Handbook is focusing on Protection Concepts,
Testing and Simulation for Modern Interfaces. We got so far a lot of positive
feedback by our Engineering Community from Customers representing all
Industries word wide. In addition to this ESD Application Handbook, Nexperia is also
offering on-site Technical ESD Seminars to share our insights with our customers,
cross all relevant applications like Automotive, Mobile Communication, Consumer,
Computing and Industrial. At the end we want to help minimize the risk of ESD
nexperia | Design Engineer’s Guide
damage — supporting the design community in protecting applications and

products against ESD issues. Both Design Engineer’s Guides are also available in
Chinese Version.
Introducing the Logic Application Handbook

“Why a Logic Handbook?” You may ask. Well, even though logic may have been
around since the days when engineers still used slide rules, today logic is still an
essential part of many embedded designs.
Of course, it is the go-to resource for I/O expansion and interfacing between
analog and digital domains, but in many ways, today’s designers need logic more
than ever. Why? Because today’s systems need to be smaller, more power efficient,
and more portable than ever before. That means managing tight layouts, and
dealing with looped traces, which can generate cross-talk and create signal-
integrity issues. It also means working with multi-layer boards, implementing
real-time responses to real-world events, and supporting multitasking operations.
In many cases, the right logic device makes these things easier to manage, and
helps optimize operation.
In fact, while Logic is great for making these kind of minor modifications and
fine-tuning performance in the later design stages, that’s not all it can do! Today’s
logic devices let developers add features and improve functionality, so they can
meet their design requirements right from the start, even before they need to
think about last-minute revisions.
• In systems that use application-specific integrated circuits (ASICs),

logic gates can be used to provide control or “glue” functions. Modern
logic families include features, such as overvoltage tolerance, that enable
them to be used as glue logic between ASICs that use different supply
voltages. In some cases, this can extend the lifetime of legacy ASICs.
• In systems that use a microcontroller (MCU), logic products are used for
low-cost I/O expansion. Shift registers are used for digital I/O expansion,
and analog switches are used to multiplex analog sensor inputs. The
combination of the two enables the selection of lower-pin count MCUs
with fewer analog-to-digital converters. When used this way, standard
logic enables true cost optimization of an application.
• In tablets and laptops, logic can be used for battery charging and
discharging blocks, and to provide standby mode, power-down, and
start-up control sequences. In docking stations and systems that support
multiple displays, logic provides the bus switches, resets, and audio blocks
that reduce the impact of noisy signals, and can be used to buffer the
clock and data signals.
• In mobile devices such as smartphones, tablets, and cameras,

logic provides multiplexing, buffering, and level-translation functions
for the baseband, RF interfaces, memory, and other peripherals.
• In external speakers and other high-end audio equipment logic buffers

are used to buffer the clock, sync, and data signals sent to the audio
interface and docking station.
Over the last 60 years, Nexperia — starting as Philips Semiconductors and then

incorporating the experience of Signetics — has supported growing global demand
for logic. Today, as the No. 1 volume logic supplier in the world, Nexperia offers a
broad variety of industry-leading solutions proudly serving customers across a
variety of market segments. Our reputation as a trusted supplier of exceptionally
high quality is reinforced by our No. 1 position in the automotive industry.
We proudly invite you to study our 3rd Nexperia Design Engineer’s Guide, our
Logic Application Handbook. The Table of Content makes it easy for you to navigate
to the key chapters of interest. This book is another key milestone to build the
Technical Nexperia Encyclopedia.
Olaf Vogt Robby Ferdinandus

Director Application Marketing, Global Head of Marketing,
Nexperia Nexperia
Table of Contents
Chapter 1
Introduction��17
Chapter 2
Logic basics, Generic Logic product properties
2.1 Basic logic gate functions�� 25

2.2 Logic gates�� 26
2.3 Storage elements�� 32
2.4 Switches�� 33
2.5 Logic data sheet parameters�� 34
2.6 Limiting values�� 35
2.7 Recommended operating conditions�� 35
2.8 Static characteristics�� 36
2.9 Dynamic characteristics�� 38
Chapter 3
Power considerations for CMOS and BiCMOS logic devices
3.1 Static considerations�� 42

3.2 Dynamic considerations�� 44
3.2.1 Duty cycle considerations with unbalanced outputs�� 46
3.2.2 Power dissipation due to slow input rise/fall times�� 46
3.2.3 Process family related dynamic power dissipation�� 47
3.3 Power dissipation capacitance�� 48
3.3.1 Example CPD calculations�� 49
3.4 Using CPD to calculate power dissipation�� 51
3.4.1 CMOS Device Calculation�� 51
3.4.2 BiCMOS Device Calculation�� 52
3.5 Results and conclusion�� 53
Chapter 4
Timing aspects of discrete devices
4.1 Synchronous and asynchronous logic�� 58

4.2 Propagation delay time of a device�� 59
4.3 Timing parameters of Flip Flops and Latches�� 60
4.4 Skew definitions�� 61
4.4.1 Output Skew tSK(o)�� 61
4.4.2 Process Skew tSK(x)�� 62
4.4.3 Pulse Skew tSK(p)�� 62
4.5 Meta stability and its mitigation�� 62
4.6 Maximum frequency information�� 64
Chapter 5
Interfacing aspects of logic devices
5.1 Application requirements for interfacing�� 66

5.2 Schmitt Trigger inputs�� 77
5.3 IOFF mechanism and purpose�� 79
5.4 Ground and VCC bounce�� 80
5.5 Bus Hold�� 82
5.6 Source Termination�� 84
Chapter 6
Analog and Logic Product Segmentation
6.1 Analog ICs�� 90

6.2 Asynchronous Interface Logic�� 93
6.2.1 Buffers, Drivers, Inverters�� 93
6.2.2 Transceivers�� 94
6.2.3 Schmitt-Triggers�� 95
6.2.4 Voltage Translators�� 96
6.2.5 Bi-directional translation with automatic sensing�� 98
6.3 Synchronous Logic��106

6.3.1 Flip Flops��106
6.3.2 Latch or D-flipflop with level controlled enable��107
6.3.3 Edge triggered flipflops and registers��109
6.3.4 Edge-controlled D-Flipflop��109
6.3.5 JK-Flipflop��110
6.3.6 Parallel-Registers��111
6.3.7 FIFO Registers��112
6.3.8 Counters��112
6.3.9 Monostable Multivibrator��115
6.4 Where to use Synchronous Interface Logic�� 116
Chapter 7
Packages
7.1 Standard Logic Packages��124

7.2 Mini Logic Packages��130
7.2.1 MicroPak (Extremely thin small outline no-leads)��130
7.2.2 PicoGate (Single, dual or triple gate functions in small packages)��137
7.2.3 Leads (PicoGate) or no leads (MicroPak)?��141
7.3 Package soldering aspects ��143
7.4 Thermal resistance of packages��149
7.5 Thermal characterization of packages –
Explanation and possible setup��153
Chapter 8
Automotive Quality��157
Chapter 9
Logic Families��161
9.1 The HC/HCT/HCU Logic Family��165

9.2 The AHC/AHCT Logic Family��175
9.3 The LVC Logic Family��185
9.4 The AVC Logic Family��201
9.5 The AUP Logic Family��212
9.6 The AXP Logic Family��227
9.7 The LVT/ALVT Logic Family��237
Chapter 10
FAQ��257
Appendix��269
Abbreviations��299
Index��303
Legal information��307
1
Chapter 1
Introduction
Introduction
17
1 nexperia | Design Engineer’s Guide
Nexperia logic history begins with some of the very first integrated logic devices in
Introduction
the 1970’s with the acquisition of Signetics. Nexperia technology is built upon
decades of logic development and research over the years from Signetics, Philips,
NXP and Nexperia.
Nexperia’s logic portfolio is already very extended and will grow further. A general
document for supporting the application of discrete logic devices, covering all
important aspects of applications design, is very useful for engineers and helps to
establish a common understanding for both Nexperia and the customers.
This handbook is dedicated to application and design engineers who are developing
and using electronic circuits, often within embedded systems for all kind of
applications. The demand for discrete logic devices is widespread. Many aspects of
system and board design have to be addressed and the usage of logic devices is
very often generating questions and support requirements which cannot be met
just by data sheets. In order to provide a compact and handy document, condensed
from application notes, customer support experience and general logic knowledge,
this book is meant to support development engineers who are dealing with logic
devices.
Digital systems are running at faster speeds, operating at lower voltages, and they
are becoming more integrated. Many functions can be integrated into FPGAs or
ASICs/SOCs, however, this does not mean that generic standard logic will disappear.
Designers may choose to design with standard logic for the following reasons:
• The addition of features in next generation products with lower power

consumption
• Space constraints requiring small packaging
• Bus driving capability
• Interfacing between mixed voltage systems and voltage level translation
• Need for hot insertion capability
• Need for bus switching.
• Need for I/O expansion of embedded systems
To create a content suitable for application engineers using Nexperia’s logic

devices, we are trying to take the designers point of view.
Each chapter of the book is addressing aspects of designing with logic devices and
the systems they are used in. We start with basics of logic theory and circuit
elements: logic equations, binary code and basic logic functions are introduced as
well as circuit design aspects like CMOS gate implementations. The explanation of
data sheet items is addressed and the associated properties of logic process
families.
18
1
Another aspect is the power consumption of logic devices in embedded circuits,
Introduction
here we provide the calculation methods and explain the dependencies on process
technology and topology.
As well as power, timing behavior needs to be calculated and must be understood

for a circuit design. In the timing chapter, we deliver information and explanations
for this.
Many behavioral aspects of logic devices need to be addressed when using them
interfacing other devices. These effects are explained in the chapter Interfacing
Aspects.
Background information about package types, soldering and footprints are

provided in an extra chapter Package. For further system integration items like
Simulation of PCB design we have created an extra chapter to enable users to
successfully integrate Nexperia’s logic devices into their embedded systems and
verify the system before production.
The logic process families and their specific properties are addressed in another
chapter with information about I/O characteristics and all technology specific
information useful for selecting the suitable process family for a dedicated
function.
Finally, frequently asked questions from customers are compiled in a chapter to

address the most popular support issues.
19
Introduction
20
2
Chapter 2

Logic basics,
Generic Logic product
properties
21
Digital electronic data processing uses binary numbers. Only two states exist, zero
and one. These states are also referred to as true and false. In electronics input
voltage ranges are defined to represent a logic low (zero) and a logic high (one).
Logic products can have inputs that are described as active high or active low. An
A ˄ 𝐴𝐴where
input = 01 = true is said to be an active
A ˅high
𝐴𝐴 =input
1 whereas an input where
0 = true is said to be an active low input.
Binary code
𝐴𝐴 ˄ 𝐵𝐵 = (𝐴𝐴 ˅ 𝐵𝐵) 𝐴𝐴 ˅ 𝐵𝐵 = (𝐴𝐴 ˄ 𝐵𝐵)
The binary numeral system is a positional numeral system with a base or radix of 2.
The single digits in a binary system are represented by 2n with n ≥ 0  20, 21, 22, 23,
24 …, in decimal = 1, 2, 4, 8, 16 …
! !
𝑃𝑃! = 𝐶𝐶!" × 𝑉𝑉!! × 𝑓𝑓! × 𝑁𝑁 + 𝐶𝐶! × 𝑉𝑉!! × 𝑓𝑓!
Below an example how a decimal number is converted to a binary number:
1317(10) =
1 * 210 + 0 * 29 + 1 * 28 + 0 * 27 + 0 * 26 + 1 * 25 +
0 * 24 + 0 * 23 + 1 * 22 + 0 * 21 + 1 * 20
1317(10) = 10100100101(2)
Each 1011
digit of a binary number is referred to as bit in logic nomenclature. Standard
+ 0011like adding, subtraction, multiplication and division work identical to
calculations
1110
decimal system. For example adding two numbers the digits can be added
sequentially while taking care of carry bits from the single operations.
Below the example of adding 1011 plus 0011 (decimal: 11 + 3). Starting from the
!of 1 to the next digit. 1+1+1 is 1 plus!a carry again.
𝑃𝑃!"#
lowest = 𝐶𝐶is!"
bit 1+1 ×a𝑉𝑉carry
0 plus
!! × 𝑓𝑓! × 𝑁𝑁 + 𝐶𝐶! × 𝑉𝑉!! × 𝑓𝑓!
In the next digit there is the 1 of the carry plus 0, so 1 as result. For the highest digit
1 + 0 delivers 1.
1011
+0011
Carry bits 1 1
1110
22 1

2
Boolean Algebra

For elementary algebra expressions are noted down in numbers normally. In
Boolean algebra the truth values false and true are used. These values can also be
denoted with bits or binary digits, represented by logical 0 or 1.
Basic Operations in Boolean algebra are the AND and OR operation as depicted in
Table 1. The AND operation delivers a true or 1 as result if all input values are
equal 1. For the two input variable example both A and B need to be equal 1 for a
result of 1, all other combinations deliver the result 0.
For the OR operation, all inputs need to be 0 to get a 0 as result. If at least one
input variable is 1 or true, the OR operation delivers a 1.
Table 1: Basic Boolean operations AND and OR

with 2 input values A and B
AND OR
A B A ˄ B A ˅ B
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 1
The AND and OR operation works in the same way if more than 2 variables are
involved.
An additional very important Boolean operation is the inversion. It is quite simple as

Table 2 shows. A zero input variable results in a result of 1 and vice versa for a 1 as
input.
Table 2: Boolean operation of Inversion
A A
0 1
1 0
23
Boolean algebra is identical for many rules if the operation ˅ (OR operation) is
replaced by an addition and the operation ˄ (AND operation) by a multiplication.

The following laws known from normal algebra are common with Boolean algebra
and called the monotone laws.
Associativity of ˄ . . . . . . . . . . . . . . . .A ˄ (B ˄ C) = (A ˄ B) ˄ C
Associativity of ˅ . . . . . . . . . . . . . . . .A ˅ (B ˅ C) = (A ˅ B) ˅ C
Commutativity of ˄ . . . . . . . . . . . . . . A ˄ B = B ˄ A
Commutativity of ˅ . . . . . . . . . . . . . . A ˅ B = B ˅ A
Distributivity of ˄ over ˅ . . . . . . . . . . . A ˄ (B ˅ C) = (A ˄ B) ˅ (A ˄ C)
Identity rule for ˄ . . . . . . . . . . . . . . . .A ˄ 0 = 0
Identity rule for ˅ . . . . . . . . . . . . . . . .A ˅ 1 = 1
There are additional laws that are valid in Boolean algebra but do not exist in
normal algebra:
Annihilation of ˅ . . . . . . . . . . . . . . . .A ˅ 1 = 1
Idempotence of ˄ . . . . . . . . . . . . . . . A ˄ A = A
Idempotence of ˅ . . . . . . . . . . . . . . . A ˅ A = A
Absorptions rules . . . . . . . . . . . . . . . A ˅ (A ˄ B) = A
. . . . . . . . . . . . . . . . . . . . . . . . .A ˄ (A ˅ B) = A
Distributivity of ˅ over ˄ . . . . . . . . . . . A ˅ (B ˄ C) = (A ˅ B) ˄ (A ˅ C)
The complementation rules are.
A ˄ 𝐴𝐴 = 0 A ˅ 𝐴𝐴 = 1
A very important rule is the so called de Morgan law. It can be used to optimize and
𝐴𝐴 ˄ 𝐵𝐵 = (𝐴𝐴
restructure ˅ designs.
logic 𝐵𝐵) 𝐴𝐴 ˅ 𝐵𝐵 = (𝐴𝐴
If inverted inputs are˄processed
𝐵𝐵) with an AND operation
this is identical to process these variables via an OR operation and to invert the
result. The same law can be applied if you process inverted input variables with an
OR operation. It is identical to have an AND operation for the variables
𝐶𝐶!" × 𝑉𝑉!! ! ×
𝑃𝑃! =result.
invert the
𝑓𝑓! × 𝑁𝑁 + 𝐶𝐶! × 𝑉𝑉!! ! × and
𝑓𝑓! to
A ˄ 𝐴𝐴 = 0
De Morgan laws:
A ˅ 𝐴𝐴 = 1
1317(10) =
1 * 210 + 0 * 2
𝐴𝐴 ˄ 𝐵𝐵 = (𝐴𝐴 9 + 1 * 28 + 0 * 2
˅ 𝐵𝐵) 7 + 0 * 2
𝐴𝐴 ˅ 𝐵𝐵 = (𝐴𝐴 6 + 1 * 25 +
˄ 𝐵𝐵)
0 * 2 + 0 * 2 + 1 * 2 + 0 * 2 + 1 * 2
4 3 2 1 0
Where:
1317
˄ = logic = = 10100100101
𝑃𝑃!(10)
AND,𝐶𝐶˅ = logic
!" × OR 𝑉𝑉!! ! × 𝑓𝑓(2)
!× 𝑁𝑁 + 𝐶𝐶! × 𝑉𝑉!! ! × 𝑓𝑓!
24 1011
1317(10) =
+ 0011
2
2.1 Basic logic gate functions

Inverter/ NOT Gate
The most simple gate function is the inverter. Below is the simple logic table of an
inverter.
Table 3: Inverter or NOT Gate
Input A Output Y
0 1
1 0
There are two styles of symbols commonly used for Gates. One is the ANSI/
IEEE Std 91/91a-1991 type, the other one is according IEC 60617-12. In English and
US publications the IEC symbols can be found seldomly only. So they do not reach
the high international relevance of the IEEE style.
mna108
mna109
A Y 1
Figure 2.1a | IEEE symbol of an Inverter Figure 2.1b | IEC symbol of an Inverter
25
2.2 Logic gates

In the logic portfolio basic functions are provided to enable the direct application
of Boolean algebra. For example, the logic component for the AND operation is
called an AND gate. Within electrical systems these gates are often referred to as
control logic
AND Gate
The 2-input AND function is depicted in Table 4. The output of an AND gate will
only be high (1) if all inputs are high. All other input combinations will result in a low
(0) at the output. In electronic systems with active high enable, an AND gate output
can be used to prevent enabling the system until certain conditions (e.g. power and
temperature status) monitored at the AND gate inputs are met. If either input is
held high the output will have the same state as the other input. This enables either
input to be used as an active high enable to gate data streamed on the other input.
In Figure 2.2 the symbols for a 2-input AND gate are depicted.
Table 4: 2-Input AND gate function table
Input A Input B Output Y
0 0 0
0 1 0
1 0 0
1 1 1
mna113
mna114
1 B 1
Y 4 & 4
2 A 2
Figure 2.2a | IEEE symbol of an AND gate Figure 2.2b | IEC symbol of an AND gate
26
2
NAND Gate

If the output of an AND gate is inverted another basic function, a NAND gate is
realized. The 2-input NAND function is depicted in Table 5. The output of a NAND
gate will only be low if all inputs are high. All other input combinations will result in
a high at the output. In electronic systems with active high enable, a NAND gate
output can be used to disable the system if a combination of undesired conditions
monitored at the NAND gate inputs have been met. If either input is held high the
output will have the inverted state of the other input. This provides an active high
gated inverter function.
In Figure 2.3 the symbols for a 2-input NAND gate are depicted.
Table 5: 2-Input NAND gate function table
0 0 1
0 1 1
1 0 1
1 1 0
mna097
1 mna098
1 B &
Y 4 4
2 A 2
Figure 2.3a | IEEE symbol of a NAND gate Figure 2.3b | IEC symbol of a NAND gate
27
OR Gate
The 2-input OR function is depicted in Table 6. The output of an OR gate will only
be low if all inputs are low. All other input combinations will result in a high at the
output. In electronic systems with active high enable, an OR gate output can be
used to enable the system if one or more conditions (e.g. automatic or manual
start) monitored at the OR gate inputs is true. If either input is held low the output
will have the same state as the other input. This enables either input to be used as
an active low enable to gate data streamed on the other input.
In Figure 2.4 the symbols for a 2-input OR gate are depicted.
Table 6: 2-Input OR gate function table
0 0 0
0 1 1
1 0 1
1 1 1
mna164
mna165
1 B 1
Y 4 ≥1 4
2 A 2
Figure 2.4a | IEEE symbol of an OR gate Figure 2.4b | IEC symbol of an OR gate
28
2
NOR Gate

If the output of an OR gate is inverted another basic function, a NOR gate is
realized. The 2-input NOR function is depicted in Table 7. The output of a NOR gate
will only be high if all inputs are low. All other input combinations will result in a low
at the output. In electronic systems with active high enable, a NOR gate output can
be used to disable the system if any undesired conditions monitored at the NOR
gate inputs have been met. If either input is held low the output will have the
inverted state of the other input. This provides an active low gated inverter
function.
In Figure 2.5 the symbols for a 2-input NOR gate are depicted.
Table 7: 2-Input NOR gate function table
0 0 1
0 1 0
1 0 0
1 1 0
mna103
1 mna165
1 B ≥1
Y 4 4
2 A 2
Figure 2.5a | IEEE symbol of a NOR gate Figure 2.5b | IEC symbol of a NOR gate
29
Exclusive-OR (XOR) Gate

The 2-input Exclusive-OR (XOR) function is depicted in Table 8. The output of a XOR
gate will only be high if only one of the inputs is high. All other input combinations
will result in a low at the output. In electronic systems with active high enable, an
XOR gate output can be used to enable the system if only one condition monitored
at the XOR gate inputs has been met. If either input is held low the output will have
the same state as the other input. If either input is held high the output will have
the inverted state of the other input. This provides a dynamically controlled device
that can stream data or inverted data.
In Figure 2.6 the symbols for a 2-input XOR gate are depicted.
Table 8: 2-Input Exclusive-OR-Gate
0 0 0
0 1 1
1 0 1
1 1 0
mna038
mna039
B 1
1 Y =1
A 4 4
2 2
Figure 2.6a | IEEE symbol of a XOR gate Figure 2.6b | IEC symbol of a XOR gate
30
2
Exclusive-NOR (XNOR) Gate

If an inverter is added behind an exclusive OR the function of an XNOR is realized.
The 2-input Exclusive-NOR (XNOR) function is depicted in Table 9. The output of a
XNOR gate will only be high if both inputs are the same. All other input
combinations will result in a low at the output. In electronic systems with active
high enable, an XOR gate output can be used to enable the system if both
conditions monitored at the XOR gate inputs are the same. If either input is held
high the output will have the same state as the other input. If either input is held
low the output will have the inverted state of the other input. This provides a
dynamically controlled device that can stream data or inverted data.
In Figure 2.7 the symbols for a 2-input XNOR gate are depicted.
Table 9: 2-Input Exclusive NOR-Gate
0 0 1
0 1 0
1 0 0
1 1 1
aaa-027780
aaa-027781
1 B 1 =1
Y 4 4
2
2 A
Figure 2.7a | IEEE symbol of a XOR gate Figure 2.7b | IEC symbol of a XOR gate
31
2.3 Storage elements

Flipflops
A flipflop is a circuit which has two stable conditions at the output. This logic
condition of a low or high state at the output does not depend on the actual
setting of control inputs only but also on the history. A flipflop can store a state for
an infinite time as long as a supply voltage is present. So it can store the
information of one bit.
There are several types of flipflops with different topologies.
Most simple is a so-called RS-flipflop. It can be set and reset via two inputs that
work level controlled.
A more important category of flipflops are D-flipflops. They have a data input D
and can store the state of this signal line. Storage can be controlled by an enable
signal. These flipflops are transparent from input to output as long as the enable
signal is set to high level. The last logical state is stored once the enable is turned
off.
The most important category of flipflops work with a so-called clock signal CLK. The
input signal is sampled and stored by the rising or falling edge of the clock. The
clock-driven flipflops are the basic block for many important circuits in logic
designs. These are multi-bit storage devices called registers as well as counters and
shift registers.
Logic devices from the standard families with storage stages have no internal
power-on circuitry applying a reset to the flipflops in the IC. If a defined start
condition for such devices is required, the application has to take care that after the
supply voltage is ramped up into the recommended VCC range, suitable controls are
provided to the IC to bring it into the desired state.
If the product has a reset pin, this control can be used to clear flipflops contained in
the design. This makes it easy to create a cleared state power-on condition. The
timing requirements for the reset have to be obeyed. It does not work to connect a
low active reset pin to the supply directly. Then VCC and reset pin ramp up together
and the device has no chance to perform a safe reset. In the FAQ section more
advice can be found how to secure a reliable power up behavior if this is required
by the target application.
A detailed explanation of flipflop types and more complex circuits designed with
this basic function can be found in Chapter 6 of this handbook.
32
2
2.4 Switches

Analog Switches
Analog switches are bi-directional transmission gates, consisting of a PMOS and a

NMOS transistor in parallel. They are used for switching rail to rail analog and low
frequency digital signals. There are many configurations of analog switch available.
Single pole single throw (SPST) is used in isolation applications. A single digital
control pin is used to turn the switch on or off connecting or isolating the signal
path. In the SP8T configuration three digital control pins are used to connect one
input/output to one of eight output/inputs. Due to the bi-directional feature of
analog switches the SP8T configuration is also known as an 8:1 analog multiplexer/
demultiplexer. In Figure 2.8 an SPDT configuration is shown. Two transmission
gates have one common terminal, the pole and two independent throw terminals.
This configuration uses a single digital control signal S to switch the pole terminal Z
to either of the throw terminals Y1 or Y2.
aaa-032003
aaa-032004
Y1
S 6
1 Y1
S Z
Z 4
3 Y0
Y0
Figure 2.8 | SPDT analog switch Figure 2.9 | Logic diagram SPDT switch
Many products include a control pin to allow the multiplexer to be enabled or

disabled. When disabled all switches are non-conducting (off). This enables the
poles of several devices to be connected to create larger multiplexer/
demultiplexing solutions. Devices with this feature are identified with SPxT-Z,
the -Z indicating they can be disabled.
Multiplexer configurations are used extensively in analog input expansion

applications. Many microprocessors have a limited number of analog to digital
converter (ADC) inputs. An analog multiplexer can be used to sequentially monitor
many analog sensors using the same ADC input. On resistance (RON) and switching
time (ten) specifications are provided in datasheets to enable an assessment to be
made for application suitability.
33
Analog switches can also be used with digital signal isolation and multiplexing/
demultiplexing. As they are transmission gates they will not behave as a repeater
and regenerate the digital signals, care must be taken to ensure that the digital
signal is not compromised by any bandwidth limitations of the analog switch.
Analog switch datasheets include a −3 dB bandwidth specification to allow
assessment on the effect on the digital signal to ensure signal integrity within the
application.
Bus switches
If several SPxT-Z analog switches are used in parallel, data from several sources can
be multiplexed onto a single data line. From a system standpoint connecting poles
together does increase the effective load capacitance seen by the data signal. This
will reduce the bandwidth of the solution. Bus switches have the same key
parameters and are available in the same configurations as the above discussed
analog switches. They can be used in isolation and multiplexing applications. To
support the data rate increases in modern applications, bus switches have lower
switch capacitance CS(ON), resulting in higher bandwidth. Additional features of bus
switches include options of voltage level translation and switching signals higher
than the bus switch supply voltage.
2.5 Logic data sheet parameters

Each logic device is supported by a datasheet as a result the data sheet parameters
published will be explained in detail. The logic data sheets start with a general
description of a device followed by a section about major features and benefits.
Automotive qualified components can be identified easily via the Q100 at the end
of the product name.
All logic parts exceed at least a 2 kV HBM (Human Body Model) and 1 kV CDM
(Charged Device Model) ESD rating to ensure safe handling in assembly and
production.
A section with ordering information follows addressing different package variants

of the product. Marking code information is provided next, followed by functional
diagrams as discussed above. Pinning information per package option can be found
and a pin description.
A function table describes in detail how the device works exactly in dependence on
all control inputs and/or a clock signal.
34
2
2.6 Limiting values

Liming values are provided in accordance with the Absolute Maximum Rating
System (IEC 60134). The device is not guaranteed to function under these
conditions, it is guaranteed not to be degraded if stresses are kept within the
limiting values.
The limiting values start with the allowed supply voltage range from VCC(min) up to
VCC(max). If this range is obeyed, no damage can happen to the device, but it does
not need to be functional. VCC(min) is equal −0.5 V in most cases. This is not a supply
for operation of course. A range for the input and output voltages VI and VO is
informed as next parameter. These values can be exceeded as long as the related
clamping current limit IIK and IOK are obeyed.
A limiting value for the current of a single output is provided as well as an ICC and
IGND limit which is reached for example if several outputs drive a comparably
low-ohmic resistor load. If the output termination is applied towards ground, an ICC
current will be seen if the output state is high. If output termination is realized
towards VCC, additional ground current is created if the state of the output is the
low-state.
Logic components can be stored at temperatures from −65 °C up to 150 °C. The

power dissipation of a device is limited to the value Ptot for a defined temperature
range. For some package options a linear derating is mentioned as a footnote with
a power decrease factor of e.g. 7.8 mW/K to be applied starting for temperatures
above 118 °C. Ptot reaches 0 mW at Tamb = 150 °C. An electronic component with
bond wires of gold shall not exceed a die temperature or Tj above 150 °C.
2.7 Recommended operating conditions

In this section of a logic device data sheet, the ranges for VCC, VI and VO is informed.
For VO ranges can be found for products that support the IOFF feature. These
components have high-ohmic output stages if the supply voltage is removed
(VCC = 0 V). In power down or suspend mode, the maximum value for the
recommended supply voltage range can be applied.
An important parameter in the recommended operating condition section is the

maximum allowed input transition and fall rate ∆t/∆V. If this condition is not
fulfilled, current consumption can increase and malfunction could occur for clocked
devices or in case of noise overlay to the signals.
35
2.8 Static characteristics

The static characteristics chapter inform the minimum voltage for a high-level input
signal VIH(min) and the maximum voltage for a low-level input signal VIL(max) for a
specific supply voltage VCC. These parameters tell which area of the input voltage
range is undefined or forbidden.
Figure 2.10 shows the resulting input voltage ranges dependent on VCC for the
logic family AUP. The signal has to stay in one of the blue areas to be processed as a
low-level or high-level.
aaa-032005
3V
2V
VIH range
VIL range
1V
1V 2V 3V
Figure 2.10 | Input voltage ranges of the logic family AUP dependent on VCC
For Schmitt trigger inputs the positive going threshold voltage VT+ and the
negative-going threshold voltage VT- is shown as transfer characteristic to define
the behavior of a digital input. A Schmitt Trigger input provides a hysteresis
characteristic as depicted in Figure 2.11. Schmitt Trigger inputs are tolerant to
smooth transitions and quite immune against noise on the input signals. Many logic
components feature a so-called Schmitt Trigger Action input. Such input does not
have a wide hysteresis like a full performance Schmitt-Trigger input but performs
more safely in case of noise overlay on transitions compared to a conventional
input characteristic.
36
2
The static characteristics in a data sheet

mna207
furthermore include the output VO
voltages for a logic high-level VOH and
low-level VOL for defined output
currents and supply voltages. For a
proper operation from a logic device
output to a logic device input the
relation between output and input VI
VH
voltage has to be in line with row 1 and
VT- VT+
4 of Table 10.
Figure 2.11 | Schmitt Trigger Input

Characteristic
Table 10: Voltage requirements from output to input

for a proper operation
Device 1 Device 2 Operation
VOH(min) > VIH(min) Function guaranteed
VOH(min) < VIH(min) Function not guaranteed
VOL(max) > VIL(max) Function not guaranteed
VOL(max) < VIL(max) Function guaranteed
Additional static parameters are the supply current maximum for open outputs
ICC(max) and the maximum input leakage current II(max). For devices that support
the IOFF feature, the maximum power-off current IOFF(max) is informed for VCC = 0 V
and a maximum ∆IOFF for VCC from 0 V to 0.2 V, means that a VCC turn-off is not
ideal.
As an additional supply current parameter for input voltage deviating from perfect
0 V or VCC low or high level condition, a maximum ∆ICC current value can be found.
The above described static characteristics are provided for different temperature
ranges for many logic devices in separate tables.
37
2.9 Dynamic characteristics

The propagation delay tPD is a very important dynamic parameter of a logic device.
For a gate or buffer it is the simple delay for a change at an input to a change of a
logic state at the output. In Figure 2.12 an example is shown for a 2-input AND-
Gate. The diagram depicts a propagation delay for the negative-going edge tPHL
and the opposite direction from low to high state tPLH. Propagation delay is
measured from a 50% level of the related transitions.
mna614
VI
A, B input VM
GND
t PHL t PLH
VOH
Y output VM
VOL
Figure 2.12 | Data input to output propagation delay
For edge-triggered devices propagation delay is defined as time between the active
clock transition and the change of state at the output. Figure 2.13 is a timing
diagram of a Flipflop. Propagation delay is measured from the rising edge to the
change of the output signal. Beside propagation delay other important timing
parameters are shown in the diagram. The data input D needs to be stable for at
least the set-up time tsu before the active clock transition and needs to stay stable
at least for the hold time th. fmax is the maximum clock frequency of a logic device.
This value is a good indication for the maximum signal speed that gates can handle
from a considered logic family. The parameter tW defines the minimum pulse width
for the clock input CP low state and the width of the set and reset signals. All these
parameters can be found in the dynamic characteristics chapter of a data sheet.
38
2

001aae365
tW
VI
CP input VM
GND
1/fmax
VI
D input VM
GND
th th
t su t su
t PHL t PLH
VOH
Q output VM
VOL
VOH
Q output VM
VOL
t PLH t PHL
Figure 2.13 | Timing diagram of a Flipflop
The dynamic parameters are listed for different supply voltages (VCC). The higher
the voltage, the faster a CMOS logic device becomes. Lower temperature
decreases tpd.
39
2 A ˄ 𝐴𝐴 = 0 A ˅ 𝐴𝐴 = 1
CPD is an equivalent power dissipation capacitance that supports the calculation of

𝐴𝐴 ˄ 𝐵𝐵 = (𝐴𝐴 ˅ power
the dynamic 𝐵𝐵) dissipation:
𝐴𝐴 ˅ 𝐵𝐵 = (𝐴𝐴 ˄ 𝐵𝐵)
𝑃𝑃! = 𝐶𝐶!" × 𝑉𝑉!! ! × 𝑓𝑓! × 𝑁𝑁 + 𝐶𝐶! × 𝑉𝑉!! ! × 𝑓𝑓!
fI = input frequency in MHz VCC = Supply voltage in V

1317 (10) =
fO = output frequency in MHz N = number of inputs
1 * 2 10 + 0 * 29 + 1 * 28 + 0 * 27 + 0 * 26 + 1 * 25 +
CL = output load capacitance in pF Sum [CL × VCC² × fO] = sum of all outputs
0 * 24 + 0 * 23 + 1 * 22 + 0 * 21 + 1 * 20
More details about timing aspects are discussed in the chapter Timing
1317(10) = 10100100101(2)
Considerations.
Other info
1011
The logic data sheets inform with detailed waveform diagrams and test circuit
+ schematics
0011 how data sheet values and parameters are derived and need to be
1110In a final section of data sheets the package outline of all the variants of a
tested.
product are shown together with tolerance information.
𝑃𝑃!"# = 𝐶𝐶!" × 𝑉𝑉!! ! × 𝑓𝑓! × 𝑁𝑁 + 𝐶𝐶! × 𝑉𝑉!! ! × 𝑓𝑓!
40
3
Chapter 3

Power considerations
for CMOS and
BiCMOS logic devices
41
As general purpose components, logic devices are used at different frequencies

and power supply voltages in many different varieties of applications. This large
diversity has produced the need to express a single parameter that can be used in
determining the power dissipation of a device in a given application. This chapter
describes different components of power dissipation and how they may be
calculated.
3.1 Static considerations
CMOS
When a CMOS device is not switching and the input levels are GND or VCC, the
p-channel and n-channel transistors do not conduct at the same time; no direct
MOS transistor channel path exists between VCC & GND. In practice however,
thermally generated minority carriers, which are present in all reverse biased diode
junctions, allow a very small leakage current to flow between VCC and GND. As this
leakage current is typically a few nA, quiescent CMOS power dissipation is
extremely low. Maximum quiescent power dissipation for the above conditions is
calculated as:
(1)
PD = VCC × ICC
PD = VCC × (n1ICCL + n2ICCH)/(n1

Where: + n2 )
ICC = specified in the device datasheet
PD = VCC × [(n1ICCL + n2ICCH)/(n1 + n2) + nΔICC]
PD = Σ(CPDVCC2 fI) + Σ(CLVCC2 fO)
PD1 = 3.6 V × 10 µA + 4 × 3.6 V × 500 µA

= 7.24 mW
PD2 = 4 × (CPD + CL) × 3.62 × 40 MHz + 2 × (CPD + CL) ×

3.62 × 80 MHz
= 87.1 mW + 87.1 mW
= 174.2 mW
42
3
BiCMOS

In the case of BiCMOS (Bipolar CMOS) devices; the current in the output bipolar
stage is different when the output is set high or low. This results in two datasheet
specifications for quiescent current ICC(for output low) & ICC(for output high). Quiescent
power dissipation for input levels of GND or VCC is calculated as:
(2)
PD = VCC × (n1ICC(for output low) + n2ICC(for output high))/(n1 + n2)
PD = VCC × [(n1ICC(for output low) + n2ICC(for output high))/(n1 + n2) + nΔICC]

Where:
n1 = number of outputs LOW n2 = number of outputs HIGH
PD1 = 3.6 V × 10 µA + 4 × 3.6 V × 500 µA
= stage
Input 7.24 mW
current due to GND < VI < VCC
In the case where the input levels of the device are not held at GND or VCC, a direct
PD1 =transistor
MOS 3.6 V ×current
(6 × ICC(for
path output
can exist + 2 x ICC(for
high)between VCC and low))this
GND;
output / 8leads
+ 4to
x 3.6 V × Δ ICC
= 11.3
additional mWcurrent
supply + 2.9 mWthrough the input buffer stage of CMOS devices, and
= 14.2
additional mWdissipation. In device datasheets this is represented as ΔICC, the
power
additional current due to an input level other than VCC or GND. In the case of 5.5 V
logic families this parameter is generally measured at an input voltage of VCC −2.1;
in the case of 3.3 V logic families it’s measured at an input voltage of VCC −0.6 V.
Static power dissipation is then calculated as:
PD = VCC × (n1ICC(for output low) + n2ICC(for output high))/(n1 + n2)
(3)
PD = VCC × [(n1ICC(for output low) + n2ICC(for output high))/(n1 + n2) + nΔICC]
PD1 = 3.6 V × 10 µA + 4 × 3.6 V × 500 µA

Where:
= 7.24ofmW
n = number inputs at the intermediate level
Note:
PD1 = 3.6 V × (6 × ICC(for output high) + 2 x ICC(for output low)) / 8 + 4 x 3.6 V × Δ ICC
For CMOS ICCL = ICCH = ICC, simplifying Equation (3): PD = VCC × [ICC + nΔICC]
= 11.3 mW + 2.9 mW
= 14.2 mW
43
Table 1 shows a comparison of ICC and ΔICC for the ’244 (octal buffer) function of
several logic families.
Table 1: Power consumption of logic process families
CMOS families
Device Voltage ICCQ VI ∆ICC Units
74HC244 6 V 80 VCC − 2.1 V 450 µA
74AHC244 5.5 V 40 VCC − 2.1 V 1500 µA
74LV244 5.5 V 20 VCC − 0.6 V 500 µA
74LVC244 3.6 V 10 VCC − 0.6 V 500 µA
74ALVC244 3.6 V 10 VCC − 0.6 V 750 µA
BICMOS families
Device Voltage ICCZ ICCL ICCH VI ∆ICC Units
74LVT244 3.6 V 0,19 12 0,19 VCC − 0.6 V 0,2 mA
3.2 Dynamic considerations

When a device is clocked or changing state, power is dissipated through the
charging and discharging of on-chip parasitic and load capacitances. Power is also
dissipated at the moment the output switches when both the p-channel and the
n-channel transistors are partially conducting. This transient energy loss is typically
only 10% of that due to parasitic capacitance.
44
PD = VCC × ICC

PD = VCC × (n1ICCL + n2ICCH)/(n1 + n2) 3
PD =
The VCC
total × [(npower
dynamic 1ICCL + n2ICCH)/(n
dissipation 1 + nis:
per device 2) + nΔICC]

(4)
PD1 = 3.6 V × 10 µA + 4 × 3.6

Where: V × 500 µA
= 7.24
CPD = power mW capacitance
dissipation fO = output frequency
per buffer CL = total external load capacitance
fI = input frequency per output
It should3.6 × 80from
be 2noted MHz the Equation (4), that CPD is a useful parameter for
= 87.1 mW + 87.1 mW
determining power dissipation in any device for which power dissipation is a linear
function of frequency.
= 174.2 mW Figure 3.1 shows ICC as a function of frequency for the
devices listed in Table 1. From this we can conclude that for all CMOS and BiCMOS
logic families CPD can be used in order to determine the worst case power
PD(ave) = (15
consumption of a× 7.24inmW
device +application.
a given 25 x 174.2 mW) / 40
= 111.6 mW
aaa-032306
PD1 = 3.6350× (6 × ICCH + 2 x ICCL) / 8 + 4 x 3.6 × Δ ICC
PD (mV)
= 11.3
300 mW + 2.9 mW AHC ALVC AXP*
= 14.2
250
mW LV
LVC
LVT
AUP*
HC
200
PD2 = 4 × (CPD + CL) × 3.62 × 40 MHz + 2 x (CPD + CL) ×
150
3.62 × 80 MHz + 3.6 × ISTAT
= 180
100 mW + 180 mW + 14.2 mW
= 374.2
50 mW
0
10 20 30 40 50 60 70 80 90 100
PD(ave) = (15 × 14.2mW + 25 × 374.2 mW) / 40
Frequency (MHz)
= 239.2 mW
* AXP and AUP compare 2 input AND function
as they currently do not include octal buffer function
1

Figure 3.1 | Power consumption over frequency for various logic process families
45
3.2.1 Duty cycle considerations with unbalanced outputs

In the case of unbalanced output drive, such as found in BiCMOS, the output duty
cycle could also be considered. Figure 3.2 shows the effect of duty cycle on the
power dissipation of the 74LVT244. It can be concluded from these measurements
that the duty cycle has little effect on the total power dissipation. This is due to the
switching currents within BiCMOS products being more dominant than steady state
currents.
aaa-032307
40
Icc(ave) (mA)
30%
35
70%
30
25
20
15
10
0
0 20 40 60 80 100
Frequency (MHz)
Figure 3.2 | Current consumption for different duty cycles
3.2.2 Power dissipation due to slow input rise/fall times
When an CMOS push pull stage switches, there is a brief period when both output
transistors conduct. The resulting through-current is additional to the normal
supply current and causes power dissipation to increase linearly with the input rise
or fall time. As long as the input voltage is less than the n-channel transistor
threshold voltage, or is higher than VCC minus the p-channel transistor threshold
voltage, one of the input transistors is always off and there is no through-current.
When the input voltage equals the n-channel transistor threshold voltage
(typ. 0.7 V), the n-channel transistor starts to conduct and through-current flows,
reaching a maximum at VI = 0.5 VCC. For devices with CMOS inputs, the maximum
current is determined by the geometry of the input transistors. When Schmitt
triggers are used to square pulses with long rise/fall times, through-current at the
Schmitt-trigger inputs will increase the power dissipation (see Schmitt-trigger data
sheets).
46
3
3.2.3 Process family related dynamic power dissipation

Dynamic power dissipation can be reduced using more advanced process technology.
The table below shows a comparison of propagation delay and dynamic power
dissipation for various process family devices based on the 2 input AND function. In
the comparison, AUP and AXP have the lowest power consumption, generally the
trend towards low power consumption of newer process families can be clearly seen.
4.5 V to 5.5 V 3.0 V to 3.6 V
min typ max min typ max

tPD (ns) PD (mW) tPD (ns) PD (mW)
HC(T) - 9.0 23.0 750 - - - -
AHC(T) 1.0 4.6 9.0 550 1.0 6.5 14.0 240
LVC 0.5 1.7 4.0 525 0.5 2.1 4.5 229
AUP - - - - 0.9 2.2 4.3 98
AXP - - - - - - - -
2.3 V to 2.5 V 1.65 V to 1.95 V
min typ max min typ max

tPD (ns) PD (mW) tPD (ns) PD (mW)
HC(T) - - - - - - - -
AHC(T) - - - - - - - -
LVC 0.5 2.2 5.5 111 1.0 3.4 8.0 68
AUP 1.0 2.4 4.8 45 1.3 3.0 6.1 26
AXP 0.9 2.0 3.0 41 1.2 2.6 4.1 24
1.4 V to 1.6 V 1.1 V to 1.3 V 0.75 V to 0.85 V
min typ max min typ max min typ max

PD PD PD
tPD (ns) (mW) tPD (ns) (mW) tPD (ns) (mW)
HC(T) - - - - - - - - - - - -
AHC(T) - - - - - - - - - - - -
LVC - - - - - - - - - - - -
AUP 1.5 3.7 7.5 17.6 2.1 5.1 11.7 11.1 - 17 - 4.8
AXP 1.5 3.2 5.0 16.7 1.8 4.3 7.3 10.7 1.8 11 122 4.7
47
3.3 Power dissipation capacitance

CPD is specified in the CMOS device data sheets, the published values being
calculated from the results of tests described in this section. The test set-up is
shown in Figure 3.3. The worst-case operating conditions for CPD are always chosen
and the maximum number of internal and output circuits are toggled
simultaneously, within the constraints listed in the data sheet. Devices that can be
separated into independent sections are measured per section, the others are
measured per device.
The recommended test frequency for determining CPD is 10 MHz, 50% duty cycle.
Loading the switched outputs gives a more realistic value of CPD, because it
prevents transient through-current in the output stages.
The values of CPD provided in datasheets have been calculated using:
(5)
𝐼𝐼!! !"# × 𝑉𝑉!! − 𝐶𝐶! × 𝑉𝑉!!! × 𝑓𝑓! + 𝑉𝑉!! × 𝐼𝐼!"#"
𝐶𝐶!" =
𝑉𝑉!!! ×𝑓𝑓!
!
Where: 2.24 𝑚𝑚𝑚𝑚 × 3.6 𝑉𝑉 − 50 𝑝𝑝𝑝𝑝 × 3.6 𝑉𝑉 × 10 𝑀𝑀𝑀𝑀𝑀𝑀 + 0 𝑚𝑚𝑚𝑚
𝐶𝐶!" =
CPD 3.6 𝑉𝑉 ! × 10 f𝑀𝑀𝑀𝑀𝑀𝑀
= power dissipation capacitance O = output frequency
(per buffer)
𝐶𝐶!" = 12.2 𝑝𝑝𝑝𝑝 fI = input frequency
ICC(ave) = supply current ISTAT = supply current at dc
VCC = supply voltage (approx. zero for CMOS)
CL = output load𝑚𝑚𝑚𝑚
11.53 × 3.6 𝑉𝑉 − 50 𝑝𝑝𝑝𝑝 × 3.6 𝑉𝑉 ! × 30 𝑀𝑀𝑀𝑀𝑀𝑀
capacitance
𝐶𝐶!" =
3.6 𝑉𝑉 ! × 30 𝑀𝑀𝑀𝑀𝑀𝑀
𝐶𝐶!" = 56.8 𝑝𝑝𝑝𝑝
𝑃𝑃! = 𝐶𝐶!" × 𝑉𝑉!!! × 𝑓𝑓!" + 𝐶𝐶! × 𝑉𝑉!!! × 𝑓𝑓!"#
!!" ! !!"(!) !.! ! ! !.!" !

𝑅𝑅!" = = = 210 Ω
!!(!) !" !!
48
3

aaa-032308
VCC(max)
ICC(ave) nA
0.1 µF 10 µF
INPUT DEVICE
UNDER OUTPUT
TEST
CL = 50 pF
Figure 3.3 | Test set-up for CPD determination
3.3.1 Example CPD calculations
CMOS
In the case of 74LVC244, ISTAT is negligible and can be considered as zero for the
purpose of CPD calculation. The test set-up for the ’244 as indicated in Conditions for
CPD tests was used, with the load shown in Figure 3.3. At VCC = 3.6 V, fI = 10 MHz;
ICC(ave) was
𝐼𝐼 found×to𝑉𝑉be 2.24
− mA.
𝐶𝐶 × 𝑉𝑉 ! × 𝑓𝑓 + 𝑉𝑉 × 𝐼𝐼
!! !"# !! ! !! ! !! !"#"
𝐶𝐶!" =
Using Equation (5): 𝑉𝑉!!! ×𝑓𝑓!
2.24 𝑚𝑚𝑚𝑚 × 3.6 𝑉𝑉 − 50 𝑝𝑝𝑝𝑝 × 3.6 𝑉𝑉 ! × 10 𝑀𝑀𝑀𝑀𝑀𝑀 + 0 𝑚𝑚𝑚𝑚

𝐶𝐶!" =
𝐶𝐶!" = 12.2 𝑝𝑝𝑝𝑝
11.53 𝑚𝑚𝑚𝑚 × 3.6 𝑉𝑉 − 50 𝑝𝑝𝑝𝑝 × 3.6 𝑉𝑉 ! × 30 𝑀𝑀𝑀𝑀𝑀𝑀

𝐶𝐶!" =
𝐶𝐶!" = 56.8 𝑝𝑝𝑝𝑝
𝑃𝑃! = 𝐶𝐶!" × 𝑉𝑉!!! × 𝑓𝑓!" + 𝐶𝐶! × 𝑉𝑉!!! × 𝑓𝑓!"#
!!" ! !!"(!) !.! ! ! !.!" ! 49

𝑅𝑅!" = = = 210 Ω
!!(!) !" !!
BiCMOS
𝐼𝐼!! !"# × 𝑉𝑉!! − 𝐶𝐶! × 𝑉𝑉!!! × 𝑓𝑓! + 𝑉𝑉!! × 𝐼𝐼!"#"

𝐶𝐶 =
In the case of 74LVT244, ISTAT cannot
𝑉𝑉!!! ×𝑓𝑓be considered as negligible at low frequency.
!"
!
As a result, a higher frequency is recommended for modeling its CPD. The test setup
depicted in Figure 3.3 has been used, however at a frequency of 30 MHz. ICC(ave) was
found to2.24
be 11.53 ! with the assumption that ISTAT is
𝑚𝑚𝑚𝑚 mA. We
× 3.6 𝑉𝑉 then
− apply
50 𝑝𝑝𝑝𝑝Equation
× 3.6 𝑉𝑉(5)
× 10 𝑀𝑀𝑀𝑀𝑀𝑀 + 0 𝑚𝑚𝑚𝑚
𝐶𝐶 =
negligible.
!" !
3.6 𝑉𝑉 × 10 𝑀𝑀𝑀𝑀𝑀𝑀
𝐶𝐶!" =Equation
Using 12.2 𝑝𝑝𝑝𝑝(5):
11.53 𝑚𝑚𝑚𝑚 × 3.6 𝑉𝑉 − 50 𝑝𝑝𝑝𝑝 × 3.6 𝑉𝑉 ! × 30 𝑀𝑀𝑀𝑀𝑀𝑀

𝐶𝐶!" =
𝐶𝐶!" = 56.8 𝑝𝑝𝑝𝑝
Note:
𝑃𝑃! = 𝐶𝐶!" × 𝑉𝑉!!! × 𝑓𝑓!" + 𝐶𝐶! × 𝑉𝑉!!! × 𝑓𝑓!"#
Performing the measurement and calculation at 20 MHz results in a CPD of 66 pF.
Due to the uncertainty of ISTAT in a given configuration, it is recommended that a 5
to 10% guardband
!!" ! !!"(!) is used when approximating power dissipation for BiCMOS
!.! ! ! !.!" !
𝑅𝑅!" =
devices. = = 210 Ω
!!(!) !" !!
50
3
3.4 Using CPD to calculate power dissipation

3.4.1 CMOS Device Calculation
Consider a 3.6 V application in which every 40 ms a 74LVC244A device is used to

buffer four 40 MHz, 75% positive duty cycle signals and two 80 MHz, 75% positive
duty cycle signals, for a duration of 25 ms. The unused inputs are tied to 3.6 V, the
PD = VCC × ICC
outputs drive 30 pF loads, and when not buffering, four inputs are held at 3.0 V and
two inputs held at GND.
In = VCC ×the
PDcalculating (naverage
1ICCL +power
n2ICCH )/(n1 +we
dissipation n2need
) to consider both the power
dissipation for the 15 ms when the device is not buffering, and the power
dissipation for the 25 ms when the buffers are active.
PD = VCC × I[(n
CC 1ICCL + n2ICCH)/(n1 + n2) + nΔICC]
In the first 15 ms the device is static and power dissipation is calculated using
simplified Equation (3). In this case we have four inputs that are connected to
PDD −0.6 V.
VPCC
=
=V V
Σ(C × VI(n
CC ×
CC PD
CC 2I f ) + Σ(C
CC1 CCLI n2ICCH
LV)/(n
CC fO1)+ n2)
2
PDDD1=
P ==V CC ×
V3.6
CC ×V(n
[(n ICCLµA
1ICCL
×110 +++
nn22I4CCH
×)/(n
ICCH 1+
)/(nV
3.6 1×+n500
n22)) +
µAnΔICC]
= 7.24 mW
PDD =
P =V [(n21ICCL + n2ICCH)/(n
CC × V
Σ(C PD CC fI) + Σ(CLVCC fO)
2 1 + n2) + nΔICC]
In the=
PD2 4 × (C
second 25 ms +
PD
theCtotal
L) × 3.6 × 40 MHz + 2 × (CPD + CL) ×
power2 dissipation can be estimated as the
combination2of static the dynamic dissipation due to the four buffers and outputs
3.6
PDD1==Σ(C
P 3.6 V×
PD 80
V×CC 2 fMHz
I)µA
10and +dynamic
Σ(C
+ 4L× Vdissipation
3.6fOV) ×due
CC
2
500toµA
switching at 40 MHz, the two buffers and outputs
=
= 87.1
7.24
switching
mW
mW + 87.1 mW
at 80 MHz.
= 174.2 mW
PD1 = 3.6 V × 10 µA + 4 × 3.6 V × 500 µA
PD2 == 7.24
4 × (CmWPD + CL) × 3.6 × 40 MHz + 2 × (CPD + CL) ×
2
PD(ave)3.6
= (15 × 7.24
2 × 80 MHz mW + 25 x 174.2 mW) / 40
= 111.6 mW
PD2 = 87.1
4 × (CmWPD ++C87.1 mW2 × 40 MHz + 2 × (CPD + CL) ×
L) × 3.6
= 3.6
174.2
2 × mW
80 MHz
PD1 = 3.6 × (6 × ICCH + 2 x ICCL) / 8 + 4 x 3.6 × Δ ICC
= 87.1 mW + 87.1 mW
= 11.3 mW + 2.9 mW
= 174.2
PD(ave) mW
The
==
average(15
14.2power
mW 7.24 mWis +
× dissipation 25 x 174.2 mW) / 40
then:
= 111.6 mW
PD(ave) = (15 × 7.24 mW +225 x 174.2 mW) / 40
PD2 =
P 4 ×× (C(6
PD + CL) × 3.6 × 40 MHz + 2 x (CPD + CL) ×
D1 = 3.6
= 111.6 ×
mWICCH + 2 x ICCL) / 8 + 4 x 3.6 × Δ ICC
3.6
= 11.3 mW + 2.9+mW
2 × 80 MHz 3.6 × ISTAT
= 180
=3.6
14.2 mW + 180 mW + 14.2 mW
PD1 = × mW
(6 × I + 2 x ICCL) / 8 + 4 x 3.6 × Δ ICC
= 374.2 mW CCH
= 11.3 mW + 2.9 mW
PD2 ==414.2
× (CmWPD + CL) × 3.6 × 40 MHz + 2 x (CPD + CL) ×
2 51
PD(ave)3.6
= (15
2 × 80 MHz + 3.6 25
× 14.2mW + × I× 374.2 mW) / 40
P =V
PDD = Σ(C PDVCC fI) + Σ(CLVCC fO)
2 2
CC × (n1ICCL + n2ICCH)/(n1 + n2)
P = 3.6 V × 10 µA + 4 × 3.6 V × 500 µA

D = VCC × [(n1ICCL + n2ICCH)/(n1 + n2) + nΔICC]
PD1
3.4.2 = 7.24 mWDevice Calculation
BiCMOS
PD = VCC the
Consider × (nLVT244
1ICC(for output
in thelow) + napplication.
same 2ICC(for output high))/(n1 + n2)
In the=
PD2 4×
case of (C PD + devices,
BiCMOS CL) × 3.6 × 40
the 2duty cycleMHzmust+ be2 × (C
taken into + CL) ×
PD consideration
PD = VCC3.6
because × [(n
ICCL 1 I
× 80 MHz
2and I are
CC(for
CCH not
output + n
identical.
low) 2 I In the
CC(for first
output )/(n
15 ms
high) of
1 + n
the2 ) + nΔICC] the static
application
PD1 =
power =dissipation
3.6 V × 10
87.1 mW + 87.1 mW
is µA
calculated+ 4 ×
using 3.6 V
Equation × 500
(2) to µA
determine quiescent power
PD1 ===3.6
7.24
dissipationV × mW
and
174.2 adding
10mW the power dissipation
µA + 4 × 3.6 V × 500 µA caused by the four inputs that are
connected to
= 7.24 mW VCC −0.6 V.

PPD1
D(ave)
= 3.6=V(15(6×
2×× × 7.24 mWhigh)
ICC(for output ++
252 xx I174.2 mW) / 40
CC(for output low)) / 8 + 4 x 3.6 V × Δ ICC
3.6
= 111.680 MHz
mW
= 11.3 mW + 2.9 mW
==14.2
87.1
mW mW + 87.1 mW
PD1 == 174.2
3.6 × (6 mW × ICCH + 2 x ICCL) / 8 + 4 x 3.6 × Δ ICC
= 11.3
The power mW +in 2.9
dissipation mW25 ms contains in addition to those of the
the next
= 14.2
74LVC244A casemW
PD(ave) = (15 × 7.24 mW +
the component 25
ISTAT x can
. PD1 174.2 mW)
be used / 40
to approximate ISTAT.
= 111.6 mW
PD2 = 4 × (CPD + CL) × 3.62 × 40 MHz + 2 x (CPD + CL) ×
PD1 = 3.6
3.62××(680×MHzICCH ++ 23.6
x I×CCLI) / 8 + 4 x 3.6 × Δ ICC
STAT
= 180
= 11.3mW mW+ +180
2.9 mW
mW + 14.2 mW
= 374.2
= 14.2 mW mW
Pshould
D2 = 4be
ItPD (CPDthat
×noted + CinLusing
) × 3.6 2 × 40 MHz + 2 x (C + ) ×
(ave) = (15 × 14.2mW + 25 × 374.2 mW) / 40
equation 3 to determine our dynamic
PD CLdissipation
components3.6 ×
2we 80
are
= 239.2 mW MHz
assuming +a 3.6 ×
rail to I
rail output
STAT swing. As BiCMOS outputs don’t
swing =rail180
to railmW + 180 mW + 14.2 mW
this will produce a worse case approximation.
The = 374.2 mW
1 calculated average power dissipation is then:

PD(ave) = (15 × 14.2mW + 25 × 374.2 mW) / 40

= 239.2 mW
52
1
3
3.5 Results and conclusion

Table 2: Comparison of measured and calculated results
Static 15 ms Dynamic 25 ms Total
PD1 (mW) PD2 (mW) PD(ave) (mW)
Calculated
Calculated
Calculated
Measured
Measured
Measured
ICC(ave) ICC(ave)
Device (mA) (mA)
74LVC244A 0,008 0,028 7,24 48,2 173,5 174,2 108,4 111,6
74LVT244 2,5 9 14,2 102,4 368,6 374,2 233,8 239,2
Determination of power dissipation is an essential part of system design. By

understanding the static and dynamic components of power dissipation, and how
they can be modeled; a system designer is able to estimate the worst case power
dissipation of an application.
Table 2 shows the comparison of the measured results to those calculated. The
values of static and dynamic current that were calculated are within 10% of the
measured values. Importantly the calculated values are higher than the measured
values. This is due to the calculations being made with worse case datasheet limits.
This is considered advantageous in system level power calculations, as it provides
extra power budget margin in the application. It can be concluded, from the
examples presented, that any device that has a linear relationship between supply
current and frequency can be modeled as a single power dissipation capacitance
CPD for the purpose of power dissipation calculations of that device used in any
application.
53
Conditions for CPD tests

Gates Latches
All inputs except one are held at either The device is clocked and data is
VCC or GND, depending on which state toggled on alternate clock pulses. Other
causes the output to toggle. The preset or clear inputs are held so that
remaining input is toggled at a known output toggling is enabled. If the device
frequency. CPD is specified per-gate. has common-locking latches, one latch
is toggled by the clock. 3-State latches
Decoders
are measured with their outputs
One input is toggled, causing the
enabled. CPD is specified per-latch.
outputs to toggle at the same rate
(normally one of the address-select pins Flip-flops
is switched while the decoder is Measurement is performed as for
enabled). All other inputs are tied to VCC latches. The inputs to the device are
or GND, whichever enables operation. toggled and any preset or clear inputs
CPD is specified per-independent- are held inactive.
decoder.
Shift registers
Multiplexers The register is clocked and the serial
One data input is tied HIGH and the data input is toggled at alternate clock
other is tied LOW. The address-select pulses (as described for latches). Clear
and enable inputs are configured such and load inputs are held inactive and
that toggling one address input selects parallel data are held at VCC or GND.
the two data inputs alternately, causing 3-State devices are measured with
the outputs to toggle. With 3-State outputs enabled. If the device is for
multiplexers, CPD is specified per output parallel loading only, it is loaded with
function for enabled outputs. 101010..., clocked to shift the data out
and then reloaded.
Bilateral switches
The switch inputs and outputs are Counters
open-circuit. With the enable input A signal is applied to the clock input but
active, one of the select inputs is other clear or load inputs are held
toggled, the others are tied HIGH or inactive. Separate values for CPD are
LOW. CPD is specified per switch. given for each counter in the device.
3-State buffers and transceivers Arithmetic circuits

CPD is specified per buffer with the Adders, magnitude comparators,
outputs enabled. Measurement is as for encoders, parity generators, ALUs and
simple gates. miscellaneous circuits are exercised to
obtain the maximum number of
simultaneously toggling outputs when
toggling only one or two inputs.
54
3
Display drivers

CPD is not normally required for LED
drivers because LEDs consume so much
power as to make the effect of CPD
negligible. Moreover, when blanked, the
drivers are rarely driven at significant
speeds. When it is needed, CPD is
measured with outputs enabled and
disabled while toggling between lamp
test and blank (if provided), or between
a display of numbers 6 and 7.
LCD drivers are tested by toggling the

phase inputs that control the segment
and backplane waveforms outputs. If
either type of driver (LCD or LED) has
latched inputs, then the latches are set
to a flow-through mode.
One-shot circuits
In some cases, when the device ICC is
significant, CPD is not specified. When it
is specified, CPD is measured by toggling
one trigger input to make the output a
square wave. The timing resistor is tied
to a separate supply (equal to VCC) to
eliminate its power contribution.
55
3
56
Power considerations for CMOS and BiCMOS logic devices nexperia | Design Engineer’s Guide
4
Chapter 4

Timing aspects of
discrete devices
57
In a circuit design, the right timing of all participating components is essential for
functionality. A wrongly calculated delay of a component or a misunderstanding of

its temporal behavior could end up in a complete system failure. This chapter will
explain the required fundamentals to understand the timing aspects of logic
devices and successfully apply them in the design process.
4.1 Synchronous and asynchronous logic

An asynchronous circuit, or self-timed circuit, is a digital logic circuit which is not
governed by a clock circuit or global clock signal. Instead it often uses signals that
indicate completion of instructions and operations, specified by simple data
transfer protocols. This type of circuit is contrasted with synchronous circuits, in
which changes to the signal values in the circuit are triggered by single or repetitive
pulse called a clock signal. Most digital devices today use synchronous circuits.
However asynchronous circuits have the potential to be faster, and may also have
advantages in lower power consumption, lower electromagnetic interference, and
better modularity in large systems. An illustration of asynchronous and
synchronous logic circuit examples is given in Figure 4.1 and Figure 4.2.
Figure 4.1 shows a symbol for asynchronous logic. In contrast to just combinatorial

logic, a logic state can be stored and therefore a feedback loop is needed. An
example for such an element is a simple RS Flip-Flop.
For a synchronous Logic element, the feedback loop id synchronized by an extra

clock signal as shown in Figure 4.2.
A Z
Combinational
y Logic Y
A Z
Combinational
y Logic Y
Digital Storage
aaa-032006
aaa-032007
CLK
Figure 4.1 | Asynchronous Logic element Figure 4.2 | Synchronous Logic element
58
4
4.2 Propagation delay time of a device

In digital circuits, the propagation delay, or gate delay, is the length of time which
starts when the input to a logic gate becomes stable and valid to change, to the
time that the output of that logic gate is stable and valid to change. In logic
components datasheets this refers to the time required for the output to reach
50% of its final output level when the input changes to 50% of its final input level.
Reducing gate delays in digital circuits allows them to process data at a faster rate
and improve overall performance. The determination of the propagation delay of a
combined circuit requires identifying the longest path of propagation delays from
input to output and by adding each tPD time along this path.
The difference in propagation delays of logic elements is the major contributor to

glitches in asynchronous circuits as a result of race conditions.
Pulse Width tW is the time gap between a rising edge and a falling edge of a signal.
The reference signal level for measuring the time is 50% of the amplitude between
high and low level. Figure 4.3 shows the measurement parameters for propagation
delay (tpd if tPHL = tPLH), rise and fall times (tr = tTLH, tf =tTHL). Transition times are
measured from 10% to 90% of signal level.
aaa-010415
VI
A, B input VM VM
GND
tPHL tPLH
VOH
90 % 90 %
Y output VM VM
10 % 10 %
VOL
tTHL tTLH
Figure 4.3 | Propagation delay measurement
59
4.3 Timing parameters of

Flip Flops and Latches

Flip-Flops and Latches are circuits with two stable states that can be used to store
state information. Flip-flops can be either level-triggered (asynchronous,
transparent or opaque) or edge-triggered (synchronous, or clocked).
Propagation delay — Propagation delay for a Flip Flop is the time between the
clock event (either rising or falling edge) and the output signal change. As well as
for gates, 50% of the signal level is taken for measurement window.
Setup time tSU — Setup time is the minimum amount of time the data input should
be held steady before the clock event (either rising or falling edge), so that the data
is reliably sampled by the clock.
Hold time tH — Hold time is the minimum amount of time the data input should be
held steady after the clock event, so that the data is reliably sampled by the clock.
Both set-up and hold time are illustrated in Figure 4.4.
The timing parameters set-up and hold time are related to interface signal levels
and are caused by internal gate delays, meaning that the clock signal needs to be
propagated internally to sample the data signal.
Aperture is the sum of setup and hold time. The data input should be held steady
throughout for this period of time.
VI mna653
D input VM
GND
th th
t su(L) t su(H)
1/fmax
VI
CP input VM
GND
tW
t PLH t PHL
VOH
Q output VM
VOL
Figure 4.4 | The Clock input (CP) to output (Q) propagation delays, clock pulse width,
D to CP set-up and hold times and the maximum clock input frequency
60
4
Recovery time is the minimum amount of time the asynchronous set or reset input

should be inactive before the clock event, so that the data is reliably sampled by
the clock. The recovery time for the asynchronous set or reset input is thereby
similar to the setup time for the data input.
Removal time is the minimum amount of time the asynchronous set or reset input
should be inactive after the clock event, so that the data is reliably sampled by the
clock.
4.4 Skew definitions

Skew specification measurements are taken at certain conditions which may or,
more likely, may not match a specific condition in a system application. However,
like other AC specifications the skew specification is valuable as a “benchmark” for
estimating certain circuit characteristics. Skew specifications are most valuable in
clock–driving applications and applications where duty cycle characteristics are
important. Three specific skew specifications are described as follows:
4.4.1 Output Skew tSK(o)
JEDEC definition: “The difference between two concurrent propagation delay

times that originate at either a single input or two inputs switching simultaneously
and terminate at different outputs.”
This skew generally characterizes

like–going edges of a single IC only. It
compares tPLH versus tPLH (or tPHL vs.
tPHL) for two or more output data paths.
This parameter is very useful in
describing output distribution
capabilities of a device. tSK(o) would be
most valuable to designers using the
device as a clock driver, distributing
clock signals. tSK(o) could be further
subdivided into tSK(LH) (output rising
edge) and tSK(HL) (output falling edge) Figure 4.5 | Output skew illustration
skews, as can be seen in Figure 4.5.
61
4.4.2 Process Skew tSK(x)

JEDEC definition: “The difference

between identically specified
propagation delay times on any two
samples of an IC at identical operating
conditions.”
This parameter addresses the issue of

process variations by quantifying the
difference between propagation delays
that are caused by lot–to–lot variations.
It does not include variations due to
differences in supply voltage, operation
temperature, output load, input edge
rates, etc.
This parameter could be viewed as a

tSK(o) skew over several like devices. An
example of two devices with process
skew is shown in Figure 4.6.
Figure 4.6 | Process Skew
4.4.3 Pulse Skew tSK(p)
JEDEC definition: “The difference between the propagation delay times tPHL and
tPLH when a single switching input causes one or more outputs to switch.”
This parameter is used to quantify duty cycle characteristics. Some applications

require a nearly perfect 50% duty cycle. tSK(p) specifies the duty cycle retention
characteristics of the device.
4.5 Meta stability and its mitigation

Meta stability in electronics is the ability of a digital electronics system to persist for
an unbounded time in an unstable equilibrium or metastable state. In digital logic
circuits, a digital signal is required to be within certain voltage or current limits to
represent a ‘0’ or ‘1’ logic level for correct circuit operation; if the signal is within a
forbidden intermediate range it may cause faulty behavior in logic gates the signal
is applied to. In metastable states, the circuit may be unable to settle into a stable
‘0’ or ‘1’ logic level within the time required for proper circuit operation. As a result,
the circuit can act in unpredictable ways, and may lead to a system failure,
sometimes referred to as a “glitch”.
62
4
Reasons for Meta Stability

In most cases, the cause for an undefined internal state of a logic device is the
absence of input drive. The basic element of all logic devices is the inverter with a
PMOS and an NMOS transistor connected with common drain and common gate. In
stable state, one of them is conducting while the other is disabled. In case of an
input signal driving the common gate to an intermediate voltage level between VCC
and GND, both PMOS and NMOS transistors are partly conducting. This
intermediate state is normally occurring during switching transition. If it remains as
a static state, the device is metastable and a constant current through the
transistors is drawn. In addition to the undefined logic state, the increased current
consumption is another reason for the necessity to avoid meta stable states in a
logic circuit.
Comb Din Ds Dout Comb

logic D Q D Q D Q logic
CLK-A CLK-B
CLK-A
CLK-B
Din
Ds
Dout
aaa-032020
Metastable Stable Output

phase
Figure 4.7 | Meta stability in a synchronizer where data crosses between 2 clock domains
Mitigation of Meta stability
As far as meta stability is caused by input signals, it is important for the circuit
designer to assure that driving signals are in defined states, logic high or low.
Causes related to internal device configurations as shown in Figure 4.6, must be

prevented by design measures taken by the designer. Unused inputs should always
be connected to VCC or ground thru an appropriate current limiting resistor.
63
4.6 Maximum frequency information

The operation frequency and the related data rate of logic devices is to a large
extent dependent on process technology.
The maximum clock or operation frequency is specified in data sheets for those
devices which are timing related such as Flip Flops and Counters. Generally, devices
of the product segment ‘synchronous interface logic’ in Nexperia’s web page have a
specification for frequency.
For other devices, the best way to find out the operation frequency is to compare a
timing related device of the same process family.
64
5
Chapter 5

Interfacing aspects
of logic devices
65
The usage of discrete logic devices is associated with various aspects of interfaces.
The timing was already addressed in the previous chapter. Further to timing, many
more aspects need to be considered when integrating a discrete logic device into
an application design. In particular, voltage level shifting needs to be addressed.
Various features of logic devices are also interface related, such as Bus Hold, IOFF,
and Schmitt-Trigger inputs. Physical effects are affecting the interfaces of discrete
device, and are therefore addressed in this chapter as well, i.e. Ground and VCC
bounce.
5.1 Application requirements for interfacing

A high performance of a system is very often the result of a thorough system
integration. In a system integration process, all parts of the system need to be
composed to form a functional unit. The primary requirements that make a
component fit into the system are oriented to its interface properties such as
timing, voltage and other features. In the following sub-chapters, we will explain
the most important interface properties of discrete logic devices to support their
integration.
Level shifting/translation
Level shifter and translator circuits are

used to interface between components 3.3V Translator 1.8V
with different supply voltage and
T
input-output voltage levels. A classic PCMCIA
Card
Application
processor
example is a Microcontroller with a
T
supply voltage of 1.8 V and a peripheral
device, i.e. a sensor with a supply
voltage of 3.3 V. If the enable signal for
Figure 5.1 | Translating transceiver interface
the sensor is driven by a GPIO of the
Microcontroller (which has 1.8 V) it
needs to be level shifted to 3.3 V. There
are various mechanisms for level
shifting.
Input and Output levels
Logic devices have input level requirements (Vinput high = VIH and Vinput low = VIL)
and provide output voltage levels (VOH and VOL). The levels depend on the supply
voltage as well as on process technology and design. Table 1 shows an extract of a
data sheet table showing these figures.
66
5
Table 1: Specified input and output logic levels

Tamb
Conditions
Parameter
25 °C
Symbol
Min Typ Max Unit
VIH HIGH-level VCC = 0.8 V 0.70 × VCC – – V

input voltage
VCC = 0.9 to 1.95 V 0.65 × VCC – – V
VCC = 2.3 to 2.7 V 1.6 – – V
VCC = 3.0 to 3.6 V 2.0 – – V
VIL LOW-level VCC = 0.8 V – – 0.30 × VCC V
input voltage
VCC = 0.9 to 1.95 V – – 0.35 × VCC V
VCC = 2.3 to 2.7 V – – 0.7 V
VCC = 3.0 to 3.6 V – – 0.9 V
VOH HIGH-level VI = VIH or VIL
input voltage
IO = −20 μA; VCC = 0.8 to 3.6 V VCC − 0.1 – – V
IO = −1.1 mA; VCC = 1.1 V 0.75 × VCC – – V
IO = 1.7 mA; VCC =1.4 V 1.11 – – V
IO = 1.9 mA; VCC = 1.65 V 1.32 – – V
IO = 2.3 mA; VCC = 2.3 V 2.05 – – V
IO = 3.1 mA; VCC = 2.3 V 1.9 – – V
IO = 2.7 mA; VCC = 3.0 V 2.72 – – V
IO = 4.0 mA; VCC = 3.0 V 2.6 – – V
VOL LOW-level VI = VIH or VIL
output voltage
IO = −20 μA; VCC = 0.8 to 3.6 V – – 0.1 V
IO = −1.1 mA; VCC = 1.1 V – – 0.3 × VCC V
IO = 1.7 mA; VCC =1.4 V – – 0.31 V
IO = 1.9 mA; VCC = 1.65 V – – 0.31 V
IO = 2.3 mA; VCC = 2.3 V – – 0.31 V
IO = 3.1 mA; VCC = 2.3 V – – 0.44 V
IO = 2.7 mA; VCC = 3.0 V – – 0.31 V
IO = 4.0 mA; VCC = 3.0 V – – 0.44 V
67
VIH is the high-level input voltage, if a voltage is applied that is > VIH, it will be
considered logic HIGH. VIL is the low-level input voltage, if a voltage is applied that
is < VIL, it will be considered logic LOW. VOH is the high-level output voltage at a
specified output current. VOL is the low-level output voltage at a specified output
current.
Table 2 shows the input and output levels for TTL and CMOS products over a range
of supply voltages.
Table 2: CMOS and TTL input and output voltage levels
TTL CMOS
Input Voltage Output Voltage Input Voltage Output Voltage
Voltage VIH VIL VOH VOL VIH VIL VOH VOL
5.0–15.0 V 0.7 × VCC 0.3 × VCC
5.0 V 2.00 0.80 2.40 0.50 3.50 1.50 4.50 0.40
3.3 V 2.00 0.80 2.40 0.55 2.31 0.99 2.55 0.45
1.8 V 1.27 0.68 1.30 0.35
1.5 V 0.98 0.78 1.30 0.35
1.2 V 0.78 0.42 1.03 0.36
As shown in Table 3, to guarantee functionality, the VOH of the driver must be

higher than the VIH of the receiver. Similarly, the VOL of the driver must be lower
than the VIL of the receiver.
Table 3: Output and input voltage relations required for functionality
Device 1 Device 2 Operation

VOH (min) > VIH (min) Function guaranteed
VOH (min) < VIH (min) Function not guaranteed
VOL (max) > VIL (max) Function not guaranteed
VOL (max) < VIL (max) Function guaranteed
68
5
The existence of many voltage nodes creates issues when trying to connect circuits

together. Figure 5.2 depicts H-L and L-H translation between devices of 3 different
process families, in this example LVC, AUP and AXP types. As can be seen, level
translation will be necessary when devices of these process types are connected in
a circuit.
VCC VCC = 5V
5.0 V
4.5 V
V IH>=3.5V
Defi ned HIGH
4.0 V
VCC = 3.3V
3.5 V
3.0 V
Undefi ned VOH=2.55V
2.5 V Input VOH< V IH
2.0 V
1.5 V
1.0 V V IL< 1.5V

0.5 V Defi ned LOW
VOL= 0.45V
LVC AUP
VCC
5.0 V
4.5 V
4.0 V
VCC = 3.3V
3.5 V
3.0 V
V IH>=2 .5V
2.5 V Defi ned HIGH
VCC = 1.8V
2.0 V
Undefi ned
1.5 V VOH< V IH VOH>1.35V
Input
1.0 V
V IL< 1.08V
0.5 V
Defi ned LOW
VOL<0.31V
AUP AXP
Figure 5.2 | I/O Voltage level overview for LVC, AUP, AXP
69
Types of translations
Uni-directional
Uni-directional translators can be either high-to-low or low-to-high level translators,
but the signal direction is fixed. As an advantage, these translators only need one
power supply domain, if the voltage gap between the 2 domains is within limits of
< 2 V.
VCCA=5V VCCB=3.3V
3.3V
1.8V 3.3V
Receiver Bi
Driver directional Receiver
Driver T Translator
Figure 5.3 | Uni-directional low-to-high Figure 5.4 | Bi-directional LOW to HIGH

voltage translation and HIGH to LOW voltage translation
Bi-directional
Bi-directional translators are more flexible, both directions are supported and this
is requiring dual power supply domains.
Bidirectional translation can be implemented using a direction control pin or with

automatic sensing of the direction. The direction control pin needs to be driven by
one of the participants, and it needs to have the right voltage level in dual supply
voltage translators, in most cases this will be the VCCA domain.
Auto Direction translators have no direction control pin and instead can be
implemented using one of the following approaches:
• an inner circuit for sensing the driver

• a low power feedback loop that holds that last direction used and can be
overwritten
• an intrinsic direction control such as a pass transistor.
70
5
Dual-supply voltage translators

Dual-supply devices have two supply
DIR
voltages at different voltage ranges.
These translators can be used for uni or
bi-directional voltage level translation. 1A 1B
Dual supply devices are designed for
asynchronous communication between
devices operating at different voltages
and are also known as dual-supply
voltage translators. Dual-supply voltage
translators can be used for LOW to HIGH nA nB
and HIGH to LOW voltage translation. VCCA VCCB

These devices are supplied at
VCCA & VCCB and interface data ports
A & B operating in different voltage Figure 5.5 | Dual supply voltage
domains. They feature DIR pins to translating transceiver
control signal direction. They are more

power efficient than the single supply
solutions.
Mechanisms of translation
Clamp Diode Inputs
Clamping diode
VCC=5V
RCL
15V
Device
Input
buffer
ESD Protection
Figure 5.6 | Clamp input diode using current-limiting resistors
By using input current limiting resistors with the internal clamp diode, High to Low
voltage translation is possible.
71
Many CMOS inputs include diodes to VCC in their input ESD protection structures.
Voltages higher than VCC can be clamped by these diodes if current limiting
resistors are used. This provides High to Low voltage translation using current
limiting resistors. When voltages are higher than VCC, it must be assured that the
supply voltage is able to compensate the higher input voltage and does not
increase the VCC of the device.
Value of current limiting resistor RCL can be calculated using VCC values of driver
and receiver devices. The input clamp diode also serves as an ESD protection.
Table 4: Output and input voltage relations required for functionality

Symbol Parameter Condition Min Max Unit
IIK input clamping current VI < -0.5 V or – ±20 mA

VI > VCC + 0.5 V
ICC supply current – 50 mA
IGND supply current −50 – mA
Devices with input ESD diodes to VCC:
A device has input ESD diodes to VCC if the datasheet limiting value of IIK includes
the condition VI > VCC + 0.5 V and the max recommended VI = VCC (see Table 4).
To use the ESD diode as a clamp diode the value of the current limiting resistors RCL
should be set to ensure that the limiting value of IIK is not exceeded. If there are
more than one inputs, ensure that the combined current does not exceed the
limiting value of ICC.
Advantage: Disadvantage:
• Can be used to interface any voltage • Requires external components
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5
Overvoltage tolerant inputs

5V Device 3.3V Device
Input buffer
ESD
Protection
Figure 5.7 | Using overvoltage tolerant inputs to enable HIGH-to-LOW level translation
Modern CMOS ESD protection circuits provide the same ESD protection without
including a diode to VCC. These devices have over-voltage tolerant inputs because
the recommended value of VI is not VCC but the same as the recommended
maximum VCC. A device specified for operation over a supply voltage range of 1.65
to 5.5 V can be used at 3.3 V with 5.5 V applied to inputs. A device with overvoltage
tolerant inputs is suitable for High to Low level translation.
A device has overvoltage tolerant inputs if the datasheet limiting value of IIK does
not include the condition VI > VCC + 0.5 V and the max recommended VI is not VCC
• No external components required • Input cannot be driven at voltages
• Lower system power than clamp greater than the recommended
diode solution maximum value of VCC
73
Open-drain outputs
An open-drain output can be pulled-up to the desired voltage level in Low to High
voltage translation. The open drain output itself can only pull down, as it is
implemented as a NMOS transistor with an open drain connected to the output of
the device. In conduction mode, the NMOS conducts the output to GND. In devices
equipped with an open-drain output, the output is pulled-up to a pull-up voltage
level matching the input requirements of the device it is driving. A pull-up resistor is
used on the output for level translation.
1.8V Device V pull-up = 3.3V 3.3V Device
Pull-up
resistor
Output Input
1.8V 1/0
System
Figure 5.8 | Open-drain output and pull-up resistor for level translation
Important points to note when considering open-drain outputs with pull-up

resistors for level translation:
• The output rise and fall times are dependent upon the value of pull-up
resistor used.
• The pull-up may be higher than or lower than the device supply voltage
• In designs that use power-down to save battery life use devices that
include IOFF in the static characteristics
• How to detect devices with open-drain outputs from data sheet
properties:
• Logic devices with open-drain outputs will not have a VOH parameter
listed in the static characteristics of the datasheet.
• High Low or Low High translation • Requires external components
• Additional system power
74
5
Low threshold inputs

CMOS devices with input switching
thresholds set lower than the typical VCC
VCC/2 can be used for Low to High

translation. Figure 5.9 shows an input D1
structure of a low threshold device. The P2
combination of N1 sizing and the drop

across diode D1 determines the input P1
Input
threshold. The P2 PMOS reduces
To logic
cross-bar current through the inverter. circuit
N1
The AHCT and HCT families operate at
5 V and have inputs that can be
interfaced to 5 V TTL or 3.3 V CMOS
outputs. AUP1T operate at 3.3 V and
can be used to interface to 1.8 V CMOS Figure 5.9 | CMOS input structure for low
outputs. threshold input
Devices with low-threshold inputs can be detected from data sheet properties:
They will have a ΔICC included in the static characteristics listed in the datasheet.
This is the extra static current due to an input being applied that is less than VCC.
Table 5 shows a fraction from the data sheet table specifying the additional ΔICC.
Table 5: Parameters for devices with low-threshold inputs

Smybol Parameter Conditions Min Typ Max Typ
ΔICC additional supply VI = VCC − 0.6 V; – – 50 μA

current IO = 0 A; VCC = 3.3 V
It must be ensured that power dissipation is minimized the input should be set low
as the default condition.
• No external components required • Higher power dissipation due to ΔICC
• Same footprint as standard function
75
Examples of combinations of translation features

Overvoltage-tolerant inputs with open-drain outputs
In some cases a modular system may Figure 5.10 shows the 74AUP2G07

consist of circuits in three different being supplied at 2.5 V and interfacing
voltage nodes. Control logic may be control signals between circuits at 3.3 V
required to ensure correct functionality and 1.2 V.
across all modules. A device that
includes overvoltage-tolerant inputs 1.2V
and opendrain outputs can be used to 2.5V
interface between three voltage 3.3V 1.2V

74AUP2G07
domains. Device Device
Figure 5.10 | OVT input with open drain

outputs
Clamp diode inputs with open-drain outputs A device that includes an ESD
protection diode and opendrain outputs can be used to interface between three
voltage domains. Figure 5.11 shows the 74HC3G07 being supplied at 5.0 V and
interfacing control signals between circuits at 12 V and 3.3 V Low-threshold inputs
with open-drain outputs.
A device that includes low-threshold inputs and open-drain outputs can be used to
interface between three voltage domains. Figure 5.12 shows the 74HCT3G07 being
supplied at 5.0 V and interfacing control signals between circuits at 3.3 V and 1.8 V.
3.3V
1.8V
5V 5V
RCL
12V 74HC3G07 3.3V
3.3V 74HCT3G07 1.8V
Device Device
Device Device
Figure 5.11 | Clamp diode inputs with open Figure 5.12 | Low threshold inputs with open
drain outputs drain outputs
76
5
5.2 Schmitt Trigger inputs

Schmitt trigger is a comparator circuit with hysteresis implemented. It is an active
circuit which can convert an analog input signal to a digital output signal. When the
input is higher than a chosen threshold, the output is high. When the input is below
a different (lower) chosen threshold, the output is low, and when the input is
between the two levels the output retains its value. This dual threshold action is
called hysteresis.
Schmitt trigger devices are typically used in signal conditioning applications to

remove noise from signals used in digital circuits, particularly mechanical contact
bounce in switches. They are also used in closed loop negative feedback
configurations to implement relaxation oscillators, used in function generators and
switching power supplies.
aaa-032351
Input 1 Input 2
(slow input signal) (noisy input signal)
∆t/∆V = no limits High

threshold
Vt+
Low
threshold
Vt-
t
t
Output
Figure 5.13 | The effect of noise compensation via Schmitt-Trigger input
A device with Schmitt-Trigger input has a specification for threshold voltage levels
in the static characteristics table as shown in Figure 5.14:
A similar input function is the Schmitt trigger action, it has a smaller hysteresis than
Schmitt-Trigger to improve noise immunity but will have an input and rise time limit
77
Figure 5.14 | Schmitt-Trigger Symbol and input voltage characteristics
Table 6: Schmitt-Trigger data sheet figures VT+, VT−, VH
Tamb Tamb
Conditions
Parameter
−40 °C to −40 °C to
Symbol
+85 °C +125 °C
Unit
Min Typ Max Min Max
VT+ positive-going VCC = 1.8 V 0,82 1 1,14 0,79 1,14 V

threshold voltage
VCC = 2.3 V 1,03 1,2 1,4 1 1,4 V
VCC = 3.0 V 1,29 1,5 1,71 1,26 1,71 V
VCC = 4.5 V 1,84 2,1 2,36 1,81 2,36 V
VCC = 5.5 V 2,19 2,5 2,79 2,16 2,79 V
VT- negative-going VCC = 1.8 V 0,46 0,6 0,75 0,46 0,78 V
threshold voltage
VCC = 2.3 V 0,65 0,8 0,96 0,65 0,99 V
VCC = 3.0 V 0,88 1 1,24 0,88 1,27 V
VCC = 4.5 V 1,32 1,5 1,84 1,32 1,87 V
VCC = 5.5 V 1,58 1,8 2,24 1,58 2,27 V
VH hysteresis voltage VCC = 1.8 V 0,26 0,4 0,51 0,19 0,51 V
VCC = 2.3 V 0,28 0,4 0,57 0,22 0,57 V
VCC = 3.0 V 0,31 0,5 0,64 0,25 0,64 V
VCC = 4.5 V 0,4 0,6 0,77 0,34 0,77 V
VCC = 5.5 V 0,47 0,6 0,88 0,41 0,88 V
78
5
Summary:

• Schmitt trigger inputs will have specs • Schmitt trigger action will have rise
of Vt+ and Vt- depicted in datasheets time and fall time limitations specified
• Schmitt trigger action will not have Vt for inputs in the recommended
specs in the datasheet operating conditions
5.3 IOFF mechanism and purpose

In a standard CMOS output circuit, body diodes of both NMOS and PMOS transistor
are conducting even if the transistor is not in conduction mode. When a circuit is
switched to partial power down mode, the body diode of the PMOS transistor is
still conducting to the VCC node if the output is connected to a certain voltage level.
This is not desired and the IOFF mechanism is used to mitigate this effect.
aaa-032352
BUS
VCC1 = 0
Device 1
IOFF
VCC3 = 0
AUP1G08 VCC2 = 0
IOFF
Device 2
IOFF
Figure 5.15 | Bus system with Logic devices featuring IOFF
79
5.4 Ground and VCC bounce

Ground bounce is usually seen on integrated circuits where insufficient precautions

have been taken to supply a logic gate with a sufficiently low resistance connection
(or sufficiently high capacitance) to ground. In this phenomenon, when a transistor
is turned on, enough current flows through the transistor circuit that the silicon in
the immediate vicinity of the ground connection is pulled partially high, sometimes
by several volts, thus raising the local ground, as perceived at the gate, to a value
significantly above true ground. Relative to this local ground, the gate voltage can
go negative, thus shutting off the transistor. As the excess local charge dissipates,
the transistor turns back on, possibly causing a repeat of the phenomenon,
sometimes up to several bounces.
VCC bounce is a similar effect based on insufficient capability of the supply rail to
drive the drawn current or by inductive effects of adjacent devices.
The VCC node in the power subsystem is supposed to be at a constant potential or a

constant voltage with respect to logic ground. Real power subsystems have varying
currents drawn from them. Real power subsystems have non-zero impedances. The
combination of these two result in “ripple” or VCC rail bounce. Any signal line that is
at a logic 1 using a CMOS driver will have this ripple riding on it unattenuated.
aaa-032353
Figure 5.16 | Ground bounce effect caused by signal switching
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5

aaa-032354
Figure 5.17 | VCC bounce effect caused by signal switching
Measures to mitigate ground and VCC bounce:
• Decoupling capacitors between VCC and ground provide a temporary, low

impedance, stable potential for the IC and localize the bounce effect to
keep it from spreading to the rest of your circuit. By keeping the
capacitors close to the IC, you minimize the area of inductive loop in the
PCB traces and decrease the disturbance
• serially-connected current-limiting resistors to prevent excessive current

from flowing into and out of the Device
• Address ground bounce in Layout/Routing implementation. Any

unnecessary separation between the signal and return path will increase
the inductance of that signal line and the subsequent effects of ground
bounce
• Measures to reduce VCC bounce are the same as described for reducing
Ground bounce.
81
5.5 Bus Hold

CMOS device inputs are connected to A way to mitigate this situation is to

the gate oxide of the NMOS and PMOS apply external pullup- or pull-down
transistors and have a very high circuits. However, if these measures
impedance. The advantage of CMOS, cannot be implemented, an internal
the very low power consumption under feature that can be offered to prevent
static conditions, is dependent on floating inputs is the Bus Hold feature.
defined levels of the gate input voltage.
In Figure 5.18 below we can see the
CMOS input schematics and the ΔICC
current/Vin curve. When VI has a value
at ~VDD/2, ICC reaches its peak and that
should only occur during a switching
process. If the input is floating and the
input voltage has a value nearby VDD/2,
an unwanted ΔICC current flows which
leads to undesired power consumption.
Figure 5.18 | ∆ICC current over VI
It provides a weak internal feedback inverter to the input, forming a latch together
with the input stage (see Figure 5.20). By doing so, the last input level (low or high)
is stored and thus the input voltage level is at a defined state, even in the absence
of external voltage supply. Due to the relative weakness of the feedback inverter,
the required driver strength of external signals at the input is not much increased.
With this feature, floating input condition and associated increased ΔICC can be
avoided.
Figure 5.19 | Illustration of ∆ICC current Figure 5.20 | Bus hold circuit
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5
• Bus-Hold is a standard feature of Nexperia’s LVT & ALVT bus interface

products. It is available as an option in Nexperia’s LVC, ALVC, and AVC bus
interface products. An H is used to identify the bus-hold option (e.g.
LVCH)
• Bus interface solutions from Nexperia include 8-, 16-, 18- and 32-bit
buffers/inverters/drivers, flip-flops, latches/registered drivers, level
shifters/translators and transceivers
In the data sheet, the Bus Hold properties are described in the table of static
characteristics (Table 7). An example is shown in Figure 5.20. The high and low hold
currents are the leakage currents in the device in high and low state respectively,
flowing into the common drain of the feedback inverter shown in Figure 5.20. The
overdrive currents are required to force the logic state to change into the
respective opposite direction.
Table 7: Static characteristic table for a transceiver with Bus Hold feature
Tamb Tamb
Conditions
Parameter
−40 °C to −40 °C to
Symbol
+85 °C +125 °C
Unit
Min Typ* Max Min Max
IBHL bus hold LOW VCC = 1.65 V;

10 – – 10 – μA
current VI = 0.58 V
VCC = 2.3 V; VI = 0.7 V 30 – – 25 – μA
VCC = 3.0 V; VI = 0.8 V 75 – – 60 – μA
IBHH bus hold HIGH VCC = 1.65 V;
−10 – – −10 – μA
current VI = 1.07 V
VCC = 2.3 V; VI = 1.7 V −30 – – −25 – μA
VCC = 3.0 V; VI = 2.0 V −75 – – −60 – μA
IBHLO bus hold LOW VCC = 1.95 V 200 – – 200 – μA
overdrive
VCC = 2.7 V 300 – – 300 – μA
current
VCC = 3.6 V 500 – – 500 – μA
IBHHO bus hold HIGH VCC = 1.95 V −200 – – −200 – μA
overdrive
VCC = 2.7 V −300 – – −300 – μA
current
VCC = 3.6 V −500 – – −500 – μA
* All typical values are measured at Tamb = 25 °C.
83
5.6 Source Termination

With increasing systems speeds and faster logic devices, interconnect

characteristics have become significant. The signal transition times of faster devices
can increase transmission line effects on printed circuit board traces and cables. If
not taken into consideration, signal degradation can cause data errors in a system.
Lumped and distributed systems
Series termination is one of many ways to terminate what are known as distributed
systems
Electronic systems can be considered as either lumped systems or distributed

systems. Factors that determine if a system is lumped or distributed include the rise
time of applied signals and the delay time of the conductor.
If all points on the conductor react to a potential at the same time the system is
lumped. Lumped systems have short trace lengths.
If all points on a conductor do not react

to a potential at the same time the
system is distributed. Distributed
systems have longer trace lengths.
Generally the border between lumped

and distributed systems occurs when
trace length exceeds the signal rise (ps)
Figure 5.21 | Calculation of conductor length
divided by six times the delay time of
the conductor (ps/in), as shown in the
equation in Figure 5.21.
Unlike lumped systems, distributed loads cannot be modeled using a single lumped
capacitance. Transmission line models must be applied to determine the
characteristic impedance of the distributed system.
If left unterminated, reflections occur in distributed systems. This is due to

impedance mismatch between the output and the load it is driving. Reflections can
lead to ringing on the signals. Unterminated distributed systems can lead to signal
integrity issues within applications.
84
5

Figure 5.22 | ZL = characteristic Impedance of Figure 5.23 | Signal diagram for driver with
distributed load distributed load
Source termination
To avoid signal integrity issues, one common way of terminating distributed

systems is source termination. In source termination, the output resistance of the
driver is matched to the characteristic impedance of the distributed system
The matching is done by adding a series resistor RS between the driver output and
the distributed load. The value of the series resistor is set to ZL – ROUT. ZL is the
characteristic impedance of the distributed system and ROUT is the output
resistance of the driver. The updated circuit diagram is shown is shown in
Figure 5.24, the improved Signal behaviour can be seen in Figure 5.25.
Figure 5.24 | Updated circuit of driver and Figure 5.25 | Improved signal behavior due to
load with series resistor added series resistor
85
The value of Rout is not given in the data sheet of the driver but can be calculated
from data sheet figures. In the table for static characteristics, the output high level
voltage VOH is specified for certain levels of IO and VCC. Rout is the ohmic resistance
of the output stage and can be calculated like Rout = (VCC-VOH)/IO, the values for
VCC, VOH and IO can be taken from the static characteristics tale in the data sheet as
shown in Table 8 below.
Table 8: Specification of VOH
Tamb Tamb
Conditions
Parameter
−40 °C to −40 °C to
Symbol
+85 °C +125 °C
Min Typ* Max Min Max Unit

output voltage
IO = −100 μA; VCC − VCC −
– – – V
VCC = 1.65 V to 3.6 V 0.2 0.3
IO = −4 mA;
1.2 – – 1.05 – V
VCC = 1.65 V
IO = −8 mA;
1.8 – – 1.65 – V
VCC = 2.3 V
IO = −12 mA;
2.2 – – 2.05 – V
VCC = 2.7 V
IO = −18 mA;
2.4 – – 2.25 – V
VCC = 3.0 V
IO = −24 mA;
2.2 – – 2.0 – V
VCC = 3.0 V
86
5
Integrated source termination

Nexperia provides solutions in which output impedance matching is included. In
general, the outputs are matched to a characteristic impedance of 50 ohms, making
them suitable for a range of common PCB trace and cable impedances. While not
providing perfect impedance matching for all loads, they can be used to reduce the
amplitude of reflections in applications that are space constrained. The undershoot
and overshoot performance into distributed systems of characteristic impedance
from 50 to 75 ohms is acceptable.
Nexperia’s advanced low voltage

BiCMOS LVT & ALVT families and
advanced low voltage CMOS families
LVC, ALVC & AVC(M) all include source
termination as an option. Many of
Nexperia’s 8-bit, 16-bit and 32-bit
products include source termination as
an option. These include buffers/
inverters/drivers, flip-flops, latches/
registered drivers and transceivers.
Figure 5.26 | Signal behaviour with
When source termination is included on 3 different internal source termination resistors
a transceiver device, it is included on
both ports.
When source termination is included as an option within a family, a 2 is added after

the family name in 8-bit devices. In 16-bit devices such as the 74LVC16244, the 2 is
added after the 16. 16244 is changed to 162244 to indicate that the source
termination feature is included.
87
88
6
Chapter 6

Analog and Logic
Product Segmentation
89
In this Chapter, the functions and features of discrete Logic and analog devices are
described. The coverage is largely corresponding to the product portfolio of

Nexperia and clustered in a similar way as in the Internet portal. For various product
groups, typical application examples are presented to support understanding and
practical usage of the product group.
6.1 Analog ICs
Analog Switches
Analog switches can be used to transmit both, analog and digital signals. An ohmic
conduction is established between input and output, implemented with MOSFETs
and controlled by logic gates. The structure of an Analog Switch is basically a
N-Channel FET in parallel with a P-Channel FET which allows signals to pass in either
direction like shown in Figure 6.1.
V-
N-CHANNEL
Input Output
S D
G
V+
P-CHANNEL
S D
G
Control
aaa-032355
LOGIC 1 = ON
Basic Internal Structure
Figure 6.1 | Analog Switch circuit
90
6
There are various kinds of analog switches classified as:

aaa-032356
aaa-032357
SPST SPDT
Figure 6.2a | Single pole single throw switch: Figure 6.2b | Single pole double throw switch:
one input is switched to one output one input is switched between 2 outputs
aaa-032358
aaa-032359
Enable
SP3T
Figure 6.2c | Single pole Triple throw switch:

1 input is switched between 3 outputs
DPDT
There are more permutations possible
and available, such as Single pole 4
throw, Single pole 8 throw, Single pole
Figure 6.2d | Double pole double throw:
16 throw. In all cases, switches are 2 inputs are switched to 2 outputs each
bidirectional, thus input and output can
be swapped.
91
Table 1: Important parameters for analog switches

Parameter Description Explanation
VI Input Voltage Range Determines the analog signal Amplitude

that can be passed without clipping
VIH / VIL Switch Control Signal Levels Digital control pin logic levels
RON(peak) ON resistance (peak) Maximum resistance of the switch when

conducting
RON(flat) ON resistance (flatness) Specifies the variation of RON with input

voltage
CS(ON) / ON-state/ Total Switch and Load Capacitance affect

CS(OFF) OFF-state capacitance response time, settling time, and fan out
limitation
f(-3dB) -3dB frequency response Bandwidth of the switch
THD total harmonic distortion Typical signal distortion caused by the switch
Xtalk Crosstalk Figure of merit for the isolation between

switches
Q Charge Injection Defines the amount of charge coupled into

the pass FET when switched on/off
MBB Make-Before-Break Guarantees that two Multiplexer paths are

never open when signal path is changed.
Disadvantage of this solution is that 2 inputs
could be temporarily shorted
BBM Break-Before-Make Guarantees that there is only one channel

active at a time and no more than one
channel being active simultaneously, which
excludes a scenario of two inputs being
connected during transition time
92
6
Bus switches

Like analog switches, Bus switches establish an ohmic connection between
terminals. In terms of functionality there are various overlaps and similarities with
normal analog switches. The main difference is that Bus switches need to be able
to properly disconnect in power-off mode. In a system with multiple participants
sharing the same bus, access to the bus must be controlled and thus disconnecting
the signal lines, also in power off mode, is an essential feature. In comparison to
analog switches, the transmission speed of bus switches is typically higher with up
to 500 MHz.
6.2 Asynchronous Interface Logic

In asynchronous Logic, signals are not synchronized with a clock signal. This cluster
includes:
• Buffers, Inverters, Drivers with single- and multi-bit topology.

• Transceivers
• Schmitt-Triggers
• Voltage translators
Lower-drive microcontroller signals are often not capable of controlling higher-load

peripherals. With high-impedance inputs and high-drive outputs asynchronous
interface logic is used to improve signal integrity. Beside buffers and inverters,
voltage translators are included in this section.
6.2.1 Buffers, Drivers, Inverters

aaa-032360
A Buffer is technically a series of two

Inverters which is used to refresh a
0 0=0
weak digital signal, typically caused by a
low strength drive output connected to
Buffer/Driver
a rather big capacitive load or many
parallel inputs. The output of the buffer
shall rebuild a properly shaped digital
waveform and improve signal integrity.
Both, non-inverting and inverting
functions are available. Figure 6.3 shows Buffer
the refreshing effect of a buffer.
Figure 6.3 | Symbol of a buffer
93
6.2.2 Transceivers
A Transceiver is a bidirectional Buffer, used to receive and/or transmit data from/to

a data bus. A direction control pin is used to select the direction of data flow.
aaa-032361
Transceiver
Direction Control
In/Out 1
In/Out 2
In/Out 1 In/Out 2
0 In Out
Direction Control 1 Out In
Figure 6.4 | Symbol and truth table of a transceiver
The simple transceiver is built of two buffers with direction control circuitry. Other
kinds of transceivers are also including latches or registers allowing to store input
values and release them to the output when needed.
Transceivers are available in many topologies such as single, dual, quad, octal, 16 or
18 bit editions related to bus connection requirements.
Various features are associated with transceivers:
• Open drain outputs

• Bus hold option for inputs maintaining the input value in case that the
input is not actively driven
• Schmitt-Trigger and Schmitt-action inputs providing input hysteresis.
More information about interfacing features is available in the Interface-Chapter.
94
6
6.2.3 Schmitt-Triggers

A Schmitt Trigger device has a hysteresis behavior for the detected logic state at an
input dependent on the direction of the state change. The input state and together
with this also an output of a logic function does not switch at a dedicated voltage.
A change of state happens later compared to a simple input if the input voltage
increases or decreases towards a state change.
The distance of the transition voltages
mna207
for the state changes define the width VO
of the hysteresis called VH. VT+ is the
voltage where the input state changes
from low level to high level whereas
VT- is the input voltage where the input
state changes from high level to low
level. In Figure 6.5 an example of a VI
VH
Schmitt-trigger Inverter is shown.
VT- VT+
Voltage for a state change of a
Schmitt-Trigger depends on the prior
Figure 6.5 | Input to Output transfer curve for
state, the input tends to keep an actual a Schmitt Trigger Inverter
state because of the hysteresis.
This makes Schmitt Trigger inputs more stable for noisy input signals. Normal logic
devices require a minimum rise and fall rate for input signals. Schmitt Trigger
devices do not have such kind of restrictions because there is not a risk of
undesired switching if there is noise on a smooth changing input signal.
For Schmitt Trigger components the parameter VH, VT+ and VT- can be found in the
input characteristics of the data sheet. Devices which do feature a small width for
the hysteresis of some 10 mV only are referred to as Schmitt (Trigger) action
devices. This small hysteresis is not quantified in the data sheets but mentioned in
the feature list.
95
In applications Schmitt Triggers are Ƭ = R*C. The second input of the gate
used for slow transition input signals works as an enable. Oscillation stops if
and in case of noise overlay. With enable is put to low level. The second
Schmitt Trigger Inverters, NAND or NOR gate is applied as buffer behind the
gates simple oscillators can be realized. oscillator.
Figure 6.6 shows the example of a
Application example:
NAND gate-based circuit (e.g.
74HCT132). The left side NAND is
coupled back from output to one input Enable
Vout
via a resistor. At this input a capacitor is
applied to ground. Because of the
R
inversion function, the capacitor is
charged until the output state changes
aaa-032008
C
to low level, then the capacitor is
discharged until the output swaps back
to high level. The circuit shown works as
Figure 6.6 | Schmitt Trigger NAND-Gate
a rectangular pulse generator. The time Oscillator with output buffer gate
constant for oscillation is dependent on
6.2.4 Voltage Translators
Many factors have caused the existence of the number of voltage domains in
modern applications. In modular designs, newer low voltage processors might need
to operate with proven peripherals which operate at higher voltages. Using
translators, signals of different voltage domains can be interfaced together.
In this product section voltage translators or level-shifters with different topology
can be found. The translators can be unidirectional or bidirectional with an
additional direction control pin for the data flow.
Types of translations
Uni-directional
Uni-directional translators can be either high-to-low or low-to-high level translators,
but the signal direction is fixed. For uni-directional translation, either single or dual
supply voltage topology is possible.
There are single supply translators which can provide a voltage translation towards
a lower voltage by means of an over-voltage tolerance at the inputs. This means
that the logic device is supplied with 2.5 V for example and input signals from a
3.3 V-driven device are provided.
96
6

3.3V
1.8V 3.3V
Receiver
Driver T
Figure 6.7 | Example showing a voltage translation device
For a translation from a low voltage towards a higher voltage logic inputs are
required that feature a rather low VIH rating. In this case a comparably low voltage
drive can switch safely between the logical states although the supply voltage is
relatively high. With open drain output devices, a level conversion from low to high
level is also simple if the maximum pull-up voltage has a rather high limit.
Dual supply voltage translators give more flexibility for a level up or down
translation. They have the advantage that the input levels are always perfectly
matched to VCCA, whereas VCCB defines the output voltages.
Dedicated voltage translator devices can be identified quite easily by the letter T in
the type name, e.g. 74AUP1T08 is a unidirectional, single supply device.
Bi-directional
Bi-directional translators are more flexible, both directions are supported. This is
associated with dual supply voltage, a bidirectional translation with a single supply
is not possible. An example of a bidirectional dual supply device is 74AUP1T45.
VCCA=5V VCCB=3.3V
Bi
Driver directional Receiver
Translator
Figure 6.8 | Bidirectional translating transceiver
97
Dual supply versus single power supply translation

Dual-supply voltage translators can be used for Low to High and High to Low
voltage translation. These devices are supplied at VCCA & VCCB and interface data
ports A & B, operating in different voltage domains. They feature output enable (OE)
and direction control (DIR) pins to enable or disable the outputs and control signal
direction. They are more power efficient than the single supply solutions. Gates,
buffers and shift registers are often implemented with translator function built in.
Advantage
• No ΔIcc issue as it always works with
DIR
proper input voltage levels
• Low power consumption for battery
operated & handheld systems
1A 1B
• Same interface
(w.r.t firmware & hardware)
• Flexibility in translating to/from a
variety of voltage nodes
Disadvantage
nA nB
• Different footprint leads to change in
VCCA VCCB
the layout.
• Larger packages are required, extra
pin for second supply. Figure 6.9 | Multi bit dual supply transceiver
6.2.5 Bi-directional translation with automatic sensing
If bi-directional translation is needed but no direction signal by the system

components is available, an auto sensing translator can be used to resolve the
problem. A pair of I/O spanning voltage domains can act as either inputs or outputs
depending on external stimulus without the need for a dedicated direction control
pin. Internally, an extra current sensing circuit detect the direction and configures
the translation circuit accordingly.
LSF translators
THE LSF010x translator family is a bidirectional multi-voltage level translator with

an internal pass transistor. It has a reference channel and, dependent on the type,
several translation channels that can be used independently. The independent
usage of the channels is meant in terms of different voltage levels as well as
different directions.
98
6
Using reference channel and enable pins

The internal structure of the LSF translator is shown in Figure 6.10, as an example
of an LSF0101 with one translating channel. The source of the reference channel is
supplied by Vref_A, resulting in a voltage level of Vref_A + VTH (~0.8 V) at the source
of Vref_B and at the gates of all pass transistors in the IC. Thus, the gate voltage
levels of all pass transistors is determined by Vref_A.
The enable pin of the LSF translator should be externally shorted to the Vref_B pin.
If the enable pin shall be controlled dynamically, this pin should not be driven by a
push-pull stage because in case of high level drive, the enable pin voltage would be
forced to the supply voltage level of the driver. Instead, the enable pin should be
driven with an open drain driver without a pull-up resistor, as it is already provided
by Vref_B.
aaa-032362
Vref_B
supply
Vref_A
200 kΩ
supply
Vref_A EN Vref_B
VBPU
Vref_A + VTH
A1 B1
Figure 6.10 | Using enable and reference Voltage of a LSF0101 translator
99
Translation channel usage

If the transmitter uses a push-pull stage, the external pull-up resistors can be
omitted. For open drain transmission drivers, external pull-up resistors are essential
as open-drain outputs can only drive the low state actively.
Down translation
It is recommended to connect the B-side to the higher voltage. In the down
translation scenario, the B-side is driving and the A-side is receiving.
When the driver is driving a low voltage, the input of the translator is pulled to low
level, causing the internal transmission FET to conduct. This will open the
connection to the output of the transistor and current will flow from the output
through the pass transistor into the open drain of the driver. As a result, the output
at the A-side is pulled down to low level.
When the driver outputs a high level, the output voltage will follow the input until
the FET turns off. The output voltage will then be pulled high by via the pull-up
resistor on the A-Side.
Up translation
In this use case, the A-side is driving and the B-side is receiving. When the
transmitter is driving the input low, the internal pass transistor will be turned on,
pulling down the output of the translator as well as in down translation scenario.
When the driver is driving a high level, the output voltage will follow the input until
the FET turns off. The output voltage will then be pulled high by via the pull-up
resistor on the B-Side.
Multi voltage translation application Example

The LSF translator can also be used to translate different voltage levels per channel
as shown in the example in Figure 6.11. It shows a scenario with one
Microcontroller and three communication partners, each of them operating at a
different voltage level. On the A-side, each channel is pulled up to 3.3 V via a
resistor. This is important because if the Microcontroller is in receive mode, it’s
inputs are high impedance and without the pull-up resistors on the A-side, the input
voltage of the Microcontroller I/O would have the high level of the respective
transmitter from the B-side rather than the required own input voltage level.
It is also important to select the Vref_A supply voltage to the lowest in the system,
in the example case in Figure 6.11, determined to 1.2 V by Receiver 2, marked with
a red circle.
100
6

Figure 6.11 | LSF translation with multi voltage receivers
Calculating pull-up resistor values

On the A-side, pull-up resistors are only required in case of Vref_A < VCC of the
device on the A-side. Otherwise the A-side high level voltage will be determined by
Vref_A. In case where there is only one voltage domain per side, pull-up resistors on
the A-side are not needed.
For the calculation of external pull-up resistors, we assume that Vref is opening the
channel of the pass transistor sufficiently so that we can use the values for Ron
from the data sheet.
the pullup-resistor on the B-side shown in Figure 6.12 can be calculated using the
assumptions:
200kΩ
LSF0102
VCCA VCCB
RPU RPU Enable RPU RPU
refA refB
I2C Slave
I2C Master
SDA SDA
SDA SDA
SCL SCL
SCL SCL
Figure 6.12 | Example of I2C translation with Master in transmission mode
101
𝐼𝐼!! !"# × 𝑉𝑉!! − 𝐶𝐶! × 𝑉𝑉!!! × 𝑓𝑓! + 𝑉𝑉!! × 𝐼𝐼!"#"
𝐶𝐶!" =
6 𝑉𝑉!!! ×𝑓𝑓! nexperia | Design Engineer’s Guide
!
The A-side2.24 𝑚𝑚𝑚𝑚 ×down
is pulling 3.6 𝑉𝑉 the
− voltage
50 𝑝𝑝𝑝𝑝level
× 3.6 𝑉𝑉 a ×
and 10 𝑀𝑀𝑀𝑀𝑀𝑀
current flows+from
0 𝑚𝑚𝑚𝑚
B to A or the
𝐶𝐶!" =
B-side is pulling low and current 3.6 𝑉𝑉 ! × 10directly
is flowing 𝑀𝑀𝑀𝑀𝑀𝑀 from VCCB into the target
device
𝐶𝐶!" =at12.2
the 𝑝𝑝𝑝𝑝
B-side.
When the B-side is pulled LOW following the above assumptions, the condition will
exist that the specified VOL(B) is higher than the V!IL(A), so in order for the solution to
11.53 𝑚𝑚𝑚𝑚 × 3.6 𝑉𝑉 − 50 𝑝𝑝𝑝𝑝 × 3.6 𝑉𝑉 × 30 𝑀𝑀𝑀𝑀𝑀𝑀
𝐶𝐶!" = VOL(B) is lowered to be!equal to VIL(A) in order for the I/O to register a LOW.
operate,
3.6 𝑉𝑉 × 30 𝑀𝑀𝑀𝑀𝑀𝑀
Therefore, the voltage at B1 must be calculated to be VIL(A). Since no current flows
𝐶𝐶!" = 56.8
through 𝑝𝑝𝑝𝑝
the switch, the voltage at B1 equals the voltage at A1, and the I/O is
satisfied. The current path is shown in Figure 6.12. ID(B) is equal to the B-side driver
sink current.
! !
𝑃𝑃 = 𝐶𝐶
! !" !!× 𝑉𝑉 !" × 𝑓𝑓 +
! !! 𝐶𝐶 × 𝑉𝑉
!"# × 𝑓𝑓
Equation 3 calculates Rpu when the B-side is asserted.
!!" ! !!"(!) !.! ! ! !.!" ! (3)

𝑅𝑅!" = = = 210 Ω
!!(!) !" !!
The lower limit of the pull-up resistor is determined by the VIL level and the drive
current of the devices. The high limit of the pull-up resistor is determined by
frequency requirements, too high resistance reduces the maximum frequency.
NXS translators
The second auto sense translator family we present is the NXS family. Like the LSF,
it is bidirectional and capable of multi-voltage level translation. The NXS has an
internal pass transistor and additional one shot circuits to accelerate rising edges of
the input signals. Internal 10 kΩ pull-up resistors lift up the output voltage of a
channel to the respective pull-up voltage.
To achieve faster data rates through the device, these translators include rising
edge-rate acceleration circuitry to provide stronger drive for the rising edge by
bypassing the integrated 10-kΩ pull-up resistors through a low impedance path
during low-to-high signal transitions. A one-shot (O.S.) circuit with an associated
T1/ T2
1
PMOS transistor is used to increase switching speeds for the rising-edge
input signals. When a rising edge is detected by the O.S. circuit, the T1/T2 PMOS
transistors turn on momentarily to rapidly drive the port high, effectively lowering
the output impedance seen on that port and speeding up rising edge inputs.
102
6
The N-channel pass-gate transistor is used to open and close the connection

between the A and B ports. When a driver connected to A or B port is low, the
opposite port is, in turn, pulled low by the N2 pass-gate transistor. The gate bias
voltage of the pass-gate transistor (T3) is set at approximately one threshold
voltage above the VCC level of the low-voltage side. During a low-to-high transition,
the output one-shot accelerates the output transition by switching on the PMOS
transistors (T1, T2), bypassing the 10 kΩ pull-up resistors, and increasing current
drive capability. The one-shot is activated once the input transition reaches
approximately VCCI/2, and is de-activated approximately 50 ns after the output
reaches VCCO/2. During the acceleration time, the driver output resistance is
between approximately 50 and 70 Ω. To avoid signal contention and minimize
dynamic ICC, the user should wait for the one-shot circuit to turn off before
applying a signal in the opposite direction. The pass-gate transistor T3 is on when
VGS is greater than VT. When one side of T3 is held low by an external driver, with
the input to T3 at 0 V, T3 will be on and the output of T3 will be held to nearly 0 V
due to the on-state resistance of T3. As the input voltage rises due to a rising edge,
the output voltage of T3 tracks the input until the input voltage reaches VGATE
minus VT and T3 turns off. After T3 stops conducting, the input and output ports
continue to rise to their respective supply voltages due to the internal pull-up
resistors. In the second case, both ports start with high levels since the integrated
pull-up resistors tie the inputs to the respective supply voltages, VCC(A) and VCC(B).
When the input ports are pulled low by external drivers, T3 starts to conduct when
VGS is greater than VT and output starts tracking the input. The source current
needed for this operation must be provided by the external driver connected to
the A or B port.
Input driver requirements

Since NXS level shifters are switch-type level shifters, properties of the input driver
directly affect the output signal. The external open-drain or push-pull driver applied
to an I/O determines the static current sinking capability of the system; the
maximum data rate high-to-low output transition time (tTHL) and the propagation
delay (tPHL) depend on the output impedance and the edge rate of the external
driver. The limits provided in the datasheet for these parameters assume use of a
driver with output impedance below 50 Ω.
Output load considerations

The maximum lumped capacitive load that can be driven depends on the one-shot
pulse duration. In cases with very heavy capacitive loading, there is a risk that the
output will not reach the positive rail within the one-shot pulse duration. Capacitive
loads up to 150 pF can be driven without any issues using NXS level shifters.
103
NXB translators
NXB translators are the third bidirectional autosense translator family of Nexperia.
Figure 6.13 shows the architecture of one I/O channel of an NXB level translator.
The translator incorporates a weak buffer with one-shot circuitry to improve
switching speeds for rising and falling edges. When the A port is connected to a
system driver and driven high, the weak 4 kΩ buffer drives the B port high in
conjunction with the upper one shot, which becomes active when it senses a rising
edge. The B port is driven high by both the buffer and the T1 PMOS, which lowers
the output impedance seen on the B port while the one-shot circuit is active. On
the falling edge, the lower one-shot is triggered and the buffer, along with the T2
NMOS, lowers the output impedance seen on the B port while the one-shot circuit
is operating and the output is driven low. Figure 6.14 shows the active circuitry in
the NXB I/O channel during translations from low to high and high to low.
001aal965
VCC(A) VCC(B)
T1 T2
ONE ONE
SHOT SHOT
10 kΩ 10 kΩ
GATE BIAS
T3
A B
Figure 6.13 | Basic NXS Architecture
104
6

001aal921
VCC(A) VCC(B)
ONE
SHOT T1
4 kΩ
T2
ONE
SHOT
B
A
ONE
T3 SHOT
4 kΩ
T4
ONE
SHOT
Figure 6.14 | Architecture of a NXB IO cell
105
6.3 Synchronous Logic

6.3.1 Flip Flops
A flipflop is a circuit with two stable conditions at the output.
An RS-Flipflop can be realized with basic gates. Figure 6.15 shows a realization with
two NOR-Gates. Table 2 shows how the output reacts on the setting of the control
inputs S (set) and R (reset). The input pins realize a positive control, so the flipflop
can be set and reset with a high level at the corresponding input pin. With both
inputs at low level, the state programmed before is stored.
If both control pins are put to high state at the same time, both outputs deliver a
low state which is not a desired condition as Q and QN are not inverse anymore.
After a change from this input control towards the store state, the output will
acquire a random logical state. So putting both inputs to high cannot be
recommended and should be avoided.
Table 2: Control table for Flipflop created with 2 NOR-Gates
aaa-032009
Input Input Output Output
S
S R Y QN Q
1 0 1 0
0 1 0 1
Q'
R
0 0 Store Store
1 1 0 0 Figure 6.15 | RS-Flipflop
created with NOR-Gates
If 2 NAND-Gates are connected in the same structure like the NOR-Gate approach
discussed above, a circuit as depicted in Figure 6.16 is realized. We get an RS-
Flipflop again but with negative control logic. This means the a low level at the set
or reset input programs the state of the flipflop. With both inputs high, the storage
condition is created. Putting both input pins to low is the forbidden condition
which can lead to a random state after changing into the storage state.
106
6
Table 3: Control table for Flipflop created with 2 NAND-Gates

aaa-032010
Input Input Output Output
S
S R Q Q Q
0 1 1 0
1 0 0 1
Q
R
1 1 Store Store
0 0 1 1 Figure 6.16 | RS-Flipflop
created with NAND-Gates
6.3.2 Latch or D-flipflop with level controlled enable
A simple extension of an RS-Flipflop creates a D-Flipflop or latch like depicted in the

principle schematic in Figure 6.17. The data input is one input signal to an AND-
Gate which second input is connected to an Enable signal. The inverted data signal
is connected to a second AND-Gate which is connected to Enable at the second
input again. Behind the two AND-Gates an RS-Flipflop is placed.
If Enable is at high state the flipflop is either set or reset dependent on the state at
the D-Input. While the Enable signal is high, the incoming D signal can be seen at
the output Q, the latch is transparent. If Enable is low, the last state is stored.
Table 4: Function Table for Latch or level controlled D-Flipflop

aaa-032011
Input Input Output

D E Q D
Q
0 1 0 E
Q
1 1 1
Store
X 0 Figure 6.17 | Principle schematic of a
last state
level-controlled Latch or D-Flipflop
Different from the principle diagram in Figure 6.17, a transparent latch can be

designed like shown in Figure 6.18. For Latch Enable (LE) in high state the incoming
signal D is fed to the inverter towards the output, with the left side switch in
on-state. The switch in the feedback loop is in off-state. If LE is turned off, incoming
data are disconnected by the switch at the data input which is in off-state. The
second switch feeds back the inverted QN signal to the input of the output
inverter, so the current state is kept stable and stored.
107
001aae051
LE
LE
LE
D Q
LE
Figure 6.18 | Transparent Latch
The described level controlled D-flipflop type can also be found combined to larger
multi-bit transparent latches for usage in a wider data bus. Figure 6.19 shows an
8-bit example with latch-enable control pin LE and an additional output enable OE
control option with two symbol versions.
001aae048
001aae049
11
1
OE EN
LE
3 2 11 C1
D0 Q0 LE
4 5
D1 Q1
3 2
7 6 D0 1D Q0
D2 Q2
4 5
8 9 D1 Q1
D3 Q3
7 6
13 12 D2 Q2
D4 Q4 8 9
14 15 D3 Q3
D5 Q5 13 12
17 16 D4 Q4
D6 Q6 14 15
D5 Q5
18 19
D7 Q7 17 16
D6 Q6
OE
18 19
D7 Q7
1
Figure 6.19 | Symbols for an 8 bit transparent latch
108
6
6.3.3 Edge triggered flipflops and registers

More complex und high speed logic designs need to be realized as a synchronous
digital network. In order to cope with propagation delay variation over
temperature, process spread and supply voltage, it is necessary to have an
edge-driven design approach. By a defined sampling of data into storage elements
with e.g. the rising edge of a master clock, different delays in the design become
resynchronized and the circuit can work reliable. The overall processing delay
becomes multiples of the cycle time of the clock dependent on the number of
edge-controlled storage elements used in series.
6.3.4 Edge-controlled D-Flipflop
The basic element for a synchronous design is an edge-controlled D-Flipflop.

Figure 6.20 shows the logic diagram of such a flipflop. There are two latched run in
series. The latch enable signal, now driven by the clock signal CP (C and CN after
inversion and buffering), works as described in the prior section. The control for the
second latch is inverted compared to the latch at the input. While the clock is in low
state, the latch placed on the data input side is transparent. The second latch is in
the storage mode and outputs the logic state of the prior clock cycle. Once the
clock signal changes to high state, the first latch stores the latest state from the
input and the second latch becomes transparent and outputs this logical state with
short delay to the rising edge of the clock.
Q
C
C
C
C
C
C
D
Q
C C
RD
SD
CP C
mna421
Figure 6.20 | Logic diagram of an rising clock edge triggered D-Flipflop
The schematics in Figure 6.20 includes a non-synchronous, so a direct, active low

state driven set and reset function that immediately puts the latches in the circuit
into the required state.
109
4
S 5
3
C1
6 2 nexperia | Design Engineer’s Guide
1
1D 6
R
Figure 6.21 shows the IEC symbol of the

mna419
described D-Flipflop with all the control 10
S 9
pins, means a clock input for rising edge 11
C1
operation, a positive logic output and 12
1D 8
an inverted output, the D-input for the 13
R
signal to be sampled and the low active
set and reset pins for non-synchronous
initialization of the flipflop. Figure 6.21 | IEC symbol of an edge-triggered
D-Flipflop
6.3.5 JK-Flipflop
Another variant of an edge-controlled flipflop is a so-called JK-Flipflop. Table 5

shows the action of the flipflop dependent on the settings of the J and K input. If
the input J is set to 1 while K is cleared, the flipflop will be set with the next active
edge of the clock. In this case it is assumed that the flipflop works with the rising
edge of the clock. If J is cleared and K is set, the flipflop is prepared to be reset with
the next active clock edge. If both inputs are cleared, the flipflop stores the logical
state that was present after the prior clock edge already.
Table 5: Function table of a JK-Flipflop with action

on rising edge of the clock
Action Clock J K Q Q
set  1 0 1 0
reset  0 1 0 1
Hold/Store  0 0 q q
Toggle  1 1 q q
As products various variants of the flip

aaa-032012
flop type exist with either active 5

S
negative edge clock operation or 2
1J 6
inverted J and K inputs. Figure 6.22 4
shows an example with a positive C1 7
3
J-Input polarity and a negative polarity 1K
K input. The part also supports an 1
R
asynchronous set and reset function via
negative polarity activated inputs.
Figure 6.22 | Example of a symbol for a
JK-Flipflop
110
6
6.3.6 Parallel-Registers

If many flipflop are put in parallel a register is created. It can store not a single bit
only but several bits, so a multi digit word. In registers the same basic flipflop types
can be found like described in the sections above. Most of the registers sample the
incoming data edge-triggered. Figure 6.23 shows an example of an octal D-Flipflop
register that is triggered by the positive edge of the clock signal. The outputs are
enabled if the input OE is at low level.
mna893
D0 D1 D2 D3 D4 D5 D6 D7
D Q D Q D Q D Q D Q D Q D Q D Q
CP CP CP CP CP CP CP CP
FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8
CP
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Figure 6.23 | Logic diagram of an octal register, positive clock edge triggered
In Figure 6.24 an equivalent register device based on transparent latches is

depicted. While LE is high and the output are enabled, incoming data appear at the
outputs. Once LE is set to low level, the latest state of the 8 bits is stored.
001aae052
D0 D1 D2 D3 D4 D5 D6 D7
LATCH LATCH LATCH LATCH LATCH LATCH LATCH LATCH
1 2 3 4 5 6 7 8
LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE
LE
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Figure 6.24 | Logic diagram of an octal transparent latch register controlled by LE
111
6.3.7 FIFO Registers

FiFO stands for first in first out. A FiFO Register delivers data that has been stored
first also as first data to the output. Simple shift registers with a single clock work
as a simple FIFO. They generate a constant delay by a number of clocks, which is the
length of the shift register in bits.
More sophisticated is a flexible storage which has independent input and output
clocks. Data stored into the FIFO appear at the output with the next output clock. A
maximum number of data words can be stored. Such a FIFO can be used as a buffer
if writing and reading clock is not identical. Input and output pointers need to be
controlled correctly and it needs to be indicated whether the FIFO is empty or full.
An application example is e.g. a CD-player where the output data have to run with
an exact crystal clock but data read from the disc have some speed variation from
the optical laser unit reading data from the rotating disc. The rotation speed has to
be controlled such that the buffer FIFO compensates possible deviations of the
rotation speed and thus can provide data to the output all the time. The buffer
should be filled half in average, to allow a maximum safety buffer.
6.3.8 Counters
Ripple counter
If the inverted output of an edge-triggered flipflop is fed back to the D-input, the
output toggles with half of the clock frequency. A clock divider by the factor 2 is
created. Figure 6.25 shows the simple approach of a toggle flipflop. The state of
the output is changing state with every rising edge of the clock.
+5 V +5 V +5 V
D S S S
D D
Qo
Q Qout Q Q Q1
CLK CLK CLK CLK CLK
Q Q Q
R R R
+5 V +5 V +5 V
CLK
CLK
aaa-032013
aaa-032014
Q1
Qout
Figure 6.25 | Toggle Flipflop Figure 6.26 | 2 Stage Ripple-Counter
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6
If the depicted stage of Figure 6.25 is put in series, a division of the clock by a

higher factor can be realized. With N stages a division by 2N is created for the
output of the last stage in the serial structure. Figure 6.26 shows the simple
example of a 2-stage Ripple-Counter which divides the clock by the factor 4. The
second flipflop gets the output signal of the first stage as clock signal. Therefore
the propagation delay from data input to the output of each flipflop sums up for
the delay of an output QN according the equation: tpdN = (N + 1) * tpd
This behavior is the reason for the name ripple counter because state changes
ripple through the entire counter from the first flipflop to the last in the series
structure. If a specific state is selected by gates connected to the outputs, this can
lead to spikes during the settling of the final counter condition.
Synchronous Counter
For an synchronous counter all flipflops change the state at the same time. Each
flipflop gets the same clock signal. In Figure 6.27 an example of a 4-stage
synchronous counter is shown. This counter supports a synchronous parallel load
and reset operation. The counter has a special carry output supporting the
construction of bigger counters.
aaa-012189
D0 D1 D2 D3
CET
CEP
PE
MR
FF FF FF FF
D 1 Q D 2 Q D 3 Q D 4 Q
CP CP CP CP CP
Q Q Q Q
Q0 Q1 Q2 Q3 TC
Figure 6.27 | Logic diagram of a 4-bit synchronous counter with parallel load and reset
113
Table 6 shows how to control the counter. A low case variable in the table indicates
that the input has to be in the logical state listed at least the set-up time before the
next rising edge of the clock appears. If the Reset pin MR is set to low level, the
counter is cleared with the next active clock edge. This means all Outputs aquire a
low state, as depicted with a capitol L in the table. The reset function has the
highest priority and overrides all other functions. If the input PE is set to low level,
the data applied to the Dn inputs is taken over by the flipflops with the next rising
edge of the clock. If the counter shall count, both inputs, CP and CET need to be set
to high level while no parallel load or reset action is initialized. For cascading of the
counters, the TC output is simply connected to the CET input of the next counter. If
counter one reaches the state 15, TC junps to high state and with the next clock
cycle the second counter increments its counter state by 1.
The preset option and the reset operation can be used to modify the counter
sequence. This means the counter can start at a higher value than zero by help of
the parallel load or alternatively it can be reset before reaching the maximum value
of 15.
Table 6: Function table of the synchronous counter shown in Figure 6.27
Inputs Outputs
Operating
Mode MR CP CEP CET PE Dn Qn TC
Reset l  X X X X L L
h  X X l l L L
Parallel Load
h  X X l h H L
Count h  h h h X count
h X l l X X qn L
Hold
(do nothing)
h X X X l X qn L
Counters are used in a lot of applications. They can be used to get exact timing
windows derived from a precise clock source, to create a digital delay or to
generate multiple control signals like shown in Figure 6.28. The signals can have any
waveform within the distance between 2 reset signals. This could be for example a
horizontal timing controller for digital TV to create memory control signals. The
output register samples the outputs from the decoding block behind the counter
and ensures that all signal have the same delay between clock and the outputs.
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6

aaa-032363 001aak192
CEXT REXT
GND VCC
Signal 1
Clock nCEXT nREXT/CEXT
Signal 2
nQ
Register
Counter
Reset n Control nA T
logic Signal nB
nQ T = 0.7 × REXT × CEXT
(n-1)
Signal n nCD
Figure 6.28 | Application example for a Figure 6.29 | Monostable Multivibrator

synchronous counter with attached decoding
control network and output register
6.3.9 Monostable Multivibrator
Monostable multivibrators create an output pulse that is triggered with an edge of

a digital signal. The length of the pulse is defined by a time constant realized with
the selection of a proper resistor and capacitor combination. Many monostable
multivibrators have a so-called retrigger function. The output pulse is extended by
an additional window in time, so the output stays high, as adjusted via the RC
combination restarted with every incoming trigger event. This feature can be used
to detect if input pulses appear within a given time. In a conventional car the supply
for the electrical fuel pump has to be turned off if no ignition pulses are present.
With the described logic device such a function can be realized easily.
Figure 6.29 shows a block diagram of a monostable multivibrator which can be

triggered either with the rising or falling edge of a digital signal like shown in
Table 7. With nA set to high level, a rising edge at the input nB the device is
triggered and the output switches to high level for the selected duration T
according to the formula below.
Table 7: Function Table of a Monostable Multivibrator

as depicted in Figure 6.29
Inputs Outputs
nA nB nCD nQ nQ
 L H
H  H
X X L L H
115
Big capacitors tend to change capacity over lifetime and often suffer from leakage
current at high temperature. This limits the accuracy of the pulse length generated
and needs to be taken into account if the devices shall be used for very long pulses.
6.4 Where to use Synchronous Interface Logic

Synchronous logic design is using a common clock signal which is provided to
edge-driven flipflops in order to achieve a fully reproducible timing between
processing blocks and for the whole design. A complex digital design has to be
partitioned into the discrete times steps of the clock signal. If there is for example a
complex decoding stage, the output of this block needs to be ready to be safely
taken over by a connected flipflop stage with the next e.g. rising edge of the clock.
For every assumed process spread and targeted operating temperature of the
design sampling of the signals by the flipflops needs to be safe and predictable. If
an asynchronous digital processing takes too long it can be necessary to introduce
an additional flipflop for safe sampling of the signals.
IO expansion Logic
In case of limited IO pin count of a core processor in an application, IO expansion

Logic devices can be used to generate additional interface pins.
Analog switches and Bus switches
Analog switches and Bus switches are used for IO expansion and are already
described in section Analog.
Decoders/Demultiplexers
Decoders are logic devices that convert a digit al input format into another one at
the output. As an example a BCD 4-bit input can be decoded to 10 separate
outputs. Exactly one output is changing state for the 10 possible input
combinations. Figure 6.30 shows an example for such a device. Any other
combination of 3 bits at the input to 8 outputs, or a 4 bit input towards 16 outputs
are further examples of decoders.
In an application the decoders can be used to select and activate a memory bank in
an SSD application for example.
116
6

001aae600
Y0
Y1
A0
Y2
Y3
A1
Y4
Y5
A2
Y6
Y7
A3
Y8
Y9
Figure 6.30 | BCD to decimal 10 outputs decoder
117
Digital Multiplexers
Digital multiplexers have digital inputs like a logic gate with a VIL(max) and VIH(min)
rating. Via selection pins an input can be chosen and the incoming data stream is
connected to an output. This means that data from an input to an output are
re-shaped and not simply connected through like for an analog switch. Digital
multiplexers can have different topologies with different number of inputs to be
selected. If several multiplexers are put in parallel complete busses can be
switched. Figure 6.31 shows an example of an 8 input to one output multiplexer.
aaa-008237
I7
I6
I5
I4
Y
I3
I2
Y
I1
I0
S2 S1 S0 OE
Figure 6.31 | Digital 8-to-1 multiplexer
Shift Registers
If edge-triggered D-Flipflops are put in series like depicted in Figure 6.32, a shift

register is created. In the example there are 2 inputs to an AND-Gate that provides
the input to the first D-Flipflop in the chain. A incoming data signal at the shift
input DSA is taken over with the rising edge of the clock signal CP, if CPB is at logic
high-level. The state of each flipflop is shifted to the next flipflop in the series
structure with every clock cycle. Data sampled present at Q0 from FF1, appear 7
clocks later the output Q7. The whole shifter register can be cleared via the MR
input.
118
6

DSA
DSB CP CP CP CP CP CP CP CP
FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8
RD RD RD RD RD RD RD RD
CP
MR
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
001aac616
Figure 6.32 | Logic diagram of an 8-Bit Shift register
The major application area for shift registers is the serial to parallel data
conversion. Therefore shift registers with an additional register connected to the
outputs can be found as a useful configuration supporting this function. Once a
word is shifted at the desired position in the shift register, the output register takes
over this value. A new value is sampled after a new word is completed in the shift
register. Figure 6.33 shows an example for such a component. SHCP is the shifting
clock for the shift register. With the rising edge of STCP data are stored into the
output register.
STAGE 0 STAGES 1 TO 6 STAGE 7
DS D Q D Q D Q Q7S
FF0 FF7
CP CP
R R
SHCP
MR
D Q D Q
LATCH LATCH
CP CP
STCP
OE
mna555
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Figure 6.33 | Logic diagram of a shift register with output latch
119
Shift registers can be used for a parallel

aaa-012056
STCP MR DS
to serial conversion as well. This
function can be realized with a shift 12 10 14
D0 15
registers featuring a parallel load
D1 1
function.
D2 2
Figure 6.34 shows a suitable device
D3 3 INPUT 8-BIT
which can convert incoming 8 bit words FLIP- SHIFT
D4 4 FLOPS REGISTER
into a serial data stream. The parallel
data is stored in the input register with D5 5
the rising edge of STCP. If the parallel D6 6
load input PL is at low level the clock D7 7 9 Q

13 11
STCP loads the input data directly into
the shift register. If there is no rising PL SHCP
clock edge while PL low, data stored in
the input latch are transferred to the Figure 6.34 | Logic diagram of a shift register
shift register. The shifting clock SHCP with parallel load (74HC/HCT597 as example)
shifts data from Qn-1 to Qn and takes

over new input data from the serial 1
001aad943
A
input DS. 3
B
4
6 Y
Control Logic C
The devices of the Control Logic

Figure 6.35 | Combination of AND and OR
segments are mainly Gates and some gate
digital comparators.
Gates A
3
The Gate portfolio covers simple gates 4

Y
1
like AND, NAND, OR, NOR, XOR, XNOR, B
some combination gates and

001aad998
6
configurable logic gates. The Basic gate C
functions are already well described in

Chapter 2: Logic Basics.
Figure 6.36 | Configurable logic gate
74AUP1G97
Combination gates are two or more discrete logic gates in a single logic solution.
The integrated gates may be internally connected to generate a specific Boolean
function or can remain independent. The devices include over-voltage tolerant
input options and open-drain output options to facilitate interfacing between
different voltage nodes. An example for a combination gate can be seen in
Figure 6.35, the function is 0832: 08 for the AND gate, 32 for the OR gate.
120
6
Configurable Logic is offering various functions in a device, where the choice for the

function is dependent on the external pin configuration. It can be an advantage
especially when components need to be qualified for usage in an application. Flexible
usage can be a factor of cost saving here. An example for a configurable gate is the
74AUP1G97, which is providing multiple configurable functions. The output state is
determined by eight patterns of 3-bit input. The user can choose the logic functions
MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to VCC
or GND. The block diagram Figure 6.36 shows the internal circuit of the 1G97.
The possible functions that can be implemented are shown in the following figures:
001aae002 VCC 001aae003 VCC
B 1 6 C 1 6 C
B
Y A
2 5 Y 2 5
C
A
A 3 4 Y A 3 4 Y
C
Figure 6.37a | 2-Input MUX Figure 6.36b | 2-Input AND gate
001aae004 VCC 001aae005 VCC
A B
Y 1 6 C Y B 1 6 C
C C
2 5 2 5
A B
Y A 3 4 Y Y 3 4 Y
C C
Figure 6.37c | 2-Input NAND or 2-Input OR Figure 6.37d | 2-Input NOR or 2-Input AND gate
001aae006 001aae007 VCC

VCC
B 1 6 C
1 6 C
B
Y 2 5
C C Y 2 5
3 4 Y
3 4 Y
Figure 6.37e | 2-Input OR gate Figure 6.37f | Inverter
001aae008 VCC
B 1 6
B Y 2 5
3 4 Y
Figure 6.37g | Buffer
121
Digital comparators
Digital comparators perform a pairwise comparison of two input words, either 4 bit
or 8 bit. The result is a one bit output indicating equality of the two input data
words. This can be helpful in cases where input pins of processors are not available
and only a simple comparison of data words is needed.
122
7
Chapter 7
Packages
Packages
123
This chapter explains and discusses various aspects of packages for Logic IC’s. The
Packages
sections are split into Mini Logic packages with up to 10 pins and Standard Logic
packages with more than 10 pins.
7.1 Standard Logic Packages

Modern applications require improved electrical and mechanical performance,
smaller size and lower cost.
Most of Logic IC packaging options support wider temperature ranges (−40°C to

+125°C), and many are also offered as automotive-qualified per AEC-Q100, Grade 1
standard. Conventional logic packages such as SO and TSSOP are used in a majority
of designs and it can be expected that these will be supported in the future.
In today’s world, wherein ultra-compact designs can be a challenge when it comes

to squeezing more functionality into a smaller space, leadless DHVQFN and XQFN
packages offer smaller footprint with improved mechanical performance. Such
leadless packages use pads instead of leads. These pads present a larger solderable
area, creating a stronger solder interconnect with PCB. This results in a design that
is more compact, and potentially more durable. Leadless packages perform better
in mechanical tests like shear, pull, bend and board level thermal cycling.
For functions with more than 10 pins, DHVQFN is recommended when transitioning
to leadless packages. These use the same die as TSSOP with up to 76% footprint
reduction.
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7
Table 1: Logic functions using Standard Logic package
Packages
DHVQFN-14
DHVQFN-16
DHVQFN-20
DHVQFN-24
TVSOP-48
TSSOP-14
TSSOP-16
TSSOP-20
TSSOP-24
TSSOP-48
TSSOP-56
XQFN-12
XQFN-16
SO-14
SO-16
SO-20
SO-24
Category
Segment
SOT1174
SOT1161
SOT762
SOT763
SOT764
SOT815
SOT108
SOT109
SOT163
SOT137
SOT402
SOT403
SOT360
SOT355
SOT362
SOT480
SOT364
Buffers/inverters/
• • • • • • • • • • • • •
Asynchronous interface
drivers
Level shifter/
translator • • • • •
• • • • • • • • • •
Printer interface •
Schmitt-triggers • • • • •
Transceivers • • • • • •
Digital comparators • • • •
Control logic
Gates • • • •
Parity generators/
checkers •
Analog switches • • • • • • • • • •
Bus switches • • • • • • • • • • • • • •
I/o expansion
Decoders/
demultiplexers • • • • • •
Digital multiplexer • • •
Shift registers • • • • • • • •
Counters/
frequency dividers • • • • • • •
Synchronous interface
FIFO registers • •
Flip-flops • • • • • • • • • • • • •
Latches/
registered drivers • • • • • • • • •
Multivibrators • • • •
Phase locked loops • •
125
SO
Packages
Logic functions in small outline surface mount packages

The SO or SOIC logic portfolio Key features & benefits
comprises all functions in 8-, 14-, 16-,
• Surface mount
20-, 24-pin packages. They are surface
• 1.27 mm pitch
mount packages with gull-wing pins. Pin
• Pb-free, RoHS and dark green
pitch is typically 1.27 mm. SO packages
compliant
provide 30 to 50% space saving
• Temperature range −40°C to 125°C
compared to DIP solutions. Profile
• AEC-Q100, Grade 1 qualified
height is 70% less than DIP solutions.
• Zero Delamination option available
TSSOP
Logic functions in thin-shrink small outline surface mount packages
The TSSOP logic portfolio comprises Key features & benefits

functions in 8-, 14-, 16-, 20-, and 24-pin
• Small footprint
packages as well as 16-bit functions in
• Surface mount
48- 56-pin packages. They are surface
• 0.65 mm pitch
mount packages with gull-wing pins. Pin
pitch is typically 0.65 mm. TSSOP
compliant
packages provide 35 to 65% space
saving compared to SO solutions.
Profile height is 35% less than SO
solutions.
DHVQFN
Depopulated very-thin Quad Flat-pack No-leads
The DHVQFN, sometimes abbreviated The package is an ideal choice for space
as DQFN, packages house the same constrained applications where PCB
silicon die as larger SO, SSOP and TSSOP space and low cost assembly is critical.
packages. This ensures that along with With their larger pads the DHVQFN
the smaller footprint identical electrical packages offer easier component
performance is assured. Signal integrity placement as well as improved
may be improved due to lower package strength, reliability, and thermal
parasitic inductance. Its tiny size saves characteristics.
valuable board real estate, while the
DHVQFN have a center pad which can
0.5 mm pad pitch allows it to be used in
be either connected to ground or to
existing 0.5 mm pitch assembly
VCC or left floating, dependent on the
processes.
recommendation in the data sheet. It is
most important to pay attention that
126
7
this pad is not accidently connected to Key features & benefits
Packages
the wrong polarity, as larger pads often
• Very small footprint
suggest they are ground pads. Leaving
• Ease of assembly 0.5 mm lead pitch
the center pad floating is generally
• Leadless, no bent leads
recommended.
• No co-planarity issues
To support automated optical • Pb-free, RoHS and dark green
inspection, side wettable flanks compliant
implemented on devices for automotive • Temperature range −40°C to 125°C
applications. • AEC-Q100, Grade 1 qualified
• Zero Delamination
• Superior Board Level Reliability
performance
• Side-wettable Flanks version optional
XQFN
Extremely thin quad flat package
XQFN logic portfolio comprises of Key features & benefits

functions in 12 and 16 pin packages. Its
tiny size saves valuable board real
• Ease of assembly 0.4 mm lead pitch
estate, while the 0.4 mm pad pitch
• Leadless, no bent leads
allows it to be used in existing 0.4 mm
assembly processes. Furthermore XQFN
packages are extremely thin for height
compliant
restricted applications.
• Extremely thin (height < 0.5 mm)
• Zero Delamination option in
development (Q3/20)
127
Table 2: Standard Logic packages

Packages
D PW BQ
Package
suffix
SO14 TSSOP14 DQFN14
Package SOT108-1 SOT402-1 SOT762-1
Width (mm) 6.00 6.40 2.50
Length (mm) 8.65 5.00 3.00
Height (mm) 1.75 1.10 1.00
Pitch (mm) 1.27 0.65 0.50
PW BQ D
Package
suffix
TSSOP20 DQFN20 SO24
Width (mm) 6.40 2.50 10.30
Length (mm) 6.50 4.50 15.40
Height (mm) 1.10 1.00 2.65
Pitch (mm) 0.65 0.50 1.27
Note: The HEF4000B family uses different package suffixes than the other families.
Package suffix D corresponds to HEF4000B package suffix T and PW to TT.
128
7
Packages
D PW BQ D
SO16 TSSOP16 DQFN16 SO20
SOT109-1 SOT403-1 SOT763-1 SOT163-1
6.00 6.40 2.50 10.30
9.90 5.00 3.50 12.80
1.75 1.10 1.00 2.65
1.27 0.65 0.50 1.27
PW BQ DGG DGV
TSSOP24 DQFN24 TSSOP48 TVSOP48
SOT355-1 SOT815-1 SOT362-1 SOT480-1
6.40 3.50 8.10 6.40
7.80 5.50 12.50 9.70
1.10 1.00 1.20 1.10
0.65 0.50 0.50 0.40
129
7.2 Mini Logic Packages

Packages
The Mini Logic packages house the same logic families as the larger SO,
TSSOP & DHVQFN packages. These packages allow the use of single gates rather
than using one gate of a quad. Mini Logic packages have 10 pins or fewer. As well as
reducing the complexity of board layout, Mini Logic devices are ideal glue logic to
implement last minute feature additions and improve time-to-market. Their small
size and lower-power consumption make them ideal for portable electronic
devices.
Mini Logic is a portfolio composed of Key features & benefits

MicroPak and PicoGate packages.
Leaded Mini Logic packages are known
• Simplify board layout
as PicoGates. They are available in TSOP,
• Leaded and leadless options
TSSOP and VSSOP with 0.95 mm,
• 0.95 mm, 0.65 mm, 0.50 mm, 0.40 mm,
0.65 mm and 0.5 mm pin pitch
0.35 mm & 0.30 mm pitch options
respectively. Leadless Mini Logic
packages are known as MicroPak. They
compliant
are available in XSON, X2SON and
XQFN. They have 0.5 mm, 0.4 mm,
• Many products AEC-Q100,
0.35 mm and 0.30 mm pad pitch.
Grade 1 qualified
• Suitable for automotive
7.2.1 MicroPak (Extremely thin small outline no-leads)
Mini Logic leadless MicroPak packages
MicroPak XSON packages advance state of the art packaging. Originally designed
for use in portable applications whose board space is limited, XSON packages allow
for smaller, more compact and slimmer overall designs. MicroPak packages are an
ideal choice for space constrained applications where PCB space and low cost
automated assembly are critical.
XSON leadless Mini Logic packages provide up to 60% space saving over traditional
leaded Mini Logic packages that are also known as PicoGate.
130
Table 3: Functions using Mini Logic package
TSOP-5
TSOP-6
TSSOP-5
TSSOP-6
TSSOP-8
TSSOP-10
TSSOP-8
VSSOP-8
XSON-6
XSON-8
XSON-6
XSON-8
XSON-6
XSON-8
XQFN-10
X2SON-4
X2SON-5
X2SON-6
X2SON-8
SOT753
SOT457
SOT353
SOT363
SOT505
SOT552
SOT530
SOT765
SOT886
SOT833
SOT1202
SOT1203
SOT1115
SOT1116
SOT1160
SOT1269
SOT1226
SOT1255
SOT1233
Segment Category
Buffers / inverters / drivers • • • • • • • • • • • • • • • •
Asynchronous
Level shifter / translator
interface • • • • • • • • • • • • • • • •
Schmitt-triggers • • • • • • • • • • • • • • • •
Control logic Gates • • • • • • • • • • • • • • • • •
Analog switches • • • • • • • • • • • • • • •
Bus switches • • •
I/O expansion
Decoders / demultiplexers • • • • •
Digital multiplexer • • • • • • • • • •
Counters / frequency dividers •
Flip-flops
Synchronous • • • • • • • • • • • • • •
interface
Latches / registered drivers • • • •
Multivibrators • • • • •
7
Packages
131
Packages
TSSOP6 XSON6
(SOT363) (SOT1202)
60%
Size reduction
1 mm
2.1 mm
1 mm
2.1 mm
Figure 7.1 | TSSOP6 and XSON6 comparison
MicroPak packages are leadless Mini Logic packages which house the same silicon
die as larger leaded PicoGate packages (refer to PicoGate section). Along with the
smaller footprint, this ensures identical electrical performance. Signal integrity may
also improve due to lower package parasitic inductance.
MicroPak leadless Mini Logic packages are an ideal choice for space-constrained
applications where PCB space, height and low cost assembly is critical. With their
larger pads, MicroPak packages offer easier component placement as well as
improved strength, reliability, and thermal characteristics over similar sized BGA
solutions.
MicroPak range is very broad and includes gates, analog switches, buffers/
inverters/drivers, bus switches, translators, flip-flops, decoders/demultiplexers,
multiplexers, latches, level-shifters, and Schmitt-trigger devices.
MicroPak solutions’ tiny size saves Key features & benefits

valuable board real estate thanks to
0.5 mm, as well as state of the art
• 0.5 mm, 0.35 mm and 0.30 mm pitch
0.35 mm and 0.30 mm pad pitch while
options
providing a more reliable bond between
• Low profile height (0.5 mm or
device and PCB. X2SON solutions are
0.35 mm)
available with ≥0.4 mm pad pitch, for
• Leadless
convenient mass production without a
step-down mask.
MicroPak packages include 4-pin compliant
X2SON, 5-pin X2SON, 6-pin XSON and • Temperature range −40°C to 125°C
X2SON, 8-pin XSON and X2SON, as well • AEC-Q100, Grade 1 options available
as 10-pin XQFN variant. • Zero delamination versions available
132
7
Table 4: Overview of current MiroPak packages
Packages
GX4 GX GX GN
Package
suffix
X2SON4 X2SON5 X2SON6 XSON6
Package SOT1269-2 SOT1226 SOT1255 SOT1115
Width (mm) 0.60 0.80 0.80 1.00
Length (mm) 0.60 0.80 1.00 0.90
Height (mm) 0.32 0.35 0.35 0.35
Pitch (mm) ≥0.4 ≥0.4 ≥0.4 0.30
GS GM GX GN
Package
suffix
XSON6 XSON6 X2SON8 XSON8
Package SOT1202 SOT886 SOT1233 SOT1116
Width (mm) 1.00 1.00 0.80 1.00
Length (mm) 1.00 1.45 1.35 1.20
Height (mm) 0.35 0.50 0.35 0.35
Pitch (mm) 0.35 0.50 ≥0.4 0.30
GS GT GU
Package
suffix
XSON8 XSON8 XQFN10
Package SOT1203 SOT833-1 SOT1160-1

Width (mm) 1.00 1.00 1.80
Length (mm) 1.35 1.95 1.40
Height (mm) 0.35 0.50 0.50
Pitch (mm) 0.35 0.50 0.40
133
MicroPak X2SON packages

Packages
The smallest logic leadless packages

First X2SON (GX) 5 pin package was introduced in 2012 to provide the smallest
footprint for logic functions while ensuring pad pitch remains 0.4 mm or over,
making step-down masks unnecessary. X2SON (GX) packages feature 4, 5, 6 or
8 pins and are available in low-power AUP, AXP, LV & LVC technology families,
covering over one hundred logic functions. In 2018, X2SON4 was introduced; this
4-pin package option further reduces footprint by 44% compared to the 5-pin
X2SON5.
X2SON5 X2SON4
(SOT1226) (SOT1269)
44%
0.8 mm Size reduction 0.6 mm
0.6 mm
0.8 mm
Figure 7.2 | Comparison of X2SON5 and X2SON4 package
X2SON packages are MicroPak packages Key features & benefits

also known under package suffix GX for
• Very small footprint (up to −36% vs.
X2SON8, X2SON6 and X2SON5 or GX4
GF & −25% vs. GN packages)
for X2SON4. X2SON packages’ tininess
• High contact area-to-chip ratio and
saves valuable board real estate and
enhanced durability
supports the miniaturization trend (see
• RoHS & dark-green compliant with
also next section regarding solder
NiPdAu Leadframe finish
stencil thicknesses). Single, dual and
• Low profile height (0.35 mm) and low
triple gates are available as well as
width (0.8 mm)
translators.
• Lower PCB costs, easier placement
and miniaturization
• Zero Delamination
134
7
Table 5: Micropak X2SON (GX) package details
Packages
Package L W H P
Package version Suffix
name (mm) (mm) (mm) (mm)
X2SON4 SOT1269 0.6 0.6 0.32 ≥ 0.4 GX4
X2SON5 SOT1226 0.8 0.8 0.35 ≥ 0.4 GX
X2SON6 SOT1255-2 1.0 0.8 0.35 ≥ 0.4 GX
X2SON8 SOT1233-2 1.35 0.8 0.35 ≥ 0.4 GX
Trade-off: Lead pitch vs DFM incl Mask/Stencil Design

The X2SONx packages are certainly very compact, with a height of only 0.35 mm.
But the most important feature is the novel placement of the contacts — by
utilizing the space at the corners of the package, and for some versions, including
one or even 2 terminals in the center of the part, Nexperia developed packages
that provides an extremely small form factor while maintaining a pitch greater than
0.4 mm for ALL of these X2SONx versions.
To understand the full significance of this innovative design, we need to consider

some details related to PCB assembly procedures.
Design for Manufacturability (DFM) is a critical factor in the success of high-volume

products. At the same time, consumers expect ongoing miniaturization, especially
with portable and wearable devices such as mobile phones, smart tablets, and
biometric sensors. A conflict arises when package miniaturization requires a pin- or
land pitch that is smaller than 0.4 mm, because this is the approximate threshold at
which standard manufacturing practices can become expensive and unreliable.
135
When a component’s pitch is less than 0.4 mm, the board-assembly process may
Packages
need to be modified to ensure that reflow soldering does not result in shorts
between pins. First, fine-pitch components are more likely to require costly Type 4
solder paste, rather than the standard Type 3. Type 4 paste, which has higher
viscosity and smaller particle size, is more effective with small stencil apertures.
Solder paste
Step down Mask/stencil
Lands/traces
PCB
Figure 7.3 | Step down Mask technology
Step-down portions
Figure 7.4 | Step down Masks on a PCB
136
7
Second, the thickness of the solder stencil must be reduced. Reducing the stencil
Packages
thickness leads to a corresponding reduction in the amount of solder deposited on
the pad, and this smaller quantity of solder is less likely to form a bridge between
adjacent pads. In order to ensure adequate mechanical strength and accommodate
smaller or tighter pitch components, the assembly process for these components
with very fine-pitch will employ a so-called “step-down” stencil or mask.
Such stencils are, of course, more complex to manufacture and therefore more
expensive; they are also more fragile and may need to be replaced more
frequently. In addition to the increased cost, the need for a step-down stencil
imposes irksome restrictions on component placement — the smaller-pitch
components must be located in PCB areas that correspond to the thinner sections
of the stencil.
Saving space, reducing cost

We can see from the previous discussion that X2SONx devices represent a
milestone in IC packaging technology: same functionality, less board space,
improved manufacturability. We achieved a significant reduction of footprint
compared to GN or GF packages, while the pitch has increased to > 0.4 mm, enough
to eliminate the DFM issues.
7.2.2 PicoGate (Single, dual or triple gate functions in small packages)
Single, dual or triple gate functions in small footprint packages

PicoGate portfolio comprises single-, dual-, and triple-gate functions in small 5-, 6-,
8- or 10-pin leaded packages. Compared to traditional quad-gate solutions,
PicoGate allows you to select just the number of functions you need. These leaded
Mini Logic packages easily allow the creation of intricate line layout patterns while
saving up to 85% board space.
PicoGates are available in technology families AXP, AUP, AVC, LVC, AHC(T), HC(T),
LV1T and CBTLV(D). PicoGate packages house the same logic functions as the larger
SO, TSSOP & DHVQFN packages, but in single gates rather than using one gate of a
quad. With the extensive portfolio of solutions, board space and lower-power
consumption can be achieved.
These products are all Pb-free, RoHS and dark green compliant, and designed for
use at ambient temperatures between −40°C and 125°C. Automotive variants that
meet the AEC-Q100, grade 1 standard are available for a range or PicoGate
solutions. PicoGate packages have a pitch of 0.95 mm, 0.65 mm, or 0.5 mm.
137
Nexperia’s PicoGate portfolio is the Key features & benefits

Packages
industry’s broadest and includes gates,

• Small footprint
level- shifters/translators, analog
• Simplify board layout
switches, buffers/inverters/drivers, bus
• 0.95 mm, 0.65 mm & 0.50 mm pitch
switches, decoders/demultiplexers,
options
flip-flops, multiplexers, latches and
Schmitt-Trigger devices. PicoGate
compliant
solutions are available in eight
technology families.
Our PicoGate package range includes
TSOP, TSSOP and VSSOP leaded
packages (5 to 10 pins).
138
Table 6: Picogate portfolio Parametrics and features
Family HC(T) AHC(T) AUP AVC AXP CBT(D) CBTLV LV1T
Supply voltage (V) 2 to 6.0 2 to 5.5 0.8 to 3.6 1.2 to 3.6 0.7 to 2.75 4.5 to 5.5 2.3 to 3.6 1.6 to 5.5
Propagation delay, typ (ns) 9 5 3.4 3.5 2.9 0.15 0.15 4.6
Output drive (mA) ±8 ±8 ±1.9 ±8 ±4.5 N/A N/A ±8

Standby current (µA) 80 40 0.9 12 0.6 3 10 10
Temperature range (ºC) −40 to +125 −40 to +125 −40 to +125 −40 to +125 −40 to +85 −40 to +85 −40 to +125 −40 to +125
Automotive option • • • • • • •
Features
Over-voltage tolerant input • • • • • • •

Schmitt-trigger inputs • • • • •
Low-threshold inputs • • • • •
Input clamp diodes • •
TTL inputs • • •
Bus hold
Power-off leakage (Ioff) • • •

Source termination
Open-drain outputs • • • • •
Low-delay isolation • •
7
Packages
139
Table 7: PicoGate package range includes TSOP, TSSOP and

Packages
VSSOP leaded packages (5 to 10 pins)
GW GV GW GV
Package
suffix
TSSOP5 TSOP5 TSSOP6 TSOP6
Package SOT353-1 SOT753 SOT363 SOT457
Width (mm) 1.25 1.5 1.25 1.5
Length (mm) 2.1 2.9 2.1 2.9
Height (mm) 0.95 1 0.95 1
Pitch (mm) 0.65 0.95 0.65 0.95
DP DC DP
Package
suffix
TSSOP8 VSSOP8 TSSOP10
Width (mm) 3 2.3 3.3
Length (mm) 3 2 3.3
Height (mm) 1.1 1 1.1
Pitch (mm) 0.65 0.50 0.50
140
7
7.2.3 Leads (PicoGate) or no leads (MicroPak)?
Packages
The X2SONx, like various other Nexperia logic packages, is leadless — that is, it
connects to the PCB through metal pads or “lands” instead of protruding leads.
There are a number of benefits associated with leadless packages. These are not
specific to X2SONn devices, but it’s important to recognize that these package
offers not only the DFM improvements discussed already but also the following
advantages over leaded devices:
• Leadless packages are actually more mechanically robust than

comparable leaded packages; the pads present a larger contact area and
thus allow for a stronger bond. Nexperia has abundant empirical data that
confirms the reliability of leadless packages such as the X2SONn.
• The connection pads for X2SON and other leadless devices are flat metal
surfaces on the bottom of the package; this eliminates assembly
difficulties that can occur when the pins of a leaded package are either
bent or do not exhibit sufficient coplanarity.
• Reflow soldering automatically corrects for small errors in component

placement or orientation because the surface tension of molten solder
naturally favors good alignment between a component and its
corresponding PCB pads. However, this effect is more pronounced with
leadless packages because they are smaller and lighter than comparable
leaded packages.
• Even electrical performance can improve when moving from leaded to

leadless devices: leadless packages offer lower parasitic inductance and
thus enhanced signal integrity for high-speed applications.
Contact area vs. chip area: the key to mechanical strength

As mentioned in the previous section, leadless packages offer superior durability
compared to leaded packages. The primary reason for this is quite simple: solder
provides the mechanical connection between a device and the PCB, and packages
that have a higher ratio of contact area to package area will have more solder
relative to the size of the package/IC.
Leadless packages have far higher contact-area-to-chip-area ratio than the leaded
parts. Furthermore, testing conducted by Nexperia has confirmed that leadless
components can surpass leaded components in their ability to withstand both pull
force and shear force.
141
Packages
Pull
Package
Shear
PCB
Figure 7.5 | Pull and Shear forces on a package
X2SONn devices are leadless and thus share in this enhanced durability. However,
the unique geometry of the GX package with center pad(s) create an even higher
contact-area-to-package-area ratio. This means that the X2SONn family of packages
may be not only the world’s smallest but also the world’s strongest logic package.
Conclusion X2SON (GX, GX4)

Space-constrained applications have benefited immensely from the high levels of
integration offered by microcontrollers, FPGAs, and sophisticated ASICs.
Nonetheless, discrete logic is and will continue to be an important factor in
enabling designers to produce low-cost, high-performance devices that satisfy the
market’s expectations for increasing portability and continuous innovation.
Nexperia is committed to supplying the logic devices that engineers need, and the
X2SONn packages — truly a breakthrough in IC packaging technology — are a prime
manifestation of this commitment.
142
7
7.3 Package soldering aspects
Packages
Introduction
PicoGate and MicroPak packages are approximately ten to fifteen times smaller
than conventional SO14 packages, providing significant miniaturization in space-
constrained applications. They are available in a wide range of logic functions with a
wide range of choices and deliver the right levels of performance.
PicoGate and MicroPak devices include single-, dual-, and triple-gate functions and
are housed in 4-, 5-, 6-, 8- and 10-pin packages with selectable functions. To support
the widest range of applications, every product in the portfolio is specified for high-
temperature operation (- 40°C to +125°C). Since they perform the most popular
functions and either meet or exceed competitive specifications, they eliminate
single-source problems.
Picogate vs MicroPak and soldering restrictions

Picogate, or leaded SMD devices, can be soldered on PCB by 2 different solder
processes called reflow process or wave soldering. The wave soldering can only be
applied to leaded packages without exposed pads and lead pitches ≥0.65 mm.
Leadless packages (MicroPak and also Standard Logic DHVQFN) can only be
reflowed, rather than attached on board with a wave soldering process, as the
pitch of the leads is smaller or equal to 0.5 mm. On top of this, any package with
exposed pads, require stencil printing (reflow process).
The following note describes the mounting methods for MicroPak packages, hence
using the reflow process.
MicroPak overview
Driven by applications with a very small circuit board mounting area, the MicroPak
Logic family offers the most popular logic functions for space-constrained systems
such as cellular phones and other portable consumer products. They can also be
used as simple glue/repair logic to implement last minute design changes or to
eliminate dependence on intricate line layout patterns and to simplify routing.
The MicroPak package is a plastic encapsulated package with a copper lead frame
base. The package has no leads or bumps but peripheral land terminals at the
bottom of the package. The terminals are soldered to solder lands on the Printed-
Circuit Board (PCB), after solder paste is deposited.
143
MicroPak soldering information

Packages
Solder paste
Currently most of the solder pastes to be used for Nexperia’s components is
lead-free (Pb-free) or called SAC. Recommended is a ‘no-clean’-type as due to the
small stand-off height of the MicroPak, proper cleaning underneath the package is
not possible.
Although low Pb-based solders (Pb ~36–38%, like Sn63Pb37) are still in use, it is
advised to use Pb-free solder paste, as this is required by i.e. European legislation
since July 2006.
A wide variety of Pb-free solder pastes is available, containing combinations of tin,

copper, antimony, silver, bismuth, indium, and other elements. The different types
of Pb-free solder pastes have a wide range of melting temperatures. Solders with a
high melting point may be more suitable for the automotive industry, whereas
solders with a low melting point can be used for soldering consumer IC packages.
The most common substitute for SnPb solder, is Pb-free paste SAC, which is a
combination of tin (Sn), silver (Ag), and copper (Cu). These three elements are
usually in the range of 1% to 4% of Ag and 0% to 1% of Cu, which is near eutectic.
Well-known types are SAC105, 305 and 405, with 1,3 and 4% of Ag and 0.5% Cu
resp. SAC typically has a melting temperature of around 217°C, and requires a
reflow temperature of more than 235°C.
Below, the most wide-spread Pb-free solder pastes are shown:
Typical Pb-free solder
Solder type Composition
SAC 105 paste 98.5% Sn, 1% Ag, 0.5% Cu
SAC 305 paste 96.5% Sn, 3% Ag, 0.5% Cu
SAC 405 paste 95.5% Sn, 4% Ag, 0.5% Cu
A no-clean solder paste does not require cleaning after reflow soldering. If a
no-clean paste is used, flux residues may be visible on the board after reflow. For
more information on the solder paste, please contact your solder paste supplier.
144
7
Moisture sensitivity level and storage
Packages
The MicroPak components have a very good package moisture resistance. The
Moisture Sensitivity Level (MSL) according to JEDEC J-STD-020D is MSL1, i.e.
unlimited floor life under the condition of < 30°C/85%RH or in other words it is
classified as not being moisture sensitive and thus does not require dry pack.
Stencil
The table below gives a first guideline regarding recommended electroformed
stencil thickness for MicroPak packages with a terminal pitch of greater than or
equal to 0.5 mm, between 0.4 mm to 0.5 mm and less than or equal to 0.4 mm. Side
wall roughness of the apertures should be smooth to improve the solder paste
release.
Typical stencil thicknesses
Package terminal pitch Stencil thicknesses
≥ 0.5 mm 150 μm
0.4 mm to 0.5 mm 100 μm or 125 μm
≤ 0.4 mm 80 μm or 100 μm
MicroPak placement
The required placement accuracy of a package depends on a variety of factors, such
as package size and the terminal pitch, but also the package type itself. During
reflow, when the solder is molten, a package that has not been placed perfectly
may center itself on the pads: this is referred to as self-alignment. The table below
gives typical placement tolerances as a function of the package terminal pitch.
Typical placement accuracies
Package terminal pitch Placement tolerance
≥ 0.65 mm 50 μm
< 0.65 mm 100 μm
145
Reflow soldering
Packages
The most important step in reflow soldering is the reflow itself, when the solder
paste deposits melt and solder joints are formed. This is achieved by passing the
boards through an oven and exposing them to a temperature profile that varies in
time. A temperature profile essentially consists of three phases:
1. Preheat: the board is warmed up to a temperature that is lower than the melting
point of the solder alloy. Subsequently to the preheat phase and still prior to the
next phase of reflow, the soaking stage takes place with the purpose of
evaporation of solvents and activation of the flux.
2. Reflow: the board is heated to a peak temperature that is well above the melting
point of the solder, but below the temperature at which the components and
board’s Organic Solderability Preservative (OSP) finish are damaged
3. Cooling down: the board is cooled down rapidly, so that soldered joints freeze
before the board exits the oven
The peak temperature during reflow has an upper and a lower limit:
• Lower limit of peak temperature; the minimum peak temperature must

be at least high enough for the solder to make reliable solder joints; this is
determined by solder paste characteristics; contact your paste supplier
for details
• The upper limit of the peak temperature must be lower than:

· the maximum temperature the component can withstand according to the
specification
· the temperature at which the board or the components on the board are
damaged (contact your board supplier for details)
The below temperature profile for moisture sensitivity characterization is based on

the IPC/JEDEC joint industry standard: J-STD-020D. The shown data is for devices
with a package thickness < 2.5 mm and a package volume < 350 mm³. The
temperature profile curves for a reflow process are shown in Figure 7.6. The inner
curve is for fast soldering, the outer curve for slow soldering.
146
7
Table 8: temperature profile for moisture sensitivity characterization
Packages
SnPn eutectic Pb-free
Profile feature
assembly assembly
Average ramp-up rate (Tsmax to Tp) 3°C/s maximum 3°C/s maximum
Preheat Temperature
100 °C 150 °C
minimum (Tsmin)
Temperature
150 °C 200 °C
maximum (Tsmax)
Time
60 s to 120 s 60 s to 120 s
(tsmin to tsmax)
Time maintained Temprature (TL) 183 °C 217 °C

above
Time (tL) 60 s to 150 s 60 s to 150 s
Peak/classification temperature (Tp) 235 °C 260 °C
Number of allowed reflow cycles 3 3
Time with 5°C of actual peak

10 s to 30 s 20 s to 40 s
temperature (tp)
Ramp-down rate 6 °C/s maximum 6 °C/s maximum
Time 25°C to peak temprature 6 minutes maximum 8 minutes maximum
aaa-027797
temperature
tp
Tp critical zone
TL to Tp
ramp-up
TL
Tsmax tL
Tsmin
ramp-down
ts
preheat
25 °C
time
t25°C to peak
Figure 7.6 | Temperature profile of a reflow process for an XSON6 package
147
Every package has its own solder land information, also called reflow soldering
Packages
footprint. This is normally illustrated as part of the outline-drawing available on the

Nexperia Website. As an example the X2SON6 (SOT1255-2) is shown in Figure 7.7.
sot1255_fr
1.2
0.4 (4x) 0.2 0.18
0.76
0.6
0.4 0.3 0.22

(4x) (4x)
0.15
)
(6x 0.36
0.3 60°
1.1 0.18 0.3 0.72
0.22 (6x)
0.4
0.07 (4x)
0.47 0.13
occupied area solder resist
solder lands solder paste
Dimensions in mm
Figure 7.7 | Solder land information for an XSON6 package
148
7
7.4 Thermal resistance of packages
Packages
Logic components normally do not require or produce a lot of electrical or thermal
power, however it may still be good to understand the impact of thermal resistance
of the packages in the final application. Most of the times, the Printed Circuit Board
(PCB) acts as heat sink for our Surface Mounted Devices, while this exposed pad (or
heatsink) of the package (chip carrier to leadframe), if applicable, is directly
soldered to the PCB. The thermal resistance of these packages between the chip or
die and the heat sink of the package is called Rth(j-c) (thermal resistance junction-to-
case) and is measured in [K/W]. An explanation how this is measured is given in the
next section.
For ease of use we will first explain the static properties of the thermal path from
junction (chip or die) to PCB in its application. The internal structure of a package
(simplified) consist of a die on a leadframe which is connected to the outside world
via a solder layer on the PCB (see Figure 7.8).
Mold compound
Die adhesive
Die
Leadframe Solder
PCB and/or Heatsink
Figure 7.8 | Simplified structure of a package
This static equivalent circuit (without e.g. wirebonds) follows in analogy the
electrical scheme below:
The power dissipation from the die PD is symbolized by a current source, whereas
all thermal resistances (Rth) are symbolized by ohmic resistors. Seen from the
sketch above, the main thermal resistors are placed in sequence, with the mold
compound in parallel, covering the whole structure or package. This parallel path
can be neglected for most of the cases, especially having low power as valid for
Logic packages.
The ambient temperature Ta is represented in the scheme below as a voltage

source. With the thermal layout sketched in Figure 7.9, one can clearly distinguish
between the case and the ambient impact on the performance.
149
The majority of the heat generated in the junction is conveyed to the case by
Packages
conduction rather than convection. A measure of the effectiveness of heat

conduction is the above described thermal resistance junction-to-case, Rth(j-c), the
value which is governed by the package construction of the device. Any heat
transfer from the case to the surrounding air involves radiation, convection and
conduction. The effectiveness of this external transfer is defined by a Rth(application)
(thermal resistance case-to ambient or application dependent value). The total
thermal resistance between junction-to-ambient is consequently
𝑅𝑅!! !!! = 𝑅𝑅!! !!! + 𝑅𝑅!!(!""#$%!&$'()
!!"#$ – !! !!"#$ – !!
𝑃𝑃!"#$ =
!!! !!!
=
R th !!!(!!!) ! !!!(!""#$%!&$'()
Mold
compound
R th
! !! !!"#$
R th R th R th R th
𝑃𝑃!"#$ = Die +adhesive

Die Leadframe Solder PCB
!!!(!!!) !!!(!!!) (Heatsink)
Tj Tc
Rth (j-c) Rth (application) = Ta
PD
!!
!!!(!!!)
Rth (j-a)
!! ! !!"#
𝛹𝛹!!(!!!"#) =
!"#$%from Junction to Ambient
Figure 7.9 | Thermal Resistances
The total package thermal resistance junction-to-ambient is thus application

dependent, hence PCB and package connection to the board (the solder thereof) is
!! ! !!
𝑅𝑅!!(!!!)
of importance.=The latter impact (ambient conditions) is often not known to the
package provider.!"#$%
Whenever we, as Nexperia, calculate the Rth(j-a) (thermal
resistance junction-to-ambient) we have to make assumptions with a certain known
PCB configuration, in our case often a PCB (1) stated by JEDEC with a 4 layer
configuration and dimension of 100 × 100 mm, (2) heat transfer path top/
bottom = 15 (W/m²*K) and (3) No plated through vias.
150
7
𝑅𝑅The
!! total = 𝑅𝑅!!power,
!!!maximum !!! P+ 𝑅𝑅 of a semiconductor device can be expressed as
Dmax!!(!""#$%!&$'()
Packages
follows
!!"#$ – !! !!"#$ – !!
𝑃𝑃!"#$ =
!!! !!!
= !
!!(!!!) ! !!!(!""#$%!&$'()
𝑅𝑅!! !!! = 𝑅𝑅!! !!! + 𝑅𝑅!!(!""#$%!&$'()
𝑅𝑅
!! !!! = 𝑅𝑅!! !!! + 𝑅𝑅!!(!""#$%!&$'()
where
! !! !!"#$
𝑃𝑃T!"#$ = !!"#$junction
jmax is the maximum
–+!! temperature!and !"#$ Ta–is!the
! highest ambient
𝑃𝑃!"#$ =!likely
temperature
!!(!!!)
to!!!
!=!!(!!!)
be reached ! under the most unfavorable conditions. The
!!! !!(!!!) ! ! !!(!""#$%!&$'()
! (Ta) or– !!
function PDmax = f!"#$
!!"#$ – !!
𝑃𝑃!"#$ =
!!! !!!
= !
!!(!!!) ! !!!(!""#$%!&$'()
!!
!!!(!!!) ! !! !!"#$
𝑃𝑃!"#$ = +
!!!(!!!) !!!(!!!)
! !! !!"#$
𝑃𝑃!"#$ = +
!!!(!!!)
!! ! !!"# !!!(!!!)
𝛹𝛹 !!(!!!"#)
!! =
reveals a descending straight line of gradient:
!"#$%
!!!(!!!)
!!
!!!(!!!) !! ! !!
𝑅𝑅!!(!!!) = ! ! !
!"#$%
! !"#
𝛹𝛹!!(!!!"#) =
with its zero at Tjmax.!"#$%
!! ! !!"#
𝛹𝛹!!(!!!"#) =
!"#$%
!! ! !!
𝑅𝑅!!(!!!) =
!"#$%
!! ! !!
𝑅𝑅!!(!!!) =
!"#$%
1
151
Derating factor
Packages
It should be noted that in the data sheets of the products from Nexperia the total
power dissipation is given as a function of the package (case) temperature TC,
because the application-specific thermal resistances are not known to us. This
function, like the previous one, is a descending straight line. The slope now has the
value 1/R(th(j-c). The zero remains at Tjmax, i.e. 150°C. The slope of this straight line is
called derating factor and is measured in [mW/K]. The total power dissipation PDmax
or Ptot remains constant until a certain TC, at which the power derates linearly down
to the Tjmax @ 150°C. In the example below a Package is determined by a derating
of 7.8 mW/K starting at a case temperature TC of 118°C.
The limiting case temperature TC is defined by the die-junction temperature Tjmax

subtracted by the multiplication of the thermal resistance Rth(j-c) and the total
power dissipation PDmax, whereas the derating factor is defined by the total power
divided by the temperature difference between the die-junction temperature Tjmax
and the “limiting” case temperature TC defined above.
Permissible Power Disspiation Ptot as f(Tcase)

300
Ptot (mW)
250
“Derating Factor”
200
[7.8 mW/K]
150
100
50
0
0 20 40 60 80 100 120 140 160
Tcase (°C)
Figure 7.10 | Example of a package with a derating factor of 7.8 mW/K starting at 118°C
152
7
7.5 Thermal characterization of packages –
Packages
Explanation and possible setup
All our Logic packages exhibit or consume only low thermal power, but in case of
necessity for certain applications we would like to explain a bit more on thermal
measurements incl some background on it. Generally speaking, only a fraction of
the thermal power is exhibiting at the top side, but for completeness reasons we
𝑅𝑅!! !!!
explain
= 𝑅𝑅!! !!!
how to measure
+ 𝑅𝑅!!(!""#$%!&$'()
this and where it is used for:
Junction-to-Package Ψth(j-top)
!!"#$ –a!correlation
This parameter provides ! !!"#$
between chip –temperature
!! and temperature
𝑃𝑃!"#$ =
of package at the!top
= !!!(!!!) ! !!!(!""#$%!&$'()
!! side.
!!! It is used to estimate chip temperature in certain
applications and is not to be confounded with the thermal resistance Rth(j-c)!
Set-up:
The package must!be ! mounted!on a standard board (e.g. FR4 PCB with JEDEC
!"#$
defined = with!a thermocouple
𝑃𝑃!"#$4 layers) +
!!!(!!!) !!!(!!!)on top of its package. When driving this
package in a standard test environment (e.g. a wind tunnel) one has to apply a
KNOWN amount of power to the die while the temperature of the chip (Tj or
Tjunction) and the temperature of the top of the package (Ttop) (via the
!!
thermocouple) will be measured.
!!!(!!!)
Calculations:
!! ! !!"#
𝛹𝛹!!(!!!"#) =
!"#$%
Again: It has to be mentioned that this Ψth(j-top) is not a thermal resistance and it is
!! ! !!
𝑅𝑅!!(!!!)
only =
used to estimate the junction temperature from a measurement of top of
package in actual!"#$%
applications
153
Packages
Thermocouple
Mold compound
Die
Leadframe
PCB and/or Heatsink
Figure 7.11 | Measurement of case temperature
Thermal Resistance Junction-to-Case Rth(j-c)
This parameter is of much higher interest and importance as this is a better

reflectance of real applications in the field, including the use of external heat sinks.
It represents the thermal resistance between the chip-junction temperature and
the case temperature of the package in “real life”, including possible external heat
sinks on the package. Contribution factors, like the die, the die attach material
(adhesive or solder) and leadframe, have been discussed in the former section.
Set-up to measure:
The package has to be mounted on a standard board (e.g. FR4 PCB with JEDEC
defined 4 layers) or socket while the package must be in “perfect“ physical
(thermal) contact with a temperature stabilized plate (preferably water-cooled).
Any air flow around the package has to be minimized to ensure that the whole heat
flux from the package exhibits to the cold plate rather than redirected by
convection and evaporation. Also here a KNOWN amount of power has to be
applied to the die while the temperature of the chip (Tj or Tjunction) and the
temperature of the case of the package (Tc or Tcase) will be measured. The Tcase is
different with respect to the Ttop as it represents the temperature of the package
(case) at the position where the package is connected to the heatsink, assuming
that the majority of the heat flow is directed towards either top or bottom only
(depending on application and design), hence no significant portion of radiation or
side wall conduction exist. Therefore, the use of thermal grease or thermal pads
between the package and the PCB, and or external heat sink, is highly
recommended, but only in case of necessity.
154
!!!(!!!)

7
!! ! !!"#
𝛹𝛹!!(!!!"#) =
!"#$%
Calculations:
Packages
!! ! !!
𝑅𝑅!!(!!!) =
!"#$%
A low thermal resistance Rth(j-c) indicates that the heat flux from the die to the
heatsink is high, hence a high absorption of the heat (thermal power) can be
guaranteed. A possible setup for Rth(j-c) measurement is sketched below:
Watercooling
Inlet Outlet
Thermocouple
External
Heatsink
Thermal
grease
Mold compound
1 Die
Leadframe
PCB
Plunger
Force
Figure 7.12 | Measurement of case temperature underneath a heat sink
155
Packages
Heatsink
Mold compound
Die
Leadframe
PCB
Figure 7.13 | External Heatsink on a package
For high power applications, which is unlikely for Logic IC designs, an external
heatsink should be attached to the package to improve the thermal performance
of the application specific part of the resistance junction-to-ambient Rth(j-a). See
sketch below.
156
8
Chapter 8
Automotive Quality
Automotive Quality
157
The operating environment of automobile semiconductor components is much

Automotive Quality
more hostile than that of semiconductors used in the home or portable

applications. For instance, A television set will generally spend its operating lifetime
within an ambient temperature range of 0°C to 40°C. Due to internal heating, its
semiconductor devices can be expected to operate between 20°C and 60°C. By
comparison, an automobile is likely to start at temperatures lower than −20°C and,
in some cases, operate within the engine compartment at temperatures
approaching 150°C.
To ensure the reliability of automotive electronics, the Automotive Electronics

Council introduced its AEC-Q100 standard, which outlines procedures to be
followed to ensure integrated circuits meet the quality and reliability levels
required by automotive applications. Due to a long history in automotive Nexperia’s
automotive (-Q100) portfolio meets all requirements and exceed some.
Benefits of an automotive portfolio
AEC-Q100 product qualification and reliability monitoring

Operating at elevated temperatures reduces the lifetime of a semiconductor and
temperature cycling has a negative impact on the stability of a package. In cases
where there is no history of a product’s reliability within automotive applications, a
series of stresses to simulate the life cycle within an automotive environment must
be applied to guarantee conformance to the AEC-Q100 standard.
To ensure continued reliability, Nexperia logic maintains an extensive reliability

monitoring program that often exceeds the AEC requirement; the results of which
are published half-yearly. These QSUM reports are available upon request via your
Nexperia sales representative.
Manufa
ctu
rin
on g
i
at
ific
Qual
Custome
rs
Phase out
Figure 8.1 | Product life cycle
158
8
Tightened manufacturing process controls
Automotive Quality
Q100 devices are manufactured in TS16949 certified and VDA approved production
facilities; they are flagged as automotive lots to ensure they receive highest priority
and to facilitate traceability for improved quality analysis. Moreover, they are
subjected to additional process flow quality gates and stricter rules for lot dis-
positioning and maverick lot handling ensures any outlier lots, which are lots that
although they pass a quality gate are not within an acceptable distribution, are
assigned to standard, non-automotive, types.
Six Sigma design, zero-defect test and inspection methodology

Six sigma design philosophy is applied to all Q100 devices. This ensures that an
end-user application designed to the datasheet limits can tolerate a shift as high as
one and a half sigma in Nexperia’s manufacturing processes. As the process control
limits are much tighter than one and a half sigma, this virtually guarantees trouble-
free end-user applications. During the electrical test process, average test limits or
statistical test limits are applied to screen outliers within automotive lots.
Figure 8.2 shows the distribution of devices passing a test and the calculated
statistical test limits in yellow. Although the outliers are within the upper and lower
specification limits, they are not delivered as Q100 products.
aaa-032365
LSL USL
Outliers Outliers
Statistical test limits
Figure 8.2 | Application of statistical test limits
159
Dedicated website and datasheets

Automotive Quality
A summary of Nexperia logic’s Q100 portfolio including a search by function and a

parametric search within each function can be found at www.nexperia.com/
products/automotive/logic, and unlike the standard types, each Q100 device has a
dedicated datasheet confirming that it has been qualified in accordance with
AEC-Q100 and is suitable for automotive applications.
Priority technical support

Nexperia’s first and second tier technical support teams give Q100 product
design-in assistance their highest priority, and upon request, AEC-Q100 production
part approval process (PPAP) qualification data will be made available. Due to the
stricter qualification requirements of automotive end-user applications, a 180-day
process change notification (PCN) approval cycle is applied for Q100 products
instead of the 90 day PCN approval cycle for standard types. In the unlikely event of
a quality issue, Nexperia logic guarantees a 10 day through put time with initial
verification within 24 hours for its Q100 portfolio.
160
9
Chapter 9
Logic Families
Logic Families
161
Nexperia offers a wide range of Logic process families. The overview of all families
Logic Families
with properties and features is given in the following tables. In the following
chapters, the most important focus process families are described in more detail.
The structure for each chapter is:
Structure of the Logic process family chapters
• Construction: brief description of process properties like gate length,

input capacity and other properties that devices of this family have in
common
• Input Output structure: some information specific to the interface

structure such as voltages and features
• Input Output figures: Simulation figures for I/V curves are shown here.
Very useful for analysis of interface behaviour.
• Operating conditions: the specified properties from the data sheets are
listed in tables, such as limited and recommended conditions, static and
dynamic characteristics. Generally valid for devices of the respective
process family
• Power calculation: a formula is given here, as well as in the data sheets
• Special features: some families have special feature, i.e. Bus hold on
inputs. These are described here.
Overview of the Nexperia’s Logic process family portfolio:
162
Table 1: High voltage families
Family ABT AHC(T) CBT(D) HC(T) HEF LV-A(T) LVnT LVC NPIC
Supply voltage (V) 4.5 to 5.5 2 to 5.5 4.5 to 5.5 2 to 6.0 3 to 15 2 to 5.5 1.6 to 5.5 1.6 to 5.5 4.5 to 5.5
Propagation delay, typ (ns) 2 5 0,25 9 90 3,4 3,1 1,7 5
Output drive(mA) -0,5 ±8 N/A ±8 ±3 ±12 ±8 ±24 ±100
Standby current (µA) 500 40 3 80 600 20 10 10 200
−40 to −40 to −40 to −40 to −40 to −40 to −40 to −40 to −40 to

Temprature range (°C)
+85 +125 +85 +125 +85 +125 +125 +125 +125
Automotive option • • • • • • • •
Portfolio
Standard Logic • • • • • •
Mini Logic • • • • •
Features
Over-voltage tolerant inputs • • •* • • • •
Schmitt-trigger inputs • • • • •
Low-threshold inputs • • •
TTL inputs • • • • •
Input clamp diodes • • •
Power-off leakage (Ioff) • • •
Open-drain outputs • • • • •
Low-delay isolation •
* 4049 & 4050 functions only
9
Logic Families
163
9
Logic Families
164
Table 2: Low voltage families
Family ALVC ALVT AUP AVC AXP CB3Q CBTLV(D) AUP1T LVC LVT
Supply voltage (V) 1.2 to 3.6 2.3 to 3.6 0.8 to 3.6 1.2 to 3.6 0.7 to 2.75 2.3 to 3.6 2.3 to 3.6 2.3 to 3.6 1.2 to 3.6 2.7 to 3.6
Propagation delay, typ (ns) 2 1,5 3,4 1 2,9 0,2 0,15 4 4 2
Output drive(mA) ±24 -32/64 ±1.9 ±8 ±4.5 N/A N/A ±4 ±24 −32/64
Standby current (µA) 40 90 0,9 20 0,6 400 10 1,5 20 120
−40 to −40 to −40 to −40 to −40 to −40 to −40 to -40 to −40 to −40 to
Temprature range (°C)
+85 +85 +125 +85 +85 +85 +125 +125 +125 +85
Automotive option • • • • • • •
Portfolio
Standard Logic • • • • • • •
Mini Logic • • • • •
Features
Over-voltage tolerant inputs •* • • • • • • • • •
Schmitt-trigger inputs • • • • • •
Low-threshold inputs • • •
Input clamp diodes •
Bus hold • • • • •
Power-off leakage (Ioff) • • • • • • • •
Source termination • • • •
Open-drain outputs • • •
Low-delay isolation • •
* Non bus hold versions only
9
9.1 The HC/HCT/HCU Logic Family
Logic Families
Introduction to family / General description
The 74HC/HCT/HCU high-speed Si-gate CMOS logic family combines the low power
advantages of the HEF4000B family with the high speed and drive capability of low
power Schottky CMOS. The family has the same pin-out as older 74 series and
provides the same circuit functions.
The basic family of buffered devices, designated as 74HC, operate at CMOS input
logic levels for high noise immunity, negligible typical quiescent supply and input
current. It is operated from a power supply of 2 to 6 V.
A subset of the family, designated as 74HCT with the same features and functions
as the “HC-types”, will operate at standard TTL power supply voltage (5 V ± 10%)
and logic input levels (0.8 to 2.0 V) for use as pin-to-pin compatible CMOS
replacements to reduce power consumption without loss of speed. These types are
also suitable for converted switching from TTL to CMOS.
Another subset, the 74HCU, consists of single-stage unbuffered CMOS compatible

devices for application in RC or crystal-controlled oscillators and other types of
feedback circuits which operate in the linear mode.
Construction
The HC/HCT/HCU family devices are built in a the 5 V CMOS technology with a gate
length of 1.2 micron. The process technology is Pb-Free, RoHS and Dark Green
compliant. Bond wiring is done with copper.
165
Input Output structures

Logic Families
aaa-032015
VC C VCC VCC
source source
R p - channel
p-channel p-
channel
gate drain gate drain

input output input output input output
n-
channel
n-channel
R n - channel
source source
GND GND
(a) (b) (c)
Figure 9.1 | Input structure of HC(T) family devices
The input structure of the HC/HCT/HCU logic family provides ESD protection and
low capacitive coupling
Latch-up protected inputs:
aaa-032366
Latch-up is the creation of a low-
impedance path between the power
+
supply rails caused by the triggering of VCC
-
parasitic bipolar structures (SCRs) by
input, output or supply over-voltages. Input stage
of the IC
These overvoltages induce currents that Input
can exceed maximum device ratings.
When the low-impedance path remains
after removal of the triggering voltage,
the device is said to have latch-up.
Overvoltage protected inputs:

Inputs include clamp diodes. This
Figure 9.2 | ESD protection circuit for HC(T)
enables the use of current limiting input stages
resistors to interface inputs to voltages
in excess of VCC. HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
ESD protection: the input structure
has rail-to-rail Diodes, as illustrated in
Figure 9.2.
It is recommended to drive all logic inputs with a defined value, not to leave them
floating
166
9
Input Output characteristics
Logic Families
Input characteristics
Idd (A) Idd (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
125°C min 125°C min
VIN (V) VIN (V)
HC input curves at 2V HC input curves at 3V3
Idd (A) Idd (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VIN (V) VIN (V)
HC input curves at 5V HC input curves at 6V
167
Output characteristics
Logic Families
IOL (A) IOL (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VOUT (V) VOUT (V)
HC output curves at 2V HC output curves at 3V3
IOL (A) IOL (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VOUT (V) VOUT (V)
HC output curves at 5V HC output curves at 6V
IOH (A) IOH (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VOUT (V) VOUT (V)
HC output curves at 2V HC output curves at 3.3V
168
9
Logic Families
IOH (A) IOH (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VOUT (V) VOUT (V)
HC output curves at 5V HC output curves at 6V
Operating Conditions
Table 3: Limiting values

Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0,5 +7 V

IIK input clamping current VI < −0.5 V or
– ±20 mA
VI > VCC + 0.5 V
IOK output clamping current VO < −0.5 V or
– ±20 mA
VO > VCC + 0.5 V
IO output current VO = −0.5 V to (VCC + 0.5 V) – ±25 mA
ICC supply current – +100 mA
IGND ground current −100 – mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation – 500 mW
169
Table 4: Recommended operating conditions

Logic Families
Conditions
Parameter
74HC74-Q100 74HCT74-Q100
Symbol
Min Typ Max Min Typ Max Unit
VCC supply voltage 2,0 5,0 6,0 4,5 5,0 5,5 V

VI input voltage 0 – VCC 0 – VCC V
VO output voltage 0 – VCC 0 – VCC V
Tamb ambient tempe-
−40 +25 +125 −40 +25 +125 °C
rature
∆t/∆V input transition VCC = 2.0 V – – 625 – – – ns/V
rise and fall rate
VCC = 4.5 V – 1,67 139 – 1,67 139 ns/V
VCC = 6.0 V – – 83 – – – ns/V
Table 5: Static characteristics
Tamb Tamb
Conditions
Parameter
−40 °C to −40 °C to
+85 °C +125 °C
Symbol
74HC74-Q100
VIH HIGH-level input VCC = 2.0 V 1,5 1,2 – 1,5 – V
voltage
VCC = 4.5 V 3,15 2,4 – 3,15 – V
VCC = 6.0 V 4,2 3,2 – 4,2 – V
VIL LOW-level input VCC = 2.0 V – 0,8 0,5 – 0,5 V
voltage
VCC = 4.5 V – 2,1 1,35 – 1,35 V
VCC = 6.0 V – 2,8 1,8 – 1,8 V
VOH HIGH-level output VI = VIH or VIL
voltage
IO = −4.0 mA;
3,84 4,32 – 3,7 – V
VCC = 4.5 V
IO = −5.2 mA;
5,34 5,81 – 5,2 – V
VCC = 6.0 V
170
9
Logic Families
Tamb Tamb
Conditions
Parameter
−40 °C to −40 °C to
+85 °C +125 °C
Symbol
VOL LOW-level output VI = VIH or VIL

voltage
IO = 4.0 mA;
– 0,15 0,33 – 0,4 V
VCC = 4.5 V
IO = 5.2 mA;
– 0,16 0,33 – 0,4 V
VCC = 6.0 V
II input leakage VI = VCC or GND;
– – ±1.0 – ±1.0 μA
current VCC = 6.0 V
ICC supply current VI = VCC or GND;
– – 40 – 80 μA
IO = 0 A; VCC = 6.0 V
CI input capacitance – 3,5 – – – pF
74HCT74-Q100
VIH HIGH-level input
VCC = 4.5 to 5.5 V 2,0 1,6 – 2,0 – V
voltage
VIL LOW-level input
VCC = 4.5 to 5.5 V – 1,2 0,8 – 0,8 V
voltage
VOH HIGH-level output VI = VIH or VIL; VCC = 4.5 V
voltage
IO = −4 mA 3,84 4,32 – 3,7 – V
VOL LOW-level output VI = VIH or VIL; VCC = 4.5 V
voltage
IO = 4.0 mA – 0,15 0,33 – 0,4 V
II input leakage VI = VCC or GND;
– – ±1.0 – ±1.0 μA
current VCC = 5.5 V
ICC supply current VI = VCC or GND;
– – 40 – 80 μA
IO = 0 A; VCC = 5.5 V
ΔICC additional supply VI = VCC − 2.1 V; other inputs at VCC or GND;
current VCC = 4.5 to 5.5 V; IO = 0 A
per input pin;
– 70 315 – 343 μA
nD, nRD inputs
per input pin;
– 80 360 – 392 μA
nSD, nCP input
CI input capacitance – 3,5 – – – pF
171
Table 6: Dynamic characteristics

Logic Families
Tamb Tamb
Conditions
Parameter
−40 °C to −40 °C to
+85 °C +125 °C
Symbol
74HCT74-Q100
tW pulse width nCP HIGH or LOW
VCC = 2.0 V 100 19 – 120 – ns
VCC = 4.5 V 20 7 – 24 – ns
VCC = 6.0 V 17 6 – 20 – ns
nSD, nRD LOW
VCC = 2.0 V 100 19 – 120 – ns
VCC = 4.5 V 20 7 – 24 – ns
VCC = 6.0 V 17 6 – 20 – ns
trec recovery time nSD, nRD
VCC = 2.0 V 40 3 – 45 – ns
VCC = 4.5 V 8 1 – 9 – ns
VCC = 6.0 V 7 1 – 8 – ns
tsu set-up time nD to nCP
VCC = 2.0 V 75 6 – 90 – ns
VCC = 4.5 V 15 2 – 18 – ns
VCC = 6.0 V 13 2 – 15 – ns
th hold time nD to nCP
VCC = 2.0 V 3 −6 – 3 – ns
VCC = 4.5 V 3 −2 – 3 – ns
VCC = 6.0 V 3 −2 – 3 – ns
fmax maximum nCP
frequency VCC = 2.0 V 4,8 23 – 4,0 – MHz
VCC = 4.5 V 24 69 – 20 – MHz
VCC = 5 V; CL = 15 pF – 76 – – – MHz
VCC = 6.0 V 28 82 – 24 – MHz
CPD power CL = 50 pF; f = 1 MHz;
dissipation VI = GND to VCC [3] – 24 – – – pF
capacitance
172
9
Logic Families
Tamb Tamb
Conditions
Parameter
−40 °C to −40 °C to
+85 °C +125 °C
Symbol
74HCT74-Q100
tpd propagation nCP to nQ, nQ [1]
delay VCC = 4.5 V – 18 44 – 53 ns
VCC = 5 V; CL = 15 pF – 15 – – – ns
nSD to nQ, nQ [1]
VCC = 4.5 V – 23 50 – 60 ns
VCC = 5 V; CL = 15 pF – 18 – – – ns
nRD to nQ, nQ [1]
VCC = 4.5 V – 24 50 – 60 ns
VCC = 5 V; CL = 15 pF – 18 – – – ns
tt transition time nQ, nQ [1]
VCC = 4.5 V – 7 19 – 22 ns
tW pulse width nCP HIGH or LOW
VCC = 4.5 V 23 9 – 27 – ns
nSD, nRD LOW
VCC = 4.5 V 20 9 – 24 – ns
trec recovery time nSD, nRD
VCC = 4.5 V 8 1 – 9 – ns
VCC = 4.5 V 15 5 – 18 – ns
VCC = 4.5 V 3 −3 – 3 – ns
fmax maximum nCP
frequency VCC = 4.5 V 22 54 – 18 – MHz
VCC = 5 V; CL = 15 pF – 59 – – – MHz
CPD power CL = 50 pF; f = 1 MHz;
dissipation VI = GND to – 29 – – – pF
capacitance VCC − 1.5 V [3]

[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
173
Power calculations
Logic Families
Static Power Consumption can be calculated by the following:
Ps (Static Power) = ICC (supply current) + Delta ICC (per input where

Vin = VCC − 2.1 V) + Ii (input leakage current per input when Vin = 0 or 5 V) + Iout (sum
of all output current)
A ˄ 𝐴𝐴 = 0 A ˅ 𝐴𝐴 = 1
Dynamic Power Consumption for the device can be calculated by the following
equation:
𝐴𝐴 ˄ 𝐵𝐵 = (𝐴𝐴 ˅ 𝐵𝐵) 𝐴𝐴 ˅ 𝐵𝐵 = (𝐴𝐴 ˄ 𝐵𝐵)

CPD is used to determine the dynamic power dissipation (PD in μW):
Where:
1317 (10) =
fI = input frequency in MHz V = supply voltage in V
1 * 2 10 + 0 * 29 + 1 * 28 + 0 * 27 + 0 * 2CC
6 + 1 * 25 +
fO = output frequency in MHz N = number of inputs switching
0 * 2 4 + 0 * 23 + 1 * 22 + 0 * 21 + 1 * 20
CL = output load capacitance in pF ∑ [CL × VCC² × fO] = sum of outputs
1317(10) = 10100100101
Special Features (2)
Bus Hold, Unbuffered output, Schmitt vs Schmitt Action (particularly for confusion
1011
on LVC family), onboard translation as specific to that particular family
+ 0011
Summary
1110
• Input levels:
For 74HC00: CMOS level
!
𝑃𝑃!"# = 𝐶𝐶!" TTL
For 74HCT00: × 𝑉𝑉level
!! × 𝑓𝑓! × 𝑁𝑁 + 𝐶𝐶! × 𝑉𝑉!! ! × 𝑓𝑓!
• Complies with JEDEC standard no. 7A
• Multiple package options
• Specified from -40C to +125C
174
1
9
9.2 The AHC/AHCT Logic Family
Logic Families
The AHC/AHCT family is an Advanced version of the HC/HCT family with lower
noise, lower power consumption, higher speed (lower propagation delay), higher
output drive current and overvoltage protected inputs. Functions are pin
compatible with HC/HCT devices and available as both standard (quad/hex/octal)
and MiniLogic (single/dual/triple) versions.
Applications
The AHC family is designed for The key applications addressed by this
operation from 2.0 to 5.5 V to provide logic family are:
support for CMOS level designs while • Industrial applications in general
the AHCT family is optimized for • Consumer electronics
operation at TTL levels (4.5 to 5.5 V). All • Computer peripherals
devices can support up to 8 mA output • Communications
drive current.
Construction
AHC/AHCT devices are built on a 1.2-micron process on an 8 inch wafer production

facility. All devices use copper wire bonds.
All AHC/AHCT devices have overvoltage tolerant inputs, allowing input signals to
exceed the Vcc supply (Vin = 5.5 V max regardless of VCC). External driving of the
output pins should be limited to VCC.
Inputs are protected from ESD damage (HBM EIA/JESD22-A114E exceeds 2000 V,
MM EIA/JESD22-A115-A exceeds 200 V, CDM EIA/JESD22-C101C exceeds 1000 V).
Input/output clamping current must be limited to 20 mA to prevent damage to the

ESD protection circuits. Note that the input and output voltage ratings may be
exceeded if the input and output current ratings are observed
All inputs have Schmitt Trigger Action except for 10 devices which have True
Schmitt Triggers (74AHC/AHCT132, -14, -1G14, -1G17, -3G14). Schmitt Trigger
Action input provide improved tolerance to input noise but do not have the long
rise/fall times of True Schmitt Triggers. Schmitt Trigger action is indicated in the
datasheet by the presence of the Transfer Characteristics Vt+, Vt- and Vh.
floating.
175
AHC/AHCT input and output characteristics

Logic Families
AHC Input figures AHCT Input figures
didd (A) didd (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VIN (V) VIN (V)
AHC input curves at 4V5 AHCT input curves at 4V5
Idd (A) Idd (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VIN (V) VIN (V)
AHC input curves at 5V AHCT input curves at 5V
Idd (A) Idd (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VIN (V) VIN (V)
AHC input curves at 5V5 AHCT input curves at 5V5
176
9
Outputs
Logic Families
aaa-028531
aaa-028530
0 15
IOH (mA)
IOL (mA)
12.5
-2
10
-4 7.5
-6
25°C 25°C
25°C min 2.5 25°C min
85°C min 85°C min
-8 0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 VO (V) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 VO (V)
IOH at 2.0 V IOL at 2.0 V

aaa-028529
aaa-028528
0 50
IOH (mA)
IOL (mA)
-5
40
-10
30
-15
20
-20
25°C 10 25°C
-25 25°C min 25°C min
85°C min 85°C min
-30 0
0 0.5 1 1.5 2 2.5 3 3.5 VO (V) 0 0.5 1 1.5 2 2.5 3 3.5 VO (V)

aaa-028527
aaa-028526
0 100
IOH (mA)
IOL (mA)
80
-20
60
-40
40
-60
25°C 20 25°C
25°C min 25°C min
85°C min 85°C min
-80 0
0 1 2 3 4 5 VO (V) 0 1 2 3 4 5 VO (V)
177
Logic Families

In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to GND (ground = 0 V).
VCC supply voltage −0,5 +7,0 V

VI input voltage −0,5 +7,0 V
IIK input clamping current VI < −0.5 V * −20 – mA
IOK output clamping current VO < −0.5 V or
−20 +20 mA
VO > VCC + 0.5 V *
IO output current VO = −0.5 V to (VCC + 0.5 V) −25 +25 mA
Ptot total power dissipation Tamb = −40 °C to +125 °C ** – 500 mW
* The input and output voltage ratings may be exceeded if the input and output current ratings are
observed.
** For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C.
For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C.
For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C.

Conditions
Parameter
74AHC74 74AHCT74
Symbol
Min Typ Max Min Typ Max Unit
VCC supply voltage 2,0 5,0 5,5 4,5 5,0 5,5 V

VI input voltage 0 – 5,5 0 – 5,5 V
VO output voltage 0 – VCC 0 – VCC V
Tamb ambient
−40 +25 +125 −40 +25 +125 °C
temperature
∆t/∆V input transition VCC =
– – 100 – – – ns/V
rise and fall rate 3.0 to 3.6 V
VCC =
– – 20 – – 20 ns/V
4.5 to 5.5 V
178
9
Logic Families
Tamb Tamb
Tamb
Conditions
Parameter
−40 °C to −40 °C to
25 °C
+85 °C +125 °C
Symbol
Min Typ Max Min Max Min Max Unit
74AHC74
VIH HIGH-level VCC = 2.0 V 1,5 – – 1,5 – 1,5 – V
input voltage
VCC = 3.0 V 2,1 – – 2,1 – 2,1 – V
VCC = 5.5 V 3,85 – – 3,85 – 3,85 – V
VIL LOW-level VCC = 2.0 V – – 0,5 – 0,5 – 0,5 V
input voltage
VCC = 3.0 V – – 0,9 – 0,9 – 0,9 V
VCC = 5.5 V – – 1,65 – 1,65 – 1,65 V
output
IO = −50 μA;
voltage 1,9 2,0 – 1,9 – 1,9 – V
VCC = 2.0 V
IO = −50 μA;
2,9 3,0 – 2,9 – 2,9 – V
VCC = 3.0 V
IO = −50 μA;
4,4 4,5 – 4,4 – 4,4 – V
VCC = 4.5 V
IO = −4.0 mA;
2,58 – – 2,48 – 2,40 – V
VCC = 3.0 V
IO = −8.0 mA;
3,94 – – 3,80 – 3,70 – V
VCC = 4.5 V
output
IO = 50 μA;
voltage – 0 0,1 – 0,1 – 0,1 V
VCC = 2.0 V
IO = 50 μA;
– 0 0,1 – 0,1 – 0,1 V
VCC = 3.0 V
IO = 50 μA;
– 0 0,1 – 0,1 – 0,1 V
VCC = 4.5 V
IO = 4.0 mA;
– – 0,36 – 0,44 – 0,55 V
VCC = 3.0 V
IO = 8.0 mA;
– – 0,36 – 0,44 – 0,55 V
VCC = 4.5 V
II input leakage VI = 5.5 V or
current GND; VCC = 0 to – – 0,1 – 1,0 – 2,0 μA
5.5 V
179
Logic Families
Tamb Tamb
Tamb
Conditions
Parameter
−40 °C to −40 °C to
25 °C
+85 °C +125 °C
Symbol
Min Typ Max Min Max Min Max Unit
ICC supply VI = VCC or GND;

current IO = 0 A; – – 2,0 – 20 – 40 μA
VCC = 5.5 V
CI input VI = VCC or GND
– 3 10 – 10 – 10 pF
capacitance
74AHCT74
VIH HIGH-level VCC = 4.5 to 5.5 V
2,0 – – 2,0 – 2,0 – V
input voltage
VIL LOW-level VCC = 4.5 to 5.5 V
– – 0,8 – 0,8 – 0,8 V
input voltage
VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V
output
IO = −50 μA 4,4 4,5 – 4,4 – 4,4 – V
voltage
IO = −8.0 mA 3,94 – – 3,80 – 3,70 – V
VOL LOW-level VI = VIH or VIL; VCC = 4.5 V
output
IO = 50 μA – 0 0,1 – 0,1 – 0,1 V
voltage
IO = 8.0 mA – – 0,36 – 0,44 – 0,55 V
II input leakage VI = 5.5 V or
current GND; VCC = 0 to – – 0,1 – 1,0 – 2,0 μA
5.5 V
ICC supply VI = VCC or GND;
current IO = 0 A; – – 2,0 – 20 – 40 μA
VCC = 5.5 V
ΔICC additional per input pin;
supply VI = VCC − 2.1 V;
current other pins at VCC – – 1,35 – 1,5 – 1,5 mA
or GND; IO = 0 A;
VCC = 4.5 to 5.5 V
CI input VI = VCC or GND
– 3 10 – 10 – 10 pF
capacitance
180
9
Logic Families
Tamb Tamb
Tamb
Conditions
Parameter
−40 °C to −40 °C to
25 °C
+85 °C +125 °C
Symbol
Min Typ* Max Min Max Min Max Unit
74AHC74
tpd propagation nCP to nQ, nQ; [1]
delay
VCC = 3.0 to
– 5,2 11,9 1,0 14,0 1,0 15,0 ns
3.6 V; CL = 15 pF
VCC = 3.0 to
– 7,4 15,4 1,0 17,5 1,0 19,5 ns
3.6 V; CL = 50 pF
VCC = 4.5 to
– 3,7 7,3 1,0 8,5 1,0 9,5 ns
5.5 V; CL = 15 pF
VCC = 4.5 to
– 5,2 9,3 1,0 10,5 1,0 12,0 ns
5.5 V; CL = 50 pF
nSD, nRD to nQ, nQ
VCC = 3.0 to
– 5,4 12,3 1,0 14,5 1,0 15,5 ns
3.6 V; CL = 15 pF
VCC = 3.0 to
– 7,7 15,8 1,0 18,0 1,0 20,0 ns
3.6 V; CL = 50 pF
VCC = 4.5 to
– 3,7 7,7 1,0 9,0 1,0 10,0 ns
5.5 V; CL = 15 pF
VCC = 4.5 to
– 5,3 9,7 1,0 11,0 1,0 12,5 ns
5.5 V; CL = 50 pF
fmax maximum VCC = 3.0 to
80 125 – 70 – 70 – MHz
frequency 3.6 V; CL = 15 pF
VCC = 3.0 to
50 75 – 45 – 45 – MHz
3.6 V; CL = 50 pF
VCC = 4.5 to
130 170 – 110 – 110 – MHz
5.5 V; CL = 15 pF
VCC = 4.5 to
90 115 – 75 – 75 – MHz
5.5 V; CL = 50 pF
tW pulse width CP HIGH or LOW; nSD, nRD LOW
VCC = 3.0 to 3.6 V 6,0 – – 7,0 – 7,0 – ns
VCC = 4.5 to 5.5 V 5,0 – – 5,0 – 5,0 – ns
181
Logic Families
Tamb Tamb
Tamb
Conditions
Parameter
−40 °C to −40 °C to
25 °C
+85 °C +125 °C
Symbol

VCC = 3.0 to 3.6 V 6,0 – – 7,0 – 7,0 – ns
VCC = 4.5 to 5.5 V 5,0 – – 5,0 – 5,0 – ns
VCC = 3.0 to 3.6 V 0,5 – – 0,5 – 0,5 – ns
VCC = 4.5 to 5.5 V 0,5 – – 0,5 – 0,5 – ns
trec recovery time nRD to nCP
VCC = 3.0 to 3.6 V 5,0 – – 5,0 – 5,0 – ns
VCC = 4.5 to 5.5 V 3,0 – – 3,0 – 3,0 – ns
CPD power fi = 1 MHz;
dissipation VI = GND to VCC – 12 – – – – – pF
capacitance [2]
74AHCT74
delay
VCC = 4.5 to
– 3,3 7,8 1,0 9,0 1,0 10,0 ns
5.5 V; CL = 15 pF
VCC = 4.5 to
– 4,8 8,8 1,0 10,0 1,0 11,0 ns
5.5 V; CL = 50 pF
nSD, nRD to nQ, nQ
VCC = 4.5 to
– 3,7 10,4 1,0 12,0 1,0 13,0 ns
5.5 V; CL = 15 pF
VCC = 4.5 to
– 5,3 11,4 1,0 13,0 1,0 14,5 ns
5.5 V; CL = 50 pF
fmax maximum VCC = 4.5 to
100 160 – 80 – 80 – MHz
frequency 5.5 V; CL = 15 pF
VCC = 4.5 to
80 140 – 65 – 65 – MHz
5.5 V; CL = 50 pF
tW pulse width CP HIGH or LOW; nSD, nRD LOW
VCC = 4.5 to 5.5 V 5,0 – – 5,0 – 5,0 – ns
VCC = 4.5 to 5.5 V 5,0 – – 5,0 – 5,0 – ns
182
9
Logic Families
Tamb Tamb
Tamb
Conditions
Parameter
−40 °C to −40 °C to
25 °C
+85 °C +125 °C
Symbol

VCC = 4.5 to 5.5 V 0 – – 0 – 0 – ns
trec recovery time nRD to nCP
VCC = 4.5 to 5.5 V 3,5 – – 3,5 – 3,5 – ns
CPD power fi = 1 MHz;
dissipation VI = GND to VCC – 16 – – – – – pF
capacitance [2]
* Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
Power calculations
Static Power Consumption can be calculated by the following:
Ps (Static Power) = ICC (supply current) + Delta ICC (per input where

A ˄V𝐴𝐴 =CC 0− 2.1 V) + Ii (input leakage current
in = V A ˅ 𝐴𝐴 per
= 1input when Vin = 0 or 5 V) + Iout (sum
of all output current)
Dynamic Power Consumption for the device can be calculated by the following
𝐴𝐴 ˄ 𝐵𝐵 = (𝐴𝐴
equation: ˅ 𝐵𝐵) 𝐴𝐴 ˅ 𝐵𝐵 = (𝐴𝐴 ˄ 𝐵𝐵)
Where:
1317 (10) =
fI = input frequency in MHz VCC = supply voltage in V
1 * 2 10 + 0 * 29 + 1 * 28 + 0 * 27 + 0 * 2N = number
fO = output frequency in MHz
6 + 1 * 25 +
of inputs switching
0 * 2 4 + 0 * 2load
CL = output
3 + 1 * 22 + 0 * 2
capacitance in pF + 1 * 2∑ [CL × VCC² × fO] = sum of outputs
1 0
1317(10) = 10100100101(2)
1011
+ 0011
1110 183
Special Features Summary

Logic Families
An overview of features available for The advanced high-speed CMOS AHC(T)

the AHC logic family: logic family is a speed upgrade of HC(T)
with over-voltage tolerant inputs for
• 8-bit bus interface functions
true mixed voltage applications.
• MiniLogic gates
Nexperia provides AHC products for use
• Analog switch functions
in 2.0 V to 6.0 V CMOS applications and
• TTL level input/outputs (AHCT family)
AHCT products for use in 4.5 V to 5.5 V
• Schmitt trigger inputs
TTL applications.
• Shift registers
• Clock dividers • 5 ns typical propagation delay
• Open drain outputs • Output drive capability IOH/
• Over voltage tolerant inputs IOL = ±8 mA
• Low power
• 5 V tolerant inputs
• Low noise: VOLP = 0.8 V (max.)
184
9
9.3 The LVC Logic Family
Logic Families
Nexperia offers the feature rich Low Voltage CMOS (LVC) logic portfolio to enable
the migration of electronic solutions from 5.5 V to lower power mixed 5.5 V / 3.3 V
and beyond. The LVC family includes Standard Logic functions with supply range
1.65 V to 3.3 V, as well as Mini Logic functions with supply range 1.65 V to 5.5 V.
Compared to older logic families, it has a much lower ICC. The power consumption
is very low due to very small CPD which is lower than in competition devices. The
LVC family offers features like overvoltage tolerant inputs and IOFF circuitry as well
as Schmitt-Trigger (action) inputs for many devices.
Applications Construction
The LVC logic device family supports The LVC family devices are built in 5 V
the trend to lower supply voltages. CMOS125 technology with a gate
It can therefore be applied in length of 600 nm. The process
applications like technology is Pb-free, RoHS and Dark
Green compliant. Bond wiring is done
• Computing, servers
with copper.
• Telecom and networking
equipment
• Advanced bus interface
• Industrial and Automotive
Inputs
There are two types of input circuits in the LVC family.
Schmitt-trigger action input. This input has a small amount of hysteresis built into
the input switching levels. The hysteresis is not formally specified but it does allow
the input to be tolerant to input slew rates as high as 20 ns/V at VCC = 1.65 V to 2.7 V
and 10 ns/V at VCC = 2.7 V to 5.5 V. The Schmitt-trigger action input may be
preceded by a bus-hold cell to define unused inputs. This bus-hold cell does not
affect the performance of the device.
185
Schmitt-trigger input. This input has much higher input hysteresis which is formally
Logic Families
specified in the datasheet. The advantage of true Schmitt-trigger inputs is that they
are tolerant to very slow edges. The following figures show a side by side
comparison of the IV characteristics of the Schmitt-trigger action input and the
Schmitt-trigger input.
All inputs are 5 V tolerant.
floating.
aaa-007079
aaa-007115
1.0 4
ICC (mA)
ICC (mA)
0.5 2
0 0
0 0.5 1.0 1.5 2.0 VI (V) 0 0.5 1.0 1.5 2.0 VI (V)
1.8 V Schmitt action 1.8 V Schmitt trigger

aaa-007078
aaa-007114
8 12
ICC (mA)
ICC (mA)
4 6
0 0
0 1 2 3 VI (V) 0 1 2 3 VI (V)
186
9
Logic Families
aaa-007077
aaa-007113
18 20
ICC (mA)
ICC (mA)
9 10
0 0
0 1 2 3 4 VI (V) 0 1 2 3 4 VI (V)

aaa-007076
aaa-007112
40 40
ICC (mA)
ICC (mA)
20 20
0 0
0 1 2 3 4 5 VI (V) 0 1 2 3 4 5 VI (V)
Outputs
Three types of output drivers are used in the LVC family.
The standard output is used in the standard logic devices. It provides a balanced
24 mA output drive at 3.3 V.
The source terminated output is used in standard logic devices that feature source
termination for better matching in distributed load applications such as
transmission lines. It has a balanced 12 mA output drive at 3.3 V.
The Mini Logic output is suitable for use over a wider supply voltage range. It
provides a balanced 24 mA output drive at 3.3 V and a balanced 32 mA output drive
at 5.0 V. The following figures show a side by side comparison of the IV
characteristics of all three outputs.
187
Logic Families
aaa-007075
aaa-007074
IOL (mA) 40 0
IOH (mA)
Standard output Standard output
VCC = 1.8 V VCC = 1.8 V
-10
20
-20
25°C 25°C
25°C min 25°C min
85°C min 85°C min
0 -30
0 0.5 1.0 1.5 2.0 VO (V) 0 0.5 1.0 1.5 2.0 VO (V)
IOL at 1.8 V IOH at 1.8 V

aaa-007073
aaa-007072
80 0
IOL (mA)
IOH (mA)
VCC = 2.7 V VCC = 2.7 V
40 -30
25°C 25°C
25°C min 25°C min
85°C min 85°C min
0 -60
0 1 2 3 VO (V) 0 1 2 3 VO (V)

aaa-007071
120 0
aaa-007070
IOL (mA)
IOH (mA)

VCC = 3.3 V VCC = 3.3 V
60 -50
25°C 25°C
25°C min 25°C min
85°C min 85°C min
0 -100
0 1 2 3 4 VO (V) 0 1 2 3 4 VO (V)
188
9
Logic Families
Table 11: Limiting values of the LVC family devices

IIK input clamping current VI < 0 V −50 – mA
VI input voltage * −0,5 +6,5 V
IOK output clamping current VO > VCC or VO < 0 V – ±50 mA
VO output voltage Active mode * −0,5 VCC + 0.5 V
Power-down mode;
−0,5 +6,5 V
VCC = 0 V *
IO output current VO = 0 V to VCC – ±50 mA
observed.
** For TSSOP8 packages: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
Recommended operating conditions
Table 12: Recommended operating conditions for the mini LVC logic
devices (≤10 pins)
VCC supply voltage 1,65 5,5 V

VI input voltage 0 5,5 V
VO output voltage Active mode 0 VCC V
Power-down mode; VCC = 0 V 0 5,5 V
Tamb ambient temperature −40 +125 °C
input transition rise VCC = 1.65 to 2.7 V – 20 ns/V

Δt/ΔV
and fall rate VCC = 2.7 to 5.5 V – 10 ns/V
189
Table 13: Recommended operating conditions for the standard LVC logic
Logic Families
devices (>10 pins)
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage for maximum speed

1,65 – 3,6 V
performance
for low-voltage
1,2 – 3,6 V
applications
VI input voltage 0 – 5,5 V
VO output voltage 0 – VCC V
Tamb ambient temperature −40 – +125 °C
Δt/ΔV input transition rise VCC = 1.65 V to 2.7 V 0 – 20 ns/V
and fall rate
VCC = 2.7 V to 3.6 V 0 – 10 ns/V
Static characteristics
Table 14: Static characteristics for mini Logic devices (≤10 pins)
Tamb Tamb
Conditions
Parameter
−40 °C to +85 °C −40 °C to +125 °C

Symbol
VIH HIGH-level VCC = 1.65 to

0.65 VCC – – 0.65 VCC – V
input 1.95 V
voltage
VCC = 2.3 to
1,7 – – 1,7 – V
2.7 V
VCC = 2.7 to
2,0 – – 2,0 – V
3.6 V
VCC = 4.5 to
0.7 VCC – – 0.7 VCC – V
5.5 V
VIL LOW-level VCC = 1.65 to
– – 0.35 VCC – 0.35 VCC V
input 1.95 V
voltage
VCC = 2.3 to
– – 0,7 – 0,7 V
2.7 V
VCC = 2.7 to
– – 0,8 – 0,8 V
3.6 V
VCC = 4.5 to
– – 0.3 VCC – 0.3 VCC V
5.5 V
190
9
Logic Families
Tamb Tamb
Conditions
Parameter
−40 °C to +85 °C −40 °C to +125 °C
Symbol

output
IO = −100 μA;
voltage
VCC = 1.65 to VCC − 0.1 – – VCC − 0.1 – V
5.5 V
IO = −4 mA;
1,2 1,54 – 0,95 – V
VCC = 1.65 V
IO = −8 mA;
1,9 2,15 – 1,7 – V
VCC = 2.3 V
IO = −12 mA;
2,2 2,50 – 1,9 – V
VCC = 2.7 V
IO = −24 mA;
2,3 2,62 – 2,0 – V
VCC = 3.0 V
IO = −32 mA;
3,8 4,11 – 3,4 – V
VCC = 4.5 V
output
IO = 100 μA;
voltage
VCC = 1.65 to – – 0,10 – 0,10 V
5.5 V
IO = 4 mA;
– 0,07 0,45 – 0,70 V
VCC = 1.65 V
IO = 8 mA;
– 0,12 0,30 – 0,45 V
VCC = 2.3 V
IO = 12 mA;
– 0,17 0,40 – 0,60 V
VCC = 2.7 V
IO = 24 mA;
– 0,33 0,55 – 0,80 V
VCC = 3.0 V
IO = 32 mA;
– 0,39 0,55 – 0,80 V
VCC = 4.5 V
II input VI = 5.5 V or
leakage GND;
– ±0.1 ±1 – ±1 μA
current VCC = 0 to
5.5 V
IOFF power-off VI or
leakage VO = 5.5 V; – ±0.1 ±2 – ±2 μA
current VCC = 0 V
191
Logic Families
Tamb Tamb
Conditions
Parameter
−40 °C to +85 °C −40 °C to +125 °C
Symbol
ICC supply VI = 5.5 V or

current GND;
– 0,1 4 – 4 μA
VCC = 1.65 to
5.5 V; IO = 0 A
ΔICC additional per pin;
supply VI = VCC −
current 0.6 V; IO = 0 A; – 5 500 – 500 μA
VCC = 2.3 to
5.5 V
CI input
– 4,0 – – – pF
capacitance
Table 15: Static characteristics for standard Logic devices (> 10 pins)
Tamb Tamb
Conditions
Parameter
−40 °C to +85 °C −40 °C to +125 °C

Symbol
VIH HIGH-level VCC = 1.2 V 1,08 – – 1,08 – V

input
VCC = 1.65 to 0.65 × 0.65 ×
voltage – – – V
1.95 V VCC VCC
VCC = 2.3 to
1,7 – – 1,7 – V
2.7 V
VCC = 2.7 to
2,0 – – 2,0 – V
3.6 V
VIL LOW-level VCC = 1.2 V – – 0,12 – 0,12
input
VCC = 1.65 to 0.35 × 0.35 ×
voltage – – –
1.95 V VCC VCC
VCC = 2.3 to
– – 0,7 – 0,7
2.7 V
VCC = 2.7 to
– – 0,8 – 0,8
3.6 V
192
9
Logic Families
Tamb Tamb
Conditions
Parameter
−40 °C to +85 °C −40 °C to +125 °C
Symbol

output
IO = −100 μA;
voltage
VCC = 1.65 to VCC − 0.2 – – VCC − 0.3 – V
3.6 V
IO = −4 mA;
1,2 – – 1,05 – V
VCC = 1.65 V
IO = −8 mA;
1,8 – – 1,65 – V
VCC = 2.3 V
IO = −12 mA;
2,2 – – 2,05 – V
VCC = 2.7 V
IO = −18 mA;
2,4 – – 2,25 – V
VCC = 3.0 V
IO = −24 mA;
2,2 – – 2,0 – V
VCC = 3.0 V
output
IO = 100 μA;
voltage
VCC = 1.65 to – – 0,2 – 0,3 V
3.6 V
IO = 4 mA;
– – 0,45 – 0,65 V
VCC = 1.65 V
IO = 8 mA;
– – 0,6 – 0,8 V
VCC = 2.3 V
IO = 12 mA;
– – 0,4 – 0,6 V
VCC = 2.7 V
IO = 24 mA;
– – 0,55 – 0,8 V
VCC = 3.0 V
II input VCC = 3.6 V;
leakage VI = 5.5 V or – ±0.1 ±5 – ±20 μA
current GND
ICC supply VCC = 3.6 V;
current VI = VCC or – 0,1 10 – 40 μA
GND; IO = 0 A
193
Logic Families
Tamb Tamb
Conditions
Parameter
−40 °C to +85 °C −40 °C to +125 °C
Symbol
ΔICC additional per input pin;

supply VCC = 2.7 to
current 3.6 V; – 5 500 – 5000 μA
VI = VCC −
0.6 V; IO = 0 A
CI input VCC = 0 to
capacitance 3.6 V; VI = – 4 – – – pF
GND to VCC
Dynamic characteristics
Table 16: Dynamic characteristics for mini logic
Tamb Tamb
Conditions
Parameter
−40 °C to −40 °C to
+85 °C +125 °C
Symbol
tpd propagation CP to Q, Q; [1]

delay
VCC = 1.65 to 1.95 V 1,5 6,0 13,4 1,5 13,4 ns
VCC = 2.3 to 2.7 V 1,0 3,5 7,1 1,0 7,1 ns
VCC = 2.7 V 1,0 3,5 7,1 1,0 7,1 ns
VCC = 3.0 to 3.6 V 1,0 3,5 5,9 1,0 5,9 ns
VCC = 4.5 to 5.5 V 1,0 2,5 4,1 1,0 4,1 ns
SD to Q, Q; [1]
VCC = 1.65 to 1.95 V 1,5 6,0 12,9 1,5 12,9 ns
VCC = 2.3 to 2.7 V 1,0 3,5 7,0 1,0 7,0 ns
VCC = 2.7 V 1,0 3,5 7,0 1,0 7,0 ns
VCC = 3.0 to 3.6 V 1,0 3,0 5,9 1,0 5,9 ns
VCC = 4.5 to 5.5 V 1,0 2,5 4,1 1,0 4,1 ns
194
9
Logic Families
Tamb Tamb
Conditions
Parameter
−40 °C to −40 °C to
+85 °C +125 °C
Symbol
tpd propagation RD to Q, Q; [1]

delay
VCC = 1.65 to 1.95 V 1,5 5,0 12,9 1,5 12,9 ns
VCC = 2.3 to 2.7 V 1,0 3,5 7,0 1,0 7,0 ns
VCC = 2.7 V 1,0 3,5 7,0 1,0 7,0 ns
VCC = 3.0 to 3.6 V 1,0 3,0 5,9 1,0 5,9 ns
VCC = 4.5 to 5.5 V 1,0 2,5 4,1 1,0 4,1 ns
tW pulse width CP HIGH or LOW
VCC = 1.65 to 1.95 V 6,2 – – 6,2 – ns
VCC = 2.3 to 2.7 V 2,7 – – 2,7 – ns
VCC = 2.7 V 2,7 – – 2,7 – ns
VCC = 3.0 to 3.6 V 2,7 1,3 – 2,7 – ns
VCC = 4.5 to 5.5 V 2,0 – – 2,0 – ns
SD and RD LOW
VCC = 1.65 to 1.95 V 6,2 – – 6,2 – ns
VCC = 2.3 to 2.7 V 2,7 – – 2,7 – ns
VCC = 2.7 V 2,7 – – 2,7 – ns
VCC = 3.0 to 3.6 V 2,7 1,6 – 2,7 – ns
VCC = 4.5 to 5.5 V 2,0 – – 2,0 – ns
trec recovery time SD or RD
VCC = 1.65 to 1.95 V 1,9 – – 1,9 – ns
VCC = 2.3 to 2.7 V 1,4 – – 1,4 – ns
VCC = 2.7 V 1,3 – – 1,3 – ns
VCC = 3.0 to 3.6 V +1,2 −3,0 – +1,2 – ns
VCC = 4.5 to 5.5 V 1,0 – – 1,0 – ns
195
Logic Families
Tamb Tamb
Conditions
Parameter
−40 °C to −40 °C to
+85 °C +125 °C
Symbol
tsu set-up time D to CP

VCC = 1.65 to 1.95 V 2,9 – – 2,9 – ns
VCC = 2.3 to 2.7 V 1,7 – – 1,7 – ns
VCC = 2.7 V 1,7 – – 1,7 – ns
VCC = 3.0 to 3.6 V 1,3 0,5 – 1,3 – ns
VCC = 4.5 to 5.5 V 1,1 – – 1,1 – ns
th hold time D to CP
VCC = 1.65 to 1.95 V 1,5 – – 1,5 – ns
VCC = 2.3 to 2.7 V 1,0 – – 1,0 – ns
VCC = 2.7 V 1,0 – – 1,0 – ns
VCC = 3.0 to 3.6 V 1,0 0,6 – 1,0 – ns
VCC = 4.5 to 5.5 V 1,0 – – 1,0 – ns
fmax maximum CP
frequency
VCC = 1.65 to 1.95 V 80 – – 80 – MHz
VCC = 2.3 to 2.7 V 175 – – 175 – MHz
VCC = 2.7 V 175 – – 175 – MHz
VCC = 3.0 to 3.6 V 175 280 – 175 – MHz
VCC = 4.5 to 5.5 V 200 – – 200 – MHz
CPD power VI = GND to VCC;
dissipation VCC = 3.3 V [2] – 15 – – – pF
capacitance
* Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
196
9
Table 17: Dynamic characteristics for standard logic
Logic Families
Tamb Tamb
Conditions
Parameter
−40 °C to −40 °C to
+85 °C +125 °C
Symbol

delay VCC = 1.2 V – 15 – – – ns
VCC = 1.65 to 1.95 V 1,0 5,0 10,3 1,0 11,9 ns
VCC = 2.3 to 2.7 V 1,8 2,9 5,8 1,8 6,7 ns
VCC = 2.7 V 1,0 2,7 6,0 1,0 7,5 ns
VCC = 3.0 to 3.6 V 1,0 2,6 5,2 1,0 6,5 ns
nSD to nQ, nQ
VCC = 1.2 V – 15 – – – ns
VCC = 1.65 to 1.95 V 0,5 4,0 10,6 0,5 12,2 ns
VCC = 2.3 to 2.7 V 1,0 2,4 6,1 1,0 7,1 ns
VCC = 2.7 V 1,0 2,9 6,4 1,0 8,0 ns
VCC = 3.0 to 3.6 V 1,0 2,2 5,4 1,0 7,0 ns
nRD to nQ, nQ
VCC = 1.2 V – 15 – – – ns
VCC = 1.65 to 1.95 V 0,5 4,1 10,7 0,5 12,4 ns
VCC = 2.3 to 2.7 V 1,0 2,4 6,1 1,0 7,1 ns
VCC = 2.7 V 1,0 3,0 6,4 1,0 8,0 ns
VCC = 3.0 to 3.6 V 1,0 2,2 5,4 1,0 7,0 ns
tW pulse width clock HIGH or LOW
VCC = 1.65 to 1.95 V 5,0 – – 5,0 – ns
VCC = 2.3 to 2.7 V 4,0 – – 4,0 – ns
VCC = 2.7 V 3,3 – – 4,5 – ns
VCC = 3.0 to 3.6 V 3,3 1,3 – 4,5 – ns
set or reset LOW
VCC = 1.65 to 1.95 V 5,0 – – 5,0 – ns
VCC = 2.3 to 2.7 V 4,0 – – 4,0 – ns
VCC = 2.7 V 3,3 – – 4,5 – ns
VCC = 3.0 to 3.6 V 3,3 1,7 – 4,5 – ns
197
Logic Families
Tamb Tamb
Conditions
Parameter
−40 °C to −40 °C to
+85 °C +125 °C
Symbol
trec recovery time set or reset

VCC = 1.65 to 1.95 V 1,5 – – 1,5 – ns
VCC = 2.3 to 2.7 V 1,5 – – 1,5 – ns
VCC = 2.7 V 1,5 – – 1,0 – ns
VCC = 3.0 to 3.6 V +1,0 -3,0 – 1,0 – ns
VCC = 1.65 to 1.95 V 3,0 – – 3,0 – ns
VCC = 2.3 to 2.7 V 2,5 – – 2,5 – ns
VCC = 2.7 V 2,2 – – 2,2 – ns
VCC = 3.0 to 3.6 V 2,0 0,8 – 2,0 – ns
VCC = 1.65 to 1.95 V 2,0 – – 2,0 – ns
VCC = 2.3 to 2.7 V 1,5 – – 1,5 – ns
VCC = 2.7 V 1,0 – – 1,0 – ns
VCC = 3.0 to 3.6 V +1,0 -0,2 – 1,0 – ns
fmax maximum nCP
frequency VCC = 1.65 to 1.95 V 100 – – 80 – MHz
VCC = 2.3 to 2.7 V 125 – – 100 – MHz
VCC = 2.7 V 150 – – 120 – MHz
VCC = 3.0 to 3.6 V 150 250 – 120 – MHz
tsk(o) output skew VCC = 3.0 to 3.6 V [2]
– – 1,0 – 1,5 ns
time
CPD power per flip-flop; VI = GND to VCC [3]
dissipation VCC = 1.65 to 1.95 V – 12,4 – – – pF
capacitance
VCC = 2.3 to 2.7 V – 16,0 – – – pF
VCC = 3.0 to 3.6 V – 19,1 – – – pF
[2] Skew between any two outputs of the same package switching in the same direction. This
parameter is guaranteed by design.
198
9
1317(10) =
1 * 210 + 0 * 2
Power 9 + 1 * 28 + 0 * 27 + 0 * 26 + 1 * 25 +
calculations
Logic Families
0 * 24 + 0 * 2
The static
3
power + 1 * 22 + 0 * 21 + 1 * 20
consumption calculation is much dependent on the input voltage
level: if it is properly set to either VCC or GND level, we can use the static supply
1317
current = 10100100101
(10)ICC for calculating the power
(2) consumption: Pstatic = VCC x ICC
In case Vin is at some intermediate level and the device is operating in undefined
state,
1011both NMOS and PMOS transistors of the input stage may be conducting and
then we need to use the
+ 0011
The1110
dynamic power consumption calculation is:
Where:
fI = input frequency in MHz VCC = number of inputs switching

fO = output frequency in MHz ∑(CL × VCC² × fO) = sum of inputs
CL = output load capacitance in pF
An additional current through the devices can be caused by driving the devices with
a voltage nearby VCC/2 causing both NMOS and PMOS transistor of the input stage
to be conducting, although not fully conducting. The ΔICC values are listed in the
static characteristics.
These characteristics are generally valid for devices of the LVC family, please look at
1 the respective data sheet for more specific details of Power calculations.

199
Special Features
Logic Families
To reduce standby current, many applications use advanced power management

that powers down unused circuits within the application. To support this partial
power down architecture a logic family must not have any leakage paths to the
supply rails when the supply voltage (VCC) is 0 V. LVC includes IOFF circuitry that
prevents current paths through inputs and outputs when VCC = 0 V.
A couple of 16/32 bit Buffers/line drivers (LVCH) have Bus hold functionality for the
inputs, holding the last input stage when inputs are temporarily disconnected.
An overview of features available for the AUP logic family:
• Bus hold inputs • Open drain outputs

• Schmitt-Trigger/Schmitt Action inputs • Source termination
• Over voltage tolerant inputs • Dual supply translations
Summary
Nexperia offers the feature rich Low Voltage CMOS (LVC) logic portfolio to enable
the migration of electronic solutions from 5.5 V to lower power mixed 5.5 V / 3.3 V
and beyond. The LVC family includes Standard Logic functions with supply range
1.65 V to 3.3 V, as well as Mini Logic functions with supply range 1.65 V to 5.5 V.
Some key features are:
• 4 ns typical propagation delay • Over voltage tolerant inputs

• 24 mA balanced output drive • IOFF circuitry
• Wide supply range • AEC-Q100 compliant options
• 5 V tolerant I/O • Fully specified (-40 to +125°C)
• Series termination options • Pb-free, RoHS compliant and Dark
• Bus Hold options Green
200
9
9.4 The AVC Logic Family
Logic Families
Nexperia’s AVC (Advanced Very low voltage CMOS) logic family is optimized for
high performance bus interface applications. Operating with sub 2 ns propagation
delays, AVC meets the demands of new digital systems that require low power
consumption, very high bus speeds in excess of 100 MHz, and low noise. AVC is
targeted for new high performance workstations, PCs, telecommunications
equipment, and data communications equipment.
New circuit techniques have been pioneered that give AVC unique properties.
Optimized for 2.5 V systems, AVC also operates at 3.3 V and 1.8 V to support mixed
voltage systems. AVC also features a power-off disable output circuit that isolates
the outputs during power-down modes. This chapter will provide designers better
insight into this new family for use in their applications.
Construction
The AVC family is built in 3.3 V CMOS technology with 0.35 μm gate length. The
process technology is Pb-Free, RoHS and Dark Green compliant. Bond wiring is
done with copper.
Input and output structure
Input Structures VCC

To bus hold circuit
AVC inputs use a CMOS totem pole
inverter as shown in Figure 9.3. The ESD and clamp circuit
circuit does not have the overshoot Input
clamping diode from the input to VCC

aaa-032016
that is used in classic CMOS circuits.

Since there is no current path to VCC,
the voltage may be raised above the VCC
level and allows interfacing in 1.8 V to Figure 9.3 | Simplified AVC input structure
3.3 V systems.
Since the circuit is CMOS, care must still be taken to ensure that the inputs don’t
float. When inputs float, the voltage level may reach the threshold level such that
both transistors in the totem pole structure will conduct, causing a current path
from VCC and ground, wasting power.
floating.
201
Input and Output figures

Logic Families
AVC Input Figures
dIcc_total (A) dIcc_total (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VIN (V) VIN (V)
AVC input at 0.8V AVC input at 1V2
Idd (A) Idd (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VIN (V) VIN (V)
AVC input at 1V8 AVC input at 3V3
Output figures
IOL (A) IOL (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VOUT (V) VOUT (V)
AVC output at 0.8V AVC output at 1V2
202
9
Logic Families
IOL (A) IOL (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VOUT (V) VOUT (V)
AVC output at 1V8 AVC output at 3V3
IOH (A) IOH (A)
25°C typ
25°C min
85°C min
125°C min
25°C typ
25°C min
85°C min
125°C min
VOUT (V) VOUT (V)
IOH (A) IOH (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VOUT (V) VOUT (V)
203
Logic Families

VCC supply voltage −0.5 +4,6 V

IIK input clamping current VI < 0 V – −50 mA
VI input voltage * −0.5 +4,6 V
IOK output clamping current VO < 0 V −50 – mA
VO output voltage output HIGH or LOW * −0.5 VCC + 0.5 V
output 3-state * −0.5 +4,6 V
observed.
** Above 60 °C, the value of Ptot derates linearly with 5.5 mW/K.

VCC supply voltage according to JEDEC Low 1,4 – 1,6 V

Voltage Standards 1,65 – 1,95 V
2,3 – 2,7 V
3,0 – 3,6 V
for low-voltage applications 1,2 – 3,6 V
VO output voltage output HIGH or LOW 0 – VCC V
output 3-state 0 – 3,6 V
Tamb ambient temperature in free air −40 – +85 °C
∆t/∆V input transition rise VCC = 1.4 to 1.6 V 0 – 40 ns/V
and fall rate VCC = 1.65 to 2.3 V 0 – 30 ns/V
VCC = 2.3 to 3.0 V 0 – 20 ns/V
VCC = 3.0 to 3.6 V 0 – 10 ns/V
204
9
Logic Families
Tamb
Conditions
Parameter
−40 °C to +85 °C
Symbol
Min Typ* Max Unit
VIH HIGH-level VCC = 1.2 V VCC – – V

input voltage VCC = 1.4 to 1.6 V 0.65 × VCC 0,9 – V
VCC = 1.65 to 1.95 V 0.65 × VCC 0,9 – V
VCC = 2.3 to 2.7 V 1,7 1,2 – V
VCC = 3.0 to 3.6 V 2,0 1,5 – V
VIL LOW-level input VCC = 1.2 V – – GND V
voltage VCC = 1.4 to 1.6 V – 0,9 0.35 × VCC V
VCC = 1.65 to 1.95 V – 0,9 0.35 × VCC V
VCC = 2.3 to 2.7 V – 1,2 0,7 V
VCC = 3.0 to 3.6 V – 1,5 0,8 V
output voltage IO = −100 μA;
VCC − 0.20 VCC – V
VCC = 1.65 to 3.6 V
IO = −3 mA; VCC = 1.4 V VCC − 0.35 VCC − 0.23 – V
output voltage IO = 100 μA;
– GND 0,20 V
VCC = 1.65 to 3.6 V
IO = 3 mA; VCC = 1.4 V – 0,10 0,35 V
IO = 4 mA; VCC = 1.65 V – 0,10 0,45 V
IO = 8 mA; VCC = 2.3 V – 0,26 0,55 V
IO = 12 mA; VCC = 3.0 V – 0,36 0,70 V
II input leakage per pin;
current VI = VCC or GND; – 0,1 2,5 μA
VCC = 1.4 to 3.6 V
IOFF power-off VI or VO = 3.6 V;
– ±0.1 ±10 μA
leakage current VCC = 0.0 V
IOZ OFF-state VI = VIH or VIL; VO = VCC or GND
output current VCC = 1.4 to 2.7 V – 0,1 5 μA
VCC = 3.0 to 3.6 V – 0,1 10 μA
205
Logic Families
Tamb
Conditions
Parameter
−40 °C to +85 °C
Symbol
Min Typ* Max Unit
ICC supply current VI = VCC or GND; IO = 0 A

VCC = 1.4 to 2.7 V – 0,1 20 μA
VCC = 3.0 to 3.6 V – 0,2 40 μA
CI input
– 5 – pF
capacitance
Tamb
Conditions
Parameter
−40 °C to +85 °C
Symbol
Min Typ* Max Unit
tpd propagation nCP to nQn; [1]

delay
VCC = 1.2 V – 3,1 – ns
VCC = 1.4 to 1.6 V 1,2 2,4 8,4 ns
VCC = 1.65 to 1.95 V 1,0 2,0 6,7 ns
VCC = 2.3 to 2.7 V 0,8 1,5 4,1 ns
VCC = 3.0 to 3.6 V 0,7 1,3 3,3 ns
ten enable time nOE to nQn, nBn; [1]
VCC = 1.2 V – 5,4 – ns
VCC = 1.4 to 1.6 V 1,6 3,9 8,5 ns
VCC = 1.65 to 1.95 V 2,3 3,3 6,7 ns
VCC = 2.3 to 2.7 V 0,9 2,3 4,3 ns
VCC = 3.0 to 3.6 V 0,7 2,0 3,4 ns
tdis disable time nOE to nQn; [1]
VCC = 1.2 V – 5,6 – ns
VCC = 1.4 to 1.6 V 2,5 4,5 9,4 ns
VCC = 1.65 to 1.95 V 1,8 3,3 7,8 ns
VCC = 2.3 to 2.7 V 1,0 1,8 4,2 ns
VCC = 3.0 to 3.6 V 1,2 2,0 3,9 ns
206
9
Logic Families
Tamb
Conditions
Parameter
−40 °C to +85 °C
Symbol
Min Typ* Max Unit
tW pulse width HIGH; nCP

VCC = 1.2 V – 0,8 – ns
VCC = 1.4 to 1.6 V – 0,5 – ns
VCC = 1.65 to 1.95 V 3,1 0,3 – ns
VCC = 2.3 to 2.7 V 2,5 0,2 – ns
VCC = 3.0 to 3.6 V 2,5 0,2 – ns
tsu set-up time nDn to nCP
VCC = 1.2 V – −0.6 – ns
VCC = 1.4 to 1.6 V 2,7 −0.3 – ns
VCC = 1.65 to 1.95 V 1,9 −0.3 – ns
VCC = 2.3 to 2.7 V 1,4 −0.2 – ns
VCC = 3.0 to 3.6 V 1,4 −0.1 – ns
th hold time nDn to nCP
VCC = 1.2 V – 0,8 – ns
VCC = 1.4 to 1.6 V 1,3 0,7 – ns
VCC = 1.65 to 1.95 V 1,2 0,6 – ns
VCC = 2.3 to 2.7 V 1,1 0,5 – ns
VCC = 3.0 to 3.6 V 1,1 0,4 – ns
fmax maximum VCC = 1.2 V – 250 – MHz
frequency
VCC = 1.4 to 1.6 V – 300 – MHz
VCC = 1.65 to 1.95 V 160 320 – MHz
VCC = 2.3 to 2.7 V 200 350 – MHz
VCC = 3.0 to 3.6 V 200 350 – MHz
CPD power per input; VI = GND to VCC [2]
dissipation
outputs enabled – 66 – pF
capacitance
outputs disabled – 1 – pF
[1] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ.
207
Table 22: Propagation Delay

Logic Families
Parameter Characteristic Values
Supply Voltage 1.65–1.95 V 2.3–2.7 V 3.0–3.6 V

Input Voltage 3.6 V 3.6 V 3.6 V
Maximum Propagation Delay1 3.2 ns 1.9 ns 1.7 ns
1: 74AVC16245
Power calculations
AVC is constructed using a 0.35 micron CMOS fabrication process resulting in low
current consumption. Figure 9.4 shows simulation data of ICC at various frequencies
for single and multiple output switching:
250
ICC (mA)
16 outputs switching
8 outputs switching
200
1 output switching
Typical process
150 parameters:
VCC = 2.5 V
Tamb = 25 °C
100 30 pF loading
50
0
0 50 100 150 200
aaa-032309
Operating frequency (MHz)
Figure 9.4 | ICC over frequency
208
𝐶𝐶!" = 12.2 𝑝𝑝𝑝𝑝
𝐶𝐶!" =
11.53 𝑚𝑚𝑚𝑚 × 3.6 𝑉𝑉 − 50 𝑝𝑝𝑝𝑝 × 3.6 𝑉𝑉 ! × 30 𝑀𝑀𝑀𝑀𝑀𝑀 9
𝐶𝐶!" = 56.8
Dynamic 𝑝𝑝𝑝𝑝dissipation can be calculated by the following formula:
power
Logic Families
𝑃𝑃! = 𝐶𝐶!" × 𝑉𝑉!!! × 𝑓𝑓!" + 𝐶𝐶! × 𝑉𝑉!!! × 𝑓𝑓!"#
Where: !!" ! !!"(!) !.! ! ! !.!" !

𝑅𝑅!" = = = 210 Ω
!!(!) !" !!
CPD = power dissipation capacitance fOUT = output frequency
per buffer, latch, or flip-flop CL = output load capacitance
fIN = input frequency ∑ (CL × VCC² × fOUT) = sum of outputs
For an example, with a typical CPD of 20 pF for an AVC16244, 15 pF loading,
100 MHz operation, and 2.5 V VCC, power dissipation is 162.5 mW with 16 outputs
switching.
Special Features
Output Protection: IOFF
Another feature of AVC is the output protection circuit. In mixed voltage systems,
when the output node is tied to a bus from a higher voltage system, the original
diode connection provides a current path to VCC when the output node is 0.6 V
higher than the AVC device’s VCC. This current can damage the diode, and a current
path now exists between the two power supplies. Damage can also occur from the
higher voltage supply charging the lower voltage supply.
1 protect the diodes, the cathodes are switched rather than hard-wired to V . A
To CC
comparator senses the output node voltage and shorts out the diode when the
voltage rises above the AVC device’s VCC by 0.6 V. This works in the 3-State mode
only, and the current path to VCC is eliminated, allowing the output to be raised
above VCC in a mixed voltage system. While the device is powered down, the diodes
are disconnected, and only leakage current of 10uA maximum is present when a
voltage is applied to the output. This current parameter is called IOFF, and the
protection feature is useful for power-down modes.
209
Bus Hold
Logic Families
Also, floating inputs can cause output oscillation, creating excessive current and
heat which can damage the device. To keep inputs from floating, a common
practice is to tie a pull-up resistor of several thousand ohms between the input and
VCC. Although effective, this adds board component count and extra power
dissipation. Another solution is to use a device with an integrated bus hold cell. AVC
devices have an option to integrate this bus hold feature on inputs. This is
designated in the part type with an “H” by calling it 74AVCH. Figure 9.5 shows a bus
hold cell:
aaa-032017
VCC
To input inverter
Input pin
Bus hold cell
Figure 9.5 | Simplified bus holder cell
The cell consists of two inverters to keep the logic level the same at the input node.
The inverters are comprised of small MOS transistors with weak drive capability in
the order of several hundred microamps. When the input starts to float, the PMOS
or NMOS structures pull the bus to the VCC or ground rail of the last valid logic
state. The cell requires a small amount of current, called IBHH or IBHL, to sustain
the logic HIGH and LOW threshold levels. Also, the cell needs several hundred
microamps, called IBHHO or IBHLO, to overdrive the cell and flip the logic level
from 3-State to a HIGH or LOW. These specifications are shown in Table 23.
Simulation data for the bus hold current characteristics are shown in Figure 9.6. The
user must also take considerations when the bus hold cell is connected to existing
external pull-up or pull-down resistors. When using external resistors, or when a
connected ASIC has them built-in, the resistor value must be low enough to allow
sufficient current to overpower the bus hold cell and drive the input past the
threshold point to the HIGH or LOW state.
210
9
Table 23: Bus hold current specification
Logic Families
Tamb Test Conditions
Symbol Parameter −40 to +85°C Min. Unit VCC (V) VI (V)
IBHL Bus hold LOW 25 μA 1.65 0.35 VCC

sustaining current 45 μA 2.3 0.7 V
75 μA 3.0 0.8 V
IBHH Bus hold HIGH −25 μA 1.65 0.65 VCC
sustaining current −45 μA 2.3 1.7 V
−75 μA 3.0 2.0 V
IBHLO Bus hold LOW 200 μA 1.95
overdrive current 300 μA 2.7
450 μA 3.6
IBHHO Bus hold HIGH −200 μA 1.95
overdrive current −300 μA 2.7
−450 μA 3.6
aaa-032310
250
Input Current (µA)
VCC = 3.3 V
200
VCC = 2.5 V
150 VCC = 1.8 V
Typical process
100
parameters: Tamb = 25 °C
50
-50
-100
-150
-200
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Input voltage (V)
Figure 9.6 | Bus Hold current characteristics
Summary
The AVC family offers a solution for new designs needing the highest performance
in 1.8 V, 2.5 V, and 3.3 V systems. AVC offers a line of bus interface functions for
today’s high performance, low voltage systems.
211
9.5 The AUP Logic Family

Logic Families
The AUP family of Si-gate CMOS devices uses advanced process technology and
next generation packaging technology to create extremely small functions that
consume very little power. The devices are available in single (1G), dual (2G) and
triple (3G) gate formats.
Multiple standard, combination and configurable logic functions are available in the
AUP family as well as low threshold input variants and dual supply voltage level
translators.
Due to its advanced process technology AUP provides very low static and dynamic
power dissipation.
Applications
The AUP logic devices are specifically designed for battery powered mobile
applications with which are demanding low energy consumption for operation.
Examples are:
• Cellular handsets and smart phones • Consumer entertainment

• MP3 players and mobile video players (LCD TVs, DVD+R/W systems, STBs)
• DSCs and digital camcorders • Portable instrumentation
• Portable handhelds
(PDAs, GPS devices, notebook PCs)
The low propagation delay and the wide voltage range are making this family
suitable for mixed voltage applications. 3.6 V tolerant inputs enable a device
supplied at 1.8 V to interface between 3.3 V and 1.8 V systems. Options with
low-threshold inputs (1T) can interface between 1.2 V and 3.3 V systems when
supplied with 3.3 V. The portfolio also includes dual supply uni-directional and
bi-directional voltage level translators. Schmitt trigger action at all inputs improves
noise immunity and makes the circuit tolerant to slower input rise and fall times
across the entire range of supply voltage.
Construction
The AUP family devices are built in CMOS035 technology with a gate length of
350 nm. The process technology is Pb-free, RoHS and Dark Green compliant. Bond
wiring is done with copper.
212
9
Logic Families
The AUP family devices are built with overvoltage tolerant input stages (3.6 V) and
allows a supply range of 0.8 V to 3.6 V.
All configurable logic devices have Schmitt trigger inputs with ~400 mV Hysteresis
@VCC = 1.2 V. Some Buffer, Inverter and NAND gate types have Schmitt-trigger
inputs as well. All other devices have Schmitt-trigger actions, which causes a smaller
hysteresis of about 60 mV @VCC = 1.2 V. The hysteresis leads to a higher noise
immunity.
floating.
Input figures
There are two types of input circuits in the AUP family.
Schmitt-trigger action input — This input has a small amount of hysteresis built

into the input switching levels. The hysteresis is not formally specified but it does
allow the input to be tolerant to input slew rates as high as 20 ns/V at VCC = 1.65 V
to 2.7 V and 10 ns/V at VCC = 2.7 V to 5.5 V. The Schmitt-trigger action input may be
preceded by a bus-hold cell to define unused inputs. This bus-hold cell does not
affect the performance of the device.
Schmitt-trigger input — This input has much higher input hysteresis which is

formally specified in the datasheet. The advantage of true Schmitt-trigger inputs is
that they are tolerant to very slow edges.
The following figures show a side by side comparison of the IV characteristics of the
Schmitt-trigger action input and the Schmitt-trigger input.
aaa-007368
aaa-007358
10 40
ICC (µA)
ICC (µA)
Schmitt action input Schmitt trigger input

VCC = 1.2 V VCC = 1.2 V
5 20
0 0
0 0.5 1.0 1.5 VI (V) 0 0.5 1.0 1.5 VI (V)
213
Logic Families
aaa-007369
aaa-007359
ICC (µA) 40 160
ICC (µA)
VCC = 1.5 V VCC = 1.5 V
20 80
0 0
0 0.5 1.0 1.5 VI (V) 0 0.5 1.0 1.5 VI (V)

aaa-007370
aaa-007360
160 280
ICC (µA)
ICC (µA)
VCC = 1.8 V VCC = 1.8 V
80 140
0 0
0 0.5 1.0 1.5 2.0 VI (V) 0 0.5 1.0 1.5 2.0 VI (V)

aaa-007371
0.6 0.8
aaa-007361
ICC (mA)
ICC (mA)

VCC = 2.5 V VCC = 2.5 V
0.3 0.4
0 0
0 0.5 1.0 1.5 2.0 2.5 VI (V) 0 0.5 1.0 1.5 2.0 2.5 VI (V)
214
9
Logic Families
aaa-007372
aaa-007362
1.2 1.4
ICC (mA)
ICC (mA)
VCC = 3.3 V VCC = 3.3 V
0.6 0.7
0 0
0 1.0 2.0 3.0 4.0 VI (V) 0 1.0 2.0 3.0 4.0 VI (V)
Output figures
An AUP device provides a balanced 1.9 mA output drive at VCC = 1.8 V. The following
table of output figures shows the measured output characteristics of the AUP
family devices for 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V.
aaa-007338
aaa-007339
6 6
IOL (mA)
IOH (mA)

VCC = 1.2 V VCC = 1.2 V
3 -3
25°C 25°C
25°C min 25°C min
85°C min 85°C min
0 -6
0 0.5 1.0 1.5 VO (V) 0 0.5 1.0 1.5 VO (V)
215
Logic Families
aaa-007340
aaa-007341
10 0
IOL (mA)
IOH (mA)
VCC = 1.5 V VCC = 1.5 V
5 -5
25°C 25°C
25°C min 25°C min
85°C min 85°C min
0 -10
0 0.5 1.0 1.5 VO (V) 0 0.5 1.0 1.5 VO (V)

aaa-007342
aaa-007343
16 0
IOL (mA)
IOH (mA)
VCC = 1.8 V VCC = 1.8 V
8 -8
25°C 25°C
25°C min 25°C min
85°C min 85°C min
0 -16
0 0.5 1.0 1.5 2.0 VO (V) 0 0.5 1.0 1.5 2.0 VO (V)

aaa-007344
28 0
aaa-007345
IOL (mA)
IOH (mA)

VCC = 2.5 V VCC = 2.5 V
14 -14
25°C 25°C
25°C min 25°C min
85°C min 85°C min
0 -28
0 0.5 1.0 1.5 2.0 2.5 VO (V) 0 0.5 1.0 1.5 2.0 2.5 VO (V)
216
9
Logic Families
aaa-007346
aaa-007347
40 0
IOL (mA)
IOH (mA)
VCC = 3.3 V VCC = 3.3 V
20 -20
25°C 25°C
25°C min 25°C min
85°C min 85°C min
0 -40
0 1 2 3 4 VO (V) 0 1 2 3 4 VO (V)


IIK input clamping current −0,5 +4,6 V
VI input voltage Active mode and
−0,5 +4,6 V
Power-down mode
IOK output clamping current VI < 0 V −50 – mA
VO output voltage VO < 0 V −50 – mA
Ptot total power dissipation Tamb = −40 °C to +125 °C – 250 mW
217

Logic Families

Power-down mode;
0 3,6 V
VCC = 0 V
∆t/∆V input transition rise and VCC = 0.8 to 3.6 V
– 200 ns/V
fall rate
Tamb Tamb
Tamb
Conditions
Parameter
−40 °C to −40 °C to
25 °C
+85 °C +125 °C
Symbol
Unit
Min Typ Max Min Max Min Max
VIH HIGH-level VCC = 0.8 V 0.70 × 0.70 × 0.75 ×

– – – – V
input VCC VCC VCC
voltage VCC = 0.65 × 0.65 × 0.70 ×
– – – – V
0.9 to 1.95 V VCC VCC VCC
VCC =
1,6 – – 1,6 – 1,6 – V
2.3 to 2.7 V
VCC =
2,0 – – 2,0 – 2,0 – V
3.0 to 3.6 V
VIL LOW-level VCC = 0.8 V 0.30 × 0.30 × 0.25 ×
– – – – V
input VCC VCC VCC
voltage VCC = 0.35 × 0.35 × 0.30 ×
– – – – V
0.9 to 1.95 V VCC VCC VCC
VCC =
– – 0,7 – 0,7 – 0,7 V
2.3 to 2.7 V
VCC =
– – 0,9 – 0,9 – 0,9 V
3.0 to 3.6 V
218
9
Logic Families
Tamb Tamb
Tamb
Conditions
Parameter
−40 °C to −40 °C to
25 °C
+85 °C +125 °C
Symbol
Unit

output IO = −20 μA;
voltage VCC − VCC − VCC −
VCC = – – – – V
0.1 0.1 0.11
0.8 to 3.6 V
IO = −1.1 mA; 0.75 × 0.7 × 0.6 ×
– – – – V
VCC = 1.1 V VCC VCC VCC
IO = −1.7 mA;
1,11 – – 1,03 – 0,93 – V
VCC = 1.4 V
IO = −1.9 mA;
1,32 – – 1,30 – 1,17 – V
VCC = 1.65 V
IO = −2.3 mA;
2,05 – – 1,97 – 1,77 – V
VCC = 2.3 V
IO = −3.1 mA;
1,9 – – 1,85 – 1,67 – V
VCC = 2.3 V
IO = −2.7 mA;
2,72 – – 2,67 – 2,40 – V
VCC = 3.0 V
IO = −4.0 mA;
2,6 – – 2,55 – 2,30 – V
VCC = 3.0 V
output IO = 20 μA;
voltage VCC = – – 0,1 – 0,1 – 0,11 V
0.8 to 3.6 V
IO = 1.1 mA; 0.3 × 0.3 × 0.33 ×
– – – – V
VCC = 1.1 V VCC VCC VCC
IO = 1.7 mA;
– – 0,31 – 0,37 – 0,41 V
VCC = 1.4 V
IO = 1.9 mA;
– – 0,31 – 0,35 – 0,39 V
VCC = 1.65 V
IO = 2.3 mA;
– – 0,31 – 0,33 – 0,36 V
VCC = 2.3 V
IO = 3.1 mA;
– – 0,44 – 0,45 – 0,50 V
VCC = 2.3 V
IO = 2.7 mA;
– – 0,31 – 0,33 – 0,36 V
VCC = 3.0 V
IO = 4.0 mA;
– – 0,44 – 0,45 – 0,50 V
VCC = 3.0 V
219
Logic Families
Tamb Tamb
Tamb
Conditions
Parameter
−40 °C to −40 °C to
25 °C
+85 °C +125 °C
Symbol
Unit
II input VI = GND to
leakage 3.6 V; VCC = 0 – – ±0.1 – ±0.5 – ±0.75 μA
current to 3.6 V
IOFF power-off VI or VO =
leakage 0 to 3.6 V; – – ±0.2 – ±0.5 – ±0.75 μA
current VCC = 0 V
ΔIOFF additional VI or VO = 0
power-off to 3.6 V;
– – ±0.2 – ±0.6 – ±0.75 μA
leakage VCC = 0 to
current 0.2 V
ICC supply VI = GND or
current VCC; IO = 0 A;
– – 0,5 – 0,9 – 1,4 μA
VCC = 0.8 to
3.6 V
ΔICC additional VI = VCC −
supply 0.6 V; IO = 0 A;
– – 40 – 50 – 75 mA
current VCC = 3.3 V;
per pin [1]
[1] One input at VCC − 0.6 V, other input at VCC or GND.
Tamb Tamb
Tamb
Conditions
Parameter
−40 °C to −40 °C to
25 °C
+85 °C +125 °C
Symbol
Unit
Min Typ* Max Min Max Min Max
CL = 5 pF
delay VCC = 0.8 V – 25,4 – – – – – ns
VCC = 1.1 to 1.3 V 2,9 6,7 14,0 2,6 14,2 2,6 14,2 ns
VCC = 1.4 to 1.6 V 2,4 4,5 7,6 2,3 8,3 2,3 8,6 ns
VCC = 1.65 to 1.95 V 1,9 3,5 5,7 1,7 6,5 1,7 6,8 ns
VCC = 2.3 to 2.7 V 1,7 2,6 3,8 1,4 4,4 1,4 4,7 ns
VCC = 3.0 to 3.6 V 1,5 2,2 3,1 1,2 3,4 1,2 3,7 ns
220
9
Logic Families
Tamb Tamb
Tamb
Conditions
Parameter
−40 °C to −40 °C to
25 °C
+85 °C +125 °C
Symbol
Unit
tpd propagation SD to Q, Q; [1]

delay VCC = 0.8 V – 19,6 – – – – – ns
VCC = 1.1 to 1.3 V 2,7 5,6 11,0 2,5 11,4 2,5 11,5 ns
VCC = 1.4 to 1.6 V 2,4 4,0 6,3 2,2 6,9 2,2 7,3 ns
VCC = 1.65 to 1.95 V 2,0 3,3 4,9 1,7 5,6 1,7 5,9 ns
VCC = 2.3 to 2.7 V 1,9 2,7 3,7 1,7 4,0 1,7 4,2 ns
VCC = 3.0 to 3.6 V 1,8 2,5 3,2 1,5 3,6 1,5 3,8 ns
RD to Q, Q; [1]
VCC = 0.8 V – 19,2 – – – – – ns
VCC = 1.1 to 1.3 V 2,6 5,5 11,0 2,5 11,3 2,5 11,5 ns
VCC = 1.4 to 1.6 V 2,3 3,9 6,3 2,2 6,8 2,2 7,3 ns
VCC = 1.65 to 1.95 V 1,9 3,2 5,0 1,8 5,6 1,8 5,9 ns
VCC = 2.3 to 2.7 V 1,9 2,6 3,6 1,7 4,1 1,7 4,3 ns
VCC = 3.0 to 3.6 V 1,8 2,4 3,3 1,5 3,6 1,5 3,8 ns
fmax maximum CP
frequency VCC = 0.8 V – 53 – – – – – MHz
VCC = 1.1 to 1.3 V – 203 – 170 – 170 – MHz
VCC = 1.4 to 1.6 V – 347 – 310 – 300 – MHz
VCC = 1.65 to 1.95 V – 435 – 400 – 390 – MHz
VCC = 2.3 to 2.7 V – 550 – 490 – 480 - MHz
VCC = 3.0 to 3.6 V – 619 – 550 – 510 – MHz
CL = 15 pF
delay VCC = 0.8 V – 32,4 – – – – – ns
VCC = 1.1 to 1.3 V 3,5 8,3 17,6 3,3 17,8 3,3 18,0 ns
VCC = 1.4 to 1.6 V 3,2 5,6 9,5 2,8 10,5 2,8 11,1 ns
VCC = 1.65 to 1.95 V 2,7 4,6 7,2 2,5 8,1 2,5 8,6 ns
VCC = 2.3 to 2.7 V 2,4 3,6 5,2 2,2 5,8 2,2 6,2 ns
VCC = 3.0 to 3.6 V 2,2 3,2 4,4 2,0 4,9 2,0 5,2 ns
221
Logic Families
Tamb Tamb
Tamb
Conditions
Parameter
−40 °C to −40 °C to
25 °C
+85 °C +125 °C
Symbol
Unit
tpd propagation SD to Q, Q; [1]

delay VCC = 0.8 V – 26,7 – – – – – ns
VCC = 1.1 to 1.3 V 3,3 7,3 14,7 3,1 15,2 3,1 15,4 ns
VCC = 1.4 to 1.6 V 3,2 5,2 8,3 2,9 9,0 2,9 9,5 ns
VCC = 1.65 to 1.95 V 2,8 4,3 6,4 2,5 7,1 2,5 7,5 ns
VCC = 2.3 to 2.7 V 2,8 3,7 5,1 2,2 5,5 2,2 5,8 ns
VCC = 3.0 to 3.6 V 2,5 3,5 4,6 2,4 5,0 2,4 5,2 ns
RD to Q, Q; [1]
VCC = 0.8 V – 26,1 – – – – – ns
VCC = 1.1 to 1.3 V 3,2 7,2 14,5 3,1 15,0 3,1 15,2 ns
VCC = 1.4 to 1.6 V 3,1 5,1 8,4 2,7 9,2 2,7 9,7 ns
VCC = 1.65 to 1.95 V 2,7 4,3 6,5 2,6 7,3 2,6 7,7 ns
VCC = 2.3 to 2.7 V 2,6 3,6 5,0 2,4 5,5 2,4 5,8 ns
VCC = 3.0 to 3.6 V 2,4 3,4 4,6 2,3 5,0 2,3 5,2 ns
fmax maximum CP
frequency VCC = 0.8 V – 50 – – – – – MHz
VCC = 1.1 to 1.3 V – 181 – 120 – 120 – MHz
VCC = 1.4 to 1.6 V – 301 – 190 – 160 – MHz
VCC = 1.65 to 1.95 V – 407 – 240 – 190 – MHz
VCC = 2.3 to 2.7 V – 422 – 300 – 270 – MHz
VCC = 3.0 to 3.6 V – 481 – 320 – 300 – MHz
CL = 5 pF, 10 pF, 15 pF and 30 pF
tW pulse width CP HIGH or LOW
VCC = 1.1 to 1.3 V – 2,1 – 2,7 – 2,7 – ns
VCC = 1.4 to 1.6 V – 1,1 – 1,5 – 1,5 – ns
VCC = 1.65 to 1.95 V – 0,9 – 1,6 – 1,6 – ns
VCC = 2.3 to 2.7 V – 0,6 – 1,7 – 1,7 – ns
VCC = 3.0 to 3.6 V – 0,6 – 1,9 – 1,9 – ns
222
9
Logic Families
Tamb Tamb
Tamb
Conditions
Parameter
−40 °C to −40 °C to
25 °C
+85 °C +125 °C
Symbol
Unit
tW pulse width SD or RD LOW

VCC = 1.1 to 1.3 V – 4,2 – 11,3 – 11,5 – ns
VCC = 1.4 to 1.6 V – 2,3 – 6,2 – 6,4 – ns
VCC = 1.65 to 1.95 V – 1,8 – 4,8 – 5,0 – ns
VCC = 2.3 to 2.7 V – 1,2 – 3,3 – 3,5 – ns
VCC = 3.0 to 3.6 V – 1,1 – 2,6 – 2,8 – ns
tsu set-up time D to CP HIGH
VCC = 0.8 V – 3,4 – – – – – ns
VCC = 1.1 to 1.3 V – 0,6 – 1,2 – 1,2 – ns
VCC = 1.4 to 1.6 V – 0,3 – 0,6 – 0,6 – ns
VCC = 1.65 to 1.95 V – 0,4 – 0,5 – 0,5 – ns
VCC = 2.3 to 2.7 V – 0,2 – 0,4 – 0,4 – ns
VCC = 3.0 to 3.6 V – 0,3 – 0,4 – 0,4 – ns
D to CP LOW
VCC = 0.8 V – 3,0 – – – – – ns
VCC = 1.1 to 1.3 V – 0,5 – 1,2 – 1,2 – ns
VCC = 1.4 to 1.6 V – 0,3 – 0,7 – 0,7 – ns
VCC = 1.65 to 1.95 V – 0,4 – 0,7 – 0,7 – ns
VCC = 2.3 to 2.7 V – 0,5 – 0,7 – 0,7 – ns
VCC = 3.0 to 3.6 V – 0,6 – 0,8 – 0,8 – ns
th hold time D to CP
VCC = 0.8 V – −1,9 – – – – – ns
VCC = 1.1 to 1.3 V – −0,3 – 0,5 – 0,5 – ns
VCC = 1.4 to 1.6 V – −0,2 – 0,2 – 0,2 – ns
VCC = 1.65 to 1.95 V – −0,2 – 0,1 – 0,1 – ns
VCC = 2.3 to 2.7 V – −0,2 – 0,1 – 0,1 – ns
VCC = 3.0 to 3.6 V – −0,2 – 0,1 – 0,1 – ns
223
Logic Families
Tamb Tamb
Tamb
Conditions
Parameter
−40 °C to −40 °C to
25 °C
+85 °C +125 °C
Symbol
Unit
trec recovery RD
time VCC = 1.1 to 1.3 V – −0,5 – -0,9 – −0,9 – ns
VCC = 1.4 to 1.6 V – −0,2 – -0,6 – −0,6 – ns
VCC = 1.65 to 1.95 V – −0,2 – -0,4 – −0,4 – ns
VCC = 2.3 to 2.7 V – −0,1 – -0,1 – −0,1 – ns
VCC = 3.0 to 3.6 V – −0,1 – -0,1 – −0,1 – ns
SD
VCC = 1.1 to 1.3 V – −0,5 – −0,3 – −0,3 – ns
VCC = 1.4 to 1.6 V – −0,4 – −0,1 – −0,1 – ns
VCC = 1.65 to 1.95 V – −0,3 – 0 – 0 – ns
VCC = 2.3 to 2.7 V – −0,2 – 0,1 – 0,1 – ns
VCC = 3.0 to 3.6 V – −0,1 – 0,1 – 0,1 – ns
CPD power fi = 1 MHz; VI = GND to VCC [2]
dissipation VCC = 0.8 V – 2,8 – – – – – pF
capacitance
VCC = 1.1 to 1.3 V – 2,9 – – – – – pF
VCC = 1.4 to 1.6 V – 3,0 – – – – – pF
VCC = 1.65 to 1.95 V – 3,0 – – – – – pF
VCC = 2.3 to 2.7 V – 3,5 – – – – – pF
VCC = 3.0 to 3.6 V – 3,9 – – – – – pF
* All typical values are measured at nominal VCC.

224
9
1317(10) =
1 * 210 + 0 * 2
Power 9 + 1 * 28 + 0 * 27 + 0 * 26 + 1 * 25 +
calculations
Logic Families
0 * 24 + 0 * 2
The static
3
power + 1 * 22 + 0 * 21 + 1 * 20
1317
current = 10100100101
state,
+ 0011
The1110
Where:

Special Features
AUP devices are fully specified for

partial power-down applications that aaa-032367
use the IOFF feature. The IOFF circuitry 1A

1A 1Y
1Y
disables the output, preventing damage
1
caused by backflow current passing
2A
2A 2Y
2Y
through the device when it is powered
down.
Combination logic offers two or more

unique functions in a single package. Figure 9.7a | Stand-alone combination logic
The functions are either stand alone or
they can be cascaded.
aaa-032367
A
A
Figure 9.7a shows a buffer and inverter B
B
with no internal connection as a
YY
stand-alone example and Figure 9.7b CC
shows the output of an AND gate being
applied to one of the inputs of an OR
Figure 9.7b | Cascaded combination logic
gate as a cascaded example.
225
Combination logic is typically the integration of discrete logic solutions to known

Logic Families
issues on PCB. Solutions based on combination logic have lower total cost,
including pick and place cost, and reduced PCB area. It also helps to optimize and
simplify the PCB layout and signal routing.
An overview of features available for the AUP logic family:
• Low threshold inputs • Open drain outputs

• Schmitt-Trigger/Schmitt Action inputs • Power-off protection (IOFF)
• 3.6 V tolerant I/O’s • Dual supply translations
Summary
Designed for high-performance, low-power applications, these low-voltage, Si-gate

CMOS devices provide logic solutions with very low static and dynamic power
dissipation. Some key features are:
• Very low dynamic power dissipation (CPD)

• tpd of 2.5 ns at VCC of 2.5 V
• Wide supply voltage range (0.8 V to 3.6 V)
• Schmitt-trigger action on all inputs
• Low-threshold input options
• 1.9 mA balanced output drive
• Over-voltage tolerant I/Os
• Fully specified (-40 to +85°C and -40 to +125°C)
• Automotive options (-Q100 suffix)
• Pb-free, RoHS compliant and Dark Green
226
9
9.6 The AXP Logic Family
Logic Families
Introduction to family / support overvoltage-tolerant inputs,
General description Schmitt-trigger inputs, low-threshold
inputs, partial power-down circuitry and
The AXP family of Si-gate CMOS devices
open-drain outputs.
uses low threshold process technology
and next-generation packaging to
Construction
deliver extremely small logic functions.
All AXP solutions offer low propagation The AXP family devices are built in C050
delay and standby current, enabling process with a gate length of 250 nm.
both high-speed and low power This approach results in a typical input
dissipation capacitance Applications. capacitance of 0.5 pF. AXP devices are
modelled as a 0.8 pF capacitance on the
AXP provides higher speed than AUP
input supply (CPDI) and a 7.6 pF
but retains low power dissipation
capacitance on the output supply
capacitance (CPD). Because of its use of
(CPDO). The power consumption
low threshold transistors, AXP is the
capacitance, CPD, is typically at 2.9 pF.
first logic family fully specified at 0.8 V,
The process technology is Pb-free, RoHS
allowing to migrate applications from
and Dark Green compliant. Bond wiring
1.8 V and 1.2 V easily.
is done with copper.
Types released in AXP technology can
The AXP family devices are built with It is recommended to drive all logic
overvoltage tolerant input stages (3.6 V) inputs with a defined value, not to leave
and allows a supply range of 0.7 V to them floating.
2.75 V.
Input Output figures
Input figures
The AXP inputs are fully specified for supply voltage ranges of 2.3–2.7 V, 1.65–
1.95 V, 1.4–1.6 V, 1.1–1.3 V and 0.75–0.85 V. The ESD protection circuit used results
in the input being over voltage tolerant to 2.75 V. This tolerance permits the
application of input signals that exceed the supply voltage. The input options
include Schmitt-trigger inputs and Schmitt-trigger action inputs. Schmitt-trigger
action makes the input tolerant of slower input transition rates. Hysteresis is not
specified, but the input can tolerate input transition rise and fall rates of 200 ns/V.
Schmitt-trigger inputs include an input hysteresis specification and have no
restriction on input transition rates.
227
The following figures show the typical characteristics of

Logic Families
the Schmitt-trigger action input.
aaa-010193
aaa-010192
0.8 280
ICC (µA)
ICC (µA)
0.4 140
0 0
0 0.5 1.0 1.5 2.0 2.5 VI (V) 0 0.5 1.0 1.5 2.0 VI (V)
2.5 V Schmitt action 1.8 V Schmitt action

aaa-010191
aaa-010190
140 60
ICC (µA)
ICC (µA)
70 30
0 0
0 0.5 1.0 1.5 VI (V) 0 0.5 1.0 1.5 VI (V)
1.5 V Schmitt action 1.2 V Schmitt action

aaa-010189
2
ICC (µA)
0
0 0.5 1.0 VI (V)
0.8 V Schmitt action
228
9
The following figures show the typical characteristics of
Logic Families
the Schmitt-trigger input.
aaa-010203
aaa-010202
1.2 500
ICC (µA)
ICC (µA)
0.6 250
0 0
0 0.5 1.0 1.5 2.0 2.5 VI (V) 0 0.5 1.0 1.5 2.0 VI (V)
2.5 V Schmitt trigger 1.8 V Schmitt trigger

aaa-010201
aaa-010200
300 100
ICC (µA)
ICC (µA)
150 50
0 0
0 0.5 1.0 1.5 VI (V) 0 0.5 1.0 1.5 VI (V)
1.5 V Schmitt trigger 1.2 V Schmitt trigger

aaa-010199
3
ICC (µA)
0
0 0.5 1.0 VI (V)
0.8 V Schmitt trigger
229
Output figures
Logic Families
The output is fully specified for supply voltage ranges of 4.5–5.5 V, 3.0–3.6 V,
2.3–2.7 V, 1.65–1.95 V and 1.4–1.6 V. To support partial power down mode, the
output features IOFF, which ensures there is no current leakage path through the
outputs when the device supply voltage is set to 0 V.
140
140 00
aaa-021850
aaa-021850
OL (mA)
OH (mA)
IOL
IOH
70
70 -70
-70
25°C
25°C typ
typ 25°C
25°C typ
typ
25°C
25°C min
min 25°C
25°C min
min
85°C
85°C min
min 85°C
85°C min
min
00 -140
-140
00 1.0
1.0 2.0
2.0 3.0
3.0 4.0
4.0 5.0 V
5.0 VOO(V)
(V) 00 1.0
1.0 2.0
2.0 3.0
3.0 4.0
4.0 5.0 V
5.0 VOO(V)
(V)
80
80 00
aaa-021849
aaa-021849
OL (mA)
OH (mA)
IOL
IOH
40
40 -40
-40
25°C
25°C typ
typ 25°C
25°C typ
typ
25°C
25°C min
min 25°C
25°C min
min
85°C
85°C min
min 85°C
85°C min
min
00 -80
-80
00 0.5
0.5 1.0
1.0 1.5
1.5 2.0
2.0 2.5
2.5 3.0
3.0 3.5 V
3.5 VOO(V)
(V) 00 1.0
1.0 2.0
2.0 3.0
3.0 4.0 V
4.0 VOO(V)
(V)
230
9
Logic Families
48
48 00
aaa-021848
aaa-021848
OL (mA)
OH (mA)
IOL
IOH
24
24 -24
-24
25°C
25°C typ
typ 25°C
25°C typ
typ
25°C
25°C min
min 25°C
25°C min
min
85°C
85°C min
min 85°C
85°C min
min
00 -48
-48
00 0.5
0.5 1.0
1.0 1.5
1.5 2.0
2.0 2.5 V
2.5 VOO(V)
(V) 00 0.5
0.5 1.0
1.0 1.5
1.5 2.0
2.0 2.5 V
2.5 VOO(V)
(V)
24
24 00
aaa-021847
aaa-021847
OL (mA)
OH (mA)
IOL
IOH
12
12 -12
-12
25°C
25°C typ
typ 25°C
25°C typ
typ
25°C
25°C min
min 25°C
25°C min
min
85°C
85°C min
min 85°C
85°C min
min
00 -24
-24
00 0.5
0.5 1.0
1.0 1.5
1.5 2.0 V
2.0 VOO(V)
(V) 00 0.5
0.5 1.0
1.0 1.5
1.5 2.0 V
2.0 VOO(V)
(V)
14
14 00
aaa-021846
aaa-021846
OL (mA)
OH (mA)
IOL
IOH
77 -7
-7
25°C
25°C typ
typ 25°C
25°C typ
typ
25°C
25°C min
min 25°C
25°C min
min
85°C
85°C min
min 85°C
85°C min
min
00 -14
-14
00 0.5
0.5 1.0
1.0 1.5 V
1.5 VOO(V)
(V) 00 0.5
0.5 1.0
1.0 1.5 V
1.5 VOO(V)
(V)
231
Logic Families
66 00
aaa-021845
aaa-021845
OL (mA)
OH (mA)
IOL
IOH
33 -3
-3
25°C
25°C typ
typ 25°C
25°C typ
typ
25°C
25°C min
min 25°C
25°C min
min
85°C
85°C min
min 85°C
85°C min
min
00 -6
-6
00 0.5
0.5 1.0
1.0 1.5 V
1.5 VOO(V)
(V) 00 0.5
0.5 1.0
1.0 1.5 V
1.5 VOO(V)
(V)


VO output voltage * −0,5 +3,3 V
Ptot total power dissipation Tamb = −40 °C to +85 °C – 250 mW
* The minimum input and output voltage ratings may be exceeded if the input and output current
ratings are observed.
232
9
Logic Families

Power-down mode;
0 2,75 V
VCC = 0 V
∆t/∆V input transition rise and VCC = 0.7 V to 2.75 V
0 200 ns/V
fall rate

At recommended operating conditions, unless otherwise specified;
voltages are referenced to GND (ground = 0 V).
Tamb Tamb
Conditions
Parameter
25 °C −40 °C to +85 °C

Symbol
Unit
VIH HIGH-level VCC =

0.75 VCC – – 0.75 VCC – V
input 0.75 to 0.85 V
voltage
VCC =
0.65 VCC – – 0.65 VCC – V
1.1 to 1.95 V
VCC =
1,6 – – 1,6 – V
2.3 to 2.7 V
VIL LOW-level VCC =
– – 0.25 VCC – 0.25 VCC V
input 0.75 to 0.85 V
voltage
VCC =
– – 0.35 VCC – 0.35 VCC V
1.1 to 1.95 V
VCC =
– – 0,7 – 0,7 V
2.3 to 2.7 V
233
Logic Families
Tamb Tamb
Conditions
Parameter
25 °C −40 °C to +85 °C
Symbol
Unit
VOH HIGH-level IO = -20 μA;

– 0,69 – – – V
output VCC = 0.7 V
voltage
IO = -100 μA;
0,65 – – 0,65 – V
VCC = 0.75 V
IO = -2 mA;
0,825 – – 0,825 – V
VCC = 1.1 V
IO = -3 mA;
1,05 – – 1,05 – V
VCC = 1.4 V
IO = -4.5 mA;
1,2 – – 1,2 – V
VCC = 1.65 V
IO = -8 mA;
1,7 – – 1,7 – V
VCC = 2.3 V
VOL LOW-level IO = 20 μA;
– 0,01 – – – V
output VCC = 0.7 V
voltage
IO = 100 μA;
– – 0,1 – 0,1 V
VCC = 0.75 V
IO = 2 mA;
– – 0,275 – 0,275 V
VCC = 1.1 V
IO = 3 mA;
– – 0,35 – 0,35 V
VCC = 1.4 V
IO = 4.5 mA;
– – 0,45 – 0,45 V
VCC = 1.65 V
IO = 8 mA;
– – 0,7 – 0,7 V
VCC = 2.3 V
II input VI = 0 to 2.75 V;
leakage VCC = 0 to – 0,001 ±0.1 – ±0.5 μA
current 2.75 V [1]
IOFF power-off VI or VO =
leakage 0 to 2.75 V; – 0,01 ±0.1 – ±0.5 μA
current VCC = 0 V [1]
ΔIOFF additional VI or VO =
power- off 0 V or 2.75 V;
– 0,02 ±0.1 – ±0.5 μA
leakage VCC = 0 to 0.1 V
current [1]
ICC supply VI = 0 V or VCC;
– 0,01 0,3 – 0,6 μA
current IO = 0 A [1]
234
9
Logic Families
Tamb Tamb
Conditions
Parameter
25 °C −40 °C to +85 °C
Symbol
Unit
ΔICC additional VI = VCC − 0.5 V;

supply IO = 0 A; – 2 100 – 150 μA
current VCC = 2.5 V
[1] Typical values are measured at VCC = 1.2 V.

Voltages are referenced to GND (ground = 0 V)
Tamb
Tamb
Conditions
Parameter
−40 °C to
25 °C
+85 °C
Symbol
Unit
tpd propagation A to Y [1]

delay
VCC = 0.75 to 0.85 V 3 11 33 2 100 ns
VCC = 1.1 to 1.3 V 1,8 4,3 7,0 1,7 7,3 ns
VCC = 1.4 to 1.6 V 1,5 3,1 4,7 1,3 5,1 ns
VCC = 1.65 to 1.95 V 1,2 2,6 3,8 1,1 4,1 ns
VCC = 2.3 to 2.7 V 1,0 2,0 2,8 0,9 3,1 ns
tt transition time VCC = 2.7 V [2] – – – 1,0 – ns
CI input VI = 0 V or VCC;
– 0,5 – – – pF
capacitance VCC = 0 to 2.75 V
CO output VO = 0 V;
– 1,0 – – – pF
capacitance VCC = 0 V
CPD power fi = 1 MHz; VI = 0 V to VCC [3]
dissipation
VCC = 0.75 to 0.85 V – 2,3 – – – pF
capacitance
VCC = 1.1 to 1.3 V – 2,3 – – – pF
VCC = 1.4 to 1.6 V – 2,4 – – – pF
VCC = 1.65 to 1.95 V – 2,4 – – – pF
VCC = 2.3 to 2.7 V – 2,7 – – – pF
* All typical values are measured at nominal VCC.

[2] tt is the same as tTHL and tTLH.
235
1317(10) =
1 * 210 + 0 * 2
Power 9 + 1 * 28 + 0 * 27 + 0 * 26 + 1 * 25 +
calculations
Logic Families
0 * 24 + 0 * 2
The static
3
power + 1 * 22 + 0 * 21 + 1 * 20
1317
current = 10100100101
state,
+ 0011
The1110
Where:

Special Features
• Wide supply voltage range and fully specified at 0.8 V

• Very low dynamic power dissipation & standby current (0.6 μA)
• Typical 2.9 ns low propagation delay at VCC of 1.8 V
• Schmitt action on all inputs & overvoltage tolerant inputs
1
• ±4.5 mA balanced output drive
Summary
Designed for high-performance, low-power applications, these low-voltage, Si-gate

CMOS devices provide logic solutions with very low static and dynamic power
dissipation.
236
9
9.7 The LVT/ALVT Logic Family
Logic Families
Nexperia has two low voltage families optimized for backplane driving applications:
LVT (Low Voltage Technology) and ALVT (Advanced LVT). The purpose of this note
is to provide better insight into both families for optimal use by designers in their
applications.
ALVT family devices are intended primarily for fast low voltage bus driver
applications, especially driving low bus impedances such as backplanes. For this
range of applications, a number of parameters are important such as operating
voltage range, propagation delay, drive capability and power. Other important
factors, discussed below, are power-up/down characteristics, 5 Volt input and
output capability, bus hold and ground bounce.
Construction
Both families are fabricated using QUBiC, an advanced BiCMOS process, where the
best properties of bipolar transistors (fT = 17 GHz) are combined with optimized
CMOS (0.65–0.8 micron). In addition, special components can be built in such as
Schottky diodes and zener diodes for specific requirements. QUBiC processing
enables short propagation delay times combined with low power dissipation, low
noise and high output drive. The process also allows low temperature dependency
of AC and DC characteristics.
Due to the trade-off between speed and ground bounce, ALVT focuses on bus-wide
devices with multiple GND and VCC pins (flow-through architecture). ALVT devices
have versions with built-in damping resistors (for example, ’2244 or ’162244) to
minimize undershoot, especially for driving memory busses.
ALVT is different from LVT in two ways. First ALVT is fully specified at VCC = 2.5 V,
and second, it is about 40% faster than LVT. Due to the trade-off between speed
and ground bounce, ALVT focuses on bus-wide devices with multiple GND and VCC
pins (flow-through architecture). Having the same speed in a standard pin 8 bit
device would require the speed to be tuned down to a level comparable to LVT. As
a result, LVT has a much wider product portfolio with a variety of 8 to 10-bit bus
functions and also some very fast, lower drive gates and flip-flops. Both families
have versions with built-in damping resistors (for example, ’2244 or ’162244) to
minimize undershoot, especially for driving memory busses.
237

Logic Families
Figure 9.8 gives a simplified version of the internal buffer circuit, with the output
enable function (OE) and other details (some of which will be discussed later)
omitted. Its purpose is to show the basic aspects of the internal circuit so that
applying LVT circuits is made easier and certain aspects of the datasheet are
clarified. The input uses a small CMOS inverter stage with a low input capacitance,
so no drive energy is needed. The output LOW is bipolar (Q4) with a small (M7) in
parallel, and the output HIGH is a combination of a bipolar transistor (Q2) and
PMOS (M4) to pull the output to the full VCC. Bipolar transistors introduce less
bounce than pure CMOS. The NMOS M7 is very small and therefore does not affect
ground bounce. The PMOS transistor M4 is delayed via the inverters INV1/INV2 so
that it becomes active somewhat later than Q2 with only a minimal effect on VCC
bounce. This construction enables the best possible trade-off between speed and
bounce.
aaa-032311
VCC
M1 D1
Q1
M2 Q2
M3
IN
M4
INV1 INV2
OUT
VCC
ONE REF
M5 COMP
SHOT M6
R1 R2 R3
Q3
D2 D3
Q4
M7
Figure 9.8 | Simplified ALVT circuit
238
9
The drive of Q2 in the active HIGH state, taken care of by M1, M2 and Q1, is
Logic Families
standard for advanced BiCMOS and makes optimum use of MOS and bipolar
transistors to get the fastest, lowest internal capacitance inverter. M3 ensures a
fast turn-off of Q2 when the output goes LOW or into 3-state. When the output is
forced LOW, a ‘power-on-demand’ circuit is activated. A one shot delivers Q4 with a
high base current (via M5, R1 and Q3), which will quickly pull the output low.
Additional base current is provided via M6/R2 and R3. The path M6/R2 is connected
to the output voltage via a very fast comparator. When the output drops lower
than approximately 1 V, the current path via M6/R2 is blocked. The diodes D2/D3
prevent deep saturation of Q4 to enable quick turn-off.
This, at first sight, rather complex circuit ensures a very fast transition to around
1 V, and below that value the output voltage smooths out somewhat so that the
amount of ringing generated is kept to a minimum. Also, when the output is active
LOW, a very low current is drained from the supply voltage. When a glitch appears
on the output trying to pull the output HIGH, the diodes D2/D3 stop conducting,
providing base current into Q3/Q4 so that the bus is pulled LOW again. This
structure provides an excellent dynamic behavior, little ringing and good glitch
suppression combined with low power dissipation. When the output is in 3-state or
active HIGH, only a small bias current flows (for the power-up/down circuit
discussed in Section 3.1) while in the active LOW state some current flows via R3,
which may vary somewhat among part types. Therefore ICCH and ICCZ are low, while
ICCL is somewhat higher.
floating.
239
Input and Output figures

Logic Families
Input Figures for ALVT
Idd (A) Idd (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VIN (V) VIN (V)
ALVT input curves at 2V7 ALVT Schmitt-Trigger input curves at 2V7
Idd (A) Idd (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VIN (V) VIN (V)
ALVT input curves at 3V3 ALVT Schmitt-Trigger input curves at 3V3
240
9
Input Figures for LVT
Logic Families
Idd (A) Idd (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VIN (V) VIN (V)
LVT input curves at 2V7 LVT Schmitt-Trigger input curves at 2V7
Idd (A) Idd (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VIN (V) VIN (V)
LVT input curves at 3V3 LVT Schmitt-Trigger input curves at 3V3
241
Output figures for ALVT

Logic Families
IOL (A) IOL (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VOUT (V) VOUT (V)
ALVT output curves at 2V7 ALVT output curves at 3V3
IOH (A) IOH (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VOUT (V) VOUT (V)
ALVT output curves at 2V7 ALVT output curves at 3V3
242
9
Output figures for LVT
Logic Families
IOL (A) IOL (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VOUT (V) VOUT (V)
LVT output curves at 2V7 LVT output curves at 3V3
IOH (A) IOH (A)
25°C typ 25°C typ

25°C min 25°C min
85°C min 85°C min
VOUT (V) VOUT (V)
LVT output curves at 2V7 LVT output curves at 3V3
243
Operating Conditions of ALVT

Logic Families


VO output voltage output in OFF-state or
−0,5 +7,0 V
HIGH-state *
IIK input clamping current VI < 0 V – −50 mA
IOK output clamping current VO < 0 V – −50 mA
IO output current output in LOW-state – 128 mA
output in HIGH-state – −64 mA
Tstg junction temperature −65 +150 °C
Tj storage temperature ** – 150 °C
* The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
** The performance capability of a high-performance integrated circuit in conjunction with its
thermal environment can create junction temperatures which are detrimental to reliability.

Conditions
VCC = VCC =
Parameter
2.5 V ± 0.2 V 3.3 V ± 0.3 V
Symbol
Min Max Min Max Unit
VCC supply voltage 2,3 2,7 3,0 3,6 V

VI input voltage 0 5,5 0 5,5 V
IOH HIGH-level output
– -8 – −12 mA
current
IOL LOW-level output
none – 12 – 12 mA
current
Δt/ΔV input transition rise
outputs enabled – 10 – 10 ns/V
and fall rate
Tamb ambient temperature free-air −40 +85 −40 +85 °C
244
9
Logic Families
Symbol Parameter Conditions Min Typ* Max Unit
VCC = 2.5 V ± 0.2 V
VIK input clamping VCC = 2.3 V; IIK = −18 mA
– −0,85 −1,2 V
voltage
1,7 – – V
voltage
VIL LOW-level input
– – 0,7 V
voltage
VOH HIGH-level VCC = 2.3 to 3.6 V; VCC −
VCC – V
output voltage IO = -100 μA 0.2
VCC = 2.3 V; IO = -8 mA 1,8 2,1 – V
VOL LOW-level VCC = 2.3 V; IO = 100 μA – 0,07 0,2 V
output voltage
VCC = 2.3 V; IO = 24 mA – 0,3 0,5 V
VCC = 2.3 V; IO = 8 mA – – 0,4 V
VOL(pu) power-up VCC = 2.7 V; IO = 1 mA;
LOW-level VI = VCC or GND [1] – – 0,55 V
output voltage
II input leakage all input pins
current
VCC = 0 V or 2.7 V; VI = 5.5 V
– 0,1 10 μA
[2]
control pins
VCC = 2.7 V; VI = VCC or GND – 0,1 ±1 μA
data pins; [2]
VCC = 2.7 V; VI = VCC – 0,1 1 μA
VCC = 2.7 V; VI = 0 V – 0,1 −5 μA
IOFF power-off VCC = 0 V; VI or VO = 0 to
– 0,1 ±100 μA
leakage current 4.5 V
IBHL bus hold LOW data inputs; VCC = 2.3 V;
- 90 – μA
current VI = 0.7 V
IBHH bus hold HIGH data inputs; VCC = 2.3 V;
- −10 – μA
current VI = 1.7 V
IEX external current output in HIGH-state when
VO > VCC; VO = 5.5 V; – 10 125 μA
VCC = 2.3 V
245
Logic Families
IO(pu/pd) power-up/ VCC ≤ 1.2 V; VO = 0.5 V to

power-down VCC;
– 1 ±100 μA
output current VI = GND or VCC;
nOE = don’t care [3]
IOZ OFF-state VCC = 2.7 V; VI = VIL or VIH
output current
output HIGH-state;
– 0,5 5 μA
VO = 2.3 V
output LOW-state;
– 0,5 −5 μA
VO = 0.5 V
ICC supply current VCC = 2.7 V; VI = GND or VCC; IO = 0 A
outputs HIGH-state – 0,04 0,1 mA
outputs LOW-state – 2,3 4,5 mA
outputs disabled [4] 0,04 0,1 mA
ΔICC additional per input pin; VCC = 2.3 to
supply current 2.7 V; one input at
– 0,04 0,4 mA
VCC − 0.6 V; other inputs at
VCC or GND [5]
CI input capacitan- VI = 0 V or VCC
– 3 – pF
ce
CO output VO = 0 V or VCC
– 9 – pF
capacitance
VCC = 3.3 V ± 0.3 V
– −0,85 −1,2 V
voltage
2,0 – – V
voltage
VIL LOW-level input
– – 0,8 V
voltage
VOH HIGH-level VCC = 3.0 to 3.6 V; VCC −
VCC – V
output voltage IO = −100 μA 0.2
VCC = 3.0 V; IO = −32 mA 2,0 2,3 – V
VOL LOW-level VCC = 3.0 V
output voltage
IO = 100 μA – 0,07 0,2 V
IO = 16 mA – 0,25 0,4 V
IO = 32 mA – 0,3 0,5 V
IO = 64 mA – 0,4 0,55 V
246
9
Logic Families

LOW-level VI = VCC or GND [1] – – 0,55 V
output voltage
II input leakage all input pins;
current
VCC = 0 V or 3.6 V; VI = 5.5 V – 0,1 10 μA
control pins
data pins; [2]
VCC = 3.6 V; VI = VCC – 0,5 1 μA
VCC = 3.6 V; VI = 0 V – 0,1 −5 μA
IOFF power-off VCC = 0 V; VI or VO = 0 to
– 0,1 ±100 μA
leakage current 4.5 V
IBHL bus hold LOW data inputs; VCC = 3 V;
75 130 – μA
current VI = 0.8 V
IBHH bus hold HIGH data inputs; VCC = 3 V;
−75 -140 – μA
current VI = 2.0 V
IBHLO bus hold LOW data inputs; VCC = 3.6 V;
overdrive VI = 0 to 3.6 V [6] 500 – – μA
current
IBHHO bus hold HIGH data inputs; VCC = 3.6 V;
overdrive VI = 0 to 3.6 V [6] −500 – – μA
current
IEX external current output in HIGH-state when
VO > VCC; VO = 5.5 V; – 10 125 μA
VCC = 3.0 V
IO(pu/pd) power-up/ VCC ≤ 1.2 V; VO = 0.5 V to
power-down VCC;
– 1 ±100 μA
output current VI = GND or VCC;
nOE = don’t care [7]
IOZ OFF-state VCC = 3.6 V; VI = VIL or VIH
output current
output HIGH-state;
– 0,5 5 μA
VO = 3.0 V
output LOW-state;
– 0,5 -5 μA
VO = 0.5 V
247
Logic Families

outputs HIGH-state – 0,07 0,1 mA
outputs LOW-state – 5,1 7 mA
outputs disabled [4] – 0,07 0,1 mA
ΔICC additional per input pin; VCC = 3 to
supply current 3.6 V;
one input at VCC − 0.6 V; – 0,04 0,4 mA
other inputs at VCC or GND
[5]
CI input capacitan- VI = 0 V or VCC
– 3 – pF
ce
CO output VO = 0 V or VCC
– 9 – pF
capacitance
* All typical values for VCC = 2.5 V ± 0.2 V are measured at VCC = 2.5 V and Tamb = 25 °C.
All typical values for VCC = 3.3 V ± 0.3 V are measured at VCC = 3.3 V and Tamb = 25 °C.
[1] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
[2] Unused pins at VCC or GND.
[3] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms.
From VCC = 1.2 V to (2.5 ± 0.2) V a transition time of 100 μs is permitted. This parameter is valid for
Tamb = 25 °C only.
[4] ICC with outputs disabled is measured with outputs pulled to VCC or GND.
[5] This is the increase in supply current for each input at the specified voltage level other than VCC or
GND.
[6] This is the bus hold overdrive current required to force the input to the opposite logic state.
From VCC = 1,2 V to (3.3 ± 0.3) V a transition time of 100 μs is permitted. This parameter is valid for
Tamb = 25 °C only.

VCC = 2.5 V ± 0.2 V
tPLH LOW to HIGH nCP to nQn
1,0 4,4 7,0 ns
propagation delay
tPHL HIGH to LOW nCP to nQn
1,0 3,8 6,4 ns
propagation delay
tPZH OFF-state to HIGH nOE to nQn
1,5 4,6 7,5 ns
propagation delay
tPZL OFF-state to LOW nOE to nQn
1,0 2,8 4,6 ns
propagation delay
248
9
Logic Families
tPHZ HIGH to OFF-state nOE to nQn

1,5 3,5 5,5 ns
propagation delay
tPLZ LOW to OFF-state nOE to nQn
1,0 3,7 5,7 ns
propagation delay
tsu set-up time nDn to nCP HIGH 1,5 0,1 – ns
nDn to nCP LOW 2,0 0,5 – ns
th hold time nDn to nCP HIGH 0,3 −0,5 – ns
nDn to nCP LOW 0,5 −0,1 – ns
tW pulse width nCP HIGH or LOW 1,5 – – ns
fmax maximum frequency nCP 150 – – MHz
VCC = 3.3 V ± 0.3 V
1,0 3,2 5,0 ns
propagation delay
1,0 3,2 4,7 ns
propagation delay
1,0 3,4 5,6 ns
propagation delay
0,5 2,3 3,7 ns
propagation delay
1,5 3,7 5,4 ns
propagation delay
1,5 3,0 4,3 ns
propagation delay
tsu set-up time nDn to nCP HIGH or
1,5 0,1 – ns
LOW
th hold time HIGH nDn to nCP HIGH or
0,5 0,1 – ns
LOW
tW pulse width nCP HIGH or LOW 1,5 – – ns
fmax maximum frequency nCP 150 – – MHz
* All typical values for VCC = 2.5 V ± 0.2 V are measured at VCC = 2.5 V and Tamb = 25 °C.
All typical values for VCC = 3.3 V ± 0.3 V are measured at VCC = 3.3 V and Tamb = 25 °C.
249
Operating Conditions of LVT

Logic Families


VO output voltage output in OFF-state or
−0,5 +7,0 V
HIGH-state *
IO output current output in LOW-state – 128 mA
output in HIGH-state −64 – mA
Tstg junction temperature −65 +150 °C
Tj storage temperature ** – +150 °C
* The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
** The performance capability of a high-performance integrated circuit in conjunction with its
thermal environment can create junction temperatures which are detrimental to reliability.

VCC supply voltage 2,7 – 3,6 V

Δt/ΔV input transition rise outputs enabled
– – 10 ns/V
and fall rate
Tamb ambient temperature −40 – +85 °C
250
9
Logic Families
Tamb
Conditions
Parameter
−40 °C to +85 °C
Symbol
Min Typ* Max Unit

– −0,85 −1,2 V
voltage
2,0 – – V
voltage
VIL LOW-level input
– – 0,8 V
voltage
VOH HIGH-level output VCC = 3.0 V; IOH = −12 mA
2,0 – – V
voltage
VOL LOW-level output VCC = 3.0 V; IOL = 12 mA
– – 0,8 V
voltage
IOH HIGH-level output
– – −12 mA
current
IOL LOW-level output
– – 12 mA
current
LOW-level output VI = GND or VCC [1] – 0,1 0,55 V
voltage
II input leakage all input pins [2]
current
VCC = 0 V or 3.6 V; VI = 5.5 V – 0,4 10 μA
control pins [2]
I/O data pins; VCC = 3.6 V [2]
VI = VCC – 0,1 1 μA
VI = 0 V – −0,4 -5 μA
IOFF power-off leakage VCC = 0 V; VI or VO = 0 to
– 0,1 ±100 μA
current 4.5 V
IBHL bus hold LOW nDn inputs; VCC = 3 V;
75 135 – μA
current VI = 0.8 V
IBHH bus hold HIGH nDn inputs; VCC = 3 V;
−75 -135 – μA
current VI = 2.0 V
IBHLO bus hold LOW nDn inputs; VCC = 3.6 V;
500 – – μA
overdrive current VI = 0 to 3.6 V [3]
251
Logic Families
Tamb
Conditions
Parameter
−40 °C to +85 °C
Symbol
Min Typ* Max Unit
IBHHO bus hold HIGH nDn inputs; VCC = 3.6 V;

– – −500 μA
overdrive current VI = 0 to 3.6 V [3]
ICEX output high output in HIGH-state when
leakage current VO > VCC; VO = 5.5 V; – 50 125 μA
VCC = 3.0 V
IO(pu/pd) power-up/ VCC ≤ 1.2 V; VO = 5.0 V to VCC;
power-down VI = GND or VCC; nOE = don’t – 1 ±100 μA
output current care [4]
IOZ OFF-state output VCC = 3.6 V; VI = VIH or VIL
current
VO = 3.0 V – 0,5 5 μA
VO = 0.5 V – 0,5 −5 μA
outputs HIGH – 0,07 0,12 mA
outputs LOW – 4 6 mA
outputs disabled [5] – 0,07 0,12 mA
ΔICC additional supply per input pin; VCC = 3 to
current 3.6 V; one input at
– 0,1 0,2 mA
VCC − 0.6 V; other inputs at
VCC or GND [6]
CI input capacitance VI = 0 V or 3.0 V – 3 – pF
CO output capacitance outputs disabled;
– 9 – pF
VO = 0 V or 3.0 V
* All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.

[1] For valid test results, data must not be loaded into the flip-flops after applying power.
[2] Unused pins at VCC or GND.
[3] This is the bus-hold overdrive current required to force the input to the opposite logic state.
From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 μs is permitted. This parameter is
valid for Tamb = 25 °C only.
[5] ICC is measured with outputs pulled to VCC or GND.
[6] This is the increase in supply current for each input at the specified voltage level other than VCC or
GND.
252
9
Logic Families
Tamb
Conditions
Parameter
−40 °C to +85 °C
Symbol
Min Typ* Max Unit
fmax maximum frequency nCP; VCC = 3.0 to 3.6 V 150 – – MHz

propagation delay VCC = 2.7 V – – 6,2 ns
VCC = 3.0 to 3.6 V 1,5 3,0 5,3 ns
VCC = 3.0 to 3.6 V 1,5 3,0 4,9 ns
VCC = 3.0 to 3.6 V 1,5 3,5 5,6 ns
VCC = 3.0 to 3.6 V 1,5 3,2 4,9 ns
VCC = 3.0 to 3.6 V 1,5 3,5 5,4 ns
VCC = 3.0 to 3.6 V 1,5 3,2 5,0 ns
tsu set-up time nDn to nCP
VCC = 2.7 V 2,0 – – ns
VCC = 3.0 to 3.6 V 2,0 0,7 – ns
th hold time nDn to nCP
VCC = 2.7 V 0,1 – – ns
VCC = 3.0 to 3.6 V 0,8 0 – ns
tWH pulse width HIGH nCP
VCC = 2.7 V 1,5 – – ns
VCC = 3.0 to 3.6 V 1,5 0,6 – ns
tWL pulse width LOW nCP
VCC = 2.7 V 3,0 – – ns
VCC = 3.0 to 3.6 V 3,0 1,6 – ns
* Typical values are measured at VCC = 3.3 V and Tamb = 25 °C.

253
Special Features
Logic Families
Powering-up/Powering-down
LVT and ALVT have a feature that is useful for live insertion and removal. A circuit is
built into these families that monitors the supply voltage and ensures that the
output is forced to a 3-state mode when VCC is lower than 1.2 V. Then, the transistor
does not conduct and the external OE signal is overruled and the output goes into
3-state mode. Normally, when removing a board in a live system, the power supply
is removed first and high currents into the output circuit are prevented. Above
1.2 V the transistor will start to conduct and the part may again become active (i.e.,
the external OE enables the output). It’s the task of the system designer to ensure
that an external circuit forces the correct OE signal when VCC is higher than 1.2 V.
aaa-032312
OE
INPUT OUTPUT
VCC
OE NOR
GND
Figure 9.9 | Power-up state
254
9
Bus Hold
Logic Families
aaa-032313
+
All ALVT products have integrated bus
hold inputs. A bus hold circuit allows
CMOS input pins to be left open: the
input is always defined to be LOW or
HIGH via the small MOS transistors that
serve as dynamic pull-up or pull-down
INPUT
resistors. To allow 5 V on the inputs, a
Schottky diode is inserted between
input and the PMOS transistor, blocking
any current VCC, even when the part is
powered down.
Figure 9.10 | Bus Hold circuit
Summary
Both LVT and ALVT logic families are optimized for use as backplane drivers. These
parts combine very fast switching with low power dissipation. The clever design
makes them an ideal choice for use in backplanes in high-end EDP and telecom
applications. In other areas also where very short propagation delays are a must,
both families excel. Added features such as automatic 3-state when the part’s
output is tied to a higher voltage make them an ideal choice in many mixed mode
3 V–5 V systems.
255
Logic Families
256
10
Chapter 10
FAQ
FAQ
257
What is the maximum operating frequency of a logic device?

FAQ
Datasheets for synchronous logic devices (clock dependent) provide a maximum

operating frequency (example 74HC165 is rated at 56 MHz maximum frequency at
specific voltage/drive values). Datasheets for asynchronous logic devices (general
gates, not clock dependent) do not typically provide this data. In general, logic
devices can be clocked to about 100 MHz before capacitive loading of the PCB and
external circuitry become the limiting factor. IBIS models are available for most
devices which allow simulation at specific user frequencies.
What are the output drive of various logic families?

Nexperia logic devices have output drive capability between 3 mA (HEF-family) and
100 mA (NPIC). See Appendix for complete table of output drive current by family
What is the difference between a Schmitt Trigger and

Schmitt Trigger “Action” input?
Schmitt Trigger adds hysteresis to an input signal to reduce the impact of noise
that occurs around the transition point. “True” Schmitt triggers will list two
switching thresholds in the datasheet for Vt+ (LO-HI transition) and Vt- (HI-LO
transition). The Schmitt Trigger feature allows input signals with long transitions
times. There is no maximum input transition fall and rise rate to be obeyed (∆t/∆V).
Schmitt Trigger “Action” inputs will have a much smaller hysteresis that is not
specified in the datasheet (no Vt+/Vt- listing), a maximum transition fall and rise
rate is required for the input signals, like for a standard logic input.
A standard (non-Schmitt or any type) input will have time/volt rise time of
10–20 ns max. A Schmitt trigger "action" input will have a time/volt rise time of
20–100 ns max. A “true” Schmitt trigger device will have an essentially infinite time/
volt rise time.
What happens to a logic gate above or below the maximum

rated temperature?
Operation of a logic device should be limited to the datasheet rating (Ta = −40°C to
+125°C for most devices).
Operation above this rating can exceed the maximum junction temperature
(+150°C) and impact lifetime or lead to damage the device. Operation below this
rating may cause the device to violate the datasheet specifications for power/
voltage/timing (due to temperature-reduced on-state resistance).
258
10
What is the operating lifetime of a logic gate?
FAQ
Operating lifetime is a measure of how long the device will operate in a biased
(powered on) condition. Logic devices have no specific design lifetime and with
MTBF calculated at 304 billion hours (74AUP1G08GM) gates may operate “forever”.
Real world applications show that devices powered continually for over 50 years
show no sign of degradation.
What is the expected manufacturing EOL of a logic gate?

Nexperia logic devices have extremely long manufacturing lifetimes: some have
been in continuous production since the 1970’s. For timelines into the future, see
our “Longevity” section on the website which lists devices (by package type) which
are guaranteed to be in production for at least 10 years. In general: “we will make
parts until customers stop buying them”
What is the difference between gold and copper wire bonding?

Historically integrated circuits used gold bond wire between the package
leadframe and the die. This was due to the ease of attaching gold wire to the die
pads. Recent innovations in copper ultrasonic welding now makes it possible to
wire bond with copper. Besides the much lower cost for the wire, copper is actually
a better conductor than gold (conductivity of copper = 58 Ωm−1 and for
gold = 45 Ωm−1).
Are logic functions standardized by part number?

Logic device part numbers from all logic suppliers contain a standard “function part
number” following the process family. For example 74LVC08 indicates a logic
device in the LVC process family and “08” indicates the function in a “two input
AND”. See the appendix for list of most common function numbers.
Can I supply a signal voltage to an input/output when VCC = 0 V?

Older logic families may consume excess power and may even “back-drive” the
device (leak enough power from the input/output pins to the VCC supply rail to
inadvertently energize the logic device). Newer logic families (LVC, AUP, AXP, LV-A
etc.) have a feature called “Ioff” which isolates the output pins from the internal
circuits of the logic device when VCC = 0. At the input the over-voltage tolerance
feature lets the inputs stay high-ohmic without a supply voltage. In this case there
is no diode path from the input to the VCC rail (see input stage schematics in the
logic family chapters).
259
Can I drive an LED directly from a logic gate?

FAQ
It depends. LEDs consume from a few mA to amps of drive current. Logic families
can drive from a few mA to 24 mA (LVC family) or even 100 mA (NPIC family). Always
confirm that the output drive of the Logic family is compatible with the drive
requirements of the LED.
Can I pull up an open-drain output to higher than VCC?

Consult the datasheet for the Vo specification. For example, the 74HC06 (triple
inverter with open-drain outputs) has a VCC rating of 2.0 V–6.0 V and a Vo of 0 V to
VCC. However, the 74LVC1G06 (single inverter with open-drain output) has a VCC
range of 1.65 V–5.5 V and Vo range of 0 V–5.5 V. The output of the HC cannot
exceed VCC but the output of the LVC variant can.
Can I use a gate to drive the VCC of the rest of the circuit?
Can it discharge the VCC capacitance?
The output drive capability of the supplying logic gate must always be observed.
See the Appendix listing of output drive capability of a logic family. As the receiving
logic gate will have a decoupling capacitor VCC to ground, the inrush charging
current of the capacitor must be added to the calculation.
Can I use a Nexperia logic device for military or aerospace or

life critical applications?
Nexperia logic device datasheets explicitly state “Nexperia products are not
designed, authorized or warranted to be suitable for use in life support, life-critical
or safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk”.
What is the most common mode of failure of a logic device?

The primary failure modes of logic gates are EOS (Electrical Over Stress) or ESD
(Electro Static Discharge). EOS typically occurs when exceeding the output drive
capability of the device, resulting in localized die heating and damage. FA (Failure
Analysis) reports will show thermal damage to the die near the output drive
transistors. ESD damage occurs when voltage exceeding the ESD protection level
of the device (typically 2 kV) enters through an input or output pin and causes
vaporization or burn-through of an internal trace (usually not one of the output
drivers which are more robust in general)
260
10
How do the AUP and AUC logic families compare?
FAQ
AUP and AUC are both low voltage logic families (AUP VCC range 0.8 V–3.6 V and
AUC VCC range 1 V–3.6 V). Propagation delay of the AUC family is faster (1.5 ns
versus 3.8 ns for AUP) while the static power consumption of AUP is less (0.5 uA
versus 10 uA for the AUC). AUP trades off some performance for lower power
consumption.
How can I cross reference from one vendor package to another?

Most logic suppliers adhere to IEEE “SOT” package standards. For example, a
SOT-363 will have the same mechanical dimensions across all suppliers. See the
Appendix for a listing of the Packaging Codes for the most common industry
package types.
How can I cross reference from one vendor process to another?

Logic process families (74HCxx, 74AUP1Gxx, etc.) were created to support a
particular microprocessor family in a particular timeframe, therefore all logic
suppliers tend to use the same silicon process. Family name is usually the same (HC
is same for all suppliers) but some families are not obvious. For a complete list of
compatible logic process families, see the Appendix.
How much heat does a part generate? How do I use thermal

coefficient values?
Device datasheets provide the Ptot (Total Power Dissipation) value, indicating the
maximum power (heat) that the package type can dissipate. Thermal Resistance
values (Rth(j-a), Rth(j-c)) are listed on the website (not the datasheet) and provide the
thermal resistance from Junction-to-Ambient and Junction-to-Case in degrees
Kelvin/Watt. To calculate the exact current consumption (and thus power
dissipation) of a device in your specific application, see the Chapter on “Power
Considerations”
On dual supply devices, is there a restriction which supply has

to be the higher or lower one of the two VCC levels?
Most dual voltage supply devices have no restriction if VCC(A) is the lower or higher
supply compared to VCC(B). This can be determined by the relationship of VCC(A) to
VCC(B). For example, the 74AVC4T245 datasheet indicates that VCC(A) and VCC(B) are
both valid 0.8 V to 3.6 V and thus independent of each other (either can be higher/
lower than the other) For optimal system design you establish VCC(A) first if you are
presenting signals to the “A” side of the device that references “Pins A and DIR are
referenced to VCC(A)” (example 74AUP1T45)
261
What is a packing suffix? Why is it not in the datasheet?

FAQ
The packing suffix is part of the orderable number and indicates the method in
which the devices are shipped. Example 74AUP1G08GM is available with a ,132
suffix (shipped as Reel 7” Q3/T4 orientation) or with a ,115 suffix (shipped as Reel
7” Q1/T1 orientation). Some newer devices may include a single alphanumeric
(example “X”) in place of this three-digit number. Nexperia chooses not to include
this information in the device datasheet as it has no bearing on the electrical
characteristics of the device. For a complete listing of Nexperia packing codes,
please see the appendix. Note that not all packing methods are available for all
devices. Always consult our website for valid part/packing combinations.
What are the modern replacements for historical TTL, LS, S

logic devices?
Historic logic families can sometimes be replaced with modern equivalents with
certain precautions taken. Most legacy logic families operated at 4.5 V–5.5 V with
Tpd Propagation Delay speeds no faster than 10 ns. The biggest difference to today
logic devices is the amount of output drive required due to the large fanout
requirements: often 16 mA–64 mA. Modern 74HCTxx and 74AHCTxx devices can
match VCC requirements and meet/exceed Tpd but output current is limited to
8 mA. Carefully evaluate your actual output drive requirements to determine if
74HCT/74AHCT are viable replacements.
What does the suffix “-Q100” indicate?

The Q100 suffix (example 74AHC1G00GW-Q100) indicates that the logic device has
been designed and manufactured to pass Automotive AEC-Q100 Qualification.
Q100 devices have tightened process controls including: TS16949 and VDA
approved production facilities, flagged as automotive lots, subjected to additional
process flow quality gates and stricter rules for lot dispositioning and maverick lot
handling. For complete benefits of Q100 Logic, see our Q100 Logic portfolio
Brochure
What happens if I exceed the VCC rating?

Exceeding VCC for any period of time will cause higher-than-normal temperatures
of the components on the die. Duration of the overvoltage and the amount of
overvoltage will determine if there is an impact to the expected lifetime of the
device based on increased Arrhenius Activation Energy. All datasheets include VCC
specifications under Limiting Values and Recommended Operating Conditions.
VCC operation under the wider Limiting Values will not affect device lifetime but
may cause voltage/timing values in the datasheet to be exceeded. Always design
for Recommended Operating Conditions
262
10
The AXP family only shows Vil/Vih values for certain ranges of VCC.
FAQ
What if I want to operate between those ranges?
As seen in the following graph, values of Vil/Vih are only provided for certain values
of VCC. The discontinuities between voltage ranges can be linearly approximated
aaa-032005
3V
2V
VIH range
VIL range
1V
1V 2V 3V
Figure 10.1 | Input voltage ranges of the logic family AUP dependent on VCC
What is a Date Code and how do I read it? What do the top
markings mean?
The size of the logic package determines the amount/type of data printed. For
large packages (greater than 10 pins) there will be three lines of information. Line 1
contains the device part number. It may be concatenated for long part numbers
(ex: 74AVC8T245 will concatenate to AVC8T245). Line 2 contains the Manufacturing
Lot number (an internal number but useful for tracing batches for Failure Analysis).
Line 3 contains the Manufacturing locations (Diffusion/Assembly/Test) and the
Date Code (format Year/week number). There may or may not be a Nexperia logo
on the device: in some cases the older NXP logo will remain. For more details, see
the Appendix.
For smaller devices (8 pins and smaller) special coding is used due to space
limitations. The device part number will be represented by a 3-digit alphanumeric
code (this code is included in the datasheet). The date code is written in binary on
the edges of the package: left side contains the Last Digit of Year
(ie 0110 = 6 = 2016), right side contains Month Number Code (ex: 0001 = January).
See the Appendix for details
263
What is MSL and what does it have to do with package storage?

FAQ
MSL (Moisture Sensitivity Level) indicates the devices proclivity to absorbing

humidity from the ambient environment. Absorbed humidity can cause issues
during reflow and wave soldering operations (“popcorn” delamination of packages
due to escape of trapped steam). Most Nexperia devices are MSL = 1 which
indicates an unlimited floor life out of the shipping bag (no effect to humidity). MSL
data is available for each device on our website.
What is MTBF and what does it tell me about the lifetime of a

part? How does it compare to FIT?
MTBF (Mean Time Between Failures) is a predicted elapsed time between inherent
failures of the logic device. It is inversely related to IFR measure in FITs.
Intrinsic Failure Rate (IFR)
The “plateau” of the failure rate curve consists of random failures, and the failure rate is
relatively low and constant. This is the best behaviour observed in large populations of mature
components, and is commonly referred to as the “useful life” of the product. The Intrinsic
Failure Rate (IFR) is usually defined by the Failure-In-Time (FIT); one FIT being one failure in 1
billion device hours of operation.
The formula used to calculate the Intrinsic Failure Rate, expressed in FIT’s, is as follows:
n c (n)
IFR = ·10 9 [FIT]
N·t·A
Where
IFR = Intrinsic Failure Rate in FIT N = Number of products tested

n = Observed number of failures (excluding t = Duration of test at elevated temperature,
early failures!) in hours
nc(n) = Corrected number of failures, using A = Arrhenius acceleration factor energy
60% confidence intervals with Poisson (EA = 0.7 eV, Tref = 55 °C)
statistics
Throughout this Quality Summary, the Arrhenius acceleration factor is calculated with an
activation energy (EA) of 0.7 eV and a reference temperature of 55°C. As in the case for the
Early Failure Rate determination, the IFR calculations are based on the data collected from
SHTL and DHTL tests (stresses with electrical bias at elevated temperature), and all FIT data
are calculated by accumulating the applicable results over a period of 12 months.
Mean Time Between Failures (MTBF)
1
MTBF = [hours]
IFR · 10 -9
Where
MTBF = Mean Time Between Failures in hours IFR = Intrinsic Failure Rate in FIT
264
10
What is RoHS, REACH and Green and Dark Green mean?
FAQ
These terms all indicate the compliance of the device to various environmental
standards, EU RoHS Compliant, EU/CN RoHS Compliance, Halogen-Free, Lead-Free.
Etc.
For a complete listing, see our website at

www.nexperia.com/quality/environmental-indicators
What is the purpose of the center pad DQFN “BQ”-suffix

packages
The center pad on the BQ package (example 74AVC2T245BQ SOT763-1) was
originally designed as heat pad for high power devices (Class D amplifiers. etc.). As
logic devices have low power dissipation, this heat pad is no longer required but
remains for package compatibility. Please note that the substrate is attached to
this pad using conductive die attach material. There is no electrical or mechanical
requirement to solder this pad. However, if it is soldered the solder land should
remain floating or be connected to GND or VCC as indicated by the datasheet. Most
devices allow connection to GND but select devices (ex. 74HC4051BQ) should
connect only to VCC.
What is the difference between 74HC and 74HCT families? (also

74AHC and 74AHCT)
The “T” in each of these indicates the family has been optimized for “TTL” input
voltage levels. While both families can operate at TTL supply levels VCC = 4.5–5.5 V
(HC family can operate 2.0–6.0 V), the HCT family inputs are matched to legacy TTL
signal levels (Vil = 1.2 V, Vih = 1.6 V) compared to HC (VIl = 2.1, Vih = 2.4 V) at the same
VCC. Output drive for the two families is identical. HCT family has slightly slower
propagation delay tpd. Because of the similarities, these two device families will
share the same datasheet (ex: 74HC00 and 74HCT00)
What is the difference between A and non-A devices?

An “A” suffix on a logic device (example 74LVC14A) indicates that the device has
been redesigned, impacting one or more specifications from the original
specification. The “A” suffix has a special meaning when used with the LV family,
example indicating that the “A” version has the iOff feature (input/outputs are
isolated when VCC = 0). You should carefully evaluate any changes from the “non-A”
to the “A” version before replacing it
265
What should I do with pins I don’t need on a device?

FAQ
Unused input pins on all logic device must always be connected to VCC or GND.
Unconnected input pins will float due to intrinsic leakage paths on the die. As the
signal voltage crosses a transition level (Vil, Vih), the device will switch outputs,
causing a brief slump on the power supply rail. This slump in VCC can cause the Vi,
Vih levels to change, causing the device to switch output states back again. This
creates an oscillation loop, resulting in high current consumption, possibly causing
catastrophic damage to the device. Unused output-only pins can be left
unterminated safely.
Why do some buffers have termination resistors in them?

Certain devices such as the 74LVC2245 have termination resistors in each of the
output driver lines. This resistor is added for impedance matching into 50 ohm
cables to reduce overshoot and undershoot. The second “2” in the part number
differentiates this device from the standard output (no terminal resistor) 74LVC245
device
Why do the 74LVC2G74/1G74 have different part numbers but

same function? Both are single gate but the part number
indicates one has two gates included
Nexperia (then Philips/NXP) created the original device 74LVC1G74 (single D-type
flip-flop). A competitor released a functional equivalent later but named it the
74LVC2G74. The exact reason is unknown: either a simple mistake or an ingenious
method to create an apparent sole-source part number. To clear this confusion,
Nexperia now provides the same silicon under either part number, 74LVC1G74 and
74LVC2G74: one to match the original name and one to match the competition
name. There is no electrical difference between these two devices and they are in
fact the same silicon, package and top marking. We apologize for any confusion this
caused but we didn’t start it!
Why is the drive current of a device important? How does it

relate to Vol and Voh?
Each logic family has a maximum output drive capability. As the output load
increases, VOH voltage levels fall respectively VOL levels rise due to loading of the
output stage. Past the maximum rated output drive of the family (example 74HC00
8 mA) VOL/VOH no longer meet standard TTL/LVTTL voltage levels. The maximum
ICC supply current (found in Limiting Values of the datasheet) should not be used as
maximum output drive capability.
266
10
Is it allowed to operate a device below the absolute VCC limit
FAQ
rating but outside the recommended operating conditions?
Lifetime testing has been performed for Recommended Values only. Operating
above these limits can lead to reduced lifetime. Also note that Static and Dynamic
parameters listed in the datasheet may not be accurate outside of Recommended
Values.
Why are the outputs of logic devices with flipflops not cleared
after power-on?
Devices from standard logic families have no dedicated power-on circuitry that puts
the flip-flops into a default condition after VCC has been ramped up. For devices
that have a reset pin, a reset cycle can be applied immediately after power is up.
For this it needs to be mentioned that it is not allowed to connect a low active reset
pin to VCC directly. This approach does not work because the timing conditions for a
proper reset action are not fulfilled. In Fig.xx a simple solution is depicted. A low
pass filter is applied to the MR pin. The capacitor is charged from VCC by the resistor
R and keeps low level for some time until VCC has reached minimum voltage for
proper operation and additional hold time has to be provided for the reset signal.
aaa-032019
VCC
CP
R 74HCT164
MR
Figure 10.2 | Simple power-on reset generation for low-active reset pins
267
Top 10 Design Errors with Logic

FAQ
• Violating Vin/Vout levels • Violating rise/fall times (and solutions)

• Violating setup/hold times in flip flops • Operation outside of temperature
and latched inputs range
• Un-terminated/floating inputs • Understanding power calculations
• No decoupling capacitor • Understanding translation
• Exceeding output drive capability methodologies, (single/dual supply,
(damage or low voltage levels) selecting single VCC)
• Exceeding Fmax
268
Appendix
Appendix
269
List of Common 7400 and 4000 Logic Functions

Appendix
Typical nomenclature: 74HCxx or HEF4xxx
Function Number Boolean Function Function Number Boolean Function

-00 Quad 2-input NAND gate -24 Quad 2-input NAND gate gates with
-01 Quad 2-input NAND gate with open Schmitt-trigger line-receiver inputs.
collector outputs -25 Dual 4-input NOR gate with Strobe
-02 Quad 2-input NOR gate -26 Quad 2-input NAND gate with 15V
-03 Quad 2-input NAND gate with open open collector outputs
collector outputs (different pinout -27 Triple 3-input NOR gate
than 7401)
-28 Quad 2-input NOR Buffer
-04 Hex Inverter
-30 8-input NAND gate
-05 Hex Inverter with open collector
-31 Hex Delay Elements
outputs
-32 Quad 2-input OR gate
-06 Hex Inverter Buffer/Driver with 30V
open collector outputs -33 Quad 2-input NOR Buffer with open
collector outputs
-07 Hex Buffer/Driver with 30V open
collector outputs -34 Low-power dual supply translating
buffer
-08 Quad 2-input AND gate
-36 Quad 2-input NOR Gate (different
-09 Quad 2-input AND gate with open
pinout than -02)
collector outputs
-37 Quad 2-input NAND Buffer
-10 Triple 3-input NAND gate
-38 Quad 2-input NAND Buffer with
-11 Triple 3-input AND gate
open collector outputs
-12 Triple 3-input NAND gate with open
-39 Quad 2-input NAND Buffer
collector outputs
-40 Dual 4-input NAND Buffer
-13 Dual Schmitt trigger 4-input NAND
gate -41 Binary-coded decimal to Decimal
Decoder/Nixie tube Driver
-14 Hex Schmitt trigger Inverter
-42 BCD to Decimal Decoder
-15 Triple 3-input AND gate with open
collector outputs -43 Excess-3 to Decimal Decoder
-16 Hex Inverter Buffer/Driver with 15V -44 Excess-3-Gray code to Decimal
open collector outputs Decoder
-17 Hex Buffer/Driver with 15V open -45 BCD to Decimal Decoder/Driver
collector outputs -46 BCD to Seven-segment display
-18 Dual 4-input NAND gate with schmitt Decoder/Driver with 30V open
trigger inputs collector outputs
-19 Hex Schmitt trigger Inverter -47 BCD to 7-segment Decoder/Driver

with 15V open collector outputs
-20 Dual 4-input NAND gate
-48 BCD to 7-segment Decoder/Driver
-21 Dual 4-input AND gate
with Internal Pullups
-22 Dual 4-Input NAND gate with open
collector outputs
with open collector outputs
-23 Expandable Dual 4-input NOR gate
-50 Dual 2-Wide 2-input AND-OR-Invert
with strobe
Gate (one gate expandable)
270
Appendix
-51 Dual 2-Wide 2-Input AND-OR-Invert -78 Dual J-K Flip-Flop with Preset,
Gate Common Clear, and Common Clock
or Dual Negative Edge Triggered J-K
-52 Expandable 4-Wide 2-input AND-OR
Flip-Flop with Preset, Common Clear,
Gate
and Common Clock
-53 Expandable 4-Wide 2-input
-79 Dual D Flip-Flop
AND-OR-Invert Gate
-80 Gated Full Adder
-54 4-Wide 2-Input AND-OR-Invert Gate
-81 16-bit Random Access Memory
-55 2-Wide 4-Input AND-OR-Invert Gate
(-H version is expandable) -82 2-bit Binary Full Adder
-56 50:1 Frequency divider -83 4-bit Binary Full Adder
-57 60:1 Frequency divider -84 16-bit Random Access Memory
-58 2-Input & 3-Input AND-OR Gate -85 4-bit Magnitude Comparator
-59 2-Input & 3-Input AND-OR-Invert -86 Quad 2-input XOR gate
Gate
-87 4-bit True/Complement/Zero/One
-60 Dual 4-input Expander Element
-61 Triple 3-input Expander -88 256-bit Read-only memory
-62 3-2-2-3-Input AND-OR Expander -89 64-bit Random Access Memory
-63 Hex Current Sensing Interface Gates -90 Decade Counter (separate
Divide-by-2 and Divide-by-5 sections)
-64 4-2-3-2-Input AND-OR-Invert Gate
-91 8-bit Shift Register, Serial In, Serial
-65 4-2-3-2-Input AND-OR-Invert Gate
Out, Gated Input
with open collector output
-92 Divide-by-12 Counter (separate
-66 Single-pole single-throw analog
switch
-93 4-bit Binary Counter (separate
-67 16-channel analog multiplexer/
demultiplexer
-94 4-bit Shift register, Dual Asynchro-
-68 Dual 4 Bit Decade Counters
nous Presets
-69 Dual 4 Bit Binary Counters
-95 4-bit Shift register, Parallel In, Parallel
-70 AND-Gated Positive Edge Triggered Out, Serial Input
J-K Flip-Flop with Preset and Clear
-96 5-bit Parallel-In/Parallel-Out Shift
-71 AND-OR-Gated J-K Master-Slave register, Asynchronous Preset
Flip-Flop with Preset or AND-Gated
-97 Synchronous 6-bit Binary Rate
R-S Master-Slave Flip-Flop with
Multiplier
Preset and Clear
-98 4-bit Data Selector/Storage Register
-72 AND Gated J-K Master-Slave Flip-Flop
with Preset and Clear -99 4-bit Bidirectional Universal Shift
register
-73 Dual J-K Flip-Flop with Clear
-100 Dual 4-Bit Bistable Latch
-74 Dual D Positive Edge Triggered
Flip-Flop with Preset and Clear -101 AND-OR-Gated J-K Negative-Ed-
ge-Triggered Flip-Flop with Preset
-75 4-bit Bistable Latch
-102 AND-Gated J-K Negative-Edge-Trig-
-76 Dual J-K Flip-Flop with Preset and
gered Flip-Flop with Preset and Clear
Clear
-103 Dual J-K Negative-Edge-Triggered
-77 4-bit Bistable Latch
Flip-Flop with Clear
271
Appendix

-104 J-K Master-Slave Flip-Flop -133 13-Input NAND gate
-105 J-K Master-Slave Flip-Flop -134 12-Input NAND gate with Three-state
Output
Flip-Flop with Preset and Clear -135 Quad Exclusive-OR/NOR Gate
-107 Dual J-K Flip-Flop with Clear or Dual -136 Quad 2-Input XOR gate with open
J-K Negative-Edge-Triggered collector outputs
Flip-Flop with Clear
-137 3 to 8-line Decoder/Demultiplexer
-108 Dual J-K Negative-Edge-Triggered with Address Latch
Flip-Flop with Preset, Common Clear,
-138 3 to 8-line Decoder/Demultiplexer
and Common Clock
-139 Dual 2 to 4-line Decoder/Demultiple-
-109 Dual J-Not-K Positive-Edge-Triggered
xer
Flip-Flop with Clear and Preset
-140 Dual 4-input NAND Line Driver
-110 AND-Gated J-K Master-Slave Flip-Flop
with Data Lockout -141 BCD to Decimal Decoder/Driver for
cold-cathode indicator/NIXIE Tube
-111 Dual J-K Master-Slave Flip-Flop with
Data Lockout -142 Decade Counter/Latch/Decoder/
Driver for Nixie Tubes
Flip-Flop with Clear and Preset -143 Decade Counter/Latch/De-
coder/7-segment Driver, 15 mA
Constant Current
Flip-Flop with Preset
-144 Decade Counter/Latch/De-
coder/7-segment Driver, 15V open
Flip-Flop with Preset, Common Clock
collector outputs
and Clear
-145 BCD to Decimal Decoder/Driver
-116 Dual 4-bit Latches with Clear
-147 10-Line to 4-Line Priority Encoder
-118 Hex Set/Reset Latch
-148 8-Line to 3-Line Priority Encoder
-119 Hex Set/Reset Latch
-150 16-Line to 1-Line Data Selector/
-120 Dual Pulse Synchronizer/Drivers
Multiplexer
-121 Monostable Multivibrator
-122 Retriggerable Monostable Multiplexer
Multivibrator with Clear
-123 Dual Retriggerable Monostable Multiplexer
Multivibrator with Clear
-153 Dual 4-Line to 1-Line Data Selector/
-124 Dual Voltage-Controlled Oscillator Multiplexer
-125 Quad Bus Buffer with Three-State -154 4-Line to 16-Line Decoder/
Outputs, Negative Enable Demultiplexer
-126 Quad Bus Buffer with Three-state -155 Dual 2-Line to 4-Line Decoder/
Outputs, Positive Enable Demultiplexer
-128 Quad 2-input NOR Line Driver -156 Dual 2-Line to 4-Line Decoder/
Demultiplexer with open collector
-130 Quad 2-input AND gate Buffer with
outputs
30V open collector outputs
-157 Quad 2-Line to 1-Line Data Selector/
-131 Quad 2-input AND gate Buffer with
Multiplexer, Noninverting
15V open collector outputs
-158 Quad 2-Line to 1-Line Data Selector/
-132 Quad 2-input NAND Schmitt trigger
Multiplexer, Inverting
272
Appendix
-159 4-Line to 16-Line Decoder/ -209 1024-bit (1024x1) RAM with
Demultiplexer with open collector three-state output
outputs
-210 Octal Buffer
-160 Synchronous 4-bit Decade Counter
-219 64-bit (16x4) RAM with Noninverting
with Asynchronous Clear
three-state outputs
-161 Synchronous 4-bit Binary Counter
-221 Dual Monostable Multivibrator with
Schmitt trigger input
-162 Synchronous 4-bit Decade Counter
-222 16 by 4 Synchronous FIFO Memory
with Synchronous Clear
with three-state outputs
-163 Synchronous 4-bit Binary Counter
-224 16 by 4 Synchronous FIFO Memory
with Synchronous Clear
-164 8-bit Parallel-Out Serial Shift Register
-225 Asynchronous 16x5 FIFO Memory
-226 4-bit Parallel Latched Bus Transceiver
-165 8-bit Serial Shift Register, Parallel
Load, Complementary Outputs
-230 Octal Buffer/Driver with three-state
-166 Parallel-Load 8-Bit Shift Register
outputs
-167 Synchronous Decade Rate Multiplier
-232 Quad NOR Schmitt trigger
-168 Synchronous 4-Bit Up/Down Decade
-237 1-of-8 Decoder/Demultiplexer with
Counter
Address Latch, Active High Outputs
-169 Synchronous 4-Bit Up/Down Binary
-238 1-of-8 Decoder/Demultiplexer, Active
Counter
High Outputs
-170 4 by 4 Register File with open
-239 Dual 2-of-4 Decoder/Demultiplexer,
collector outputs
Active High Outputs
-171 16-Bit Multiple Port Register File
-240 Octal Buffer with Inverted
with Three-state Outputs
three-state outputs
-173 Quad D-type flip-flop; positive-edge
-241 Octal Buffer with Noninverted
trigger; 3-state
three-state outputs
-174 Hex D-type flip-flop with reset; positi-
-242 Quad Bus Transceiver with Inverted
ve-edge trigger
three-state outputs
-175 Quad D-type flip-flop with reset;
-243 Quad Bus Transceiver with
positive-edge trigger
Noninverted three-state outputs
-191 Presettable synchronous 4-bit binary
-244 Octal Buffer with Noninverted
up/down counter
three-state outputs
-193 Presettable synchronous 4-bit binary
-245 Octal Bus Transceiver with
up/down counter
Noninverted three-state outputs
-194 4-bit bidirectional universal shift
register
-200 256-bit RAM with Three-state
Outputs
-201 256-bit (256x1) RAM with three-state
outputs
with Internal Pull-up Outputs
-206 256-bit RAM with open collector
outputs
273
Appendix

-251 8-line to 1-line Data Selector/ -285 4-bit by 4-bit Parallel Binary
Multiplexer with complementary Multiplier (high order 4 bits of
three-state outputs product)
-253 Dual 4-line to 1-line Data Selector/ -287 1024-bit (256x4) Programmable
Multiplexer with three-state outputs read-only memory with three-state
outputs
-255 Dual 4-bit Addressable Latch
-288 256-bit (32x8) Programmable
-256 Dual 4-bit Addressable Latch
read-only memory with three-state
-257 Quad 2-line to 1-line Data Selector/ outputs
Multiplexer with Noninverted
-289 64-bit (16x4) RAM with open
three-state outputs
collector outputs
-258 Quad 2-line to 1-line Data Selector/
-290 Decade Counter (separate
Multiplexer with Inverted three-state
divide-by-2 and divide-by-5 sections)
outputs
-291 4-bit Universal Shift register, Binary
-259 8-bit Addressable Latch
Up/Down Counter, Synchronous
-260 Dual 5-Input NOR Gate
-292 Programmable Frequency Divider/
-261 2-bit by 4-bit Parallel Binary Digital Timer
Multiplier
-293 4-bit Binary Counter (separate
-265 Quad Complementary Output divide-by-2 and divide-by-8 sections)
Elements
-294 Programmable Frequency Divider/
-266 Quad 2-Input XNOR gate with open Digital Timer
collectorOutputs
-295 4-Bit Bidirectional Register with
-269 8-bit bidirectional binary counter Three-state outputs
-270 2048-bit (512x4) Read Only Memory -297 Digital Phase-Locked-Loop Filter
-298 Quad 2-Input Multiplexer with
-271 2048-bit (256x8) Read Only Memory Storage
-299 8-Bit Bidirectional Universal Shift/
-273 8-bit Register with Reset Storage Register with three-state
-274 4-bit by 4-bit Binary Multiplier outputs
-275 7-bit Slice Wallace tree -301 256-bit (256x1) Random access
memory with open collector output
-276 Quad J-Not-K Edge-Triggered
Flip-Flops with Separate Clocks, -309 1024-bit (1024x1) Random access
Common Preset and Clear memory with open collector output
-278 4-bit Cascadeable Priority Registers -310 Octal Buffer with Schmitt trigger
with Latched Data Inputs inputs
-279 Quad Set-Reset Latch -314 1024-bit random access memory
-280 9-bit Odd/Even Parity bit Generator/ -320 Crystal controlled oscillator
Checker -322 8-bit Shift register with Sign Extend,
-281 4-bit Parallel Binary Accumulator three-state outputs
-283 4-bit Binary Full adder -323 8-bit Bidirectional Universal Shift/
Storage Register with three-state
-284 4-bit by 4-bit Parallel Binary
outputs
Multiplier (low order 4 bits of
product) -324 Voltage Controlled Oscillator (or
Crystal Controlled)
-332 3-input OR-gate
274
Appendix
-340 Octal Buffer with Schmitt trigger -375 Quad Bistable Latch
inputs and three-state inverted
-376 Quad J-Not-K Flip-flop with Common
outputs
Clock and Common Clear
-341 Octal Buffer with Schmitt trigger
-377 8-bit Register with Clock Enable
inputs and three-state noninverted
outputs -378 6-bit Register with Clock Enable
-344 Octal Buffer with Schmitt trigger -379 4-bit Register with Clock Enable and
inputs and three-state noninverted Complementary Outputs
outputs -380 8-bit Multifunction Register
-348 8 to 3-line Priority Encoder with -381 4-bit Arithmetic Logic Unit/Function
three-state outputs Generator with Generate and
-350 4-bit Shifter with three-state outputs Propagate Outputs
-351 Dual 8-line to 1-line Data Selectors/ -382 4-bit Arithmetic Logic Unit/Function
Multiplexers with three-state Generator with Ripple Carry and
outputs and 4 Common Data Inputs Overflow Outputs
-352 Dual 4-line to 1-line Data Selectors/ -384 Bilateral switch

Multiplexers with Inverting Outputs -385 Quad 4-bit Adder/Subtractor
-353 Dual 4-line to 1-line Data Selectors/ -386 Quad 2-Input XOR gate
Multiplexers with Inverting
three-state outputs
read-only memory with open
-354 8 to 1-line Data Selector/Multiplexer collector outputs
with Transparent Latch, three-state
-388 4-bit Register with Standard and
outputs
Three-state Outputs (-LS388 is
-356 8 to 1-line Data Selector/Multiplexer equivalent to AMD Am25LS2518 ,
with Edge-Triggered Register, functional equivalent to Am2918 and
three-state outputs Am25S18)
-361 Bubble memory function timing -390 Dual 4-bit Decade Counter
generator
-393 Dual 4-bit Binary Counter
-362 Four-Phase Clock Generator/Driver
-395 4-bit Universal Shift register with
(aka TIM9904)
three-state outputs
-365 Hex Buffer with Noninverted
-398 Quad 2-input Multiplexers with
three-state outputs
Storage and Complementary
-366 Hex Buffer with Inverted three-state Outputs
outputs
-399 Quad 2-input Multiplexer with
-367 Hex Buffer with Noninverted Storage
three-state outputs
-408 8-bit Parity Tree
-368 Hex Buffer with Inverted three-state
-412 Multi-Mode Buffered 8-bit Latches
outputs
with three-state outputs and Clear
-370 2048-bit (512x4) Read-only memory (74S412 is equivalent to Intel 8212,
with three-state outputs TI TIM8212)
-371 2048-bit (256x8) Read-only memory -423 Dual Retriggerable Monostable
with three-state outputs Multivibrator
-373 Octal Transparent Latch with -424 Two-Phase Clock Generator/Driver
three-state outputs (74LS424 is equivalent to Intel 8224,
-374 Octal Register with three-state TI TIM8224)
outputs
275
Appendix

-425 Quad Gates with three-state outputs -465 Octal Buffer with three-state outputs
and Active Low Enables
-468 Dual MOS-to-TTL Level Converter
-426 Quad Gates with three-state outputs
and Active High Enables
read-only memory with open
-428 System Controller for 8080A (74S428 collector outputs
is equivalent to Intel 8228, TI
TIM8228)
read-only memory with three-state
-438 System Controller for 8080A (74S438 outputs
is equivalent to Intel 8238, TI
-472 Programmable read-only memory
TIM8238)
-440 Quad Tridirectional Bus Transceiver
-473 Quad D Flip-Flop with Three-state
with Noninverted open collector
Outputs
outputs
-473 Programmable read-only memory
with Inverted open collector outputs
-474 Hex D Flip-Flop with Common Clear
with Noninverted three-state -474 Programmable read-only memory
outputs with open collector outputs
-443 Quad Tridirectional Bus Transceiver -475 Quad D Edge-Triggered Flip-Flop

with Inverted three-state outputs with Complementary Outputs and
Asynchronous Clear
with Inverted and Noninverted -475 Programmable read-only memory
three-state outputs with three-state outputs
-448 Quad Tridirectional Bus Transceiver -476 Presettable Decade (Bi-Quinary)

with Inverted and Noninverted open Counter/Latch
collector outputs -477 Presettable Binary Counter/Latch
-450 16-to-1 Multiplexer with Comple- -478 4-bit Parallel-Access Shift Register
mentary Outputs
-479 4-bit Parallel-Access Shift Register
-451 Dual 8-to-1 Multiplexer with Asynchronous Clear and
-452 Dual Decade Counter, Synchronous Complementary QD Outputs
-453 Dual Binary Counter, Synchronous -480 9-bit Odd/Even Parity bit Generator
(Motorola, "plain" TTL) and Checker
-453 Quad 4-to-1 Multiplexer -481 4-bit Arithmetic Logic Unit and
Function Generator
-454 Dual Decade Up/Down Counter,
Synchronous, Preset Input -481 4-bit Slice Processor Elements
-455 Dual Binary Up/Down Counter, -482 Lookahead Carry Generator

Synchronous, Preset Input -482 4-bit Slice Expandable Control
-456 NBCD (Natural Binary Coded Elements
Decimal) Adder -483 Dual Carry-Save Full adder
-460 Bus Transfer Switch -484 BCD to Binary Converter
-461 8-bit Presettable Binary Counter with -484 BCD-to-Binary Converter (mask
three-state outputs programmed SN74S371 ROM)
-462 Fiber-Optic Link Transmitter -485 Binary to BCD Converter
-463 Fiber-Optic Link Receiver -485 Binary-to-BCD Converter (mask
programmed SN74S371 ROM)
276
Appendix
-486 512-bit (64x8) Read-only memory -526 Fuse Programmable Identity
with open collector outputs Comparator, 16 Bit
-487 1024-bit (256x4) Read only memory -527 Fuse Programmable Identity
with open collector outputs Comparator, 8 Bit + 4 Bit conventio-
nal Identity Comparator
read-only memory with open -528 Fuse Programmable Identity
collector outputs Comparator, 12 Bit
-489 64-bit (16x4) RAM with Inverting -531 Octal Transparent Latch with 32 mA
three-state Outputs three-state outputs
-490 Synchronous Up/Down Decade -532 Octal Register with 32 mA
Counter three-state outputs
-490 Dual Decade Counter -533 Octal Transparent Latch with
Inverting Three-state logic outputs
-491 Synchronous Up/Down Binary
Counter -534 Octal Register with Inverting
three-state outputs
-491 10-bit Binary Up/Down Counter with
Limited Preset and three-state logic -535 Octal Transparent Latch with
outputs Inverting three-state outputs
-492 Synchronous Up/Down Decade -536 Octal Register with Inverting 32 mA
Counter with Clear three-state outputs
-493 Synchronous Up/Down Binary -537 BCD to Decimal Decoder with
Counter with Clear three-state outputs
-494 4-bit Bidirectional Universal Shift -538 1 of 8 Decoder with three-state
Register outputs
-495 4-bit Parallel-Access Shift Register -539 Dual 1 of 4 Decoder with three-state
outputs
-496 Presettable Decade Counter/Latch
-540 Inverting Octal Buffer with
-497 Presettable Binary Counter/Latch
three-state outputs
-498 8-bit Bidirectional Universal Shift
-541 Non-inverting Octal Buffer with
Register
three-state outputs
-498 8-bit Bidirectional Shift Register with
-543 Octal latched transceiver with dual
Parallel Inputs and three-state
enable; 3-state
outputs
-544 Octal D-type registered transceiver;
-499 8-bit Bidirectional Universal Shift
inverting; 3-state
Register with J-Not-K Serial Inputs
-555 1-of-4 decoder/demultiplexer
-508 8-bit Multiplier/Divider
-557 1-to-64 bit variable length shift
-511 BCD to 7-segment latch/decoder/
register
driver
-558 8-Bit by 8-Bit Multiplier with
-514 4-to-16 line decoder/demultiplexer
three-state outputs
with input latches
-560 4-bit Decade Counter with
-516 Binary up/down counter
three-state outputs
-517 Dual 64-bit static shift register
-561 4-bit Binary Counter with three-state
-518 Dual BCD counter outputs
-520 8-bit Comparator - as -521 but with -563 8-bit D-Type Transparent Latch with
different input circuit Inverting three-state outputs
-521 8-bit Comparator
277
Appendix

-564 8-bit D-Type Edge-Triggered Register -602 Dynamic Memory Refresh Controller,
with Inverting three-state outputs Cycle Steal and Burst Modes, for 4K
or 16K DRAMs (74LS602 is equivalent
-568 Decade Up/Down Counter with
to TI TIM99602)
three-state outputs
-603 Dynamic Memory Refresh Controller,
-569 Binary Up/Down Counter with
Cycle Steal and Burst Modes, for 64K
three-state outputs
DRAMs (74LS603 is equivalent to TI
-573 Octal D-Type Transparent Latch with TIM99603)
three-state outputs
-604 Octal 2-input Multiplexer with Latch,
-574 Octal D-Type Edge-Triggered High-Speed, with Three-state
Flip-flop with three-state outputs outputs (74LS604 is equivalent to TI
-575 Octal D-Type Flip-Flop with TIM99604)
Synchronous Clear, three-state -605 Octal 2-input Multiplexer with Latch,
outputs High-Speed, with open collector
-576 Octal D-Type Flip-Flop with inverting outputs (74LS605 is equivalent to TI
three-state outputs TIM99605)
-577 Octal D-Type Flip-Flop with -606 Octal 2-input Multiplexer with Latch,
Synchronous Clear, inverting Glitch-Free, with Three-state outputs
three-state outputs (74LS606 is equivalent to TI
TIM99606)
-580 Octal Transceiver/Latch with
inverting three-state outputs -607 Octal 2-input Multiplexer with Latch,
Glitch-Free, with open collector
-585 4-bit magnitude comparator
outputs (74LS607 is equivalent to TI
-589 8-bit Shift Register with Input Latch, TIM99607)
three-state outputs
-608 Memory Cycle Controller (74LS608 is
-590 8-Bit Binary Counter with Output equivalent to TI TIM99608)
Registers and three-state outputs
-610 Memory Mapper, Latched,
-592 Binary Counter with Input Registers Three-state Outputs (74LS610 is
-593 8-Bit Binary Counter with Input equivalent to TI TIM99610)
Registers and three-state outputs -611 Memory Mapper, Latched, open
-594 Serial-in Shift register with Output collector outputs (74LS611 is
Registers equivalent to TI TIM99611)
-595 Serial-in Shift register with Output -612 Memory Mapper, Three-state logic
Latches Outputs (74LS612 is equivalent to TI
TIM99612)
-596 Serial-in Shift register with Output
Registers and open collector outputs -613 Memory Mapper, open collector
outputs (74LS613 is equivalent to TI
-597 Serial-out Shift register with Input TIM99613)
Latches
-620 Octal Bus Transceiver, Inverting,
-598 Shift register with Input latches Three-state Outputs
-600 Dynamic Memory Refresh Controller, -621 Octal Bus Transceiver, Noninverting,
Transparent and Burst Modes, for 4K open collector outputs
or 16K DRAMs (74LS600 is equivalent
to TI TIM99600) -622 Octal Bus Transceiver, Inverting,
open collector outputs
-601 Dynamic Memory Refresh Controller,
Transparent and Burst Modes, for -623 Octal Bus Transceiver, Noninverting,
64K DRAMs (-LS601 is equivalent to Three-state outputs
TI TIM99601)
278
Appendix
-624 Voltage-Controlled Oscillator with -648 Octal Bus Transceiver/Latch/Multiple-
Enable Control, Range Control, xer with Inverting three-state
Two-Phase Outputs outputs
-625 Dual Voltage-Controlled Oscillator -649 Octal Bus Transceiver/Latch/Multiple-
with Two-Phase Outputs xer with Inverting open collector
outputs
-626 Dual Voltage-Controlled Oscillator
with Enable Control, Two-Phase -651 Octal Bus Transceiver/Register with
Outputs Inverting three-state outputs
-627 Dual Voltage-Controlled Oscillator -652 Octal Bus Transceiver/Register with
Noninverting three-state outputs
-628 Voltage-Controlled Oscillator with
Enable Control, Range Control, Exter- -653 Octal Bus Transceiver/Register with
nal Temperature Compensation, and Inverting three-state and open
Two-Phase Outputs collector outputs
-629 Dual Voltage-Controlled Oscillator -654 Octal Bus Transceiver/Register with
with Enable Control, Range Control Noninverting three-state and open
collector outputs
-630 16-bit Error Detection and Correction
(EDAC) with three-state outputs -657 Octal transceiver with parity
generator/checker; 3-state
(EDAC) with open collector outputs -658 Octal Bus Transceiver with Parity,
Inverting
(EDAC) -659 Octal Bus Transceiver with Parity,
Noninverting
-638 Octal Bus Transceiver with Inverting
three-state outputs -664 Octal Bus Transceiver with Parity,
Inverting
Noninverting three-state outputs -665 Octal Bus Transceiver with Parity,
Noninverting
three-state outputs -668 Synchronous 4-bit Decade Up/Down
Counter
Noninverting open collector outputs -669 Synchronous 4-bit Binary Up/Down
Counter
open collector outputs -670 4 by 4 Register File with three-state
outputs
-643 Octal Bus Transceiver with Mix of
Inverting and Noninverting -671 4-bit Bidirectional Shift register/
three-state outputs Latch /Multiplexer with three-state
outputs
-644 Octal Bus Transceiver with Mix of
Inverting and Noninverting open -672 4-bit Bidirectional Shift register/
collector outputs Latch/Multiplexer with three-state
outputs
-645 Octal Bus Transceiver
-673 16-bit Serial-in Serial-Out Shift
-646 Octal Bus Transceiver/Latch/Multiple-
register with Output Storage
xer with Noninverting three-state
Registers, three-state outputs
outputs
-674 16-bit Parallel-in Serial-out Shift
-647 Octal Bus Transceiver/Latch/Multiple-
register with three-state outputs
xer with Noninverting open collector
outputs -677 16-bit Address Comparator with
Enable
279
Appendix

-678 16-bit Address Comparator with -698 4-bit Decimal Counter/Register/
Latch Multiplexer with Synchronous Reset,
three-state outputs
-679 12-bit Address Comparator with
Latch -699 4-bit Binary Counter/Register/
Multiplexer with Synchronous Reset,
-680 12-bit Address Comparator with
three-state outputs
Enable
-716 Programmable Decade Counter
-681 4-bit Parallel Binary Accumulator
(-LS716 is equivalent to Motorola
-682 8-bit Magnitude Comparator MC4016)
-683 8-bit Magnitude Comparator with -718 Programmable Binary Counter
open collector outputs (74LS718 is equivalent to Motorola
-684 8-bit Magnitude Comparator MC4018)
-685 8-bit Magnitude Comparator with -724 Voltage Controlled Multivibrator

open collector outputs -740 Octal Buffer/Line Driver, Inverting,
-686 8-bit Magnitude Comparator with three-state outputs
Enable -741 Octal Buffer/Line Driver, Noninver-
-687 8-bit Magnitude Comparator with ting, three-state outputs, Mixed
Enable enable polarity
-688 8-bit Equality Comparator -744 Octal Buffer/Line Driver, Noninver-

ting, three-state logic outputs
-689 8-bit Magnitude Comparator with
open collector outputs -748 8 to 3-line priority encoder
-690 4-bit Decimal Counter/Latch/ -779 8-bit bidirectional binary counter

Multiplexer with Asynchronous (3-State)
Reset, Three-State Outputs -783 Synchronous Address Multiplexer
-691 4-bit Binary Counter/Latch/ (74LS783 is equivalent to Motorola
Multiplexer with Asynchronous MC6883)
Reset, Three-State Outputs -790 Error Detection and Correction
-692 4-bit Decimal Counter/Latch/ (EDAC)
Multiplexer with Synchronous Reset, -794 8-Bit Register with Readback
Three-state Outputs
-795 Octal Buffer with Three-state logic
-693 4-bit Binary Counter/Latch/ outputs (74LS795 is equivalent to
Multiplexer with Synchronous Reset, 81LS95)
Three-state Outputs
-694 4-bit Decimal Counter/Latch/ outputs (74LS796 is equivalent to
Multiplexer with Synchronous and 81LS96)
Asynchronous Resets, three-state
outputs
outputs (74LS797 is equivalent to
-695 4-bit Binary Counter/Latch/ 81LS97)
Multiplexer with Synchronous and
Asynchronous Resets, three-state
outputs (74LS798 is equivalent to
outputs
81LS98)
-696 4-bit Decimal Counter/Register/
-804 Hex 2-input NAND Drivers
Multiplexer with Asynchronous
Reset, three-state outputs -805 Hex 2-input NOR Drivers
-697 4-bit Binary Counter/Register/ -808 Hex 2-input AND Drivers
Multiplexer with Asynchronous
Reset, three-state outputs
280
Appendix
-821 10-bit D-type flip-flop; positive-edge -1035 hex noninverting buffers with
trigger; 3-state open-collector outputs
-823 9-bit D-type flip-flop with 5 V -1403 3.3 V combined 8-bit bus receiver
tolerant inputs/outputs; positive and 4-bit bus driver
edge-trigger; 3-state
-2241 3.3V Octal buffer/line driver with 30
-827 10-bit buffer/line driver; non-inver- Ohm series termination resistors;
ting; 3-state 3-State
-0832 Low-power 3-input AND-OR gate -2244 Octal buffer/line driver with 30 Ω
series termination resistors (3-State)
-832 Hex 2-input OR Drivers
-2245 Octal transceiver with direction pin
-841 10-bit transparent latch with 5 V tole-
and 30 Ohm series termination
rant inputs/outputs; 3-state
resistors (3-State)
-848 8 to 3-line Priority Encoder with
-2952 Octal registered transceiver with 5 V
three-state outputs
tolerant inputs/outputs; 3-state
-873 Octal Transparent Latch
-2960 Error Detection and Correction
-874 Octal D-Type Flip-flop (EDAC) (74F2960 is equivalent to
-876 Octal D-Type Flip-flop with Inverting AMD Am2960)
Outputs -2961 EDAC Bus Buffer, Inverting
-878 Dual 4-bit D-Type Flip-flop with -2962 EDAC Bus Buffer, Noninverting
Synchronous Clear, Noninverting
-2968 Dynamic Memory Controller
three-state outputs
-2969 Memory Timing Controller for use
-879 Dual 4-bit D-Type Flip-flop with
with EDAC
Synchronous Clear, Inverting
three-state outputs -2970 Memory Timing Controller for use
without EDAC
-880 Octal Transparent Latch with
Inverting Outputs -3037 Quad 2-input NAND 30Ohm driver
-882 32-bit Lookahead Carry Generator -3125 Quadruple FET bus switch
-885 Low-power dual function gate -3126 Quad FET bus switch
-888 8-bit Slice Processor -3157 2-channel analog multiplexer/
demultiplexer
-894 12-stage shift-and-store register LED
driver -3208 Low-power 3-input OR-AND gate
-899 9-bit dual latch transceiver with 8-bit -3244 Octal bus switch with quad output
parity generator/checker (3-State) enables
-926 4-digit counter/display driver -3245 Octal bus switch
-935 3.5-digit Digital Voltmeter (DVM)
support chip for Multiplexed -3251 1-of-8 FET multiplexer/demultiplexer
7-segment displays (MM-C935 = AD- -3253 Dual 1-of-4 FET multiplexer/
D3501CCN) demultiplexer
-936 3.75-digit Digital Voltmeter (DVM) -3257 Quad 1-of-2 multiplexer/demultiple-
support chip for Multiplexed xer
7-segment displays (MM74C936 = AD-
-3306 Dual bus switch
D3701CCN)
-3384 10-bit bus switch with 5-bit output
-1005 hex inverting buffer with open-col-
enables
lector output
-3861 10-bit bus switch with output enable
-4002 Dual 4-Input NOR gate
281
Appendix

-4015 Dual 4-bit shift registers -4316 Quad analog switch
-4016 Quadruple bilateral switches -4351 8-channel analog multiplexer/
demultiplexer with latch
-4017 5-Stage ÷10 Johnson Counter
-4353 Triple 2-channel analog multiplexer/
-4024 7 Stage Ripple Carry Binary Counter
demultiplexer with latch
-4028 BCD to Decimal Decoder
-4511 BCD to 7-Segment Decoder
-4040 12-stage binary ripple counter
-4046 Phase-locked loop and voltage-cont- with input latches
rolled oscillator
-4049 Hex Inverting Buffer with input latches; inverting
-4050 Hex buffer/converter (non-inverting) -4520 Dual 4-bit Synchronous Binary
-4051 High-Speed CMOS Logic 8-Channel Counter
Analog Multiplexer/Demultiplexer -4538 Dual Retriggerable Precision
-4052 Dual 4-Channel Analog Multiplexer/ Monostable Multivibrator
Demultiplexers -4851 8-channel analog multiplexer/
-4053 Triple 2-Channel Analog Multiplexer/ demultiplexer with injection-current
Demultiplexers effect control
-4059 Programmable Divide-by-N Counter -4852 Dual 4-channel analog multiplexer/

demultiplexer with injection-current
-4060 14-stage binary ripple counter with
effect control
oscillator
-5555 Programmable delay timer with
-4066 Quad bilateral switches
oscillator
-4067 16-Channel Analog Multiplexer/
-6323 Programmable ripple counter with
Demultiplexer
oscillator; 3-state
-4075 Triple 3-input OR gate
-7007 hex buffer (like 7407, however
-4078 8-Input OR/NOR gate push-pull outputs)
-4094 8-bit Three-state Shift Register/Latch -7014 Hex non-inverting precision
-4245 Octal dual supply translating Schmitt-trigger
transceiver; 3-state -7266 Quad 2-input XNOR gate (Exclusive
NOR, Equivalence test)
282
Output Drive Current by Logic Family
Appendix
Standby Current Max Drive
Logic Family Supply Voltage
µA mA
AXP 0.7–2.75 0.6 8
AUP 0.8–3.6 0.9 4
LV 1.0–3.6 20 8
AVC 1.2–3.3 20 8
LVC 1.2–3.6 20 24
ALVC 1.2–3.6 40 24
AHC 2.0–6.0 40 8
HC 2.0–6.0 80 8
ALVT 2.3–3.6 90 64
LVT 2.7–3.6 120–190 64
FAST 4.5–5.5 90 24
ABT 4.5–5.5 250 64
4.5–5.5
NPIC 200 100
(LED output to 33 V)
3 (gates, LED
HEF 5.0–15.0 600
output to 20 mA)
Common Package Suffix by Company

Nexperia
Competitor Standard Nexperia Package
Suffix Competitor Suffix HEF Suffix Name SOT #
DW Diodes Inc GW SC88 363
FW4 Diodes Inc GF XSON6 891
FZ4 Diodes Inc GM XSON6 886
S14 Diodes Inc D T SO14 108
SE Diodes Inc GW SC70 353
T14 Diodes Inc PW TT TSSOP14 402
W5 Diodes Inc GV SO5 753
BQ Fairchild (ON Semi) BQ DHVQFN14 762
CM Fairchild (ON Semi) D T SO14 108
CN Fairchild (ON Semi) N P DIP14 27
FH(X) Fairchild (ON Semi) GF XSON8 1089
G Fairchild (ON Semi) EC LFBGA96 536
G Fairchild (ON Semi) EC LFBGA114 537
283
Appendix
Nexperia
K8 Fairchild (ON Semi) DC VSSOP8 765
KX8 Fairchild (ON Semi) GD XSON8U 996
L6 Fairchild (ON Semi) GM XSON6 886
L8 Fairchild (ON Semi) GM XQFN8U 902
M Fairchild (ON Semi) D SO8 96
M Fairchild (ON Semi) D T SO14 108
M5 Fairchild (ON Semi) GV SO5 753
ME Fairchild (ON Semi) DL SSOP48 370
ME Fairchild (ON Semi) DL SSOP56 371
MEA Fairchild (ON Semi) DL SSOP48 370
MEA Fairchild (ON Semi) DL SSOP56 371
MSA Fairchild (ON Semi) DB SSOP20 339
MT Fairchild (ON Semi) DGG TSSOP48 362
MT Fairchild (ON Semi) DGG TSSOP56 364
MTC Fairchild (ON Semi) PW TSSOP24 355
MTC Fairchild (ON Semi) PW TT TSSOP20 360
MTC Fairchild (ON Semi) PW TSSOP8 530
MTD Fairchild (ON Semi) DGG TSSOP48 362
MX Fairchild (ON Semi) D SO16 162
N Fairchild (ON Semi) N P DIP14 27
N Fairchild (ON Semi) N DIP24 101
N Fairchild (ON Semi) N DIP28 117
NT Fairchild (ON Semi) N DIP24 101
P5 Fairchild (ON Semi) GW SC70 353
P6 Fairchild (ON Semi) GW SC88 363
P6X Fairchild (ON Semi) GW SC88 363
284
Appendix
Nexperia
PC Fairchild (ON Semi) N P DIP14 27
PC Fairchild (ON Semi) N DIP28 117
QSC Fairchild (ON Semi) DK SSOP24 556
QSC Fairchild (ON Semi) DS SSOP16 519
QSC Fairchild (ON Semi) DS SSOP20 724
SC Fairchild (ON Semi) D SO8 96
SC Fairchild (ON Semi) D T SO14 108
SC Fairchild (ON Semi) D SO28 136
SPC Fairchild (ON Semi) N DIP24 101
T Fairchild (ON Semi) DGG TSSOP56 364
WM Fairchild (ON Semi) D SO28 136
WM Fairchild (ON Semi) D T SO16 162
WM Fairchild (ON Semi) D T SO20 163
BF IDT EC LFBGA96 536
CD IDT N P DIP20 146
DC IDT D SO8 96
DC IDT D T SO14 108
DJ IDT DGV TSSOP48 480
PA IDT DGG TSSOP48 362
PA IDT DGG TSSOP56 364
PC IDT DK SSOP24 556
PC IDT DS SSOP16 519
PC IDT DS SSOP20 724
PF IDT DGV TSSOP48 480
PF IDT DGV TSSOP56 481
PG IDT PW TSSOP24 355
PG IDT PW TT TSSOP20 360
PS IDT D T SO24 137
PS IDT D T SO20 163
285
Appendix
Nexperia
PV IDT DL SSOP48 370
PV IDT DL SSOP56 371
PY IDT DB SSOP20 339
2G On Semi DB TS SSOP16 338
AMX On Semi GM XSON6 886
CMX On Semi GF XSON6 891
CMX On Semi GF XSON8 1089
CPG On Semi N P DIP14 27
D On Semi D SO8 96
D On Semi D T SO14 108
D On Semi D SO28 136
D On Semi PW TSSOP8 530
DF On Semi GW SC88 363
DFT On Semi GW SC70 353
DG On Semi D T SO14 108
DR2G On Semi D SO20 163
DT On Semi DGG TSSOP48 362
DT On Semi PW TSSOP24 355
DT On Semi PW TT TSSOP14 402
DTT On Semi GV SO5 753
DW On Semi D T SO16 162
DWR2G On Semi D SO20 163
EP On Semi GM XQFN10U 1049
MN On Semi BQ DHVQFN16 763
MN On Semi BQ DHVQFN20 764
NG On Semi N P DIP14 27
NG On Semi N DIP24 101
286
Appendix
Nexperia
NG On Semi N CDIP28 135
OM On Semi GU-16 XQFN16 1161
P On Semi N P DIP14 27
P On Semi N DIP28 117
QZ On Semi DK SSOP24 556
QZ On Semi DS SSOP16 519
QZ On Semi DS SSOP20 724
SQL On Semi GW SC70 353
SQL On Semi GW SC88 363
US On Semi DC VSSOP8 765
USGH On Semi DC VSSOP8 765
CM Renesas GW SC70 353
CM Renesas GW SC88 363
P Renesas N P DIP14 27
P Renesas N DIP24 101
P Renesas N DIP28 117
P Renesas N CDIP28 135
RP Renesas D SO8 96
RP Renesas D T SO14 108
RP Renesas D SO28 136
T Renesas DGG TSSOP48 362
T Renesas DP TSSOP8 505
287
Appendix
Nexperia
T Renesas PW TSSOP24 355
T Renesas PW TT TSSOP20 360
US Renesas DC VSSOP8 765
B1R ST Micro N P DIP14 27
BEY ST Micro N P DIP14 27
BEY ST Micro N P DIP16 38
BM1 ST Micro D T SO14 108
C ST Micro GW SC70 353
DTR ST Micro GM XSON6 886
DTR ST Micro PW TT TSSOP20 360
MO13 ST Micro D T SO14 108
MTR ST Micro D T SO14 108
RM13 ST Micro D T SO14 108
STR ST Micro GV SO5 753
TTR ST Micro DGG TSSOP48 362
TTR ST Micro PW TT TSSOP20 360
D TI D SO8 96
288
Appendix
Nexperia
D TI D T SO14 108
D TI D T SO16 162
DA TI DR TSSOP32 487
DAE TI DR TSSOP32 487
DB TI DB SSOP14 337
DB TI DB TS SSOP16 338
DB TI DB SSOP20 339
DB TI DB SSOP24 340
DB TI DB SSOP28 341
DBQ TI DS SSOP16 519
DBV TI GV SO5 753
DCK TI GW SC70 353
DCK TI GW SC88 363
DCT TI DP TSSOP8 505
DCU TI DC VSSOP8 765
DCU TI GD XSON8U 996
DDC TI GV SO5 753
DDU TI DC VSSOP8 765
DGG TI DGG TSSOP48 362
DGV TI DGV TSSOP48 480
DGV TI DGV TSSOP56 481
DL TI DL SSOP48 370
DL TI DL SSOP56 371
DPW TI GX X2SON5 1226
DQE TI GF XSON8 1089
DQE TI GS XSON8 1203
DQM TI GM 1309
DRY TI GM XSON6 886
DSF TI GS XSON6 1202
DW TI D SO28 136
DW TI D T SO24 137
DW TI D T SO16 162
DW TI D T SO20 163
E TI N P DIP14 27
E TI N P DIP16 38
289
Appendix
Nexperia
E TI N P DIP24 101
E TI N DIP28 117
E TI N P DIP20 146
F TI N CDIP28 135
G TI DG TVSOP80 647
G TI DGG TSSOP48 362
GKE TI EC LFBGA96 536
GKF TI EC LFBGA114 537
GQL TI EV VFBGA56 702
J TI N CDIP28 135
L8 TI GM XQFN8U 902
M TI D SO8 96
M TI D T SO14 108
M TI D SO28 136
M TI D T SO24 137
M TI D T SO16 162
M TI D T SO16 162
M TI D T SO20 163
M96 TI D SO16 162
N TI N P DIP14 27
N TI N P DIP16 38
N TI N P DIP24 101
N TI N DIP24 101
N TI N DIP28 117
N TI N P DIP20 146
NE TI N P DIP16 38
NT TI N DIP24 101
PW TI PW TSSOP24 355
PW TI PW TT TSSOP20 360
PW TI PW TSSOP8 530
PW TI PW TSSOP10 552
RHL TI BQ DHVQFN24 815
RSE TI GM XQFN8U 902
RSV TI GU-16 XQFN16 1161
RSW TI GU UQFN 1160
290
Appendix
Nexperia
RUT TI GU-12 1174
TK TI TK HVSON10 650
TPA TI DGG TSSOP48 480
TPV TI DL SSOP56 371
YEB TI UK WLCSP4 n/a
YEC TI UK WLCSP6 n/a
YEG TI UK WLCSP12 n/a
YZB TI UK WLCSP4 n/a
YZC TI UK WLCSP6 n/a
YZG TI UK WLCSP12 n/a
YZP TI GM XSON6 886
YZP TI GT XSON8 833
YZT TI UK WLCSP12 n/a
ZKE TI EC LFBGA96 536
ZKF TI EC LFBGA114 537
ZQL TI EV VFBGA56 702
BF Toshiba D T SO14 108
BP Toshiba N P DIP14 27
BP Toshiba N P DIP16 38
F Toshiba GV SO5 753
FE Toshiba GW SC88 363
FK Toshiba DC VSSOP8 765
FN Toshiba D T SO14 108
FN Toshiba D T SO16 162
FS Toshiba DB SSOP24 340
FS Toshiba PW TSSOP24 355
FT Toshiba DB SSOP14 337
FT Toshiba DB TS SSOP16 338
FT Toshiba DB SSOP20 339
FT Toshiba DGG TSSOP48 362
FT Toshiba DGG TSSOP56 364
FT Toshiba DL SSOP48 370
FT Toshiba DL SSOP56 371
FT Toshiba PW TT TSSOP20 360
291
Appendix
Nexperia
FTG Toshiba HR HXQFN16U 1039
FU Toshiba GW SC70 353
FU Toshiba GW SC88 363
FW Toshiba D SO8 96
FW Toshiba D SO28 136
FW Toshiba D T SO16 162
P Toshiba N P DIP14 27
P Toshiba N DIP24 101
Competitor Logic Family to Nexperia Logic Family Cross Reference

Competitor Nexperia
Logic Logic
Competitor Family Family Similarity Comments
Diodes Inc AHC AHC exact
Diodes Inc AHCT AHCT exact
Diodes Inc AUP AUP exact
Diodes Inc AVC AVC exact
Diodes Inc HC HC exact
Diodes Inc HCT HCT exact
Diodes Inc LV LV exact
Diodes Inc LVC LVC exact
Diodes Inc LVT LVT exact
Fairchild (ON Semi) ABT ABT exact
Fairchild (ON Semi) AC AHC near AHC is only 8 mA vs 24 mA drive
current, but lower noise. No clamp
diode in AHC makes it 5 V tolerant, AC
is not. AHC has wider temp range
Fairchild (ON Semi) ACT AHCT near AHCT is only 8mA vs 24 mA drive
diode in AHCT makes it 5 V tolerant,
AC is not. AHCT has wider temp range
Fairchild (ON Semi) ALS ABT near ABT is similar speed and VCC range
but only half the drive current of ALS
Fairchild (ON Semi) AS ABT near Similar speed, similar drive currents
292
Appendix
Competitor Nexperia
Logic Logic
Fairchild (ON Semi) C HEF near ex: 74C74. VCC = 3–15 V, tpd = 70–
140 ns, 2 mA output
Fairchild (ON Semi) CD4K HEF exact
Fairchild (ON Semi) F F exact
Fairchild (ON Semi) FSA LVC near family name for switches, same as
NC7WB. 1.65–5.5 VCC
Fairchild (ON Semi) FST CBT exact
Fairchild (ON Semi) FXLH AUP exact
Fairchild (ON Semi) FXLP AUP1T near
Fairchild (ON Semi) HC HC exact
Fairchild (ON Semi) HCT HCT exact
Fairchild (ON Semi) LCX/H LVC near LVC is wider operating VCC, slightly
faster Tpd. Both are 24 mA drive
Fairchild (ON Semi) LS ABT near ABT is faster (1–4 vs 2–10 ns) , higher
driver current (64/32 vs 24/15 mA
drive)
Fairchild (ON Semi) LVT/H LVT exact
Fairchild (ON Semi) LVX LV near LVX is wider operating range, LV is
not 5 V input tolerant
Fairchild (ON Semi) NC7NZ LVC3G exact
Fairchild (ON Semi) NC7S AHC1G near “S” speed logic. Single gate,
2.0–6.0 V, 2 mA drive, 3.5 ns. AHC is
8 mA, 5 nS, 2–6 VCC: not quite as fast
Fairchild (ON Semi) NC7SB LVC1G near Single channel switch process crosses
to LVC switches. Same as Fairchild FSA
family. Ex: 3157
Fairchild (ON Semi) NC7SP AUP1G exact Single gate version
Fairchild (ON Semi) NC7ST HC1G near Single gate. “compatible with HC but
half drive current” per Fairchild site
Fairchild (ON Semi) NC7SV AUP1G near Single gate. 1–12 nS, 24 mA drive.
Similar to AUP but more drive
current. FSC calls SP a “cross” for SV.
AUP is slightly better VCC
Fairchild (ON Semi) NC7SZ LVC1G exact Single gate. Both families are
1.65–5.5 V VCC with 24 mA drive.
Fairchild (ON Semi) NC7WB LVC2G near Switch process crosses to LVC
switches. Same as Fairchild FSA family
Fairchild (ON Semi) NC7WP AUP2G near Dual gate devices. AUP is slightly
better VCC range, higher drive
current (4 mA vs 2.6), same speeds.
0.9–3.6 V, 2–27 nS, 2.6 mA drive
Fairchild (ON Semi) NC7WT HC2G exact Dual gate variant
293
Appendix
Competitor Nexperia
Logic Logic
Fairchild (ON Semi) NC7WV AUP2G near Dual gate. AUP is slightly better VCC.
WV family has Schmitt trigger inputs.
Mostly dual gates
Fairchild (ON Semi) NC7WZ LVC2G near Dual gate. Both families are
1.65–5.5 V VCC with 24 mA drive. WZ
family has Schmitt trigger inputs.
Dual gate devices
Fairchild (ON Semi) VCX/H ALVCH exact
Fairchild (ON Semi) VHC/T AHC/T near Traditionally crosses to HC. AHC is
slightly less power. Note that
Nexperia does make a limited number
of VHC devices also
IDT ALVC ALVC exact
IDT ALVC/H ALVC/H exact
IDT CBTLV CBTLV exact
IDT FCT (3V) LVT exact
IDT FCT (5V) ABT exact
IDT LVC LVC exact
IDT QS3VH LVC near QS3VH is a fast bus process similar to
Nexperia LVC
IDT VH LVC near VH = 2.3–3.6 VCC, V = 1.2–3.6 VCC, 5 V
tolerant
On Semi 14xxx HEF exact No differences but name
On Semi AC AHC near 5 nS tPD, 24 mA output. AHC will work
for all but high power drive
applications
On Semi ACT AHCT near AHCT is only 8 mA vs 24 mA drive
On Semi CBTL CBTL exact Bus switch process
On Semi HC HC exact
On Semi HCT HCT exact
On Semi LCX LVC near LVC is wider operating VCC, slightly
On Semi LVX LV near LV is wider operating range, LV is not
5V input tolerant
On Semi NL17SG AUP near 0.9–3.6 V, 4.6 V tolerant pins
ON Semi NL17SH HC exact tpd = 3 nS, 2–5 V VCC, single gate.
Example NL17SH00
ON Semi NL17SHT HCT exact
On Semi NL17SV AUP exact
294
Appendix
Competitor Nexperia
Logic Logic
On Semi NL17SZ LVC exact
On Semi NL27WZ LVC exact
On Semi NL37WZ LVC3G exact Ex: Triple buffer
On Semi NL7SZ LVC exact
On Semi NL7WB LVC exact
On Semi NLSX NTS exact Dual voltage bidirectional level
translators
On Semi NLU AHCT near 5.5 V VCC, TTl outputs, 8 mA drive,
3.8 ns prop delay, overvolt tolerant
inputs
ON Semi NLV HEF near HEF with Q100 grade
On Semi NLX LVC exact For 74LVC2G14, etc
On Semi VCX ALVCH exact
On Semi VHC AHC near Traditionally crosses to HC. AHC is
of VHC devices also
On Semi VHCT AHCT near Traditionally crosses to HC. AHC is
of VHC devices also
Pericom STX AHC1G exact ex P174STX1G08
Renesas AC AHC near 5 nS tPD, 24 mA output. AHC will work
applications
Renesas ACT AHCT near 5 nS tPD, 24 mA output. AHC will work
applications
Renesas ALVC ALVC exact per Renesas website
Renesas BC ABT exact 5 nS tPD, 15/64 mA output
Renesas CBT CBT exact
Renesas HC HC exact
Renesas HCT HCT exact
Renesas LD HEF near For LED drive, up to 30 V, 200 mA
drive. Similar to HEF but note that
some are even higher voltage.
Renesas LS ABT near ABT is faster(1–4 vs 2–10 ns) , higher
driver current (64/32 vs 24/15 mA
drive)
Renesas LV LV exact For 1 and 2 gate devices only (per
Renesas website)
295
Appendix
Competitor Nexperia
Logic Logic
Renesas LV-A LV, AHC near Renesas declares Nexperia LV and
AHC are both crosses to LV-A
Renesas LVC-B LVC exact From Renesas website
ST Micro AC AHC near 5 nS tPD, 24 mA output. AHC will work
applications
ST Micro ACT AHCT near AHCT is only 8 mA vs 24 mA drive
ST Micro ALVC ALVC exact
ST Micro AUP AUP exact
ST Micro HC HC exact
ST Micro HCF HEF exact
ST Micro HCT HCT exact
ST Micro LCX LVC near LVC is wider operating VCC, slightly
faster Tpd. Both are 24 mA drive.
“Speed of AC/ACT, less power”
ST Micro LVC LVC exact
ST Micro LVX LV near LV is wider operating range, LV is not
5 V input tolerant
ST Micro V LVC near V = (VCC = 2.5 V, Tpd = 4.8 ns, 8 mA
drive, overvolt tolerant), LVC=(1.65–
5.5 VCC, Tpd = 3.7 ns, 24 mA drive,
overvolt tolerant). 1G, 2G variety
ST Micro VCX ALVCH exact
ST Micro VHC AHC exact
ST Micro VHCT AHCT exact
TI ABT ABT exact
TI AHC AHC exact
TI AHCT AHCT exact
TI ALS ABT near ABT is similar speed and VCC range
but only half the drive current of ALS
TI ALVC ALVC exact
TI ALVT ALVT exact
TI AUC AUP near AUP is similar to AUC. A bit slower, a
bit less power.
TI AUP AUP exact
TI AVC AVC exact
TI CBT CBT exact
TI CBTLV CBTLV exact
296
Appendix
Competitor Nexperia
Logic Logic
TI CD4000 HEF exact No differences but name
TI F F exact
TI FCT ABT exact
TI HC HC exact
TI HCT HCT exact
TI LV LV exact
TI LVC LVC exact
TI LVT LVT exact
Toshiba AC AHC near 5 nS tPD, 24 mA output. AHC will work
applications
Toshiba ACT AHCT near AHCT is only 8 mA vs 24 mA drive
Toshiba HC HC exact
Toshiba HCT HCT exact
Toshiba LCX LVC near LVC is wider operating VCC, slightly
Toshiba LVX LV near LV is wider operating range, LV is not
5 V input tolerant
Toshiba TC4 HEF exact example TC4049
Toshiba TC4xxx HEF exact
Toshiba TC7MA ALVCH near Obsolete family number. Has been
replaced with newer family name
Toshiba TC7MET AHCT near Obsolete family number. Has been
Toshiba TC7MH AHC exact Obsolete family number. Has been
Toshiba TC7MZ LVC near Obsolete family number. Has been
Toshiba TC7PA LVC exact Single and dual gate VCX parts.
1.8–3.6 VCC
Toshiba TC7PG AUP near 0.9–3.6 VCC dual gate, 8 ma drive,
2 nS. Closest to AUC family: AUP has
less drive current
Toshiba TC7PH AHC near 2–5.5 VCC, 8 mA drive 5 nS. 5.3 nS.
Closest to AHC
Toshiba TC7PH AHC near Obsolete family number. Has been
297
Appendix
Competitor Nexperia
Logic Logic
Toshiba TC7S AHC near 2G Dual Gate devices in HC family.
2–6 VCC, 2.6 mA drive, 5 nS. Similar to
AHC
Toshiba TC7SA LVC exact 1.8–3.6 VCC, 24 mA. 2.8–7.4 nS “VCX
equivalent” per Toshiba
Toshiba TC7SET AHCT near 1 gate devices 4.5–5.5 VCC, 8 mA
drive, 5 nS. Closest to AHCT. HC is not
quite fast enough
Toshiba TC7SG AUP near 1 gate devices 0.9–3.6 VCC, 8 mA
drive, 2–5 nS. AUP has less drive
current, LV has drive but not speed.
Toshiba TC7SH AHC near 1G Single gate version of VHC family.
2–5.5 VCC, 8 mA drive, 4–5 nS
Toshiba TC7SZ LVC exact 1 gate devices of LCX family.
1.6–5.5 VCC, 32 mA drive, 2–3nS.
Toshiba TC7W HC near 2–6 VCC, 5 mA drive, dual gate,
<10 ns. AHC. Single gate version of
HCT logic
Toshiba TC7WG LV near LVP family 0.9–3.6 VCC, 8 mA drive,
2–3 nS. LV is a bit slower, AUP not as
much drive current. 1,2,3 G devices
Toshiba TC7WH AHC near 2 and 3 gate devices in VHCT family.
2–5.5 VCC, 8 mA drive, 3–5nS. 1,2,3
gates
Toshiba TC7WT HCT near High speed TTL input 4.5–5.5 VCC,
6mA drive, 15 nS.
Toshiba TC7WT HCT near Obsolete family number. Has been
replaced with newer
Toshiba TC7WZ LVC near SHS series. “Matches LCX performan-
ce”. 32 mA drive, 3 ns, 1.65–5.5. 1,2,3
gate devices. LVC VCC is not quite as
wide
Toshiba VCX ALVCH exact
Toshiba VHC AHC exact
Toshiba VHCT AHCT exact
298
Abbreviations
Abbreviations
299
ADC Analog to Digital Convertor ESD Electrostatic Discharge

Abbreviations
µF Micro Farad
AHCT Advanced High-speed Cmos
f Frequency
with Transistor–transistor
f−3dB Frequency with -3dB
logic voltages
attenuation/loss
ALVT Advanced Low-Voltage
FAQ Frequently Asked Questions
BiCMOS Technology
FET Field Effect Transistor
AND logical function
fi Input frequency
ANSI American National
FIFO first in first out
Standards Institute
fo Output frequency
ASIC Application-Specific
FPGA Field-Programmable Gate
Integrated Circuits
Array
AUP Advanced Ultralow Power
AVC Advanced Very-low-voltage
CMOS GND Supply ground reference
AXP Advanced eXtremely low level
voltage and Power GPIO General - Purpose Input/
Output
BBM Break Before Make

BiCMOS Bipolar Complementary HBM Human Body Model
Metal Oxide Semiconductor HCT High-speed Cmos with
Transistor – transistor logic
voltages
CDM Charged Device Model
Cl Load capacitance
CLK Clock I/O Input and Output
CMOS Complementary Metal IC Integrated Circuit
Oxide Semiconductor Icc Supply current
CP Clock Input Icch quiescent current when the
Cpd Equivalent power output is logic high
dissipation capacitance Iccl quiescent current when the
CS Switch Capacitance output is logic low
Cs(on) On-state capacitance ID Drain current
IEC International
Electrotechnical
D-Flipflop Data or Delay Flipflop
Commission
DIR Direction
IEEE Institute of Electrical and
D-Latch Delay Latch
Electronics Engineers
Ignd Current in supply ground
pin
Iik Input clamping current
Il Input leakage current
300
Ioff Off state current Q Charge
Abbreviations
Iok Output clamping current Q100 Automotive Electronics
Istat Static supply current Council -Q100 qualification
specification
JEDEC Joint Electron Device

Engineering Council R&D Research and Development
Rcl Current Limiting Resistor
RF Radio Frequency
LVC Low Voltage
Ron Resistance of a transitor in
Complementary metal oxide
on-state
semiconductor
RPU Pull-up Resistor
LVT Low-Voltage BiCMOS
RS flip-flop Reset Set flip flop
Technology
SOC System On Chip

MBB Make before break
SP3T Single Pole Triple Throw
MCU Micro Controller Unit
SP8T Single pole 8 throw
(microcontroller)
SPDT Single Pole Double Throw
MOSFET Metal Oxide Semiconductor
SPST Single pole single throw
Field-Effect Transistor
MR Master Reset
Ten Enable time
Tf Fall time
NAND Not AND, logical function
Th Hold time
nF Nano Farad
THD Total Harmonic Distortion
NMOST N-channel Metal Oxide
Tj Junction temperature
Semiconductor Transistor
Tpd Propagation delay time
NOR NOT OR, logical function
Tphl Propagation delay time for
logic high to low transition
OE Output Enable Tplh Propagation delay time for
OR logical function logic low to high transition
OVT Over Voltage Tolerant Tr Rise time
Tsk Skew time
Tskhl Skew time for logic
PCB Printed Circuit Board
high to low transition
PD Power dissipation
Tsklh Skew time for logic
pF piko Farad
low to high transition
PMOST P-channel Metal Oxide
Tsu Setup time
Semiconductor Transistor
Tthl Fall time for logic
Ptot Total power dissipation
high to low transition
301
TTL Transistor Transistor Logic

Abbreviations
Ttlh Rise time for logic low to

high transition
Tw Pulse width time
US United States
VCC Supply Voltage

VEE Negative Supply Voltage
VGS Gate Source Voltage
Vi Input voltage
Vih Input voltage for a logic
high level signal
Vil Input voltage for a logic low
level signal
Vo Output voltage
VOH Output high voltage
VOL Output low voltage
VSS Ground voltage
VT Threshold Voltage
VT− Negative going threshold
voltage
VT+ Positive going threshold
voltage
XNOR Excusive- Not OR, logical

funtion
XOR Excusive-OR, logical funtion
Xtalk cross talk
ZL characteristic impedance
302
Index
Index
303
A I
Index
Absolute maximum rating . . . . . . . . . . 35 Input and Output levels . . . . . . . . . . . . 66

Analog switches . . . . . . . . . . . . . . . . . . . 33 Input stage current . . . . . . . . . . . . . . . . 43
AND gate . . . . . . . . . . . . . . . . . . . . . . . . . 26 Input transistion . . . . . . . . . . . . . . . . . . . 35
IOFF mechanism and purpose . . . . . . . . 79
B
Bi-directional translators . . . . . . . . . . . 70 L
BiCMOS . . . . . . . . . . . . . . . . . . . . . . . . 43, 50 Level shifting . . . . . . . . . . . . . . . . . . . . . . 66
Binary code . . . . . . . . . . . . . . . . . . . . . . . 22 Limiting Values . . . . . . . . . . . . . . . . . . . . 35
Boolean Algebra . . . . . . . . . . . . . . . . . . . 23 Logic Data sheet parameters . . . . . . . . 34
Bus Hold . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Lumped and distributed systems . . . . 84
Bus switches . . . . . . . . . . . . . . . . . . . . . . 34
M
C Malfunction . . . . . . . . . . . . . . . . . . . . . . . 35
CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Maximum frequency . . . . . . . . . . . . . . . 64
Conditions for Cpd test . . . . . . . . . . . . . 54 Meta stability . . . . . . . . . . . . . . . . . . . . . . 62
Cpd calculations . . . . . . . . . . . . . . . . . . . 49 Minority carriers . . . . . . . . . . . . . . . . . . . 42
Current limiting resistor . . . . . . . . . . . . 72
N
D NAND gate . . . . . . . . . . . . . . . . . . . . . . . . 27
D flip flop . . . . . . . . . . . . . . . . . . . . . . . . . 32 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Duty cycle considerations . . . . . . . . . . . 46 NOR gate . . . . . . . . . . . . . . . . . . . . . . . . . 29
Dynamic characteristics . . . . . . . . . . . . 38
Dynamic considerations . . . . . . . . . . . . 44 O
Dynamic power dissipation . . . . . . . . . 47 Open-drain outputs . . . . . . . . . . . . . . . . 74
OR gate . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
E Overvoltage tolerant inputs . . . . . . . . 73
Edge triggered . . . . . . . . . . . . . . . . . . . . 38
Examples of combinations P
of translation features . . . . . . . . . . . . 76 Power dissipation . . . . . . . . . . . . . . . . . . 42
Power dissipation calculations . . . . . . 51
F Power dissipation capacitance . . . 40, 48
Fall rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Propagation delay . . . . . . . . . . . . . . 38, 59
Flip flop . . . . . . . . . . . . . . . . . . . . . . . . . . 32
R
G Race condition . . . . . . . . . . . . . . . . . . . . . 59
Gate delay . . . . . . . . . . . . . . . . . . . . . . . . . 59 Recommended operating
Ground and VCC bounce . . . . . . . . . . . . 80 conditions . . . . . . . . . . . . . . . . . . . . . . . 35
Recovery time . . . . . . . . . . . . . . . . . . . . . 61
H RS flip flop . . . . . . . . . . . . . . . . . . . . . . . . 32
Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . 36
304
Index
Schmitt trigger . . . . . . . . . . . . . . . . . . . . 36
Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Slow input rise/fall time . . . . . . . . . . . . 46
Source Termination . . . . . . . . . . . . . . . . 84
Source termination . . . . . . . . . . . . . . . . 85
Static characteristics . . . . . . . . . . . . . . . 36
Static considerations . . . . . . . . . . . . . . . 42
Synchronous and
asynchronous logic . . . . . . . . . . . . . . . 58
T
Timing parameters of Flip Flops
and Latches . . . . . . . . . . . . . . . . . . . . . . 60
Transfer characteristic . . . . . . . . . . . . . . 36
Transient energy loss . . . . . . . . . . . . . . . 44
X
XNOR gate . . . . . . . . . . . . . . . . . . . . . . . . 31
XOR gate . . . . . . . . . . . . . . . . . . . . . . . . . . 30
305
Index
306
Legal information
Legal information
307
Definitions
Legal information
Draft — The document is a draft version only. The content is still under internal
review and subject to formal approval, which may result in modifications or
additions. Nexperia does not give any representations or warranties as to the
accuracy or completeness of information included herein and shall have no liability
for the consequences of use of such information.
Disclaimers
Limited warranty and liability — Information in this document is believed to be

accurate and reliable. However, Nexperia does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information. Nexperia takes no responsibility for the content in this document if
provided by an information source outside of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive, special or
consequential damages (including — without limitation — lost profits, lost savings,
business interruption, costs related to the removal or replacement of any products
or rework charges) whether or not such damages are based on tort (including
negligence), warranty, breach of contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’ aggregate and cumulative liability towards customer for the
products described herein shall be limited in accordance with the Terms and
conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes to

information published in this document, including without limitation specifications
and product descriptions, at any time and without notice. This document
supersedes and replaces all information supplied prior to the publication hereof.
Suitability for use — Nexperia products are not designed, authorized or warranted

to be suitable for use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction of an Nexperia product
can reasonably be expected to result in personal injury, death or severe property or
environmental damage. Nexperia and its suppliers accept no liability for inclusion
and/or use of Nexperia products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
308
Applications — Applications that are described herein for any of these products are
Legal information
for illustrative purposes only. Nexperia makes no representation or warranty that
such applications will be suitable for the specified use without further testing or
modification.
Customers are responsible for the design and operation of their applications and
products using Nexperia products, and Nexperia accepts no liability for any
assistance with applications or customer product design. It is customer’s sole
responsibility to determine whether the Nexperia product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs or
problem which is based on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third party customer(s).
Customer is responsible for doing all necessary testing for the customer’s
applications and products using Nexperia products in order to avoid a default of
the applications and the products or of the application or use by customer’s third
party customer(s). Nexperia does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein may be

subject to export control regulations. Export might require a prior authorization
from competent authorities.
Translations — A non-English (translated) version of a document is for reference

only. The English version shall prevail in case of any discrepancy between the
translated and English versions.
Trademarks
Notice: All referenced brands, product names, service names and trademarks are
the property of their respective owners.
309
Notes
For more information,
please visit:
www.nexperia.com
For sales offices addresses,

please check:
www.nexperia.com/about/worldwide-
locations/sales-offices.html

Copyright © Nexperia
October 2020
www.nexperia.com
ISBN 978-0-9934854-6-6
All rights reserved.

No part of this publication may be reproduced or
distributed in any form or by any means without
the prior written permission of the author.

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LOGIC

Design Engineer’s Guide

All rights reserved.

Ghislaine Jilisen Janssen

Vikram Singh Parihar

With an absolute focus on efficiency, Nexperia consistently produces

Nexperia Design Engineer’s Guides:

damage — supporting the design community in protecting applications and

Introducing the Logic Application Handbook

• In systems that use application-specific integrated circuits (ASICs),

• In mobile devices such as smartphones, tablets, and cameras,

• In external speakers and other high-end audio equipment logic buffers

Over the last 60 years, Nexperia — starting as Philips Semiconductors and then

Olaf Vogt Robby Ferdinandus

4.1 Synchronous and asynchronous logic������������������������������������������������������������������������� 58

5.1 Application requirements for interfacing������������������������������������������������������������������ 66

9.1 The HC/HCT/HCU Logic Family�����������������������������������������������������������������������������������165

• The addition of features in next generation products with lower power

To create a content suitable for application engineers using Nexperia’s logic

As well as power, timing behavior needs to be calculated and must be understood

Background information about package types, soldering and footprints are

Finally, frequently asked questions from customers are compiled in a chapter to

Logic basics, Generic Logic product properties

Logic basics, Generic Logic product properties

Table 1: Basic Boolean operations AND and OR

An additional very important Boolean operation is the inversion. It is quite simple as

Table 2: Boolean operation of Inversion

replaced by an addition and the operation ˄ (AND operation) by a multiplication.

The complementation rules are.

Logic basics, Generic Logic product properties

Table 3: Inverter or NOT Gate

Figure 2.1a | IEEE symbol of an Inverter Figure 2.1b | IEC symbol of an Inverter

2.2 Logic gates

In Figure 2.2 the symbols for a 2-input AND gate are depicted.

Table 4: 2-Input AND gate function table

Input A Input B Output Y

Logic basics, Generic Logic product properties

In Figure 2.3 the symbols for a 2-input NAND gate are depicted.

Table 5: 2-Input NAND gate function table

Input A Input B Output Y

In Figure 2.4 the symbols for a 2-input OR gate are depicted.

Table 6: 2-Input OR gate function table

Input A Input B Output Y

Figure 2.4a | IEEE symbol of an OR gate Figure 2.4b | IEC symbol of an OR gate

Logic basics, Generic Logic product properties

In Figure 2.5 the symbols for a 2-input NOR gate are depicted.

Table 7: 2-Input NOR gate function table

Input A Input B Output Y

Exclusive-OR (XOR) Gate

In Figure 2.6 the symbols for a 2-input XOR gate are depicted.

Table 8: 2-Input Exclusive-OR-Gate

Input A Input B Output Y

Logic basics, Generic Logic product properties

In Figure 2.7 the symbols for a 2-input XNOR gate are depicted.

Table 9: 2-Input Exclusive NOR-Gate

Input A Input B Output Y

2.3 Storage elements

There are several types of flipflops with different topologies.

Logic basics, Generic Logic product properties

4.1 Synchronous and asynchronous logic�� 58

5.1 Application requirements for interfacing�� 66

9.1 The HC/HCT/HCU Logic Family��165