DD - List of Topics

Download as docx, pdf, or txt
Download as docx, pdf, or txt
You are on page 1of 3

Module 1: Boolean Algebra

1. Number System Conversion


a) Binary to Other
b) Decimal to Other
2. 1s complement
3. 2s complement
4. Laws and Theorems of Boolean Algebra
5. Simplification of Boolean Algebra
6. Min Terms And Max Terms
7. Standard SOP and POS
8. Logic Gates - Basic, Universal, Exclusive - Symbol, TT, Logic Expression.
9. VHDL - Useful Theory and Lab

Module 2: Combinational Circuits


Part I

1. Simplification - Kmap (SOP-Σ -1- AND , POS-п - 0 - OR)


2 Variable, 3 variable, 4 variable, 5 variable
3 variable , 4 variable with don’t cares
2. Simplification - QM Method or Tabulation Method
3 Variable, 4 Variable
3. Conversion between SOP and POS
4. Hazards

Part II

1. Half Adders and Full Adders


2. Half Subtractor and Full Subtractor
3. 4 bit Binary Adder
4. Magnitude Comparator (1 bit, 2bit)
5. Multiplexer (2:1, 4:1, 8:1, 16:1)
6. Implementing a Mux using MEV technique
7. DeMultiplexer (2:1, 4:1, 8:1, 16:1)
8. Implementing 16:1 mux using 8:1 or 4:1 or 2:1 mux
9. Decoder (2to4, 3 to 8)
10. Encoder (4 to 2, 8 to 3)
11. Implementing decoders using FA, smaller decoders
12. Implementing decoders using given functions
13. Priority Encoder
14. Analysis of a given circuit
 Simplified Expression
 Truthtable
15. Design Procedure (TT, KMAP, EXP, CKT)
a) BCD to Excess 3
b) Design based on given condition

Module 3: Sequential Circuit

1. Differences
a) Combinational Vs Sequential
b) Synchronous Vs Asynchronous
c) Flipflop Vs Latch
d) Moore Model and Mealy Model
2. LATCHES
a) SR NAND LATCH
b) SR NOR LATCH
c) Gated SR LATCH
d) Gated D LATCH

3. FLIPFLOPS ( Circuit Diagram, Characaterstic Equation, Excitation Table, Truth table)


a) Edge Triggering
b) Symbols
c) SR FLIPFLOP
d) D FLIPFLOP
e) JK FLIPFLOP
f) T FLIPFLOP
g) Master Slave Flipflop
4. Asynchronous or Ripple Counter (2 bit, 3 bit, 4 bit)- ckt and timing diagram
Up, Down Counter,
BCD Ripple Counter
5. Synchronous Counters(2 bit, 3 bit, 4 bit) - ckt and timing diagram
Up, Down Counter,
6. Counter With Unused Counters
Mod Counters
7. Analysis of Sequential Circuit
a) State Equation
Mark all ip’s op’s and ps values
Characterstic eqn’s of the Flip flop
b) State Table
PS IP NS OP
c) State Diagram

8. Shift Registers (Circuit, Truthtable)


a) SISO
a) SIPO
b) PISO
c) PIPO

9. Shift Register Counters


A) Ring Counter
B) Johnson Counter

1) Approximate Weightages for Modules are as follows:


Module-1= 20%
Module-2= 40%
Module-3= 40%.

2) Question Paper consists of Three Parts. Part A, B & C

Part A consists of 24 MEMORY RECALL objective type MCQ questions (24Qx1M=24Marks)

Part B consistsof 4 THOUGHT PROVOKING Subjective type questions(4Qx10M=40Marks)


- No Choice

Part C consists of 4 PROBLEM SOLVING Subjective type questions (3Qx12M=36Marks)

Students shouldwrite Answers for Part-B & Part-C Questions, and upload the written answer Scripts
on EDHITCH in PDF form only.

You might also like