Vlsi Final Project

4-Bit Adder
GROUP-03
Submitted by:
GHSOH SAIKAT 13-23829-1
HASAN MD MEHIDI 17-35310-2
JAMAN ASFAQUR 17-35542-3
COURSE TEACHER : NIRJHOR TAHMIDUR ROUF

(Semester for Submission)
SPRING -2020
4-Bit Adder
Faculty © of Engineering, American International University – Bangladesh

Abstract
The project is to design a 4-bit adder, while taking care of
performance parameters: area, speed and power consumption,
the team has chosen to design according to the cost function:
Area*Delay*Power. The project is implemented in three phases:
simulation phase, and evaluation/reevaluation phase. The adder
circuit implemented as Ripple-Carry Adder (RCA), the team
added improvements to overcome the disadvantages of the RCA Figure 1: Gate level implementation 1 of the full adder
architecture, for instance the first 1-bit adder is a Half Adder,
which is faster and more power-efficient, the team was also
carefully choosing the gates to match the stated cost function.
Gates are implemented using different logic families, according
to each gate usage and functionality in the circuit in order to
achieve the desired performance. Transistor sizes are also
selected based upon simulation and optimization, to reach the
needed performance according to the specified cost function.
Introduction(Heading-1) Figure 2: Gate level implementation 2 of the full adder

The topic of the course project is to design a 4-bit adder in the
standard 0.25 um CMOS Technology. The main objectives of
the project is to minimize the total delay of the adder (i.e. the
worst case delay of the circuit), the area used to implement the
adder, and its average power consumption. That in mind, the
team was able to split the project in the simulation phase. The
team had to compare different adder defining the advantages
and disadvantages of each one in terms of area and delay to be
able to choose what could be the most efficient adder.compare Figure 3: Gate level implementation 3 of the full adder
the different logic families’ impleme-ntations for each gate,
Comparing these different implementations in terms of area
and finally decide on the proper logic family implementation
and delay, it was clear that implementation 1 will be too slow
for each gate in light of the project objectives stated and takes too much area, while the other 2 implementations do
beforehand. In the simulation phase, the team had to design not differ too much. However, as NAND gates can be
each gate separately and optimize it to achieve the optimum implemented using CMOS logic family without the need for
delay and power-co nsumption, and finally simulate the an inverter at the output, while AND and OR cannot, the team
whole 4-bit adder. The simulation phase concludes the project decided to choose implementation 2 to have the option of
by estimating the worst case delay of the 4-bit adder design using CMOS logic whenever it is needed without the need to
and the average power consumption of the circuit. use inverters.
Therefore, the final implementation of the full adder in this
Theory project is as follows:
The gate level implementation of the 4-bit ripple carry adder
is presented. After the group agreed on implementing ripple Sum = A XOR B XOR C
carry adder and mainly 3 implementations were compare. Carry out = (A NAND B) NAND [(A XOR B) NAND Cin]
Implementation 1 uses only NAND gates to implement the
logic of the full adder. Logic Families Comparison for XOR and NAND of
Implementation 2 uses 2 XOR gates and 3 NAND to full adder:
implement the logic . XOR gate has mainly 3 implementations Complementary
Pass-transistor Logic XOR (CPL) The main advantage of the
CPL logic family is that it uses few numbers of transistors so
in terms of area it has an edge over other implementations.
Implementation 3 uses 2 XOR, 2 AND and 1 OR to However, CPL has a reduced swing so it cannot be used as the
implement the logic. output of any adder since according to project description;
reduced swing at the output is unacceptable.

Figure 3: XOR CPL implementation
Double Pass-transistor LogicXOR(DPL)
The main advantages of the DPL logic family is that its delay
is low since always 2 transistors are ON in any charging or Figure 7: NANDDPL implementation
discharging input combinations.Also it has an advantage over
the CPL that it has a full swing at the output and uses
reasonable number of gates.
Figure 4: XOR DPL implementation

Figure 8: NANDCMOS implementation
Transmission gate XOR(TG)
Transmission gate is another implementation for the XOR CMOS NAND
function. However, its worst case delay is probably higher that CMOS logic family has an advantage over DPL that it uses less
the DPL since when A is HIGH only 1 transistor is charging number of transistors (no need for inverters), and has an
or discharging the output compared to two in the DPL edge over CPL that its output is full swing.
implementation. So in terms of delay DPL has an edge over
transmission gate. However, it uses less number of transistors SIMULATION:
. Figure 5: XOR Transmission gate implementation

REFERANCE:
I. Zhao, J.: Design of PLC control system for traffic

lights, Mechatronics and Manufacturing
NAND gate has mainly 3 implementations: Technologies (2016)
II. Zhao, J.: Research on the measurement system of
liquid weighing based on PLC. In: International
Conference Energy and Mechanical Engineering
(2015)
III. Zhao, J.: PLC counter applications technique,
Progress in Mechatronics and Information
Technology (2013)
Figure 6: NANDCPL implementation IV. Floyd, T.L.: Digital Fundamentals (2006)

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4-Bit Adder

COURSE TEACHER : NIRJHOR TAHMIDUR ROUF

Faculty © of Engineering, American International University – Bangladesh

Introduction(Heading-1) Figure 2: Gate level implementation 2 of the full adder

Faculty © of Engineering, American International University – Bangladesh

Figure 4: XOR DPL implementation

. Figure 5: XOR Transmission gate implementation

I. Zhao, J.: Design of PLC control system for traffic

Faculty © of Engineering, American International University – Bangladesh

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