ECE: Introduction To Computer Systems Instructor: Maria Striki Spring 2021

Introduction
ECE: Introduction to Computer Systems

Instructor: Maria Striki
Spring 2021
Overview of Presentation 1
What is an Operating System?

Major OS components
Architectural refresher
2
What is an Operating System
3
Operating System Definition
 OS is a resource allocator
 Manages all resources
 Decides between conflicting requests for efficient and fair resource use
 OS is a control program
 Controls execution of programs to prevent errors and improper use of
the computer
Operating System Concepts – 9th Edition 1.4 Silberschatz, Galvin and Gagne ©2013
Quiz Question 1: What Is An Operating System?
What Is An Operating System?

a) collection of programs that manages hardware resources
b) system service provider to the application programs
c) link to interface the hardware and application programs
d) all of the above
Answer:
5
Quiz Question 1

a) collection of programs that manages hardware resources
b) system service provider to the application programs
c) link to interface the hardware and application programs
d) all of the above
Answer: d
6
Quiz Question 2
To access the services of operating system, the

interface is provided by the ___________
a) System calls
b) API
c) Library
d) Assembly instructions
Answer: 7
Quiz Question 2
To access the services of operating system, the

interface is provided by the ___________
a) System calls
b) API
c) Library
d) Assembly instructions
Answer: a 8
Quiz Question 3
Which facility dynamically adds probes to a running

system, both in user processes and in the kernel?
a) DTrace
b) DLocate
c) DMap
d) DAdd
Answer: 9
Quiz Question 3
Which facility dynamically adds probes to a running system, both
in user processes and in the kernel?
a) DTrace
b) DLocate
c) DMap
d) DAdd
Answer: a
DTrace is a comprehensive dynamic tracing framework created by Sun Microsystems for
troubleshooting kernel and application problems on production systems in real time.
Originally developed for Solaris, then ported to several Unix-like systems. DTrace can be
used to get a global overview of a running system, such as: amount of memory, CPU time,
filesystem and network resources used by the active processes, a log of the arguments with
which a specific function is being called, or a10list of the processes accessing a specific file.
application (user)
operating system
hardware
1. A software layer between the hardware and the application programs/users which
provides a virtual machine interface: easy and safe.
2. A resource manager that allows programs/users to share the hardware resources:
fair and efficient. It controls execution of programs to avoid improper use of the
computer
3. A set of utilities to simplify application development and execution
4. A program that acts as an intermediary between a user of a computer and the
computer hardware
11
Operating System Definition (Cont.)
 “The one program running at all times on the computer” is the kernel.
 Everything else is either
 a system program (ships with the operating system) , or
 an application program.
What are the goals of an Operating System?
Operating system goals:

1. Execute user programs and make solving user problems easier
2. Make the computer system convenient to use
3. Use the computer hardware in an efficient manner
13
Computer System Structure
Computer system can be divided into four components:

Hardware – provides basic computing resources
CPU, memory, I/O devices
Operating system
Controls and coordinates use of hardware among various
applications and users
Application programs – define the ways in which the system resources are
used to solve the computing problems of the users
Word processors, compilers, web browsers, database systems,
video games
Users
People, machines, other computers
14
Four Components of a Computer System
15
Why Do We Want An OS?
Benefits for application writers

Easier to write programs
See high level abstractions instead of low-level hardware
details
E.g. files instead of disk blocks
Portability
Benefits for users
Easier to use computers
Can you imagine trying to use a computer without the OS?
Safety
OS protects programs from each other
OS protects users from each other
16
Mechanism And Policy
application (user)
operating system: mechanism + policy
hardware
Mechanisms: data structures and operations that implement an abstraction

(e.g. the buffer cache)
Policies: the procedures that guide the selection of a certain course of action
among alternatives (e.g. the replacement policy for the buffer cache)
Want to separate mechanisms and policies as much as possible
Different policies may be needed for different operating environments
17
Examples of Various Levels of Abstraction
application (user)
operating system: mechanism + policy
hardware
Question 1: How are different programming models actually implemented?

Question 2: How do different programming models are abstracted to the User?
What does the user need to do or need to know about (which levels in the hierarchy
of implementation) to be able to run a program in a given model?
Food for thought: Compare the following two examples of programming models:
1) Posix Pthreads, 2) ISPC
18
System layers: interface, implementation, interface, ...
Parallel Applications
Abstractions for describing Abstractions for “Programming
concurrent, parallel, or describing model”
independent computation communication (way of thinking about
things)
Language or
library
Compiler and/or parallel runtime Primitives
/mechanisms
OS system
call API
Operating system
Hardware
Architecture
Micro-architecture (hardware implementation) (HW/SW boundary)
Blue italic text:

abstraction/concept
Red italic text: system interface
Black text: system implementation 19
Example: expressing parallelism with
pthreads
Abstraction for describing parallel computation: Programming
thread model
pthread_create()
pthread library implementation
System call API

OS support: kernel thread management
x86-64
modern multi-core CPU
Blue italic text:

abstraction/concept
Red italic text: system interface
Black text: system 20
Example: expressing parallelism (ISPC)
Parallel Applications
Abstractions for describing parallel computation:
Programming
1. For specifying simultaneous execution (true parallelism)
model
2. For specifying independent work (potentially parallel)
ISPC language (call ISPC function, foreach construct)
ISPC compiler
System call API

OS support
x86-64 (including AVX vector instructions)

single-core of CPU
Note: This diagram is specific to the ISPC gang abstraction.
21
Basic Computer Structure and Machine
Abstraction of Module Functionalities
to the User
22
Basic computer structure
CPU Memory
memory bus
I/O bus
disk Net interface
23
Computer System Organization
 Computer-system operation
 One or more CPUs, device controllers connect through common
bus providing access to shared memory
 Concurrent execution of CPUs and devices competing for
memory cycles
Virtual Machine Abstractions
Processes: system abstraction – illusion of being the only job

executing in the system (not quite when want to share)
Threads: CPU abstraction – illusion of having a dedicated CPU
Virtual memory: memory abstraction – illusion of having an
unlimited memory
File system: storage abstraction – illusion of structured,
persistent storage system
Messaging: communication abstraction – illusion of reliable,
ordered communication
Character and block devices: I/O abstraction – standardized I/F
for devices
25
Major Issues In OS Design
Programming API: what should the VM look like?

Resource management: how should resources be shared among
multiple users?
Security: how to protect users from each other? How to protect
programs from each other? How to project the OS from
applications and users?
Communication: how can applications exchange information?
Structure: how to organize the OS?
Concurrency: how do we deal with the concurrency inherent in
OS’s?
26
Major Issues In OS Design
Performance: how to make it all run fast?

Reliability: how do we keep the OS from crashing?
Persistence: how can we make data last beyond program
execution?
Accounting: how do we keep track of resource usage?
Distribution: how do we make it easier to use multiple computers
in conjunction?
Scaling: how do we keep the OS efficient and reliable as the
imposed load and so the number of computers grow?
27
Storage Management
28
Storage Structure
Main memory – only large storage media that the CPU can
access directly
Random access
Typically volatile
Secondary storage – extension of main memory that

provides large nonvolatile storage capacity
Hard disks – rigid metal or glass platters covered with
magnetic recording material
Disk surface is logically divided into tracks, which are subdivided into sectors
The disk controller determines the logical interaction between the device and the
computer
Solid-state disks – faster than hard disks, nonvolatile

Various technologies
Becoming more popular
29
Storage Hierarchy
Storage systems organized in hierarchy

Speed
Cost
Volatility
Caching – copying information into faster storage
system; main memory can be viewed as a cache
for secondary storage
Device Driver for each device controller to
manage I/O
Provides uniform interface between controller and kernel
30
Storage-Device Hierarchy
31
Caching
Important principle, performed at many levels in a computer (in

hardware, operating system, software)
Information in use copied from slower to faster storage

temporarily
Faster storage (cache) checked first to determine if information

is there
If it is, information used directly from the cache (fast)
If not, data copied to cache and used there
Cache smaller than storage being cached

Cache management important design problem
Cache size and replacement policy
32
Direct Memory Access Structure
Used for high-speed I/O devices able to transmit information at close

to memory speeds
Device controller transfers blocks of data from buffer storage directly

to main memory without CPU intervention
Only one interrupt is generated per block, rather than the one
interrupt per byte
33
How a Modern Computer Works
A von Neumann architecture
34
Memory Layout for Multiprogrammed System
Architectural Refresher
36
Architectural Refresher
View of a computer from an Operating System’s designer

perspective
Operating system is a layer of software that creates a virtual
machine
OS also manages the resources of this machine but this mostly involves
sharing policies so will be discussed later
These lectures will familiarize you with
The underlying machine
The extra hardware mechanisms needed for virtualization
37
Topics
The von Neumann architecture

CPU + memory
Hardware support for abstracting the basic machine
Modes, Exceptions, Traps and Interrupts
Input and Output
Network, storage and graphics
38
Conceptual Model
Addresses of
memory cells Memory contents
0
CPU
1
+ 2
- 3
4
"big byte array"
* 5
/ 6
7
8
9
39
Operating System Perspective
A computer is a piece of hardware which runs the fetch-decode-

execute loop
Next slides: walk through a very simple computer to illustrate
Machine organization
What are the pieces and how they fit together
The basic fetch-decode-execute loop
How higher-level constructs are translated into machine instructions
At its core, the OS builds what looks like a more complex
machine on top of this basic hardware
40
Fetch-Decode-Execute
Computer as a large, general purpose calculator

want to program it for multiple functions
All von Neumann computers follow the same loop:
Fetch the next instruction from memory
Decode the instruction to figure out what to do
Execute the instruction
Store the result
Instructions are simple. Examples:
Increment the value of a memory cell by 1
Add the contents of memory cells X and Y and store in Z
Multiply contents of memory cells A and B and store in B
41
Instruction Encoding
How to represent instructions as numbers?
8 bits 8 bits 8 bits 8 bits

operators operands destination
+: 1
-: 2
*: 3
/: 4
42
Simple Fictitious Example Encoding
Add cell 28 to cell 63 and place result in cell 100:
8 bits 8 bits 8 bits 8 bits

operator/ source operands destination
instruction Cell 28 Cell 63 Cell 100
+: 1 Instruction as a number in:
-: 2 Decimal: 1:28:63:100
*: 3 Binary: 00000001:00011100:00111111:01100100
Hexadecimal: 01:1C:3F:64
/: 4
How many instructions can this encoding have?

43
Example Encoding (cont)
How many instructions can this encoding have?

8 bits, 2^8 combinations = 256 instructions
How much memory can this example instruction set support?
Assume each memory cell is a byte (8 bits) wide
Assume operands and destination come from the same memory
8 bits per source/dest = 2^8 combinations = 256 bytes
How many bytes did we use per instruction?
4 bytes per instruction
How could we get more memory without changing the encoding?
Why is this simple encoding not realistic?
44
The Program Counter
Q: Where is the “next instruction” held in the machine?
45
The Program Counter
Q: Where is the “next instruction” held in the machine?

Answer:
In a special memory cell in the CPU called the “program
counter" (the PC)
Special purpose memory in the CPU and devices are called registers
Naive fetch cycle: Increment the PC by the instruction length (4)
after each execute
Assumes all instructions are the same length
46
Conceptual Model
Memory
0 operator Instruction 0
CPU
1 operand 1 @ memory
+ 2 operand 2
address 0
Arithmetic - 3
4
destination
Units
* 5
Instruction 1
@ memory
/ 6 address 4
Program 7
4
Counter 8
9
47
Memory Indirection
Q: How do we access array elements efficiently if all we can do

is name a cell?
48
Memory Indirection
Q: How do we access array elements efficiently if all we can do

is name a cell?
Answer:
Modify the operand to allow for fetching an operand "through" a
memory location
E.g.: LOAD [5], 2 means fetch the contents of the cell whose address is
in cell 5 and put it into cell 2
So if cell 5 had the number 100, we would place the contents of cell 100
into cell 2
This is called indirection
Fetch the contents of the cell “pointed to” by the cell in the opcode
Steal an operand bit to signify if an indirection is desired
49
Conditionals and Looping
Instructions that modify the Program Counter

Conditional instructions
If the content of this cell is [positive, not zero, etc.] execute the
instruction or not
Branch Instructions
If the content of this cell is [zero, non zero, etc.], set the PC to this
location
jump is an unconditional branch
50
Example: While Loop
while (counter > 0) { Variables to memory cells:

counter is cell 1
sum = sum + Y[counter];
sum is cell 2
counter–-; index is cell 3
}; Y[0]= cell 4, Y[1]=cell 5…
Memory Assembler Assembler
English
cell address label "mnemonic"
100 LOOP: BNZ 1,END // branch to address of END
// if cell 1 is not 0.
104 ADD 2,[3],2 // Add cell 2 and the value
// of the cell pointed to by
// cell 3 then place the
// result in cell 2
108 DEC 3 // decrement cell 3 by 1
112 DEC 1 // decrement cell 1 by 1
116 JUMP LOOP // start executing from the
// address of LOOP
120 END: <next code block>
51
Registers
Architecture rule: large memories are slow, small ones are fast
But everyone wants more memory!
Solution: Put small amount of memory in the CPU for faster operation
Most programs work on only small chunks of memory in a given time period (locality).
So, if we cache the contents of a small number of memory cells in the CPU memory, we
might be able to execute a number of instructions before having to access memory
Most CPUs have 16-32 “general purpose” registers

Source or destination registers look the “same”: operations are 100-1000 times faster when
operands are in registers compared to when they are in memory.
Operands and destination can be in:
Registers only (Sparc, PowerPC, Mips, RISC-V, Alpha)
Registers & 1 memory operand (x86) OR any combination of registers and memory (Vax)
Only memory operations possible in "register-only" machines are load from and store
to memory. Save instruction space too 52
Register Machine Model
Memory
0
CPU
1
Arithmetic Units +,-,*,/ 2
3
Logic Units <,>,!= 4
Program Counter 8 5
register 0 24 6
7
register 1 100 8
register 2 9
18
53
Typical Instructions
Add the contents of register 2 and register 3 and place result in

register 5
ADD r2,r3,r5
Add 100 to the PC if register 2 is not zero
Relative branch
BNZ r2,100
Load the contents of memory location whose address is in
register 5 into register 6
LDI r5,r6
54
Abstracting the Machine
55
Abstracting the Machine
Bare hardware provides a computation device

How to share this expensive piece of equipment between
multiple users?*
Sign up during certain hours? Give program to an operator?
Use software to give the illusion of having it all to yourself while
actually sharing it with others (time-sharing)!
This software is the Operating System
Need hardware support to “virtualize” machine
56
Virtual Machines vs. Operating Systems
App App App App App App
OS OS OS
VM VM VM … App
OS
Machine
Rutgers University 57
Operating System Structure
Process Management
 A process is a program in execution. It is a unit of work within the system.
Program is a passive entity, process is an active entity.
 Process needs resources to accomplish its task
 CPU, memory, I/O, files, Initialization data
 Process termination requires reclaim of any reusable resources
 Single-threaded process has one program counter specifying location of next

instruction to execute
 Process executes instructions sequentially, one at a time, until completion
 Multi-threaded process has one program counter per thread
 The OS is responsible for the following activities of process management:

 Creating and deleting both user and system processes
 Suspending and resuming processes
 Providing mechanisms for process synchronization
 Providing mechanisms for process communication
 Providing mechanisms for deadlock handling
How the Basic Machine is abstracted in
Software
Architecture Features for the OS
Next we'll look at the mechanisms the hardware designers add to

allow OS designers to abstract the basic machine in software
Processor modes
Exceptions
Traps
Interrupts
These require modifications to the basic fetch-decode-execute
cycle in hardware
Processor Modes
OS code is stored in memory (von Neumann model)

What if a user program modifies OS code or data?
Introduce modes of operation

Instructions can be executed in user mode or system mode
A special register holds which mode the CPU is in
Certain instructions can only be executed when in system mode

Certain memory location can only be written when in system mode
Only OS code is executed in system mode
Only OS can modify its “own” memory
The mode register can only be modified in system mode
Operating-System Operations
 Interrupt driven (hardware and software).
 If there are no processes to execute, no I/O devices to service, no
users to whom to respond, OS will sit quietly waiting for something
to happen.
 Events are almost always signaled by the occurrence of an
interrupt or trap or exception.
 Hardware interrupt by one of the devices (e.g., keyboard)

 Software interrupt (exception or trap):
 Software error (e.g., division by zero, invalid memory access)
(exception)
 Request from a specific program for an OS service (system call)
(trap)
Operating-System Operations (cont.)
 Dual-mode operation allows OS to protect itself and other system
components
 User mode and kernel mode
 Mode bit (kernel: 0 and user:1) provided by hardware
 Provides ability to distinguish when system is running user code or
kernel code
 Some instructions designated as privileged, only executable in
kernel mode
 System call changes mode to kernel, return from call resets it to
user
 At system boot time, hardware starts in kernel mode. OS is loaded and starts
user applications in user mode.
 Whenever a trap or interrupt occurs, the hardware changes the state of the
mode bit from 1 to 0 (from user mode to kernel mode).
 Whenever the OS gains control of the computer, it is in kernel mode.
 System always switches to user mode before passing control to a user
program.
Operating-System Operations (cont.)
 Ensure protection by designating some instructions as privileged.
Privileged instructions can be executed only in kernel mode.
 If attempt to execute privileged instruction in user mode is made, the
hardware does not execute it, but treats it as illegal and traps it to OS.
 Examples of protected instructions: when executing in kernel mode,

I/O control, timer management, interrupt management.
 Initial control resides in the OS, where instructions are executed in kernel
mode.
 When control is given back to a user application, the mode is set to user
mode.
 Eventually, control is switched back to the OS via an interrupt, an

exception, or a trap (system call).
 System calls provide the means for a user program to ask the OS to
perform tasks reserved for the OS on the user program’s behalf. A sys call
takes the form of a trap to a specific location in the interrupt vector.
Transition from User to Kernel Mode
Common Functions of Interrupts
 Interrupt transfers control to the interrupt service routine through the

interrupt vector, which contains the addresses of all the service routines
 Interrupt architecture must save the address of the interrupted instruction
 A trap or exception is a software-generated interrupt caused either by an
error or a user request
 An operating system is interrupt driven
 The operating system preserves the state of the CPU by storing registers and
the program counter (PC).
 Determines which type of interrupt has occurred: separate segments of code
determine what action should be taken for each type of interrupt
I/O Structure
 Version 1: After I/O starts, control returns to user program only upon I/O
completion
 Wait instruction idles the CPU until the next interrupt
 Wait loop (contention for memory access)
 At most one I/O request is outstanding at a time, no simultaneous I/O
processing
 Version 2: After I/O starts, control returns to user program without waiting
for I/O completion
 System call – request to the OS to allow user to wait for I/O completion
 Device-status table contains entry for each I/O device indicating its
type, address, and state
 OS indexes into I/O device table to determine device status and to
modify table entry to include interrupt
Simple Protection Scheme
All addresses < 100 are reserved for operating system use
Mode register provided
zero = CPU is executing the OS (in system mode)
one = CPU is executing in user mode
Hardware does this check:
On every fetch, if mode bit is 1 and address < 100, then do not execute
the instruction
When accessing operands, if mode bit is 1 and operand address < 100,
do not execute the instruction
Mode register can only be set if mode is 0
Simple Protection Model
CPU Memory
Arithmetic Units +,-,*,/ 0
Logic Units <,>,!= OS
99
Program Counter 8 100
User
101
Registers 0-31
102
Mode register 0 103
104
105
106
Fetch-decode-execute Revised
Fetch:
if (( the PC < 100) && ( the mode register == 1)) then
Error! User tried to access the OS
else
fetch the instruction at the PC
Decode:
if (( destination register == mode) && ( the mode register == 1)) then
Error! User tried to set the mode register
< more decoding >
Execute:
if (( an operand < 100) && ( the mode register == 1) then
error! User tried to access the OS
else
execute the instruction
Exceptions
What happens when a user program tries to access memory

holding the operating system code or data?
Answer: exceptions
An exception occurs when the CPU encounters an instruction

which cannot be executed
Modify fetch-decode-execute loop to jump to a known location
in the OS when an exception happens
Different errors jump to different places in the OS
Fetch-decode-execute with Exceptions
Fetch:
if (( the PC < 100) && ( the mode bit == 1)) then
set the PC = 60 60 is the well
set the mode = 0 known entry point
fetch the instruction at the PC for a memory
Decode: violation
set the PC = 64
set the mode = 0 64 is the well
goto fetch known entry point
< more decoding > for a mode
Execute: register violation
< check the operands for a violation>
Note: Execute phase must check both operands and check again when performing an indirect load
Recovering from Exceptions
The OS can figure out what caused the exception from the entry point. But
how can it figure out where in the user program the problem was?
Solution: add another register, the PC’
When an exception occurs, save the current PC to PC’ before loading the PC
with a new value
OS can examine the PC' and perform some recovery action
Stop user program and print an error message: error at address PC'
Run a debugger
Fetch-decode-execute with Exceptions & Recovery
Fetch:
set the PC' = PC
set the PC = 60
set the mode = 0
Decode:
set the PC' = PC
set the PC = 64
set the mode = 0
goto fetch
< more decoding >
Execute:
…
Traps
Now we know what happens when a user program illegally tries to

access OS code or data
How does a user program legitimately access OS services?
Solution: Trap instruction
A trap is a special instruction that forces the PC to a known address
and sets the mode into system mode
Unlike exceptions, traps carry some arguments to the OS
Foundation of the system call
Fetch-decode-execute with traps
Fetch:
< memory exception>
Decode:
if (the instruction is a trap) then
set the PC' = PC
set the PC = 68
set the mode = 0
goto fetch
if (( destination register == mode) && ( the mode bit == 1)) then
< mode exeception >
Execute:
…
Traps
How does the OS know which service the user program wants to invoke on a trap?
User program passes the OS a number that encodes which OS service is desired
Our example machine could include the trap service ID in the opcode itself.
Trap opcode Trap service ID
Most real CPUs have a convention for passing the trap code in a set of registers
E.g. the user program sets register 0 with the trap code, then executes the trap instruction
Question: In our example, we do have a trap command: no 68. What is the

role of number 68? Where does it get stored?
Refresher
(1) CPU has two execution modes. 0 means ________ and 1

means ______________
(2) Exception makes the CPU to transit from _______ mode to
__________ mode. Please give an example of an exception.
Does CPU check for exception in instruction decoding
phase?
(3) What is a trap? Why do programs need to call a trap?
79
Switching from User to Kernel Mode
How to "get back" to user mode and the user's code after a trap?
Set the mode register = 1 then set the PC? What happens then?
A: Exception? Trap? What number of instruction do we jump to?
Set the PC, then set the mode bit? What happens then?
A: Exception? Trap? What number of instruction do we jump to?
Switching from User to Kernel Mode
How to "get back" to user mode and the user's code after a trap?
Option 1: Set the mode register = 1 then set the PC?
But after the mode bit is set to user, exception!
Option 2: Set the PC, then set the mode bit?
Jump to "user-land", still in kernel mode
Most machines have a "return from exception" instruction

A single hardware instruction:
Swaps the PC and the PC'
Sets the mode bit to user mode
Traps and exceptions use the same mechanism (ReTurn from Exception: RTE)
Interrupts
How can we force a the CPU back into system mode if the user
program is off computing something?
Solution: Interrupts
An interrupt is an external event that causes the CPU to jump to a
known address
Example: How to link an interrupt to a periodic clock?

Modify fetch-decode-execute loop to check an external line set
periodically by the clock
Summary 1: Hardware and Software Interrupts
Interrupts are signals sent to the CPU by external devices, normally I/O. They tell the
CPU to stop its current activities and execute the appropriate part of the OS. There
are 3 types of interrupts:
Hardware Interrupts are generated by h/w devices to signal they need attention
from the OS. They may have just received some data (keystrokes on the keyboard or
a piece of data on the Ethernet card); or they just completed a task which the OS
previously requested.
Software Interrupts (traps, exceptions) when they want to request a system call to
be performed by the OS.
 Exceptions are generated by the CPU itself to indicate that some error or condition
occurred for which assistance from the OS is needed.
 Traps are generated by program transferring data between hard drive and memory.
Interrupts give the user better control over the computer. Otherwise, a user may
have to wait for a given application to have a higher priority over the CPU to be ran.
This ensures that the CPU will deal with the process immediately.
Summary 2: Hardware and Software Interrupts
Summary 3: Interrupts
In user mode you cannot just switch to kernel mode. Interaction

between user and kernel is done via system-calls. Each system-call is
providing one defined service. The user sends the service name
(usually a number) and the required parameters.
X86 Assembler example: It moves the system-call name into the EAX
register, the pointer to the parameters into the EBX register of the
CPU and then emits software interrupt no 42. The interrupt
handling will do the switch to kernel mode. The interrupt number is
looked up in the Interrupt Descriptor Table (IDT) and invokes the
function that's registered there, the syscall handler. This handler
executes in kernel mode. On return to the user mode the code will
move the content of EAX into the variable RET….
The Clock
The clock starts counting to 10 milliseconds

The clock sets the interrupt line "high" (e.g. sets it to logic 1,
maybe +5 volts)
When the CPU toggles the reset line, the clock sets the interrupt
line low and starts count to 10 milliseconds again
Simple Interrupt Model
CPU Memory
Arithmetic Units +,-,*,/ OS
User
Logic Units <,>,!=
Program Counter 8
PC' Interrupt line Clock
Registers 0-31
Reset line
Mode register 0
Fetch-decode-execute with Interrupts
Fetch:
if (the clock interrupt line == 1) then
set the PC' = PC
set the PC = 72
set the mode = 0
goto fetch
< memory exception >
fetch next instruction
Decode:
if (the instruction is a trap) then
< trap exception >
if (( destination register == mode) && ( the mode bit == 1)) then
< mode exeception >
<more decoding>
Execute: …
Entry Points
What are the "entry points" for our little example machine?
60: memory access violation
64: mode register violation
68: User-initiated trap
72: Clock interrupt
Each entry point is typically a jump to some code block in the OS
All real OS’es have a set of entry points for exceptions, traps and
interrupts
Sometimes they are combined and software has to figure out what happened.
Saving and Restoring Context
Recall the processor state:

PC, PC', R0-R31, mode register
When an entry to the OS happens, we want to start executing the
correct routine then return to the user program such that it can
continue executing normally
Can't just start using the registers in the OS!
Solution: save/restore the user context
Use the OS memory to save all the CPU state
Before returning to user, reload all the registers and then execute a return
from exception instruction
Questions for class (True-False)
A trap an is a hardware generated interrupt whereas an exception

is a software generated interrupt.
Ans: T/F?
Only a trap with mode bit set to 1 is the way to transition from
user to kernel mode to service a request.
Ans: T/F?
Input and Output
How can humans get at the data?

How to load programs?
What happens if I turn the machine off?
Can I send the data to another machine?
Solution: add devices to perform these tasks:

Keyboards, mice, graphics
Disk drives
Network cards
A Simple I/O device
Network card has 2 registers:

a store into the “transmit” register sends the byte over the wire (to the network
device).
Transmit often is written as TX (E.g. TX register)
a load from the “receive” register reads the last byte which was read from the wire
(from the network device).
Receive is often written as RX
How does the CPU access these registers?

Solution: map them into the memory space
An instruction that access memory cell 98 really accesses the transmit register
instead of memory
An instruction that accesses memory cell 99 really accesses the receive register
These registers are said to be memory-mapped
Basic Network I/O
CPU Memory
0
Arithmetic Units +,-,*,/
Logic Units <,>,!= 98 Transmit Reg.
Program Counter 8 99 Receive Reg.
PC' Network card
Registers 0-31
Clock
Mode register 0 Interrupt line
Reset line
Why Memory-Mapped Registers
"Stealing" memory space for device registers has 2 functions:

Allows protected access --- only the OS can access the
device.
User programs must trap into the OS to access I/O devices
because of the normal protection mechanisms in the processor
Why do we want to prevent direct access to devices by user
programs?
Because: (hint words: prevent, orchestrate, access, …)
OS can control devices and move data to/from devices using

regular load and store instructions
No changes to the instruction set are required
This is called programmed I/O (PIO)
Homework:
When does the processor check whether an interrupt has occurred?
Why do we need to map the registers on Network Interface Cards
(NICs) to the main memory?
96
Status Registers
How does the OS know if a new byte has arrived?

How does the OS know when the last byte has been transmitted? (so
it can send another one)
Solution: Status Registers
A status register holds the state of the last I/O operation. It has size
for at least two bits: bit 0 maps to the TX and bit 1 maps to the RX.
Our network card has 1 status register
To transmit, the OS writes a byte into the TX register and sets bit 0 of the
status register to 1. When the network card has successfully transmitted the
byte, it sets bit 0 of the status register back to 0.
When the network card receives a byte, it puts the byte in the RX register and
sets bit 1 of the status register to 1. After the OS reads this data, it sets bit 1 of
the status register back to 0.
Polled I/O
To Transmit:
While (status register bit 0 == 1); // wait for card to be ready
TX register = data;
Status reg = status reg | 0x1; // tell card to TX (set bit 0 to 1)
Naïve Receive:
While (status register bit 1 != 1); // wait for data to arrive
Data = RX register; // Are we correct? You check…
Status reg = status reg & 0x01; // tell card got data (clear bit 1)
Cant' stall OS waiting to receive!!! ; // Are we correct? You check…
Solution: poll after the clock ticks

If (status register bit 1 == 1)
Data = RX register
Status reg = status reg & 0x01;
IsRutgers
the technique
University
above (polling) synchronous
98
or asynchronous?
Interrupt driven I/O
Polling can waste many CPU cycles

On transmit, CPU slows to the speed of the device.
The CPU polls on the status registers.
Can't block on receive, so tie CPU polling to clock (not OS, so this is not
considered an interrupt), but wasted work if no RX data.
Solution: use interrupts

When network has data to receive, signal an interrupt
When data is done transmitting, signal an interrupt.
Is the technique above (interrupts) synchronous or asynchronous?
Polling vs. Interrupts
Why poll at all?

Interrupts have high overhead:
Stop processor
Figure out what caused interrupt
Save user state
Process request
Key factor is frequency of I/O vs. interrupt overhead

Direct Memory Access (DMA)
Problem with Programmed I/O (or PIO): CPU must load/store

all the data into device registers. The data has to go through CPU
The data is probably in memory anyway!
Solution: more hardware to allow the device to read and write
memory just like the CPU
Base + bound (or base + count registers) in the device
Set base + count register
Set the start transmit register
I/O device reads memory from base
Interrupts when done

PIO vs. DMA
Overhead less for PIO than DMA

PIO is a check against the status register, then send or receive
DMA must set up the base, count, check status, take an interrupt
DMA is more efficient at moving data (in what sense then?)

PIO ties up the CPU for the entire length of the transfer
Size of the transfer becomes the key factor in when to use PIO
vs. DMA

Example of PIO vs. DMA
Given:
A load costs 100 CPU "cycles“ (time units)
A store costs 50 CPU “cycles” (time units).
To process an interrupt costs 2000 instructions, each an average of 2 cycles
To send a packet via PIO costs 1 load + 1 store per byte
To send via DMA costs 4 loads + interrupt
Find the packet size where transmitting via DMA costs less CPU
cycles than PIO

Example PIO vs. DMA
Find the number of bytes were PIO==DMA (cutoff point)

cycles per load: L
cycles per store: S
byte in the packet: C
Express simple equation for CPU cycles in terms of cost per byte:
# of cycles for PIO = (L + S)*B = (100 + 50)*B
# of cycles for DMA = setup + interrupt
# of cycles for DMA = 4L + 2*2000
Set PIO cycles equal to DMA cycles and solve for bytes:
(L+S)*B = 4L+4000
(100+50)*B = 4*100+4000
B >= 29.33 bytes = 30 (cutoff point)
When the packet size is >= 30 bytes, DMA costs less cycles than PIO.

Typical I/O devices
Disk drives:
Present the CPU a linear array of fixed-sized blocks that are persistent
across power cycles
Network cards:
Allow the CPU to send and receive discrete units of data (packets) across
a wire, fiber or radio
Packet sizes 64-8000 bytes are typical
Graphics adapters:
Present the CPU with a memory that is turned into pixels on a screen

Recap: the I/O design space
Polling vs. interrupts

How does the device notify the processor an event happened?
Polling: Device is passive, CPU must read/write a register
Interrupt: device signals CPU via an interrupt
Programmed I/O vs. DMA

How the device sends and receives data
Programmed I/O: CPU must use load/store into the device
DMA: Device reads and writes memory

How to boot?

Practical: How to boot?
How does a machine start running the operating system in the first
place?
The process of starting the OS is called booting
Sequence of hardware + software event form the boot protocol
Boot protocol in modern machines is a 3-stage process

CPU starts executing from a fixed address
Firmware loads the boot loader
Boot loader loads the OS

Boot Protocol
(1) CPU is hard-wired to start executing from a known address

in memory
e.g., on x86 this address is 0xFFFF0 (hexadecimal)
This memory address is typically mapped to read-only memory (ROM)
(2) ROM contains the “boot” code

This kind of read-only software is called firmware
On x86, the starting address corresponds to the BIOS (basic input-
output system) boot entry point
This "firmware" code contains only enough code to read 1 block from
the disk drive. This block is loaded and then executed. This program is
the boot loader.

Boot Protocol (cont)
(3) The boot loader can then load the rest of the operating system
from disk. Note that this point the OS still is not running
The boot loader can know about multiple operating systems
The boot loader can know about multiple versions of the OS

Why Have A Boot Protocol?
Why not just store the OS into ROM?

Separate the OS from the hardware
Multiple OSes or different versions of the OS
Want to boot from different devices
E.g. security via a network boot
OS is pretty big (4-8MB). Rather not have it as firmware

Memory Management
and
Storage Management
at a glance!
112
Memory Management
 To execute a program all (or part) of the instructions must be in

memory
 All (or part) of the data that is needed by the program must be in
memory.
 Memory management determines what is in memory and when
 Optimizing CPU utilization and computer response to users
 Memory management activities

 Keeping track of which parts of memory are currently being
used and by whom
 Deciding which processes (or parts thereof) and data to
move into and out of memory
 Allocating and deallocating memory space as needed
Storage Management
 OS provides uniform, logical view of information storage
 Abstracts physical properties to logical storage unit - file
 Each medium is controlled by device (i.e., disk drive, tape drive)
 Varying properties include access speed, capacity, data-transfer
rate, access method (sequential or random)
 File-System management
 Files usually organized into directories
 Access control on most systems to determine who can access what
 OS activities include
 Creating and deleting files and directories
 Primitives to manipulate files and directories
 Mapping files onto secondary storage
 Backup files onto stable (non-volatile) storage media
Mass-Storage Management
 Usually disks used to store data that does not fit in main memory or data that
must be kept for a “long” period of time
 Proper management is of central importance
 Entire speed of computer operation hinges on disk subsystem and its
algorithms
 OS activities
 Free-space management
 Storage allocation
 Disk scheduling
 Some storage need not be fast

 Tertiary storage includes optical storage, magnetic tape
 Still must be managed – by OS or applications
 Varies between WORM (write-once, read-many-times) and RW (read-write)
Performance of Various Levels of Storage
Movement between levels of storage hierarchy can be explicit or implicit
Computing Environments - Traditional
 Stand-alone general purpose machines

 But blurred as most systems interconnect with others (i.e.,
the Internet)
 Portals provide web access to internal systems
 Network computers (thin clients) are like Web terminals
 Mobile computers interconnect via wireless networks
 Networking becoming ubiquitous – even home systems use
firewalls to protect home computers from Internet attacks
Computing Environments - Mobile
 Handheld smartphones, tablets, etc

 What is the functional difference between them and a
“traditional” laptop?
 Extra feature – more OS features (GPS, gyroscope)
 Allows new types of apps like augmented reality
 Use IEEE 802.11 wireless, or cellular data networks for
connectivity
 Leaders are Apple iOS and Google Android
Computing Environments – Distributed
 Distributed computiing
 Collection of separate, possibly heterogeneous, systems
networked together
 Network is a communications path, TCP/IP most common
– Local Area Network (LAN)
– Wide Area Network (WAN)
– Metropolitan Area Network (MAN)
– Personal Area Network (PAN)
 Network Operating System provides features between
systems across network
 Communication scheme allows systems to exchange
messages
 Illusion of a single system
Computing Environments – Client-Server
 Client-Server Computing
 Dumb terminals supplanted (superseded) by smart PCs
 Many systems now provide servers, responding to requests
generated by clients
 Compute-server system provides an interface to client to
request services (i.e., database)
 File-server system provides interface for clients to store
and retrieve files
Computing Environments - Peer-to-Peer
 Another model of distributed system

 P2P does not distinguish clients and servers
 Instead all nodes are considered peers
 May each act as client, server or both
 Node must join P2P network
 Registers its service with central lookup
service on network, or
 Broadcast request for service and
respond to requests for service via
discovery protocol
 Examples include Napster and Gnutella,
Voice over IP (VoIP) such as Skype
Computing Environments - Virtualization
 Allows operating systems to run applications within other OSes

 Vast and growing industry
 Emulation used when source CPU type different from target type (i.e. PowerPC
to Intel x86)
 Generally slowest method
 Interpretation: When computer language not compiled to native code –
(Computer programs are usually written on high level languages.
... Interpreter translates just one statement of the program at a time into machine
code. Compiler scans the entire program and translates the whole of it into
machine code at once. An interpreter takes much less time to analyze the source
code)
 Virtualization – OS natively compiled for CPU, running guest OSes also natively
compiled
 Consider VMware running WinXP guests, each running applications, all on
native WinXP host OS
 VMM (virtual Machine Manager) provides virtualization services
 Use cases involve laptops and desktops running multiple OSes

for exploration or compatibility
 Apple laptop running Mac OS X host, Windows as a guest
 Developing apps for multiple OSes without having multiple
systems
 QA testing applications without having multiple systems
 Executing and managing compute environments within data
centers
 VMM can run natively, in which case they are also the host
 There is no general purpose host then (VMware ESX and
Citrix XenServer)
Computing Environments – Cloud Computing
 Delivers computing, storage, even apps as a service across a network

 Logical extension of virtualization because it uses virtualization as the base
for its functionality.
 Amazon Elastic Compute Cloud EC2 has thousands of servers, millions
of virtual machines, petabytes of storage available across the Internet,
pay based on usage
 Many types
 Public cloud – available via Internet to anyone willing to pay
 Private cloud – run by a company for the company’s own use
 Hybrid cloud – includes both public and private cloud components
 Software as a Service (SaaS) – one or more applications available via
the Internet (i.e., word processor)
 Platform as a Service (PaaS) – software stack ready for application use
via the Internet (i.e., a database server)
 Infrastructure as a Service (IaaS) – servers or storage available over
Internet (i.e., storage available for backup use)
Computing Environments – Cloud Computing
 Cloud computing environments composed of traditional OSes,

plus VMMs, plus cloud management tools
 Internet connectivity requires security like firewalls
 Load balancers spread traffic across multiple applications
Computing Environments – Real-Time Embedded Systems
 Real-time embedded systems most prevalent form of computers

 Vary considerable, special purpose, limited purpose OS,
real-time OS
 Use expanding
 Many other special computing environments as well
 Some have OSes, some perform tasks without an OS
 Real-time OS has well-defined fixed time constraints
 Processing must be done within constraint
 Correct operation only if constraints met

ECE: Introduction To Computer Systems Instructor: Maria Striki Spring 2021

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Introduction

ECE: Introduction to Computer Systems

What is an Operating System?

What Is An Operating System?

b) system service provider to the application programs

c) link to interface the hardware and application programs

d) all of the above

What Is An Operating System?

b) system service provider to the application programs

c) link to interface the hardware and application programs

d) all of the above

To access the services of operating system, the

To access the services of operating system, the

Which facility dynamically adds probes to a running

Operating system goals:

Computer system can be divided into four components:

Benefits for application writers

operating system: mechanism + policy

Mechanisms: data structures and operations that implement an abstraction

operating system: mechanism + policy

Question 1: How are different programming models actually implemented?

Blue italic text:

pthread library implementation

System call API

Blue italic text:

ISPC language (call ISPC function, foreach construct)

System call API

x86-64 (including AVX vector instructions)

Note: This diagram is specific to the ISPC gang abstraction.

disk Net interface

Processes: system abstraction – illusion of being the only job

Programming API: what should the VM look like?

Performance: how to make it all run fast?

Secondary storage – extension of main memory that

Solid-state disks – faster than hard disks, nonvolatile

Storage systems organized in hierarchy

Important principle, performed at many levels in a computer (in

Information in use copied from slower to faster storage

Faster storage (cache) checked first to determine if information

Cache smaller than storage being cached

Used for high-speed I/O devices able to transmit information at close

Device controller transfers blocks of data from buffer storage directly

A von Neumann architecture

View of a computer from an Operating System’s designer

The von Neumann architecture

A computer is a piece of hardware which runs the fetch-decode-

Computer as a large, general purpose calculator

How to represent instructions as numbers?

8 bits 8 bits 8 bits 8 bits

Add cell 28 to cell 63 and place result in cell 100:

8 bits 8 bits 8 bits 8 bits

How many instructions can this encoding have?

How many instructions can this encoding have?

Q: Where is the “next instruction” held in the machine?

Q: Where is the “next instruction” held in the machine?

Q: How do we access array elements efficiently if all we can do

Q: How do we access array elements efficiently if all we can do

Instructions that modify the Program Counter

while (counter > 0) { Variables to memory cells: