GMW3122 11-2005 Ens

WORDLWIDE General Specification
ENGINEERING GMW3122
Electrical/Electronic
STANDARDS
Dual Wire CAN Physical Layer and Data Link Layer Specification
a. To state a binding requirement on the network

1 Introduction or the nodes which comprise the network,
which is verifiable by external manipulation
1.1 Scope. This document specifies the physical
and/or observation of a node or the network.
layer requirements for a Carrier Sense Multiple
Access/Collision Resolution (CSMA/CR) data link b. To state a binding requirement upon a node’s
which operates on a dual wire medium to requirements document that is verifiable
communicate among Electronic Control Units through a review of the document.
(ECU) on road vehicles at normal transmission The word “Must” shall be used to state a binding
rates of: requirement upon nodes on the network
High Speed Bus 500 kbit/sec components which will have a corresponding ECU
or component requirements document. These
Medium Speed Bus 95.24 and 125 kbit/sec
requirements will be verified as part of the
This document is to be referenced by the particular component verification.
Component Technical Specification (CTS) which
The word “Should” denotes a preference or
describes any given ECU in which the dual wire
desired conformance.
data link controller and physical layer interface is
located. The performance of the data link layer and Note: In the event of a conflict between the text of
physical layer is specified in this document. ECU this specification and the documents cited herein,
environmental and other requirements shall be the text of this specification takes precedence.
provided in the Component Technical Note: Nothing in this specification supersedes
Specification. Functional as well as parameter applicable laws and regulations unless a specific
requirements in this document generally apply over exemption has been obtained.
the applicable operating conditions and aging. This
includes, for example, operating ambient 2 References
temperature, operating supply voltage and age drift
Note: Only the latest approved standards are
over component life time unless otherwise noted.
applicable unless otherwise specified.
The intended audience includes, but is not limited
2.1 External Standards/Specifications.
to, ECU suppliers, component release engineers,
platform system engineers and semiconductor ISO 11898-1 ISO 21848-2
manufacturers of CAN controller and CAN ISO 11898-2 SAE J2284-3
transceiver ICs. ISO 16845 SAE J2284-1
1.2 Mission/Theme. This specification describes 2.2 GM Standards/Specifications.
the physical layer requirements for a dual wire data
link capable of operating with CSMA/CR protocols GME6718 GMW3097
such as CAN version 2.0A (standard frame GME14010 GMW3172
format). All ECUs shall tolerate CAN version 2.0B GMW3001 GMW3173
(29 bit identifier extended frame format) messages, GMW3059 GMW3191
i.e. ECUs may not disturb such messages unless GMW3091 GMW8763
bit errors were detected. This serial data link
network is intended for use in applications where a
high data rate is required. 3 Requirements
1.3 Requirement Wording Conventions. Within 3.1 Physical and Data Link Layer
this document the following conventions are Characteristics.
applied: 3.1.1 Data link layer and two-wire physical layer
The word “Shall” shall be used in the following according to ISO 11898 (high-speed CAN physical
ways: layer).
© Copyright 2005 General Motors Corporation All Rights Reserved
November 2005 Originating Department: North American Engineering Standards Page 1 of 42

GMW3122 GM WORLDWIDE ENGINEERING STANDARDS
3.1.2 Capable of operating with CAN 2.0A protocol Note: Operation at battery voltages of less than
messages and tolerates CAN 2.0B protocol approximately 6.5 V typically implies usage of a
messages. If platform-specific documents or low-dropout voltage regulator.
SSTS/CTS require conformance to CAN 2.0B, then The bus network shall support communication
the applicable interfaces shall be capable to between powered nodes even when only two of
transmit and receive standard as well as extended the nodes on each network are sufficiently
frame format messages at any time during powered and the rest of the nodes are non-
operation, that is support the protocol CAN 2.0B powered or under powered. Under powered is
running in mixed-mode operation. when battery voltage at the ECU power input pins
3.1.3 Supports the enhanced protocol for extended is within the range of 0 V to 6.0 V unless otherwise
clock tolerance specified, see applicable SSTS and/or CTS.
3.1.4 Only performs bit re-synchronization on Nodes that are not able to communicate without
recessive to dominant bus signal edges disturbing the communication between other
3.1.5 Meets GMW3173 GMLAN architecture and nodes, e.g. due to non-powered or under powered
bus wiring requirements conditions, shall not be allowed to communicate.
Nodes shall, under these conditions, close down
3.1.6 Complies to GMW3097GS and
communication circuits in a controlled manner.
GMW3091GS EMC requirements
Nodes that are in sleep condition shall not disturb
3.1.7 Intended to operate at ground offset voltages
communication between other nodes.
of up to 2V temporarily
In addition, ECU’s that transmit and receive
3.2 Bus Operation.
message frames which are required to support
3.2.1 General Requirements on Bus Operation engine start such as immobilizer data or Crank
for 12V-Powered Devices. Per default the bus command shall support communication in the
network when awake shall be fully functional - i.e. range of 16 V to 18 V for 1 hour and 18 V to 26.5 V
nodes shall be able to transmit and receive data - for 1 minute (jump start condition) unless otherwise
when the supply voltage at the ECU power input specified (see, e.g., GMW3172GS).
pins is within a range as specified in GMW3172
3.2.2 General Requirements on Bus Operation
and/or the applicable CTS and/or SSTS document.
for 42V-Powered Devices. If an ECU is supplied
Note: In any case bus communication shall be exclusively by 42V nominal power as main supply,
supported down to (at least) 9.0 V as measured at then it shall comply to the following requirements
the ECU power/ground input pins. on bus operation:
Note: The requirement “shall support 3.2.2.1 The bus network when awake shall be fully
communication” does not imply that valid sensor functional (i.e., device shall be able to transmit and
data or actuator function must be supported at this receive data) when the battery voltage at the ECU
voltage. power input pins is within the range of 21.0 V to
Note: Those devices which are involved in the 50.0 V.
vehicle immobilization function in some fashion 3.2.2.2 Devices that are relevant for vehicle
typically need to support bus communication down functions at crank and/or which are not permitted
to a supply voltage of 6.0 V. to perform a reset or re-initialization during an
If local ECU supply voltage had decreased below engine Start & Stop cycle, shall be fully functional
the specified minimum value, then the ECU shall (i.e., devices shall be able to transmit and receive
resume bus receive and transmit capability within a data) when a supply voltage starting profile
time as specified in the ECU Component Technical according to ISO 21848-2 is applied. The ECU
Specification. The time is measured from the point shall support error-free bus communication during
in time when the voltage increases to a level of and after the complete ISO 21848-2 starting
0.5 V higher than the specified minimum supply profile.
voltage until bus receive and transmit capability is Devices, that are not relevant to vehicle functions
resumed. If no time is specified in the CTS, then during crank and/or that are allowed to perform
the ECU shall resume bus receive and transmit reset or re-initialization during an engine Start &
capability within trsm (See section 3.10). In Stop cycle, shall not cause error conditions to
addition, if local ECU supply voltage decreases occur on the bus, i.e., there shall be no error
below the specified minimum value, then the ECU frames during and after the application of the crank
shall continue to support bus receive and transmit pulse. The device shall resume bus communication
capability for a time of t > 2 ms. within t ≤ trsm after the supply voltage has reached
Page 2 of 42 November 2005

GM WORLDWIDE ENGINEERING STANDARDS GMW3122
a level of 21 V unless otherwise specified in the 3.2.2.5 Nodes that are in sleep condition shall not
applicable SSTS or CTS. disturb communication of other nodes.
3.2.2.3 High Speed Bus networks shall operate if 3.2.2.6 Physical interface drivers which are not
only two of the nodes on each network are powered or under-powered shall not disturb the
sufficiently powered and the rest of the nodes are communication on the network.
not powered or are in a low supply voltage 3.2.3 Bus Operation During Crank. Table 1
condition. Low supply voltage in this context describes the bus network functionality during
means the battery voltage at the ECU power input crank. Please refer to the applicable CTS, SSTS or
pins is less than 21.0 V. platform-specific technical document to determine
3.2.2.4 High Speed Bus Nodes that are not able to which devices are required to support this function
communicate without disturbing the communication during crank.
of other nodes while in low supply voltage Note: Each ECU that is supposed to contribute
condition shall automatically disable data for engine start purposes (e.g., immobilizer
communication under that condition. Such nodes data) needs to support bus transmission function
shall close down their communication function in a during Crank, depending on platform- or vehicle-
controlled manner while in low supply voltage specific requirements.
condition.
Voltage levels and timing of the Crank pulse are
specified in GMW3097GS and GMW8763 (PPEI).
Table 1: ECU Functional Status at Crank
Period Description
Run/Crank Transition The bus network shall be fully functional, nodes shall be able to transmit and receive
data
Crank1 Bus functionality during this period shall be stated in the Component Technical
Specification. Under no circumstances shall any node disturb ongoing bus
communication. Ongoing message transmissions should be concluded normally, e.g.
without causing error conditions on the bus.
Crank2 See Crank1
Crank3 Upon return of power nodes shall resume data receive and transmit function within a
time period being specified in the Component Technical Specification. If such time is
not specified in the CTS and/or SSTS, then the node shall resume receive/transmit
function within t ≤ trsm (See section 3.10). Under no circumstances shall any node
disturb ongoing bus communication, e.g. due to start-up initiation.
Crank/Run Transition The bus network shall be fully functional, nodes shall be able to transmit and receive
data
3.2.3.1 Transferred 42V Crank Pulse To 14V not allowed to perform reset or re-initialization
Side (e.g., via 42V/14V DC/DC converter). All during and after the complete test pulse.
designated ECU’s shall be fully functional (i.e., Note: See the CTS, SSTS and or platform-specific
device shall be able to transmit and receive data technical document to determine which devices
on high-speed CAN) when a test pulse according shall support operation while a transferred crank
to the table below is applied. Designated ECUs pulse is present.
shall support error-free bus communication and are
Nominal Voltage [V] Minimum Pulse Voltage [V] Pulse Duration [Seconds] Rise and Fall Time [ms]
13.8 7 1 5
3.2.4 Tolerance of the CAN Bit Time. Any CAN transmitted by an ECU shall meet this tolerance
interface of an ECU must be compliant to an requirement and each ECU shall be capable to
overall tolerance of the CAN bit time length as receive messages from other ECUs which meet
specified in 4.1 (5.1). That is, CAN bits being this requirement. The tolerance value is applicable
November 2005 Page 3 of 42

over operating conditions and aging, e.g., be necessary in a subnet for an ECU to be present
temperature, supply voltage and age drift over which supports wakeup on bus traffic (technique 2)
specified vehicle temperature including component and in addition to control the discrete wakeup line
life time. This is to ensure proper operation of the (technique 3).
network, e.g., with respect to the CAN bus 3.3.1 ECU Selective Awake Using a Wake Up
resynchronization function. Wire. ECU selective awake is accomplished by a
Careful analysis of the bit time tolerance is dedicated wire, a wake up wire.
recommended when ceramic resonators and/or The wake up wire is a common wire for all ECU’s
PLL clocks are considered. The permitted connected on the same bus. Each ECU needs one
tolerance of the oscillator circuit is reduced when a pin assigned for this function. The below parameter
PLL clock is used for the CAN data link layer specifications of the wake up wire concept support
controller. For example, the suitable oscillator connection of up to 22 ECU’s. The wake up wire
tolerance would be 0.1%, for the case where the signal is an input/output interface, i.e., the ECU
PLL circuit would exhibit an add-on tolerance of can send and receive the wake up signal on the
0.35% (at 125 or 95.2 kbit/s: 0.4%). same wire.
When a ceramic resonator with a maximum 3.3.1.1 Concept Description.
tolerance of 0.3% is used with a PLL, the add-on
3.3.1.1.1 The wake up output requirements are:
clock tolerance of the PLL is limited to 0.15% (at
125 or 95.2 kbit/s: 0.2%) over a single bit time. At 3.3.1.1.1.1 The wake up voltage Vtwu shall be
a bus speed of 500 bit/s, this is equivalent to applied on the wake up wire for a time ttwuo.
0.15% of 2 µs, or 3 ns maximum jitter over 2 µs. At 3.3.1.1.1.2 Wake up is generated as a hardware
a bus speed of 125 kbit/s, this is equivalent to signal on the wake up wire. The ECU generating
0.2% of 8 µs, or 16 ns max jitter over 8 µs. At a this signal shall wake up or notify all ECU’s
bus speed of 95.2 kbit/s, this is equivalent to 0.2% connected on the same bus.
of 10.5 µs, or 21 ns max jitter over 10.5 µs. 3.3.1.1.2 The wake up input requirements are:
3.3 Wake Up Techniques. Dual wire CAN allows 3.3.1.1.2.1 An ECU currently in sleep mode, that
three types of ECU awake/sleep techniques. If a detects a voltage in excess of Vrwu for a time
wakeup technique is used then it must conform to longer than trwui applied on the wake up wire, shall
GMW3097GS EMC requirements. switch to active mode.
a. Selective awake by an awake pulse. When 3.3.1.1.2.2 The wake up pulse shall also affect an
used, it will be possible to communicate on the ECU in active mode, not only an ECU that is in
dual wire CAN network without forcing nodes sleep mode, i.e., an ECU that is in active mode
that are not needed to stay awake. For details shall be able to detect the wake up pulse.
see section 3.3.1 3.3.1.1.2.3 Each ECU shall be able to generate
b. Non-selective wakeup on presence of CAN wake up pulses and detect wake up pulses on the
bus communication. When used, it will force wake up wire.
nodes to stay awake as long as ongoing 3.3.1.2 Wake Up Wire Basic Requirements.
communication occurs. This is the
recommended concept for new designs. For 3.3.1.2.1 An ECU should not change power modes
details see section 3.3.2. when subjected to GMW3097GS EMC conditions.
For example, the ECU shall not take
Attention: this concept requires to employ CAN conducted/coupled immunity test conditions as
transceiver products which support node wakeup valid wake up or go to sleep events.
upon bus traffic, see 3.11.1.2.11.
3.3.1.2.2 Fault tolerant modes:
c. Non-selective awake by a continuous high
level discrete signal, typically called 3.3.1.2.2.1 ECU power loss. An ECU shall not
“Communication Enable”. When used, it will interfere with wake up function among other ECUs
force nodes to stay awake as long as the during a loss of power or low supply voltage
discrete signal is at a high level (example: condition. Upon return of power, normal wake up
Ignition signal). For details see section 3.3.3. operation shall resume without any operator
intervention within a time period being specified by
Usage of awake/sleep techniques are optional. the ECU Component Technical Specification. If a
Whether and how the above approaches shall be time period is not specified in the CTS, then the
used is to be defined in the applicable platform-
ECU shall resume operation within t ≤ trsm. (See
specific data bus implementation document. Note Section 3.10).
more than one of the above concepts can apply to
a particular ECU or network. For example, it may

3.3.1.2.2.2 Wake up wire short to ground. Wake up resume without any operator intervention within a
function may be interrupted but there shall be no time period being specified by the ECU
damage to any ECU when the wake up wire is Component Technical Specification. If a time
shorted to ground or to a negative voltage down to period is not specified in the CTS, then the ECU
Vwu = –5 V. Upon removal of the wiring fault, shall resume normal operation within t ≤ trsm.
normal wake up operation shall resume without 3.3.1.2.3 The ECU´s wake up input/output function
any operator intervention within a time period being shall be fully functional when the ECU is powered
specified by the ECU Component Technical with a supply voltage of Vs = 6.5 V to 16.0 V.
Specification. If a time period is not specified in the When the ECU supply voltage has decreased
CTS, then the ECU shall resume normal operation below Vs = 6.5 V, then the wake up function shall
within t ≤ trsm. resume operation when the supply voltage reaches
3.3.1.2.2.3 Wake up wire shorted to battery a level of Vs = 7 V or higher.
voltage. Wake up function may be interrupted but Note: This operating supply voltage range for the
there shall be no damage to any ECU when the wake up wire function only applies if not otherwise
wake up wire is shorted to a positive battery specified in the applicable SSTS or CTS.
voltage of Vwu = 16 V without time limit, 18 V for
1 h and 26.5 V for 1 minute. Upon removal of the
wiring fault, normal wake up operation shall
ECU1 ECU2
Wake up wire
ECU3 ECUn
n <= 22
Figure 1: Wake Up Wire
3.3.1.3 Wake Up Output Requirements. Note, temperature and component life time unless
parameter specifications apply over operating otherwise noted.
conditions and aging, e.g. temperature, supply
voltage and age drift over specified vehicle

Table 2: Wake Up Wire Output Parameter Specifications

Conditions: 6.0 V ≤ Vs ≤ 18 V, -40oC < Tamb < TambMax unless otherwise noted. TambMax shall be specified in the
CTS.
Parameter Conditions Symbol Min. Nom. Max. Unit
Low Level Output RL > 100 kΩ, Vwuol - 0.3 0 +0.3 V
Voltage
High Level Output RL = 240 Ω Vwuoh Min {9, (Vs Vs Max V
Voltage – 1.7)} {16,(Vs +
0.3)}
Short-circuit output Vwu = 0V Vwuohsc 25 250 mA
current
Transmit Wake up pulse See Verification of twuo 400 500 600 ms
length Wake up pulse,
section 6.2.2.1
Input capacitance CLWU 20 nF
3.3.1.4 Wake Up Input Requirements.
Table 3: Wake-Up Wire Input Parameter Specifications

Conditions: 6.0 V ≤ Vs ≤ 18 V, -40oC < Tamb < TambMax unless otherwise noted. TambMax shall be specified in the
CTS.
Low level wake up input Vwuil -2.0 0 +2.0 V
voltage
High level wake up input Vwuih 4.5 VS 16 V
voltage
Wake up input filter time See Verification, section twui 0.1 2.0 ms
6.2.2.2
Low Level Input Current Vwu = VwuilMax = 2.0 V Iil 0.1 0.24 0.35 mA
High Level Input Current Vwu = VbattNom = 12 V, Note 1 Iih 1.2 1.4 2.0 mA
Input capacitance Ci 0 1 nF
Note 1: This requirement can be implemented, for example, using a pull down resistance to ECU ground potential, see Appendix C.
3.3.2 Wake Up on Bus Activity. Dual wire CAN a. Devices shall not wake up when transient bus
transceivers which support this wake up method dominant conditions occur with a duration of
have to provide a low power standby/power down less or equal to tfwu_min = 0.75 µs. This means
mode. The µC sets the transceiver to standby the device shall continue to meet the quiescent
before it enters standby /power down mode. Wake current limit for sleep mode.
up shall be performed by an ECU upon detection b. Devices shall wakeup if a valid bus traffic
of any activity on the bus. In standby mode the detection condition is present, that is the bus
transceivers of the involved ECU’s detect has been in “dominant” condition for a duration
recessive to dominant transitions and generate a of at least tfwu_max = 5 µs. It is acceptable to
wake up signal to the µC. Note it is necessary to utilize devices that require multiple transitions
apply appropriate bus input signal filtering against from recessive to dominant to recognize a valid
inadvertent wake-up’s. Specifically, devices shall.

wakeup event within a single bus frame; the primary HS-GMLAN interface based on the
however, the device shall not require more voltage level of a dedicated input. There is (at
than two recessive to dominant or dominant to least) one ECU which controls the voltage on this
recessive transitions. dedicated wake up line. Devices which provide
c. When the bus is in dominant state at the point output control capability for the dedicated wakeup
in time when the ECU attempts to enter a low line shall also provide the input function specified
power mode, then the ECU shall enter the low in this section. Note it is possible that only a subset
power mode and shall remain in the low power of ECUs of a subnet is connected to the wake up
mode until there is a valid wakeup condition. In line. The Component Technical Specification
this case a valid wakeup condition requires at specifies whether the ECU shall have a wake up
least one recessive to dominant transition on output function and/or whether it shall have a wake
the bus, unless otherwise explicitly specified up detection input function. For ESD protection
for a particular ECU. requirements refer to GMW3097. Wake up outputs
and inputs shall be proof against short circuits to
3.3.2.1 Requirements On Valid Wakeup Request
any voltage between –3 V and +26.5 V.
Messages. It is important to note a bus frame must
meet certain characteristics in order to enable ECUs which shall be able to request wake up of
reliable wakeup request functionality. The frame the network shall meet the following requirements
that is used for the purpose of bus wakeup request at the particular output:
must contain the pattern as specified below: In principle the wake up wire output shall provide
3.3.2.1.1 The frame must contain at least 2 open collector characteristic. When asserted the
instances consisting of at least 3 consecutive ECU shall typically output battery voltage level.
dominant bits separated by a pattern that includes When not asserted the ECU shall exhibit a weak
at least one phase consisting of at least 3 low state.
consecutive recessive bits. At data rates higher Note: Parameter specifications apply over
than 500 kbit/s the specified phases have to operating conditions and aging, e.g. temperature,
contain more than the above described number of supply voltage and age drift over specified vehicle
consecutive bits. temperature and component life time unless
3.3.2.1.2 The frame must not contain any data otherwise noted.
bytes. Exception: If an ECU-specific frame header ECUs which shall provide wake up input detection
is utilized for the purpose to facilitate bus wakeup capability shall meet the following requirements at
requests, then presence of data bytes is permitted. this particular input:
Note: The above described pattern may be located The ECU shall have a logic input that connects to
anywhere in the transmitted bus frame, e.g., the continuous high level signal. This input shall be
including ID field, DLC, fixed form bits, CRC, SOF used for detecting presence of a wake up request.
and stuff bits. In principle the wake up wire input shall provide
3.3.3 Wake Up on Continuous High Level weak pull down to ground potential characteristic.
Discrete Input. This approach foresees that ECUs
shall enable/disable the communication function of
Table 4: Wake up line output requirements
Active State Output RL = 240 Ω Vwuoh Vs – 1.0 Vs Max {26.5, V
Voltage (Vs + 0.3)}
Active State Output Vs ≥ 9 V IOh 50 200 mA
Current
Active State Short-Circuit Vwu = 0 V and/or Vwuohsc - 250 mA
Output Current Vwu = 26.5 V
Inactive State Output Vwu = +12 V ILEAKmax -10 0 +10 uA
Leakage Current
o
Conditions: 6.0 V ≤ Vs ≤ 26.5 V, -40 C < Tamb < TambMax unless otherwise noted. TambMax shall be specified in the CTS.
Vwu corresponds to the voltage at the Communication Enable I/O pin of the ECU.

Table 5: Wake up line input requirements

High Level Input Current Vwu = VsNom = 12V Iih 1.2 1.4 2.0 mA
Low Level Input Current Vwu = 2.0V Iil 0.1 0.24 0.35 mA
High Level Wake Up Vwuih 4.0 Vs 26.5 V
Input Voltage
Low Level Wake Up Vwuil -2.0 0 2.0 V
Input Voltage
Edge Input Recognition See Verification, twui 1 - 40 ms
Time section 6.2.2.2
o
Conditions: 6.0 V ≤ Vs ≤ 26.5 V, -40 C < Tamb < TambMax unless otherwise noted. TambMax shall be specified in the CTS.
For an example circuit see appendix C. J2284-1 unless otherwise specified in this
3.4 ECU Requirements. ECU requirements for document.
high speed CAN shall be according to SAE J2284- All ECUs shall be proof against the following
3. ECU requirements for medium speed CAN shall conditions being applied to the bus lines, CANH
be according to ISO 11898 (part 1 and part 2, and CANL, unless an explicit exemption was made
High-Speed Medium Access Unit). per applicable subsystem technical specification or
In addition, a medium speed ECU designated for platform-specific technical document.
operation at 125 kbit/s shall comply with SAE
Table 6: ECU Absolute Maximum Ratings Note 1, Note 2
Parameter Symbol Min Max Unit Conditions/Comment
CANH and CANL DC voltage VCAN_DC -5 +18 V No deviations allowed after removal of
condition No time limit, all modes (e.g.,
normal and sleep), recessive and dominant
bus output states Note 3
CANH and CANL voltage for VCAN_1m - +26.5 V No deviations after removal of condition.
1 minute Time limit 1 min., all modes, recessive and
dominant bus output states.
CANH and CANL voltage for VCAN_10ms - +40 V No deviations after removal of condition.
10 milliseconds Time limit 10 ms, all modes, recessive and
Source voltage at coupling of VCAN_trn -150 +100 V 1.No deviations allowed after removal of
conducted transients to condition.
CANH and CANL lines, see 2. No functional deviations allowed during
GMW3097GS, section exposure.
3.2.1.3.3 All operating modes, recessive and
ESD protection for CANH VCAN_ESD -4 +4 kV HBM contact discharge, powered and
and CANL unpowered ; additional requirements may
apply, e.g., per GMW3097GS. Note 4
Note 1: In addition, the device shall survive the interruption of its connection to ground without time limit at battery voltages up to 16V.
Note in that case a (locally) negative voltage is present at the bus pins relative to the locally disconnected ECU ground pin.
Note 2: When the ECU is in low-power mode, the bus outputs CAN_H and CAN_L shall output a voltage of 0V nominal to the bus via an
output resistance as specified in ISO 11898-2 (see parameter internal resistance of CAN_H and CAN_L).
Note 3: If the physical bus interface was subjected to an overtemperature shutdown condition, then it shall resume regular operation within
10 s unless a component-specific exception were made per CTS.
Note 4: For more detailed EMC & ESD requirements and test conditions applicable to the CAN bus interface of an ECU see GMW3097GS
specifications. Note there are requirements on ESD for packaging and handling in section 3.2.1.4.3 and ESD during operation of the
device (power-on mode) in sections 3.2.1.4.1 and 3.2.1.4.2.

3.5 Bus Termination. Each network needs to be Specification (SSTS), CTS or platform-specific
equipped with two bus termination units. For high- technical document.
speed CAN buses crossing the PPEI border per When the ECU is in low power mode, the bus
default one bus termination shall be implemented termination unit shall not drive a certain common
on the platform side and one termination on the mode voltage onto the bus, i.e. the output Vsplit
powertrain side unless otherwise specified. Per shall be in high impedance state with an output
default this circuit shall be implemented in every leakage of less than ± 100 uA for –3V < V_CAN_H/L <
ECM/PCM component unless explicitly otherwise +16V. Note the differential resistance as measured
specified. Bus termination characteristics shall between CANH and CANL shall always be
meet the SAE J2284-3 specification unless present, also in low-power mode.
otherwise specified in this document. All electronic
control units shall package protect for a bus The bus interface and termination circuit shall be
termination circuit on the PCB unless otherwise applied as shown below.
specified per CTS and/or SSTS. Whether the bus Important note: If a bus termination shall be
termination components (R1, R2, C1) are to be placed outside of a control unit (e.g. in the wiring
populated in a certain control unit shall be specified harness), then a different circuit applies, see
in the applicable Sub-System Technical section “Bus Termination in the Wiring Harness”
below.
Bus Termination
Unit CANH
R1 D1
CAN-
L1 ESD prot.
Transceiver
(if needed)
(ISO 11898)
R2
D2
CANL
C1
Common-
mode C2 C3
Choke
Two termination units EMC Caps GND

present in a subnet
Figure 2: CAN Bus Application Circuit

Note: The length of the traces CANH and CANL such mechanization is suggested by the
should be as short as feasible, e.g., l< 10 cm to semiconductor manufacturer for the particular
minimize EMC hazard. transceiver product. Note, this path may need to be
Note: For a device there are 3 bus termination interrupted if the used transceiver product
choices including regular, secondary, and no changes.
termination. Please refer to the applicable platform- Capacitors C2 and C3 shall be chosen as follows:
specific technical document which devices shall 40 pF < Cin_nom < 100 pF, tolerance less or equal to
perform with kind of bus termination function. 10%, working voltage 100 V or higher. The actual
The requirements on the Common Mode Choke L1 capacitance value of both parts shall be close to
are specified in section 3.9.1. The center tap of the each other to optimize EMC behaviors (see
termination unit shall be connected to the Section 4.1). If a special ESD protection circuit is
reference voltage output of the bus transceiver IC if used (see Section 3.7), then C2 and C3 might

have to be chosen with a lower value or be Devices that are not assigned to provide primary
omitted, depending on the capacitance of the bus termination shall implement a secondary bus
protection circuit. Both capacitors shall be placed termination function, if that is called out per SSTS,
close to the bus connector with minimum trace CTS or platform-specific technical document.
length. Secondary bus termination units shall meet the
If ESD protection elements are needed acceptable same requirements as the regular termination,
parts are PESD24VS2UAT or MMBZ27VCLT1 or except that the nominal values of R1 and R2 are
equivalent. The capacitance of the ESD protection different.
elements shall be less than or equal to 50 pF. The nominal resistance of R1 and R2 shall be
3.5.1 Regular Bus Termination. between 619 Ω < Rnom < 620 Ω, 1% 250 mW;
C1 = 100 nF, 50V. The component C1 may be left
3.5.1.1 The value of the resistor configuration R1 +
unpopulated if it is not needed to meet component-
R2 shall be as specified in SAE J2284-3. The
level and/or vehicle-level EMC requirements.
nominal value of R1 and R2 shall be between 60 Ω
and 62 Ω (regular bus termination). Note, this 3.5.3 Central Bus Termination Concept. For
allows the following IEC 60063 1% resistance medium speed bus applications at 95.238 kbit/s,
values: 60.4, 61.9 Ohms. Note each of resistances the bus termination can be located centrally, if
R1 and R2 is equivalent to half of the bus called out per SSTS, CTS or platform-specific
termination resistance RL being specified in SAE technical document. This means only one device in
J2284-3. the network performs bus termination function.
Note using this approach implies the sub network
3.5.1.2 The bus termination resistors R1 and R2 function is down in case one of the bus connector
shall meet an initial tolerance of the resistance pins of the central termination device becomes
value of ± 1%. In addition, the resistance of R1 disconnected from the bus.
shall be equal to the resistance of R2 with a
tolerance of 3% over vehicle lifetime. The power The parameter values for the central termination
dissipation rating of R1 and R2 shall be at least P = unit shall meet the specifications for regular bus
250 mW over the ECU’s operating ambient termination see section 3.5.1. with the following
temperature range. For applications in the exceptions.
passenger compartment this is typically Differential internal resistance:
implemented by using a resistor type with 58 Ohms < RdiffC < 64 Ohms
P = 400 mW nominal rating. At higher ambient Nominal resistance of R1 and R2:
temperatures (e.g., underhood etc.) the nominal
power rating shall be adapted accordingly. The 30 Ohms < R12nomC < 32 Ohms, 1%, 250 mW
electronic components R1, R2 and C1 shall be Note: Since R1 and R2 are supposed to be
suited for high frequency applications. (E.g., type connected in series, the resulting bus termination
MMA 0204 HF (BC Components) or similar parts.) resistance shall be twice the value of R12nomC.
3.5.1.3 The nominal capacitance value for C1 is 3.5.4 No Bus Termination. All devices which are
100 nF with a working voltage of 50 V or higher. not specifically assigned to perform bus
C1 shall be suited for high frequency applications, termination (e.g., regular or secondary) shall not
e.g., type ‘NP0’ or similar. C1 shall be connected to populate R1, R2 and C1.
the GND terminal via a low-inductance trace. This 3.5.5 Bus Termination in the Wiring Harness. If
trace shall not be used for supplying noisy parts a bus termination shall be placed outside of a
such as microcontrollers, PWM mode units and control unit, e.g., in the wiring harness, then the
oscillator circuits. Its length should be less than following specifications apply. The resistors R1 and
3 cm as measured from the device’s GND terminal R2 should be implemented as a single resistor
to the corresponding pins of C1, C2 and C3. part. This single resistor part shall meet the
3.5.2 Secondary Bus Termination. The primary following specifications:
purpose of secondary bus termination is to Nominal resistance = 121 Ohms, 1%
minimize signal reflection effects when devices are The resistor shall support a power dissipation
connected to the bus via a longer stub line. There
rating of 0.5 W at the applicable maximum ambient
may be optionally up to 4 secondary bus temperature.
termination units in a subsystem network.
Note: TambMax depends on the location in the
Note: A secondary termination is only suitable if all
vehicle.
devices comply to the extra bus output drive
capability requirement (e.g., 45 Ohms load), see
section 4.1.

Attention: It is highly recommended to locate this 3.7.1 General Requirements for Every ECU.
termination in a dry environment, e.g., in the Each ECU shall meet the applicable ESD
passenger compartment. requirements at the CAN bus input pins, see
3.6 Bus Wiring Requirements. The bus wiring GMW3097GS. Note this includes ESD during
harness and bus connector implementation shall operation (power-on mode) and ESD protection for
meet GMW3173 requirements. For network packaging & handling. See the GMW3097 sections
topology requirements see sections 4.2 and 5.2 of “Remote Inputs/Outputs” and “Handling of
this document. Devices” for details.
3.6.1 Bus Wiring Configurations. Additional requirements which apply to CAN bus
interfaces which are in scope of this document:
3.6.1.1 Each ECU shall provide two terminals per
bus signal that shall be shorted within the ECU, 3.7.1.1 The ESD transient suppressor technique
see GMW3173. shall be compliant to the common mode bus
voltage range. Therefore the ESD protection circuit
3.6.1.2 The internal connection between, for
shall exhibit a high impedance in this voltage
instance CANH_in and CANH_out, shall be
range, e.g.:
implemented with a trace width that corresponds to
the CAN physical media characteristic impedance. Rin_ESD > 100 kΩ for –2V < VCAN_H/L < +7V
(preferred: –7V < VCAN_H/L < +12V).
3.6.1.3 The internal connection shall be as short as
possible and the loop area of the internal 3.7.1.2 The ESD protection circuit shall not
connection shall be as small as possible. The area degrade the bus input resistance and bus input
between CANH and CANL on the PCB-board shall capacitance matching of the CAN interface.
be kept as small as possible. 3.7.1.3 Possible ESD protection components
3.6.1.4 CANH and CANL shall also be placed as include e.g. back-to-back Zener diodes, MLE, MOV
close as possible in the ECU connector to keep or other suppression parts that do not exceed the
loop area in the vicinity of the connector to a capacitance limits specified in SAE J2284-3.
minimum. 3.7.1.4 The ESD transient suppressor components
3.6.1.5 The overall CANH and CANL wiring/trace should provide a breakdown voltage which is
length inside of an ECU shall be less than 10 cm higher than the maximum battery voltage at jump
each. start condition, e.g., higher than 26.5 V.
3.6.2 Connector Parameters. Connector 3.7.2 Specific Requirements for ECUs with
parameters shall be according to ISO 11898, Central ESD Protection Function. Usage of
GMW3191 and GMW3173. Note bus connectors central ESD protection is not foreseen by this
need to provide uninterrupted contact even at document. Each device shall protect itself against
presence of maximum vibration. There shall be no ESD.
repetitive temporary interruption even for times up 3.8 Radiated Emission and Immunity. ECU’s
to 0.2 times the nominal bit time which equals shall conform to EMC requirements according to
t < 0.4 us for the high-speed CAN bus. Typically, the latest revisions of GMW3097GS and
multiple contact points/fingers are necessary to GMW3091GS when built into a vehicle.
meet this requirement, e.g., 4 or more.
3.7 ESD Protection of CAN Bus Pins.
Table 7: Common Mode Choke Asymmetrical Insertion Loss (Common Mode)
Frequency Min Nom Max Unit Conditions/Comment
150 to 500 kHz 0 dB
500 kHz to 5 MHz 5 dB
5 to 110 MHz 20 dB
110 to 300 MHz 10 dB
300 to 1000 MHz t.b.f. dB

Table 8: Common Mode Choke Asymmetrical Insertion Loss (Differential Mode)

Frequency Min Nom Max Unit Conditions/Comment
150 to 500 kHz 1 dB
500 kHz to 5 MHz 10 dB
30 to 110 MHz 6 dB
3.9 Bus Protection and Transient Suppression. should not degrade the EMC performance of the
The following components shall be accommodated network (e.g., bus signal symmetry). Upon return
in the PCB layout to support an ECU meeting of power, normal operation shall resume without
GMW3097GS EMC/ESD requirements. any operator intervention within a time period being
3.9.1 Line Common Mode Choke. The ECU shall specified by the ECU Component Technical
provide the provision for a common-mode choke Specification. If a time period is not specified in the
for FM- & AM-band. The common mode choke, if SSTS/CTS, then the ECU shall resume bus
used, should provide an insertion loss as specified communication operation within t < trsm. An ECU
in Table 7 and Table 8: Asymmetrical insertion loss shall not disturb ongoing transmissions upon return
of line common-mode choke with both coil of power: generation of dominant bus conditions
branches connected in parallel (common-mode). (disturbance) and/or sending of error frames is not
allowed during ECU supply voltage ramp up and
Each PCB layout shall accommodate footprints for
initialization.
placing a bus EMC inductor. The footprint shall
support at least all the inductor products being 3.10.2 ECU loses ground. ECU shall not interfere
mentioned in this section. The footprint provision is with the communication function among other
also required when all EMC tests have been ECUs during a loss of ground condition. Upon
successfully passed without inductor. If a bus return of ground connection, normal operation shall
inductor were not necessary for a certain resume without any operator intervention within a
component, then the footprints shall be populated time period being specified by the ECU
with zero Ohms resistors. Component Technical Specification. If a time
period is not specified in the CSTS / CTS, then the
The typical inductance of the coil is approximately
ECU shall resume bus communication operation
51 µH. Example implementations include types within t < trsm.
B82793-S0513-N201, ZJYS 81R5-2PL(T)-G,
ACT45B-510-2P and/or equivalent products. The 3.10.3 Any ECU that is attached to the network
potential usage of other parts is to be evaluated by means of a stub connection and does not
upon supplier request. provide bus termination becomes
disconnected from the bus wires. All remaining
3.10 Fault Tolerant Modes. The network shall ECUs continue communication with no degradation
meet requirements on Communication/Survivability of the communication function and/or
Under Fault Conditions according to SAE J2284-3. electromagnetic compatibility. Upon removal of the
Specifically each ECU shall meet the specified wiring fault, normal operation shall resume without
fault case behavior in 3.10.1 through 3.10.9, where any operator intervention within a time period being
the default time for resuming normal bus specified by the ECU Component Technical
communication operation (i.e., capability to receive Specification. If such time period is not specified in
and transmit messages) is trsm ≤ 300 ms unless the SSTS / CTS, then the ECU shall resume
otherwise specified per Subsystem Technical normal bus communication operation within
Specification or Component Technical t < trsm.
Specification.
3.10.4 An ECU that provides bus termination
3.10.1 ECU loses power. ECU shall not interfere becomes disconnected from the bus wires. All
with the communication function among other remaining ECUs should continue communication;
ECUs during a loss of power or low supply voltage however, there may be degradation of e.g. the
condition. Ongoing CAN frame transmissions electromagnetic compatibility. Upon removal of the
should be concluded normally, e.g. without causing wiring fault, normal operation shall resume without
error conditions on the bus. The affected ECU any operator intervention within a time period being

specified by the ECU Component Technical 3.10.8 CANH wire shorted to CANL wire.
Specification. If such time period is not specified in Communication may be interrupted but there shall
the SSTS/CTS, then the ECU shall resume normal be no damage to any ECU. Upon removal of the
bus communication operation within t < trsm. wiring fault, normal operation shall resume without
3.10.5 Interruption of CANH and/or CANL wire any operator intervention within a time period being
at any location. There shall be no damage to any specified by the ECU Component Technical
ECU. Data communication between ECUs on Specification. If such time period is not specified in
opposite sides of the interruption is not required. the SSTS/CTS, then the ECU shall resume normal
Data communication capability between ECUs on bus communication operation within t < trsm.
the same side of an interruption is desired. Upon 3.10.9 Presence of above wiring fault
removal of the wiring fault, normal operation shall conditions should not prevent an ECU from
resume without any operator intervention within a entering low power standby mode. E.g., an
time period being specified by the ECU edge-triggered wakeup function is preferred. Also,
Component Technical Specification. If such time a pending transmission request, where an ECU is
period is not specified in the SCTS/CTC, then the waiting for in-frame acknowledgement from other
ECU shall resume normal bus communication ECUs, should not prevent an ECU from entering
operation within t < trsm. standby mode unless otherwise specified per CTS.
3.10.6 CANH and/or CANL wire shorted to 3.11 Requirements On The CAN Transceiver
ground. Communication may be interrupted but and CAN Protocol Controller. This section
there shall be no damage to any ECU when a bus specifies requirements that apply to dual wire CAN
wire is shorted to ground potential. Upon removal transceivers and CAN protocol controllers (stand-
of the wiring fault, normal operation shall resume alone and/or up-integrated) when used with the
without any operator intervention within a time dual wire CAN interface described in this
period being specified by the ECU Component document. For information about device-specific
Technical Specification. If such time period is not reported problems see Appendix A and Appendix
specified in the SSTC / CTS, then the ECU shall B.
resume normal bus communication operation 3.11.1 CAN Transceiver Requirements. The
within t < trsm. CAN transceiver IC (integrated circuit) is the
3.10.7 CANH and/or CANL wire shorted to interface between the CAN protocol controller and
battery voltage. Communication may be the physical bus line.
interrupted but there shall be no damage to any 3.11.1.1 CAN Transceiver Requirements.
ECU when a bus wire is shorted to positive
3.11.1.1.1 The CAN transceiver shall comply to
voltages of up to 18 V. It is highly desirable that
ISO 11898 part 1 and part 2 (High-Speed Medium
there be no damage to any ECU when a bus wire
Access Unit).
is shorted to a voltage of 26.5 V for 1 minute. Upon
removal of the wiring fault, normal operation shall 3.11.1.1.2 CAN bus pin protection
resume without any operator intervention within a requirements. These requirements apply to all
time period being specified by the ECU modes and conditions unless explicitly otherwise
Component Technical Specification. If such time noted, e.g. including recessive state, dominant
period is not specified in the SSTS / CTS, then the state, sleep mode, low-battery, not powered.
ECU shall resume normal bus communication
operation within t < trsm.

Table 9: Transceiver Absolute Maximum Ratings Requirements

Parameter for CAN bus Conditions Min Max Unit Extra requirement if protection
pins of integrated circuit against 42V supply is required
(e.g., transceiver IC) per CTS or platform-specific
technical document
DC Voltage No time limit -5 +18 V +50 V
Short-Term Voltage t = 1 min - +26.5 V n/a
Sporadic Overshoot t = 0.5 s - +40 V +58 V

Voltage
Transient Voltage t = 100 ns, -150 +100 V n/a

(ISO 7637-1, pulses 3a R = 50 Ohms,
and 3b) C = 1 nF
ESD protection HBM contact -4 +4 kV n/a

in powered and discharge,
unpowered state 10 pulses each
In addition, the transceiver shall survive loss of Specification or per platform-specific technical
ground conditions without time limit at battery document.
voltages of up to 16 V. Note in that case the bus 3.11.1.1.7 The CAN transceiver product shall not
pins assume the lowest voltage and all other be a customer-specific integrated circuit (CSIC).
transceiver pins may be biased to a voltage of up That means the CAN transceiver core shall be
to 16 V higher than the bus pins (in case of a 12V intended and released for general automotive
nominal supply). usage, specifically across vehicle manufacturers. It
3.11.1.1.3 The transceiver shall be self-protected shall be an industry available part.
against bus overload conditions, e.g. through 3.11.1.1.8 When the transmit input (TxD) is not
thermal shutdown function. driven, then the bus pins of the CAN transceiver
3.11.1.1.4 The implementation of the CAN- product shall exhibit high-impedance bus output
transceiver shall support an ECU complying to the behavior during supply voltage ramp-up and ramp-
GMW3097GS EMC requirements and when down. Especially any turning on of bus output
implemented in a vehicle shall support complying driver stages is not permitted when the TxD input
with GMW3091GS. Note the IC shall support is not driven, also during supply voltage on/off
successful data transmission while the bus signal cycling.
line is subjected to coupling of conducted 3.11.1.1.9 In case of the logic transmit control input
transients, see GMW3097GS section 3.2.1.3.3 (e.g., TxD) being erroneously locked in dominant
Note: This test condition is similar to ISO 7637 part state, then the transceiver IC shall automatically
3, pulses 3a and 3b. disable the bus driver, e.g., turn back to
3.11.1.1.5 When not powered, the transceiver shall transmission of a recessive bus condition, after a
not exhibit a bus input resistance less than timeout of 150 µs < tTxD_timeout < 10 ms.
specified in ISO 11898 for the high-speed CAN 3.11.1.1.10 The transceiver device must support
physical layer. transmission of frames with 50% bit duty cycle (at
Additional bus leakage requirement if the device is a frame duty cycle of 100% forever). At supply
not foreseen for permanent battery supply: The voltages greater than 18 V, the device must
bus input leakage current shall be less than transmit forever with a frame duty cycle of 50%.
0.25 mA when a voltage of 5 V is applied at the Note: The bit duty cycle is the percentage of bits
bus input while the transceiver supply voltage is which are dominant in any given message and is
0 V (applies to inputs CAN_H and CAN_L). equivalent to the percentage of time the transmit
3.11.1.1.6 The transceiver shall support a low- data line (see, e.g., figure 3) is dominant during
power standby mode, if such function is required any given message.
for an ECU per the Component Technical 3.11.1.1.11 The transceiver device must support
transmission of frames with 75% bit duty cycle at a

frame duty cycle of 100% forever when the 3.11.1.2.5 In standby mode the transceiver should
operating ambient temperature is less or equal to consume less than 80 µA over the temperature
85°C (Celsius). range that corresponds to the ignition-off state, e.g.
3.11.1.1.12 This requirement applies to -40 to +85°C (preferred: +105°C).
transceivers which remain powered and are placed 3.11.1.2.6 When the transceiver is not powered the
into a standby or sleep mode when the ECU is in leakage current into its logic level inputs (e.g., TxD,
the low power state. This requirement does not RxD) should be less than 50 µA when a voltage of
apply to transceivers which are unpowered when +5 V is applied to any of the logic level inputs.
the ECU is in the low power state. 3.11.1.2.7 The transceiver should support wakeup
When the bus is in a dominant state and the interrupt notification upon detection of bus traffic.
transceiver is requested to change to a low power Attention: This specification item is mandatory, if
mode, the transceiver shall not assert the RxD the applicable SSTS and/or CTS calls out for
output line prior to the bus changing its logic state. wakeup on bus traffic functionality. This is typically
Note: This is necessary so that the device can the case for specific ECUs in an electrical
enter the low power state when the bus is shorted architecture. For a specification of the wakeup filter
to battery. function refer to section 3.3.2.
3.11.1.1.13 The transceiver shall automatically limit 3.11.1.2.8 The transceiver shall not generate a bus
the bus output current to less or equal to 200 mA wakeup notification when noise occurs on the bus
when the CANH or CANL line is shorted to any line or when the bus line is clamped. For details
voltage between –3 V and +26.5 V. refer to section 3.3.2.
3.11.1.2 CAN Transceiver Preferred 3.11.1.2.9 The transceiver should support
Conformance. operation with differential input voltages in the
Note: Preferred conformance items are typically range of –2 V < Vdiff < +7 V, where
candidates for being qualified as requirements in Vdiff = VCANH - VCANL.
one of the following revisions of this document. 3.11.1.2.10 The transceiver should provide a
3.11.1.2.1 Successful reception of data should be notification flag output to indicate whether its
provided within a bus voltage range of operation is degraded or interrupted. This flag shall
-7V < VCAN_H/L < +12V. be set to the representation of the state “out of
3.11.1.2.2 The transceiver should provide a regular operation” for example when the
common mode bus output voltage of transceiver detects a low supply voltage condition
2.25 V < VCM < 2.75 V in the recessive state and (e.g., Vcc < Vcc_min) and/or while it is in self
2.1 V < VCM < 2.9 V in the dominant state over protection mode (e.g., overtemperature shutdown)
and/or while it has disabled transmitting due to a
operating conditions, e.g., Vcc = 5 V ± 5%, where
timeout condition for the TxD input.
VCM = 0.5 * (VCANH + VCANL).
3.11.1.2.11 In low-power mode the transceiver
3.11.1.2.3 The transceiver shall be prepared for
should output a bias voltage of 0 V nominal to the
driving bus cable with a line impedance down to
bus with an internal resistance as specified in ISO
95 Ω see updated ISO 11898-2. Specifically it shall
11898-2 (see “internal resistance of CANH and
be capable of providing a differential bus output
CAN_L”).
voltage level of Vdiff > 1.4V at a load resistance of
RL = 45 Ω if called out per platform-specific 3.11.1.2.12 The transceiver should provide a
technical document. suitable voltage output for attachment to the center
tap of the bus termination resistors. This output
Note: This is to provide proper drive capability for shall assume high-impedance state when the
2 regular and 4 secondary bus termination loads. transceiver is not powered, e.g., Vcc < 1.5 V and/or
The requirement can be established per platform- when the transceiver is in low-power mode. The
specific technical document if longer bus cable bus input leakage current shall be less than
stubs shall be supported in a certain vehicle
± 100 µA for –3V < V_CAN_H/L < +16V.
platform.
3.11.2 CAN Controller Requirements.
3.11.1.2.4 The sum of the bus output delay and
bus input delay of the transceiver should be less 3.11.2.1 The CAN controller shall support the
than 280 ns (250 ns preferred) on the bus signal protocol specification CAN 2.0A (standard format)
rising and falling edge at a bus load condition of and CAN 2.0B passive (29 bit ID extended format)
60 Ω, 50 pF. and shall be fully compatible to ISO 11898-1. For
example, the enhanced protocol for higher clock
tolerance must be supported (e.g., tolerate 2 bit

message intermission) and extended frame 3.11.2.5.1 The controller must sample the bit value
messages shall not be disturbed unless bit errors at the specified time after this signal edge and
are being detected. must disregard any consecutive edges until
Alternatively the CAN controller shall be capable of sampling of the current bit has been concluded
transmitting and receiving messages with both (e.g., hard sync function must be disabled
standard frame format, i.e., 11 bit CAN identifiers, immediately upon detection of the first recessive to
and extended frame format, i.e., 29 bit CAN dominant edge).
identifiers (CAN 2.0B active) if explicitly called out 3.11.2.5.2 If the sampling result is “dominant”, then
per SSTS, CTS or platform-specific bus this event shall be taken as a valid start of frame
implementation specification. bit.
3.11.2.2 Compliance to ISO 11898 shall be verified 3.11.2.5.3 Otherwise if the sampling result is
through CAN conformance testing according to the “recessive”, then the edge shall be considered as a
ISO 16845 test plan. Successful passing of the glitch and shall be disregarded. In particular there
complete conformance test shall be documented must not be any error frame transmission due to a
through provision of a written statement of the glitch while the bus is idle.
semiconductor manufacturer. The test plan 3.11.2.6 It is not recommended to feed CAN
conformance declaration shall indicate which controllers with a PLL-generated clock signal. If a
product version was tested and which version of CAN controller is operated with a PLL clock, then
the CAN conformance test plan was used as careful analysis of the implications of the additional
reference. clock jitter is required. As a preventive measure
3.11.2.3 The controller must support the complete extra accuracy requirements on the oscillator clock
range of resynchronization jump width settings apply in this case, see 3.2.4.
specified in ISO 11898-1. In particular, a bit timing 3.11.2.7 The information processing time of the
parameter setting of SJW = 2 time quanta = protocol controller must be equal to 2 time quanta
PHASE_SEG2 must be supported. Also, the or less.
resynchronization function must be operational
3.11.2.8 The CAN controller may employ a
when a synchronization edge is detected outside
message buffer concept with or without Dual
the range set by the SJW parameter, i.e. when
Ported RAM (DPRAM).
then phase error is greater than the SJW, the CAN
controller shall adjust the timing of the current bit 3.11.2.9 The CAN protocol controller shall provide
by SJW time quanta. at least 2 transmit message buffers and 2 receive
message buffers. The transmit buffers shall be
3.11.2.4 The controller must perform at most one
able to be independently loaded. The CAN
hard- and/or re-synchronization action between
controller shall have the capability of determining
two consecutive bit sampling actions. The earliest
the higher priority message and attempt to transmit
point in time when the next re-synchronization is
this message first. The CAN controller shall
permitted is when the configured number of time
recheck the priority each time a message
quanta per bit time minus the length of TSEG2 has
transmission is attempted. Note: Two (2) transmit
elapsed as counted from the bit start time as
buffers are required to be able to queue a higher
determined by the most recent bit
priority message while a low priority message is
resynchronization action. This means after any bit
waiting for bus access. Two (2) receive buffers are
resynchronization action (hard- and/or re-sync) the
required to be able to receive new data while the
resynchronization function must be disabled until
host is still reading the current content of the
the currently pending bit sampling has been
particular receive buffer.
concluded. This would allow the next
resynchronization (at the earliest) in the TSEG2 3.11.2.10 Any time when more than one transmit
segment of the current bit, in case the bit sample buffer is armed for transmission, then the protocol
result is “recessive”. This case might occur due to controller shall automatically (e.g., without any
a glitch on the bus. Note this requirement applies CPU-support) transmit the message with the
to both the hard-synchronization function at the lowest CAN identifier first.
start of a frame as well as to the re-synchronization 3.11.2.11 When two or more messages with the
function while frame transmission/reception is same CAN identifier are armed for transmission,
ongoing. then the protocol controller shall transmit these
3.11.2.5 When the bus is idle and a recessive to messages in a FIFO fashion, i.e., in the sequence
dominant signal edge has occurred then the how they were armed.
controller shall behave in the following way: 3.11.2.12 The controller product shall support a
low-power sleep mode with wake-up capability via

interrupt signal from the CAN bus line and/or 3.11.2.20.3 Bus error warning notification flag that
application-level interrupt and/or power-on reset. becomes present earliest when the transmit error
Note: The controller product data sheets counter reaches a level of 96 and latest when the
sometimes refer to “stop mode” when specifying CAN bus error passive condition is reached. The
the function called “sleep mode” in this document. error warning notification shall become absent no
later than after the transmit error counter has
3.11.2.13 In sleep mode the power consumption of
decreased below a level of 32.
the controller should be less than approximately
Iq = 50 µA. This is typically implemented by 3.11.2.21 It is preferred the CAN controller
stopping the controller clock or turning it to a lower supporting specific notification of (i.e. differentiation
frequency. between) the following fault cases:
3.11.2.14 The controller product shall provide 3.11.2.21.1 CAN receive input is locked in the
dedicated indication flags for each wakeup event dominant state. Note, the bus shall be considered
source since ECUs need to take specific action as locked dominant when N_lock consecutive
depending on which source triggered the wakeup dominant bits have been detected, where
event, e.g., bus wakeup event vs. local wakeup 32 < N_lock < 256.
event vs. reset event and so on. 3.11.2.21.2 Transmission attempt failed because
3.11.2.15 Deleted. CAN receive input is locked in the recessive state.
3.11.2.16 The controller must properly respond to 3.11.2.21.3 Transmission attempt failed because of
(e.g., latch) any activation conditions at any time, missing in-frame acknowledge response. Note, this
also while a goto sleep command is in progress. denotes the case where the ACK slot was detected
to be recessive rather than dominant.
3.11.2.17 The controller shall not provide any
means to suppress/ignore a pending bus wakeup 3.11.2.21.4 Transmission attempt failed due to
interrupt. Exception: The controller may ignore detection of a dominant bus condition in the
pending wakeup interrupts as long as it is in acknowledge delimiter slot.
regular operation and no goto sleep command is 3.11.2.22 The CAN controller function shall cover
present or pending. the complete range of standard frame format
3.11.2.18 The controller product shall support fast message identifiers from 0 through 2047 dec.
startup following a detection of a wakeup condition. Specifically it shall also be capable to receive and
Startup includes supply voltage ramp up (if transmit messages with CAN identifiers 2032
applicable), oscillator start up, memory test, through 2047 dec ($7F0 through $7FF).
controller initialization and transceiver mode 3.11.2.23 The microcontroller shall support
change. Note, in some applications the startup protection mechanisms against use of corrupted
time for an ECU from detection of a wakeup memory data e.g. checksum and/or CRC. It shall
condition until the controller is ready for support checking (e.g., CRC check or equivalent)
reception/transmission of CAN messages needs to of proper function and correct data content of the
be less than approximately 70 ms. The required complete memory including volatile (e.g. RAM) and
startup time for the ECU can be found in the non-volatile memory (e.g., NV-program and
applicable CTS or SSTS or platform-specific bus -configuration data) within a default time of less or
implementation document. equal to 250 ms unless otherwise specified in the
3.11.2.19 The CAN controller shall support the applicable CTS/SSTS. Note the memory check
implementation of the GMW3097GS EMC could be performed immediately at microcontroller
requirements for an ECU. Therefore, it is startup and/or as a background task during
recommended that the CAN controller be operation. The CTS/SSTS shall state whether
integrated with the corresponding CPU in a single testing prior communication startup is required.
package. 3.11.2.24 The microcontroller product shall support
3.11.2.20 The following control and indication retaining certain RAM memory data while in low
functions shall be supported by the CAN controller, supply voltage condition. RAM memory data shall
e.g. by accessing the appropriate register in the be retained as long as the controller’s supply
CAN controller or by interrupt notification: voltage is greater or equal to 2.5 V unless an
exemption is made per SSTS or CTS. RAM
3.11.2.20.1 Abort transmission function i.e. memory data must be automatically marked as
capability to suspend transmission attempts invalid, when the content must be regarded as
without causing error condition on bus and without unreliable due to presence of a low supply voltage
interrupting bus reception function. condition. This capability is required, for example,
3.11.2.20.2 Bus-off condition notification flag. to retain vehicle configuration data during crank.

Note: The minimum device supply voltage at crank 3.11.3 CAN Controller Set-up. The CAN
can be as low as 4.5 V. controller’s CAN transmit output should be
3.11.2.25 It is preferred that the CAN controller programmed to active low push-pull operation, e.g.
product support logic operation (specifically set the CAN transmit output control register
capability to receive and transmit bus messages) accordingly.
within a supply voltage range of 3 V < VuC_op < See sections 4.1 and 5.1 for bit timing
5.25 V. requirements.
Note: This does not imply support of sensor data
A/D conversion and/or actuator control. 4 High Speed Bus Requirements
3.11.2.26 The CAN controller product shall be An ECU being designated for application in a high-
capable of supporting uninterrupted bus data speed network shall meet the general
reception for a bus utilization of up to 100% on all requirements as specified in the ISO 11898 part 1
CAN interfaces using the applicable nominal data and part 2 (High-Speed Medium Access Unit) and
rate(s) unless an explicit exemption is made for a SAE J2284-3 standards unless otherwise specified
certain device. in this document.
3.11.2.27 The CAN controller product shall not be 4.1 ECU Parameter Specifications. All parameter
a customer-specific integrated circuit (CSIC). That specifications shall be met over the applicable
means the CAN controller core shall be intended ECU operating conditions and life time. This
and released for general automotive usage, includes for example the temperature range,
specifically across vehicle manufacturers. It shall supply voltage, network load conditions and
be an industry available part. lifetime degradation unless otherwise noted. All
3.11.2.28 The CAN controller product and/or the requirements do apply to test tools as well unless
host microcontroller shall be capable of detecting an explicit exemption were made.
the presence of frames on the CAN bus and In particular cases bit timing settings other than the
subsequently initializing the start-up sequence ones specified in Table 10 can be used depending
when in a low power mode. The detection of the on the size of the network and its topology. If this is
presence of frames shall be supported desirable then contact a member of the GMLAN
independent of the current frame acceptance filter Hardware Team for more information.
settings. I.e., the device shall be able to wake-up
on any frame independent of the identifier or the
format of the frame.
Table 10: High-Speed CAN Parameter Specifications
Parameter / Function Symbol Min Nom Max Unit Conditions / Comment
Number of in-vehicle ECUs - - 21 Pay attention to the
relation between node
count, wiring length
and clock tolerance
Number of off-board ECUs 0 - 1 Tester or CAN tool
Bus speed fB 500 kbit/s
Tolerance of bus speed for vehicle ∆fB 0 - ± 0.45 % over operating
ECUs conditions and
component lifetime
Preferred tolerance of bus speed ∆fB_Tool 0 - ± 0.15 % Over operating
for off board tools conditions and tool
lifetime
Bit time tB 1991 2000 2009 ns ± 0.45 % (incl. aging)
Nominal time quantum length, tQ_1 - 125 - ns 16 tQ per bit
option 1
Nominal time quantum length, tQ_2 - 100 - ns 20 tQ per bit
option 2

Parameter / Function Symbol Min Nom Max Unit Conditions / Comment

Resynchronization mode Note 1 RSM - R to D - resync on recessive to
only dominant edges only
Number of samples per bit SM 1 1 1 single sample mode
Note 2
Nominal sample point position SP 0.785 0.8 0.834 tB 78.5% to 83.4% of bit
time
Bit resynchronization jump width tSJW 3 3 3 tQ Typically corresponds
with 16 time quanta per bit to SJW = 10bin
Bit resynchronization jump width tSJW 4 4 4 tQ Typically corresponds
with 20 time quanta per bit to SJW = 11bin
ECU internal delay Note 3 tECU 30 - 350 ns Sum of transmit output
plus receive input delay
Differential voltage bus output rise trdiff 20 - 200 ns Figure 3
time
Differential voltage bus output fall tfdiff 20 - 400 ns Figure 3
time
Differential bus voltage at RL = Vdiff45 1.4 - 3.0 V note this requirement is
45 Ω Note 4 not covered by
ISO 11898 to date
CANH and CANL bus output level V0u 0.81 1.5 Vcsdy V overshoot relative to
when signal value changed and Vcsdy the steady state
t < 1 µs voltage
CANH and CANL bus output level V1u 0.95 1.05 V relative to the steady
when 1 µs has elapsed after a Vcsdy Vcsdy state voltage
signal value change
Common mode voltage when 0.2us Vcm 0.95 1.05 V relative to the average
has elapsed after a signal value Vcmavg Vcmavg common mode voltage
change Note 5
ECU CANH input capacitance to CinCANH 40 - 150 pF ftest = 1 MHz
ground Note 6
ECU CANL input capacitance to CinCANL 40 - 150 pF ftest = 1 MHz
ground
ECU CANH to CANL input Cindiff 0 - 90 pF ftest = 1 MHz
capacitance
Deviation between CANH and ∆ Cin 0 - 20 % ftest = 1 MHz
CANL bus input capacitance
Note 1: The CAN resynchronization mode shall be set to resynchronization on recessive-to-dominant edges only and shall meet the
enhanced protocol for extended clock tolerance.
Note 2: The nominal sample point position shall be located at the specified time after the start of a bit cell. Other settings may be possible
after careful analysis, see Appendix D.
Note 3: The ECU internal delay includes the bus output delay and the bus input delay of the physical medium attachment (e.g. CAN
transceiver IC, common-mode coil) plus the CAN controller delay.
Note 4: This requirement is not covered by ISO 11898 and SAE J2284 to date. See the platform-specific technical document whether it
applies to a certain device. Note secondary bus terminations are recommended if longer bus cable stubs shall be supported.
Note 5: This signal symmetry requirement can be waived for a certain vehicle type, if component-level and vehicle-level radiated emission
tests have been successfully passed.
Note 6: Attention: See chapter 3.5 for more details on which bus input capacitors are permitted.

Transmit data from

CAN-controller
(e.g. TX0)
90%
Vdiff = VCANH - VCANL 0.7V

10%
Differential output
voltage on BUS tfdiff
trdiff
Receive data of
Vih
CAN-controller
(e.g. RX0)
Vil
Transceiver internal delay
Figure 3: AC Parameters of Physical Medium Attachment
4.2 Wiring and Network Topology. The bus cable shall be twisted. Twisting is required
Physical media parameters (e.g., cable and regardless of presence or absence of a cable
connectors) shall meet GMW3173 and GME14010 sheath. Per default the term “twist” refers to a full
requirements unless otherwise specified, e.g., per period turn meaning a turn of 360 degrees.
vehicle platform-specific document. A bus cable without and/or with sheath can be
Note: The overall resistance of a CAN bus wire employed, see the vehicle platform-specific
between any two ECUs must not exceed the value technical document.
of Rwh < 4 Ohms over operating ambient If wiring splices are used, then they should be
temperature and vehicle lifetime. For clarification placed in dry environment, e.g., passenger
this includes the resistance of all connectors and compartment.
conductors between any two ECUs in the network.
Additional hints:
Tester
ECU n < 22
n
ECU ECU ECU
L3
3 4 n-1
DLC
J1962
Bus L1
Bus
termination termination
L2
d
ECU ECU
1 2
L4 L4
Figure 4: AC Parameters of Physical Medium Attachment

Table 11: High-Speed CAN Topology Specifications (Figure 4)

Parameter Symbol Minimum Nominal Maximum Unit Comment
Cumulative In- accumulated total
Vehicle Cable LΣ 0.1 - 25 Note 1
meter cable length including
Length trunk line and stubs
ECU Cable Stub Minimum of 0 allows
length L1 0 - 1 Note 2
meter for daisy chain
configurations.
In-Vehicle DLC Minimum of 0 allows
Cable Stub Length L2 0 - 1 meter for DLC direct
mounting on PCB.
Off-Board DLC
Cable Stub Length L3 0 - 5 meter Tester cable
Ground wire length

for ECUs with L4 0 - 1 meter Length from split bus
regular bus termination to vehicle
termination chassis
Note 1: The maximum overall length per network is 30m. If the architecture of a vehicle foresees the high-speed CAN in-vehicle network is
not directly connected to the DLC (e.g. using a signal converter device), then the length budget for in-vehicle usage is equal to the overall
budget, e.g. 30 m.
Note 2: In general longer stubs are not suitable. Nevertheless a single stub with L >1m might be acceptable under certain conditions after
careful analysis and verification in a particular vehicle type on a case-by-case basis. Secondary bus termination is recommended to be
placed at the end of long stubs.
Additional Requirements:
a. To minimize standing waves ECUs should not 5 Medium Speed Bus Requirements
be placed equally spaced on the network and An ECU being designated for application in a
cable tail lengths should not all be the same medium speed network shall meet the general
length. requirements as specified in the ISO 11898
b. The bus line terminations may be placed within standard part 1 and part 2 (High-Speed Medium
modules. Terminations shall be placed Access Unit) unless otherwise specified in this
adjacent to or within the two On-Board ECUs document. In addition, an ECU designated for
which are typically located at the largest bus operation at 125 kbit/s shall comply with SAE
cable distance from each other. J2284-1 unless otherwise specified in this
document.
c. ECUs that do not provide bus line termination
function can be optional devices. 5.1 ECU Parameter Specifications. All parameter
specifications have to be met over the applicable
For the purpose of mounting of bus connectors the
ECU operating conditions and life time. This
cable may be untwisted for a length of less than
includes for example the temperature range,
50 mm at a connector (less than 25 mm preferred).
supply voltage, network load conditions and
For more information about the relation between
lifetime degradation unless otherwise noted.
maximum cable length, bit timing and number of
ECUs contact a member of the GMLAN Hardware
Team.

Table 12: 125 kbit/s Medium-Speed CAN Parameter Specifications

Parameter/Function Symbol Min Nom Max Unit Conditions/Comment
Number of in-vehicle ECUs - - 31
Bus speed fB 125 kbit/s
Tolerance of bus speed ∆fB 0 - ± 0.5 % over operating
conditions and
component lifetime
Bit time tB 7960 8000 8040 ns ± 0.5% incl. aging
Nominal time quantum length tQ 380.95 - 666.67 ns 12 to 21 tQ per bit
Resynchonization mode Note 1 RSM - R to D - resync on recessive to
Nominal resynchronization jump width tSJW 0.15 - 0.25 tB 15% to 25% of bit time
Number of samples per bit SM 1 1 1 single sample mode
Note 2
Nominal sample point position SP 0.75 0.775 0.85 tB 75% to 85% of bit time
ECU internal delay Note 3 tECU 30 - 1000 ns
time
time
ECU CANH input capacitance to CinCANH 40 - 140 pF f = 10 MHz
ground
ECU CANL input capacitance to CinCANL 40 - 140 pF f = 10 MHz
ground
ECU CANH to CANL input Cindiff 0 - 50 pF f = 10 MHz
capacitance
Note1: The CAN resynchronization mode shall be set to resynchronization on recessive-to-dominant edges only and shall meet the
Note 2: The nominal sample point position shall be located at the specified time after the start of a bit cell.
Note 3: The ECU internal delay includes bus output delay and bus input delay of the physical medium attachment (e.g., CAN transceiver
IC, common-mode coil) plus the CAN controller delay.

Table 13: 95.238 kbit/s Medium-Speed CAN Parameter Specifications

Parameter/Function Symbol Min Nom Max Unit Conditions/Comment
Number of in-vehicle ECUs - - 15
Bus speed fB 95.238 kbit/s
Tolerance of bus speed ∆fB 0 - ± 0.5 % over operating
conditions and
component lifetime
Bit time tB 10447.5 10500 10552.5 ns ± 0.5% incl. aging
Nominal time quantum length tQ 500 - 750 ns 14 to 21 tQ per bit
Resynchonization mode Note 1 RSM - R to D - resync on recessive to
Nominal resynchronization jump width tSJW 0.157 - 0.22 tB 15.7% to 22% of bit
time
Number of samples per bit SM 1 1 3 single sample mode or
triple sample mode
Nominal sample point position Note 2 SP 0.75 0.775 0.80 tB 75% to 80% of bit time
ECU internal delay Note 3 tECU 30 - 1000 ns
time
time
ECU CANH input capacitance to CinCANH 40 - 500 pF f = 10 MHz
ground
ECU CANL input capacitance to CinCANL 40 - 500 pF f = 10 MHz
ground
ECU CANH to CANL input Cindiff 0 - 300 pF f = 10 MHz
capacitance
Note1: The CAN resynchronization mode shall be set to resynchronization on recessive-to-dominant edges only and shall meet the
Note 2: The nominal sample point position shall be located at the specified time after the start of a bit cell. In case of triple sample mode
the sample point position denotes the location of the last sample being taken.
Note 3: The ECU internal delay includes bus output delay and bus input delay of the physical medium attachment (e.g., CAN transceiver
IC, common-mode coil) plus the CAN controller delay.
5.2 Wiring and Network Topology. Physical in dry environment, e.g. passenger compartment.
media parameters (wiring) shall meet GME14010 The overall resistance of a CAN bus wire between
requirements unless otherwise specified. The bus any two ECUs must not exceed the value of Rwh <
cable shall be twisted. Twisting is required 4 Ohms over operating ambient temperature and
regardless of presence or absence of a cable vehicle lifetime. For clarification this includes the
sheath. Per default the term “twist” refers to a full resistance of all connectors and conductors
period turn meaning a turn of 360 degrees. The between any two ECUs in the network.
bus cable typically shall come without sheath The topology requirements for a network
unless otherwise called out per applicable containing more than one ECU on-board the
platform-specific technical document. Attention if vehicle and a single off-board tool are specified
wiring splices are used, then they should be placed below:

Table 14: 125 kbit/s Medium-Speed CAN Topology Specifications (See Figure 4)
Cumulative in- Accumulated total cable

vehicle cable LΣ 0.1 50 meter length when 2 regular
length terminations are
present.
ECU Cable Minimum of 0 allows for

Stub length L1 0 1 meter daisy chain
configurations.
In-Vehicle Minimum of 0 allows for

DLC Cable L2 0 1 meter DLC direct mounting on
Stub Length PCB.
Off-Board DLC
Cable Stub L3 0 5 meter Tester cable
Length
Table 15: 95.238 kbit/s Medium-Speed CAN Topology Specifications (See Figure 4)
Cumulative in- Accumulated total cable

vehicle cable LΣ 0.1 35 meter length when 2 regular
length terminations are
(20) present.
In parenthesis: When
central termination
approach employed
ECU Cable Minimum of 0 allows for

Stub length L1 0 6 meter daisy chain
configurations.
In-Vehicle Minimum of 0 allows for

DLC Cable L2 0 3 meter DLC direct mounting on
Stub Length PCB.
Off-Board DLC
Cable Stub L3 0 5 meter Tester cable
Length
6.1 Production Testing at Supplier’s End of

6 Verification Line. Suppliers shall take appropriate measures to
All parameter specifications have to be met over ensure that each delivered device meets the
the applicable ECU operating conditions and life specified properties. Specifically suppliers shall
time. This includes for example the temperature verify each individual dual wire CAN interface by
range, supply voltage, network load conditions and applying (at least) the following tests at the end of
lifetime degradation unless otherwise noted. production line prior to delivery to the automaker:
Please refer to the latest revision of the GME6718 Functional communication test with tool (Functional
GMLAN Device Test Specification or follower as well as diagnostic messages shall be covered
document for applicable test procedures. using an appropriate tool e.g., CANoe or similar.)

• CANH recessive state output level when with automatic test equipment unless an explicit
device is powered (see GME6718) exception were made.
• CANL recessive state output level when device 6.2 Development Testing.
is powered (see GME6718) 6.2.1 CAN Bus In-/Outputs. For specifications
• CANH output current at VCANH = -7 V when how to test the CAN bus in-/outputs refer to the
device is powered (see GME6718) latest version of the document GME6718.
• CANL output current at VCANL = +16 V when 6.2.2 Wake Up Pulse. The tests in this section are
device is powered (see GME6718) only applicable in case the device supports a
dedicated wakeup input terminal.
Each test value shall meet the specified min/max
parameter limits. These tests shall be performed 6.2.2.1 Transmit Wake Up Pulse.
ECU
Vbatt
Wake up wire
V U
RLOAD
Vtwu Us
Test Cases:
Parameter Min Nom Max Conditions
Vtwuoh 6.5 V - 16 V Vs = 9 V and 16V, RLOAD = 240 Ω,
Wake up wire active
Vtwuoh_lo batt 4.8 V - 16 V Vs = 6.5 V, RLOAD = 240 Ω,
Wake up wire active
Vtwuol -0.3 V - +0.3 V Vs = 6.5V and 16 V, RLOAD > 100 kΩ,
Wake up wire inactive
ttwuo 400 ms 500 ms 600 ms Vs = 8 V, RLOAD = 240 Ω,
Wake up wire active
The wake up voltage Vtwu and wake up time ttwu shall be measured with an oscilloscope.
Figure 5: Test Setup for Wake up Wire Output Function

6.2.2.2 Receive Wake Up Pulse.
ECU
Vbatt
Wake up wire
V U
Pulse Generator Vrwu Us
Figure 6: Test Setup Wake Up Input Function

The wake up receive threshold shall be determined The wake up pulse sensitivity shall be determined
by varying the amplitude of a test wake up pulse by applying a test pulse with duration of the
applied by the pulse generator. The test pulse maximum and the minimum trwu length.
duration shall be 2 ms.
Test Cases:
Parameter Min Nom Max Conditions
Vrwu input 2.0 V 4.5 V 6.5 V ≤ Vs ≤ 16 V
threshold
ECU wake up Successful 6.5 V ≤ Vs ≤ 16 V
detection wake up apply single pulse of Vrwu = 4.5 V for
function detection trwu = 2 ms
ECU wake up No wake up 6.5 V ≤ Vs ≤ 16 V
filter function detection trwu = 100 µs ; apply square wave
permitted signal of 1 kHz, 10% duty cycle,
0 V/8 V levels
Iih 1.2 mA 1.4 mA 2.0 mA Vrwu = 12 V
Vs ≤ 16 V
6.2.3 Communication Enable I/Os. For test secondary termination, etc.) shall be documented
specifications see GME6718. though a change of appropriate device
identification codes of the affected device, e.g.
7 Change Management change of the hardware number/suffix. The device
identification code that indicates the type of bus
Suppliers shall report any pending significant
termination used shall be readable by test
change of the hardware and/or software to the
equipment via standardized diagnostic request
vehicle manufacturer prior to execution of the
services (see GMW3110).
change. A significant change includes but is not
limited to a change of the CAN transceiver and/or Further requirements may apply per applicable
CAN data link controller core and/or microcontroller automaker- or vehicle-line-specific change
product. management document.
Any modification of a device’s bus termination
behavior (e.g., removal or inclusion of regular bus 8 Notes
termination in a device, change from regular to 8.1 Glossary. Not applicable.

8.2 Acronyms, Abbreviations, and Symbols. tQ: Time quantum (Note a bit time
ECU Electronic Control Unit consists of an integer number of time
quanta)
Node A device that is connected to a
network and is capable of operating n/a not applicable
according to the relevant protocol trsm: time it takes for an ECU to resume bus
specifications communications after an interruption of
CAN Controller Area Network power or after wiring fault is removed
CTS Component Technical Specification
9 Additional Paragraphs
SSTS Sub-System Technical Specification
9.1 All materials supplied to this specification must
EMC Electromagnetic Compatibility
comply with the requirements of GMW3001, Rules
ESD Electrostatic Discharge and Regulations for Materials Specifications.
IC Integrated circuit 9.2 All materials supplied to this specification must
µC Microcontroller comply with the requirements of GMW3059,
VbattNom: Nominal vehicle system battery Restricted and Reportable Substances for
voltage Parts.
Vs: Voltage between the ECU´s battery
supply and ground inputs 10 Coding System
tB: CAN bit time length This specification shall be referenced in other
documents, drawings, VTS, CTS, etc. as follows:
GMW3122

11 Release and Revisions

11.1 Release. This general specification originated in June 1998. It was first published in January 1999.
11.2 Revisions.
Rev Approval Description (Organization)
Date
C FEB 2005 Maximum number of HS-CAN nodes changed to 22 (including off-board tool).
All section numbers have changed as follows (previous Î current)
§1 Î §11.2; §2 Î §1; §2.1 Î§1.1; §2.2 Î §1.2; §2.3 Î §1.3; §3 Î §2; §3.1 Î §2; §3.2 Î §2.2:
References introduced: GME6718, GME14010. References eliminated: GMW3094, GMW3100,
GMW3098, GMW3104, GMW3128; §3.3 Î §2.1; §3.4 Î §8.1; §4 Î §3; §4.1 Î §3.1; §4.2 Î §3.2;
§4.2.1 Î §3.2.1: Specifications for minimum operating voltage modified. Specification for resuming
operation after power dropout changed; §4.2.2 Î §3.2.2; §4.2.3 Î §3.2.3; §4.2.4 Î §3.2.4:
Considerations for using PLL changed; §4.3 Î §3.3: Some introductory statements modified. “t” and
“r” in symbol subscripts eliminated; §4.3.1 Î §3.3.1; §4.3.2 Î §3.3.2: Specifications modified.
Clause 2 modified to limit the number of transitions required for a wake-up. Clause 3 introduced;
§4.3.3 Î §3.3.3: Electrical specifications for Communication Enable I/Os introduced; §4.4 Î §3.4;
§4.5 Î §3.5: Reference to ECM/PCM appended. Figure 2 modified. Maximum resistance changed
to 32 Ohms with central termination concept. Package protect on the PCB made dependent on
CTS/SSTS. New section §4.5.4 introduced dealing with termination in the harness; §4.5.1 Î §3.5.1;
§4.5.2 Î §3.5.2; §4.5.3 Î §3.5.3; §4.5.4 Î §3.5.4; §4.6 Î §3.6; §4.6.1 Î §3.6.1: Clause 5
introduced; §4.6.2 Î §3.6.2; §4.7 Î §3.7; §4.7.1 Î §3.7.1: Clause 4 introduced. Reference to
sections “Remote Inputs/ Outputs” and “Handling of Devices” introduced; §4.7.2 Î §3.7.2:
requirement eliminated.; §4.8 Î §3.8; §4.9 Î §3.9; §4.9.1 Î §3.9.1: Wording corrected, population
of coil when necessary; §4.10 Î §3.10; §4.11 Î §3.11: Reference to appendices A and B
introduced; §4.11.1 Î §3.11.1: Added specification of transmit duty cycles. Requirement “industry
available part” introduced in clause 7; §4.11.2 Î §3.11.2: New requirement on not asserting RxD
when locked dominant. New requirement on bus output short circuit current. Clause 9 changed to
define behavior of transmit buffers. Clause 15 for controller devices eliminated. Clause 16 dealing
with wakeup on bus traffic changed. Changed wording of clause 23, microcontroller support for
detection of corrupted memory. Requirement “industry available part” introduced in clause 27.
Clause 28 added.
§3.11.3: New section specifying set up of the CAN Controller TxD line; §5 Î §4; §5.1 Î §4.1: Bit
time tolerance changed to 0.45%. Tolerance at component delivery eliminated. Tolerance statement
for GM tools introduced. All bit timing options except of 16 and/or 20 time quanta per bit eliminated;
§5.2 Î §4.2 and §5.2: Reference to GME14010 introduced. References to SAE and ISO eliminated.
Upper limit for resistance of the wiring harness introduced. Twist rate and specific line delay specs
eliminated. Clarification to the term twist introduced. Note on splices introduced; §6 Î §5; §6.1 Î
§5.1; §6.2 Î §5.2; §7 Î §6: CAN I/O test specifications replaced by a reference to GME6718; §7.1
Î §6.1; §7.2 Î §6.2; §7.2.1 Î §6.2.1; §7.2.2 Î §6.2.2; §7.2.3 Î §6.2.3; §8 Î §7; §9 New
Section; §10 New Section; §11 New Section; Appendix A, Appendix B: List of known device-specific
issues replaced by a reference to the GMLAN web page; Appendix C: Reference circuit for
Communication Enable I/Os introduced.
D NOV 2005 §1.1, §2.1, §3.2.4, §5, §5.1, §5.2 Æ Added requirements for a 125 kbit/s mid-speed bus.
§3.5.3 Æ Information on Central Bus Termination moved here from section 5.1.
§3.11.1.1.12 Æ Clarified when this requirement applies.
§3.2.3 Æ Changed PPEI reference from GMW3119 to GMW8763.
§3.3.3 Æ Modified Input thresholds and output voltages for Wake Up Line.
§3.5.3 Æ Modified wake up line requirements to be compatible with micro I/O pin.
Note: At the time of publication, GME6718 was in the process of being made inactive, replaced by
GMW14241.

Appendix A
Reported Transceiver Component Problems .
Note: CAN transceiver requirements have been
relocated to section 3.11.1.
Please refer to the GMLAN website for the latest
list of known CAN transceiver issues and
precautions.
The GMLAN website is:
http://ived.gm.com/electrical/warren/ssltexpt/gmlan/
index.html

Appendix B
Reported CAN Controller Component Problems
Note: CAN controller requirements have been
relocated to section 3.11.2.
Please refer to the GMLAN website for the latest
list of known CAN controller issues, resolutions
and precautions.
The GMLAN website is:
http://ived.gm.com/electrical/warren/ssltexpt/gmlan/
index.html

Appendix C
Implementation Guidelines WAKE UP WIRE
Example Mechanization for Wakeup Technique 3

Vcc
Vbatt
Voltage
Inhibit Regulator
Comm Enable Detecting
Line Input
Circuits
(all ECUs)
Signal Hold
Comm condition-
Enable ing
Line Pin Vbatt
IRQ
Generating
Comm Enable Circuits
Control Output
(typically only present on
one ECU in the subnet)
uC
CAN- CAN-
Transceiver Controller
Figure C1: Implementation Guideline Wake Up Wire
Note that applicable sleep/standby mode power It is recommended the wake up input filter function
consumption ratings are to be specified in the be implemented using passive filter components.
component technical specification. If an ECU has several interrupt sources (wake up
The wakeup input circuit provides a resistive pull- wire, door open) it is recommended these interrupt
down behavior to ECU ground. This can be sources be polled on an I/O-port in order to quickly
implemented for example with a resistance of R = identify the signal source that initiated the wake up
8.2 kΩ nominal, ± 10% tolerance, P = 50 mW no event.
time limit and P =100 mW for 1 minute over the
ECU operating ambient temperature range.

Appendix D
Propagation Delay (tPROP)
Because CAN is a protocol employing bit by bit arbitration, the network propagation delay is equal to the
complete round trip signal delay time for one CAN controller to another one and back. This translates to the
following equation:
tPROP = 2(tTX + tRX + tLOGIC + tCHK + tBUS)
or
tPROP = 2(tECU + tBUS)
with Test tool:
tPROP = tECU + tTtool + 2*tBUS

Bit Timing Requirements
The following table specifies the CAN bit timing requirements. Coordinated bit timing settings are required to
maintain synchronization between modules during both normal and error conditions.
Parameter Min (ns) Nominal (ns) Max (ns)

tBIT * 1991 2000 2009
tBUS** 0 ----- 165
tECU 30 ----- 350
tTtool ----- ----- 390
tQNom - 125 or 100 -
tSEG1 *** *** ***
* The nominal bit time typically is a programmable, integer multiple of the controller IC´s oscillator clock periods.
** tBUS considers one trip through 30 meters using a bus cable with a specific line delay of less than 5.5 ns/m
(5 ns/m nominal).
*** tSEG1 = tBIT - tSEG2 - tQ
The following table specifies all acceptable bit timing settings.

tQ/tB tQNom (ns) tB tolerance (%) tTSEG2 tSJW BTR0 BTR1
(number of time (hex) Note 1 (hex)
quanta per bit)
16 125 0.5 3 tQ 3 tQ $80 $2B
20 100 0.5 4 tQ 4 tQ $C0 $3E
Note 1: BTR0 and BTR1 values apply to the SJA1000 controller when clocked with 16 MHz. Refer to data sheet and/or contact the
semiconductor manufacturer for other controller products or clock speeds.
The above bit timing register settings BTR0 and BTR1 are typical values. Please refer to the particular product
data sheet for exact information.
Bit settings for above time quanta has been calculated from the following equations:

Note: tBIT is always set to 2000 ns. If the ECU is unable to be programmed such as to allow tBIT nominal to be
equal to 2000 ns, then the offset shall be taken into account in the ∆f term and not in the tBIT term .
20tBIT∆f ∆f(20tBIT - tQ) + tQ - tPROP min

tSJW ≥ maximum of 1 - ∆f or 1 + ∆f
tSEG2min ≥ maximum of tSJW or 2 tQ
or ∆f(24tBIT - tQ) + tQ - tPROP min

1 + ∆f
tBIT(1 - 25∆f) - tPROP max tBIT - tPROP max - tQ - ∆f(25tBIT - tQ) + tPROPmin / 2
tSEG2max < minimum of 1 - ∆f or 1 - ∆f
Definition: ∆f equals the maximum deviation (either maximum or minimum) from the specified nominal bit rate
divided by the specified nominal bit rate for specified values.
Implementation Example
Note: This example applies to the 82527. Other controller products may employ different clock division
mechanisms and need different bus timing register settings relative to this example. See the applicable data
sheets and application info of the semiconductor manufacturer.
Implementation example for CAN bit timing parameters on a High Speed Bus.
Reference circuit used in the example: Intel 527 with an oscillator frequency of 16 MHz.
The system clock (SCLK) is set to: 0.5 * 16 MHz = 8 MHz ± 0.45% (DSC = 1)
Prescaler value (BRP) is set to: 0
Nominal time quantum length tQ = tSCLK * (BRP + 1) = 2 * (BRP + 1) / fXTAL = 125 ns
If the number of time quanta per bit is set to 16. That gives:
Nominal bit time: tBIT = 2000 ns
Nominal baudrate: f = 500 kbit/s
tBIT = tSYNC_SEG + tSEG1 + tSEG2

tSYNC_SEG = 1 tQ
With tSEG1 and tSEG2 set to: tSEG1 = (TSEG1 + 1) * tQ = 12 tQ

tSEG2 = (TSEG2 + 1) * tQ = 3 tQ
That gives:
Nominal sample point position: (tSEG1 + tSYNC_SEG) / tBIT = (12 tQ + 1 tQ) / 16 tQ = 0.8125 equals 81.25 %

Resynchronization Jump Width is set to: tSJW = (SJW + 1) * tQ = 3 tQ

That gives:
SJW: tSJW /tBIT = 3 tQ / 16 tQ = 0.1875 equals 18.75 %
Several suitable clock frequency examples with their associated calculated CAN bit settings are shown in the
table below: (Note: The values TSEG1, TSEG2, DSC, BRP, BTR0 and BTR1 apply to the 82527 controller.
Refer to data sheets and application info for other controller products or clock frequencies.
fxtal TSEG1 TSEG2 SJW DSC BRP BTR0 BTR1 CANbus tQ (ns) SJW Sample
(MHz) speed (%) point
(kb/s) (%)
16 11 2 2 1 0 $80 $2B 500 125 18.75 81.25
20 14 3 3 1 0 $C0 $3E 500 100 20 80
data sheet for exact information. Note the operation mode of the controller IC´s CAN transmit output (e.g.,
TX0) shall be set to push-pull operation with active low polarity.

Appendix E
125 kbit/s Medium Speed Bit Timing Example
Because CAN is an arbitrating protocol, the propagation delay must take into account the time required for a
signal to make a complete round trip from one ECU to another and back. This translates to the following
equation:

or
The following table defines the CAN bit timing requirements. Coordinated bit timing settings are required to

tBIT * 7960 8000 8040
tBUS** 0 ----- 400
tECU 30 ----- 1000
tQNom 3200 ----- 1000
tSEG1 *** *** ***
* The nominal bit time is typically a programmable, integer multiple of the CAN controller oscillator clock periods.
** tBUS considers one trip through 40 meters using a bus cable with a specific line delay of less than 8 ns/m.
The following table shows compliant bit timing settings for 125 kbit/s medium-speed CAN:
tQ/tB tQNom Sampling tTSEG2 tSJW BTR0 BTR1

(number of Mode (hex) Note 1 (hex)
time quanta
per bit)
12 666.67 ns Single 3 tQ 3 tQ $8… $27
(1.5 MHz)
13 615.38 ns Single 3 tQ 3 tQ $8… $28
(1.625 MHz)
14 571.43 ns Single 3 tQ 3 tQ $8… $29
(1.75 MHz)
15 533.33 ns Single 3 tQ 3 tQ $8… $2A
(1.875 MHz)


time quanta
per bit)
16 500 ns Single 3 tQ 3 tQ $8… $2B
(2.0 MHz)
17 470.59 ns Single 3 tQ 3 tQ $8… $2C
(2.125 MHz)
18 444.44 ns Single 3 tQ 3 tQ $8… $2D
(2.25 MHz)
19 421.05 ns Single 3 tQ 3 tQ $8… $2E
(2.375 MHz)
20 400 ns Single 4 tQ 4 tQ $C… $3E
(2.5 MHz)
21 380.95 ns Single 4 tQ 4 tQ $C… $3F
(2.625)
Note 1: BTR0 and BTR1 values apply to the SJA1000 controller. The BTR0 setting depends on the particular oscillator frequency used.
Refer to applicable data sheets for other controller products.
Note: tBIT is always set to 8000 ns. If the ECU is unable to be programmed to allow tBIT nominal to be equal to
8000 ns, then the offset shall be taken into account in the ∆f term not in the tBIT term .
1 + ∆f
Definition: ∆f equals the maximum allowable deviation (either maximum or minimum) from the specified
nominal bit rate divided by the specified nominal bit rate for specified values.

Implementation example of CAN bit time parameters on an Infotainment Bus.
Reference circuit used in the example: Intel 527
The system clock (SCLK) is set to: 8 MHz ± 0.5%
Nominal time quantum length: tQ = tSCLK * (BRP + 1)

tQ = 500 ns
If the number of tQ (N) is set to 21. That gives:
Nominal bit time: tBIT = 8 µs.
Nominal baudrate: f = 125 kbit/s
tSYNC_SEG = 1 tQ
With tSEG1 and tSEG2 is set to: tSEG1 = (TSEG1 + 1) * tQ = 12 tQ
tSEG2 = (TSEG2 + 1) * tQ = 3 tQ
That gives:
Sample Point: (tSYNC_SEG + tSEG1)/ tBIT 81.25 %
reSyncronisation Jump Width is set to: tSJW = (SJW + 1) * tQ = 3 tQ
That gives:
SJW: (tSJW/ tBIT) 18.75 %

table below:
fxtal TSEG1 TSEG2 SJW DSC BRP Note 1 CANbus tQ (ns) SJW Sample point
(MHz) speed (%) (%)
(kb/s)
4 11 2 2 0 1 125 500 18.75 81.25
8 11 2 2 0 3 125 500 18.75 81.25
12 11 2 2 0 5 125 500 18.75 81.25
16 11 2 2 0 7 125 500 18.75 81.25
20 11 2 2 0 9 125 500 18.75 81.25
Note the operation mode of the controller IC´s CAN transmit output (e.g. TX0) shall be set to push-pull operation with active low polarity.
Note 1: DSC and BRP values apply to the 82527 controller. See controller data sheets and application info for other products or clock
frequencies.

95.238 kbit/s Medium Speed Bit Timing Example

Because CAN is an arbitrating protocol, the propagation delay must take into account the time required for a
signal to make a complete round trip from one ECU to another and back. This translates to the following
equation:

or
The following table defines the CAN bit timing requirements. Coordinated bit timing settings are required to

tBIT * 10447.5 10500 10552.5
tBUS** 0 ----- 320
tECU 30 ----- 1000
tQNom 500 ----- 750
tSEG1 *** *** ***
* The nominal bit time is typically a programmable, integer multiple of the CAN controller oscillator clock periods.
** tBUS considers one trip through 40 meters using a bus cable with a specific line delay of less than 8 ns/m.
The following table shows compliant bit timing settings for medium-speed CAN:
(number of time Mode (hex)Note 1 (hex)
quanta per bit)
14 750 ns Single 3 tQ 3 tQ $8… $29

(1.333 MHz)
15 700 ns Single 3 tQ 3 tQ $8… $2A

(1.4286 MHz)
16 656.25 ns Single 4 tQ 3 tQ $8… $3A

(1.5238 MHz)

The following table shows compliant bit timing settings for medium-speed CAN:
time quanta
per bit)
14 750 ns Single 3 tQ 3 tQ $8… $29
(1.333 MHz)
15 700 ns Single 3 tQ 3 tQ $8… $2A
(1.4286 MHz)
16 656.25 ns Single 4 tQ 3 tQ $8… $3A
(1.5238 MHz)
17 617.65 ns Single 4 tQ 3 tQ $8… $3B
(1.619 MHz)
18 583.33 ns Single 4 tQ 3 tQ $8… $3C
(1.7143 MHz)
19 522.63 ns Single 4 tQ 3 tQ $8… $3D
(1.8095 MHz)
20 525 ns Single 5 tQ 4 tQ $C… $4D
(1.9048 MHz)
21 500 ns Single 5 tQ 4 tQ $C… $4E
(2 MHz)
18 583.33 ns 3x 3 tQ 3 tQ $8… $AC
(1.7143 MHz)
19 522.63 ns 3x 3 tQ 3 tQ $8… $AD
(1.8095 MHz)
20 525 ns 3x 4 tQ 4 tQ $C… $BD
(1.9048 MHz)
21 500 ns 3x 4 tQ 4 tQ $C… $BE
(2 MHz)
Note: tBIT is always set to 10500 ns. If the ECU is unable to be programmed to allow tBIT nominal to be equal to
10500 ns, then the offset shall be taken into account in the ∆f term not in the tBIT term .

1 + ∆f
Definition: ∆f equals the maximum allowable deviation (either maximum or minimum) from the specified
nominal bit rate divided by the specified nominal bit rate for specified values.
Implementation example of CAN bit time parameters on an Infotainment Bus.
Reference circuit used in the example: Intel 527
The system clock (SCLK) is set to: 8 MHz ± 0.5%
Nominal time quantum length: tQ = tSCLK * (BRP + 1)

tQ = 500 ns
If the number of tQ (N) is set to 21. That gives:
Nominal bit time: tBIT = 10.5 µs.
Nominal baudrate: f = 95.238 kbit/s
tSYNC_SEG = 1 tQ
With tSEG1 and tSEG2 is set to: tSEG1 = (TSEG1 + 1) * tQ = 15 tQ
tSEG2 = (TSEG2 + 1) * tQ = 5 tQ
That gives:
Sample Point: (tSYNC_SEG + tSEG1)/ tBIT 76.19 %
reSyncronisation Jump Width is set to: tSJW = (SJW + 1) * tQ = 4 tQ
That gives:
SJW: (tSJW/ tBIT) 19 %

table below:
fxtal TSEG1 TSEG2 SJW DSC BRP Note 1 CANbus tQ (ns) SJW Sample point
(MHz) speed (%) (%)
(kb/s)
4 14 4 3 0 1 95.238 500 19 76.19
8 14 4 3 0 3 95.238 500 19 76.19
12 14 4 3 0 5 95.238 500 19 76.19
16 14 4 3 0 7 95.238 500 19 76.19
20 14 4 3 0 9 95.238 500 19 76.19
Note the operation mode of the controller IC´s CAN transmit output (e.g. TX0) shall be set to push-pull operation with active low polarity.
Note 1: DSC and BRP values apply to the 82527 controller. See controller data sheets and application info for other products or clock
frequencies.

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WORDLWIDE General Specification

a. To state a binding requirement on the network

© Copyright 2005 General Motors Corporation All Rights Reserved

November 2005 Originating Department: North American Engineering Standards Page 1 of 42

© Copyright 2005 General Motors Corporation All Rights Reserved

Page 2 of 42 November 2005

© Copyright 2005 General Motors Corporation All Rights Reserved

November 2005 Page 3 of 42

Page 4 of 42 November 2005

© Copyright 2005 General Motors Corporation All Rights Reserved

November 2005 Page 5 of 42

Table 2: Wake Up Wire Output Parameter Specifications

3.3.1.4 Wake Up Input Requirements.

Table 3: Wake-Up Wire Input Parameter Specifications

Page 6 of 42 November 2005

© Copyright 2005 General Motors Corporation All Rights Reserved

November 2005 Page 7 of 42

Table 5: Wake up line input requirements

© Copyright 2005 General Motors Corporation All Rights Reserved

Page 8 of 42 November 2005

Two termination units EMC Caps GND

Figure 2: CAN Bus Application Circuit

November 2005 Page 9 of 42

Page 10 of 42 November 2005

© Copyright 2005 General Motors Corporation All Rights Reserved

November 2005 Page 11 of 42

Table 8: Common Mode Choke Asymmetrical Insertion Loss (Differential Mode)

Page 12 of 42 November 2005

© Copyright 2005 General Motors Corporation All Rights Reserved

November 2005 Page 13 of 42

Table 9: Transceiver Absolute Maximum Ratings Requirements

Short-Term Voltage t = 1 min - +26.5 V n/a

Sporadic Overshoot t = 0.5 s - +40 V +58 V

Transient Voltage t = 100 ns, -150 +100 V n/a

ESD protection HBM contact -4 +4 kV n/a

Page 14 of 42 November 2005

November 2005 Page 15 of 42

Page 16 of 42 November 2005

November 2005 Page 17 of 42

© Copyright 2005 General Motors Corporation All Rights Reserved

Page 18 of 42 November 2005

Parameter / Function Symbol Min Nom Max Unit Conditions / Comment

© Copyright 2005 General Motors Corporation All Rights Reserved

November 2005 Page 19 of 42

Transmit data from

Vdiff = VCANH - VCANL 0.7V

Transceiver internal delay

Figure 3: AC Parameters of Physical Medium Attachment

Figure 4: AC Parameters of Physical Medium Attachment

© Copyright 2005 General Motors Corporation All Rights Reserved

Page 20 of 42 November 2005

Table 11: High-Speed CAN Topology Specifications (Figure 4)

Ground wire length

© Copyright 2005 General Motors Corporation All Rights Reserved

November 2005 Page 21 of 42

Table 12: 125 kbit/s Medium-Speed CAN Parameter Specifications

© Copyright 2005 General Motors Corporation All Rights Reserved

Page 22 of 42 November 2005

Table 13: 95.238 kbit/s Medium-Speed CAN Parameter Specifications