Quartus II Introduction For Verilog Users

Quartus® II Introduction for Verilog Users
This tutorial presents an introduction to the Quartus® II software. It gives a general overview of a typical CAD
flow for designing circuits that are implemented by using FPGA devices, and shows how this flow is realized in the
Quartus® II software. The design process is illustrated by giving step-by-step instructions for using the Quartus®
II software to implement a simple circuit in an Altera® FPGA device.
The Quartus® II system includes full support for all of the popular methods of entering a description of the
desired circuit into a CAD system. This tutorial makes use of the Verilog design entry method, in which the
user specifies the desired circuit in the Verilog hardware description language. Another version of this tutorial is
available that uses VHDL hardware description language.
The screen captures in the tutorial were obtained using Quartus® II version 13.0; if other versions of the soft-
ware are used, some of the images may be slightly different.
Contents:
Getting Started
Starting a New Project
Design Entry Using Verilog Code
Compiling the Verilog Code
Using the RTL Viewer
Specifying Timing Constraints
Quartus® II Windows
Computer Aided Design (CAD) software makes it easy to implement a desired logic circuit by using a pro-
grammable logic device, such as a field-programmable gate array (FPGA) chip. A typical FPGA CAD flow is
illustrated in Figure 1.
Figure 1: Typical CAD flow.
It involves the following basic steps:

• Design Entry – the desired circuit is specified either by using a hardware description language, such as
Verilog or VHDL, or by means of a schematic diagram
• Synthesis – the CAD Synthesis tool synthesizes the circuit into a netlist that gives the logic elements (LEs)
needed to realize the circuit and the connections between the LEs
• Functional Simulation – the synthesized circuit is tested to verify its functional correctness; the simulation
does not take into account any timing issues
• Fitting – the CAD Fitter tool determines the placement of the LEs defined in the netlist into the LEs in
an actual FPGA chip; it also chooses routing wires in the chip to make the required connections between
specific LEs
• Timing Analysis – propagation delays along the various paths in the fitted circuit are analyzed to provide
an indication of the expected performance of the circuit
A LTERA® C ORPORATION 2
F EBRUARY 2013 Q UARTUS® II I NTRODUCTION FOR V ERILOG U SERS
• Timing Simulation – the fitted circuit is tested to verify both its functional correctness and timing
• Programming and Configuration – the designed circuit is implemented in a physical FPGA chip by pro-
gramming the configuration switches that configure the LEs and establish the required wiring connections
This tutorial introduces the basic features of the Quartus® II software. It shows how the software can be used to
design and implement a circuit specified using the Verilog hardware description language. It makes use of the
graphical user interface to invoke the Quartus® II commands. During this tutorial, the reader will learn about:
• Creating a project
• Synthesizing a circuit from Verilog code using the Quartus® II Integrated Synthesis tool
• Fitting a synthesized circuit into an Altera® FPGA

• Examining the report on the results of fitting and timing analysis
• Examining the synthesized circuit in the form of a schematic diagram generated by the RTL Viewer tool
• Making simple timing assignments in the Quartus® II software
1 GETTING STARTED
1 Getting Started
Each logic circuit, or subcircuit, being designed with the Quartus® II software is called a project. The software
works on one project at a time and keeps all information for that project in a single directory (folder) in the file
system. To begin a new logic circuit design, the first step is to create a directory to hold its files. To hold the design
files for this tutorial, we will use a directory called quartus_tutorial. The running example for this tutorial is a
simple adder/subtractor circuit, which is defined in the Verilog hardware description language.
Start the Quartus® II software. You should see a display similar to the one in Figure 2. This display consists
of several windows that provide access to all the features of the Quartus® II software, which the user selects with
the computer mouse. Most of the commands provided by the Quartus® II software can be accessed by using a set
of menus that are located below the title bar. For example, in Figure 2 clicking the left mouse button on the menu
named File opens the menu shown in Figure 3. Clicking the left mouse button on the entry Exit exits from the
Quartus® II software. In general, whenever the mouse is used to select something, the left button is used. Hence
we will not normally specify which button to press. In the few cases when it is necessary to use the right mouse
button, it will be specified explicitly.
For some commands it is necessary to access two or more menus in sequence. We use the convention Menu1
> Menu2 > Item to indicate that to select the desired command the user should first click the left mouse button
on Menu1, then within this menu click on Menu2, and then within Menu2 click on Item. For example, File >
Exit uses the mouse to exit from the system. Many commands can be invoked by clicking on an icon displayed in
one of the toolbars. To see the list of available toolbars, select Tools > Customize.... Once a toolbar is opened,
it can be moved using the mouse. To see the command associated with an icon, position the mouse over the icon
and a tooltip will appear that displays the command name.
It is possible to modify the appearance of the display in Figure 2 in many ways. Section 7 shows how to move,
resize, close, and open windows within the main Quartus® II display.
Figure 2: The main Quartus® II display.
1.1 Quartus® II Online Help 1 GETTING STARTED
Figure 3: An example of the File menu.
1.1 Quartus® II Online Help

The Quartus® II software provides comprehensive online documentation that answers many of the questions that
may arise when using the software. The documentation is accessed from the menu in the Help window. To get
some idea of the extent of documentation provided, it is worthwhile for the reader to browse through the Help
menu.
The user can quickly search through the Help topics by selecting Help > Search, which opens a web-based
interface with a dialog box into which keywords can be entered. Another method, context-sensitive help, is
provided for quickly finding documentation about specific topics. While using most applications, pressing the F1
function key on the keyboard opens a Help display that shows the commands available for the application.
2 STARTING A NEW PROJECT
2 Starting a New Project

To start working on a new design we first have to define a new design project. The Quartus® II software makes
the designer’s task easy by providing support in the form of a wizard.
1. Select File > New Project Wizard to reach a window that indicates the capability of this wizard. Press
Next. This will bring up the wizard screen as shown in Figure 4.
Figure 4: Creation of a new project.
2. Set the working directory to be quartus_tutorial; of course, you can use a directory name of your choice.
The project must have a name, which is usually the same as the top-level design entity that will be included
in the project. Choose addersubtractor as the name for both the project and the top-level entity, as shown in
Figure 4. Press Next. Since we have not yet created the directory quartus_tutorial, the Quartus® II software
displays the pop-up box in Figure 5 asking if it should create the desired directory. Click Yes, which leads
to the window in Figure 6.
Figure 5: The Quartus® II software can create a new directory for the project.
Figure 6: The wizard can include user-specified design files.
3. This window makes it easy to specify which existing files (if any) should be included in the project. Assum-
ing that we do not have any existing files, click Next, which leads to the window in Figure 7.
Figure 7: Choose the device family and a specific device.
4. In this window, we can specify the type of device in which the designed circuit will be implemented. Choose
the Stratix III® menu item as the target device family. We can let the Quartus® II software select a specific
device in the family, or we can choose the device explicitly. We will take the latter approach. From the list
of available devices, choose the device called EP3SE50F484C2. Press Next, which opens the window in
Figure 8.
Figure 8: Other EDA tools can be specified.
5. In this window we can specify any third-party tools that should be used. A commonly used term for CAD
software for electronic circuits is EDA tools, where the acronym stands for Electronic Design Automation.
This term is used in the Quartus® II messages that refer to third-party tools, which are the tools developed
and marketed by companies other than Altera® ; other tutorials show how such tools may be used. Since we
will rely solely on the Quartus® II tools, we will not choose any other tools. Press Next. Now, a summary
of the chosen settings appears in the screen shown in Figure 9. Press Finish, which returns to the main
Quartus® II display. Note that addersubtractor is now specified as the current project, as indicated in the
title bar at the top of the display. The screen should look similar to that of Figure 10.
Figure 9: Summary of the project settings.
Figure 10: The Quartus® II display for the created project.
3 DESIGN ENTRY USING VERILOG CODE
3 Design Entry Using Verilog Code

As a design example, we will use the adder/subtractor circuit shown in Figure 11. The circuit can add, subtract, and
accumulate n-bit numbers using the 2’s complement number representation. The two primary inputs are numbers
A = an−1 an−2 · · · a0 and B = bn−1 bn−2 · · · b0 , and the primary output is Z = zn−1 zn−2 · · · z0 . Another input
is the AddSub control signal which causes Z = A + B to be performed when AddSub = 0 and Z = A − B when
AddSub = 1. A second control input, Sel, is used to select the accumulator mode of operation. If Sel = 0, the
operation Z = A ± B is performed, but if Sel = 1, then B is added to or subtracted from the current value of Z.
If the addition or subtraction operations result in arithmetic overflow, an output signal, Overflow, is asserted.
To make it easier to deal with asynchronous input signals, we will load them into flip-flops on a positive edge
of the clock. Thus, inputs A and B will be loaded into registers Areg and Breg, while Sel and AddSub will be
loaded into flip-flops SelR and AddSubR, respectively. The adder/subtractor circuit places the result into register
Zreg.
Figure 11: The adder/subtractor circuit.
The required circuit is described by the Verilog code in Figure 12. For our example, we will use a 16-bit circuit
as specified by n = 16.
3 DESIGN ENTRY USING VERILOG CODE
// Top-level module
module addersubtractor (A, B, Clock, Reset, Sel, AddSub, Z, Overflow);
parameter n = 16;
input [n-1:0] A, B;
input Clock, Reset, Sel, AddSub;
output [n-1:0] Z;
output Overflow;
reg SelR, AddSubR, Overflow;
reg [n-1:0] Areg, Breg, Zreg;
wire [n-1:0] G, H, M, Z;
wire carryout, over_flow;
// Define combinational logic circuit

assign H = Breg ∧ {n{AddSubR}};
mux2to1 multiplexer (Areg, Z, SelR, G);
defparam multiplexer.k = n;
adderk nbit_adder (AddSubR, G, H, M, carryout);
defparam nbit_adder.k = n;
assign over_flow = carryout ∧ G[n-1] ∧ H[n-1] ∧ M[n-1];
assign Z = Zreg;
// Define flip-flops and registers

always @(posedge Reset or posedge Clock)
if (Reset == 1)
begin
Areg <= 0; Breg <= 0; Zreg <= 0;
SelR <= 0; AddSubR <= 0; Overflow <= 0;
end
else
begin
Areg <= A; Breg <= B; Zreg <= M;
SelR <= Sel; AddSubR <= AddSub; Overflow <= over_flow;
end
endmodule
// k-bit 2-to-1 multiplexer

module mux2to1 (V, W, Sel, F);
parameter k = 8;
input [k-1:0] V, W;
input Sel;
output [k-1:0] F;
reg [k-1:0] F;
always @(V or W or Sel)

if (Sel == 0) F = V;
else F = W;
endmodule
... continued in Part b
Figure 12: Verilog code for the circuit in Figure 11 (Part a)
3.1 Using the Quartus® II Text Editor 3 DESIGN ENTRY USING VERILOG CODE
// k-bit adder
module adderk (carryin, X, Y, S, carryout);
parameter k = 8;
input [k-1:0] X, Y;
input carryin;
output [k-1:0] S;
output carryout;
reg [k-1:0] S;
reg carryout;
always @(X or Y or carryin)

{carryout, S} = X + Y + carryin;
endmodule
Figure 12: Verilog code for the circuit in Figure 11 (Part b).
Note that the top Verilog module is called addersubtractor to match the name given in Figure 4, which was
specified when the project was created. This code can be typed into a file by using any text editor that stores
ASCII files, or by using the Quartus® II text editing facilities. While the file can be given any name, it is a
common designers’ practice to use the same name as the name of the top-level Verilog module. The file name
must include the extension v, which indicates a Verilog file. So, we will use the name addersubtractor.v.
3.1 Using the Quartus® II Text Editor

This section demonstrates how to use the Quartus® II Text Editor. You can skip this section if you prefer to use
another text editor to create the addersubtractor.v file.
1. Select File > New to get the window in Figure 13, choose Verilog HDL File, and click OK. This opens the
Text Editor window.
Figure 13: Choose to prepare a Verilog file.
2. The first step is to specify a name for the file that will be created. Select File > Save As to open the pop-up
box shown in Figure 14. In the field labeled Save as type choose Verilog HDL File. In the field labeled
File name type addersubtractor. Put a checkmark in the box Add file to current project. Click Save,
which puts the file into the directory quartus_tutorial and leads to the Text Editor window shown in Figure
15.
Figure 14: Name the file.
Figure 15: The Quartus® II display after saving the file.
3. Enter the Verilog code in Figure 12 into the Text Editor Window, which is located on the right side of the
screen. Save the file by going to File > Save, or by typing the shortcut Ctrl-s.
Most of the commands available in the Text Editor are self-explanatory. Text is entered at the insertion point,
which is indicated by a thin vertical line. The insertion point can be moved either by using the keyboard arrow
keys or by using the mouse. Two features of the Text Editor are especially convenient for typing Verilog code.
First, the editor can display different types of Verilog statements in different colors, which is the default choice.
Second, the editor can automatically indent the text on a new line so that it matches the previous line. Such options
can be controlled by the settings in Tools > Options... > Text Editor, as shown in Figure 16.
3.2 Adding Design Files to a Project 3 DESIGN ENTRY USING VERILOG CODE
Figure 16: Text Editor Options.
3.1.1 Using Verilog Templates

The syntax of Verilog code is sometimes difficult for a designer to remember. To help with this issue, the Text
Editor provides a collection of Verilog templates. The templates provide examples of various types of Verilog
statements, such as a module declaration, an always block, and assignment statements. It is worthwhile to browse
through the templates by selecting Edit > Insert Template > Verilog HDL to become familiar with these re-
sources.
3.2 Adding Design Files to a Project

As we indicated when discussing Figure 6, you can tell the Quartus® II software which design files it should
use as part of the current project. To see the list of files already included in the addersubtractor project, select
Assignments > Settings... > Files, which leads to a window similar to the window in Figure 17. An alternative
way of making this selection is to go to Project > Add/Remove Files in Project....
If you used the Quartus® II Text Editor to create the file and checked the box labeled Add file to current
project, as described in Section 3.1, then the addersubtractor.v file is already a part of the project and will be
listed in the window in Figure 17. Otherwise, the file must be added to the project.
Figure 17: Settings window.
1. If not already done, place a copy of the file addersubtractor.v into the directory quartus_tutorial.
2. To add this file to the project, click on the ... button beside the File name field in Figure 17 to get the
pop-up window in Figure 18.
Figure 18: Select the file.
3. Select the addersubtractor.v file and click Open. The selected file is now indicated in the File name field
of Figure 17. Click Add and then OK to include the addersubtractor.v file in the project.
We should mention that in many cases the Quartus® II software is able to automatically find the right files to
use for each entity referenced in Verilog code, even if the file has not been explicitly added to the project. However,
for complex projects that involve many files it is a good design practice to specifically add the needed files to the
project, as described above.
4 COMPILING THE VERILOG CODE
4 Compiling the Verilog Code

The Verilog code is processed by several Quartus® II tools that analyze the code and generate an implementation
of it for the target chip. These tools are controlled by the application program called the Compiler.
1. Run the Compiler by selecting Processing > Start Compilation, or by using the toolbar icon . As
the compilation moves through various stages, its progress is reported in the Tasks window on the left
side. This window also provides a comprehensive interface to edit, start, and monitor different stages of
the compilation. Successful (or unsuccessful) compilation is indicated in a pop-up box. Acknowledge it
by clicking OK. This leads to the Quartus® II display in Figure 19, in which we have expanded the Entity
hierarchy in the top left corner to show all modules in the addersubtractor design. In the message window,
located at the bottom of the display, various messages are shown. In case of errors, there will be appropriate
messages given.
Figure 19: Display after a successful compilation.
2. When the compilation is finished, a compilation report is produced. A window showing this report, dis-
played in Figure 20, is opened automatically. The window can be resized, maximized, or closed in the
normal way, and it can be opened at any time either by selecting Processing > Compilation Report or
by clicking on the icon in the toolbar. The report includes a number of sections listed on the left side
of its window. Figure 20 shows the Compiler Flow Summary section, which indicates that only a miniscule
amount of chip resources are needed to implement this tiny circuit on the selected FPGA chip.
Figure 20: Compilation report.
The Compilation Report provides a lot of information that may be of interest to the designer, such as the speed
of the implemented circuit. A good measure of the speed is the maximum frequency at which the circuit can be
clocked, referred to as fmax. This measure depends on the longest delay along any path between two registers
clocked by the same clock. The Quartus® II software performs a timing analysis to determine the expected
performance of the circuit. It evaluates several parameters, which are listed in the TimeQuest Timing Analyzer
section of the Compilation Report.
3. Expand the TimeQuest Timing Analyzer section of the report, as shown in Figure 21. Notice there are mul-
tiple models included, which describe the performance of the circuit under different operating conditions.
Expand the report for Slow 1100mV 85C Model and click on the item Fmax Summary to display the table
in Figure 21. The table shows that the maximum frequency for our circuit implemented on the specified chip
is 475.06 MHz. You may get a different value of fmax, dependent on the specific version of the Quartus® II
software installed on your computer.
Figure 21: Fmax Summary of TimeQuest Timing Analysis.
4. While fmax is a function of the longest propagation delay between two registers in the circuit, it does not
indicate the delays with which output signals appear at the pins of the chip. Time elapsed from an active
edge of the clock signal at the clock source until a corresponding output signal is produced (from a flip-flop)
at an output pin is denoted as the Clock to Output Time at that pin. To see this parameter, expand Datasheet
Report under the Slow 1100mV 85C Model heading and select Clock to Output Times to obtain the
display in Figure 22. For each output signal, the delays for rise edge and fall edge are listed. The clock
signal and its active edge are also shown in the table. Two other parameters listed in the Datasheet Report
are Setup Times and Hold Times. The Setup Time measures the length of time for which data that feeds a
register must be present at an input pin before the clock signal is asserted at the clock pin. The Hold Time
measures the minimum length of time for which data that feeds a register must be retained at an input pin
after the clock signal is asserted at the clock pin.
Figure 22: The Clock to Output Time delays.
5. An indication of where the circuit is implemented on the chip is available by selecting Tools > Chip
Planner(Floorplan and Chip Editor), or by clicking on the icon . This opens the Chip Planner display,
as shown in Figure 23. This display highlights the location of the logic elements used to implement the
circuit. To make the image appear as shown in Figure 23 you may have to select View > Fit in Window
(shortcut Ctrl-Alt-w).
Figure 23: View of the floorplan.
6. A Zoom Tool, activated by the icon in the left hand toolbar, can be used to enlarge parts of the image
even more. You can click and drag a box over an area of the chip to quickly zoom into that part of the chip.
Figure 24 shows a zoomed-in view of the floorplan that highlights the implemented circuit. By positioning
the cursor on any logic element, the designer can see what part of the circuit is implemented in this resource.
The chip planner tool has several icons that can be used to view aspects such as fan-in and fan-out of nodes,
connecting paths between nodes, and so on. For more information on using this tool, refer to Help by
selecting Help > Search > Contents > Achieving Timing Closure > Working With Assignments in
the Chip Planner from the main Quartus® II display.
Figure 24: A portion of the expanded view.
4.1 Errors 4 COMPILING THE VERILOG CODE
4.1 Errors
The Quartus® II software displays messages produced during compilation in the Messages window. If the Verilog
design file is correct, one of the messages will state that the compilation was successful and that there are no errors.
If the Compiler does not report zero errors, then there is at least one mistake in the Verilog code. In this case,
a message corresponding to each error found will be displayed in the Messages window. Double-clicking on an
error message will highlight the offending statement in the Verilog code in the Text Editor window. Similarly, the
Compiler may display some warning messages. Their details can be explored in the same way as in the case of
error messages. The user can obtain more information about a specific error or warning message by selecting the
message and pressing the F1 function key.
1. To see the effect of an error, open the file addersubtractor.v. Line 14 has the statement
assign H = Breg ∧ {n{AddSubR}};
Remove the semicolon in this statement, illustrating a typographical error that is easily made. Compile the
erroneous design file. The Quartus® II software displays a pop-up box indicating that the compilation was
not successful. Acknowledge it by clicking OK. The compilation report summary, given in Figure 25, now
confirms the failed result.
Figure 25: Compilation report for the failed design.
2. In this window, Click on Analysis & Synthesis > Messages to have all messages displayed as shown in
Figure 26.
4.1 Errors 4 COMPILING THE VERILOG CODE
Figure 26: Error messages.
3. Double-click on the first error message, which states that there is a Verilog syntax error. The Quartus® II
software responds by opening the addersubtractor.v file and highlighting the statement affected by the error,
as shown in Figure 27. Correct the error and recompile the design.
Figure 27: Identifying the location of the error.
5 USING THE RTL VIEWER
5 Using the RTL Viewer

The Quartus® II software includes a tool that can display a schematic diagram of the designed circuit. The display
is at the Register Transfer Level of detail, and the tool is called the RTL Viewer.
1. Click Tools > Netlist Viewers > RTL Viewer, to reach the window shown in Figure 28.
Figure 28: The addersubtractor circuit displayed by the RTL Viewer.
The displayed image shows the structure of the entire addersubtractor circuit. The inputs to the circuit, shown
on the left side, are registered. The two subcircuits, defined by the mux2to1 and adderk modules, are drawn as
shaded boxes and their respective names appear above the boxes. The remainder of the circuit are the XOR gates
used to complement the B vector when subtraction is performed, and the circuitry needed to generate the Overflow
signal.
2. Use the Zoom Tool, located in the toolbar, to enlarge the image and view the upper-left portion of the circuit,
as illustrated in Figure 29. Note that individual flip-flops are used for the AddSub and Sel signals. Sixteen-bit
vectors A and B are denoted by heavy lines connected to the registers, Areg and Breg, which are indicated
as heavily outlined flip-flop symbols. The Zreg register is drawn in the same manner as Areg and Breg.
5 USING THE RTL VIEWER
Figure 29: An enlarged view of the circuit.
3. Details of subcircuits can be seen by clicking on the box that represents a subcircuit. Select the Selection
Tool from the toolbar (near the Zoom Tool), and double-click on the mux2to1 box to obtain the image in
Figure 30. It shows the multiplexers used to choose either the Areg or Z vector as one of the inputs to the
adder, under control of the Sel signal. Observe that the multiplexer data inputs are labeled as specified in the
Verilog code for the mux2to1 module in part b of Figure 12, namely as V and W rather than Areg and Z.
Figure 30: The multiplexer subcircuit.
The RTL viewer is a useful tool. It can be used effectively to facilitate the development of Verilog code for
a circuit that is being designed. It provides a pictorial feedback to the designer, which gives an indication of the
structure of the circuit that the code will produce. Viewing the pictures makes it easy to spot missing elements,
wrong connections, and other typical errors that one makes early in the design process.
6 SPECIFYING TIMING CONSTRAINTS
6 Specifying Timing Constraints

The Quartus® II software allows the user to specify timing constraints for the designed circuit.
1. Open TimeQuest Timing Analyzer by selecting Tools > TimeQuest Timing Analyzer, or by clicking the
icon . Figure 31 shows the interface of TimeQuest Timing Analyzer. It is a very powerful tool for
the designer to create, manage, and analyze timing constraints, and to quickly perform timing verification
for their design. The compilation in Section 4 produced the fmax of 475.06 MHz, which translates to a
minimum period of 2.105 ns. Suppose that we need a circuit that can operate at a clock frequency of 480
MHz. We can use the TimeQuest Timing Analyzer tool to create a new SDC (Synopsys Design Constraints)
file containing the clock constraint.
Figure 31: TimeQuest Timing Analyzer.
In the TimeQuest Analyzer window, double click Create Timing Netlist under the Tasks heading to gen-
erate the timing netlist from database created after compilation. Then select Constraints > Create Clock
from the menu to reach the dialog box in Figure 32. Specify a name for the clock you want to constrain.
This name can be used to refer to this clock when creating other timing constraints. For this example, we
will name the clock "CLOCK". As we want the circuit to operate at a clock frequency of 480 MHz, set the
period to 2.08 ns in the Period field. To specify the actual clock this constraint is applied to, click on the ...
button beside the Targets field in the Create Clock window to get the pop-up window in Figure 33.
Figure 32: Create clock constraints.
Figure 33: Choose target clock.
Click on the list button in the middle left of the window to get a list of all the ports. Select Clock from
the list of matches on the left and click on the > button to reach the display in Figure 33. This tells the
TimeQuest Timing Analyzer to constrain the Clock port to the period you have specified. Notice in a larger
design with many ports, we can enter the name of the port in the Filter field located in the top right of the
window to reduce the number of matches in our search. Click OK to return to the dialog box in Figure 34.
Figure 34: Complete clock constraint.
In the SDC command field at the bottom of the dialog box in Figure 34, we can see the actual command
that would be written into the SDC file. It creates a simple clock named CLOCK with a 2.08 ns period
and associates this constraint with the port Clock. Click Run to return to the window in Figure 31. Se-
lect Constraints > write SDC File and save the file as addersubtractor.out.sdc in the project directory
quartus_tutorial. Close the TimeQuest Timing Analyzer window to return to the Quartus® II main display.
2. From the main Quartus® II window, click Assignments > Settings... > TimeQuest Timing Analyzer
to reach the window in Figure 35. Here, we can add the SDC file we have created to the project. Click on
the ... button beside the SDC filename field and select addersubtractor.out.sdc, which is the SDC file we
created using TimeQuest Timing Analyzer. Click on Open to return to the window in Figure 35 and click
Add to associate the SDC file with this project. Click OK to return to the main Quartus® II window.
Figure 35: Adding SDC file to project.
The Quartus® II Compiler includes a Fitter executable that places the designed circuit into the available
logic elements on the chip and generates the necessary wiring connections to realize the circuit. This is a
complex process that can take a long time, particularly if the circuit is large and an ambitious value of fmax
is specified. The time can be reduced if a lower value of fmax is acceptable. The user can indicate the level
of the Fitter’s effort.
3. From the main Quartus® II window, click Assignments > Settings... and then select the category Fitter
Settings which opens the window in Figure 36. Three different levels of effort can be given. Choose the
Auto Fit option, which instructs the Fitter to stop as soon as it finds an adequate implementation. The Fast
Fit option reduces the compilation time, but it may produce a lower fmax. The third option, Standard Fit,
forces the Fitter to produce the best implementation it can find; at this effort level the Fitter will exceed the
user’s timing requirements as much as it can, which often results in longer compilation time. Click OK, and
recompile the circuit.
Figure 36: Fitter settings.
4. The new timing results are shown in Figure 37. The new fmax is 501.5 MHz, which meets the specified
requirement.
Figure 37: New timing results.
The fmax of a circuit is limited by the path with the longest delay. To view this critical path of this circuit,
open the TimeQuest Timing Analyzer. Under the Tasks heading, select Reports > Custom Reports >
Report Timing... and double-click on it. This creates the dialog box in Figure 38. In the drop down boxes
labeled From clock and To clock, select CLOCK, which is the name we specified for the clock in the circuit
when we were creating the SDC file. Use a value of 10 for the Report number of paths field, located in
the Paths section of the window, to reach the display in Figure 38. Click on the Report Timing button to
start the analysis. After the analysis is complete, a timing report similar to Figure 39 will be displayed.
Figure 38: Create timing report.
The Report Timing window shows the ten paths with the longest delays in our circuit. We see that the
critical path begins at SelR and ends at Overflow. The first column in the top part of the window shows the
slack for each path, which is the amount of delay that could still be added to a given path without violating
the specified timing constraint. The bottom part of the window shows the actual elements in the selected
path and the incremental delay for each stage in the path.
Figure 39: Critical path.
7 QUARTUS® II WINDOWS
7 Quartus® II Windows
The Quartus® II display contains several utility windows which can be positioned in various places on the screen,
changed in size, or closed. In Figure 19, which is reproduced in Figure 40, there are five windows.
Figure 40: The main Quartus® II display.
The Project Navigator window is shown near the top left of the figure. Under the heading Entity, it depicts a
tree-like structure of the designed circuit using the names of the modules in the Verilog code of Figure 12.
1. To see the usefulness of this window, open the previously compiled project quartus_tutorial\addersubtractor.qpf
to get a window similar to Figure 40.
2. Double-click on the name adderk in the hierarchy under the Entity heading. The Quartus® II software will
open the file addersubtractor.v and highlight the Verilog module that specifies the adder subcircuit.
3. Right-click on the same name and choose Locate > Locate in Chip Planner(Floorplan & Chip Editor)
from the pop-up menu that appears. This causes the Quartus® II software to display the floorplan, as in
Figure 23, and highlight the part that implements the adder subcircuit.
The Tasks window is located below the Project Navigator window in the Quartus® II main window. As you
have already observed, this window displays the compilation progress. It can also be used to edit and start different
7 QUARTUS® II WINDOWS
stages of the compilation. Double-clicking on a compilation stage from the Tasks window causes that stage of the
compilation to be re-run.
At the bottom of the Quartus® II main window is the Message window, which displays user messages produced
during the compilation process.
The large area in the middle-right of the Quartus® II window is used for various purposes. As we have seen, it
is used by Report Viewers and the Text Editor.
A utility window can be moved by dragging its title bar, resized by dragging the window border, or closed by
clicking on the X in the top-right corner of that window. A particular utility window can be opened by selecting it
from the View > Utility Windows menu.
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Quartus® II Introduction for Verilog Users

Figure 1: Typical CAD flow.

It involves the following basic steps:

• Fitting a synthesized circuit into an Altera® FPGA

Figure 2: The main Quartus® II display.

Figure 3: An example of the File menu.

1.1 Quartus® II Online Help

2 Starting a New Project

Figure 4: Creation of a new project.

Figure 6: The wizard can include user-specified design files.

Figure 7: Choose the device family and a specific device.

Figure 8: Other EDA tools can be specified.

Figure 9: Summary of the project settings.

Figure 10: The Quartus® II display for the created project.

3 Design Entry Using Verilog Code

Figure 11: The adder/subtractor circuit.

// Define combinational logic circuit

// Define flip-flops and registers

// k-bit 2-to-1 multiplexer

always @(V or W or Sel)

... continued in Part b

Figure 12: Verilog code for the circuit in Figure 11 (Part a)

always @(X or Y or carryin)

3.1 Using the Quartus® II Text Editor

Figure 13: Choose to prepare a Verilog file.

Figure 14: Name the file.

Figure 15: The Quartus® II display after saving the file.

Figure 16: Text Editor Options.

3.1.1 Using Verilog Templates

3.2 Adding Design Files to a Project

Figure 17: Settings window.

Figure 18: Select the file.

4 Compiling the Verilog Code

Figure 19: Display after a successful compilation.

Figure 20: Compilation report.

Figure 21: Fmax Summary of TimeQuest Timing Analysis.

Figure 22: The Clock to Output Time delays.

Figure 23: View of the floorplan.

Figure 24: A portion of the expanded view.

assign H = Breg ∧ {n{AddSubR}};

Figure 25: Compilation report for the failed design.

Figure 26: Error messages.

Figure 27: Identifying the location of the error.

5 Using the RTL Viewer

Figure 28: The addersubtractor circuit displayed by the RTL Viewer.

Figure 29: An enlarged view of the circuit.

Figure 30: The multiplexer subcircuit.

6 Specifying Timing Constraints

Figure 31: TimeQuest Timing Analyzer.

Figure 32: Create clock constraints.

Figure 33: Choose target clock.

Figure 34: Complete clock constraint.

Figure 35: Adding SDC file to project.

Figure 36: Fitter settings.

Figure 37: New timing results.

Figure 38: Create timing report.

Figure 39: Critical path.

Figure 40: The main Quartus® II display.

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