Advance Information: 128 RGB X 160 Dot Matrix OLED/PLED Segment/Common Driver With Controller

SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1355
Advance Information
128 RGB x 160 Dot Matrix
OLED/PLED Segment/Common Driver with Controller
This document contains information on a new product. Specifications and information herein are subject to change
without notice.
http://www.solomon-systech.com
SSD1355 Rev 1.2 P 1/111 Oct 2007 Copyright © 2007 Solomon Systech Limited
CONTENTS
1 GENERAL DESCRIPTION ....................................................................................................6
2 FEATURES................................................................................................................................6
3 ORDERING INFORMATION ................................................................................................7
4 BLOCK DIAGRAM..................................................................................................................8
5 DIE FLOOR PLAN...................................................................................................................9
6 PIN ARRANGEMENT...........................................................................................................12
6.1 SSD1355U2R1 PIN ASSIGNMENT ....................................................................................................... 12
7 PIN DESCRIPTIONS .............................................................................................................21
8 FUNCTIONAL BLOCK DESCRIPTIONS..........................................................................24
8.1 MCU INTERFACE ................................................................................................................................ 24
8.1.1 MCU Parallel 6800-series Interface................................................................................................................24
8.1.2 MCU Parallel 8080-series Interface................................................................................................................25
8.1.3 MCU Serial Interface (4-wire SPI) .................................................................................................................26
8.1.4 MCU Serial Interface (3-wire SPI) .................................................................................................................27
8.2 RESET CIRCUIT .................................................................................................................................... 28
8.3 GDDRAM........................................................................................................................................... 28
8.3.1 GDDRAM structure........................................................................................................................................28
8.3.2 Data bus to RAM mapping under different input mode..................................................................................29
8.4 COMMAND DECODER .......................................................................................................................... 30
8.5 OSCILLATOR & TIMING GENERATOR.................................................................................................. 30
8.5.1 Oscillator.........................................................................................................................................................30
8.6 SEG/COM DRIVING BLOCK ................................................................................................................ 31
8.7 SEG / COM DRIVER ............................................................................................................................ 32
8.8 GRAY SCALE DECODER ...................................................................................................................... 35
8.9 POWER ON AND OFF SEQUENCE ........................................................................................................ 37
8.10 TEARING EFFECT TIMING ................................................................................................................ 38
8.11 VDD REGULATOR ............................................................................................................................. 39
8.11.1 VDD Regulator in Sleep Mode.........................................................................................................................40
9 COMMAND.............................................................................................................................41
9.1 BASIC COMMAND LIST........................................................................................................................ 41
9.2 SUPPLEMENTARY COMMAND LIST ..................................................................................................... 42
9.3 COMMAND DESCRIPTION .................................................................................................................... 43
9.3.1 NOP (00h).......................................................................................................................................................43
9.3.2 Software Reset (01h).......................................................................................................................................44
9.3.3 Read Display Identification Information (04h)...............................................................................................45
9.3.4 Read Display Power Mode (0Ah) ...................................................................................................................46
9.3.5 Read Display MADCTL (0Bh).......................................................................................................................47
9.3.6 Read Display Pixel Format (0Ch)...................................................................................................................48
9.3.7 Read Display Image Mode (0Dh) ...................................................................................................................49
9.3.8 Read Display Signal Mode (0Eh) ...................................................................................................................50
9.3.9 Sleep In (10h)..................................................................................................................................................51
9.3.10 Sleep Out (11h)...............................................................................................................................................52
9.3.11 Enable Partial Display (12h) ...........................................................................................................................53
9.3.12 Normal Display Mode ON (13h) ....................................................................................................................54
9.3.13 Display Inversion OFF (20h) ..........................................................................................................................55
9.3.14 Display Inversion ON (21h)............................................................................................................................56
9.3.15 All Pixels ON (23h) ........................................................................................................................................57
Solomon Systech Oct 2007 P 2/111 Rev 1.2 SSD1355

9.3.16 All Pixels OFF (28h).......................................................................................................................................58
9.3.17 Disable All Pixels ON/OFF (29h)...................................................................................................................59
9.3.18 Set Column Address (2Ah) .............................................................................................................................60
9.3.19 Set Row Address (2Bh) ..................................................................................................................................61
9.3.20 Memory Write (2Ch) ......................................................................................................................................62
9.3.21 Memory Read (2Eh) .......................................................................................................................................63
9.3.22 Partial Area (30h)............................................................................................................................................64
9.3.23 Vertical Scrolling Definition (33h) .................................................................................................................65
9.3.24 Disable Tearing Effect (34h)...........................................................................................................................66
9.3.25 Enable Tearing Effect (35h)............................................................................................................................66
9.3.26 Memory Access Control (36h)........................................................................................................................67
9.3.27 Vertical Scrolling Start Address (37h)............................................................................................................73
9.3.28 Interface Pixel Format (3Ah) ..........................................................................................................................74
9.3.29 Write Luminance (51h)...................................................................................................................................75
9.3.30 Read Luminance Value (52h) .........................................................................................................................76
9.3.31 Read Display Identification Information (DAh) .............................................................................................77
9.3.32 OTP Write (B1h) ............................................................................................................................................78
9.3.33 OTP MCU Read (B2h) ...................................................................................................................................80
9.3.34 Function Selection (B3h) ................................................................................................................................81
9.3.35 Linear Gamma Look Up Table (B9h).............................................................................................................82
9.3.36 Set Contrast For Color A, B &C (BAh)..........................................................................................................83
9.3.37 Set First Pre-Charge Voltage (BDh) ...............................................................................................................84
9.3.38 Gamma Look Up Table (BEh)........................................................................................................................85
9.3.39 Set Display Offset (C8h).................................................................................................................................87
9.3.40 Horizontal Scrolling (C9h) .............................................................................................................................88
9.3.41 Set MUX ratio (CAh)......................................................................................................................................89
9.3.42 Set Phase Length (CDh)..................................................................................................................................90
9.3.43 Set Second Precharge Period (CEh)................................................................................................................91
9.3.44 Set Second Precharge speed (CFh) .................................................................................................................92
9.3.45 Set Display Clock Divider / Oscillator Frequency (D2h) ...............................................................................93
9.3.46 Set VCOMH (D3h) .............................................................................................................................................94
9.3.47 GPIO (D7h).....................................................................................................................................................95
9.3.48 Command Lock (FDh)....................................................................................................................................96
10 MAXIMUM RATINGS ..........................................................................................................97
11 DC CHARACTERISTICS .....................................................................................................98
12 AC CHARACTERISTICS .....................................................................................................99
13 APPLICATION EXAMPLE ................................................................................................104
14 PACKAGE INFORMATION ..............................................................................................105
14.1 SSD1355U2R1 DETAIL DIMENSION ............................................................................................. 105
SSD1355 Rev 1.2 P 3/111 Oct 2007 Solomon Systech

TABLES
Table 3-1 : Ordering Information .........................................................................................................................................7
Table 5-1 : SSD1355Z Pin Assignment Table....................................................................................................................10
Table 6-1 : SSD1355U2R1 Pin Assignment Table.............................................................................................................13
Table 6-2: SSD1355U3R1 Pin Assignment Table..............................................................................................................16
Table 6-3: SSD1355U6R1 Pin Assignment Table..............................................................................................................19
Table 27-1 : SSD1355 Pin Description...............................................................................................................................21
Table 27-2 : Bus Interface selection ...................................................................................................................................22
Table 7-1 : MCU interface assignment under different bus interface mode .......................................................................24
Table 7-2 : Data bus selection modes .................................................................................................................................24
Table 7-3 : Control pins of 6800 interface..........................................................................................................................24
Table 7-4 : Control pins of 8080 interface..........................................................................................................................26
Table 7-5 : Control pins of 4-wire Serial interface .............................................................................................................26
Table 7-6 : Control pins of 3-wire Serial interface .............................................................................................................27
Table 7-7 : 262k Color Depth Graphic Display Data RAM Structure................................................................................28
Table 7-8 : Write Data bus usage under different bus width and color depth mode ...........................................................29
Table 7-9 : Read Data bus usage under different bus width and color depth mode............................................................29
Table 7-10 : Gamma Settings with identical brightness in current drive phase..................................................................36
Table 8-1 : Controls for column and row counters under different conditions ...................................................................62
Table 8-2 : Colour contrast adjustment...............................................................................................................................78
Table 9-1 : Maximum Ratings ............................................................................................................................................97
Table 10-1 : DC Characteristics..........................................................................................................................................98
Table 11-1 : AC Characteristics..........................................................................................................................................99
Table 11-2 : 6800-Series MCU Parallel Interface Timing Characteristics .......................................................................100
Table 11-3 : 8080-Series MCU Parallel Interface Timing Characteristics .......................................................................101
Table 11-4 : Serial Interface Timing Characteristics (4-wire SPI) ...................................................................................102
Table 11-5 : Serial Interface Timing Characteristics (3-wire SPI) ...................................................................................103

FIGURES
Figure 4-1 Block Diagram ....................................................................................................................................................8
Figure 5-1 : SSD1355Z Die drawing ....................................................................................................................................9
Figure 6-1: SSD1355U2R1 Pin Assignment ......................................................................................................................12
Figure 7-1 : Data read back procedure - insertion of dummy read .....................................................................................25
Figure 7-2 : Example of Write procedure in 8080 parallel interface mode ........................................................................25
Figure 7-3 : Example of Read procedure in 8080 parallel interface mode .........................................................................25
Figure 7-4 : Display data read back procedure - insertion of dummy read.........................................................................26
Figure 7-5 : Write procedure in 4-wire Serial interface mode ............................................................................................27
Figure 7-6 : Write procedure in 3-wire Serial interface mode ............................................................................................27
Figure 7-7 : Oscillator Circuit.............................................................................................................................................30
Figure 7-8 : IREF Current Setting by Resistor Value............................................................................................................31
Figure 7-9 : Segment and Common Driver Block Diagram ...............................................................................................32
Figure 7-10 : Segment and Common Driver Signal Waveform..........................................................................................33
Figure 7-11: Gray Scale Control in Segment......................................................................................................................34
Figure 7-12 : Relation between GDDRAM content and Gray Scale table entry for three colors in 262K color mode
(under command B9h Linear Gamma Look Up Table) ..............................................................................................35
Figure 7-13 : Illustration of current drive phase (phase 4) under different Gamma Settings..............................................35
Figure 7-14: The Power ON sequence................................................................................................................................37
Figure 7-15: The Power OFF sequence ..............................................................................................................................37
Figure 7-16 VCI > 2.6V, VDD regulator enable : pin connection scheme ............................................................................39
Figure 7-17 VDD regulator disable : pin connection scheme...............................................................................................39
Figure 7-18 : Case 1 - Command sequence for just entering/ exiting sleep mode..............................................................40
Figure 7-19 : Case 2 - Command sequence for disabling internal VDD regulator during sleep mode.................................40
Figure 8-1 : Transition between different modes................................................................................................................54
Figure 8-2 : Example of Inverse Display OFF....................................................................................................................55
Figure 8-3 : Example of Inverse Display ON .....................................................................................................................56
Figure 8-4 : Example of all pixel ON .................................................................................................................................57
Figure 8-5 : Example of all pixels OFF ..............................................................................................................................58
Figure 8-6 : Example of Disable All Pixels ON/OFF .........................................................................................................59
Figure 8-7 : Example of partial display function ................................................................................................................64
Figure 8-8 : Address Pointer Movement of Horizontal Address Increment Mode .............................................................67
Figure 8-9 : Address Pointer Movement of Vertical Address Increment Mode .................................................................68
Figure 8-10 : Example Bit A[5], A[6], A[7] in command MADCTL (36h).......................................................................68
Figure 8-11 : COM Pins Hardware Configuration (MUX ratio: 160) ................................................................................69
Figure 8-12 : Example of Gamma correction by Gamma Look Up table setting ...............................................................86
Figure 8-13 : Example of Set Display Start Line with no Remap (i.e. Command 36h bit A7=0b) ....................................87
Figure 11-1 : 6800-series MCU parallel interface characteristics.....................................................................................100
Figure 11-2 : 8080-series MCU parallel interface characteristics.....................................................................................101
Figure 11-3 : Serial interface characteristics (4-wire SPI)................................................................................................102
Figure 11-4 : Serial interface characteristics (3-wire SPI)................................................................................................103
Figure 12-1 : SSD1355 application example for 18-bit 6800-parallel interface mode (Internal regulated VDD)..............104
Figure 13-1 : SSD1355U2R1 Detail Dimension...............................................................................................................105

1 GENERAL DESCRIPTION
The SSD1355 is a CMOS OLED/PLED driver with 384 segments and 160 commons output, supporting
up to 128RGB x 160 dot matrix display. This chip is designed for Common Cathode type OLED/PLED
panel.
The SSD1355 had embedded Graphic Display Data RAM (GDDRAM). It supports with 8, 16, 18 bits
8080 / 6800 parallel interface, Serial Peripheral Interface. It has 256-step contrast and 262K color control,
giving vivid color display on OLED panels. This driver IC can be used in many different applications
such as MP3, PDA, PMP, mobile phone and Digital Camera.
2 FEATURES
• Resolution: 128 RGB x 160 dot matrix panel
• 262k color depth supported by embedded 128x160x18 bit SRAM display buffer
• Power supply
o VDD = 2.4V – 2.6V (Core VDD power supply, can be regulated from VCI)
o VDDIO = 1.6V – VCI (MCU interface logic level)
o VCI = 2.4V - 3.5V (Low voltage power supply)
o VCC = 10.0V – 21.0V (Panel driving power supply)
o When VCI is lower than 2.6V, VDD should be supplied by external power source
• Segment maximum source current: 200uA
• Common maximum sink current: 80mA
• 256 step brightness current control for the each color component plus 16 step master current control
• Pin selectable MCU Interfaces:
o 8/16/18 bits 6800-series parallel interface
o 8/16/18 bits 8080-series parallel interface
o 3 –wire and 4-wire Serial Peripheral Interface
• Support various color depths
o 262k color (6:6:6)
o 65k color (5:6:5)
• OLED Driving Scheme: PAM + PWM
• Three programmable Gamma Look Up Tables (GLUT) for red, green and blue. Each GLUT entry
size is 7-bit.
• RAM write synchronization signal to avoid flickering when updating new image
• Sleep mode current <10uA with ram data kept
• Non-volatile memory (OTP) for panel calibration
• Row re-mapping and Column re-mapping
• Horizontal and Vertical scrolling
• Programmable Frame Rate and Multiplexing Ratio
• On-Chip Oscillator
• High Power Protection
• Color Swapping Function (RGB – BGR), arranged in RGB sequence when reset
• Slim chip layout for COF
• Operating temperature range -40°C to 85°C.

3 ORDERING INFORMATION
Table 3-1 : Ordering Information
Ordering Part Package
SEG COM Reference Remark
Number Form
Gold
• Min SEG pad pitch : 27um
SSD1355Z 128RGB 160 Bump Page 9
• Min COM pad pitch : 35um
Die
• 35mm film, 4 sprocket hole
• Hot bar type COF
Page 12,
SSD1355U2R1 128RGB 128 COF • 16/8-bit 80/68/SPI interface
105
• SEG lead pitch 0.051mm x 0.999 = 0.050949mm
• COM lead pitch 0.051mm x 0.999 = 0.050949mm
Page 15,
SSD1355U3R1 128RGB 96 COF • 8-bit 8080/6800 interface
107
Page 18,
SSD1355U6R1 128RGB 160 COF • 16/8-bit 80/68/SPI interface
109

4 BLOCK DIAGRAM
Figure 4-1 Block Diagram
VCI
BGGND
VDD VDD Regulator
RES#
CS#
Common Drivers
D/C# COM159
COM157
Gray Scale Decoder

R/W#(W/R#) COM155
MCU Interface
E(RD#)
(odd)
.
GDDRAM
.
.
D[17:0] COM5
COM3
COM1
BS[1:0]
SC127
SB127
SA127
SC126
VDDIO SB126
Segment Drivers
SA126
SC125
VLSS SB125
SA125
VCC .
.
VCI .
SC2
SB2
VSS SA2
SC1
VSL SB1
SA1
SC0
SEG/COM Driving Block
SB0
Command
SA0
Decoder
Temperature Sensor
Display Timing
GPIO 0
Common Drivers
Generator
GPIO 1 COM0
Oscillator
COM2
COM4
(even)
.
.
.
COM154
COM156
COM158
OTP
VPP
CL
TE
VCOMH
CLS
IREF

5 DIE FLOOR PLAN
Figure 5-1 : SSD1355Z Die drawing
Pin 1
Alignment marks
Position Size
+ shape ( -4988.93 , 42.65 ) 75um x 75um
+ shape ( 4988.93 , 14.46 ) 75um x 75um
Die Size 10.852mm x 1.65mm

Die Thickness 457um
Min I/O pd pitch 70um
Min SEG pad pitch 27um
Min COM pad pitch 35um
Bump Height nominal 15um
Bump Size
Pad # size [um2]
217-607 18um x 84um
1-62, 129-190, 192-215,
26um x 60um
609-632
63-128 45um x 90um
191, 633 50um x 60um
216, 608 50um x 84um

Table 5-1 : SSD1355Z Pin Assignment Table
Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos
1 VLSS -5078.9 -724.45 81 VDDIO -1440.59 -709.45 161 COM49 4063.9 -724.45 241 SA8 4620.45 744
2 VLSS -5043.9 -724.45 82 BS1 -1370.39 -709.45 162 COM48 4098.9 -724.45 242 SB8 4593.45 744
3 COM102 -5008.9 -724.45 83 VSS -1300.59 -709.45 163 COM47 4133.9 -724.45 243 SC8 4566.45 744
4 COM103 -4973.9 -724.45 84 TE -1209.17 -709.45 164 COM46 4168.9 -724.45 244 SA9 4539.45 744
5 COM104 -4938.9 -724.45 85 CL -1119.53 -709.45 165 COM45 4203.9 -724.45 245 SB9 4512.45 744
6 COM105 -4903.9 -724.45 86 VSS -1049.53 -709.45 166 COM44 4238.9 -724.45 246 SC9 4485.45 744
7 COM106 -4868.9 -724.45 87 CS# -979.53 -709.45 167 COM43 4273.9 -724.45 247 SA10 4458.45 744
8 COM107 -4833.9 -724.45 88 RES# -909.53 -709.45 168 COM42 4308.9 -724.45 248 SB10 4431.45 744
9 COM108 -4798.9 -724.45 89 D/C# -839.53 -709.45 169 COM41 4343.9 -724.45 249 SC10 4404.45 744
10 COM109 -4763.9 -724.45 90 R/W# (WR#) -699.62 -709.45 170 COM40 4378.9 -724.45 250 SA11 4377.45 744
11 COM110 -4728.9 -724.45 91 E (RD#) -629.44 -709.45 171 COM39 4413.9 -724.45 251 SB11 4350.45 744
12 COM111 -4693.9 -724.45 92 VDDIO -559.53 -709.45 172 COM38 4448.9 -724.45 252 SC11 4323.45 744
13 COM112 -4658.9 -724.45 93 VPP -446.09 -709.45 173 COM37 4483.9 -724.45 253 SA12 4296.45 744
14 COM113 -4623.9 -724.45 94 VPP -376.09 -709.45 174 COM36 4518.9 -724.45 254 SB12 4269.45 744
15 COM114 -4588.9 -724.45 95 VPP -283.43 -709.45 175 COM35 4553.9 -724.45 255 SC12 4242.45 744
16 COM115 -4553.9 -724.45 96 VDD -126.55 -709.45 176 COM34 4588.9 -724.45 256 SA13 4215.45 744
17 COM116 -4518.9 -724.45 97 VDD -56.55 -709.45 177 COM33 4623.9 -724.45 257 SB13 4188.45 744
18 COM117 -4483.9 -724.45 98 VDD 56.89 -709.45 178 COM32 4658.9 -724.45 258 SC13 4161.45 744
19 COM118 -4448.9 -724.45 99 VCI 170.33 -709.45 179 COM31 4693.9 -724.45 259 SA14 4134.45 744
20 COM119 -4413.9 -724.45 100 D0 261.75 -709.45 180 COM30 4728.9 -724.45 260 SB14 4107.45 744
21 COM120 -4378.9 -724.45 101 D1 347.15 -709.45 181 COM29 4763.9 -724.45 261 SC14 4080.45 744
22 COM121 -4343.9 -724.45 102 D2 456.99 -709.45 182 COM28 4798.9 -724.45 262 SA15 4053.45 744
23 COM122 -4308.9 -724.45 103 D3 542.39 -709.45 183 COM27 4833.9 -724.45 263 SB15 4026.45 744
24 COM123 -4273.9 -724.45 104 D4 652.23 -709.45 184 COM26 4868.9 -724.45 264 SC15 3999.45 744
25 COM124 -4238.9 -724.45 105 D5 737.63 -709.45 185 COM25 4903.9 -724.45 265 SA16 3972.45 744
26 COM125 -4203.9 -724.45 106 D6 847.47 -709.45 186 COM24 4938.9 -724.45 266 SB16 3945.45 744
27 COM126 -4168.9 -724.45 107 D7 932.87 -709.45 187 COM23 4973.9 -724.45 267 SC16 3918.45 744
28 COM127 -4133.9 -724.45 108 D8 1042.71 -709.45 188 COM22 5008.9 -724.45 268 SA17 3891.45 744
29 COM128 -4098.9 -724.45 109 D9 1128.11 -709.45 189 VLSS 5043.9 -724.45 269 SB17 3864.45 744
30 COM129 -4063.9 -724.45 110 D10 1237.95 -709.45 190 VLSS 5078.9 -724.45 270 SC17 3837.45 744
31 COM130 -4028.9 -724.45 111 D11 1323.35 -709.45 191 VLSS 5325.45 -742.15 271 SA18 3810.45 744
32 COM131 -3993.9 -724.45 112 D12 1433.19 -709.45 192 COM21 5325.45 -695.15 272 SB18 3783.45 744
33 COM132 -3958.9 -724.45 113 D13 1518.59 -709.45 193 COM20 5325.45 -660.15 273 SC18 3756.45 744
34 COM133 -3923.9 -724.45 114 D14 1628.43 -709.45 194 COM19 5325.45 -625.15 274 SA19 3729.45 744
35 COM134 -3888.9 -724.45 115 D15 1713.83 -709.45 195 COM18 5325.45 -590.15 275 SB19 3702.45 744
36 COM135 -3853.9 -724.45 116 D16 1823.67 -709.45 196 COM17 5325.45 -555.15 276 SC19 3675.45 744
37 COM136 -3818.9 -724.45 117 D17 1909.07 -709.45 197 COM16 5325.45 -520.15 277 SA20 3648.45 744
38 COM137 -3783.9 -724.45 118 VSS 2000.49 -709.45 198 COM15 5325.45 -485.15 278 SB20 3621.45 744
39 COM138 -3748.9 -724.45 119 BGGND 2070.49 -709.45 199 COM14 5325.45 -450.15 279 SC20 3594.45 744
40 COM139 -3713.9 -724.45 120 CLS 2140.49 -709.45 200 COM13 5325.45 -415.15 280 SA21 3567.45 744
41 COM140 -3678.9 -724.45 121 VCI 2210.49 -709.45 201 COM12 5325.45 -380.15 281 SB21 3540.45 744
42 COM141 -3643.9 -724.45 122 VDDIO 2367.37 -709.45 202 COM11 5325.45 -345.15 282 SC21 3513.45 744
43 COM142 -3608.9 -724.45 123 VDD 2437.37 -709.45 203 COM10 5325.45 -310.15 283 SA22 3486.45 744
44 COM143 -3573.9 -724.45 124 IREF 2550.81 -709.45 204 COM9 5325.45 -275.15 284 SB22 3459.45 744
45 COM144 -3538.9 -724.45 125 VCOMH 2620.81 -709.45 205 COM8 5325.45 -240.15 285 SC22 3432.45 744
46 COM145 -3503.9 -724.45 126 VCOMH 2690.81 -709.45 206 COM7 5325.45 -205.15 286 SA23 3405.45 744
47 COM146 -3468.9 -724.45 127 VCC 2792.29 -709.45 207 COM6 5325.45 -170.15 287 SB23 3378.45 744
48 COM147 -3433.9 -724.45 128 VCC 2862.29 -709.45 208 COM5 5325.45 -135.15 288 SC23 3351.45 744
49 COM148 -3398.9 -724.45 129 VLSS 2943.9 -724.45 209 COM4 5325.45 -100.15 289 SA24 3324.45 744
50 COM149 -3363.9 -724.45 130 VLSS 2978.9 -724.45 210 COM3 5325.45 -65.15 290 SB24 3297.45 744
51 COM150 -3328.9 -724.45 131 COM79 3013.9 -724.45 211 COM2 5325.45 -30.15 291 SC24 3270.45 744
52 COM151 -3293.9 -724.45 132 COM78 3048.9 -724.45 212 COM1 5325.45 4.85 292 SA25 3243.45 744
53 COM152 -3258.9 -724.45 133 COM77 3083.9 -724.45 213 COM0 5325.45 39.85 293 SB25 3216.45 744
54 COM153 -3223.9 -724.45 134 COM76 3118.9 -724.45 214 VLSS 5325.45 74.85 294 SC25 3189.45 744
55 COM154 -3188.9 -724.45 135 COM75 3153.9 -724.45 215 VLSS 5325.45 109.85 295 SA26 3162.45 744
56 COM155 -3153.9 -724.45 136 COM74 3188.9 -724.45 216 VCC 5337.26 744 296 SB26 3135.45 744
57 COM156 -3118.9 -724.45 137 COM73 3223.9 -724.45 217 SA0 5268.45 744 297 SC26 3108.45 744
58 COM157 -3083.9 -724.45 138 COM72 3258.9 -724.45 218 SB0 5241.45 744 298 SA27 3081.45 744
59 COM158 -3048.9 -724.45 139 COM71 3293.9 -724.45 219 SC0 5214.45 744 299 SB27 3054.45 744
60 COM159 -3013.9 -724.45 140 COM70 3328.9 -724.45 220 SA1 5187.45 744 300 SC27 3027.45 744
61 VLSS -2978.9 -724.45 141 COM69 3363.9 -724.45 221 SB1 5160.45 744 301 SA28 3000.45 744
62 VLSS -2943.9 -724.45 142 COM68 3398.9 -724.45 222 SC1 5133.45 744 302 SB28 2973.45 744
63 VCC -2876.99 -709.45 143 COM67 3433.9 -724.45 223 SA2 5106.45 744 303 SC28 2946.45 744
64 VCC -2806.99 -709.45 144 COM66 3468.9 -724.45 224 SB2 5079.45 744 304 SA29 2919.45 744
65 VCOMH -2705.51 -709.45 145 COM65 3503.9 -724.45 225 SC2 5052.45 744 305 SB29 2892.45 744
66 VCOMH -2635.51 -709.45 146 COM64 3538.9 -724.45 226 SA3 5025.45 744 306 SC29 2865.45 744
67 VSS -2565.51 -709.45 147 COM63 3573.9 -724.45 227 SB3 4998.45 744 307 SA30 2838.45 744
68 VSS -2495.51 -709.45 148 COM62 3608.9 -724.45 228 SC3 4971.45 744 308 SB30 2811.45 744
69 VSL -2425.51 -709.45 149 COM61 3643.9 -724.45 229 SA4 4944.45 744 309 SC30 2784.45 744
70 VSL -2355.51 -709.45 150 COM60 3678.9 -724.45 230 SB4 4917.45 744 310 SA31 2757.45 744
71 VCI -2285.51 -709.45 151 COM59 3713.9 -724.45 231 SC4 4890.45 744 311 SB31 2730.45 744
72 VCI -2215.51 -709.45 152 COM58 3748.9 -724.45 232 SA5 4863.45 744 312 SC31 2703.45 744
73 VDDIO -2102.07 -709.45 153 COM57 3783.9 -724.45 233 SB5 4836.45 744 313 SA32 2676.45 744
74 VDDIO -2032.07 -709.45 154 COM56 3818.9 -724.45 234 SC5 4809.45 744 314 SB32 2649.45 744
75 VDD -1918.63 -709.45 155 COM55 3853.9 -724.45 235 SA6 4782.45 744 315 SC32 2622.45 744
76 VLSS -1848.63 -709.45 156 COM54 3888.9 -724.45 236 SB6 4755.45 744 316 SA33 2595.45 744
77 GPIO0 -1757.21 -709.45 157 COM53 3923.9 -724.45 237 SC6 4728.45 744 317 SB33 2568.45 744
78 GPIO1 -1671.81 -709.45 158 COM52 3958.9 -724.45 238 SA7 4701.45 744 318 SC33 2541.45 744
79 VSS -1580.59 -709.45 159 COM51 3993.9 -724.45 239 SB7 4674.45 744 319 SA34 2514.45 744
80 BS0 -1510.39 -709.45 160 COM50 4028.9 -724.45 240 SC7 4647.45 744 320 SB34 2487.45 744

Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos
321 SC34 2460.45 744 401 SB61 300.45 744 481 SC85 -1859.55 744 561 SB112 -4019.55 744
322 SA35 2433.45 744 402 SC61 273.45 744 482 SA86 -1886.55 744 562 SC112 -4046.55 744
323 SB35 2406.45 744 403 SA62 246.45 744 483 SB86 -1913.55 744 563 SA113 -4073.55 744
324 SC35 2379.45 744 404 SB62 219.45 744 484 SC86 -1940.55 744 564 SB113 -4100.55 744
325 SA36 2352.45 744 405 SC62 192.45 744 485 SA87 -1967.55 744 565 SC113 -4127.55 744
326 SB36 2325.45 744 406 SA63 165.45 744 486 SB87 -1994.55 744 566 SA114 -4154.55 744
327 SC36 2298.45 744 407 SB63 138.45 744 487 SC87 -2021.55 744 567 SB114 -4181.55 744
328 SA37 2271.45 744 408 SC63 111.45 744 488 SA88 -2048.55 744 568 SC114 -4208.55 744
329 SB37 2244.45 744 409 SA64 84.45 744 489 SB88 -2075.55 744 569 SA115 -4235.55 744
330 SC37 2217.45 744 410 SB64 57.45 744 490 SC88 -2102.55 744 570 SB115 -4262.55 744
331 SA38 2190.45 744 411 SC64 30.45 744 491 SA89 -2129.55 744 571 SC115 -4289.55 744
332 SB38 2163.45 744 412 SA65 3.45 744 492 SB89 -2156.55 744 572 SA116 -4316.55 744
333 SC38 2136.45 744 413 SB65 -23.55 744 493 SC89 -2183.55 744 573 SB116 -4343.55 744
334 SA39 2109.45 744 414 SC65 -50.55 744 494 SA90 -2210.55 744 574 SC116 -4370.55 744
335 SB39 2082.45 744 415 SA66 -77.55 744 495 SB90 -2237.55 744 575 SA117 -4397.55 744
336 SC39 2055.45 744 416 SB66 -104.55 744 496 SC90 -2264.55 744 576 SB117 -4424.55 744
337 SA40 2028.45 744 417 SC66 -131.55 744 497 SA91 -2291.55 744 577 SC117 -4451.55 744
338 SB40 2001.45 744 418 SA67 -158.55 744 498 SB91 -2318.55 744 578 SA118 -4478.55 744
339 SC40 1974.45 744 419 SB67 -185.55 744 499 SC91 -2345.55 744 579 SB118 -4505.55 744
340 SA41 1947.45 744 420 SC67 -212.55 744 500 SA92 -2372.55 744 580 SC118 -4532.55 744
341 SB41 1920.45 744 421 SA68 -239.55 744 501 SB92 -2399.55 744 581 SA119 -4559.55 744
342 SC41 1893.45 744 422 SB68 -266.55 744 502 SC92 -2426.55 744 582 SB119 -4586.55 744
343 SA42 1866.45 744 423 SC68 -293.55 744 503 SA93 -2453.55 744 583 SC119 -4613.55 744
344 SB42 1839.45 744 424 SA69 -320.55 744 504 SB93 -2480.55 744 584 SA120 -4640.55 744
345 SC42 1812.45 744 425 SB69 -347.55 744 505 SC93 -2507.55 744 585 SB120 -4667.55 744
346 SA43 1785.45 744 426 SC69 -374.55 744 506 SA94 -2534.55 744 586 SC120 -4694.55 744
347 SB43 1758.45 744 427 SA70 -401.55 744 507 SB94 -2561.55 744 587 SA121 -4721.55 744
348 SC43 1731.45 744 428 SB70 -428.55 744 508 SC94 -2588.55 744 588 SB121 -4748.55 744
349 SA44 1704.45 744 429 SC70 -455.55 744 509 SA95 -2615.55 744 589 SC121 -4775.55 744
350 SB44 1677.45 744 430 SA71 -482.55 744 510 SB95 -2642.55 744 590 SA122 -4802.55 744
351 SC44 1650.45 744 431 SB71 -509.55 744 511 SC95 -2669.55 744 591 SB122 -4829.55 744
352 SA45 1623.45 744 432 SC71 -536.55 744 512 SA96 -2696.55 744 592 SC122 -4856.55 744
353 SB45 1596.45 744 433 SA72 -563.55 744 513 SB96 -2723.55 744 593 SA123 -4883.55 744
354 SC45 1569.45 744 434 SB72 -590.55 744 514 SC96 -2750.55 744 594 SB123 -4910.55 744
355 SA46 1542.45 744 435 SC72 -617.55 744 515 SA97 -2777.55 744 595 SC123 -4937.55 744
356 SB46 1515.45 744 436 SA73 -644.55 744 516 SB97 -2804.55 744 596 SA124 -4964.55 744
357 SC46 1488.45 744 437 SB73 -671.55 744 517 SC97 -2831.55 744 597 SB124 -4991.55 744
358 SA47 1461.45 744 438 SC73 -698.55 744 518 SA98 -2858.55 744 598 SC124 -5018.55 744
359 SB47 1434.45 744 439 VSS -725.55 744 519 SB98 -2885.55 744 599 SA125 -5045.55 744
360 SC47 1407.45 744 440 VSS -752.55 744 520 SC98 -2912.55 744 600 SB125 -5072.55 744
361 SA48 1380.45 744 441 VSS -779.55 744 521 SA99 -2939.55 744 601 SC125 -5099.55 744
362 SB48 1353.45 744 442 VSS -806.55 744 522 SB99 -2966.55 744 602 SA126 -5126.55 744
363 SC48 1326.45 744 443 VSS -833.55 744 523 SC99 -2993.55 744 603 SB126 -5153.55 744
364 SA49 1299.45 744 444 VSS -860.55 744 524 SA100 -3020.55 744 604 SC126 -5180.55 744
365 SB49 1272.45 744 445 VSS -887.55 744 525 SB100 -3047.55 744 605 SA127 -5207.55 744
366 SC49 1245.45 744 446 SA74 -914.55 744 526 SC100 -3074.55 744 606 SB127 -5234.55 744
367 SA50 1218.45 744 447 SB74 -941.55 744 527 SA101 -3101.55 744 607 SC127 -5261.55 744
368 SB50 1191.45 744 448 SC74 -968.55 744 528 SB101 -3128.55 744 608 VCC -5337.26 744
369 SC50 1164.45 744 449 SA75 -995.55 744 529 SC101 -3155.55 744 609 VLSS -5325.45 109.85
370 SA51 1137.45 744 450 SB75 -1022.55 744 530 SA102 -3182.55 744 610 VLSS -5325.45 74.85
371 SB51 1110.45 744 451 SC75 -1049.55 744 531 SB102 -3209.55 744 611 COM80 -5325.45 39.85
372 SC51 1083.45 744 452 SA76 -1076.55 744 532 SC102 -3236.55 744 612 COM81 -5325.45 4.85
373 SA52 1056.45 744 453 SB76 -1103.55 744 533 SA103 -3263.55 744 613 COM82 -5325.45 -30.15
374 SB52 1029.45 744 454 SC76 -1130.55 744 534 SB103 -3290.55 744 614 COM83 -5325.45 -65.15
375 SC52 1002.45 744 455 SA77 -1157.55 744 535 SC103 -3317.55 744 615 COM84 -5325.45 -100.15
376 SA53 975.45 744 456 SB77 -1184.55 744 536 SA104 -3344.55 744 616 COM85 -5325.45 -135.15
377 SB53 948.45 744 457 SC77 -1211.55 744 537 SB104 -3371.55 744 617 COM86 -5325.45 -170.15
378 SC53 921.45 744 458 SA78 -1238.55 744 538 SC104 -3398.55 744 618 COM87 -5325.45 -205.15
379 SA54 894.45 744 459 SB78 -1265.55 744 539 SA105 -3425.55 744 619 COM88 -5325.45 -240.15
380 SB54 867.45 744 460 SC78 -1292.55 744 540 SB105 -3452.55 744 620 COM89 -5325.45 -275.15
381 SC54 840.45 744 461 SA79 -1319.55 744 541 SC105 -3479.55 744 621 COM90 -5325.45 -310.15
382 SA55 813.45 744 462 SB79 -1346.55 744 542 SA106 -3506.55 744 622 COM91 -5325.45 -345.15
383 SB55 786.45 744 463 SC79 -1373.55 744 543 SB106 -3533.55 744 623 COM92 -5325.45 -380.15
384 SC55 759.45 744 464 SA80 -1400.55 744 544 SC106 -3560.55 744 624 COM93 -5325.45 -415.15
385 SA56 732.45 744 465 SB80 -1427.55 744 545 SA107 -3587.55 744 625 COM94 -5325.45 -450.15
386 SB56 705.45 744 466 SC80 -1454.55 744 546 SB107 -3614.55 744 626 COM95 -5325.45 -485.15
387 SC56 678.45 744 467 SA81 -1481.55 744 547 SC107 -3641.55 744 627 COM96 -5325.45 -520.15
388 SA57 651.45 744 468 SB81 -1508.55 744 548 SA108 -3668.55 744 628 COM97 -5325.45 -555.15
389 SB57 624.45 744 469 SC81 -1535.55 744 549 SB108 -3695.55 744 629 COM98 -5325.45 -590.15
390 SC57 597.45 744 470 SA82 -1562.55 744 550 SC108 -3722.55 744 630 COM99 -5325.45 -625.15
391 SA58 570.45 744 471 SB82 -1589.55 744 551 SA109 -3749.55 744 631 COM100 -5325.45 -660.15
392 SB58 543.45 744 472 SC82 -1616.55 744 552 SB109 -3776.55 744 632 COM101 -5325.45 -695.15
393 SC58 516.45 744 473 SA83 -1643.55 744 553 SC109 -3803.55 744 633 VLSS -5325.45 -742.15
394 SA59 489.45 744 474 SB83 -1670.55 744 554 SA110 -3830.55 744
395 SB59 462.45 744 475 SC83 -1697.55 744 555 SB110 -3857.55 744
396 SC59 435.45 744 476 SA84 -1724.55 744 556 SC110 -3884.55 744
397 SA60 408.45 744 477 SB84 -1751.55 744 557 SA111 -3911.55 744
398 SB60 381.45 744 478 SC84 -1778.55 744 558 SB111 -3938.55 744
399 SC60 354.45 744 479 SA85 -1805.55 744 559 SC111 -3965.55 744
400 SA61 327.45 744 480 SB85 -1832.55 744 560 SA112 -3992.55 744

6 PIN ARRANGEMENT
6.1 SSD1355U2R1 Pin Assignment
Figure 6-1: SSD1355U2R1 Pin Assignment

Table 6-1 : SSD1355U2R1 Pin Assignment Table

6.2 SSD1355U3R1 Pin Assignment

Table 6-2: SSD1355U3R1 Pin Assignment Table

6 08 6.3
6 07
6 06
6 05 58
6 04 56
Solomon Systech
527
526
525
524
SSD1355U6R1 Pin Assignment
5 19
5 18
5 17
5 16
5 15
5 14
13 7 26
13 6 27
13 5 27
13 4 27
13 3
Oct 2007
13 2
P 18/111
12 7
12 6
12 5
12 4
Rev 1.2
47 57
46 59
45
44
43
SSD1355
Table 6-3: SSD1355U6R1 Pin Assignment Table
Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name
1 NC 81 COM89 161 SC118 241 SA92
2 VLSS 82 COM87 162 SB118 242 SC91
3 NC 83 COM85 163 SA118 243 SB91
4 VCC 84 COM83 164 SC117 244 SA91
5 VCOMH 85 COM81 165 SB117 245 SC90
6 IREF 86 COM79 166 SA117 246 SB90
7 VSS 87 COM77 167 SC116 247 SA90
8 D15 88 COM75 168 SB116 248 SC89
9 D14 89 COM73 169 SA116 249 SB89
10 D13 90 COM71 170 SC115 250 SA89
11 D12 91 COM69 171 SB115 251 SC88
12 D11 92 COM67 172 SA115 252 SB88
13 D10 93 COM65 173 SC114 253 SA88
14 D9 94 COM63 174 SB114 254 SC87
15 D8 95 COM61 175 SA114 255 SB87
16 D7 96 COM59 176 SC113 256 SA87
17 D6 97 COM57 177 SB113 257 SC86
18 D5 98 COM55 178 SA113 258 SB86
19 D4 99 COM53 179 SC112 259 SA86
20 D3 100 COM51 180 SB112 260 SC85
21 D2 101 COM49 181 SA112 261 SB85
22 D1 102 COM47 182 SC111 262 SA85
23 D0 103 COM45 183 SB111 263 SC84
24 VDD 104 COM43 184 SA111 264 SB84
25 VPP 105 COM41 185 SC110 265 SA84
26 E/RD# 106 COM39 186 SB110 266 SC83
27 R/W# 107 COM37 187 SA110 267 SB83
28 D/C# 108 COM35 188 SC109 268 SA83
29 RES# 109 COM33 189 SB109 269 SC82
30 CS# 110 COM31 190 SA109 270 SB82
31 TE 111 COM29 191 SC108 271 SA82
32 BS1 112 COM27 192 SB108 272 SC81
33 BS0 113 COM25 193 SA108 273 SB81
34 VDDIO 114 COM23 194 SC107 274 SA81
35 VCI 115 COM21 195 SB107 275 SC80
36 VSL 116 COM19 196 SA107 276 SB80
37 VSS 117 COM17 197 SC106 277 SA80
38 NC 118 COM15 198 SB106 278 SC79
39 VCC 119 COM13 199 SA106 279 SB79
40 NC 120 COM11 200 SC105 280 SA79
41 VLSS 121 COM9 201 SB105 281 SC78
42 NC 122 COM7 202 SA105 282 SB78
43 NC 123 COM5 203 SC104 283 SA78
44 NC 124 COM3 204 SB104 284 SC77
45 NC 125 COM1 205 SA104 285 SB77
46 COM159 126 NC 206 SC103 286 SA77
47 COM157 127 NC 207 SB103 287 SC76
48 COM155 128 NC 208 SA103 288 SB76
49 COM153 129 NC 209 SC102 289 SA76
50 COM151 130 NC 210 SB102 290 SC75
51 COM149 131 NC 211 SA102 291 SB75
52 COM147 132 NC 212 SC101 292 SA75
53 COM145 133 NC 213 SB101 293 SC74
54 COM143 134 SC127 214 SA101 294 SB74
55 COM141 135 SB127 215 SC100 295 SA74
56 COM139 136 SA127 216 SB100 296 SC73
57 COM137 137 SC126 217 SA100 297 SB73
58 COM135 138 SB126 218 SC99 298 SA73
59 COM133 139 SA126 219 SB99 299 SC72
60 COM131 140 SC125 220 SA99 300 SB72
61 COM129 141 SB125 221 SC98 301 SA72
62 COM127 142 SA125 222 SB98 302 SC71
63 COM125 143 SC124 223 SA98 303 SB71
64 COM123 144 SB124 224 SC97 304 SA71
65 COM121 145 SA124 225 SB97 305 SC70
66 COM119 146 SC123 226 SA97 306 SB70
67 COM117 147 SB123 227 SC96 307 SA70
68 COM115 148 SA123 228 SB96 308 SC69
69 COM113 149 SC122 229 SA96 309 SB69
70 COM111 150 SB122 230 SC95 310 SA69
71 COM109 151 SA122 231 SB95 311 SC68
72 COM107 152 SC121 232 SA95 312 SB68
73 COM105 153 SB121 233 SC94 313 SA68
74 COM103 154 SA121 234 SB94 314 SC67
75 COM101 155 SC120 235 SA94 315 SB67
76 COM99 156 SB120 236 SC93 316 SA67
77 COM97 157 SA120 237 SB93 317 SC66
78 COM95 158 SC119 238 SA93 318 SB66
79 COM93 159 SB119 239 SC92 319 SA66
80 COM91 160 SA119 240 SB92 320 SC65

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name
321 SB65 401 SC38 481 SA12 561 COM70
322 SA65 402 SB38 482 SC11 562 COM72
323 SC64 403 SA38 483 SB11 563 COM74
324 SB64 404 SC37 484 SA11 564 COM76
325 SA64 405 SB37 485 SC10 565 COM78
326 SC63 406 SA37 486 SB10 566 COM80
327 SB63 407 SC36 487 SA10 567 COM82
328 SA63 408 SB36 488 SC9 568 COM84
329 SC62 409 SA36 489 SB9 569 COM86
330 SB62 410 SC35 490 SA9 570 COM88
331 SA62 411 SB35 491 SC8 571 COM90
332 SC61 412 SA35 492 SB8 572 COM92
333 SB61 413 SC34 493 SA8 573 COM94
334 SA61 414 SB34 494 SC7 574 COM96
335 SC60 415 SA34 495 SB7 575 COM98
336 SB60 416 SC33 496 SA7 576 COM100
337 SA60 417 SB33 497 SC6 577 COM102
338 SC59 418 SA33 498 SB6 578 COM104
339 SB59 419 SC32 499 SA6 579 COM106
340 SA59 420 SB32 500 SC5 580 COM108
341 SC58 421 SA32 501 SB5 581 COM110
342 SB58 422 SC31 502 SA5 582 COM112
343 SA58 423 SB31 503 SC4 583 COM114
344 SC57 424 SA31 504 SB4 584 COM116
345 SB57 425 SC30 505 SA4 585 COM118
346 SA57 426 SB30 506 SC3 586 COM120
347 SC56 427 SA30 507 SB3 587 COM122
348 SB56 428 SC29 508 SA3 588 COM124
349 SA56 429 SB29 509 SC2 589 COM126
350 SC55 430 SA29 510 SB2 590 COM128
351 SB55 431 SC28 511 SA2 591 COM130
352 SA55 432 SB28 512 SC1 592 COM132
353 SC54 433 SA28 513 SB1 593 COM134
354 SB54 434 SC27 514 SA1 594 COM136
355 SA54 435 SB27 515 SC0 595 COM138
356 SC53 436 SA27 516 SB0 596 COM140
357 SB53 437 SC26 517 SA0 597 COM142
358 SA53 438 SB26 518 NC 598 COM144
359 SC52 439 SA26 519 NC 599 COM146
360 SB52 440 SC25 520 NC 600 COM148
361 SA52 441 SB25 521 NC 601 COM150
362 SC51 442 SA25 522 NC 602 COM152
363 SB51 443 SC24 523 NC 603 COM154
364 SA51 444 SB24 524 NC 604 COM156
365 SC50 445 SA24 525 NC 605 COM158
366 SB50 446 SC23 526 COM0 606 NC
367 SA50 447 SB23 527 COM2 607 NC
368 SC49 448 SA23 528 COM4 608 NC
369 SB49 449 SC22 529 COM6
370 SA49 450 SB22 530 COM8
371 SC48 451 SA22 531 COM10
372 SB48 452 SC21 532 COM12
373 SA48 453 SB21 533 COM14
374 SC47 454 SA21 534 COM16
375 SB47 455 SC20 535 COM18
376 SA47 456 SB20 536 COM20
377 SC46 457 SA20 537 COM22
378 SB46 458 SC19 538 COM24
379 SA46 459 SB19 539 COM26
380 SC45 460 SA19 540 COM28
381 SB45 461 SC18 541 COM30
382 SA45 462 SB18 542 COM32
383 SC44 463 SA18 543 COM34
384 SB44 464 SC17 544 COM36
385 SA44 465 SB17 545 COM38
386 SC43 466 SA17 546 COM40
387 SB43 467 SC16 547 COM42
388 SA43 468 SB16 548 COM44
389 SC42 469 SA16 549 COM46
390 SB42 470 SC15 550 COM48
391 SA42 471 SB15 551 COM50
392 SC41 472 SA15 552 COM52
393 SB41 473 SC14 553 COM54
394 SA41 474 SB14 554 COM56
395 SC40 475 SA14 555 COM58
396 SB40 476 SC13 556 COM60
397 SA40 477 SB13 557 COM62
398 SC39 478 SA13 558 COM64
399 SB39 479 SC12 559 COM66
400 SA39 480 SB12 560 COM68

7 PIN DESCRIPTIONS
Key:
I = Input NC = Not Connected
O =Output Pull LOW= connect to Ground
I/O = Bi-directional (input/output) Pull HIGH= connect to VDDIO
P = Power pin
Table 7-1 : SSD1355 Pin Description

Pin Name Pin Type Description
VDD P Power supply pin for core logic operation.
VDD can be supplied externally (within the range of 2.4V to 2.6V) or regulated
internally from VCI. A capacitor should be connected between VDD and VSS under all
circumstances.
Refer to Section 8.11 for details.

VDDIO P Power supply for interface logic level. It should match with the MCU interface
voltage level and must be connected to external source.
VCI P Low voltage power supply

VCI must always be equal to or higher than VDD and VDDIO.

VCC P Power supply for panel driving voltage. This is also the most positive power voltage
supply pin. It is supplied by external high voltage source.
VPP P Power supply for programming OTP.
In OTP programming, this pin is powered up to 7.5V. Refer to Section 9.3.32 OTP
Write (B1h) for details.
In operation mode (without programming OTP), this pin must be connected to VDD.
VSS P Ground pin
VLSS P Analog system ground pin
VCOMH P COM signal deselected voltage level.

A capacitor should be connected between this pin and VSS.
BGGND P It should be connected to Ground.
GPIO0 I/O Refer to section 9.3.47 GPIO (D7h).
GPIO1 I/O Refer to section 9.3.47 GPIO (D7h).
VSL P This is segment voltage reference pin.

When external VSL is not used, this pin should be left open.
When external VSL is used, connect with resistor and diode to ground. (details
depend on application)

BS[1:0] I MCU bus interface selection pins. Select appropriate logic setting as described in the
following table. BS3 and BS2 are command programmable (by command 36h).
[reset = 00]. BS1 and BS0 are pin select.
Table 7-2 : Bus Interface selection
BS[3:0] Interface
0000 4 line SPI
0001 3 line SPI
0011 8-bit 6800 parallel
Note
(1)
0 is connected to VSS
(2)
1 is connected to VDDIO
IREF I This pin is the segment output current reference pin.
IREF can be supplied externally or regulated internally.
When external IREF is selected, a resistor should be connected between this pin and
VSS. When internal IREF is selected, this pin should be floated.
CL I External clock input pin.
When internal clock is enable (i.e. pull HIGH in CLS pin), this pin is not used and
should be connected to Ground.
When internal clock is disable (i.e. pull LOW is CLS pin), this pin is the external
clock source input pin.
CLS I Internal clock selection pin.
When this pin is pulled HIGH, internal oscillator is enabled (normal operation).
When this pin is pulled LOW, an external clock signal should be connected to CL.
CS# I This pin is the chip select input connecting to the MCU.
The chip is enabled for MCU communication only when CS# is pulled LOW.
RES# I This pin is reset signal input.
When the pin is pulled LOW, initialization of the chip is executed.

Keep this pin pull HIGH during normal operation.
D/C# I This pin is Data/Command control pin connecting to the MCU.
When the pin is pulled HIGH, the data at D[17:0] will be interpreted as data.
When the pin is pulled LOW, the data at D[17:0] will be interpreted as command.
R/W# (WR#) I This pin is read / write control input pin connecting to the MCU interface.
When 6800 interface mode is selected, this pin will be used as Read/Write (R/W#)
selection input. Read mode will be carried out when this pin is pulled HIGH and
write mode when LOW.
When 8080 interface mode is selected, this pin will be the Write (WR#) input. Data
write operation is initiated when this pin is pulled LOW and the chip is selected.

When serial interface is selected, this pin R/W (WR#) will be SCLK.
E (RD#) I This pin is MCU interface input.
When 6800 interface mode is selected, this pin will be used as the Enable (E) signal.
Read/write operation is initiated when this pin is pulled HIGH and the chip is
selected.
When 8080 interface mode is selected, this pin receives the Read (RD#) signal. Read
operation is initiated when this pin is pulled LOW and the chip is selected.
When serial interface is selected, this pin E(RD#) must be connected to VSS.
D[17:0] I/O These pins are bi-directional data bus connecting to the MCU data bus.
Unused pins are recommended to tie LOW. (Except for D1 pin in SPI mode)
TE O Tearing Effect.
To synchronize the MPU to the frame display writing.
Do not connect if not used.
SA[127:0] O These pins provide the OLED segment driving signals. These pins are VSS state when
SB[127:0] display is OFF.
SC[127:0]
The 384 segment pins are divided into 3 groups, SA, SB and SC. Each group can
have different color settings for color A, B and C.
COM[159:0] I/O These pins provide the Common switch signals to the OLED panel.

8 FUNCTIONAL BLOCK DESCRIPTIONS
8.1 MCU Interface
SSD1355 MCU interface consist of 18 data pin and 5 control pins. The pin assignment at different interface
mode is summarized in Table 8-1. Different MCU mode can be set by hardware selection on BS[1:0] pins
and software command on BS[3:0].(refer to Table 7-2 for BS[3:0] setting)
Table 8-1 : MCU interface assignment under different bus interface mode
Pin Name Data / Command Interface Control Signal
Bus Interface D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 E R/W# CS# D/C# RES#
8b / 8080 Tie Low D[7:0] RD# WR# CS# D/C# RES#
8b / 6800 Tie Low D[7:0] E R/W# CS# D/C# RES#
16b / 8080 Tie Low D[15:0] RD# WR# CS# D/C# RES#
16b / 6800 Tie Low D[15:0] E R/W# CS# D/C# RES#
18b / 8080 D[17:0] RD# WR# CS# D/C# RES#
18b / 6800 D[17:0] E R/W# CS# D/C# RES#
3-wrie SPI Tie Low NC SDIN Tie Low SCLK CS# Tie Low RES#
4-wire SPI Tie Low NC SDIN Tie Low SCLK CS# D/C# RES#
Table 8-2 : Data bus selection modes

6800 – series Parallel 8080 – series Parallel 3-wire Serial Interface or
Interface Interface 4-wire Serial Interface
Data Read 18-/16-/8-bits 18-/16-/8-bits No
Data Write 18-/16-/8-bits 18-/16-/8-bits 8-bits
Command Read Yes. Refer to section 9 Yes. Refer to section 9 No
Command Write Yes Yes Yes
8.1.1 MCU Parallel 6800-series Interface

The parallel interface consists of 18 bi-directional data pins (D[17:0]), R/W#, D/C#, E and CS#.
A LOW in R/W# indicates WRITE operation and HIGH in R/W# indicates READ operation.
A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write.
The E input serves as data latch signal while CS# is LOW. Data is latched at the falling edge of E signal.
Table 8-3 : Control pins of 6800 interface
Function E R/W# CS# D/C#

Write command ↓ L L L
Read status ↓ H L L
Write data ↓ L L H
Read data ↓ H L H
Note
(1)
↓ stands for falling edge of signal
(2)
H stands for HIGH in signal
(3)
L stands for LOW in signal
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual display
data read. This is shown in Figure 8-1.

Figure 8-1 : Data read back procedure - insertion of dummy read
R/W#
Databus N n n+1 n+2
Write column
Dummy read Read 1st data Read 2nd data Read 3rd data
address
8.1.2 MCU Parallel 8080-series Interface

The parallel interface consists of 18 bi-directional data pins (D[17:0]), RD#, WR#, D/C# and CS#.
A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write.
A rising edge of RD# input serves as a data READ latch signal while CS# is kept LOW.
A rising edge of WR# input serves as a data/command WRITE latch signal while CS# is kept LOW.
Figure 8-2 : Example of Write procedure in 8080 parallel interface mode
CS#
WR#
D[7:0]
D/C#
high
RD#
low
Figure 8-3 : Example of Read procedure in 8080 parallel interface mode
CS#
RD#
D[7:0]
D/C#
high
WR#
low

Table 8-4 : Control pins of 8080 interface
Function RD# WR# CS# D/C#

Write command H ↑ L L
Read status ↑ H L L
Write data H ↑ L H
Read data ↑ H L H
Note
(1)
↑ stands for rising edge of signal
(2)
(3)
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual display
data read. This is shown in Figure 8-4.
Figure 8-4 : Display data read back procedure - insertion of dummy read
WR#
RD#
Databus N n n+1 n+2
Write column
Dummy read Read 1st data Read 2nd data Read 3rd data
address
8.1.3 MCU Serial Interface (4-wire SPI)

The 4-wire serial interface consists of serial clock: SCLK, serial data: SDIN, D/C#, CS#. In 4-wire SPI mode,
R/W# (WR#) acts as SCLK, D0 acts as SDIN. For the unused data pins, D1 should be left open. The pins
from D2 to D17and E can be connected to an external ground.
Table 8-5 : Control pins of 4-wire Serial interface
Function E CS# D/C#

Write command Tie LOW L L
Write data Tie LOW L H
Note
(1)
(2)
SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, ... D0. D/C#
is sampled on every eighth clock and the data byte in the shift register is written to the Graphic Display Data
RAM (GDDRAM) or command register in the same clock.
Under serial mode, only write operations are allowed.

Figure 8-5 : Write procedure in 4-wire Serial interface mode
CS#
D/C#
SDIN/
DB1 DB2 DBn
SCLK
SCLK
(R/W# (WR#))
SDIN(D0) D7 D6 D5 D4 D3 D2 D1 D0
8.1.4 MCU Serial Interface (3-wire SPI)

The 3-wire serial interface consists of serial clock SCLK, serial data SDIN and CS#.
In 3-wire SPI mode, R/W# (WR#) acts as SCLK, D0 acts as SDIN. For the unused data pins, D1 should be
left open. The pins from D2 to D17, E and D/C# can be connected to an external ground.
The operation is similar to 4-wire serial interface while D/C# pin is not used. There are altogether 9-bits will
be shifted into the shift register on every ninth clock in sequence: D/C# bit, D7 to D0 bit. The D/C# bit (first
bit of the sequential data) will determine the following data byte in the shift register is written to the Display
Data RAM (D/C# bit = 1) or the command register (D/C# bit = 0). Under serial mode, only write operations
are allowed.
Table 8-6 : Control pins of 3-wire Serial interface
Function E R/W# CS# D/C#

Write command Tie LOW SCLK L Tie LOW Note
(1)
Write data Tie LOW SCLK L Tie LOW L stands for LOW in signal
Figure 8-6 : Write procedure in 3-wire Serial interface mode
CS#
SDIN/
DB1 DB2 DBn
SCLK
SCLK
(R/W# (WR#))
SDIN(D0) D/C# D7 D6 D5 D4 D3 D2 D1 D0

8.2 Reset Circuit
When RES# input is pulled LOW, the chip is initialized with the following status:
1. Display is OFF
2. 160 MUX Display Mode
3. Normal segment and display data column address and row address mapping (SEG0 mapped to
address 00h and COM0 mapped to address 00h)
4. Display start line is set at display RAM address 0
5. Column address counter is set at 0
6. Normal scan direction of the COM outputs
7. Individual contrast control registers of color A, B, and C are set at 80h
8.3 GDDRAM
8.3.1 GDDRAM structure
The GDDRAM is a bit mapped static RAM holding the pattern to be displayed. The RAM size is 128 x 160 x
18bits. For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by
software. Each pixel has 18-bit data. Each sub-pixels for color A, B and C have 6 bits. The arrangement of
data pixel in graphic display data RAM is shown in Table 8-7
Table 8-7 : 262k Color Depth Graphic Display Data RAM Structure
Segment Normal 0 1 2 …… …… 126 127
Address Remapped 127 126 125 …… …… 1 0
Color A B C A B C A C A B C
Data A5 B5 C5 A5 B5 C5 A5 …… …… C5 A5 B5 C5
Format A4 B4 C4 A4 B4 C4 A4 …… …… C4 A4 B4 C4
A3 B3 C3 A3 B3 C3 A3 …… …… C3 A3 B3 C3
Common A2 B2 C2 A2 B2 C2 A2 …… …… C2 A2 B2 C2
Address A1 B1 C1 A1 B1 C1 A1 …… …… C1 A1 B1 C1
A0 B0 C0 A0 B0 C0 A0 …… …… C0 A0 B0 C0 Common
Normal Remapped output
0 159 6 6 6 6 6 6 6 …… …… 6 6 6 6 COM0
1 158 6 6 6 6 6 6 6 …… …… 6 6 6 6 COM1
2 157 6 6 6 6 6 6 6 …… …… 6 6 6 6 COM2
3 156 6 6 6 6 6 6 6 …… …… 6 6 6 6 COM3
4 155 6 6 6 6 6 6 6 …… …… 6 6 6 6 COM4
5 154 6 6 6 6 6 6 6 …… …… 6 6 6 6 COM5
6 153 6 6 no of bits in this cell 6 6 …… …… 6 6 6 6 COM6
7 152 …… …… 6 6 6 6 COM7
: : : : : : : : : …… …… : : : : :
: : : : : : : : : …… …… : : : : :
: : : : : : : : : …… …… : : : : :
155 4 6 6 6 6 6 6 6 …… …… 6 6 6 6 :
156 3 6 6 6 6 6 6 6 …… …… 6 6 6 6 COM156
157 2 6 6 6 6 6 6 6 …… …… 6 6 6 6 COM157
158 1 6 6 6 6 6 6 6 …… …… 6 6 6 6 COM158
159 0 6 6 6 6 6 6 6 …… …… 6 6 6 6 COM159
SEG output SA0 SB0 SC0 SA1 SB1 SC1 SA2 …… …… SC126 SA127 SB127 SC127

8.3.2 Data bus to RAM mapping under different input mode
Table 8-8 : Write Data bus usage under different bus width and color depth mode
Write Data Data bus D[17:0]
Bus width Color Depth Input order D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1st X X X X X X X X X X C4 C3 C2 C1 C0 B5 B4 B3
8 bits / SPI 65k
2nd X X X X X X X X X X B2 B1 B0 A4 A3 A2 A1 A0
1st X X X X X X X X X X C15 C14 C13 C12 C11 C10 X X
8 bits / SPI 262k 2nd X X X X X X X X X X B15 B14 B13 B12 B11 B10 X X
3rd X X X X X X X X X X A15 A14 A13 A12 A11 A10 X X
16 bits 65k X X C4 C3 C2 C1 C0 B5 B4 B3 B2 B1 B0 A4 A3 A2 A1 A0
1st X X C15 C14 C13 C12 C11 C10 X X B15 B14 B13 B12 B11 B10 X X
16 bits 262k 2nd X X A15 A14 A13 A12 A11 A10 X X C25 C24 C23 C22 C21 C20 X X
3rd X X B25 B24 B23 B22 B21 B20 X X A25 A24 A23 A22 A21 A20 X X
18 bits 262k C5 C4 C3 C2 C1 C0 B5 B4 B3 B2 B1 B0 A5 A4 A3 A2 A1 A0
Table 8-9 : Read Data bus usage under different bus width and color depth mode
Read Data Data bus D[17:0]

Bus width Output order D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1st X X X X X X X X X X C15 C14 C13 C12 C11 C10 X X
8 bits 2nd X X X X X X X X X X B15 B14 B13 B12 B11 B10 X X
3rd X X X X X X X X X X A15 A14 A13 A12 A11 A10 X X
1st X X C15 C14 C13 C12 C11 C10 X X B15 B14 B13 B12 B11 B10 X X
16 bits 2nd X X A15 A14 A13 A12 A11 A10 X X C25 C24 C23 C22 C21 C20 X X
3rd X X B25 B24 B23 B22 B21 B20 X X A25 A24 A23 A22 A21 A20 X X
18 bits C5 C4 C3 C2 C1 C0 B5 B4 B3 B2 B1 B0 A5 A4 A3 A2 A1 A0
Note
(1)
The Read Data bus usage is independent of color depth.

8.4 Command Decoder
This module determines whether the input should be interpreted as data or command based upon the input of
the D/C# pin.
If D/C# pin is HIGH, data is written to Graphic Display Data RAM (GDDRAM). If it is LOW, the inputs at
D0-D17 are interpreted as a Command and it will be decoded and be written to the corresponding command
register.
8.5 Oscillator & Timing Generator
8.5.1 Oscillator
Figure 8-7 : Oscillator Circuit
Internal
Oscillator
Fosc
M CLK DCLK
Divider
U
CL X Display
Clock
CLS
This module is an On-Chip low power RC oscillator circuitry (Figure 8-7). The operation clock (CLK) can be
generated either from internal oscillator or external source CL pin by CLS pin. If CLS pin is HIGH, internal
oscillator is selected. If CLS pin is LOW, external clock from CL pin will be used for CLK. The frequency of
internal oscillator FOSC can be programmed by command D2h.
The display clock (DCLK) for the Display Timing Generator is derived from CLK. The division factor “D”
can be programmed from 1 to 16 by command D2h.
DCLK = FOSC / D
The frame frequency of display is determined by the following formula:

Fosc
FFRM =
D × K × No. of Mux
where
• D stands for clock divide ratio. It is set by command D2h A[3:0]. The divide ratio has the range from 1 to
1024 .
• K is the number of display clocks per row. The value is derived by
K = Phase 1 period +Phase 2 period + 75
= 9 +7 +75 =91 (reset)
• Number of multiplex ratio is set by command CAh. The reset value is 159 (i.e. 160MUX).
• Fosc is the oscillator frequency. It can be changed by command D2h A[7:4]. The higher the register setting
results in higher frequency.
If the frame frequency is set too low, flickering may occur. On the other hand, higher frame frequency leads
to higher power consumption on the whole system.

8.6 SEG/COM Driving block
This block is used to derive the incoming power sources into the different levels of internal use voltage and
current.
• VCC is the most positive voltage supply.
• VCOMH is the Common deselected level. It is internally regulated.
• VLSS is the ground path of the analog and panel current.
• IREF is a reference current for segment current drivers ISEG. The relationship between reference
current and segment current of a color is:
ISEG = Contrast / 256 * IREF * scale factor
in which
the contrast is set by Set Contrast command (BAh, BBh, BCh); and
the scale factor (1 ~ 16) is set by Master Current Control command (51h).
IREF can be supplied externally or internally. Selection is set by Function Selection command (B3h).
When the command B3h, bit A[6] is set to 1b, the internal IREF regulator is enabled. The typical
regulated IREF is about 13.5uA. When the command B3h, bit A[0] is set to 0b, external IREF is selected.
A resistor should be connected between IREF pin and Vss pin.
For example, in case external IREF is selected and target IREF is about 13.5uA, the appropriate IREF
resistor between IREF pin to VSS pin should has a value as shown in Figure 8-8.
Figure 8-8 : IREF Current Setting by Resistor Value
SSD1355
IREF (voltage at this

IREF ≈ 13.5uA
pin = VCC – 6V)
R1
VSS
Since the voltage at IREF pin is VCC – 6V, the value of resistor R1 can be found as below:
For IREF = 13.5uA, VCC =18V:
R1 = (Voltage at IREF – VSS) / IREF

≈ (18 – 6) / 13.5uA
≈ 880KΩ

8.7 SEG / COM Driver
Segment drivers consist of 384 (128 x 3 colors) current sources to drive OLED panel. The driving current can
be adjusted from 0 to 200uA with 256 steps by contrast setting command (BAh, BBh, BCh). Common drivers
generate scanning voltage pulse. The block diagrams and waveforms of the segment and common driver are
shown as follow.
Figure 8-9 : Segment and Common Driver Block Diagram
VCC
ISEG
VCOMH Current
Drive
Non-select
Row
Reset
OLED
Selected Pixel
Row
VLSS
VLSS
Segment Driver
Common Driver
The commons are scanned sequentially, row by row. If a row is not selected, all the pixels on the row are in
reverse bias by driving those commons to voltage VCOMH as shown in Figure 8-10.
In the scanned row, the pixels on the row will be turned ON or OFF by sending the corresponding data signal
to the segment pins. If the pixel is turned OFF, the segment current is disabled and the Reset switch is
enabled. On the other hand, the segment drives to ISEG when the pixel is turned ON.

Figure 8-10 : Segment and Common Driver Signal Waveform
One Frame Period

De -select Row
COM 0
V COMH
V LSS
Selected Row
C OM 1
V COMH
V LSS
COM This row is selected to

Voltage turn on
V COMH
V LSS
Time
Segment
Voltage
Waveform for ON
VP
Waveform for OFF

V LSS
Time
There are four phases to driving an OLED a pixel. In phase 1, the pixel is reset by the segment driver to VLSS
in order to discharge the previous data charge stored in the parasitic capacitance along the segment electrode.
The period of phase 1 can be programmed by command CDh A[3:0]. An OLED panel with larger capacitance
requires a longer period for discharging.

In phase 2, first pre-charge is performed. The pixel is driven to attain the corresponding voltage level VP from
VLSS. The amplitude of VP can be programmed by the command BDh. The period of phase 2 can be
programmed by command CDh A[7:4]. If the capacitance value of the pixel of OLED panel is larger, a longer
period is required to charge up the capacitor to reach the desired voltage.
In phase 3, the OLED pixel is driven to the targeted driving voltage through second pre-charge. The second
pre-charge can control the speed of the charging process. The period of phase 3 can be programmed by
command CEh.
Last phase (phase 4) is current drive stage. The current source in the segment driver delivers constant current
to the pixel. The driver IC employs PAM+PWM (Pulse Area Modulation + Pulse Width Modulation) method
to control the gray scale of each pixel individually. The gray scale can be programmed into different Gamma
settings by command B9h/BEh. The bigger gamma setting in the current drive stage results in brighter pixels
and vice versa (Details refer to Section 8.8). This is shown in the following figure.
Figure 8-11: Gray Scale Control in Segment
CFh
Phase2 A[1:0]
Phase1 Phase3 Phase4
Segment
Voltage
BDh B9h or BEh

A[4:0]
VP
VLSS
Time
CDh
A[3:0]
CDh Larger Gamma
A[7:4] Setting drives pixel
CEh
A[3:0] brighter
OLED
Panel
After finishing phase 4, the driver IC will go back to phase 1 to display the next row image data. This four-
step cycle runs continuously to refresh image display on OLED panel.

8.8 Gray Scale Decoder
The gray scale effect is generated by controlling the segment current in current drive phase. The segment
current is controlled by the Gamma Settings (Setting 0~ Setting 127). The larger the setting, the brighter the
pixel will be. The Gray Scale Table stores the corresponding Gamma Setting of the 64 gray scale levels
(GS0~GS63) through the software commands BEh or B9h. Three programmable Gray Scale Tables (Gamma
Look Up table) support the three colors A, B and C.
As shown in Figure 8-12, color A, B, C sub-pixel RAM data has 6 bits, represent the 64 gray scale level from
GS0 to GS63.
Figure 8-12 : Relation between GDDRAM content and Gray Scale table entry for three colors in 262K color mode (under
command B9h Linear Gamma Look Up Table)
Color A, B or C Gray Scale Table Default Gamma Setting
GDDRAM data (6 bits) (Command B9h Linear Gamma Look Up Table)
000000 GS0 Setting 0
: : :
: : :
111100 GS60 Setting 121
111101 GS61 Setting 123
111110 GS62 Setting 125
111111 GS63 Setting 127
The Gray Scale Table can be programmed into different Gamma setting by command BEh. For example, if
GS1 is programmed into Gamma setting 4, and the color A, B or C of GDDRAM is set as “000001b”, then
the current drive phase will be similar to the illustration in Figure 8-13(a).
Figure 8-13 : Illustration of current drive phase (phase 4) under different Gamma Settings.
Segment Segment Segment Segment

current current current current
Setting 127
Setting 112
Setting 96
Setting 80
Setting 64
Setting 48
Setting 32
Setting 16
Time Time Time Time
Setting 4 Setting 42 Setting127 Different settings

(Phase 4, Current drive phase) (Phase 4, Current drive phase) (Phase 4, Current drive phase) (Phase 4, Current drive phase)
(a) (b) (c) (d)

There are total 128 Gamma Settings (Setting 0 to Setting 127) available for the Gray Scale table. GS0 has no
pre-charge and current drive stages so it is in Gamma Setting 0.
When setting the Gray Scale Table (by BEh command) , the rules below must follow:
1) Only odd Gamma Settings (i.e. GS1, GS3, GS5,.....GS63) are entered after command BEh. SSD1355 will
automatically calculate the even Gamma Settings (i.e. GS2, GS4, GS6,.......GS62)
2) The gray scale is defined in incremental way, with reference to the length of previous table entry:
Setting of GS1 must > 0
Setting of GS3 must > Setting of GS1 +1
:
It should be notice that, the brightness under the following pairs of Gamma Setting will be the same:
Table 8-10 : Gamma Settings with identical brightness in current drive phase
Setting 15 & Setting 16 Setting 63 & Setting 64 Setting 111 & Setting 112
Setting 31 & Setting 32 Setting 79 & Setting 80
Setting 47 & Setting 48 Setting 95 & Setting 96

8.9 Power ON and OFF sequence
The following figures illustrate the recommended power ON and power OFF sequence of SSD1355 (assume
VCI and VDDIO are at the same voltage level and internal VDD is used).
Power ON sequence:
1. Power ON VCI, VDDIO.
2. After VCI, VDDIO become stable, set wait time at least 1ms (t0) for internal VDD become stable. Then
set RES# pin LOW (logic low) for at least 2us (t1) and then HIGH (logic high).
3. After set RES# pin LOW (logic low), wait for at least 2us (t2). Then Power ON VCC.(1)
4. After VCC become stable, send command 11h for Sleep Out. SEG/COM will be ON after 200ms (tAF).
Figure 8-14: The Power ON sequence.
ON VCI, VDDIO RES# ON VCC Send 11h command for Sleep Out
VCI,, VDDIO
t1
RES#
GND
VCC
tAF
ON
SEG/COM
OFF
Power OFF sequence:

1. Send command 10h for Sleep In.
2. Power OFF VCC.(1), (2)
3. Wait for tOFF. Power OFF VCI,, VDDIO. (where Minimum tOFF=0ms, Typical tOFF=100ms)
Figure 8-15: The Power OFF sequence
Send command 10h for Sleep In OFF VCC OFF VCI ,VDDIO
VCC
tOFF
VCI, VDDIO
Note:
(1)
Since an ESD protection circuit is connected between VCI, VDDIO and VCC, VCC becomes lower than VCI whenever
VCI,VDDIO is ON and VCC is OFF as shown in the dotted line of VCC in Figure 8-14 and Figure 8-15.
(2)
VCC should be kept float when it is OFF.

8.10 Tearing Effect Timing
TE synchronization signal can be used to prevent tearing effect.

Display Scanning Row# (COM Pin) 159 0 1 2 … … … … … 157 158 159 0 1 2 … … … … … 157 158 159 0 1
Display RAM Row# 0 1 2 … … … … … 157 158 159 0 1 2 … … … … … 157 158 159 0 1 2
OFF Mode, TE = 0 Falling Edge : one row

time before first row RAM.
Vsync Mode
Vsync Pulse
Total 149 Vsync Pulse

Hsync Pulse
Hsync Pulses
Vsync + Hsync Mode
MCU Write RAM 0 1 2 … … 158 159
Note:
(1) Assume MCU speed is faster than display speed.
(2) To avoid tearing effect, write the first row (row#=0) of data to RAM right after the falling edge of V-sync pulse.
(3) Hsync pulses are used for much more sophisticated applications.

8.11 VDD Regulator
In SSD1355, the power supply pin for core logic operation: VDD, can be supplied by external source or
internally regulated through the VDD regulator.
When the command B3h, bit A[0] is set to 1b, the internal VDD regulator is enabled. VCI should be larger than
2.6V when using the internal VDD regulator. The typical regulated VDD is about 2.5V
When the command B3h, bit A[0] is set to 0b, external VDD should be used. (external VDD range : 2.4V~2.6V)
It should be notice that, no matter VDD is supplied by external source or internally regulated, VCI must always
be equal or higher than VDD and VDDIO.
The following figure shows the VDD regulator pin connection scheme:
Figure 8-16 VCI > 2.6V, VDD regulator enable : pin connection scheme
VCI > 2.6V, VDD Regulator Enable,

Command: B3h A[0]=1b.
VCI VDDIO VSS VDD
VCI VDDIO GND
Figure 8-17 VDD regulator disable : pin connection scheme
VDD Regulator Disable,

Command: B3h A[0]=0b.
VCI VDDIO VSS VDD
VCI VDDIO GND VDD

8.11.1 VDD Regulator in Sleep Mode
Power can be saved by disable the internal VDD regulator during Sleep mode. The following figures show the
corresponding command sequence:
Figure 8-18 : Case 1 - Command sequence for just entering/ exiting sleep mode
Command for entering sleep mode : 10h (Sleep In)
Sleep mode
Command for exiting sleep mode : 11h (Sleep Out)
Figure 8-19 : Case 2 - Command sequence for disabling internal VDD regulator during sleep mode
Command for entering sleep mode : 10h (Sleep In)
Command for disable internal VDD regulator: B3h, bit A[0] is set to 0b
Sleep mode
Command for enable internal VDD regulator (1): B3h, bit A[0] is set to 1b
Wait at least 1ms for VDD becomes stable
Command for exiting sleep mode : 11h (Sleep Out)
In the above two cases, the RAM content can also be kept during the sleep mode.
Note:
(1)
It should be noted that the internal VDD regulator should be enabled before exiting sleep mode (issuing command 11h).
(2)
No RAM access through MCU interface when there is no external/ internal VDD.

9 COMMAND
9.1 Basic Command List

Operational Code (Hex) Function Bytes of Parameter
00 No Operation (NOP) 0
01 Software Reset (SWRESET) 0
04 Read Display Identification Information (RDDIDIF) 2
0A Read Display Power Mode (RDDPM) 2
0B Read Display MADCTL (RDDMADCTL) 2
0C Read Display Pixel Format (RDDCOLMOD) 2
0D Read Display Image Mode (RDDIM) 2
0E Read Display Signal Mode (RDDSM) 2
10 Sleep In (SLPIN) 0
11 Sleep Out (SLPOUT) 0
12 Enable Partial Display (PTLON) 0
13 Normal Display Mode ON (NORON) 0
20 Display Inversion OFF (INVOFF) 0
21 Display Inversion ON (INVON) 0
23 All Pixels ON (ALLPON) 0
28 All Pixels OFF(ALLPOFF) 0
29 Disable All Pixels ON/OFF (DISPON) 0
2A Set Column Address (CASET) 2
2B Set Row Address (RASET) 2
2C Memory Write (RAMWR) Any length
2E Memory Read (RAMRD) Any length
30 Set Partial Display Area (PLTAR) 2
33 Set Vertical Scrolling Areas (VSCRDEF) 3
34 Disable Tearing Effect (TEOFF) 0
35 Enable Tearing Effect (TEON) 1
36 Memory Access Control (MADCTL) 2
37 Vertical Scrolling Start Address(VSCRSADD) 1
3A Interface Pixel Format (COLMOD) 1
51 Write Luminance (SETLUM) 1
52 Read Luminance (RDLUM) 2
DA Read Display Identification Information (RDDIDIF) 2

9.2 Supplementary Command List
Operational Code (Hex) Function Bytes of Parameter
B1 OTP Write (OTPWR) 3
B2 OTP MCU Read (OTPRD) 3
B3 Function Selection (FUSEL) 1
B9 Linear Gamma Look Up Table (LINGLUT) 0
BA Set Contrast for Color A,B,C (ISEGABC) 5
BD Set First Pre-Charge Voltage (VPSET) 1
BE Gamma Look Up Table (GLUT) 96
C8 Set Display Offset (SETDO) 1
C9 Horizontal Scrolling (HORSCR) 1
CA Set MUX ratio (SETMUX) 1
CD Set Phase Length (PHLEN) 1
CE Set Second Precharge Period (SECPLEN) 1
CF Set Second Precharge Speed (SSPS) 1
D2 Set Display Clock Divider / Oscillator Frequency (SDCOSCF) 1
D3 Set VCOMH (SETVCOMH) 1
D7 GPIO (GPIO) 1
FD Command Lock (COMLCK) 1
Note
(1)
Issue command FDh Æ B3h to access the above supplementary commands

9.3 Command Description
Note
(1)
“xx” stands for “Don’t care”.
9.3.1 NOP (00h)

00 h NOP (No Operation)
D/C# RD# WR# D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ 0 0 0 0 0 0 0 0 00
Parameter NO PARAMETER
This is the no operation command.
However it can be used to terminate RAM Write or Read as described in RAMWR (2Ch, Memory
Description
Write) and RAMRD (2Eh, Memory Read) Commands.
Status Availability
Normal Mode ON, Sleep Out Yes
Command
Partial Mode ON, Sleep Out Yes
Availability
Sleep In Yes
Status Default Value

S/W Reset N/A
Default
H/W Reset N/A

9.3.2 Software Reset (01h)
01 h SWRESET (Software Reset)
Command 0 1 ↑ 0 0 0 0 0 0 0 1 01
When the Software Reset command is written, it causes software reset for the following commands. It resets the
commands and parameters to their S/W Reset default values. (See default tables in each command description.)
The display turns OFF after Software Reset command is written.
Software Reset scope:

Description
1) All basic commands except 0Ch (Read Display Pixel Format), 36h (Memory Access Control) & 3Ah
(Interface Pixel Format)
2) One supplementary command : B1h (OTP Write )
Note
(1)
The RAM contents and other supplementary commands are unaffected by this command
Status Availability
Command
Availability
Sleep In Yes

S/W Reset N/A
Default
H/W Reset N/A

9.3.3 Read Display Identification Information (04h)
04 h RDDIDIF (Read Display Identification Information)
Command 0 1 ↑ 0 0 0 0 0 1 0 0 04
st
1 Parameter 1 ↑ 1 xx xx xx xx xx xx xx xx xx
2nd Parameter 1 ↑ 1 0 0 0 0 ID3 ID2 ID1 ID0 xx
This read byte returns 4-bit Display Identification Information.
The 1st parameter is dummy read.

Description
The 2nd parameter ID[3:0] returns the Display Identification Information burned in OTP through B1h
command.
Status Availability
Command Normal Mode ON, Sleep Out Yes
Availability Partial Mode ON, Sleep Out Yes
Sleep In Yes
Status Default Value before OTP Default Value after OTP

Programming Programming
Default S/W Reset ID[3:0] = 0000b OTP content
H/W Reset ID[3:0] = 0000b OTP content

9.3.4 Read Display Power Mode (0Ah)
0A h RDDPM (Read Display Power Mode)
Command 0 1 ↑ 0 0 0 0 1 0 1 0 0A
1st Parameter 1 ↑ 1 xx xx xx xx xx xx xx xx xx
2nd Parameter 1 ↑ 1 0 0 A5 A4 A3 A2 0 0 xx
This command indicates the current status of the display as described in the table below:
Bit Description
A5 Partial Mode ON/OFF
A4 Sleep In/Out
A3 Display Normal Mode ON/OFF
A2 All pixels OFF
• Bit A5 – Partial Mode ON/OFF (refer to command 12h)

‘0’ = Partial Mode OFF.
‘1’ = Partial Mode ON.
Description
• Bit A4 – Sleep In/Out (refer to command 10h, 11h)
‘0’ = Sleep In Mode.
‘1’ = Sleep Out Mode.
• Bit A3 – Display Normal Mode ON/OFF (refer to command 13h)

‘0’ = Display Normal Mode OFF (i.e. Partial mode or vertical scroll mode enabled)
‘1’ = Display Normal Mode ON. (i.e. Neither partial mode nor vertical scroll mode enabled)
• Bit A2 – All pixels OFF (refer to command 28h, 29h)

‘0’ = All pixels OFF
‘1’ = Disable All pixels OFF
Status Availability
Sleep In Yes

Default S/W Reset 08h
H/W Reset 08h

9.3.5 Read Display MADCTL (0Bh)
0B h RDDMADCTL (Read Display MADCTL)
Command 0 1 ↑ 0 0 0 0 1 0 1 1 0B
2nd Parameter 1 ↑ 1 A7 A6 A5 0 A3 0 0 0 xx
(MADCTL refers to command 36h Memory Access Control)
Bit Description
A7 COM scan direction Remap
A6 Column Address Mapping
A5 Address Increment mode
A3 RGB Mapping
• Bit A7 – COM scan direction Remap

‘0’ = Scan from COM0 to COM[N –1] (When MADCTL A7=’0’).
‘1’ = Scan from COM[N-1] to COM0. (When MADCTL A7=’1’).
(Where N is the multiplex ratio.)
Description
• Bit A6 – Column Address Mapping
‘0’ = Mapping display data RAM column 0 to SEG0 pin (When MADCTL A6=’0’).
‘1’ = Mapping display data RAM column 127 to SEG0 pin (When MADCTL A6=’1’).
• Bit A5 – Address Increment mode

‘0’ = Horizontal address increment mode (When MADCTL A5=’0’).
‘1’ = Vertical address increment mode (When MADCTL A5=’1’).
• Bit A3 – RGB Mapping

‘0’ = normal order SA,SB,SC (e.g. BGR) (When MADCTL A3=’0’).
‘1’ = reverse order SC,SB,SA (e.g. RGB) (When MADCTL A3=’1’).
Note
1
Refer to section 9.3.26 Memory Access Control (36h).
Status Availability
Sleep In Yes

S/W Reset No Change
Default
H/W Reset 00h

9.3.6 Read Display Pixel Format (0Ch)
0C h RDDCOLMOD (Read Display COLMOD)
Command 0 1 ↑ 0 0 0 0 1 1 0 0 0C
2nd Parameter 1 ↑ 1 0 0 0 0 0 A2 A1 A0 xx
Bit Description
A2
A1 Control Interface Colour Format
A0
• Bits A2, A1, A0 – Control Interface Colour Pixel Format Definition. See section “9.3.28 Interface
Pixel Format (3Ah)”.
Description Interface Format A2 A1 A0
Not Defined 0 0 0
Not Defined 0 0 1
Not Defined 0 1 0
Not Defined 0 1 1
Not Defined 1 0 0
16 Bit/Pixel (65k color) 1 0 1
Not Defined 1 1 1
Status Availability
Sleep In Yes

Default S/W Reset No Change
H/W Reset 18 bit/pixel

9.3.7 Read Display Image Mode (0Dh)
0D h RDDIM (Read Display Image Mode)
Command 0 1 ↑ 0 0 0 0 1 1 0 1 0D
2nd Parameter 1 ↑ 1 A7 0 A5 A4 0 0 0 0 xx
This command indicates the current status of the display as below described:
• Bit A7 – Vertical Scrolling ON/OFF (refer to command 37h)

‘0’ = Vertical Scrolling is OFF.
‘1’ = Vertical Scrolling is ON.
• Bit A5 – Display Inversion ON/OFF (refer to command 20h & 21h)

Description
‘0’ = Display Inversion is OFF.
‘1’ = Display Inversion is ON.
• Bit A4 – All Pixels ON (refer to command 23h &29h)

‘0’ = Disable All pixels ON
‘1’ = All pixels ON
Status Availability
Sleep In Yes

Default S/W Reset 00h
H/W Reset 00h

9.3.8 Read Display Signal Mode (0Eh)
0E h RDDSM (Read Display Signal Mode)
Command 0 1 ↑ 0 0 0 0 1 1 1 0 0E
2nd Parameter 1 ↑ 1 A7 A6 0 0 0 0 0 0 xx
This command indicates the current status of the display as below described:
• Bit A7 – Tearing Effect Line ON/OFF ( refer to command 34h, 35h)

‘0’ = Tearing Effect Line OFF.(i.e. output LOW)
Description ‘1’ = Tearing Effect ON.
• Bit A6 – Tearing Effect Line Output Mode ( refer to command 34h, 35h)
‘0’ = Mode 1.
‘1’ = Mode 2.
Status Availability
Sleep In Yes

Default S/W Reset A[7]=0
H/W Reset A[7]=0

9.3.9 Sleep In (10h)
10 h SLPIN (Sleep In)
Command 0 1 ↑ 0 0 0 1 0 0 0 0 10
This command is used to turn the OLED panel display OFF.
When the display is OFF, circuits will be turned OFF.
Description Internal VDD regulator, MCU interface and memory are still working and the memory keeps its
contents.
This command has no effect when module is already in sleep in mode. Sleep In Mode can only be exit
Restriction by the Sleep Out Command (11h).
Status Availability
Sleep In Yes

Default S/W Reset Sleep in mode
H/W Reset Sleep in mode

9.3.10 Sleep Out (11h)
11 h SLPOUT (Sleep Out)
Command 0 1 ↑ 0 0 0 1 0 0 0 1 11
This command turns ON the display and exist the sleep mode.
SEG
SEG OFF
...
16 Frames
Description COM non-scan
HiZ
...
SEG / COM are ON

12 Frames
Sleep out
This command has no effect when module is already in sleep out mode. Sleep Out mode can only be
Restriction exit by the Sleep In Command (10h).
Status Availability
Sleep In Yes

Default S/W Reset Sleep in mode
H/W Reset Sleep in mode

9.3.11 Enable Partial Display (12h)
12 h PTLON (Enable Partial Display)
Command 0 1 ↑ 0 0 0 1 0 0 1 0 12
This command turns ON partial mode. The partial mode window is described by the Set Partial Display
Area command (30h).
Description
To exit Partial mode, the Normal Display Mode ON command (13h) should be written.
Restriction This command has no effect when Partial mode is active.
Status Availability
Command
Availability
Sleep In Yes

S/W Reset Normal Mode ON
Default
H/W Reset Normal Mode ON

9.3.12 Normal Display Mode ON (13h)
13 h NORON (Normal Display Mode ON)
Command 0 1 ↑ 0 0 0 1 0 0 1 1 13
This command returns the display to normal mode.
Normal display mode ON means Partial Display mode OFF (1) , Vertical Scroll mode OFF (2).
Figure 9-1 : Transition between different modes
Normal mode
13h
13h
37h
12h
Description 37h
Partial Display mode Vertical Scroll mode

12h
Note:
(1)
Refer to command 12h for Partial Display mode
(2)
Refer to command 37h for Vertical Scroll mode.
Restriction This command has no effect when Normal Display mode is active.
Status Availability
Sleep In Yes

Default S/W Reset Normal Mode ON
H/W Reset Normal Mode ON

9.3.13 Display Inversion OFF (20h)
20 h INVOFF (Display Inversion OFF)
Command 0 1 ↑ 0 0 1 0 0 0 0 0 20
This command is used to recover from display inversion mode (21h).
This command makes no change of contents of RAM.
Figure 9-2 : Example of Inverse Display OFF

Example
Description
GDDRAM Display
Restriction This command has no effect when it is already in inversion OFF mode.
Status Availability
Sleep In Yes

Default S/W Reset Display Inversion OFF
H/W Reset Display Inversion OFF

9.3.14 Display Inversion ON (21h)
21 h INVON (Display Inversion ON)
Command 0 1 ↑ 0 0 1 0 0 0 0 1 21
This command is used to enter into display inversion mode.
This command makes no change of contents of RAM. Every bit is inverted from the RAM to the
display.
Figure 9-3 : Example of Inverse Display ON
Description
GDDRAM Display
This command has no effect when it is already in inversion ON mode, All Pixels ON mode (23h) or All
Restriction
Pixels OFF mode (28h).
Status Availability
Sleep In Yes

Default S/W Reset Display Inversion OFF
H/W Reset Display Inversion OFF

9.3.15 All Pixels ON (23h)
23 h ALLPON (All Pixels ON)
Command 0 1 ↑ 0 0 1 0 0 0 1 1 23
This command forces the entire display to be at “GS63” (1) regardless of the contents of the display data
RAM

Figure 9-4 : Example of all pixel ON
GDDRAM Display
Description
The display will exit the “All pixels ON” mode through issuing commands: ‘All Pixels OFF
(28h)’, ’Disable All Pixels ON/OFF (29h)’ or ’Partial Mode ON (12h)(2)’.
The display is showing the content of the RAM after’ Disable All Pixels ON/OFF (29h)’ and ’Partial
Mode ON (12h)’.
Note
(1)
Refer to section 8.8 for details of GS63
(2)
The default partial display area is full MUX with 128RGB x 160, and the partial display area can be
set by using command ‘Partial Area (30h)’
Restriction This command has no effect when it is already in All Pixels ON mode.
Status Availability
Command
Availability
Sleep In Yes

S/W Reset Disable All Pixels ON
Default
H/W Reset Disable All Pixels ON

9.3.16 All Pixels OFF (28h)
28 h ALLPOFF (All Pixels OFF)
Command 0 1 ↑ 0 0 1 0 1 0 0 0 28
This command is used to enter into ALL PIXELS OFF mode.
In this mode, the entire display to be at gray level “GS0” (1) regardless of the contents of the display data
RAM.

Figure 9-5 : Example of all pixels OFF
Description
GDDRAM Display
The display returns to normal display (showing the content of the RAM) through issuing command 29h
“Disable All Pixels ON/OFF”.
Note
(1)
Refer to section 8.8 for details of GS0
Restriction This command has no effect when it is already in display OFF mode.
Status Availability
Sleep In Yes

S/W Reset Disable All Pixels OFF
Default
H/W Reset Disable All Pixels OFF

9.3.17 Disable All Pixels ON/OFF (29h)
29 h DISPON (Display ON)
Command 0 1 ↑ 0 0 1 0 1 0 0 1 29
This command is used to recover from All Pixels ON/OFF mode. Output from the RAM is enabled.
Figure 9-6 : Example of Disable All Pixels ON/OFF
Example
Description
GDDRAM Display
Restriction This command has no effect when it is already in Disable All Pixels ON/OFF mode.
Status Availability
Command
Availability
Sleep In Yes

S/W Reset Disable All Pixels ON/OFF
Default
H/W Reset Disable All Pixels ON/OFF

9.3.18 Set Column Address (2Ah)
2A h CASET (Set Column Address)
Command 0 1 ↑ 0 0 1 0 1 0 1 0 2A
1st Parameter 1 1 ↑ xx SC6 SC5 SC4 SC3 SC2 SC1 SC0 00..7F
2nd Parameter 1 1 ↑ xx EC6 EC5 EC4 EC3 EC2 EC1 EC0 00..7F
This command is used to define area of RAM where MCU can access.
The values of Start Column Address (SC[6:0]) and End Column Address (EC[6:0]) are referred when
Memory Write command (2Ch) is issued. Each value represents one column line in the RAM.
Description
Restriction SC[6:0] always must be equal to or less than EC[6:0]
Status Availability
Sleep In Yes

S/W Reset When Bit A5 of command 36h = 0b When Bit A5 of command 36h = 1b
Default SC[6:0]=00h SC[6:0]=00h
EC[6:0] = 7Fh EC[6:0] = 9Fh
H/W Reset SC[6:0]=00h EC[6:0] = 7Fh

9.3.19 Set Row Address (2Bh)
2B h RASET (Set Row Address)
Command 0 1 ↑ 0 0 1 0 1 0 1 1 2B
1st Parameter 1 1 ↑ SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 00..9F
2nd Parameter 1 1 ↑ ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 00..9F
This command is used to define area of RAM where MCU can access.
The values of Start row address (SR[7:0]) and End row address (ER[7:0]) are referred when Memory
Write command (2Ch) is issued.
Each value represents one row line in the RAM.
Description
Restriction SR[7:0] always must be equal to or less than ER[7:0]
Status Availability
Command
Availability
Sleep In Yes

S/W Reset When Bit A5 of command 36h = 0b When Bit A5 of command 36h = 1b
SR[7:0] = 00h SR[7:0] = 00h
Default
ER[7:0] = 9Fh ER[7:0] = 7Fh
H/W Reset SR[7:0]=00h ER[7:0] = 9Fh

9.3.20 Memory Write (2Ch)
2C h RAMWR (Memory Write)
Command 0 1 ↑ 0 0 1 0 1 1 0 0 2C
1st Parameter 1 1 ↑ D17 D16 D15 D14 D13 D12 D11 D10 00..FF
: 1 1 ↑ Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 00..FF
th
N Parameter 1 1 ↑ Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 00..FF
This command is used to transfer data from MCU to RAM.
After this command, data entries will be written into the display RAM until another command is written.
(Sending any other command can stop memory write.) This command must be sent before write data into
RAM.
When this command is accepted, the column register and the row register are reset to the Start
Column/Start Row positions.
Then parameters are stored in RAM and the column register and the row register incremented as stated in
table below:
Table 9-1 : Controls for column and row counters under different conditions
Description
Conditions Column Counter Row Counter
When RAMWR (Command 2Ch) / RAMRD Return to Return to
(Command 2Eh) command is accepted. “Start Column” “Start Row”
Complete Pixel Read/Write action Increment by 1 No change
The Column counter value is larger than “End Return to Increment by 1
column.” “Start Column”
The Column counter value is larger than “End column” Return to Return to
and the Row counter value is larger than “End Row”. “Start Column” “Start Row”
Refer to Table 8-8 for colour coding during write.
Status Availability
Command
Availability
Sleep In Yes

S/W Reset Contents of memory is not cleared
Default
H/W Reset Contents of memory is not cleared

9.3.21 Memory Read (2Eh)
2E h RAMRD (Memory Read)
Command 0 1 ↑ 0 0 1 0 1 1 1 0 2E
2nd Parameter 1 ↑ 1 D17 D16 D15 D14 D13 D12 D11 D10 00..FF
: 1 ↑ 1 Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 00..FF
(N+1) th
1 ↑ 1 Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 00..FF
Parameter
This command is used to transfer data from RAM to MCU.
After this command, data is read from the display RAM until another command is written. (Sending
any other command can stop memory read.) This command must be sent before read data from RAM.
When this command is accepted, the column register and the row register are reset to the Start
Column/Start Row positions.
Description The 1st parameter is dummy read.

Then parameters are read back from the RAM .The column register and the row register incremented
as in Table 9-1.
Refer to Table 8-9 for colour coding during read.
Note
(1)
Memory Read is only possible via the Parallel Interface.
Status Availability
Sleep In Yes

Default S/W Reset Contents of memory is not cleared
H/W Reset Contents of memory is not cleared

9.3.22 Partial Area (30h)
30 h PLTAR (Partial Area)
Command 0 1 ↑ 0 0 1 1 0 0 0 0 30
1st Parameter 1 1 ↑ SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 00..9F
2nd Parameter 1 1 ↑ ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 00..9F
This command defines the partial mode’s display area. There are 2 parameters associated with this
command, the first defines the Start Row (SR) and the second the End Row (ER), as illustrated in the
figures below. SR and ER refer to the RAM Line Pointer.
If End Row>Start Row:
If End Row<Start Row:
Description
If End Row = Start Row, then the Partial Area will be one row.
Figure 9-7 : Example of partial display function
SR[7:0]=16d OFF Area
Partial Display
Area
13:55 OFF Area
ER[7:0]=110d
Status Availability
Sleep In Yes

Default S/W Reset SR[7:0] =00h, ER[7:0]=9Fh
H/W Reset SR[7:0] =00h, ER[7:0]=9Fh

9.3.23 Vertical Scrolling Definition (33h)
33 h VSCRDEF (Vertical Scrolling Definition)
Command 0 1 ↑ 0 0 1 1 0 0 1 1 33
st
1 Parameter 1 1 ↑ TFA7 TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 TFA0 00..A0
2nd Parameter 1 1 ↑ VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 00..A0
3rd Parameter 1 1 ↑ BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0 00..A0
This command defines the Vertical Scrolling Area of the display. TFA, VSA and BFA refer to the
RAM Line Pointer.
The 1st parameter TFA[7:0] describes the Top Fixed Area in number of rows.
The 2nd parameter VSA[7:0] describes the height of the Vertical Scrolling Area in number of rows
from the Vertical Scrolling Start Address. The first row read from RAM appears immediately after the
bottom most row of the Top Fixed Area.
The 3rd parameter BFA[7:0] describes the Bottom Fixed Area in number of rows. It should be set to
MUX ratio - VSA - TFA. (where MUX ratio is set by command CAh).
i.e. TFA+VSA+BFA = MUX ratio
The vertical scrolling is determined by commands “Vertical Scrolling Definition” (33h) and “Vertical
Scrolling Start Address” (37h).
TFA = Top Fixed Area
SCA = Vertical Scrolling Area
BFA = Bottom Fixed Area
Status Availability
Sleep In Yes

Default S/W Reset TFA [7:0]=00h VSA[7:0]=A0h BFA[7:0]=00h
H/W Reset TFA [7:0]=00h VSA[7:0]=A0h BFA[7:0]=00h

9.3.24 Disable Tearing Effect (34h)
34 h TEOFF (Tearing Effect Line OFF)
Command 0 1 ↑ 0 0 1 1 0 1 0 0 34
This command is used to turn OFF (output LOW) the Tearing Effect output signal from the TE signal
Description
line.
Restriction This command has no effect when Tearing Effect output is already OFF.
Status Availability
Sleep In Yes

Default S/W Reset OFF
H/W Reset OFF
9.3.25 Enable Tearing Effect (35h)

35 h TEON (Tearing Effect Line ON)
Command 0 1 ↑ 0 0 1 1 0 1 0 1 35
Parameter 1 1 ↑ xx xx xx xx xx xx xx M0 xx
This command is used to turn ON the Tearing Effect output signal from the TE signal line.
The Tearing Effect Line ON has one parameter which describes the mode of the Tearing Effect Output
Line.
When M[0]=0:
Vertical synchronization (Vsync) pulse only
Description
When M[0]=1:
Vertical synchronization (Vsync) pulse + Horizontal synchronization (Hsync) pulse
Status Availability
Sleep In Yes

Default S/W Reset OFF
H/W Reset OFF

9.3.26 Memory Access Control (36h)
36 h MADCTL (Memory Access Control)
Command 0 1 ↑ 0 0 1 1 0 1 1 0 36
st
1 Parameter 1 1 ↑ A7 A6 A5 0 A3 xx xx xx xx
2nd Parameter 1 1 ↑ xx xx BS3 BS2 xx xx A1 A0 xx
This command has multiple configurations, for example, defines read/write scanning direction of
RAM , MCU bus interface selection bits and COM pins hardware configuration. Each bit setting is
described as follows:
BIT NAME DESCRIPTION
A7 COM scan direction Remap Details refer to description below.
A6 Column Address Mapping
A5 Address Increment mode
A3 RGB Mapping This command bit is made for flexible layout of
segment signals in OLED module to match filter
design.
A[3]=0, normal order SA,SB,SC (e.g. BGR) [reset]

A[3]=1, reverse order SC,SB,SA (e.g. RGB)
A1 COM Left / Right Remap This command bit is made for flexible layout of
common signals in OLED module with COM0
arranged on either left or right side.
A[1]=0, Disable left-right swapping on COM [reset]

A[1]=1, Set left-right swapping on COM
A0 Odd Even Split of COM pins This bit can set the odd even arrangement of COM
pins.
A[0] = 0: Disable COM split odd even, pin
assignment of common is in sequential.
A[0] = 1: Enable COM split odd even, pin
assignment of common is in odd even split. [reset]
Description
BS[3:2] MCU bus interface selection Select appropriate logic setting as described in the
bits following table.
BS[3:2] Interface
00 SPI, 8-bit parallel [reset]
01 16-bit parallel
11 18-bit parallel
BS3 and BS2 are command programmable (by
command 36h).
BS1 and BS0 are pin select (refer to Table 7-2).
• Address increment mode (A[5])
When it is set to 0, the driver is set as horizontal address increment mode. After the display
RAM is read/written, the column address pointer is increased automatically by 1. If the
column address pointer reaches column end address, the column address pointer is reset to
column start address and row address pointer is increased by 1. The sequence of movement of
the row and column address point for horizontal address increment mode is shown in Figure
9-8.
Figure 9-8 : Address Pointer Movement of Horizontal Address Increment Mode
Col 0 Col 1 ….. Col 126 Col 127
Row 0
Row 1
: : : : : :
Row 158
Row 159

When A[5] is set to 1, the driver is set to vertical address increment mode. After the display
RAM is read/written, the row address pointer is increased automatically by 1. If the row
address pointer reaches the row end address, the row address pointer is reset to row start
address and column address pointer is increased by 1. The sequence of movement of the row
and column address point for vertical address increment mode is shown in Figure 9-9.
Figure 9-9 : Address Pointer Movement of Vertical Address Increment Mode
Col 0 Col 1 ….. Col 126 Col 127
Row 0 …..
Row 1 …..
: :
Row 158 …..
Row 159 …..
• Column Address Mapping (A[6])

This command bit is made for flexible layout of segment signals in OLED module with
segment arranged from left to right or vice versa. The display direction is either mapping
display data RAM column 0 to SEG0 pin (A[6] = 0), or mapping display data RAM column
127 to SEG0 pin (A[6] = 1). The effects of both are shown in Figure 9-10.
• COM scan direction Remap (A[7])

This bit determines the scanning direction of the common for flexible layout of common
signals in OLED module either from up to down or vice versa. Details of bit A[7] can be
found in Figure 9-10.
A[7]=0, Scan from COM0 to COM[N –1] (No Remap)
A[7]=1, Scan from COM[N-1] to COM0 (Remap). Where N is the multiplex ratio.
Figure 9-10 : Example Bit A[5], A[6], A[7] in command MADCTL (36h)
Example square image is like this:
Display Example A5 A6 A7
Normal
0 0 0
Y-Invert
0 0 1
X-Invert
0 1 0

Display Example A5 A6 A7
X-Invert+ Y-Invert
0 1 1
Exchange Row-Column
1 0 0
Exchange Row-Column + X Invert (270 deg rotation)
1 0 1
Exchange Row-Column + Y Invert (90 deg rotation)
1 1 0
Exchange Row-Column + X Invert + Y Invert
1 1 1
Figure 9-11 : COM Pins Hardware Configuration (MUX ratio: 160)
Case and Conditions COM pins Configurations

A ROW159
A[0] =0 A[1]=0 A[7]=0
Disable Odd Disable COM COM Scan
Even Split of Left / Right Direction : from
COM pins Remap COM0 to ROW80 128 x 160
COM159 ROW79
Pin name Panel

COM 0 Row 0
COM 1 Row 1 ROW0
COM 2 Row 2
… ... … ...
COM 78 Row 78 COM80 COM0
SSD1355Z
COM 79 Row 79
COM159 COM79
COM 80 Row 80
COM 81 Row 81
… … ...
COM 157 Row 157 Pad 1,2,3,…192
COM 158 Row 158 Gold Bumps face up
COM 159 Row 159


B
A[0] =0 A[1]=1 A[7]=0 ROW159
Disable Odd Enable COM COM Scan
COM pins Remap COM0 to
COM159 128x160
ROW80
ROW79
Pin name Panel
COM 0 Row 80
COM 1 Row 81
ROW0
COM 2 Row 82
… ... … ...
COM 78 Row 158
SSD1355Z
COM 80 Row 0
COM159 COM79
COM 81 Row 1
… … ...
COM 157 Row 77
COM 158 Row 78 Pad 1,2,3,…192
C ROW0
A[0] =0 A[1]=0 A[7]=1
Disable Odd Disable COM COM Scan
COM pins Remap COM159 to ROW79 128 x 160
COM0 ROW80
Pin name Panel
COM 0 Row 159
COM 1 Row 158
COM 2 Row 157 ROW159
… ... … ...
COM 78 Row 81
SSD1355Z
COM 80 Row 79
… … ...
COM 157 Row 2
COM 158 Row 1 Pad 1,2,3,…192
D
A[0] =0 A[1]=1 A[7]=1 ROW0
Disable Odd Enable COM COM Scan
COM0 128x160 ROW79
ROW80
Pin name Panel
COM 0 Row 79
COM 1 Row 78
COM 2 Row 77 ROW159
… ... … ...
COM 78 Row 1
COM 80 Row 159
SSD1355Z
COM159 COM79
COM 81 Row 158
… … ...
COM 157 Row 82
COM 158 Row 81 Pad 1,2,3,…192


E [reset] ROW159 ROW158
A[0] =1 A[1]=0 A[7]=0 ROW157

Enable Odd Disable COM COM Scan
COM pins Remap COM0 to 128 x 160
COM159
Pin name Panel

COM 0 Row 0
ROW2
COM 1 Row 2 ROW1
COM 2 Row 4
ROW0
… ... … ...
COM 78 Row 156 COM0
COM80 SSD1355Z
COM 79 Row 158 COM1
COM158 COM159 COM79
COM 80 Row 1
COM 81 Row 3
… … ...
COM 157 Row 155 Pad 1,2,3,…192
COM 159 Row 159
F
A[0] =1 A[1]=1 A[7]=0 ROW159
ROW158
Enable Odd Enable COM COM Scan ROW157
COM159 128 x 160
Pin name Panel
COM 0 Row 1
COM 1 Row 3
COM 2 Row 5
ROW2 ROW1
… ... … ...
COM 78 Row 157 ROW0
COM 80 Row 0 COM81 SSD1355Z

COM 81 Row 2 COM159 COM79 COM78
… … ...
COM 157 Row 154
COM 158 Row 156
Pad 1,2,3,…192
COM 159 Row 158
Gold Bumps face up
G
A[0] =1 A[1]=0 A[7]=1 ROW0
ROW1
Enable Odd Disable COM COM Scan ROW2

COM0 128 x 160
Pin name Panel

COM 0 Row 159
COM 1 Row 157
ROW157
COM 2 Row 155 ROW158
… ... … ...
ROW159
COM 78 Row 3
COM 79 Row 1 COM0
COM80 SSD1355Z
COM 80 Row 158 COM1
COM158 COM159 COM79
COM 81 Row 156
… … ...
COM 157 Row 4
COM 158 Row 2 Pad 1,2,3,…192


H ROW0
A[0] =1 A[1]=1 A[7]=1 ROW1

ROW2
Enable Odd Enable COM COM Scan
128 x 160
COM0
Pin name Panel

COM 0 Row 158
COM 1 Row 156 ROW157 ROW158
COM 2 Row 154
… ... … ... ROW159
COM80 COM0
COM 78 Row 2
COM 79 Row 0 COM81 SSD1355Z
COM 80 Row 159 COM159 COM79 COM78
COM 81 Row 157
… … ...
COM 157 Row 5 Pad 1,2,3,…192
COM 159 Row 1
Status Availability
Command
Availability
Sleep In Yes

S/W Reset No Change
Default
H/W Reset A7=0, A6=0, A5=0, A4=0, A3=0, A1=0, A0=1
BS[3:2]=00.

9.3.27 Vertical Scrolling Start Address (37h)
37 h VSCRSADD (Vertical Scrolling Start Address)
Command 0 1 ↑ 0 0 1 1 0 1 1 1 37
Parameter 1 1 ↑ VSP7 VSP6 VSP5 VSP4 VSP3 VSP2 VSP1 VSP0 00..23
This command is used together with Vertical Scrolling Definition (33h). These two commands
describe the scrolling area and the scrolling mode.
The Vertical Scrolling Start Address command has one parameter which describes the address of the
row in the RAM that will be written as the first row after the last row of the Top Fixed Area on the
display as illustrated below:
Example:
When Top Fixed Area = Bottom Fixed Area = 0, Vertical Scrolling Area = 160 and VSP=’3’.
Description
Note
(1)
When new Pointer position and Picture Data are sent, the result on the display will happen at the
next frame to avoid tearing effect.
(2)
VSP refers to the RAM row Pointer.
(3)
Vertical Scroll mode is entered by issuing this command. Entering command 13h can OFF Vertical
Scroll mode.
Since the value of the Vertical Scrolling Start Address is absolute (with reference to the
RAM), it must not enter the fixed area (defined by Vertical Scrolling
Definition (33h), otherwise undesirable image will be displayed on the Panel.
Restriction
e.g.
If Top Fixed Area =2, Bottom Fixed Area = 3, Vertical Scrolling Area = 155 ( set by command 33h),
then RAM row 0, row 1, row 157, row 158 and row 159 are in the fixed area.
As a result VSP should be set within the range 2~156.
Status Availability
Sleep In Yes

Default S/W Reset VSP[7:0]=00h
H/W Reset VSP[7:0]=00h

9.3.28 Interface Pixel Format (3Ah)
3A h COLMOD (Interface Pixel Format)
Command 0 1 ↑ 0 0 1 1 1 0 1 0 3A
Parameter 1 1 ↑ XX XX XX XX XX A2 A1 A0 xx
This command is used to define the format of RGB picture data, which is to be transferred via the MCU
Interface. The formats are shown in the table:
Interface Format A2 A1 A0
Not Defined 0 0 0
Not Defined 0 0 1
Not Defined 0 1 0
Description
Not Defined 0 1 1
Not Defined 1 0 0
Not Defined 1 1 1
Note
(1)
16 Bit/Pixel mode is not available for 18bit interface.
Status Availability
Sleep In Yes

Default S/W Reset No Change
H/W Reset 18 Bit/Pixel

9.3.29 Write Luminance (51h)
This command has combined effect with the High Power Protection function. To eliminate the effect, once may set
according to below instruction.
Before setting write luminance command, disable the High Power protection (command: B3h Æ 00h or 01h) first.
e.g. Disable High Power Protection -> set luminance to 1111b
B3hÆ 00h or 01h Æ 51h Æ F0h.
“00” or “01” depends on enable/disable internal VDD regulator.
51 h WRLUM (Write Luminance)

Command 0 1 ↑ 0 1 0 1 0 0 0 1 51
Parameter 1 1 ↑ LUM3 LUM2 LUM1 LUM0 XX XX XX XX 00..FF
This command is to control the segment output current by a scaling factor. This factor is common to
color A, B and C. The chip has 16 master control steps. The factor is ranged from 1 [0000b] to 16
[1111b]. Reset is 16 [1111b]. The smaller the master current value, the dimmer the OLED panel display
is set.
LUM[3:0] Master Current Control
Description 0000 1/16
0001 2/16
: :
1110 15/16
1111 16/16
Status Availability
Normal Mode On, Sleep Out Yes
Command
Partial Mode On, Sleep Out Yes
Availability
Sleep In Yes

S/W Reset LUM[3:0]=1111
Default
H/W Reset LUM[3:0]=1111

9.3.30 Read Luminance Value (52h)
52 h RDLUM (Read Luminance Value)
Command 0 1 ↑ 0 1 0 1 0 0 1 0 52
2nd Parameter 1 ↑ 1 LUM3 LUM2 LUM1 LUM0 xx xx xx xx xx
This read byte returns 4-bit master current value set by command 51h.

Description The 2nd parameter LUM[3:0] returns the 4-bit master current value set by command 51h.
Status Availability
Sleep In Yes

Default S/W Reset F0h
H/W Reset F0h

9.3.31 Read Display Identification Information (DAh)
DA h RDDIDIF (Read Display Identification Information )
Command 0 1 ↑ 1 1 0 1 1 0 1 0 DA
2nd Parameter 1 ↑ 1 0 0 0 0 ID3 ID2 ID1 ID0 xx
This command performs the same function as command 04h
This read byte returns 4-bit Display Identification Information.

Description
The 2nd parameter ID[3:0] returns the Display Identification Information burned in OTP through B1h
command.
Status Availability
Sleep In Yes
Status Default Value before OTP Default Value after OTP

Programming Programming
Default
S/W Reset ID[3:0] = 0000b OTP content
H/W Reset ID[3:0] = 0000b OTP content

9.3.32 OTP Write (B1h)
B1 h OTPWR (OTP Write)
Command 0 1 ↑ 1 0 1 1 0 0 0 1 B1
1st Parameter 1 1 ↑ P7 P6 P5 P4 P3 P2 P1 P0 xx
2nd Parameter 1 1 ↑ CB3 CB2 CB1 CB0 CA3 CA2 CA1 CA0 xx
3rd Parameter 1 1 ↑ ID3 ID2 ID1 ID0 CC3 CC2 CC1 CC0 xx
This command is used to program data from MCU to OTP (One Time Program).
The 1st parameter P[7:0] is used to select between OTP programming or OTP Emulation:
Function P[7:0]
OTP Programming : Burn the OTP contents 2Bh
OTP Emulation : For evaluation purpose 2Eh
The emulated OTP bytes can be cleared by hardware or software reset (01h)
The 2nd and 3rd parameters are for the OTP bytes:
− ID[3:0] is for the Display Identification Information. The burned Display Identification
Information can be read through 04h , B2h or DAh.
− CA[3:0] is for trimming Color A contrast (1)
− CB[3:0] is for trimming Color B contrast (1)
− CC[3:0] is for trimming Color C contrast (1)
Table 9-2 : Colour contrast adjustment
CA [3:0] Adjustment CB [3:0] Adjustment CC [3:0] Adjustment
0000 0% 0000 0% 0000 0%
0001 +1/32 0001 +1/32 0001 +1/32
0010 +2/32 0010 +2/32 0010 +2/32
0011 +3/32 0011 +3/32 0011 +3/32
0100 +4/32 0100 +4/32 0100 +4/32
0101 +5/32 0101 +5/32 0101 +5/32
0110 +6/32 0110 +6/32 0110 +6/32
Description 0111 +7/32 0111 +7/32 0111 +7/32
1000 0% 1000 0% 1000 0%
1001 -1/32 1001 -1/32 1001 -1/32
1010 -2/32 1010 -2/32 1010 -2/32
1011 -3/32 1011 -3/32 1011 -3/32
1100 -4/32 1100 -4/32 1100 -4/32
1101 -5/32 1101 -5/32 1101 -5/32
1110 -6/32 1110 -6/32 1110 -6/32
1111 -7/32 1111 -7/32 1111 -7/32
The steps for OTP programming (P[7:0]=2Bh):

1. Power up VPP to 2.5V
2. Power up VDD to 2.5V
3. Hardware Reset
4. Set DCLK frequency to 9kHz (2) , (3)
5. Send OTP write Command B1h
6. Send Data 2Bh for OTP burn
7. Power Up VPP to 7.5V
8. Send two OTP bytes through MCU interface
9. Wait >=1ms for OTP burn process
10. Lower VPP and wait for VPP down to 2.5V
11. Send Software Reset Command 01h to exit OTP programming
12. Wait >= 10us
13. Power OFF VDD
14. Power OFF VPP

B1 h OTPWR (OTP Write)
The steps for OTP Emulation (P[7:0]=2Eh):
1. Send OTP write Command B1h
2. Send Data 2Eh for OTP Emulation
3. Send two OTP bytes through MCU interface
4. Hardware reset or Send Command 01h Software Reset to exit OTP programming
Note
(1)
The contrast of color A, B, C are set by command BAh, BBh and BCh respectively. The adjusted
contrast values (i.e. after trimming) are subject to the boundary and resolution in BAh, BBh and BCh.
(2)
Use the following command sequence to set DCLK frequency to 9kFz :Command FDh, Data B3h,
Command D2h, Data 67h.
(3)
If External CL clock is used, the CL frequency should be set > 200kHz and set DCLK = 9kHz
(7~11kHz)

Default S/W Reset N/A
H/W Reset N/A

9.3.33 OTP MCU Read (B2h)
B2 h OTPRD ( OTP MCU Read)
Command 0 1 ↑ 1 0 1 1 0 0 1 0 B2
2nd Parameter 1 ↑ 1 CB3 CB2 CB1 CB0 CA3 CA2 CA1 CA0 xx
3rd Parameter 1 ↑ 1 ID3 ID2 ID1 ID0 CC3 CC2 CC1 CC0 xx
This command is used to transfer data from OTP to MCU.

Description
The next 2 bytes read parameters are OTP contents burned through B1h.
The D/C# pin is set to high for reading parameters.

Default
H/W Reset N/A

9.3.34 Function Selection (B3h)
B3 h FUSEL (Function Selection)

Command 0 1 ↑ 1 0 1 1 0 0 1 1 B3
Parameter 1 1 ↑ 0 A6 0 0 0 0 A1 A0 02..03
This command is used to set the internal VDD Regulator.
• Bit A0 – Internal VDD Regulator Selection

‘0’ = Select external VDD
‘1’ = Enable internal VDD regulator [reset]
Description • Bit A1 – High Power Protection Selection

‘0’ = Disable high power protection
‘1’ = Enable high power protection [reset]
• Bit A6 – IREF Selection

‘0’ = Select external IREF [reset]
‘1’ = Enable internal IREF

Default
H/W Reset A0=1b, A1=1b, A6=0b

9.3.35 Linear Gamma Look Up Table (B9h)
B9 h LINGLUT (Linear Gamma Look Up Table)
Command 0 1 ↑ 1 0 1 1 1 0 0 1 B9
Parameter no parameter
Reset built in Linear Gray Scale table
GS0 = Gamma Setting 0;

GS1 = Gamma Setting 2
:
GS31 = Gamma Setting 62
Description
:

Default
H/W Reset Linear Gamma Look UP Table

9.3.36 Set Contrast For Color A, B &C (BAh)
BA h ISEGABC( Set Contrast For Color A, B & C )
Command 0 1 ↑ 1 0 1 1 1 0 1 0 BA
Parameter 1 1 ↑ A7 A6 A5 A4 A3 A2 A1 A0 xx
Command 0 1 ↑ 1 0 1 1 1 0 1 1 BB
Parameter 1 1 ↑ B7 B6 B5 B4 B3 B2 B1 B0 xx
Command 0 1 ↑ 1 0 1 1 1 1 0 0 BC
Parameter 1 1 ↑ C7 C6 C5 C4 C3 C2 C1 C0 xx
A[7:0] : Set contrast for all color "A" segment (Pins :SA0 – SA127)
B[7:0] : Set contrast for all color "B" segment (Pins :SB0 – SB127)
C[7:0] : Set contrast for all color "C" segment (Pins :SC0 – SC127)
Note
(1)
All six bytes (BAh A[7:0], BBh B[7:0] and BCh C[7:0]) must be inputted together. For example: the
original value is like that
Original value
BAh A[7:0]: 80h
Description
BBh B[7:0]: 80h
BCh C[7:0]: 80h
If once wanted to change the value of BBh B[7:0] to 75h, then all the following 6 bytes must be
inputted as:
BAh (command), 80h (data),
BBh (command), 75h (data),
BCh (command), 80h (data).
Otherwise, the changes may not be activated.

H/W Reset A[7:0]=128d (80h)
Default
B[7:0]=128d (80h)
C[7:0]=128d (80h)

9.3.37 Set First Pre-Charge Voltage (BDh)
BD h VPSET (Set First Pre-Charge Voltage)
Command 0 1 ↑ 1 0 1 1 1 1 0 1 BD
1st Parameter 1 1 ↑ xx xx xx V4 V3 V2 V1 V0 xx
This command is used to set the first pre-charge voltage for the three colors as follow:
V[4:0] Voltage pre-charge for three colors
00000 0.2* VCC
Description
: :
11111 0.6* VCC

Default
H/W Reset V[4:0]=10111b

9.3.38 Gamma Look Up Table (BEh)
BE h GLUT (Gamma Look Up Table )
Command 0 1 ↑ 1 0 1 1 1 1 1 0 BE
1st Parameter 1 1 ↑ xx A016 A015 A014 A013 A012 A011 A010 xx
: 1 1 ↑ xx Ann6 Ann5 Ann4 Ann3 Ann2 Ann1 Ann0 xx
nd
32 Parameter 1 1 ↑ xx A326 A325 A324 A323 A322 A321 A320 xx
33rd Parameter 1 1 ↑ xx B016 B015 B014 B013 B012 B011 B010 xx
: 1 1 ↑ xx Bnn6 Bnn5 Bnn4 Bnn3 Bnn2 Bnn1 Bnn0 xx
th
64 Parameter 1 1 ↑ xx B326 B325 B324 B323 B322 B321 B320 xx
65th Parameter 1 1 ↑ xx C016 C015 C014 C013 C012 C011 C010 xx
: 1 1 ↑ xx Cnn6 Cnn5 Cnn4 Cnn3 Cnn2 Cnn1 Cnn0 xx
th
96 Parameter 1 1 ↑ xx C326 C325 C324 C323 C322 C321 C320 xx
This command is used to define three programmable gamma look-up tables for color A, B and C
respectively in terms of Gray Scale (GS). Except GS0, which is zero as it has no pre-charge and
current drive, each entry GS level is programmed in the Gamma Setting. The larger value of
Gamma Setting, the brighter is the OLED pixel when it’s turned ON.
Following the command BEh, the Gamma Setting for GS1, GS3, GS5, …, GS61, GS63 should be
set one by one in sequence for color A, B and C: (1)
A01[6:0] / B01[6:0] / C01[6:0]: Gamma Setting for GS1 of color A / B / C respectively ;

:
A31[6:0] / B31[6:0] / C31[6:0]: Gamma Setting for GS61 of color A / B / C respectively.
A32[6:0] / B32[6:0] / C32[6:0]: Gamma Setting for GS63 of color A / B / C respectively.
The Gamma Setting of GS2, GS4, GS6,…, GS58, GS60, GS62 are derived automatically by the
Description
driver based on this formula:
GSn = (GSn-1 + GSn+1) / 2 , for n= 2,4,…,60,62 and division remainder is truncated.
The gray scale is defined in incremental way, with reference to the length of previous table entry:
Setting of GS1 must > 0
:

BE h GLUT (Gamma Look Up Table )
The following is an example of setting the GLUT:
1. Define the odd entry pulse widths that comply with the above conditions:
Gray Scale Gamma Setting

GS1 3
GS3 7
GS5 23
: :
GS59 108
GS61 115
GS63 127
2. Enter the Gamma Setting from GS1, GS3, GS5,…, GS59, GS61, GS63 one by one in sequence
following the command BEh during the software initialization.
Then the driver automatically derives the Gamma setting of the even entry : GS2, GS4, …,GS60,
GS62 with the previous mentioned formula:
Gray Scale Formula Gamma Setting

GS2 (GS1+GS3)/2=(3+7)/2=5 5
GS4 (GS3+GS5)/2=(7+23)/2=15 15
: :
GS60 (GS59+GS61)/2=(108+115)/2=111.5 111
GS62 (GS61+GS63)/2=(115+127)/2=121 121
Note
(1]
Input 1d for Gamma Setting 1, 2d for Gamma setting 2, ... ,127d for Gamma Setting127
The setting of Gray Scale entry can perform Gamma correction on OLED panel display.
Normally, it is desired that the brightness response of the panel is linearly proportional to the
image data value in display data RAM. However, the OLED panel is somehow responded in non-
linear way. Appropriate Gray Scale table setting like example below can compensate this effect.
Figure 9-12 : Example of Gamma correction by Gamma Look Up table setting

Default
H/W Reset Linear GLUT (B9h)

9.3.39 Set Display Offset (C8h)
C8 h SETDO (Set Display Offset)
Command 0 1 ↑ 1 1 0 0 1 0 0 0 C8
1st Parameter 1 1 ↑ A7 A6 A5 A4 A3 A2 A1 A0 00..9F (1)
This command specifies the mapping of display start line (it is assumed that COM0 is the display start
line, display start line register equals to 0) to one of COM0-159. For example, to move the COM16
towards the COM0 direction for 16 lines, A[7:0] should be given by 00010000. The figure below shows
an example of this command. In there, “Row” means the graphic display data RAM row.
Figure 9-13 : Example of Set Display Start Line with no Remap (i.e. Command 36h bit A7=0b)
a b c Case
160 96 96 MUX ratio (CAh)
0 0 32 Display offset (C8h A[7:0])
COM0 Row0 Row0 Row32
: : : :
COM64 Row64 Row64 -
COM65 Row65 Row65 -
COM66 Row66 Row66 -
: : : :
COM93 Row93 Row93 -
COM94 Row94 Row94 -
COM95 Row95 Row95 -
Description COM96 Row96 - -
COM97 Row97 - -
COM98 Row98 - -
: : : :
COM124 Row124 - -
COM125 Row125 - -
COM126 Row126 - -
COM127 Row127 - Row0
: : : :
Display
example
(a) (c) (d) (GDDARAM)
Note
(1)
A[7:0] + MUX ratio must be less than or equal to 160d. That means when MUX ratio is set to 160,
Restriction
this command is not recommend to use.
(2)
MUX ratio can be set by command CAh,

Default
H/W Reset A[7:0]=00h

9.3.40 Horizontal Scrolling (C9h)
C9 h HORSCR (Horizontal Scrolling)
Command 0 1 ↑ 1 1 0 0 1 0 0 1 C9
1st Parameter 1 1 ↑ xx A6 A5 A4 A3 A2 A1 A0 00..7F
This command performs the horizontal scrolling through mapping one of the columns in the graphic
display data RAM to SEG0.
A[6:0] Number of column in horizontal scroll

00h No horizontal scroll
01h RAM column address 1 maps to SEG0
: :
7Fh Last RAM column address 7F maps to SEG0
The figure below shows examples of this command. In there, “Col” means the graphic display data
RAM column.
A[6:0] SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 ... SEG122 SEG123 SEG124 SEG125 SEG126 SEG127
Description 0 Col 0 Col 1 Col 2 Col 3 Col 4 Col 5 Col 6 Col 7 ... Col 122 Col 123 Col 124 Col 125 Col 126 Col 127
2 Col 2 Col 3 Col 4 Col 5 Col 6 Col 7 Col 8 Col 9 ... Col 124 Col 125 Col 126 Col 127 Col 0 Col 1
The following code shows example of horizontal scrolling towards SEG0:
for n = 1 to 127
Command C9h \\ Horizontal Scrolling command
Data n \\ RAM column address n maps to SEG0
Insert time interval between each scroll step
end

Default
H/W Reset A[6:0]=00h

9.3.41 Set MUX ratio (CAh)
CA h SETMUX (Set MUX ratio)
Command 0 1 ↑ 1 1 0 0 1 0 1 0 CA
1st Parameter 1 1 ↑ A7 A6 A5 A4 A3 A2 A1 A0 0F..9F
Set MUX ratio to N+1 MUX
Description N = A[7:0] from 15d to 159d (i.e.16MUX -160 MUX)

A[7:0] from 00d to 14d are invalid entry

Default
H/W Reset A[7:0]=9Fh (i.e. 160MUX)

9.3.42 Set Phase Length (CDh)
CD h PHLEN (Set Phase Length )
Command 0 1 ↑ 1 1 0 0 1 1 0 1 CD
1st Parameter 1 1 ↑ A7 A6 A5 A4 A3 A2 A1 A0 00..FF
This command is used to set the OLED driving waveform length in phase 1 and phase 2.
The A[3:0] defines the Phase 1 period of 5~31 DCLK clocks as follow:
A[3:0] Phase 1 period
0000 invalid
0001 invalid
0010 5 DCLKs
0011 7 DCLKs
0100 9 DCLKs [reset]
: :
1111 31 DCLKs
The A[7:4] defines the Phase 2 period of 3~15 DCLK clocks as follow:
Description
A[7:4] Phase 2 period
0000 invalid
0001 invalid
0010 invalid
0011 3 DCLKs
0100 4 DCLKs
: :
0111 7 DCLKs[reset]
: :
1111 15 DCLKs
Refer to section 8.7 for details of phase 1 & phase 2.

Default
H/W Reset A[3:0]=4h, A[7:4]=7h

9.3.43 Set Second Precharge Period (CEh)
CE h SECPLEN (Set Second Precharge Period )
Command 0 1 ↑ 1 1 0 0 1 1 1 0 CE
1st Parameter 1 1 ↑ xx xx xx xx A3 A2 A1 A0 xx
This command sets the second precharge period as follow:
A[3:0] second Precharge Period

0000 0 DCLK
0001 1 DCLK
0010 2 DCLKs
Description : :
0111 7 DCLKs [reset]
: :
1111 15 DCLKs
Refer to section 8.7 for details of second precharge.

Default
H/W Reset A[3:0]=0111

9.3.44 Set Second Precharge speed (CFh)
CF h SSPS (Set Second Precharge speed )
Command 0 1 ↑ 1 1 0 0 1 1 1 1 CF
1st Parameter 1 1 ↑ xx xx xx xx xx 0 A1 A0 xx
Set Second Precharge speed
A[1:0]= 00b, Second Pre-charge speed =slowest

A[1:0]= 01b, Second Pre-charge speed =slow
A[1:0]= 10b, Second Pre-charge speed =normal [reset]
Description
A[1:0]= 11b, Second Pre-charge speed =Fast
Refer to section 8.7 for details of second precharge.

Default
H/W Reset A[1:0]= 10b

9.3.45 Set Display Clock Divider / Oscillator Frequency (D2h)
D2 h SDCOSCF (Set Display Clock Divider / Oscillator Frequency)
Command 0 1 ↑ 1 1 0 1 0 0 1 0 D2
1st Parameter 1 1 ↑ A7 A6 A5 A4 A3 A2 A1 A0 xx
A[3:0] Display Clock (DCLK) Divider
A[3:0] Divider
0000 divide by 1
0001 divide by 2
0010 divide by 4
0011 divide by 8
0100 divide by 16
0101 divide by 32
0110 divide by 64
0111 divide by 128
1000 divide by 256
Description 1001 divide by 512
1010 divide by 1024
>=1011 invalid
DCLK is generated from CLK divided by Divider
A[7:4] FOSC frequency

FOSC stands for frequency value of the internal oscillator
Frequency increases as setting value increases
Refer to section 8.5 for details.

Default
H/W Reset A[7:4] =1100b, A[3:0]=0000b

9.3.46 Set VCOMH (D3h)
D3 h SETVCOMH (Set VCOMH )
Command 0 1 ↑ 1 1 0 1 0 0 1 1 D3
1st Parameter 1 1 ↑ 0 0 0 0 0 A2 A1 A0 00..07
This command is used to set the VCOMH as followed:
A[2:0] VCOMH
000 0.72*VCC
001 0.74*VCC
010 0.76*VCC
Description
011 0.78*VCC
100 0.80*VCC [reset]
101 0.82*VCC
110 0.84*VCC
111 0.86*VCC

Default
H/W Reset A[2:0]=100b

9.3.47 GPIO (D7h)
D7 h GPIO (General Purpose IO )
Command 0 1 ↑ 1 1 0 1 0 1 1 1 D7
1st Parameter 1 1 ↑ xx xx xx xx D3 D2 D1 D0 xx
This command is used to enable or disable the GPIO0 pin and GPIO1 pin.
For GPIO0 pin:

D[1:0] Description
00 GPIO0 pin high impedance (HiZ). Input disabled (always read as low) [reset]
01 GPIO0 pin HiZ, Input enabled
10 GPIO0 pin output LOW
11 GPIO0 pin output HIGH
Description
For GPIO1 pin:
D[3:2] Description
00 GPIO1 pin high impedance (HiZ). Input disabled (always read as low) [reset]
01 GPIO1 pin HiZ, Input enabled
10 GPIO1 pin output LOW
11 GPIO1 pin output HIGH
Note
(1)
Input disabled means floating input is allowed.

Default
H/W Reset D[3:2]=00, D[1:0]= 00

9.3.48 Command Lock (FDh)
FD h CMDLCK (Command Lock)

Command 0 1 ↑ 1 1 1 1 1 1 0 1 FD
Parameter 1 1 ↑ A7 A6 A5 A4 A3 A2 A1 A0 xx
This command is design to prevent change of command set value. This helps to prevent
accidental/unintentional access to change important or factory configuration during normal
operation. Level of command lock can be to lock only basic commands (00h to 52h, DAh), and also
lock supplementary commands (usually for factory setting) (B1h to D7h, FDh). Please refer to section
9.1 and 9.2 for the list of basic commands and supplementary commands.
A[7:0] Description
12h Unlock basic commands. Basic command can be accessed.
Lock all commands. All commands can not be accessed, except command:
16h
FDh ->12h can be used to unlock basic command.
Lock all supplementary command. In this state, for supplementary command
B0h
access, only FDh ->16hcommand can be sent.
Unlock supplementary commands. All supplementary commands can be
B3h
accessed.
other values Invalid
Please see the below flow chart for detailed operation:
Lock state
All commands are locked,
except “unlock command”:
Description FDh ->12h
FDh
12h
Return to the
FDh previous state FDh
16h 16h
Semi-lock state Unlock state
Semi-lock state Unlock state

FDh
Basic Commands accessible. B0h
Supplementary commands are All Commands accessible
locked, except lock command:
FDh ->16h or FDh-> B3h FDh
RESET B3h
Default Status Default Value

H/W Reset Semi-lock state

10 MAXIMUM RATINGS
Table 10-1 : Maximum Ratings
(Voltage Reference to VSS)
Symbol Parameter Value Unit
VDD -0.5 to 2.75 V
VCC -0.5 to 22.0 V
Supply Voltage
VDDIO -0.5 to VCI V
VCI -0.3 to 4.0 V
VSEG SEG output voltage 0 to VCC V
VCOM COM output voltage 0 to 0.9*VCC V
Vin Input voltage Vss-0.3 to VDDIO+0.3 V
TA Operating Temperature -40 to +85 ºC
Tstg Storage Temperature Range -65 to +150 ºC
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the
Electrical Characteristics tables or Pin Description.
*This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device
is not radiation protected.

11 DC CHARACTERISTICS
Conditions (Unless otherwise specified)

Voltage referenced to VSS, VDDIO = 2.8V, VDD = 2.4V ~ 2.6V, VCI = 2.8V, TA = 25°C
Table 11-1 : DC Characteristics

Symbol Parameter Test Condition Min Typ Max Unit
VCC Operating Voltage - 10 - 21 V
VDD Logic Supply Voltage - 2.4 - 2.6 V
VCI Low voltage power supply - 2.4 - 3.5 V
VDDIO Power Supply for I/O pins - 1.6 - VCI V
VOH High Logic Output Level Iout =100uA 0.9*VDDIO - VDDIO V
VOL Low Logic Output Level Iout =100uA 0 - 0.1*VDDIO V
VIH High Logic Input Level - 0.8*VDDIO - VDDIO V
VIL Low Logic Input Level - 0 - 0.2*VDDIO V
VCI = VDDIO =2.8V, VCC =16V - - 10 uA
ISLP_VDD VDD Sleep mode Current VDD(external) = 2.5V, Display OFF,
No panel attached
VCI = VDDIO =2.8V, - - 10 uA
External VDD = 2.5V
VCC =16V
ISLP_VDDIO VDDIO Sleep mode Current
Display OFF, - - 10 uA
Internal VDD
No panel attached
VCI = VDDIO =2.8V, - - 10 uA
External VDD = 2.5V
VCC =16V
ISLP_VCC VCC Sleep mode Current
Display OFF, - - 10 uA
Internal VDD
No panel attached
- - 10 uA
External VDD = 2.5V
VCI = VDDIO =2.8V,
VCC =16V Enable Internal VDD - - 70 uA
ISLP_VCI VCI Sleep mode Current
Display OFF, during Sleep mode
No panel attached Disable Internal VDD - - 10 uA
during Sleep mode
VCI = VDDIO =2.8V, VCC = 16V, - 650 720 uA
IDD VDD Supply Current External VDD = 2.5V, Display ON,
No panel attached, contrast = FF
VCI = VDDIO =, 2.8V, - 0.5 10 uA
External VDD = 2.5V
VCC = 16, Display ON,
IDDIO VDDIO Supply Current
No panel attached, - 0.5 10 uA
Internal VDD
contrast = FF
VCI = VDDIO =, 2.8V, - -15 -9 uA
External VDD = 2.5V
ICI VCI Supply Current
No panel attached, - 670 750 uA
Internal VDD
contrast = FF
VCI = VDDIO =, 2.8V, - 1.65 1.9 mA
External VDD = 2.5V
ICC VCC Supply Current
No panel attached, - 1.65 1.9 mA
Internal VDD
contrast = FF
Contrast = FFh , GS63 = Setting 127 - 230 250 uA
Segment Output Current
ISEG Setting Contrast = 7Fh, GS63 = Setting 127 - 120 - uA
VCC = 21 IREF = 13.5uA
Contrast = 3Fh, GS31 = Setting 63 - 62 - uA
Segment (SA, SB, SC) output Dev = (ISn – IMID)/IMID n=A -3 - 3 %
current uniformity IMID = (IMAX + IMIN)/2 -3 - 3
Dev n=B
(contrast = FF) ISn = Segment n current . e.g. For n=A,
then ISn = ISA = SA current n=C -3 - 3
Adj Dev = (ISn[m]-ISn[m+1]) / (ISn [m]+ n=A -2 - 2 %
Adjacent pin output current ISn [m+1]) -2 - 2
Adj. Dev n=B
uniformity (contrast = FF) e.g. For n=A, m=3, then ISn[m]= ISA[3]
= SA[3] current n=C -2 - 2
Segment output reference 11.0 13.5 14.0 uA
IREF -
current

12 AC CHARACTERISTICS
Conditions (Unless otherwise specified):

Voltage referenced to VSS
VDD = 2.4V to 2.6V
VDDIO = 2.8V
VCI = 2.8V
TA = 25°C
Table 12-1 : AC Characteristics

Symbol Parameter Test Condition Min Typ Max Unit
FOSC (1) Oscillation Frequency of Display VCI = 2.8V 1.28 1.43 1.6 MHz
Timing Generator
FFRM Frame Frequency for 160 MUX 128x160 Graphic Display Mode, - FOSC * 1/(D*K*160) - Hz
(2)
Mode Display ON, Internal Oscillator Enabled
tRES Reset low pulse width (RES#) - 2000 - - ns
Note
(1)
FOSC stands for the frequency value of the internal oscillator and the value is measured when command D2h A[7:4] is
in default value.
(2)
D: divide ratio set by command D2h A[3:0]
K: Phase 1 period +Phase 2 period + 75

Table 12-2 : 6800-Series MCU Parallel Interface Timing Characteristics
(VDD - VSS = 2.4 to 2.6V, VDDIO=1.6V, VCI = 2.8V, TA = 25°C)

Symbol Parameter Min Typ Max Unit
tCYCLE Clock Cycle Time 300 - - ns
tAS Address Setup Time 10 - - ns
tAH Address Hold Time 0 - - ns
tDSW Write Data Setup Time 40 - - ns

tDHW Write Data Hold Time 7 - - ns
tDHR Read Data Hold Time 20 - - ns
tOH Output Disable Time - - 70 ns

tACC Access Time - - 140 ns
Chip Select Low Pulse Width (read) 120
PWCSL - - ns
Chip Select Low Pulse Width (write) 60
Chip Select High Pulse Width (read) 60
PWCSH - - ns
Chip Select High Pulse Width (write) 60
tR Rise Time - - 15 ns
tF Fall Time - - 15 ns
Figure 12-1 : 6800-series MCU parallel interface characteristics
D/C#
tAS
tAH
R/W#
tCYCLE
PWCSH
PWCSL
CS#
tR
tF tDHW
tDSW
D[17:0] (1)
(WRITE) Valid Data
tACC tDHR
D[17:0] (1)
(READ) Valid Data
tOH
Note
(1)
when 8 bit used: D[7:0] instead; when 16 bit used: D[15:0] instead; when 18 bit used: D[17:0] instead.

Table 12-3 : 8080-Series MCU Parallel Interface Timing Characteristics

tCYCLE Clock Cycle Time 300 - - ns
tDHR Read Data Hold Time 20 - - ns
tOH Output Disable Time - - 70 ns
tACC Access Time - - 140 ns
tPWLR Read Low Time 150 - - ns
tPWLW Write Low Time 60 - - ns
tPWHR Read High Time 60 - - ns
tPWHW Write High Time 60 - - ns
tCS Chip select setup time 0 - - ns
tCSH Chip select hold time to read signal 0 - - ns
tCSF Chip select hold time 20 - - ns
Figure 12-2 : 8080-series MCU parallel interface characteristics
Write cycle
CS#
tCS tCSF
D/C#
tAS tAH
tF tR
tCYCLE
WR# tPWLW tPWHW
tDSW tDHW
(1)
D[17:0]
Read cycle
CS# tCSH
tCS
D/C#
tAS tAH
tF tR
tCYCLE
RD# tPWLR tPWHR
tACC tDHR
D[17:0] (1)
tOH
Note
(1)
when 8 bit used: D[7:0] instead; when 16 bit used: [15:0] instead; when 18 bit used: D[17:0] instead.

Table 12-4 : Serial Interface Timing Characteristics (4-wire SPI)

tcycle Clock Cycle Time 50 - - ns
tCSS Chip Select Setup Time 20 - - ns
tCSH Chip Select Hold Time 10 - - ns
tCLKL Clock Low Time 20 - - ns
tCLKH Clock High Time 20 - - ns
Figure 12-3 : Serial interface characteristics (4-wire SPI)
D/C#
t AS t AH
t CSS t CSH
CS#
t cycl
t CLKL e tCLKH
SCLK(R/W# (WR#))
tF tR
t DSW t DHW
SDIN(D0) Valid Data
CS#
SCLK(R/W# (WR#))
SDIN(D0) D7 D6 D5 D4 D3 D2 D1 D0

Table 12-5 : Serial Interface Timing Characteristics (3-wire SPI)

tcycle Clock Cycle Time 50 - - ns
tCSS Chip Select Setup Time 20 - - ns
tCSH Chip Select Hold Time 10 - - ns
tCLKL Clock Low Time 20 - - ns
tCLKH Clock High Time 20 - - ns
Figure 12-4 : Serial interface characteristics (3-wire SPI)
t CSS t CSH
CS#
t CYCLE
tCLKH
t CLKL
SCLK
(R/W# (WR#)) t F tR
t DSW t
t2
SDIN Valid Data DHW
(D0)
CS#
SCLK
(R/W# (WR#))
SDIN D/C# D7 D6 D5 D4 D3 D2 D1 D0
(D0)

13 APPLICATION EXAMPLE
Figure 13-1 : SSD1355 application example for 18-bit 6800-parallel interface mode (Internal regulated VDD)
The configuration for 18-bit 6800-parallel interface mode, externally VCC is shown in the following diagram:
(VCI = 3.3V (VCI must be > 2.6V), Internal regulated VDD = 2.5V, VDDIO = 1.8V, external VCC = 18V, IREF =
13.5uA, BS[3:2] are set to 11b through command 36h)
Color OLED Panel
128RGBx160
COM158
COM159
COM0
SA127
COM1
SB127
SC127
:
:
:
:
:
:
:
:
:
:
:
:
:
SA0
SB0
SC0
SSD1355Z BGGND
D[17:0]
GPIO0
GPIO1
VCOMH
R/W#
VDDIO
RES#
D/C#
VSL
VLSS
CLS
CS#
BS1
BS0
VDD
VCC
IREF
VPP
VSS
VCI
CL
TE
E
R1
C1
C2
C3
C4a
C4b
C5
R2 D1 D2
VDDIO VCI
E
D/C#
R/W#
RES#
CS#
D[17:0]
VCC V SS
[GND]
Voltage at IREF = VCC – 6V. For VCC = 18V, IREF = 13.5uA:

R1 = (Voltage at IREF - VSS) / IREF
= (18-6) / 13.5u
= 880KΩ
R2 = 50Ω, 1/8W (1)
D1 ~ D2: Vth=0.7V, 1N4148 (1)
C1 ~ C3: 1uF, C4a, C5: 4.7uF, C4b: 0.1uF (1)
Note
(1)
The values are recommended value. Select appropriate value against module application.

14 PACKAGE INFORMATION
14.1 SSD1355U2R1 Detail Dimension
Figure 14-1 : SSD1355U2R1 Detail Dimension
2
5U
35
D1
SS
42 1

Contact Side
Plating: Sn
Contact Side
Plating: Sn

3
U
55
13
D
S
S

Contact Side
Plating: Sn
Contact Side
Plating: Sn

LJ
96
6
-0
U
39
55
19
A
13
D
S
S

Contact Side
Plating: Sn
Contact Side
Plating: Sn

Solomon Systech reserves the right to make changes without notice to any products herein. Solomon Systech makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any, and all, liability, including without
limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters,
including “Typical” must be validated for each customer application by the customer’s technical experts. Solomon Systech does not con-
vey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur.
Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the
part.
All Solomon Systech Products complied with six (6) hazardous substances limitation requirement per European Union (EU) “Restriction of
Hazardous Substance (RoHS) Directive (2002/95/EC)” and China standard “电子信息产品污染控制标识要求 (SJ/T11364-2006)” with
control Marking Symbol . Hazardous Substances test report is available upon requested.
http://www.solomon-systech.comW

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SOLOMON SYSTECH

SEMICONDUCTOR TECHNICAL DATA

Solomon Systech Oct 2007 P 2/111 Rev 1.2 SSD1355

SSD1355 Rev 1.2 P 3/111 Oct 2007 Solomon Systech

Solomon Systech Oct 2007 P 4/111 Rev 1.2 SSD1355

SSD1355 Rev 1.2 P 5/111 Oct 2007 Solomon Systech

Solomon Systech Oct 2007 P 6/111 Rev 1.2 SSD1355

SSD1355 Rev 1.2 P 7/111 Oct 2007 Solomon Systech

Figure 4-1 Block Diagram

Gray Scale Decoder

Solomon Systech Oct 2007 P 8/111 Rev 1.2 SSD1355

Die Size 10.852mm x 1.65mm

SSD1355 Rev 1.2 P 9/111 Oct 2007 Solomon Systech

Solomon Systech Oct 2007 P 10/111 Rev 1.2 SSD1355

SSD1355 Rev 1.2 P 11/111 Oct 2007 Solomon Systech

6.1 SSD1355U2R1 Pin Assignment

Figure 6-1: SSD1355U2R1 Pin Assignment

Solomon Systech Oct 2007 P 12/111 Rev 1.2 SSD1355

SSD1355 Rev 1.2 P 13/111 Oct 2007 Solomon Systech

Figure 6-2: SSD1355U3R1 Pin Assignment

SSD1355 Rev 1.2 P 15/111 Oct 2007 Solomon Systech

Solomon Systech Oct 2007 P 16/111 Rev 1.2 SSD1355

SSD1355 Rev 1.2 P 19/111 Oct 2007 Solomon Systech

Solomon Systech Oct 2007 P 20/111 Rev 1.2 SSD1355

Table 7-1 : SSD1355 Pin Description

Refer to Section 8.11 for details.

VCI P Low voltage power supply

Refer to Section 8.11 for details.

VPP P Power supply for programming OTP.

VSS P Ground pin

VLSS P Analog system ground pin

VCOMH P COM signal deselected voltage level.

BGGND P It should be connected to Ground.

GPIO0 I/O Refer to section 9.3.47 GPIO (D7h).

GPIO1 I/O Refer to section 9.3.47 GPIO (D7h).

VSL P This is segment voltage reference pin.

SSD1355 Rev 1.2 P 21/111 Oct 2007 Solomon Systech

IREF I This pin is the segment output current reference pin.

IREF can be supplied externally or regulated internally.

CLS I Internal clock selection pin.

RES# I This pin is reset signal input.

When the pin is pulled LOW, initialization of the chip is executed.

D/C# I This pin is Data/Command control pin connecting to the MCU.

Solomon Systech Oct 2007 P 22/111 Rev 1.2 SSD1355

SSD1355 Rev 1.2 P 23/111 Oct 2007 Solomon Systech

8.1 MCU Interface

Table 8-2 : Data bus selection modes

8.1.1 MCU Parallel 6800-series Interface

Table 8-3 : Control pins of 6800 interface

Function E R/W# CS# D/C#

Solomon Systech Oct 2007 P 24/111 Rev 1.2 SSD1355

Databus N n n+1 n+2

8.1.2 MCU Parallel 8080-series Interface

Figure 8-2 : Example of Write procedure in 8080 parallel interface mode

Figure 8-3 : Example of Read procedure in 8080 parallel interface mode

SSD1355 Rev 1.2 P 25/111 Oct 2007 Solomon Systech

Function RD# WR# CS# D/C#

Databus N n n+1 n+2

8.1.3 MCU Serial Interface (4-wire SPI)