Latitude 3330 12275-1 - AUSTIN13 - CHIEFRIVER - MB - A00 - 0226

5 4 3 2 1
Austin 13" Schematics Document

Vinafix.com
D
Ivy Bridge ULV D
Panther Point
2013-02-26
C
REV : A00 C
DY : None Installed
B B
A <Core Design> A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
Size Document Number Rev
A3
Austin 13 A00
Date: Tuesday, February 26, 2013 Sheet 1 of 106
5 4 3 2 1
5 4 3 2 1
CHARGER
ISL88731CHRTZ 40
Austin 13 Block Diagram Project Code: 91.4LA01.001 INPUTS

AD+
OUTPUTS
BT+
PCB P/N : 12275 SYSTEM DC/DC
Revision : A00 TPS51125RGER 41
Vinafix.com Intel CPU

INPUTS OUTPUTS
5V_PWR_2
+3.3V_ALW2
DCBATOUT +5V_ALW
D
Ivy Bridge DDRIII 1600MHz Channel A DDRIII- Slot A +3.3V_ALW
+15V_ALW
D
17W 1600MHz 14
CPU DC/DC
VT1318+VT1323 42,43
DDRIII 1600MHz Channel B DDRIII- Slot B INPUTS OUTPUTS
1600MHz 15 +5V_ALW VCC_CORE
BGA1023 GFX DC/DC

VT1318+VT1323 44
4,5,6,7,8,9,10
INPUTS OUTPUTS
+5V_ALW VCC_GFXCORE
FDIx4x2 DMIx4 SYSTEM DC/DC

VT386+RT8085
HDMI board
INPUTS OUTPUTS
TMDS
LAN +5V_ALW +1.05V_RUN_VTT
HDMI 51
Intel PCIE x 1
+3.3V_ALW +1.05V_M 45
Intel Lewisville
USB PowerShare PCH
USB 2.0 + Power share 82579LM 31 SYSTEM DC/DC
PERICOM USB2.0 x 1
CONN
PI5USB1457AZAE
Panther Point
RT8207
C
Daughter Board C
BGA989 PCIE x 1 USB2.0 x 1

Mini-Card INPUTS OUTPUTS
LVDS +1.35V_MEM
LCD 49 802.11a/b/g/n RJ45 DCBATOUT +0.675_DDR_VTT
BT V4.0 combo +V_DDR_REF 46
HM77 26
SYSTEM DC/DC
Right side RT8068A 47
Connector CardReader USB3.0 x 1
14 USB 2.0/1.1 ports INPUTS OUTPUTS
SD/SDHC/SDXC/SD UHS-I O2 PCIE x 1
+3.3V_ALW +1.8V_RUN
4 USB 3.0 ports USB 3.0
MMC/MMC+, MS/MS Pro OZ600FJ0 32
74 High Definition Audio
USB2.0 x 1 SYSTEM DC/DC
6 SATA ports APL5930 47
8 PCIE ports INPUTS OUTPUTS
LPC I/F Right side +3.3V_ALW +1.5V_RUN
USB3.0 x 1
ACPI 4.0a SYSTEM DC/DC
Mini-Card 48
SATA GEN3 & USB2.0*1
USB 3.0 SY8037
Micro SIM
66 WWAN/MSATA INPUTS OUTPUTS
USB2.0 x 1
66 +5V_ALW +VCC_SA
INT 2 SATA GenIII x 1

HDD RGB CRT CRT
56 Combo Jack
B
INPUTSN.A OUTPUTS
26
B
SPI BUS HDA

Switches
Flash ROM Codec 2CH Speaker
60
INPUTS OUTPUTS
8MB IDT +1.35V_MEM +1.35V_CPU_VDDQ
92HD93 29 58 +5V_ALW
+3.3V_ALW
+5V_RUN
+3.3V_RUN
SPI BUS +1.05V_N +1.05V_RUN
Flash ROM USB2.0 x 1 +3.3V_ALW +3.3V_M
60 +3.3V_ALW +3.3V_ALW_PCH
4MB 17,18,19,20,21,22,23,24,25 Camera +5V_ALW +5V_ALW_PCH
Internal Digital MIC 49
PCB LAYER
INT1
FFS
ST L1:Top L5:GND
SMBUS LPC BUS L2:GND L6:Bottom
LNG3DM 51 L3:Signal
L4:Signal
LPC debug port
Thermal 71
SMSC BC Link KBC SIO Expander
FAN BC link
EMC4021 28
SMSC SMSC TPM
A MEC5055 27 ECE5048 78 A
JTAG AT97SC3204-X2A1D-AB
77
PS2 BC Link <Core Design>
Wistron Corporation
Touch Keyboard Int. KB 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
PAD69 controller (Backlight supported) 69
Title
EC1117 69 Block Diagram
Custom Austin 13 A00
5 4 3 2 1
A B C D E
PCH Strapping Chief River Schematic Checklist Rev.0_72 Sandy & Ivy Bridge Compatibility Chief River Schematic Checklist Rev.0_xx
Name Schematics Notes Pin Name Configuration Schematic Notes
SPKR The signal has a weak internal pull-down. Sandy Bridge + Ivy Bridge DDR3 VREF, M1 and M3 function are required.
Vinafix.com
If the signal is sampled high, this indicates that the system is strapped to the
"No Reboot" mode (Panther Point will disable the TCO Timer system reboot feature). DDR3 VREF
Ivy Bridge No change.
4 INIT3_3V# Weak internal pull-up. Leave as "No Connect". 4
INTVRMEN Integrated 1 V VRMs is enabled when high, External when low.
Connect DF_TVS signal of the PCH to PROC_SELECT# of the processor
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile. Sandy Bridge + Ivy Bridge through a 1K±5% series resistor. PROC_SELECT# also needs a 2.2K±5%
GNT2#/GPIO53 Mobile: Used as GPIO only PROC_SELECT# pull up resistor to PCH VccDFTERM rail.
GNT1#/GPIO51 Pull-up resistors are not required on these signals. &
If pull-ups are used, they should be tied to the Vcc3_3power rail. DF_TVS
DF_TVS DF_TVS needs to be pulled up to VccDFTERM power rail through 2.2 kOhms ±5% resistor.
HAD_DOCK_EN# This signal controls the external Intel HD Audio docking isolation logic. This is
/GPIO[33] an active-low-signal. When deasserted the external docking switch is in isolate mode. The POR for Ivy Bridge mobile parts is now 1.05 V. There is no
When asserted the external docking switch electrically connects the Intel HD Audio Sandy Bridge + Ivy Bridge longer a need for a separate VR for the processor at 1.0 V and
dock signals to the corresponding Panther Point signals. This signal can instead VCCIO_SEL the PCH at 1.05 V. A single VR may be shared for both.
be used as GPIO33.
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
GPIO15 Low (0) Sandy Bridge + Ivy Bridge VCCSA[0:1] are the select pin of VCCSA's power control.
Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality
High (1) VCCSA_VID[0:1]
Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality Ivy Bridge No change.
3 3
Power Plane Processor Strapping Chief River Schematic Checklist Rev.0_72
Configuration (Default value for each bit is Default POP
Power Plane Voltage Actice Status Description Pin Name Strap Description 1 unless specified otherwise) Value Value
CFG[2] PCI-Express Static 1: Normal Operation.

+5V_RUN 5V Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1 1
+3.3V_RUN 3.3V
+1.8V_RUN 1.8V Disabled - No Physical Display Port attached to
+1.5V_RUN 1.5V CFG[4] 1: Embedded DisplayPort.
+1.05V_RUN_VTT 1.05V S0 CPU Core Rail 1 1
+1.05V_M 1.05V Graphics Core Rail Enabled - An external Display Port device is
+VCC_SA 0.75V~0.9V 0: connectd to the EMBEDDED display Port
+VCC_CORE 0.3V to 1.3V
+VCC_GFXCORE 0 to 1.25V CFG[6:5] PCI-Express 11: 1x16 PCI Express
Port Bifurcation
10: 2 x8 - PCI Express
Straps 11 11
01: Reserved
00: 1x8, 2x4 PCI Express
2 2
+1.35V_MEM 1.5V S3
+0.675V_DDR_VTT 0.75V
USB Table PCIE Table SATA Table

BT+ 6V~14.1V Pair Device PCIE SATA
DCBATOUT 6V~14.1V
15V 0 USB0(Left side-HDMI/B) Lane Device Pair Device
+15V_ALW
+5V_ALW 5V All S states AC Brick Mode only 1 USB1(Right side-IO/B, for USB3.0)
3.3V 1 NC 0 HDD1
+3.3V_ALW 2 USB2(Right side-IO/B, for USB3.0)
2 WLAN 1 mSATA
3 NC
3 NC 2 NC
4 WLAN
+3.3V_LAN 3.3V WOL_EN Legacy WOL 4 NC 3 NC
5 WWAN
5 NC 4 NC
6 NC
+3.3V_ALW2 3.3V DSW, Sx ON for supporting 6 Card Reader 5 NC
Deep Sleep states 7 NC
7 Onboard LAN
8 NC
8 NC
RTC_AUX_S5 3.3V G3, Sx Powered by Li Coin Cell 9 NC
1 in G3 and +V3ALW in Sx 10 NC
<Core Design>
1
11 NC
Wistron Corporation
12 CAMERA 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
13 NC
Title
Table of Content
A3
Austin 13 A00
5 4 3 2 1
SSID = CPU
Layout Note:
Signal Routing Guideline:
Vinafix.com PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
D D
+1.05V_RUN_VTT
CPU1A 1 OF 9
G3 PEG_IRCOMP_R R401 1 2 24D9R2F-L-GP
PEG_ICOMPI
(19) DMI_TXN[3:0] PEG_ICOMPO G1
DMI_TXN0 M2 G4
DMI_TXN1 DMI_RX#0 PEG_RCOMPO
P6 DMI_RX#1
DMI_TXN2 P1
DMI_TXN3 DMI_RX#2
P10 DMI_RX#3 PEG_RX#0 H22
J21
Layout Note: (19) DMI_TXP[3:0]
DMI_TXP0 N3
PEG_RX#1
B22
DMI_TXP1 DMI_RX0 PEG_RX#2
DMI trace length 2000~8000mil P7 DMI_RX1 PEG_RX#3 D21
DMI
DMI_TXP2 P3 A19
DMI_TXP3 DMI_RX2 PEG_RX#4
P11 DMI_RX3 PEG_RX#5 D17
(19) DMI_RXN[3:0] PEG_RX#6 B14
DMI_RXN0 K1 D13
DMI_RXN1 DMI_TX#0 PEG_RX#7
M8 DMI_TX#1 PEG_RX#8 A11
DMI_RXN2 N4 B10
DMI_RXN3 DMI_TX#2 PEG_RX#9
R2 DMI_TX#3 PEG_RX#10 G8
(19) DMI_RXP[3:0] PEG_RX#11 A8
DMI_RXP0 K3 B6
DMI_RXP1 DMI_TX0 PEG_RX#12
M7 DMI_TX1 PEG_RX#13 H8
DMI_RXP2 P4 E5
DMI_RXP3 DMI_TX2 PEG_RX#14
T3 DMI_TX3 PEG_RX#15 K7
PEG_RX0 K22
PEG_RX1 K19
(19) FDI_TXN[7:0] PEG_RX2 C21
C FDI_TXN0
FDI_TXN1
U7
W11
FDI0_TX#0 PEG_RX3 D19
C19
C
FDI_TXN2 FDI0_TX#1 PEG_RX4
W1 FDI0_TX#2 PEG_RX5 D16
FDI_TXN3 AA6 C13
W6 D12
Layout Note: FDI_TXN5 V4
FDI1_TX#0 PEG_RX7
C11
FDI trace length 2000~6500mil
PCI EXPRESS -- GRAPHICS

Y2 FDI1_TX#2 PEG_RX9 C9
FDI_TXN7 AC9 F8
FDI1_TX#3 PEG_RX10
Intel(R) FDI
PEG_RX11 C8
(19) FDI_TXP[7:0] PEG_RX12 C5
FDI_TXP0 U6 H6
FDI_TXP1 FDI0_TX0 PEG_RX13
W10 FDI0_TX1 PEG_RX14 F6
FDI_TXP2 W3 K6
FDI_TXP3 FDI0_TX2 PEG_RX15
AA7 FDI0_TX3
FDI_TXP4 W7 G22
FDI_TXP5 FDI1_TX0 PEG_TX#0
T4 FDI1_TX1 PEG_TX#1 C23
FDI_TXP6 AA3 D23
FDI_TXP7 FDI1_TX2 PEG_TX#2
AC8 FDI1_TX3 PEG_TX#3 F21
PEG_TX#4 H19
FDI_FSYNC0 AA11 C17
(19) FDI_FSYNC0 FDI0_FSYNC PEG_TX#5
FDI_FSYNC1 AC12 K15
(19) FDI_FSYNC1 FDI1_FSYNC PEG_TX#6
PEG_TX#7 F17
FDI_INT U11 F14
(19) FDI_INT FDI_INT PEG_TX#8
PEG_TX#9 A15
FDI_LSYNC0 AA10 J14
(19) FDI_LSYNC0 FDI0_LSYNC PEG_TX#10
FDI_LSYNC1 AG8 H13
(19) FDI_LSYNC1 FDI1_LSYNC PEG_TX#11
PEG_TX#12 M10
PEG_TX#13 F10
PEG_TX#14 D9
J4
B +1.05V_RUN_VTT R402 1 2 24D9R2F-L-GP DP_COMP AF3 EDP_COMPIO
PEG_TX#15 B
AD2 EDP_ICOMPO PEG_TX0 F22
AG11 EDP_HPD# PEG_TX1 A23
PEG_TX2 D24
PEG_TX3 E21
AG4 G19
Layout Note: AF4
EDP_AUX# PEG_TX4
B18
EDP_AUX PEG_TX5
Signal Routing Guideline: PEG_TX6 K17
eDP
EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_TX7 G17
AC3 E14
EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils. AC4
EDP_TX#0 PEG_TX8
C15
EDP_TX#1 PEG_TX9
AE11 EDP_TX#2 PEG_TX10 K13
AE7 EDP_TX#3 PEG_TX11 G13
PEG_TX12 K10
AC1 EDP_TX0 PEG_TX13 G10
AA4 EDP_TX1 PEG_TX14 D8
AE10 EDP_TX2 PEG_TX15 K4
AE6 EDP_TX3
IVY-BRIDGE-GP-NF
71.00IVY.A0U
A <Core Design>
A
Wistron Corporation
Title
CPU(PCIE/DMI/FDI)
A3 A00
Austin 13
5 4 3 2 1
SSID = CPU +1.05V_RUN_VTT
RN501
XDP_TDI 1 8
XDP_TMS 2 7
XDP_TDO 3 6
4
XDP 5
Vinafix.com SRN51J-1-GP
RN502
D CPU1B 2 OF 9 XDP_TRST#
XDP_TCLK
1
2
4
3
D
J3 CLK_EXP_P CLK_EXP_P (20)
XDP
+1.05V_RUN_VTT BCLK CLK_EXP_N SRN51J-GP
BCLK# H2 CLK_EXP_N (20)
MISC
CLOCKS
(22) H_SNB_IVB# F49 RN503
PROC_SELECT# CLK_DP_P_R1
DPLL_REF_CLK AG3 4
AG1 CLK_DP_N_R2 3 +1.05V_RUN_VTT
DPLL_REF_CLK#
(78) CPU_DETECT# 1 2CPU_DETECT#_R C57 PROC_DETECT#
R512 0R0402-PAD-2-GP SRN1KJ-7-GP
R502
H_THERMTRIP# +1.35V_MEM
1 DY 2
56R2J-4-GP
H_CATERR# C49 R507
CATERR#
2
R501 4K99R2F-L-GP A00_0206
THERMAL
1 2 H_PROCHOT# 1 2 R535
62R2J-GP Q511 1KR2J-1-GP
H_PECI A48 AT30 DDR3_DRAMRST#_CPU S
(27) H_PECI PECI SM_DRAMRST#
1 DY 2H_CATERR#
1
R505 49D9R2F-GP D 1 2 DDR3_DRAMRST# (14,15)
R513 BF44 SM_RCOMP_0 R506 1 2 140R2F-GP R534
SM_RCOMP0
DDR3
MISC
1 2 H_PROCHOT#_R C45 BE43 SM_RCOMP_1 R508 1 2 25D5R2F-GP G 1KR2J-1-GP
(27,40) H_PROCHOT# PROCHOT# SM_RCOMP1
BG43 SM_RCOMP_2 R511 1 2 200R2F-L-GP
56R2J-4-GP SM_RCOMP2 2N7002K-2-GP
Signal Routing Guideline: 84.2N702.J31
(28) H_THERMTRIP# 1 2 H_THERMTRIP#_R D45 THERMTRIP# SM_RCOMP keep routing length less than 500 mils. 2ND = 84.2N702.031
R514 0R0402-PAD-2-GP Trace width = 15mil 3rd = 84.2N702.W31
SCD047U16V2KX-1-GP
1 2
Layout Note: DDR_HVREF_RST_PCH (20)
1
N53 XDP_PRDY# XDP_PRDY# (71) R5321 0R0402-PAD-2-GP
2 DDR_HVREF_RST_GATE (27)
PRDY#
C505
C R501, R513 place near to CPU PREQ# N55 XDP_PREQ# XDP_PREQ# (71) R533 DY 0R2J-2-GP
C
2
L56 XDP_TCLK XDP_TCLK (71) DDR_HVREF_RST (12)
TCK XDP_TMS
TMS L55 XDP_TMS (71)
PWR MANAGEMENT
J58 XDP_TRST# XDP_TRST# (71)
TRST#
JTAG & BPM

H_PM_SYNC C48 M60 XDP_TDI_R 1 2 XDP_TDI
(19) H_PM_SYNC PM_SYNC TDI
L59 XDP_TDO_R XDP0R2J-2-GP
R531
1 2 XDP_TDO
XDP_TDI (71)
TDO XDP0R2J-2-GP
R530
XDP_TDO (71)
(22,71) H_CPUPW RGD 1 2 H_CPUPW RGD_R B46 UNCOREPWRGOOD

R504 1KR2J-1-GP K58 XDP_DBRESET#_R
1 2 XDP_DBRESET# (19,71)
DBR# R529 0R2J-2-GP
1
R503
2 DY
10KR2J-3-GP
PM_DRAM_PW RGD_CPU BE45 G58 XDP_OBS0_R 1 2 XDP_OBS0
SM_DRAMPWROK BPM#0
E55 XDP_OBS1_R XDP0R2J-2-GP
R515
1 2 XDP_OBS1
XDP_OBS0 (71)
BPM#1
E59 XDP_OBS2_R XDP0R2J-2-GP
R516
1 2 XDP_OBS2
XDP_OBS1 (71)
BPM#2
G55 XDP_OBS3_R XDP0R2J-2-GP
R523
1 2 XDP_OBS3
XDP_OBS2 (71)
BPM#3
G59 XDP_OBS4_R XDP0R2J-2-GP
R524
1 2 XDP_OBS4
XDP_OBS3 (71)
BUF_CPU_RST# D44
BPM#4
H60 XDP_OBS5_R XDP0R2J-2-GP
R525
1 2 XDP_OBS5
XDP_OBS4 (71)
RESET# BPM#5
J59 XDP_OBS6_R XDP0R2J-2-GP
R526
1 2 XDP_OBS6
XDP_OBS5 (71)
BPM#6
J61 XDP_OBS7_R XDP0R2J-2-GP
R527
1 2 XDP_OBS7
XDP_OBS6 (71)
BPM#7 XDP0R2J-2-GP XDP_OBS7 (71)
1
R528
C501
SC100P50V2JN-3GP
2
+3.3V_ALW _PCH
IVY-BRIDGE-GP-NF
71.00IVY.A0U
B B
C504
SCD1U16V2KX-3GP
Layout Note:
1
C501 place near to CPU +1.35V_CPU_VDDQ
2
U502 R520
200R2F-L-GP
(27,78) RUNPW ROK 1 B VCC 5
(19) PM_DRAM_PW RGD 2
1
+1.05V_RUN_VTT A RUNPW ROK_AND PM_DRAM_PW RGD_CPU
3 GND Y 4 1 2
1
Buffered reset to CPU +3.3V_ALW _PCH 1 2 R521 130R2F-1-GP
+3.3V_RUN R519 200R2F-L-GP R522
74AHC1G09GW -GP 39R2J-L-GP
DY
1
73.01G09.0AB
2ND = 73.01G09.BAH
Q510_D 2
C503
SCD1U16V2KX-3GP
R518 3rd = 73.7SH09.0AG

1
75R2J-1-GP Open Drain Buffer

2
2
U501
Q510
D
1 B VCC 5 2N7002K-2-GP
(18) PCH_PLTRST# 2 A BUFO_CPU_RST# BUF_CPU_RST# 84.2N702.J31
3 GND Y 4 1
R517
2
43R2J-GP H_PECI
DY 2ND = 84.2N702.031
3rd = 84.07002.I31
74AHC1G09GW -GP
4th = 84.2N702.W31
1
73.01G09.0AB
A 2ND = 73.01G09.BAH DY EC501 <Core Design> A
S
3rd = 73.7SH09.0AG SC100P50V2JN-3GP
2
Open Drain Buffer (36) RUN_ON_CPU1.5VS3#

Wistron Corporation
Title
CPU(THERMAL/CLOCK/PM)
A3
Austin 13 A00
5 4 3 2 1
SSID = CPU
CPU1D 4 OF 9
CPU1C
Vinafix.com 3 OF 9
(15) M_B_DQ[63:0]
M_B_DQ[63:0]
M_A_DQ[63:0] M_B_DQ0 AL4
(14) M_A_DQ[63:0] SB_DQ0
D M_A_DQ0 AG6 M_B_DQ1 AL1 BA34 D
M_A_DQ1 SA_DQ0 M_B_DQ2 SB_DQ1 SB_CK0 M_B_DIMB_CLK_DDR0 (15)
AJ6 SA_DQ1 SA_CK0 AU36 M_A_DIMA_CLK_DDR0 (14) AN3 SB_DQ2 SB_CK#0 AY34 M_B_DIMB_CLK_DDR#0 (15)
M_A_DQ2 AP11 AV36 M_B_DQ3 AR4 AR22
M_A_DQ3 SA_DQ2 SA_CK#0 M_A_DIMA_CLK_DDR#0 (14) M_B_DQ4 SB_DQ3 SB_CKE0 M_B_DIMB_CKE0 (15)
AL6 SA_DQ3 SA_CKE0 AY26 M_A_DIMA_CKE0 (14) AK4 SB_DQ4
M_A_DQ4 AJ10 M_B_DQ5 AK3
M_A_DQ5 SA_DQ4 M_B_DQ6 SB_DQ5
AJ8 SA_DQ5 AN4 SB_DQ6
M_A_DQ6 AL8 M_B_DQ7 AR1
AL7 SA_DQ7 AU4 SB_DQ8
M_A_DQ8 AR11 M_B_DQ9 AT2 BA36
M_A_DQ9 SA_DQ8 M_B_DQ10 SB_DQ9 SB_CK1 M_B_DIMB_CLK_DDR1 (15)
AP6 SA_DQ9 SA_CK1 AT40 M_A_DIMA_CLK_DDR1 (14) AV4 SB_DQ10 SB_CK#1 BB36 M_B_DIMB_CLK_DDR#1 (15)
M_A_DQ10 AU6 AU40 M_B_DQ11 BA4 BF27
M_A_DQ11 SA_DQ10 SA_CK#1 M_A_DIMA_CLK_DDR#1 (14) M_B_DQ12 SB_DQ11 SB_CKE1 M_B_DIMB_CKE1 (15)
AV9 SA_DQ11 SA_CKE1 BB26 M_A_DIMA_CKE1 (14) AU3 SB_DQ12
M_A_DQ12 AR6 M_B_DQ13 AR3
AP8 SA_DQ13 AY2 SB_DQ14
M_A_DQ14 AT13 M_B_DQ15 BA3
AU13 SA_DQ15 BE9 SB_DQ16
M_A_DQ16 BC7 M_B_DQ17 BD9 BE41
M_A_DQ17 SA_DQ16 M_B_DQ18 SB_DQ17 SB_CS#0 M_B_DIMB_CS#0 (15)
BB7 SA_DQ17 SA_CS#0 BB40 M_A_DIMA_CS#0 (14) BD13 SB_DQ18 SB_CS#1 BE47 M_B_DIMB_CS#1 (15)
M_A_DQ18 BA13 BC41 M_B_DQ19 BF12
M_A_DQ19 SA_DQ18 SA_CS#1 M_A_DIMA_CS#1 (14) M_B_DQ20 SB_DQ19
BB11 SA_DQ19 BF8 SB_DQ20
M_A_DQ20 BA7 M_B_DQ21 BD10
BA9 SA_DQ21 BD14 SB_DQ22
M_A_DQ22 BB9 M_B_DQ23 BE13
AY13 SA_DQ23 BF16 SB_DQ24 SB_ODT0 AT43 M_B_DIMB_ODT0 (15)
M_A_DQ24 AV14 AY40 M_B_DQ25 BE17 BG47
M_A_DQ25 SA_DQ24 SA_ODT0 M_A_DIMA_ODT0 (14) M_B_DQ26 SB_DQ25 SB_ODT1 M_B_DIMB_ODT1 (15)
AR14 SA_DQ25 SA_ODT1 BA41 M_A_DIMA_ODT1 (14) BE18 SB_DQ26
M_A_DQ26 AY17 M_B_DQ27 BE21
AR19 SA_DQ27 BE14 SB_DQ28
M_A_DQ28 BA14 M_B_DQ29 BG14
C M_A_DQ29 SA_DQ28 M_B_DQ30 SB_DQ29 C
AU14 SA_DQ29 BG18 SB_DQ30 M_B_DQS#[7:0] (15)
M_A_DQ30 BB14 M_A_DQS#[7:0] (14) M_B_DQ31 BF19 AL3 M_B_DQS#0
M_A_DQ31 SA_DQ30 M_A_DQS#0 M_B_DQ32 SB_DQ31 SB_DQS#0 M_B_DQS#1
BB17 SA_DQ31 SA_DQS#0 AL11 BD50 SB_DQ32 SB_DQS#1 AV3
M_A_DQ32 BA45 AR8 M_A_DQS#1 M_B_DQ33 BF48 BG11 M_B_DQS#2
M_A_DQ33 SA_DQ32 SA_DQS#1 M_A_DQS#2 M_B_DQ34 SB_DQ33 SB_DQS#2 M_B_DQS#3
AR43 SA_DQ33 SA_DQS#2 AV11 BD53 SB_DQ34 SB_DQS#3 BD17
M_A_DQ34 AW48 AT17 M_A_DQS#3 M_B_DQ35 BF52 BG51 M_B_DQS#4
M_A_DQ35 SA_DQ34 SA_DQS#3 M_A_DQS#4 M_B_DQ36 SB_DQ35 SB_DQS#4 M_B_DQS#5
BC48 SA_DQ35 SA_DQS#4 AV45 BD49 SB_DQ36 SB_DQS#5 BA59
M_A_DQ36 BC45 AY51 M_A_DQS#5 M_B_DQ37 BE49 AT60 M_B_DQS#6
SA_DQ36 SA_DQS#5 SB_DQ37 SB_DQS#6
DDR SYSTEM MEMORY B

M_A_DQ37 AR45 AT55 M_A_DQS#6 M_B_DQ38 BD54 AK59 M_B_DQS#7
SA_DQ37 SA_DQS#6 SB_DQ38 SB_DQS#7
DDR SYSTEM MEMORY A
M_A_DQ38 AT48 AK55 M_A_DQS#7 M_B_DQ39 BE53

M_A_DQ39 SA_DQ38 SA_DQS#7 M_B_DQ40 SB_DQ39
AY48 SA_DQ39 BF56 SB_DQ40
M_A_DQ40 BA49 M_B_DQ41 BE57
AV49 SA_DQ41 BC59 SB_DQ42
M_A_DQ42 BB51 M_B_DQ43 AY60
AY53 SA_DQ43 BE54 SB_DQ44
M_A_DQ44 BB49 M_A_DQS[7:0] (14) M_B_DQ45 BG54 M_B_DQS[7:0] (15)
M_A_DQ45 SA_DQ44 M_A_DQS0 M_B_DQ46 SB_DQ45 M_B_DQS0
AU49 SA_DQ45 SA_DQS0 AJ11 BA58 SB_DQ46 SB_DQS0 AM2
M_A_DQ46 BA53 AR10 M_A_DQS1 M_B_DQ47 AW59 AV1 M_B_DQS1
M_A_DQ47 SA_DQ46 SA_DQS1 M_A_DQS2 M_B_DQ48 SB_DQ47 SB_DQS1 M_B_DQS2
BB55 SA_DQ47 SA_DQS2 AY11 AW58 SB_DQ48 SB_DQS2 BE11
M_A_DQ48 BA55 AU17 M_A_DQS3 M_B_DQ49 AU58 BD18 M_B_DQS3
AV56 SA_DQ49 SA_DQS4 AW45 AN61 SB_DQ50 SB_DQS4 BE51
M_A_DQ50 AP50 AV51 M_A_DQS5 M_B_DQ51 AN59 BA61 M_B_DQS5
AP53 SA_DQ51 SA_DQS6 AT56 AU59 SB_DQ52 SB_DQS6 AR59
M_A_DQ52 AV54 AK54 M_A_DQS7 M_B_DQ53 AU61 AK61 M_B_DQS7
M_A_DQ53 SA_DQ52 SA_DQS7 M_B_DQ54 SB_DQ53 SB_DQS7
AT54 SA_DQ53 AN58 SB_DQ54
M_A_DQ54 AP56 M_B_DQ55 AR58
AP52 SA_DQ55 AK58 SB_DQ56
M_A_DQ56 AN57 M_B_DQ57 AL58
AN53 SA_DQ57 AG58 SB_DQ58
B M_A_DQ58 M_B_DQ59 B
AG56 SA_DQ58 AG59 SB_DQ59
M_A_DQ59 AG53 M_B_DQ60 AM60
M_A_DQ60 SA_DQ59 M_B_DQ61 SB_DQ60 M_B_A0 M_B_A[15:0] (15)
AN55 SA_DQ60 M_A_A[15:0] (14) AL59 SB_DQ61 SB_MA0 BF32
M_A_DQ61 AN52 BG35 M_A_A0 M_B_DQ62 AF61 BE33 M_B_A1
M_A_DQ62 SA_DQ61 SA_MA0 M_A_A1 M_B_DQ63 SB_DQ62 SB_MA1 M_B_A2
AG55 SA_DQ62 SA_MA1 BB34 AH60 SB_DQ63 SB_MA2 BD33
M_A_DQ63 AK56 BE35 M_A_A2 AU30 M_B_A3
SA_DQ63 SA_MA2 M_A_A3 SB_MA3 M_B_A4
SA_MA3 BD35 SB_MA4 BD30
AT34 M_A_A4 AV30 M_B_A5
SA_MA4 M_A_A5 SB_MA5 M_B_A6
SA_MA5 AU34 SB_MA6 BG30
BB32 M_A_A6 (15) M_B_BS0 BG39 BD29 M_B_A7
SA_MA6 M_A_A7 SB_BS0 SB_MA7 M_B_A8
(14) M_A_BS0 BD37 SA_BS0 SA_MA7 AT32 (15) M_B_BS1 BD42 SB_BS1 SB_MA8 BE30
(14) M_A_BS1 BF36 AY32 M_A_A8 (15) M_B_BS2 AT22 BE28 M_B_A9
SA_BS1 SA_MA8 M_A_A9 SB_BS2 SB_MA9 M_B_A10
(14) M_A_BS2 BA28 SA_BS2 SA_MA9 AV32 SB_MA10 BD43
BE37 M_A_A10 AT28 M_B_A11
SA_MA10 M_A_A11 SB_MA11 M_B_A12
SA_MA11 BA30 SB_MA12 AV28
BC30 M_A_A12 (15) M_B_CAS# AV43 BD46 M_B_A13
SA_MA12 M_A_A13 SB_CAS# SB_MA13 M_B_A14
(14) M_A_CAS# BE39 SA_CAS# SA_MA13 AW41 (15) M_B_RAS# BF40 SB_RAS# SB_MA14 AT26
(14) M_A_RAS# BD39 AY28 M_A_A14 (15) M_B_W E# BD45 AU22 M_B_A15
SA_RAS# SA_MA14 M_A_A15 SB_WE# SB_MA15
(14) M_A_W E# AT41 SA_WE# SA_MA15 AU26
IVY-BRIDGE-GP-NF
IVY-BRIDGE-GP-NF 71.00IVY.A0U
71.00IVY.A0U
A <Core Design> A
Wistron Corporation
Title
CPU (DDR)
A3 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = CPU
Vinafix.com
CFG2
CPU1E 5 OF 9
D D
1
PEG Static Lane Reversal
R702
1KR2J-1-GP 1: Normal Operation; Lane #
(71) CFG0
CFG0 B50 N59 CLK_XDP_ITP (71)
DY CFG[2] definition matches socket pin map definition
CFG1 CFG0 BCLK_ITP
(71) CFG1 C51 N58 CLK_XDP_ITP# (71)
2
CFG1 BCLK_ITP#
(71) CFG2
CFG2 B54 0:Lane Reversed
CFG3 CFG2
(71) CFG3 D53 CFG3
CFG4 A51 N42
(71) CFG4 CFG4 RSVD30
CFG5 C53 L42
CFG6 C55 L45
CFG7 H49 L47
CFG8 A55
(71) CFG8 CFG8
CFG9 H51
(71) CFG9 CFG9
CFG10 K49 M13
CFG11 K53 M14
TPAD14-OP-GP TP701 1 CFG12 F53 U14
TPAD14-OP-GP TP702 CFG13 CFG12 RSVD36
1 G53 CFG13 RSVD37 W14
TPAD14-OP-GP TP703 1 CFG14 L51 P13
TPAD14-OP-GP TP704 CFG15 CFG14 RSVD38
1 F51 CFG15
CFG16 D52
(71) CFG16 CFG16
CFG17 L53 AT49
RSVD40 K24
TPAD14-OP-GP TP715 1 VCC_VAL_SENSE H43
RESERVED
TPAD14-OP-GP TP716 VSS_VAL_SENSE VCC_VAL_SENSE
1 K43 VSS_VAL_SENSE RSVD41 AH2
RSVD42 AG13
RSVD43 AM14
TPAD14-OP-GP TP717 1 VAXG_VAL_SENSE H45 AM15
C TPAD14-OP-GP TP718 VSSAXG_VAL_SENSE VAXG_VAL_SENSE RSVD44 CFG5 C
1 K45 VSSAXG_VAL_SENSE
N50 CFG6 PCIE Port Bifurcation Straps
TPAD14-OP-GP TP719 VCC_DIE_SENSE RSVD45
1 F48 VCC_DIE_SENSE
1
TPAD14-OP-GP TP720 1 VSS_DIE_SENSE G48 RSVD47 R701 R704 CFG[6:5] 11: 1x16 PCI Express
H48
K48
RSVD6 DY 1KR2J-1-GP DY 1KR2J-1-GP
10: 2 x8 - PCI Express
RSVD7 TP_DC_TEST_A4 TP723 TPAD14-OP-GP
A4 1
2
DC_TEST_A4
DC_TEST_C4 C4 01: Reserved
BA19 D3 DC_TEST_C4_D3
RSVD8 DC_TEST_D3 TP_DC_TEST_D1 TP724 TPAD14-OP-GP
AV19 RSVD9 DC_TEST_D1 D1 1 00: 1x8, 2x4 PCI Express
AT21 A58 TP_DC_TEST_A58 1 TP725 TPAD14-OP-GP
RSVD10 DC_TEST_A58
BB21 RSVD11 DC_TEST_A59 A59
BB19 C59 TP_DC_TEST_A59_C59
RSVD12 DC_TEST_C59
AY21 RSVD13 DC_TEST_A61 A61
BA22 C61 TP_DC_TEST_A61_C61
RSVD14 DC_TEST_C61 TP_DC_TEST_D61 TP726 TPAD14-OP-GP
AY22 RSVD15 DC_TEST_D61 D61 1
AU19 RSVD16 DC_TEST_BD61 BD61 TP_DC_TEST_BD61 1 TP727 TPAD14-OP-GP
AU21 RSVD17 DC_TEST_BE61 BE61
BD21 RSVD18 DC_TEST_BE59 BE59 TP_DC_TEST_BE59_BE61
BD22 RSVD19 DC_TEST_BG61 BG61
BD25 RSVD20 DC_TEST_BG59 BG59 DC_TEST_BG59_BG61
BD26 RSVD21 DC_TEST_BG58 BG58 TP_DC_TEST_BG58 1 TP728 TPAD14-OP-GP
BG22 BG4 TP_DC_TEST_BG4 1 TP729 TPAD14-OP-GP
RSVD22 DC_TEST_BG4
BE22 RSVD23 DC_TEST_BG3 BG3
BG26 BE3 DC_TEST_BE3_BG3
RSVD24 DC_TEST_BE3
BE26 RSVD25 DC_TEST_BG1 BG1
BF23 BE1 DC_TEST_BE1_BG1
B RSVD26 DC_TEST_BE1 TP_DC_TEST_BD1 TP730 TPAD14-OP-GP B
BE24 RSVD27 DC_TEST_BD1 BD1 1
IVY-BRIDGE-GP-NF
71.00IVY.A0U
<Core Design>
A A
Wistron Corporation
Title
CPU (RESERVED)
A3 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CPU1F POWER 6 OF 9
+1.05V_RUN_VTT
8.5A
VCC_CORE AF46
VCCIO1
AG48
33A VCCIO3
VCCIO4
AG50
C862
SC1U6D3V2KX-GP
C864
SC1U6D3V2KX-GP
C865
SC1U6D3V2KX-GP
C866
SC1U6D3V2KX-GP
C869
SC1U6D3V2KX-GP
C867
SC1U6D3V2KX-GP
C868
SC1U6D3V2KX-GP
C870
SC1U6D3V2KX-GP
Voltage Rail Voltage(V) Iccmax(A)
Vinafix.com
A26 AG51
1
VCC1 VCCIO5
A29 AJ17
VCC2 VCCIO6
A31 AJ21
VCC_CORE A34
VCC3 VCCIO7
AJ25
DY DY DY DY DY DY DY DY VCC_CORE(ULV) 0.3~1.52 33
2
VCC4 VCCIO8
A35 AJ43
VCC5 VCCIO9
D A38
VCC6 VCCIO10
AJ47 VAXG(ULV) 0~1.52 33 D
A39 AK50
VCC7 VCCIO11
A42 AK51 VCCIO 1.05 8.5
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCC8 VCCIO12
C801
C821
C822
C804
C805
C806
C807
C808
C809
C810
C26 AL14
1
1
VCC9 VCCIO13
C27
VCC10 VCCIO14
AL15 VDDQ 1.5 5
C32 AL16
DY C34
VCC11 VCCIO15
AL20 VCCSA 0.9 4
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
2
2
VCC12 VCCIO16
C874
SC1U6D3V2KX-GP
C876
SC1U6D3V2KX-GP
C875
SC1U6D3V2KX-GP
C877
SC1U6D3V2KX-GP
C878
SC1U6D3V2KX-GP
C37 AL22
1
VCC13 VCCIO17
C871
C872
C873
C39 AL26 VCCPLL 1.8 1.2
VCC14 VCCIO18
C42 AL45
D27
VCC15 VCCIO19
AL48 DY
2
VCC16 VCCIO20
D32 AM16
VCC17 VCCIO21
D34 AM17
VCC18 VCCIO22
D37
VCC19 VCCIO23
AM21 VCCIO Output Decoupling Recommendation:
D39 AM43
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V3MX-1-GP
PEG IO AND DDR IO

VCC20 VCCIO24 330u x 2(Remove)
C823
C824
C828
D42 AM47
SC22U6D3V5MX-2GP
1
1
VCC21 VCCIO25 10u x 10(0603)
C811
C812
C813
C816
C818
C820
E26 AN20
VCC22 VCCIO26
C879
SC10U6D3V3MX-GP
C880
SC10U6D3V3MX-GP
C881
SC10U6D3V3MX-GP
C882
SC10U6D3V3MX-GP
DY E28 AN42 22 uf x3 1u x 26(0402)
1
VCC23 VCCIO27
E32 AN45 10 ufx9
2
2
VCC24 VCCIO28
E34
VCC25 VCCIO29
AN48 Added, cause the DY
E37 1.05V far away CPU 1 uf x23
2
VCC26
E38
VCC27
VCCPQ Output Decoupling Recommendation:
CORE SUPPLY
F25 1u x 1(0402)
VCC28
F26
VCC29 +1.05V_RUN_VTT
F28
VCC30
F32
VCC31
F34
VCC32
F37 AA14
VCC33 VCCIO30
F38 AA15
VCC34 VCCIO31
22 uf x24 F42 AB17
SC10U6D3V3MX-GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
VCC35 VCCIO32
C885
SC1U6D3V2KX-GP
C883
SC1U6D3V2KX-GP
C884
SC1U6D3V2KX-GP
C886
SC1U6D3V2KX-GP
C888
SC1U6D3V2KX-GP
C887
SC1U6D3V2KX-GP
C889
SC1U6D3V2KX-GP
C890
SC1U6D3V2KX-GP
C891
SC1U6D3V2KX-GP
C892
SC1U6D3V2KX-GP
C832
G42 AB20
10 uf x7
1
1
VCC36 VCCIO33
C825
C830
C831
C843
C847
H25 AC13
2.2uf x2 VCC37 VCCIO34
H26 AD16
DY H28
VCC38 VCCIO35
AD18
DY DY DY DY DY DY DY
2
2
VCC39 VCCIO36
H29 AD21
VCC40 VCCIO37
H32 AE14
VCC41 VCCIO38
H34 AE15
VCC42 VCCIO39
H35 AF16
VCC43 VCCIO40
H37 AF18
VCC44 VCCIO41
H38 AF20
VCC45 VCCIO42
H40 AG15
VCC46 VCCIO43
C895
SC10U6D3V3MX-GP
C897
SC10U6D3V3MX-GP
C893
SC10U6D3V3MX-GP
C894
SC10U6D3V3MX-GP
C896
SC10U6D3V3MX-GP
C J25 AG16 C
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
1
VCC47 VCCIO44
J26 AG17
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V5KX-1GP
VCC48 VCCIO45
C802
C803
C815
C817
C819
C833
C827
C840
J28 AG20
DY DY DY DY
1
VCC49 VCCIO46
C814
C829
J29 AG21
2
VCC50 VCCIO47
J32 AJ14
DY DY DY DY J34
VCC51 VCCIO48
AJ15
2
VCC52 VCCIO49
J35
VCC53
J37
VCC54
J38
VCC55
J40
VCC56
J42
VCC57
K26 W16
VCC58 VCCIO50
K27 W17
VCC59 VCCIO51
K29
VCC60
K32
VCC61
K34
VCC62
K35
VCC63
K37
VCC64
K39
VCC66 H_SNB_IVB#_PWRCTRL TP801 TPAD14-OP-GP
K42 BC22 1
VCC67 VCCIO_SEL
L25
VCC68
VCC Output Decoupling Recommendation: L28
VCC69
1.9m ohm loadline design:(for SV) L33
VCC70
L36
470u x 4(Remove) VCC71 +V1.05S_VCCPQE_R +1.05V_RUN_VTT +1.05V_RUN_VTT
L40
VCC72
22u x 20(0805) N26
VCC73
QUIET
RAILS
2.2u x 35(0402) N30 AM25 1 2
VCC74 VCCPQE1 R812 0R0402-PAD-2-GP
N34 AN22
Layout Note:
1
VCC75 VCCPQE2
N38
1
VCC76 C826 R803, R804, R805 need close to CPU
2.9m ohm loadline design:(for ULV/LV) SC1U6D3V2KX-GP R805 R804
Alert# signal must be routed between the Clock and Data
2
75R2F-2-GP 130R2F-1-GP
330u x 3(Remove) lines to reduce the cross talk between them
22u x 12(0805) R803
2
2.2u x 16(0402) 43R2J-GP
A44 H_CPU_SVIDALRT# 1 2
VIDALERT# VR_SVID_ALERT# (42)
B43 H_CPU_SVIDCLK
VIDSCLK H_CPU_SVIDCLK (42) Need place Pull Hi
SVID
C44 H_CPU_SVIDDAT
VIDSOUT H_CPU_SVIDDAT (42)
at IMVP page
VCC_CORE
B B
Layout Note:
1
R801 1. PH/PL resisors place close CPU
100R2F-L1-GP-U 2. SENSE signal recommend differential routing
2
F43 VCCSENSE
SENSE LINES
VCC_SENSE VCCSENSE (42)
G43 VSSSENSE VSSSENSE (42)
VSS_SENSE
1
+1.05V_RUN_VTT
R802
100R2F-L1-GP-U
1
AN16
VCCIO_SENSE R807
AN17
2
VSS_SENSE_VCCIO
10R2F-L-GP
VCCIO_SENSE (45)
2
VSSIO_SENSE (45)
1
IVY-BRIDGE-GP-NF
71.00IVY.A0U R806
10R2F-L-GP
Layout Note:
2
1. PH/PL resisors place close CPU
2. SENSE signal recommend differential routing
A A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
CPU (VCC_CORE)
A2 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = CPU
Layout Note:
CPU1G POWER 7 OF 9
+V_SM_VREF_CNT should have 10 mil trace width Voltage Rail Voltage(V) Iccmax(A)
+V_SM_VREF_CNT
Vinafix.com
VCC_CORE(ULV) 0.3~1.52 33
VCC_GFXCORE 33A
SM_VREF
AY43 VAXG(ULV) 0~1.52 33
AA46
VREF
VAXG1
AB47 VCCIO 1.05 8.5
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VAXG2
BE7 +DIMM0_1_VREF_CPU
C901
C902
C903
C904
C905
D AB50 +DIMM0_1_VREF_CPU D
1
VAXG3 SA_DIMM_VREFDQ
AB51 BG7 +DIMM0_1_CA_CPU +DIMM0_1_CA_CPU VDDQ 1.5 5
VAXG4 SB_DIMM_VREFDQ
VCCAXG Output Decoupling Recommendation: AB52
VAXG5
3.9m ohm loadline design:(for GT2) AB53 VCCSA 0.9 6
2
VAXG6
470u x 2(remove)
22 uf x17 AB55
VAXG7
1 uf x7 AB56
VAXG8
VCCPLL 1.8 1.2
22u x 6(0805) AB58
VAXG9
10u x 6(0603) AB59
VAXG10
AC61
1u x 11(0402) VAXG11 +1.35V_CPU_VDDQ
AD47
VAXG12
AD48
AD50
VAXG13 5A
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VAXG14
C955
C923
C920
C921
C922
C919
C911
4.6m ohm loadline design:(for GT1) AD51 AJ28
- 1.5V RAILS
1
1
VAXG15 VDDQ1
330u x 2(remove) AD52 AJ33
VAXG16 VDDQ2
AD53 AJ36
22u x 5(0805) VAXG17 VDDQ3
AD55 AJ40
1
VAXG18 VDDQ4
C944
SC1U6D3V2KX-GP
C945
SC1U6D3V2KX-GP
C946
SC1U6D3V2KX-GP
C947
SC1U6D3V2KX-GP
C948
SC1U6D3V2KX-GP
C949
SC1U6D3V2KX-GP
C950
SC1U6D3V2KX-GP
C951
SC1U6D3V2KX-GP
C952
SC1U6D3V2KX-GP
C953
SC1U6D3V2KX-GP
10u x 6(0603) AD56
VAXG19 VDDQ5
AL30
AD58 AL34
1u x 6(0402)
AD59
VAXG20 VDDQ6
AL38
DY DY DY DY DY DY DY DY +1.35V_CPU_VDDQ +1.35V_MEM
2
VAXG21 VDDQ7
AE46 AL42
VAXG22 VDDQ8 C957
N45 AM33
VAXG23 VDDQ9
P47 AM36 1 2
VAXG24 VDDQ10
P48 AM40
VAXG25 VDDQ11 SCD1U16V2KX-3GP
P50 AN30
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
VAXG26 VDDQ12
C906
C907
C908
C909
C910
P51 AN34
1
VAXG27 VDDQ13
P52 AN38
VAXG28 VDDQ14 C958
P53 AR26
DDR3
1
VAXG29 VDDQ15
PTC901
ST330U2D5VDM-24-GP-U
P55 AR28 1 2
GRAPHICS
2
1
VAXG30 VDDQ16
C936
SC10U6D3V3MX-GP
C937
SC10U6D3V3MX-GP
C938
SC10U6D3V3MX-GP
C939
SC10U6D3V3MX-GP
C940
SC10U6D3V3MX-GP
C941
SC10U6D3V3MX-GP
C942
SC10U6D3V3MX-GP
P56 AR30
P61
VAXG31 VDDQ17
AR32
DY DY SCD1U16V2KX-3GP
T48
VAXG32 VDDQ18
AR34 DY DY DY
2
VAXG33 VDDQ19
T58 AR36
2
VAXG34 VDDQ20 C959
T59 AR40
VAXG35 VDDQ21
T61 AV41 1 2
VAXG36 VDDQ22
U46 AW26
VAXG37 VDDQ23 SCD1U16V2KX-3GP
V47 BA40
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VAXG38 VDDQ24
V48 BB28
VAXG39 VDDQ25
1 V50 BG33 10 uf x8
1
VAXG40 VDDQ26
C912
C913
C914
C915
C916
C917
C918
V51 C960
V52
VAXG41 1 uf x10 1 2
VAXG42
V53
2
2
VAXG43 SCD1U16V2KX-3GP
C V55 C
VAXG44
V56
VAXG45
VDDQ Output Decoupling Recommendation:
V58 330u x 1(Remove)
VAXG46
V59
VAXG47 10u x 8(0603)
W50
W51
VAXG48
1u x 10(0402) Layout Note:
VAXG49
W52
VAXG50
For S3 reduction circuit's 1D5V return pass.
W53
VAXG51
W55
VAXG52
W56
VAXG53
VCCDQ Output Decoupling Recommendation:
VCC_GFXCORE W61
VAXG54 1u x 1(0402)
Y48
VAXG55
Y61
VAXG56
Layout Note:
1
1. PH/PL resisors place close CPU R903 +V1.35S_VCCD_Q +1.35V_CPU_VDDQ
2. SENSE signal recommend differential routing 100R2F-L1-GP-U
QUIET RAILS
AM28 1 2
SENSE
LINES
2
VCC_AXG_SENSE VCCDQ1 R909 0R0402-PAD-2-GP
(42) VCC_AXG_SENSE F45 AN26
VSS_AXG_SENSE VAXG_SENSE VCCDQ2
(42) VSS_AXG_SENSE G45
1
VSSAXG_SENSE
C954
SC1U6D3V2KX-GP
1
R904
2
100R2F-L1-GP-U
1.8V RAIL
2
BB3
VCCPLL1
BC1
+1.8V_RUN VCCPLL2
BC4
1.2A VCCPLL3
VCCPLL Output Decoupling Recommendation: BC43 TP_VDDQ_SENSE 1 TP901 TPAD14-OP-GP

1
VDDQ_SENSE
C924
SC1U6D3V2KX-GP
C925
SC1U6D3V2KX-GP
BA43 TP_VDDQ_VSS 1 TP902 TPAD14-OP-GP

330u x 1(Remove) VSS_SENSE_VDDQ
SENSE LINES
VCCSA Power Select
1u x 2(0402) DY L17
2
VCCSA1
L21
VCCSA2
N16
VCCSA3
Voltage(V) VID[0] VID[1]
N20
+VCC_SA VCCSA4
N22
6A
SA RAIL
B VCCSA5 B
P17
VCCSA6
0.9 0 0
P20 U10 VCCSA_SENSE (48)
VCCSA7 VCCSA_SENSE
R16
1
VCCSA8
C930
SC10U6D3V3MX-GP
C929
SC10U6D3V3MX-GP
C928
SC10U6D3V3MX-GP
C927
SC10U6D3V3MX-GP
C926
SC10U6D3V3MX-GP
R18
VCCSA9
0.85 0 1
R21
VCCSA Output Decoupling Recommendation: DY DY DY DY DY U15
VCCSA10
VCCSA VID
2
VCCSA11
330u x 1(Remove) V16 0.775 1 0
VCCSA12 VCCSA_SEL0
V17 D48
10u x 5(0603) VCCSA13 VCCSA_VID0 VCCSA_SEL0 (48)
lines
V18 D49 VCCSA_SEL1
VCCSA14 VCCSA_VID1 VCCSA_SEL1 (48)
1u x 5(0402) V21 0.75 1 1
VCCSA15
W20
1
1
VCCSA16
1
1
C935
SC1U6D3V2KX-GP
C934
SC1U6D3V2KX-GP
C933
SC1U6D3V2KX-GP
C932
SC1U6D3V2KX-GP
C931
SC1U6D3V2KX-GP
R911 R910
1KR2J-1-GP 1KR2J-1-GP
DY DY DY
2
IVY-BRIDGE-GP-NF
2
2
71.00IVY.A0U
A A
<Core Design>
Wistron Corporation
Title
CPU (VCC_GFXCORE)
A2 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CPU1H 8 OF 9
CPU1I 9 OF 9
A13 AM38 BG17 M4

A17
A21
VSS1
VSS2
VSS3
Vinafix.com VSS91
VSS92
VSS93
AM4
AM42
BG21
BG24
VSS181
VSS182
VSS183
VSS250
VSS251
VSS252
M58
M6
A25 VSS4 VSS94 AM45 BG28 VSS184 VSS253 N1
D A28 VSS5 VSS95 AM48 BG37 VSS185 VSS254 N17 D
A33 VSS6 VSS96 AM58 BG41 VSS186 VSS255 N21
A37 VSS7 VSS97 AN1 BG45 VSS187 VSS256 N25
A53 VSS11 VSS101 AN33 C29 VSS191 VSS260 N40
A9 VSS12 VSS102 AN36 C35 VSS192 VSS261 N43
AA1 VSS13 VSS103 AN40 C40 VSS193 VSS262 N47
AA13 VSS14 VSS104 AN43 D10 VSS194 VSS263 N48
AA53 VSS18 VSS108 AP10 D26 VSS198 VSS267 N61
AA55 VSS19 VSS109 AP51 D29 VSS199 VSS268 P14
AB16 VSS22 VSS112 AR13 D40 VSS202 VSS271 P21
AB18 AR17 D43 P58
AB21
AB48
VSS23
VSS24
VSS25
VSS113
VSS114
VSS115
AR21
AR41
D46
D50
VSS203
VSS204
VSS205
VSS VSS272
VSS273
VSS274
P59
P9
AB61 VSS26 VSS116 AR48 D54 VSS206 VSS275 R17
AC10 VSS27 VSS117 AR61 D58 VSS207 VSS276 R20
AC14 VSS28 VSS118 AR7 D6 VSS208 VSS277 R4
AC46 VSS29 VSS119 AT14 E25 VSS209 VSS278 R46
AC6 VSS30 VSS120 AT19 E29 VSS210 VSS279 T1
AD17 VSS31 VSS121 AT36 E3 VSS211 VSS280 T47
AD20 VSS32 VSS122 AT4 E35 VSS212 VSS281 T50
AD4 AT45 E40 T51
C AD61
AE13
VSS33
VSS34
VSS35
VSS VSS123
VSS124
VSS125
AT52
AT58
F13
F15
VSS213
VSS214
VSS215
VSS282
VSS283
VSS284
T52
T53
C
AE8 VSS36 VSS126 AU1 F19 VSS216 VSS285 T55

AF1 VSS37 VSS127 AU11 F29 VSS217 VSS286 T56
AF17 VSS38 VSS128 AU28 F35 VSS218 VSS287 U13
AF21 VSS39 VSS129 AU32 F40 VSS219 VSS288 U8
AF47 VSS40 VSS130 AU51 F55 VSS220 VSS289 V20
AF48 VSS41 VSS131 AU7 G51 VSS221 VSS290 V61
AF50 VSS42 VSS132 AV17 G6 VSS222 VSS291 W13
AF51 VSS43 VSS133 AV21 G61 VSS223 VSS292 W15
AF52 VSS44 VSS134 AV22 H10 VSS224 VSS293 W18
AF58 VSS48 VSS138 AV55 H4 VSS228 VSS297 Y4
AF59 VSS49 VSS139 AW13 H53 VSS229 VSS298 Y47
AG10 VSS50 VSS140 AW43 H58 VSS230 VSS299 Y58
AG14 VSS51 VSS141 AW61 J1 VSS231 VSS300 Y59
AG18 VSS52 VSS142 AW7 J49 VSS232
AG47 VSS53 VSS143 AY14 J55 VSS233
AG52 VSS54 VSS144 AY19 K11 VSS234
NCTF TEST PIN：

A5,A57,BC61,BG5
AH4 AY4 K8 A5
BG57,C3,E1,E61
VSS57 VSS147 VSS237 VSS_NCTF_1#A5
AH58 VSS58 VSS148 AY41 L16 VSS238 VSS_NCTF_2#A57 A57
AJ13 VSS59 VSS149 AY45 L20 VSS239 VSS_NCTF_3#BC61 BC61
AJ16 VSS60 VSS150 AY49 L22 VSS240 VSS_NCTF_8#BG5 BG5
AJ20 VSS61 VSS151 AY55 L26 VSS241 VSS_NCTF_9#BG57 BG57
AJ22 VSS62 VSS152 AY58 L30 VSS242 VSS_NCTF_10#C3 C3
B B
AJ26 VSS63 VSS153 AY9 L34 VSS243 VSS_NCTF_13#E1 E1
AJ30 VSS64 VSS154 BA1 L38 VSS244 VSS_NCTF_14#E61 E61
NCTF
AJ34 VSS65 VSS155 BA11 L43 VSS245
AJ38 VSS66 VSS156 BA17 L48 VSS246
AJ42 VSS67 VSS157 BA21 L61 VSS247 VSS_NCTF_4 BD3
AJ45 VSS68 VSS158 BA26 M11 VSS248 VSS_NCTF_5 BD59
AJ48 VSS69 VSS159 BA32 M15 VSS249 VSS_NCTF_6 BE4
AJ7 VSS70 VSS160 BA48 VSS_NCTF_7 BE58
AK1 VSS71 VSS161 BA51 VSS_NCTF_11 C58
AK52 VSS72 VSS162 BB53 VSS_NCTF_12 D59
AL10 VSS73 VSS163 BC13
AL21 BD12 IVY-BRIDGE-GP-NF
VSS76 VSS166
AL25 VSS77 VSS167 BD16 71.00IVY.A0U
AL28 VSS78 VSS168 BD19
AM13 VSS85 VSS175 BD48
AM30 VSS89 VSS179 BE5
AM34 VSS90 VSS180 BG13
A <Core Design> A
Wistron Corporation
IVY-BRIDGE-GP-NF 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
71.00IVY.A0U Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU (VSS)
A3 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
XDP
A3 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = MEMORY
Vinafix.com
D D
R1203
0R2J-2-GP
1 2
DY
Q1201
AP2302GN-GP
C
From CPU BE7 +DIMM0_1_VREF_CPU S D +V_DDR_REFA_M3
C
84.02302.A31
G
2nd = 84.02302.B31
3rd = 84.02300.D31
(5) DDR_HVREF_RST
R1202
0R2J-2-GP
1 2
DY
Q1202
AP2302GN-GP
From CPU BG7 +DIMM0_1_CA_CPU S D +V_DDR_REFB_M3
84.02302.A31
G
2nd = 84.02302.B31
3rd = 84.02300.D31
DDR_HVREF_RST
B B
M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
A <Core Design> A
Wistron Corporation
Title
DDRM1 & M3 solution

A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C
(Blanking) C
B B
A <Core Design> A
Wistron Corporation
Title
(Reserved)
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
X01 12/15
SSID = MEMORY X01 12/02
DM1
(6) M_A_A[15:0]
M_A_A0 98 NP1
M_A_A1 A0 NP1
97 NP2
M_A_A2 A1 NP2
96
M_A_A3 A2
95 110 M_A_RAS# (6)
M_A_A4 A3 RAS# SA0_DIMA
M_A_A5
92
A4 WE#
113 M_A_WE# (6)
SA1_DIMA
Note:
91 115 M_A_CAS# (6)
M_A_A6 A5 CAS# SA0 DIM0 = 0, SA1_DIM0 = 0
90
M_A_A7 A6
86 114 M_A_DIMA_CS#0 (6) SO-DIMMA SPD Address is 0xA0
1
M_A_A8 A7 CS0#
89 121 M_A_DIMA_CS#1 (6)
A8 CS1#
M_A_A9 SO-DIMMA TS Address is 0x30
Vinafix.com
85 R1401 R1402
M_A_A10 A9 0R0402-PAD-2-GP 0R0402-PAD-2-GP
107 73 M_A_DIMA_CKE0 (6)
M_A_A11 A10/AP CKE0
84 74 M_A_DIMA_CKE1 (6)
M_A_A12 A11 CKE1
83
2
M_A_A13 A12
119 101 M_A_DIMA_CLK_DDR0 (6)
M_A_A14 A13 CK0
D 80 103 M_A_DIMA_CLK_DDR#0 (6) D
M_A_A15 A14 CK0#
78
A15
79 102 M_A_DIMA_CLK_DDR1 (6)
(6) M_A_BS2 A16/BA2 CK1
104 M_A_DIMA_CLK_DDR#1 (6)
CK1#
109
(6) M_A_BS0 BA0
108 11
(6) M_A_BS1 BA1 DM0
(6) M_A_DQ[63:0] 28
M_A_DQ0 DM1
5 46
Layout Note: M_A_DQ1 7
DQ0 DM2
63
M_A_DQ2 DQ1 DM3
Place these caps 15
DQ2 DM4
136
M_A_DQ3 17 153
close to VREF_CA M_A_DQ4 DQ3 DM5
4 170
M_A_DQ5 DQ4 DM6
6 187
M_A_DQ6 DQ5 DM7
16
M_A_DQ7 DQ6
18 200 PCH_SMBDATA (15,20,66,71,79,82)
M_A_DQ8 DQ7 SDA
21 202 PCH_SMBCLK (15,20,66,71,79,82)
M_A_DQ9 DQ8 SCL
23
M_A_DQ10 DQ9 +3.3V_RUN
33 198
M_A_DQ11 DQ10 EVENT#
35
M_A_DQ12 DQ11
22 199
M_A_DQ13 DQ12 VDDSPD
24
M_A_DQ14 DQ13 SA0_DIMA
34 197
1
M_A_DQ15 DQ14 SA0 SA1_DIMA C1401
36 201
M_A_DQ16 DQ15 SA1 SCD1U16V2KX-3GP
39
M_A_DQ17 41
DQ16
77
DY
2
M_A_DQ18 DQ17 NC#1
51 122
M_A_DQ19 DQ18 NC#2 +1.35V_MEM
53 125
M_A_DQ20 DQ19 NC#/TEST
40
M_A_DQ21 DQ20
42 75
M_A_DQ22 DQ21 VDD1
50 76
M_A_DQ23 DQ22 VDD2
52 81
DQ23 VDD3
82
M_A_DQ25 DQ24 VDD4
Place these caps 59
DQ25 VDD5
87
M_A_DQ26 67 88
close to VREF_DQ M_A_DQ27 DQ26 VDD6 +1.35V_MEM
69 93
M_A_DQ28 DQ27 VDD7
56 94
M_A_DQ29 DQ28 VDD8
58 99
M_A_DQ30 DQ29 VDD9
68 100
M_A_DQ31 DQ30 VDD10
70 105
M_A_DQ32 DQ31 VDD11
129 106
SC10U6D3V5KX-1GP
M_A_DQ33 DQ32 VDD12
C1404
131 111
ST330U2VDM-4-GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1
1
DQ33 VDD13
EC1406
SCD1U16V2KX-3GP
EC1407
SCD1U16V2KX-3GP
EC1408
SCD1U16V2KX-3GP
TC1401
C M_A_DQ34 141 112 C
1
M_A_DQ35 DQ34 VDD14
C1403
C1405
143 117
M_A_DQ36 130
DQ35 VDD15
118
DY
DY
2
M_A_DQ37 DQ36 VDD16
132 123
2
M_A_DQ38 DQ37 VDD17
140 124
M_A_DQ39 DQ38 VDD18
142
M_A_DQ40 DQ39
147 2
M_A_DQ41 DQ40 VSS
149 3
M_A_DQ42 DQ41 VSS
157 8
M_A_DQ43 DQ42 VSS
159 9
M_A_DQ44 DQ43 VSS
146 13
M_A_DQ45 DQ44 VSS
148 14
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
M_A_DQ46 DQ45 VSS
C1407
C1416
C1417
158 19
SC10U6D3V5KX-1GP
1
1
M_A_DQ47 DQ46 VSS
160 20
M_A_DQ48 DQ47 VSS
C1406
163 25
M_A_DQ49 DQ48 VSS
165 26
2
M_A_DQ50 DQ49 VSS
175 31
M_A_DQ51 DQ50 VSS
177 32
M_A_DQ52 DQ51 VSS
164 37
DQ52 VSS
38
M_A_DQ54 DQ53 VSS
Place these caps 174
DQ54 VSS
43
M_A_DQ55 176 44
close to VTT1 and M_A_DQ56 DQ55 VSS
181 48
VTT2. M_A_DQ57 DQ56 VSS
183 49
M_A_DQ58 DQ57 VSS
191 54
M_A_DQ59 193
DQ58 VSS
55
Layout Note:
M_A_DQ60 DQ59 VSS
180
DQ60 VSS
60 Place these Caps near SO-DIMMA.
M_A_DQ61 182 61
M_A_DQ62 DQ61 VSS
192 65
M_A_DQ63 DQ62 VSS
194 66
DQ63 VSS
(6) M_A_DQS#[7:0] 71
M_A_DQS#0 VSS
10 72
+0.675V_DDR_VTT M_A_DQS#1 DQS0# VSS
27 127
M_A_DQS#2 DQS1# VSS
45 128
M_A_DQS#3 DQS2# VSS
62 133
M_A_DQS#4 DQS3# VSS
135 134
M_A_DQS#5 DQS4# VSS
152 138
M_A_DQS#6 DQS5# VSS
169 139
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
M_A_DQS#7 DQS6# VSS

C1419
C1420
C1418
186 144
1
DQS7# VSS
(6) M_A_DQS[7:0] 145
M_A_DQS0 VSS
12 150
B DY M_A_DQS1 29
DQS0 VSS
151 B
2
M_A_DQS2 DQS1 VSS

47 155
M_A_DQS3 DQS2 VSS
64 156
M_A_DQS4 DQS3 VSS
137 161
M_A_DQS5 DQS4 VSS
154 162
M_A_DQS6 DQS5 VSS
171 167
M_A_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
VSS
116 173
(6) M_A_DIMA_ODT0 ODT0 VSS
120 178
(6) M_A_DIMA_ODT1 ODT1 VSS
179
VSS
M_VREF_CA_DIMMA 126 184
VREF_CA VSS
1 185
Layout Note: M_VREF_DQ_DIMMA VREF_DQ VSS
189
VSS
All VREF traces should (5,15) DDR3_DRAMRST#
30
RESET# VSS
190
have width=20mil; 195
VSS
196
spacing=20 mil VSS
+0.675V_DDR_VTT 203 205
VTT1 VSS
204 206
VTT2 VSS
DDR3-204P-106-GP
62.10017.X31
2ND = 62.10024.G11
3RD = 62.10017.M41
+V_DDR_REFA_M3
1 2
R1405
0R0402-PAD-2-GP
+V_DDR_REF
+V_DDR_REF
Populate R1406, De-Populate R1405 for Intel DDR3
1 2
A R1408
0R0402-PAD-2-GP M_VREF_CA_DIMMA
1
R1406
2 VREFDQ multiple methods M1 A
0R0402-PAD-2-GP
M_VREF_DQ_DIMMA PopulateR1405, De-Populate R1406 for Intel DDR3
VREFDQ multiple methods M3
1
1
C1412
SCD1U16V2KX-3GP
C1430
SCD1U16V2KX-3GP
<Core Design>
1
1
C1411
SCD1U16V2KX-3GP
C1429
SCD1U16V2KX-3GP
C1426
DY
SC2D2U10V3KX-1GP
C1423
DY
SC2D2U10V3KX-1GP
Wistron Corporation
2

Title
DDR3-SODIMM1
A2 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = MEMORY DM2

(6) M_B_A[15:0]
M_B_A0 98 NP1
M_B_A1 A0 NP1
97 NP2
M_B_A2 A1 NP2
96
M_B_A3 A2
95 110 M_B_RAS# (6)
M_B_A4 A3 RAS#
92 113 M_B_WE# (6)
M_B_A5 A4 WE#
M_B_A6
91
A5 CAS#
115 M_B_CAS# (6) Note:
90
M_B_A7 A6 SO-DIMMB SPD Address is 0xA4
86 114 M_B_DIMB_CS#0 (6)
M_B_A8 A7 CS0#
89 121 M_B_DIMB_CS#1 (6) SO-DIMMB TS Address is 0x34
M_B_A9 A8 CS1#
85
M_B_A10 A9
Vinafix.com
107 73 M_B_DIMB_CKE0 (6)
M_B_A11 A10/AP CKE0
84 74 M_B_DIMB_CKE1 (6)
M_B_A12 A11 CKE1
83
M_B_A13 A12
119 101 M_B_DIMB_CLK_DDR0 (6)
M_B_A14 A13 CK0
80 103 M_B_DIMB_CLK_DDR#0 (6)
M_B_A15 A14 CK0#
D 78 D
A15
79 102 M_B_DIMB_CLK_DDR1 (6)
(6) M_B_BS2 A16/BA2 CK1
104 M_B_DIMB_CLK_DDR#1 (6)
CK1#
109
(6) M_B_BS0 BA0
108 11
(6) M_B_BS1 BA1 DM0
(6) M_B_DQ[63:0] 28
M_B_DQ0 DM1
5 46
M_B_DQ1 DQ0 DM2
7 63
M_B_DQ2 DQ1 DM3
15 136
M_B_DQ3 DQ2 DM4
17 153
M_B_DQ4 DQ3 DM5 +3.3V_RUN
4 170
Layout Note: M_B_DQ5 6
DQ4 DM6
187
M_B_DQ6 DQ5 DM7
Place these caps 16
DQ6
M_B_DQ7 18 200
close to VREF_CA PCH_SMBDATA (14,20,66,71,79,82)
1
M_B_DQ8 DQ7 SDA
21 202 PCH_SMBCLK (14,20,66,71,79,82)
M_B_DQ9 DQ8 SCL R1501
23
M_B_DQ10 DQ9 +3.3V_RUN 10KR2J-3-GP
33 198
M_B_DQ11 DQ10 EVENT#
35
M_B_DQ12 DQ11
22 199
2
M_B_DQ13 DQ12 VDDSPD
24
1
DQ13
C1501
SCD1U16V2KX-3GP
M_B_DQ14 34 197 SA0_DIMB
M_B_DQ15 DQ14 SA0 SA1_DIMB
36 201
M_B_DQ16 39
DQ15 SA1 DY SA1_DIMB
2
M_B_DQ17 DQ16
41 77
M_B_DQ18 DQ17 NC#1 SA0_DIMB
51 122
M_B_DQ19 DQ18 NC#2 +1.35V_MEM
53 125
M_B_DQ20 DQ19 NC#/TEST
40
1
M_B_DQ21 DQ20
42 75
M_B_DQ22 DQ21 VDD1 R1502
50 76
M_B_DQ23 DQ22 VDD2
52 81 0R0402-PAD-2-GP
M_B_DQ24 DQ23 VDD3
57 82
M_B_DQ25 DQ24 VDD4
59 87
2
M_B_DQ26 DQ25 VDD5
67 88
Layout Note: M_B_DQ27 69
DQ26 VDD6
93
M_B_DQ28 DQ27 VDD7
Place these caps 56
DQ28 VDD8
94
M_B_DQ29 58 99
close to VREF_DQ M_B_DQ30 DQ29 VDD9 +1.35V_MEM
68 100
M_B_DQ31 DQ30 VDD10
70 105
M_B_DQ32 DQ31 VDD11
129
DQ32 VDD12
106 X03 2/21
M_B_DQ33 131 111
M_B_DQ34 DQ33 VDD13
141 112
M_B_DQ35 DQ34 VDD14
C 143 117 C
ST330U2VDM-4-GP
SC10U6D3V5KX-1GP
M_B_DQ36 DQ35 VDD15
TC1502
C1510
130 118
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1
1
DQ36 VDD16
EC1511
SCD1U16V2KX-3GP
EC1509
SCD1U16V2KX-3GP
EC1510
SCD1U16V2KX-3GP
M_B_DQ37 132 123
M_B_DQ38 DQ37 VDD17
C1508
C1509
140 124
M_B_DQ39 DQ38 VDD18
142
2
M_B_DQ40 DQ39
147 2
M_B_DQ41 DQ40 VSS
149 3
M_B_DQ42 DQ41 VSS
157 8
M_B_DQ43 DQ42 VSS
159 9
M_B_DQ44 DQ43 VSS
146 13
M_B_DQ45 DQ44 VSS
148 14
M_B_DQ46 DQ45 VSS
158 19
+0.675V_DDR_VTT M_B_DQ47 DQ46 VSS
160 20
M_B_DQ48 DQ47 VSS
163 25
Layout Note:
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
M_B_DQ49 DQ48 VSS
C1513
C1512
C1530
C1528
165 26
1
M_B_DQ50 DQ49 VSS
Place these caps 175
DQ50 VSS
31
M_B_DQ51 177 32
close to VTT1 and M_B_DQ52 DQ51 VSS
C1518
C1519
C1521
164 37
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
2
1
VTT2. M_B_DQ53 DQ52 VSS

166 38
M_B_DQ54 DQ53 VSS
174 43
DY M_B_DQ55 176
DQ54 VSS
44
2
M_B_DQ56 DQ55 VSS

181 48
M_B_DQ57 DQ56 VSS
183 49
M_B_DQ58 DQ57 VSS
191 54
M_B_DQ59 DQ58 VSS
193 55
M_B_DQ60 DQ59 VSS
180 60
M_B_DQ61 DQ60 VSS
182 61
M_B_DQ62 192
DQ61 VSS
65
Layout Note:
M_B_DQ63 DQ62 VSS
194
DQ63 VSS
66 Place these Caps near SO-DIMMA.
(6) M_B_DQS#[7:0] 71
M_B_DQS#0 VSS
10 72
M_B_DQS#1 DQS0# VSS
27 127
M_B_DQS#2 DQS1# VSS
45 128
M_B_DQS#3 DQS2# VSS
62 133
M_B_DQS#4 DQS3# VSS
135 134
M_B_DQS#5 DQS4# VSS
152 138
M_B_DQS#6 DQS5# VSS
169 139
M_B_DQS#7 DQS6# VSS
186 144
DQS7# VSS
(6) M_B_DQS[7:0] 145
M_B_DQS0 VSS
12 150
M_B_DQS1 DQS0 VSS
29 151
B M_B_DQS2 DQS1 VSS B
47 155
M_B_DQS3 DQS2 VSS
64 156
M_B_DQS4 DQS3 VSS
137 161
M_B_DQS5 DQS4 VSS
154 162
M_B_DQS6 DQS5 VSS
171 167
M_B_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
VSS
116 173
(6) M_B_DIMB_ODT0 ODT0 VSS
120 178
(6) M_B_DIMB_ODT1 ODT1 VSS
179
VSS
M_VREF_CA_DIMMB 126 184
VREF_CA VSS
M_VREF_DQ_DIMMB 1 185
VREF_DQ VSS
189
Layout Note: 30
VSS
190
(5,14) DDR3_DRAMRST# RESET# VSS
All VREF traces should VSS
195
have width=20mil; 196
VSS
+0.675V_DDR_VTT 203 205
spacing=20 mil VTT1 VSS
204 206
VTT2 VSS
DDR3-204P-108-GP
62.10017.X41
2ND = 62.10017.V51
3rd = 62.10017.M51
+V_DDR_REFB_M3
1 2
R1504
0R0402-PAD-2-GP
+V_DDR_REF
+V_DDR_REF
Populate R1504, De-Populate R1505 for Intel DDR3
1 2
R1503
0R0402-PAD-2-GP M_VREF_CA_DIMMB
1
R1505
2 VREFDQ multiple methods M1
A
0R0402-PAD-2-GP
M_VREF_DQ_DIMMB PopulateRR1505, De-Populate R1504 for Intel DDR3 A
VREFDQ multiple methods M3

1
1
C1413
SCD1U16V2KX-3GP
C1431
SCD1U16V2KX-3GP
1
C1414
SCD1U16V2KX-3GP
C1432
SCD1U16V2KX-3GP
C1427
DY
SC2D2U10V3KX-1GP
C1428
DY
SC2D2U10V3KX-1GP
2
<Core Design>
2
Wistron Corporation
Title
DDR3-SODIMM2
A2 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = PCH
Vinafix.com
D D
+3.3V_RUN
RN1701 4 OF 10 +3.3V_RUN
PCH1D
1 4 L_CTRL_DATA (49) PANEL_BKEN_PCH J47 AP43
L_CTRL_CLK L_BKLTEN SDVO_TVCLKINN
2 DY 3 (49,78) ENVDD_PCH M45 L_VDD_EN SDVO_TVCLKINP AP45
SRN2K2J-1-GP (49) L_BKLT_CTRL P45 L_BKLTCTL SDVO_STALLN AM42
3
4
SDVO_STALLP AM40
LVDS_DDC_CLK_R T40 RN1706
(49) LVDS_DDC_CLK_R
(49) LVDS_DDC_DATA_R LVDS_DDC_DATA_R K47 L_DDC_CLK
AP39 SRN2K2J-1-GP
Layout Note:
L_DDC_DATA SDVO_INTN
SDVO_INTP AP40 Close HDMI port
L_CTRL_CLK T45
L_CTRL_DATA L_CTRL_CLK
P39
2
1
ENVDD_PCH L_CTRL_DATA
2 1
LVDS_IBG AF37 P38
100KR2J-1-GP LVD_IBG SDVO_CTRLCLK HDMI_DDC_CLK (51)
TPAD14-OP-GP TP1701 1 LVDS_VBG AF36 M39
R1703 LVD_VBG SDVO_CTRLDATA HDMI_DDC_DATA (51)
1
AE48 LVD_VREFH
R1701 AE47 AT49
Layout Note: 2K37R2F-GP LVD_VREFL DDPB_AUXN
AT47
DDPB_AUXP
Place near PCH; DDPB_HPD AT40 HDMI_PCH_DET (51)
trace to trace spacing=20mil 2 (49) LVDSA_CLK# AK39 LVDSA_CLK#
LVDS
(49) LVDSA_CLK AK40 LVDSA_CLK DDPB_0N AV42 HDMI_DATA2_R# (82)
DDPB_0P AV40 HDMI_DATA2_R (82)
(49) LVDSA_DATA0# AN48 LVDSA_DATA#0 DDPB_1N AV45 HDMI_DATA1_R# (82)
C AM47 AV46 C
(49) LVDSA_DATA1# LVDSA_DATA#1 DDPB_1P HDMI_DATA1_R (82)
Digital Display Interface

(49) LVDSA_DATA2# AK47 LVDSA_DATA#2 DDPB_2N AU48 HDMI_DATA0_R# (82)
AJ48 LVDSA_DATA#3 DDPB_2P AU47 HDMI_DATA0_R (82)
DDPB_3N AV47 HDMI_CLK_R# (82)
(49) LVDSA_DATA0 AN47 LVDSA_DATA0 DDPB_3P AV49 HDMI_CLK_R (82)
(49) LVDSA_DATA1 AM49 LVDSA_DATA1
(49) LVDSA_DATA2 AK49 LVDSA_DATA2
AJ47 P46
LVDSA_DATA3 DDPC_CTRLCLK
P42
Layout Note:
DDPC_CTRLDATA
Layout Note: HDMI trace length to DC CAP. max 10000mil
AF40 LVDSB_CLK#
LVDS signal trace AF39 LVDSB_CLK DDPC_AUXN AP47
+3.3V_RUN AP49
length max 4000mil DDPC_AUXP
AH45 LVDSB_DATA#0 DDPC_HPD AT38
AH47 LVDSB_DATA#1
AF49 LVDSB_DATA#2 DDPC_0N AY47
AF45 LVDSB_DATA#3 DDPC_0P AY49
DDPC_1N AY43
AH43 LVDSB_DATA0 DDPC_1P AY45
3
4
AH49 LVDSB_DATA1 DDPC_2N BA47

RN1707 AF47 BA48
LVDSB_DATA2 DDPC_2P
SRN2K2J-1-GP AF43 LVDSB_DATA3 DDPC_3N BB47
DDPC_3P BB49
2
1
(82) CRT_BLUE N48 CRT_BLUE DDPD_CTRLCLK M43

CRT_DDC_DATA (82) CRT_GREEN P49 M36
CRT_DDC_CLK CRT_GREEN DDPD_CTRLDATA
(82) CRT_RED T49 CRT_RED
B B
DDPD_AUXN AT45
CRT
(82) CRT_DDC_CLK T39 CRT_DDC_CLK DDPD_AUXP AT43
CRT_BLUE M40 BH41
CRT_GREEN (82) CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD
CRT_RED RN1708 BB43
CRT_HSYNC DDPD_0N
(82) CRT_HSYNC_CON_1 1 4 M47 CRT_HSYNC DDPD_0P BB45
(82) CRT_VSYNC_CON_1 2 3 CRT_VSYNC M49 BF44
CRT_VSYNC DDPD_1N
DDPD_1P BE44
SRN33J-5-GP-U BF42
DAC_IREF_R DDPD_2N
T43 DAC_IREF DDPD_2P BE42
5
6
7
8
T42 CRT_IRTN DDPD_3N BJ42

1
RN1705 BG42
SRN150F-1-GP Layout Note: R1702 DDPD_3P
Layout Note: Place near PCH; 1KR2F-L-GP PANTHER-GP-NF
Close to PCH side trace to trace spacing=30mil 71.PANTH.00U
4
3
2
1
A <Core Design> A
Wistron Corporation
Title
PCH (LVDS/CRT/DDI)
A3 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = PCH
PCH1E 5 OF 10
RSVD1 AY7
RSVD2 AV7
BG26 AU3
Vinafix.com BJ26
BH25
TP1
TP2
TP3
RSVD3
RSVD4 BG4
BJ16 TP4 RSVD5 AT10

D BG16 TP5 RSVD6 BC8 D
AH38 TP6
AH37 TP7 RSVD7 AU2
AK43 TP8 RSVD8 AT4
AK45 TP9 RSVD9 AT3
C18 TP10 RSVD10 AT1
N30 TP11 RSVD11 AY3
H3 TP12 RSVD12 AT5
AH12 TP13 RSVD13 AV3
AM4 TP14 RSVD14 AV1
AM5 TP15 RSVD15 BB1
Y13 BA3
USB3.0/2.0 Mapping Table K24
TP16
TP17
RSVD16
RSVD17 BB5
L24 TP18 RSVD18 BB3
USB 3.0 Port USB 2.0 port AB46 TP19 RSVD19 BB7
AB45 TP20 RSVD20 BE8
RSVD
Port 1 Port 0 RSVD21 BD4
RSVD22 BF6
Port 2 Port 1
Layout Note: B21 AV5
Port 3 Port 2 Trace Length : M20
TP21
TP22
RSVD23
RSVD24 AV10 USB Table
PCH ~~9000mil~~Cap~~1000mil~~CONN AY16 TP23
Port 4 Port 3 BG46 TP24 RSVD25 AT8 Pair Device
+3.3V_RUN
RN1803 AY5 0 USB0(Left side-HDMI/B)
SRN10KJ-6-GP RSVD26
RSVD27 BA2
8 1 PCI_REQ1# BE28 1 USB1(Right side-IO/B, for USB3.0)
BT_DET# USB3_RX2_N USB3RN1
7 2 (82) USB3_RX2_N BC30 USB3RN2 RSVD28 AT12
6 3 LCD_CBL_DET# USB3_RX3_N BE32 BF3 2 USB2(Right side-IO/B, for USB3.0)
C PCIE_MCARD2_DET# (82) USB3_RX3_N USB3RN3 RSVD29 C
5 4 BJ32 USB3RN4
BC28 USB3RP1 3 NC
USB3_RX2_P BE30
(82) USB3_RX2_P
(82) USB3_RX3_P
USB3_RX3_P BF32
USB3RP2
USB3RP3
USB2.0 Signal Group 4 WLAN
BG32 USB3RP4 USBP0N C24 USB_PN0 (82)
AV26 USB3TN1 USBP0P A24 USB_PP0 (82) 5 WWAN
(82) USB3_TX2_N USB3_TX2_N BB26 C25 USB_PN1 (82)
USB3_TX3_N USB3TN2 USBP1N
(82) USB3_TX3_N AU28 USB3TN3 USBP1P B25 USB_PP1 (82) 6 NC
AY30 USB3TN4 USBP2N C26 USB_PN2 (82)
AU26 USB3TP1 USBP2P A26 USB_PP2 (82) 7 NC
R1803 (82) USB3_TX2_P USB3_TX2_P AY26 K28
BBS_BIT1 USB3_TX3_P USB3TP2 USBP3N
1 DY 2 (82) USB3_TX3_P AV28 USB3TP3 USBP3P H28 8 NC
AW30 USB3TP4 USBP4N E28 USB_PN4 (82)
1KR2F-L-GP D28 USB_PP4 (82) 9 NC
USBP4P
USBP5N C28 USB_PN5 (66)
USBP5P A28 USB_PP5 (66) 10 NC
Boot Bios Strap USBP6N C29
USBP6P B29 11 NC
INT_PIRQA# K40 N28
PIRQA# USBP7N
GNT1#/GPIO51 SATA1GP/GPIO19 Boot BIOS Location INT_PIRQB# K38 PIRQB# USBP7P M28 12 CAMERA
PCI
INT_PIRQC# H38 L30
INT_PIRQD# PIRQC# USBP8N
G38 PIRQD# USBP8P K30 13 NC
0 0 LPC USBP9N G30
PCI_REQ1# C46 E30
REQ1#/GPIO50 USBP9P
USB
(66) PCIE_MCARD2_DET# C44 REQ2#/GPIO52 USBP10N C30 1. USB Ext. port 9 (HS) External debug port
0 1 Reserved BT_DET# E40 A30 use on Chief River platform.
REQ3#/GPIO54 USBP10P
USBP11N L32
BBS_BIT1 D47 K32 2. 2011 July; Microsoft will support USB3.0
GNT1#/GPIO51 USBP11P
1 0 Reserved E42 GNT2#/GPIO53 USBP12N G32 USB_PN12 (49) debug--> Port1 useable.
B PCI_GNT3# B
F46 GNT3#/GPIO55 USBP12P E32 USB_PP12 (49)
USBP13N C32
1 1 SPI(Default) USBP13P A32
(49) LCD_CBL_DET# LCD_CBL_DET# G42
PCH_GPIO3 PIRQE#/GPIO2
G40 PIRQF#/GPIO3
R1808 CAM_MIC_CBL_DET# C42 C33 USB_RBIAS 1 2
1 DY 2 PCI_GNT3# (79) HDD_FALL_INT 1 2
(49) CAM_MIC_CBL_DET#
FFS_PCH_INT D44
PIRQG#/GPIO4 USBRBIAS# R1811 Layout Note:
0R0402-PAD-2-GP PIRQH#/GPIO5 22D6R2F-L1-GP 1. USBRBIAS/# use 50ohm single-ended impedance
R1815 B33 spacing to other signal=15mil
1KR2F-L-GP TP1802 PCI_PME# K10 USBRBIAS
1 PME# 2. Length < 500mil
PCH_PLTRST# C6 A14 USB_OC#0_R 1 2
A16 Swap Override jumper PLTRST# OC0#/GPIO59 USB_OC#1_R R1809 1 USB_OC#0 (82)
OC1#/GPIO40 K20 20R0402-PAD-2-GP USB_OC#1 (82)
B17 USB_OC#2 R1812 0R0402-PAD-2-GP
R1817 1 OC2#/GPIO41
(78) CLK_PCI_5048 2 22R2J-2-GP PCI_5048 H49 CLKOUT_PCI0 OC3#/GPIO42 C16 USB_OC#3
PCI_GNT#3 Low = A16 swap override/Top-Block (27) CLK_PCI_MEC R1805 1 2 22R2J-2-GP PCI_MEC H43 CLKOUT_PCI1 OC4#/GPIO43 L16 USB_OC#4
Swap Override enabled J48 A16 USB_OC#5
CLKOUT_PCI2 OC5#/GPIO9 USB_OC#6
High = Default K42 CLKOUT_PCI3 OC6#/GPIO10 D14
(20) CLK_PCI_LOOPBACK 1 2 CLK_PCI_LOOPBACK_R H40 C14
CLKOUT_PCI4 OC7#/GPIO14 SIO_EXT_SMI# (27)
R1806
22R2J-2-GP PANTHER-GP-NF
2
DY EC1804 RN1802
1
SC4D7P50V2CN-1GP
SRN8K2J-2-GP-U
USB_OC#1_R 1 10
+3.3V_RUN +3.3V_ALW _PCH
USB_OC#3 2 9 USB_OC#6
A SIO_EXT_SMI# 3 8 USB_OC#4 <Core Design> A
USB_OC#0_R 4 7 USB_OC#5
U1801 5 6 USB_OC#2
+3.3V_ALW _PCH
1
PCH_PLTRST# C1802
(5) PCH_PLTRST# 1 A VCC 5
SCD1U16V2KX-3GP Wistron Corporation
2 RN1801 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2
B SRN8K2J-2-GP-U Taipei Hsien 221, Taiwan, R.O.C.

3 GND Y 4 PLT_RST# (27,66,71,77,78,82) 1 10 +3.3V_RUN
0R0402-PAD-2-GP INT_PIRQB# 2 9 INT_PIRQD# Title
1 R1814 PCH_GPIO3
U74LVC1G08G-AL5-R-GP-U
73.01G08.EHG 0R2J-2-GP
2
2XDP 1 R1813
PLTRST_MMI# (32)
PLTRST_XDP# (71) INT_PIRQA#
3
4
8
7 INT_PIRQC# PCH (PCI/USB/NVRAM)
2ND = 73.7SZ08.DAH 5 6 CAM_MIC_CBL_DET# Size Document Number Rev
+3.3V_RUN
A3 A00
3rd = 73.7SZ08.EAH Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = PCH
PCH1C 3 OF 10
(4) DMI_RXN[3:0] FDI_TXN[7:0] (4)
DMI_RXN0 BC24 BJ14 FDI_TXN0
DMI_RXN1 DMI0RXN FDI_RXN0 FDI_TXN1
BE20 DMI1RXN FDI_RXN1 AY14
DMI_RXN2 BG18 BE14 FDI_TXN2
Vinafix.com
(4) DMI_RXP[3:0]
DMI_RXN3 BG20
DMI2RXN
DMI3RXN
FDI_RXN2
FDI_RXN3
FDI_RXN4
BH13
BC12
FDI_TXN3
FDI_TXN4
DMI_RXP0 BE24 BJ12 FDI_TXN5
DMI_RXP1 DMI0RXP FDI_RXN5 FDI_TXN6
D BC20 DMI1RXP FDI_RXN6 BG10 D
DMI_RXP2 BJ18 BG9 FDI_TXN7
DMI_RXP3 DMI2RXP FDI_RXN7
BJ20 DMI3RXP FDI_TXP[7:0] (4)
BG14 FDI_TXP0
(4) DMI_TXN[3:0] DMI_TXN0 FDI_RXP0 FDI_TXP1
AW24 DMI0TXN FDI_RXP1 BB14
DMI_TXN1 AW20 BF14 FDI_TXP2
DMI1TXN FDI_RXP2
DMI_TXN2 BB18 BG13 FDI_TXP3 DSWODVREN - On Die DSW VR Enable
DMI_TXN3 DMI2TXN FDI_RXP3 FDI_TXP4
AV18 DMI3TXN FDI_RXP4 BE12
DMI
FDI
BG12 FDI_TXP5 HIGH Enabled (DEFAULT)
(4) DMI_TXP[3:0] DMI_TXP0 FDI_RXP5 FDI_TXP6
AY24 DMI0TXP FDI_RXP6 BJ10
DMI_TXP1 AY20 BH9 FDI_TXP7
DMI_TXP2 DMI1TXP FDI_RXP7 LOW Disabled
AY18
Layout Note: DMI_TXP3 AU18
DMI2TXP
DMI3TXP FDI_INT
DMI_ZCOMP keep W=4 mils and FDI_INT AW16 FDI_INT (4)
routing length less than 500 +1.05V_RUN RTC_AUX_S5
BJ24 AV12 FDI_FSYNC0 FDI_FSYNC0 (4)
mils. DMI_ZCOMP FDI_FSYNC0
DMI_IRCOMP keep W=4 mils and R1901 1 2 49D9R2F-GP DMI_COMP_R BG25 BC10 FDI_FSYNC1 FDI_FSYNC1 (4)
DMI_IRCOMP FDI_FSYNC1 DSW ODVREN R1917
routing length less than 500 1 2 330KR2J-L1-GP
mils. R1902 1 2 750R2F-GP RBIAS_CPY BH21 AV14 FDI_LSYNC0 FDI_LSYNC0 (4)
DMI2RBIAS FDI_LSYNC0
BB10 FDI_LSYNC1 FDI_LSYNC1 (4)
FDI_LSYNC1
A18 DSW ODVREN

ME_SUS_PW R_ACK_R 1 DSWVRMEN
2
R1928 0R0402-PAD-2-GP
System Power Management

(78) SUSACK# 1 DY 2 SUSACK#_R C12 E22 PCH_DPW ROK PCH_DPW ROK (78)
C R1923 0R2J-2-GP SUSACK# DPWROK C
+3.3V_RUN R1905 1 2 1KR2J-1-GP

(5,71) XDP_DBRESET# K3 B9 PCH_PCIE_W AKE# PCH_PCIE_W AKE# (27)
SYS_RESET# WAKE#
(71,78) SYS_PW ROK 1 2 SYS_PW ROK_R P12 N3 CLKRUN# CLKRUN# (27,77,78)

R1930 0R0402-PAD-2-GP SYS_PWROK CLKRUN#/GPIO32
1
R1931
DY 2
0R2J-2-GP +3.3V_RUN
(27) RESET_OUT# 1 2 PCH_PW ROK L22 G8 SUS_STAT#/LPCPD# 1 TP1901
R1932 0R0402-PAD-2-GP PWROK SUS_STAT#/GPIO61
1 DY 2 0R2J-2-GP R1919 1 2 8K2R2J-3-GP
R1916 PM_APW ROK_R L10 N14 SUSCLK 1 TP1902
APWROK SUSCLK/GPIO62
(5) PM_DRAM_PW RGD 1 2 PM_DRAM_PW RGD_R B13 D10 SIO_SLP_S5# SIO_SLP_S5# (27,36)
R1933 0R0402-PAD-2-GP DRAMPWROK SLP_S5#/GPIO63
PCH_DPW ROK 1 2 PCH_RSMRST#_R
(37) PCH_RSMRST#_Q R1934 1 2 0R0402-PAD-2-GP C21 H4 SIO_SLP_S4# SIO_SLP_S4# (36,46,78)
R1924 0R0402-PAD-2-GP RSMRST# SLP_S4#
(27) ME_SUS_PW R_ACK 1 2 ME_SUS_PW R_ACK_R K16 F4 SIO_SLP_S3# SIO_SLP_S3# (36,45,47,78)

R1935 0R0402-PAD-2-GP SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3#
(27) SIO_PW RBTN# 1 2SIO_PW RBTN#_R E20 PWRBTN# SLP_A# G10 SIO_SLP_A# SIO_SLP_A# (36,45,78)
(71) SIO_PW RBTN#_R R1936 0R0402-PAD-2-GP
(27) AC_PRESENT AC_PRESENT H20 G16 SIO_SLP_SUS# SIO_SLP_SUS# (78)

ACPRESENT/GPIO31 SLP_SUS#
B PCH_BATLOW # H_PM_SYNC B
E10 BATLOW#/GPIO72 PMSYNCH AP14 H_PM_SYNC (5)
PM_RI# A10 K14 SIO_SLP_LAN# SIO_SLP_LAN# (78,82)

RI# SLP_LAN#/GPIO29
PANTHER-GP-NF
Sequence: 71.PANTH.00U
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms
+3.3V_ALW
+3.3V_ALW _PCH
RN1901
1
C1912
SCD1U16V2KX-3GP
8 1 PCH_BATLOW #
7 2 PM_RI#
6 3 ME_SUS_PW R_ACK
2
5 4 PCH_PCIE_W AKE#
U1902
SRN10KJ-6-GP SIO_SLP_A# 1 5
A VCC
(27) PM_APW ROK PM_APW ROK 2 B
R1920 2 1 10KR2J-3-GP SIO_SLP_LAN# 3 4 PM_APW ROK_R
R1921 2
DY 1 10KR2J-3-GP SUS_STAT#/LPCPD#
GND Y
DY U74LVC1G08G-AL5-R-GP-U
73.01G08.EHG
A 2ND = 73.7SZ08.DAH <Core Design> A
3rd = 73.7SZ08.EAH
1
DY 2 Wistron Corporation
R1912 0R2J-2-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Title
PCH (DM I/FDI/PM)

A3 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = PCH
S5 power rail CLKREQ#:
PCIECLKRQ[0]#
+3.3V_ALW_PCH PCIECLKRQ[7:3]#
RN2001
1 8 PCIECLKRQ6# PCIE_CLK_RQ6#
2 7 MINI3CLK_REQ# PCIE_CLK_RQ3#
3 6 MINI1CLK_REQ# PCIE_CLK_RQ0#
EXPCLK_REQ# PCIE_CLK_RQ4#
Vinafix.com
4 5
SRN10KJ-6-GP +3.3V_RUN
RN2002 RN2018
PEG_B_CLKRQ# MMICLK_REQ# PCIE_CLK_RQ2#
1 8
PCIECLKRQ7#
1 4
LANCLK_REQ#
S0 power rail CLKREQ#:
D 2 7 PCIE_CLK_RQ5# 2 3 PCIE_CLK_RQ1# D
3 6 PCH_SMB_ALERT# PCIE_CLK_RQ7# PCIECLKRQ[2:1]#
4 5 PCH_GPIO74 SRN10KJ-5-GP
SRN10KJ-6-GP
+3.3V_ALW_PCH
RN2004 8 1 SMB_DATA
SRN2K2J-2-GP 7 2 SMB_CLK
6 3 SML1_SMBCLK
5 4 SML1_SMBDATA
10KR2J-3-GP 2 1 R2011 MINI2CLK_REQ#

+3.3V_RUN
2 1 DDR_HVREF_RST_PCH RN2007
1KR2J-1-GP R2009 PCH1B 2 OF 10 2 3
2 1 PEG_A_CLKRQ# 1 4
10KR2J-3-GP R2015 BG34
PERN1 PCH_SMB_ALERT# SRN2K2J-1-GP
BJ34
PERP1 SMBALERT#/GPIO11
E12 Can Place Far away PCH
CRB : 1K AV32
AU32
PETN1 NC H14 SMB_CLK
+3.3V_ALW_PCH PETP1 SMBCLK
CEKLT: 10K (82) PCIE_RXN2 BE34 C9 SMB_DATA
PERN2 SMBDATA
RN2022 (82) PCIE_RXP2 BF34 WLAN
C2005 PCIE_TXN2_C PERP2 SMB_DATA
(82) PCIE_TXN2 1 2 SCD1U16V2KX-3GP BB32 6 1 PCH_SMBDATA (14,15,66,71,79,82)
LAN_SMBCLK C2006 PCIE_TXP2_C PETN2
1 4 (82) PCIE_TXP2 1 2 SCD1U16V2KX-3GP AY32
PETP2
SMBUS
2 3 LAN_SMBDATA A12 DDR_HVREF_RST_PCH 5 2
SML0ALERT#/GPIO60 DDR_HVREF_RST_PCH (5)
BG36 84.2N702.A3F
PERN3 LAN_SMBCLK
SRN2K2J-1-GP
BJ36
PERP3 SML0CLK
C8 LAN_SMBCLK (82) 4 3 2nd = 84.DM601.03F
AV34
PETN3 NC 3rd = 84.2N702.E3F
AU34 G12 LAN_SMBDATA Q2001 4th = 84.2N702.F3F
PETP3 SML0DATA LAN_SMBDATA (82)
2N7002KDW-GP
BF36 PCH_SMBCLK (14,15,66,71,79,82)
PERN4
BE36
PERP4 PCH_GPIO74 SMB_CLK
C AY34
BB34
PETN4 NC SML1ALERT#/PCHHOT#/GPIO74
C13 C
PETP4 SML1_SMBCLK
E14 SML1_SMBCLK (27)
SML1CLK/GPIO58
PCI-E*
BG37
PERN5 SML1_SMBDATA
BH37 M16 SML1_SMBDATA (27)
PERP5 SML1DATA/GPIO75
AY36
BB36
PETN5 NC
PETP5
(32) PCH_RXN_C_MMI_TXN6 BJ38

PERN6
BG38
Layout Note: (32) PCH_RXP_C_MMI_TXP6 PERP6
Controller
C2001 2 SCD1U16V2KX-3GP PCIE_TXN6_C PCH_CL_CLK1 TP2002
Layout trace <
(32)
14000mil
MMI_RXN_C_PCH_TXN6
C2002
1
1 2 SCD1U16V2KX-3GP PCIE_TXP6_C
AU36
AV36
PETN6 MMI CL_CLK1
M7 1
(32) MMI_RXP_C_PCH_TXP6 PETP6
Link
(82) PCH_RXN_C_LAN_TXN7 BG40 T11 PCH_CL_DATA1 1 TP2003
PERN7 CL_DATA1
(82) PCH_RXP_C_LAN_TXP7 BJ40 LOM
C2009 PCIE_TXN7_C PERP7
(82) LAN_RXN_C_PCH_TXN7 1 2 SCD1U16V2KX-3GP AY40
C2010 PCIE_TXP7_C PETN7 PCH_CL_RST1#
(82) LAN_RXP_C_PCH_TXP7 1 2 SCD1U16V2KX-3GP BB40 P10 1 TP2004
PETP7 CL_RST1#
BE38
BC38
PERN8 Layout Note:
AW38
PERP8 NC CLKOUT termination
PETN8
AY38 place close to PCH <500mil
PETP8
M10 PEG_A_CLKRQ#
PEG_A_CLKRQ#/GPIO47
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P NC AB37
MINI1CLK_REQ# CLKOUT_PEG_A_N
CLOCKS
J2 AB38
PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P
RN2023 RN2017
(82) CLK_PCIE_LAN# 2 3 PCIE_LAN# AB49 AV22 CLKOUT_DMI_N 2 3 CLK_EXP_N (5)
PCIE_LAN CLKOUT_PCIE1N CLKOUT_DMI_N CLKOUT_DMI_P
(82) CLK_PCIE_LAN 1 4 AB47 LAN AU22 1 4 CLK_EXP_P (5)
0R4P2R-PAD CLKOUT_PCIE1P CLKOUT_DMI_P 0R4P2R-PAD
(82) LANCLK_REQ# M1
RN
PCIECLKRQ1#/GPIO18
RN
RN
AM12
RN2024 CLKOUT_DP_N
AM13
PCIE_MMI# CLKOUT_DP_P
(32) CLK_PCIE_MMI# 1 4 AA48
PCIE_MMI CLKOUT_PCIE2N
(32) CLK_PCIE_MMI 2 3 AA47
CLKOUT_PCIE2P MMI BF18 CLK_BUF_EXP_N 2 3
0R4P2R-PAD CLKIN_DMI_N CLK_BUF_EXP_P RN2019 1
(32) MMICLK_REQ# V10 BE18 4
PCIECLKRQ2#/GPIO20 CLKIN_DMI_P SRN10KJ-5-GP
B B
Y37 BJ30 CLK_BUF_CPYCLK_N 2 3
CLKOUT_PCIE3N CLKIN_GND1_N CLK_BUF_CPYCLK_P RN2008 1
Y36 NC BG30 4
CLKOUT_PCIE3P CLKIN_GND1_P SRN10KJ-5-GP
MINI3CLK_REQ# A8
PCIECLKRQ3#/GPIO25 CLK_BUF_DOT96_N
G24 2 3
CLKIN_DOT_96N CLK_BUF_DOT96_P RN2020 1
E24 4
CLKIN_DOT_96P SRN10KJ-5-GP
Y43
CLKOUT_PCIE4N
Y45 NC
CLKOUT_PCIE4P CLK_BUF_CKSSCD_N
AK7 2 3
EXPCLK_REQ# CLKIN_SATA_N CLK_BUF_CKSSCD_P RN2021 1
L12 AK5 4
RN
PCIECLKRQ4#/GPIO26 CLKIN_SATA_P SRN10KJ-5-GP

RN2028
1 4 PCIE_MINI2# V45 K45 CLK_BUF_REF14 R2008 1 2
(82) CLK_PCIE_MINI2# CLKOUT_PCIE5N REFCLK14IN
PCIE_MINI2 10KR2J-3-GP
(82) CLK_PCIE_MINI2 2 3 V46
CLKOUT_PCIE5P WLAN
(82) MINI2CLK_REQ# 0R4P2R-PAD L14 H45 CLK_PCI_LOOPBACK CLK_PCI_LOOPBACK (18)
Layout Note:
PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK
1500mil < Layout trace < 10000mil
AB42 V47 XTAL25_IN
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT XTAL25_IN
AB40 NC V49 1 2
CLKOUT_PEG_B_P XTAL25_OUT X2001
PEG_B_CLKRQ# E6 C2008
PEG_B_CLKRQ#/GPIO56 R2007 SC15P50V2JN-2-GP
1 4
1
Y47 XCLK_RCOMP 1 2 +1.05V_RUN
XCLK_RCOMP R2006
V40
CLKOUT_PCIE6N 90D9R2F-1-GP 1MR2J-1-GP
V42
CLKOUT_PCIE6P NC 2 3 C2007
PCIECLKRQ6# T13 SC15P50V2JN-2-GP
2
PCIECLKRQ6#/GPIO45
V38 K43 CLKOUTFLEX0 1 TP2001 XTAL25_OUT XTAL-25MHZ-155-GP 1 2
FLEX CLOCKS
CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64
V37
CLKOUT_PCIE7P NC F47 SIO_14M R2016 1 2 33R2J-2-GP CLK_SIO_14M (78)
RN
PCIECLKRQ7# CLKOUTFLEX1/GPIO65
K12
PCIECLKRQ7#/GPIO46 82.30020.D41
RN2026 H47 PCI_TPM_TCM R2018 1 2 33R2J-2-GP CLK_PCI_TPM_TCM (71,77) 2nd = 82.30020.G61
CLK_BCLK_ITP# CLKOUTFLEX2/GPIO66
(71) CLK_CPU_ITP# 1 4 AK14
CLK_BCLK_ITP CLKOUT_ITPXDP_N
(71) CLK_CPU_ITP 2 3 AK13 K49 PCH_GPIO67 1 TP2005
CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67
0R4P2R-PAD
PANTHER-GP-NF
A
71.PANTH.00U A
<Core Design>
Wistron Corporation
Title
PCH (PCI-E/SMBUS/CLOCK/CL)
A2 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = PCH Layout Note:

RTC_AUX_S5 Place it at the open door location.
RN2102
1 4
2 3 Integrated SUS 1V VRM Enable
2
1
SRN20KJ-1-GP C2104 G2101 Low = External VRs
INTVRMEN
Layout Note:
Vinafix.com
SC1U6D3V2KX-GP
GAP-OPEN
High = Internal VRs*
Place near PCH
2
1228
1
D PCH1A 1 OF 10 LPC_LAD[3..0] D
LPC_LAD[3..0] (27,71,77,78)
RTC_X1 A20 C38 LPC_LAD0_PCH R2116 1 222R2J-2-GP LPC_LAD0
RTCX1 FWH0/LAD0 LPC_LAD1_PCH R2121 1
FWH1/LAD1 A38 222R2J-2-GP LPC_LAD1
LPC
RTC_X2 C20 B37 LPC_LAD2_PCH R2127 1 222R2J-2-GP LPC_LAD2
RTCX2 FWH2/LAD2 LPC_LAD3_PCH R2128 1
FWH3/LAD3 C37 222R2J-2-GP LPC_LAD3
RTC_RST# D20
Layout Note: RTCRST#
D36 LPC_LFRAME#_PCH 1 2 LPC_LFRAME# (27,71,77,78)
SRTC_RST# FWH4/LFRAME# R2136 22R2J-2-GP
Place it at the open door location. G22 SRTCRST#
1MR2J-1-GP E36
LDRQ0#
RTC
C2103 1 R2104 2 SM_INTRUDER# K22 K36 LPC_LDRQ1# LPC_LDRQ1# (78)
SC1U6D3V2KX-GP G2102 INTRUDER# LDRQ1#/GPIO23
GAP-OPEN RTC_AUX_S5 1 R2105 2 PCH_INTVRMEN C17 V5 IRQ_SERIRQ (27,77,78)
2
330KR2F-L-GP INTVRMEN SERIRQ
1 R2131
DY 2
2
330KR2F-L-GP AM3 SATA_RXN0 (56)
HDA_BITCLK SATA0RXN
N34 AM1
HDA_BCLK SATA0RXP SATA_RXP0 (56)
HDD1
SATA 6G
SATA0TXN AP7 SATA_TXN0 (56)
HDA_SYNC L34 AP5 SATA_TXP0 (56)
HDA_SYNC SATA0TXP
(82) HDA_SPKR T10 SPKR SATA1RXN AM10 SATA_RXN1 (66)

AM8
R2123 Layout Note: HDA_RST# K34 HDA_RST#

SATA1RXP
SATA1TXN AP11
SATA_RXP1
SATA_TXN1
(66)
(66) WWAN
SATA1TXP AP10 SATA_TXP1 (66)
33R2J-2-GP Place close together.
2 1 HDA_SDOUT For RNxxxx later. (82) HDA_SDIN0 E34 AD7
(82) HDA_CODEC_SDOUT HDA_SDIN0 SATA2RXN
SATA2RXP AD5
R2125 G34 AH5
33R2J-2-GP Layout Note: HDA_SDIN1 SATA2TXN
AH4
Layout Note:
HDA_RST# SATA2TXP
C
(82) HDA_CODEC_RST# 2 1 HDA_SDO and HDA_BCLK must be C34 HDA_SDIN2
HDD < 6000mil, mSATA < 6000mil, ODD < 12500mil C
IHDA
length matched to within 500 mils SATA3RXN AB8
R2126 A34 AB10
33R2J-2-GP HDA_SDIN3 SATA3RXP
SATA3TXN AF3
2 1 HDA_BITCLK R2107 AF1
(82) HDA_CODEC_BITCLK 1KR2J-1-GP HDA_SDOUT SATA3TXP
A36 HDA_SDO
SATA
(78) ME_FW P 1 2 SATA4RXN Y7
SATA4RXP Y5
PCH_GPIO33 C36 AD3
HDA_DOCK_EN#/GPIO33 SATA4TXN
SATA4TXP AD1
Flash Descriptor Security Overide/ +3.3V_ALW _PCH PCH_GPIO13 N32 HDA_DOCK_RST#/GPIO13
Intel ME Debug Mode SATA5RXN Y3
SATA5RXP Y1
Low = Default * SATA5TXN AB3
HDA_SDOUT High = Enable R2111 1 2 51R2J-2-GP PCH_JTAG_TCK J3 AB1
DY JTAG_TCK SATA5TXP
Layout Note: R2118 1 2 210R2F-L-GP PCH_JTAG_TMS H7 Y11 +1.05V_RUN
DY JTAG_TMS SATAICOMPO
JTAG
Place at the separated point
R2119 1 2 210R2F-L-GP PCH_JTAG_TDI K5 Y10 SATA_COMP R2112 1 2 37D4R2F-GP
DY JTAG_TDI SATAICOMPI
R2120 1 2 210R2F-L-GP PCH_JTAG_TDO H1 +1.05V_RUN
+3.3V_RUN DY JTAG_TDO
AB12
SATA3RCOMPO
R2106 1 2 1KR2J-1-GP HDA_SPKR AB13 SATA3_COMP R2113 1 2 49D9R2F-GP
DY SATA3COMPI
No Reboot Strap (60) SPI_CLK_R T3 AH1 RBIAS_SATA3 R2114 1 2 750R2F-GP

SPI_CLK SATA3RBIAS
B
Low = Default * (60) SPI_CS0# Y14 SPI_CS0# B
HDA_SPKR High = No Reboot
T1
(60) SPI_CS1# SPI_CS1# Layout Note:
SPI
P3 SATA_ACT# SATA_ACT# (68)
+3.3V_ALW _PCH SATALED#
Place close PCH(<500mil)
(60) SPI_SI_R V4 V14 HDD_DET#_R 1 2 HDD_DET# (56)
R2103 1 1KR2J-1-GP HDA_SYNC SPI_MOSI SATA0GP/GPIO21 R2210 0R0402-PAD-2-GP
2
100KR2J-1-GP (60) SPI_SO_R U3 P1 BBS_BIT0
SPI_MISO SATA1GP/GPIO19
1 R2132 2
DY PANTHER-GP-NF BBS_BIT0 - BIOS BOOT STRAP BIT0
71.PANTH.00U
PLL ODVR VOLTAGE
Low = 1.8V +5V_RUN
HDA_SYNC High = 1.5V Q2101
* G
+3.3V_RUN
D HDA_SYNC +3.3V_ALW _PCH
R2124
(82) HDA_CODEC_SYNC 2 1 HDA_CODEC_SYNC_R S PCH_GPIO13 1 2 BBS_BIT0 R2102 1 2 4K7R2J-2-GP
R2130
1
33R2J-2-GP 2N7002K-2-GP RTC_X1 100KR2J-1-GP PCH_GPIO33 R2129 1 2 100KR2J-1-GP

R2117 84.2N702.J31
1MR2J-1-GP2ND = 84.2N702.031 1 2 RTC_X2 IRQ_SERIRQ 1 4
3rd = 84.2N702.W31 R2101 10MR2J-L-GP HDD_DET# 2 3
2
X2101 RN2103
HDA_CODEC_BITCLK HDA_CODEC_SDOUT SRN10KJ-5-GP
A 1 4 <Core Design> A
HDA_SYNC:
2
This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V EC2102 EC2103
DY DY Wistron Corporation
SC15P50V2JN-2-GP
1
1
C2101
VccVRM supply mode. 1K external pull-up resistor is required on this 2 3

1
1
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
C2102 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

signal on the board. Signal may have leakage paths via powered off devices (Audio SC15P50V2JN-2-GP Taipei Hsien 221, Taiwan, R.O.C.
2
Codec) and hence contend with the external pull-up. A blocking FET is X-32D768KHZ-40GPU
82.30001.841 Title
recommended in such a case to isolate HDA_SYNC from the Audio Codec device 2nd = 82.30001.A41
until after the Strap sampling is complete. PCH (SPI/RTC/LPC/SATA/IHDA)
A3 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = PCH
+3.3V_RUN PCH1F 6 OF 10
RN2203
SRN10KJ-5-GP (27) SIO_EXT_SCI# 1 2 SIO_EXT_SCI#_R T7 C40 CONTACTLESS_DET#
SIO_A20GATE R2206 0R0402-PAD-2-GP BMBUSY#/GPIO0 TACH4/GPIO68
1 4
2 3 SIO_RCIN# PCH_GPIO1 A42 B41 PCH_GPIO69
2 DY 1 PCIE_MCARD1_DET#
Vinafix.com IO_LOOP# H36
TACH1/GPIO1
TACH2/GPIO6
TACH5/GPIO69
TACH6/GPIO70 C41 PCIE_MCARD3_DET#

R2202 100KR2J-1-GP
D 2 1 USB_MCARD1_DET# PCH_GPIO7 E38 A40 USB_MCARD2_DET# USB_MCARD2_DET# (66) D
R2204 100KR2J-1-GP TACH3/GPIO7 TACH7/GPIO71
(78) SIO_EXT_W AKE# SIO_EXT_W AKE# C10 GPIO8

(78) PM_LANPHY_ENABLE PM_LANPHY_ENABLE C4 LAN_PHY_PWR_CTRL/GPIO12
PCH_GPIO15 G2 P4 SIO_A20GATE SIO_A20GATE (27)
GPIO15 A20GATE
PECI AU16
PCH_GPIO16 U2 +1.05V_RUN_VTT
SATA4GP/GPIO16 SIO_RCIN#
RCIN# P5 SIO_RCIN# (27)
GPIO
PCH_GPIO17 D40 AY11 H_CPUPW RGD H_CPUPW RGD (5,71)
TACH0/GPIO17 PROCPWRGD R2211
CPU/MISC
PCH_GPIO22 T5 AY10 PCH_THERMTRIP_R 1 2
SCLOCK/GPIO22 THRMTRIP# 56R2J-4-GP
(82) PCIE_MCARD1_DET# PCIE_MCARD1_DET# E8 T14 INIT3_3V# 1 TP2213
GPIO24 INIT3_3V# +VCCDFTERM
1
PCH_GPIO27 E16 AY1 DF_TVS
GPIO27 DF_TVS C2210
(78) SLP_ME_CSW _DEV# SLP_ME_CSW _DEV# P8 SCD1U16V2KX-3GP
2
GPIO28
1
TS_VSS1 AH8
PCH_GPIO34 K1 R2207
STP_PCI#/GPIO34
TS_VSS2 AK11 2K2R2J-2-GP
(82) USB_MCARD1_DET# USB_MCARD1_DET# K4 GPIO35
AH10
2
PCH_GPIO36 TS_VSS3 R2209
V8 SATA2GP/GPIO36
AK10 DF_TVS 1 2
TS_VSS4 H_SNB_IVB# (5)
PCH_GPIO37 M5
C SATA3GP/GPIO37 Layout Note: 1KR2F-L-GP C
TPM_ID0 N2 P37 Check these four balls are connected firstly, then to GND
SLOAD/GPIO38 NC_1
+3.3V_ALW _PCH TPM_ID1 M3 SDATAOUT0/GPIO39 +3.3V_RUN
(79) FFS_INT2 FFS_INT2 V13 BG2 PCH_NCTF_BG2 1 TP2203 TPAD14-OP-GP
SDATAOUT1/GPIO48 VSS_NCTF_15#BG2
1
R2205 (78) TEMP_ALERT# TEMP_ALERT# V3 BG48 PCH_NCTF_BG48 1 TP2204 TPAD14-OP-GP USB_MCARD2_DET# 2 1

SATA5GP/GPIO49/TEMP_ALERT# VSS_NCTF_16#BG48 R2254 100KR2J-1-GP
4K7R2J-2-GP
(69) KB_DET# KB_DET# D6 BH3 PCH_NCTF_BH3 1 TP2205 TPAD14-OP-GP PCIE_MCARD3_DET# 2 1
GPIO57 VSS_NCTF_17#BH3 R7848 100KR2J-1-GP
2
BH47 PCH_NCTF_BH47 1 TP2206 TPAD14-OP-GP

SLP_ME_CSW _DEV# VSS_NCTF_18#BH47
A4 BJ4 SIO_RCIN# 2 1
VSS_NCTF_1#A4 VSS_NCTF_19#BJ4 R2230 10KR2J-3-GP
NCTF
1
Note: PCH has internal pull up 20k ohm on A44 VSS_NCTF_2#A44 VSS_NCTF_20#BJ44 BJ44 SIO_EXT_SCI# 2 1
DY R2252 E3_PAID_TS_DET#(GPIO27) R2231 10KR2J-3-GP
1KR2F-3-GP A45 BJ45 PCH_GPIO1 2 1
VSS_NCTF_3#A45 VSS_NCTF_21#BJ45 R7849 100KR2J-1-GP
A46 BJ46 PCH_GPIO36 2 DY 1
2
SLP_ME_CSW_DEV# PULL ON DIE VR ENABLE VSS_NCTF_4#A46 VSS_NCTF_22#BJ46 R2232 10KR2J-3-GP

A5 BJ5 PCH_GPIO37 2 DY 1
VSS_NCTF_5#A5 VSS_NCTF_23#BJ5 R2249 1KR2F-3-GP
ENABLED HIGH(DEFAULT) A6 VSS_NCTF_6#A6 VSS_NCTF_24#BJ6 BJ6 PCH_GPIO16 2 1
A4,A44,A45,A46,A5,A6,B3,B47,
BJ45,BJ46,BJ5,BJ6,C2,C48,D1,
R2233 10KR2J-3-GP
BD1,BD49,BE1,BE49,BF1,BF49,
BG2,BG48,BH3,BH47,BJ4,BJ44,
TPAD14-OP-GP TP2211 1 PCH_NCTF_B3 B3 C2 PCH_NCTF_C2 1 TP2207 TPAD14-OP-GP TEMP_ALERT# 2 1
DISABLED LOW VSS_NCTF_7#B3 VSS_NCTF_25#C2 R2234 10KR2J-3-GP
TPAD14-OP-GP TP2212 1 PCH_NCTF_B47 B47 C48 PCH_NCTF_C48 1 TP2208 TPAD14-OP-GP PCH_GPIO22 2 1
VSS_NCTF_8#B47 VSS_NCTF_26#C48 R2235 10KR2J-3-GP
B B
D49,E1,E49,F1,F49
BD1 D1 PCH_GPIO7 2 1
VSS_NCTF_9#BD1 VSS_NCTF_27#D1 R2236 10KR2J-3-GP
NCTF TEST PIN:

BD49 D49 PCH_GPIO17 2 1
VSS_NCTF_10#BD49 VSS_NCTF_28#D49 R2222 8K2R2J-3-GP
BE1 E1 IO_LOOP# 2 1
VSS_NCTF_11#BE1 VSS_NCTF_29#E1 R2237 10KR2J-3-GP
BE49 E49 PCH_GPIO34 2 1
VSS_NCTF_12#BE49 VSS_NCTF_30#E49 R2238 10KR2J-3-GP
+3.3V_ALW _PCH BF1 F1 CONTACTLESS_DET# 2 1
VSS_NCTF_13#BF1 VSS_NCTF_31#F1 R2239 10KR2J-3-GP
BF49 VSS_NCTF_14#BF49 VSS_NCTF_32#F49 F49
2 1 SIO_EXT_W AKE#
R2245 10KR2J-3-GP
2 1 PCH_GPIO15 PANTHER-GP-NF PCH_GPIO36 2 1
R7851 1KR2F-3-GP 71.PANTH.00U R2240 10KR2J-3-GP
2 1 PCH_GPIO27 PCH_GPIO37 2 1
R2247 10KR2J-3-GP R2241 10KR2J-3-GP
2 1 KB_DET# PCH_GPIO17 1 DY 2
R2248 10KR2J-3-GP +3.3V_RUN +3.3V_RUN R2250 1KR2F-3-GP
2 1 PCIE_MCARD1_DET# PCH_GPIO16 2 DY 1
R2201 100KR2J-1-GP R2242 10KR2J-3-GP
2 DY 1 PM_LANPHY_ENABLE PCH_GPIO69 1 2
1
R2246 10KR2J-3-GP R2214 1K5R2F-2-GP

R2243 R2223
10KR2J-3-GP 20KR2J-L2-GP
TPM_ID0 TPM_ID1
2
<Core Design>
A TPM_ID0 TPM_ID1 No TPM, No China TPM 0 1 A
Wistron Corporation
1
TPM 1 1
R2244 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
DY 10KR2J-3-GP
TBD Title
2
PCH (GPIO/CPU)
A3 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = PCH +5V_RUN
SC1U6D3V2KX-GP
1
C2325
2325
U2305
DY
C
10 uf x1 1
POWER
2
PCH1G 7 OF 10 3D3V_LDO_DAC +3.3V_RUN 3D3V_LDO_DAC EN
2
+1.05V_RUN
1.7A
1 uf x3
Vinafix.com 0.061A R2309 L2301
3
4
GND
VIN DY
SC10U6D3V3MX-GP
VCCDAC VOUT
AA23 VCCCORE1 VCCADAC U48 1 2 2 1 5 NC#5
D AC23 VCCCORE2 D
1
SCD01U50V2KX-1GP
C2301
C2302
C2303
C2304
C2315
AD21 C2313 C2314 0R0603-PAD-2-GP MMZ1608S181C-GP DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DY
SC10U6D3V5KX-1GP
CRT
VCCCORE3
SCD1U16V2KX-3GP
AD23 U47 68.00040.201 C2324 G9091-330T12U-GP
VCCCORE4 VSSADAC SC10U10V5ZY-1GP
AF21
2
VCC CORE
VCCCORE5
AF23
2
2
VCCCORE6 +3.3V_RUN
AG21 VCCCORE7 0.001A
AG23 VCCCORE8
AG24 AK36 +3VS_VCCA_LVDS 1 2
VCCCORE9 VCCALVDS R2308 0R0402-PAD-2-GP
AG26 VCCCORE10
AG27 VCCCORE11 VSSALVDS AK37
AG29 VCCCORE12
Refer to chipset EDS V.0.7
AJ23 VCCCORE13 +1.8V_RUN
LVDS
AJ26 VCCCORE14 VCCTX_LVDS1 AM37 Voltage Rail Voltage(V) Iccmax(A)
AJ27 0.04A L2302
VCCCORE15
AJ29 AM38 +1.8VS_VCCTX_LVDS 2 1 V_PROC_IO 1.05 0.001
SC22U6D3V5MX-2GP
VCCCORE16 VCCTX_LVDS2
AJ31 VCCCORE17
+1.05V_RUN
C2316
C2317
C2318
AP36 MMZ1608S181C-GP V5REF 5 0.001
VCCTX_LVDS3
1
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
68.00040.201
AP37 V5REF_Sus 5 0.001
VCCTX_LVDS4
AN19
2
VCCIO28
Vcc3_3 3.3 0.228
TPAD14-OP-GP TP2301 1 VCCAPLLEXP BJ22 +3.3V_RUN VccADAC 3.3 0.063
VCCAPLLEXP
0.228A
VCC3_3_6 V33 VccADPLLA 1.05 0.08
HVCMOS
AN16 VCCIO15
1
VccADPLLB 1.05 0.08
AN17 C2319
VCCIO16
V34 SCD1U16V2KX-3GP VccCore 1.05 1.7
2
C VCC3_3_7 C
10 uf x4 AN21 VccDMI 1.1 0.047
VCCIO17
+1.05V_RUN 1 uf x3 +1.05V_+1.5V_1.8V_RUN VccIO 1.05 3.711
3.711A AN26 VCCIO18
0.167A
AN27 VCCIO19 VCCVRM3 AT16 VccASW 1.05 0.903
+1.05VS_VCC_DMI +1.05V_RUN_VTT
C2306
C2309
AP21 0.047A VccSPI 3.3 0.01

SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VCCIO20
1
1
EC2305
SCD1U16V2KX-3GP
C2307 C2308
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
AP23 AT20 1 2 VccDSW3_3 3.3 0.001

DY DY VCCIO21 VCCDMI1 R2306 0R0402-PAD-2-GP
2
1
DMI
AP24 VCCIO22
VccDFTERM 1.8 0.002
VCCIO
C2320
AP26 AB36 SC1U6D3V2KX-GP VccRTC 3.3 6uA
2
VCCIO23 VCCCLKDMI
AT24 VCCIO24 0.07A VccSus3_3 3.3 0.095
+1.05V_RUN
VccSusHDA 3.3 0.01
AN33 +1.05VS_VCC_DMI_CCI 1 2
VCCIO25 R2307 0R0603-PAD-2-GP VccVRM 1.5 0.167
1
AN34 VCCIO26 VCCDFTERM1 AG16
+3.3V_RUN C2321 VccClkDMI 1.05 0.07
0.228A SC1U6D3V2KX-GP
2
BH29 VCC3_3_3 VCCDFTERM2 AG17 VccSSC 1.05 0.095
DFT / SPI
1
VccDIFFCLKN 1.05 0.055

C2310 +1.05V_+1.5V_1.8V_RUN AJ16
VCCDFTERM3 +VCCDFTERM +1.8V_RUN
SCD1U16V2KX-3GP 0.002A VccALVDS 3.3 0.001
2
AP16 VCCVRM2
B B
VCCDFTERM4 AJ17 1 2 VccTX_LVDS 1.8 0.04
R2312 0R0603-PAD-2-GP
1
TPAD14-OP-GP TP2302 1VCCFDIPLL BG6 VCCAFDIPLL C2322
+1.05V_RUN SCD1U16V2KX-3GP
2
AP17 VCCIO27
V1
FDI
+1.05V_RUN_VTT VCCSPI +3.3V_M

AU20 VCCDMI2 0.01A
PANTHER-GP-NF 1
71.PANTH.00U C2323
SC1U6D3V2KX-GP
2
+1.05V_+1.5V_1.8V_RUN +1.5V_RUN
A <Core Design> A
1 2
R2311 0R0603-PAD-2-GP
Wistron Corporation
Title
PCH (POWER1)
A3 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = PCH
PCH1J POWER 10 OF 10 +1.05V_RUN
TPAD14-OP-GP TP2401 1 VCCACLK AD49 N26

+3.3V_ALW _PCH VCCACLK VCCIO29
0.001A
1
VCCIO30 P26
DG: none T16 C2438 +VCCA_USBSUS
VCCDSW3_3 SC1U6D3V2KX-GP
P28
CRB: 10uH
Vinafix.com
2
VCCIO31
1
1
+3.3V_RUN TP2402 DCPSUSBYP
C2416 TPAD14-OP-GP
1 V12 DCPSUSBYP VCCIO32 T27
DY C2437
SC1U10V2KX-1GP
2
D L2401 SCD1U16V2KX-3GP T29 D
2
+V3.3S_VCC_CLKF33 +V3.3S_VCC_CLKF33 VCCIO33 +3.3V_ALW _PCH
1 2 T38 VCC3_3_5
IND-10UH-218-GP 0.095A
1
68.10050.10Y VCCSUS3_3_7 T23
2nd = 68.1001E.10N C2402 TP2403 1 +VCCAPLL_CPY_PCH BH23 +3.3V_ALW _PCH
DY VCCAPLLDMI2
1
C2401 SC1U6D3V2KX-GP TPAD14-OP-GP T24 C2424 +5V_ALW _PCH
2
SC10U6D3V5KX-1GP VCCSUS3_3_8 SCD1U16V2KX-3GP
+1.05V_RUN AL29 VCCIO14
2
V23
2
VCCSUS3_3_9
USB
83.R0304.A8F D2401
TP2404 1 +VCCSUS1 AL24 V24 2nd = 83.R3004.A8F CH751H-40PT-GP
TPAD14-OP-GP DCPSUS3 VCCSUS3_3_10 +3.3V_ALW _PCH 3rd = 83.R2004.M8F
P24
1
VCCSUS3_3_6 +5VA_PCH_VCC5REFSUS
(0.1uFx1) 1 R2408 2
1
+1.05V_M 22 uf x2 AA19 C2425 10R2F-L-GP
VCCASW1 SCD1U16V2KX-3GP
0.93A 1 uf x3 VCCIO34 T26 +1.05V_RUN
1
AA21 0.001A C2426
2
VCCASW2 SCD1U16V2KX-3GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
C2406
SC1U6D3V2KX-GP
C2405
SC1U6D3V2KX-GP
C2419
SC1U6D3V2KX-GP
AA24 M26 +5VA_PCH_VCC5REFSUS
2
VCCASW3 V5REF_SUS
1
1
+3.3V_ALW _PCH
C2403
C2404
AA26
DY
Clock and Miscellaneous

VCCASW4 +VCCA_USBSUS
AN23
DY DY
2
2
DCPSUS4
AA27 VCCASW5
AN24 +3.3V_RUN +5V_RUN
VCCSUS3_3_1
AA29 VCCASW6
1
C2434
2
+1.05V_RUN SCD1U16V2KX-3GP
AA31 VCCASW7 0.001A D2402
83.R0304.A8F
2
AC26 P34 +5VS_PCH_VCC5REF 2nd = 83.R3004.A8F CH751H-40PT-GP
VCCASW8 V5REF
3rd = 83.R2004.M8F
C AC27 C
1
VCCASW9 +3.3V_ALW _PCH +5VS_PCH_VCC5REF
VCCSUS3_3_2 N20 1 R2409 2
0.08A 10R2F-L-GP
PCI/GPIO/LPC
AC29 VCCASW10
1
L2402 N22
+1.05VS_VCCA_A_DPL VCCSUS3_3_3 C2427
1 2 AC31 VCCASW11
1
IND-10UH-218-GP P20 +3.3V_RUN SC1U6D3V2KX-GP
2
VCCSUS3_3_4
1
1
C2408
68.10050.10Y AD29 C2428

SC10U6D3V5KX-1GP
VCCASW12
1
2nd = 68.1001E.10N C2407 P22 SC1U6D3V2KX-GP

DY
2
TC2402 VCCSUS3_3_5
SC1U6D3V2KX-GP AD31 Refer to chipset EDS V.0.7
DY
2
VCCASW13
1
ST220U2D5VAM-GP C2430
2
W21 AA16 SCD1U16V2KX-3GP Voltage Rail Voltage(V) Iccmax(A)

VCCASW14 VCC3_3_1
2
W23 W16 +3.3V_RUN V_PROC_IO 1.05 0.001
VCCASW15 VCC3_3_8
0.08A
L2403 W24 VCCASW16 VCC3_3_4 T34 V5REF 5 0.001
1 2 +1.05VS_VCCA_B_DPL
1
IND-10UH-218-GP W26 VCCASW17
C2431 V5REF_Sus 5 0.001
1
1
EC2409
SCD1U16V2KX-3GP
68.10050.10Y SCD1U16V2KX-3GP
1
2nd = 68.1001E.10N C2410 W29 +3.3V_RUN Vcc3_3 3.3 0.228
2
TC2401 VCCASW18
SC1U6D3V2KX-GP
DY
2
ST220U2D5VAM-GP W31 AJ2 VccADAC 3.3 0.063

2
VCCASW19 VCC3_3_2
1
W33 VCCASW20
C2429 VccADPLLA 1.05 0.08
AF13 SCD1U16V2KX-3GP
VCCIO5
VccADPLLB 1.05 0.08
2
+VCCRTCEXT N16 DCPRTC +1.05V_RUN VccCore 1.05 1.7
VCCIO12 AH13
1
X03 2/16 0.167A

C2411 +1.05V_+1.5V_1.8V_RUN Y49 VCCVRM4 VCCIO13 AH14 VccDMI 1.1 0.047
1
B SCD1U16V2KX-3GP B
2
C2432 VccIO 1.05 3.711

AF14 SC1U6D3V2KX-GP DY
2
VCCIO6
+1.05VS_VCCA_A_DPL BD47 VCCADPLLA
VccASW 1.05 0.903
SATA
VCCAPLLSATA AK1
+1.05VS_VCCA_B_DPL BF47 VCCADPLLB
VccSPI 3.3 0.01
+V1.05S_VCCAPLL_SATA3 1 TP2406
+1.05V_RUN +VCCDIFFCLKN TPAD14-OP-GP VccDSW3_3 3.3 0.001
0.055AR2412 +VCCDIFFCLK VCCVRM1 AF11 +1.05V_+1.5V_1.8V_RUN
AF17 VCCIO7
1 2 AF33 VCCDIFFCLKN1
VccDFTERM 1.8 0.002
0R0603-PAD-2-GP AF34 AC16
VCCDIFFCLKN2 VCCIO2
1
AG34 VCCDIFFCLKN3
VccRTC 3.3 6uA
C2414 AC17 +1.05V_RUN
VCCIO3
SC1U6D3V2KX-GP VccSus3_3 3.3 0.095
2
+V1.05S_SSCVCC AG33 AD17

VCCSSC VCCIO4
VccSusHDA 3.3 0.01
1
+VCCSST V16 C2435 VccVRM 1.5 0.167
DCPSST
1
+1.05V_M SC1U6D3V2KX-GP
2
C2415 VccClkDMI 1.05 0.07
SCD1U16V2KX-3GP T17 T21
2
TP2405 DCPSUS DCPSUS1 VCCASW22 VccSSC 1.05 0.095

1 V19 DCPSUS2
TPAD14-OP-GP
MISC
+1.05V_RUN_VTT V21 VccDIFFCLKN 1.05 0.055

+1.05V_RUN VCCASW23
0.001A
SCD1U16V2KX-3GP
CPU
R2403 BJ8 V_PROC_IO

VccALVDS 3.3 0.001
C2418
1 2 +VCCDIFFCLK 4.7 uf x1 T19

VCCASW21
1
C2420 +3VS_+1.5VS_HDA_IO +3.3V_ALW _PCH VccTX_LVDS 1.8 0.04

0.1 uf x1
1
A 0R0402-PAD-2-GP C2417 SCD1U16V2KX-3GP <Core Design> A

C2412 SC4D7U6D3V3KX-GP 0.01A R2402
2
HDA
SC1U6D3V2KX-GP A22 P32 1 2

RTC
2
RTC_AUX_S5 VCCRTC VCCSUSHDA 0R0402-PAD-2-GP

Wistron Corporation
1
6uA C2433
+1.05V_RUN PANTHER-GP-NF SCD1U16V2KX-3GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
0.095A
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
R2404 71.PANTH.00U Taipei Hsien 221, Taiwan, R.O.C.

2
1 2 +V1.05S_SSCVCC
1
1
C2421
C2422
Title
1
0R0402-PAD-2-GP C2436
C2413 SC1U6D3V2KX-GP VCCSUSHDA need to be at either 3.3V or 1.5V. PCH (POWER2)
2
SC1U6D3V2KX-GP All the CODEC I/O Voltages need to be at the same Size Document Number Rev
2
A3 A00
level either 3.3 V or 1.5 V. Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = PCH
PCH1I 9 OF 10
AY4 VSS159 VSS259 H46

AY42 VSS160 VSS260 K18
B11 K46
Vinafix.com B15
B19
VSS163
VSS164
VSS165
VSS263
VSS264
VSS265
K7
L18
B23 VSS166 VSS266 L2
D B27 VSS167 VSS267 L20 D
PCH1H 8 OF 10 B31 L26
VSS168 VSS268
H5 VSS0 B35 VSS169 VSS269 L28
B39 VSS170 VSS270 L36
AA17 VSS1 VSS80 AK38 B7 VSS171 VSS271 L48
AA2 VSS2 VSS81 AK4 F45 VSS172 VSS272 M12
AA3 VSS3 VSS82 AK42 BB12 VSS173 VSS273 P16
AA33 VSS4 VSS83 AK46 BB16 VSS174 VSS274 M18
AA34 VSS5 VSS84 AK8 BB20 VSS175 VSS275 M22
AB11 VSS6 VSS85 AL16 BB22 VSS176 VSS276 M24
AC19 VSS13 VSS92 AL27 BC14 VSS183 VSS283 M46
AC2 VSS14 VSS93 AL31 BC18 VSS184 VSS284 M8
AC21 VSS15 VSS94 AL33 BC2 VSS185 VSS285 N18
AC24 VSS16 VSS95 AL34 BC22 VSS186 VSS286 P30
AC33 VSS17 VSS96 AL48 BC26 VSS187 VSS287 N47
AC34 VSS18 VSS97 AM11 BC32 VSS188 VSS288 P11
AC48 VSS19 VSS98 AM14 BC34 VSS189 VSS289 P18
AD10 VSS20 VSS99 AM36 BC36 VSS190 VSS290 T33
AD11 VSS21 VSS100 AM39 BC40 VSS191 VSS291 P40
AD19 VSS24 VSS103 AM46 BD46 VSS194 VSS294 P7
AD24 VSS25 VSS104 AM7 BD5 VSS195 VSS295 R2
C AD26 AN2 BE22 R48 C
VSS26 VSS105 VSS196 VSS296
AD27 VSS27 VSS106 AN29 BE26 VSS197 VSS297 T12
AD33 VSS28 VSS107 AN3 BE40 VSS198 VSS298 T31
AD34 VSS29 VSS108 AN31 BF10 VSS199 VSS299 T37
AD36 VSS30 VSS109 AP12 BF12 VSS200 VSS300 T4
AD37 VSS31 VSS110 AP19 BF16 VSS201 VSS301 W34
AD40 VSS35 VSS114 AP38 BF26 VSS205 VSS305 V11
AD43 VSS37 VSS116 AP42 BD3 VSS207 VSS307 V26
AD8 VSS40 VSS119 AR2 BF40 VSS210 VSS310 V31
AE2 VSS41 VSS120 AR48 BF8 VSS211 VSS311 V36
AE3 VSS42 VSS121 AT11 BG17 VSS212 VSS312 V39
AF10 VSS43 VSS122 AT13 BG21 VSS213 VSS313 V43
AF12 VSS44 VSS123 AT18 BG33 VSS214 VSS314 V7
AD14 VSS45 VSS124 AT22 BG44 VSS215 VSS315 W17
AD16 VSS46 VSS125 AT26 BG8 VSS216 VSS316 W19
AF16 VSS47 VSS126 AT28 BH11 VSS217 VSS317 W2
AF26 VSS50 VSS129 AT34 BH19 VSS220 VSS320 Y12
AF27 VSS51 VSS130 AT39 H10 VSS221 VSS321 Y38
B B
AF4 VSS55 VSS134 AU24 BH35 VSS225 VSS325 Y8
AF42 VSS56 VSS135 AU30 BH39 VSS226 VSS328 BG29
AF46 VSS57 VSS136 AV16 BH43 VSS227 VSS329 N24
AF5 VSS58 VSS137 AV20 BH7 VSS228 VSS330 AJ3
AF7 VSS59 VSS138 AV24 D3 VSS229 VSS331 AD47
AF8 VSS60 VSS139 AV30 D12 VSS230 VSS333 B43
AG19 VSS61 VSS140 AV38 D16 VSS231 VSS334 BE10
AG2 VSS62 VSS141 AV4 D18 VSS232 VSS335 BG41
AG31 VSS63 VSS142 AV43 D22 VSS233 VSS337 G14
AG48 VSS64 VSS143 AV8 D24 VSS234 VSS338 H16
AH11 VSS65 VSS144 AW14 D26 VSS235 VSS340 T36
AH3 VSS66 VSS145 AW18 D30 VSS236 VSS342 BG22
AH36 VSS67 VSS146 AW2 D32 VSS237 VSS343 BG24
AH39 VSS68 VSS147 AW22 D34 VSS238 VSS344 C22
AH40 VSS69 VSS148 AW26 D38 VSS239 VSS345 AP13
AH42 VSS70 VSS149 AW28 D42 VSS240 VSS346 M14
AH46 VSS71 VSS150 AW32 D8 VSS241 VSS347 AP3
AH7 VSS72 VSS151 AW34 E18 VSS242 VSS348 AP1
AJ19 VSS73 VSS152 AW36 E26 VSS243 VSS349 BE16
AJ21 VSS74 VSS153 AW40 G18 VSS244 VSS350 BC16
AJ24 VSS75 VSS154 AW48 G20 VSS245 VSS351 BG28
AJ33 VSS76 VSS155 AV11 G26 VSS246 VSS352 BJ28
AJ34 VSS77 VSS156 AY12 G28 VSS247
AK12 VSS78 VSS157 AY22 G36 VSS248
AK3 VSS79 VSS158 AY28 G48 VSS249
H12 VSS250
PANTHER-GP-NF H18 VSS251
71.PANTH.00U H22 VSS252
A H24 VSS253 <Core Design> A
H26 VSS254
H30 VSS255
H32
H34
VSS256
VSS257
Wistron Corporation
F3 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
VSS258 Taipei Hsien 221, Taiwan, R.O.C.
Title
PANTHER-GP-NF
71.PANTH.00U PCH (VSS)
A3 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = KBC +3.3V_ALW

RTC_AUX_S5
1
RTC_AUX_S5 +3.3V_ALW
R2701 R2712 DY
1 2
1
C2701 2 1 +RTC_CELL_EC 100KR2J-1-GP
U2701 SCD1U16V2KX-3GP C2715
SC10U6D3V3MX-GP
1 5 0R0402-PAD-2-GP SC1U6D3V2KX-GP
2
(48) VCCSAPWROK
1
A VCC
SCD1U16V2KX-3GP
C2702
C2703
SCD1U16V2KX-3GP
C2704
SCD1U16V2KX-3GP
C2705
SCD1U16V2KX-3GP
C2706
SCD1U16V2KX-3GP
C2707
SCD1U16V2KX-3GP
C2708
SCD1U16V2KX-3GP
C2709
SCD1U16V2KX-3GP
C2710
SCD1U16V2KX-3GP
C2711
(45,48) 1.05V_VTTPWRGD 2 R2713
B
2
3 4 1 2 KBC_PWRBTN# (68)
GND Y 1.05V_0.8V_PWROK (42) (28) POWER_SW_IN#
B64
A11
A22
B35
A41
A58
A52
A26
B3
10KR2J-3-GP
Vinafix.com
73.01G08.EHG U2702
1
2ND = 73.7SZ08.DAH C2714
VBAT
VTR
VTR
VTR
VTR
VTR
VTR
VTR
VTR
3rd = 73.7SZ08.EAH SC1U6D3V2KX-GP
+3.3V_ALW
2
BC_INT#_EMC4022
D 1
R2780
DY 2
100KR2J-1-GP SML1_SMBDATA SYSTEM_ID
D
(20) SML1_SMBDATA A5 A10
PCIE_WAKE# SML1_SMBCLK GPIO7/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA GPIO21/RC_ID1 BOARD_ID
1 2 (20) SML1_SMBCLK B6 B10
R2757 10KR2J-3-GP GPIO10/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK GPIO20/RC_ID2 DDR_ON
A37 B14 DDR_ON (46)
BC_DAT_EMC4022 (69) CLK_TP_SIO GPIO110/PS2_CLK2/GPTP_IN6 GPIO25/UART_CLK HOST_DEBUG_TX
1 2 (69) DAT_TP_SIO B40 B44 HOST_DEBUG_TX (82)
R2758 100KR2J-1-GP GPIO112 GPIO111/PS2_DAT2/GPTP_OUT6 GPIO120/UART_TX HOST_DEBUG_RX
A38 B46 HOST_DEBUG_RX (82)
BC_DAT_ECE5048 GPIO113 GPIO112/PS2_CLK1A GPIO124/GPTP_OUT5/UART_RX RUNPWROK
1 2 B41 B26
R2759 100KR2J-1-GP GPIO114 GPIO113/PS2_DAT1A VCC_PWRGD EN_INVPWR RUNPWROK (5,78)
A39 A25
GPIO115 GPIO114/PS2_CLK0A GPIO60/KBRST EN_INVPWR (49)
B42 B36
GPIO115/PS2_DAT0A GPIO101/ECGP_SCLK
(39) PBAT_SMBDAT B59 B37
PBAT_SMBDAT GPIO154/I2C1C_DATA/PS2_CLK1B GPIO103/ECGP_MISO
1 2 A56 B38
R2761 2K2R2J-2-GP (39) PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B GPIO105/ECGP_MOSI DDR_HVREF_RST_GATE
A34
PBAT_SMBCLK GPIO102/HSPI_SCLK DYN_TUR_CURRNT_SET# DDR_HVREF_RST_GATE (5)
1 2 A35
R2762 2K2R2J-2-GP GPIO104/HSPI_MISO CPU1.5V_S3_GATE DYN_TUR_CURRNT_SET# (40)
A36
LPC_LDRQ#_MEC GPIO106/HSPI_MOSI MSDATA CPU1.5V_S3_GATE (36)
1
R2763
DY 2
100KR2J-1-GP JTAG_TDI GPIO116/MSDATA
A40
MSCLK
MSDATA (82)
A51 B43 MSCLK (82)
CHARGER_SMBDAT JTAG_TDO GPIO145/I2C1K_DATA/JTAG_TDI GPIO117/MSCLK
1 2 B55 A45 SIO_A20GATE (22)
R2764 2K2R2J-2-GP JTAG_CLK GPIO146/I2C1K_CLK/JTAG_TDO GPIO127/A20M
B56 A55 PSID_EC (38)
CHARGER_SMBCLK JTAG_TMS GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO153/LED3
1 2 A53 A57
R2765 2K2R2J-2-GP JTAG_RST# GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO156/LED1
B57 B61
GPU_SMBDAT JTAG_RST# GPIO157/LED2 FWP#
1 2 B65
R2768 2K2R2J-2-GP FWP# PROCHOT#_EC
A46
GPU_SMBCLK PROCHOT#/PWM4
1 2
R2769 2K2R2J-2-GP
1 2 LCD_SMBCLK DOCK_POR_RST# B22
R2770 2K2R2J-2-GP GPIO50/FAN_TACH1
A21 B2
LCD_SMBDAT AUX_ON_R GPIO51/FAN_TACH2 GPIO1/ECSPI_CS1
1 2 B23 A2
R2771 2K2R2J-2-GP (82) AUX_ON_R GPIO52/FAN_TACH3 GPIO2/ECSPI_CS2
B24 B8
DOCK_SMB_DAT PCH_ALW_ON GPIO53/PWM0 GPIO14/GPTP_IN7/HSPI_CS1
1 2 A23 B18
R2772 2K2R2J-2-GP (36) PCH_ALW_ON GPIO54/PWM1 GPIO40/GPTP_OUT3/HSPI_CS2
B25 A8
DOCK_SMB_CLK (49) BIA_PWM_EC GPIO55/PWM2 GPIO15/GPTP_OUT7 ME_SUS_PWR_ACK (19)
1 2 A24 B9 1.35V_SUS_PWRGD (46)
R2773 2K2R2J-2-GP GPIO56/PWM3 GPIO16/GPTP_IN8 R2705
A9
BAY_SMBDAT GPIO17/GPTP_OUT8 1.05V_A_PWRGD_SIO PM_APWROK (19)
1 2 A14 1 2 1.05V_A_PWRGD (45)
R2774 2K2R2J-2-GP GPIO26/GPTP_IN1 +3.3V_ALW_PCH
B15 PWR_5V3D3V_PGOOD (41)
BAY_SMBCLK BC_CLK_ECE5048 GPIO27/GPTP_OUT1 DEVICE_DET# 0R0402-PAD-2-GP
1 2 A43 A17
R2775 2K2R2J-2-GP (78) BC_CLK_ECE5048 BC_DAT_ECE5048 GPIO123/BCM_A_CLK GPIO41 RESET_OUT#
(78) BC_DAT_ECE5048 B45 B39
DYN_TUR_CURRNT_SET# BC_INT#_ECE5048 GPIO122/BCM_A_DAT GPIO107/RESET_OUT# RESET_OUT# (19)
1 2 (78) BC_INT#_ECE5048 A42 A44
R2776 100KR2J-1-GP BC_CLK_EMC4022 GPIO121/BCM_A_INT# GPIO125/GPTP_IN5 PCH_RSMRST# AC_PRESENT R2716
A12 B47 2 1 10KR2J-3-GP
1.05V_A_PWRGD_SIO (28) BC_CLK_EMC4022 BC_DAT_EMC4022 GPIO22/BCM_B_CLK GPIO126 AC_PRESENT PCH_RSMRST# (37)
1 DY 2 (28) BC_DAT_EMC4022 BC_INT#_EMC4022
B13
GPIO23/BCM_B_DAT GPIO151/GPTP_IN4
A54
AC_PRESENT (19)
R2777 100KR2J-1-GP A13 B58
(28) BC_INT#_EMC4022 GPIO24/BCM_B_INT# GPIO152/GPTP_OUT4 SIO_PWRBTN# (19)
1 2 CARD_SMBDAT B20
R2782 2K2R2J-2-GP PCH_PCIE_WAKE# A18 GPIO44/BCM_C_CLK
C C
CARD_SMBCLK (19) PCH_PCIE_WAKE# PCIE_WAKE# GPIO43/BCM_C_DAT +5V_RUN
1 2 (66,82) PCIE_WAKE# B19
R2783 2K2R2J-2-GP BC_CLK_ECE1117 A20 GPIO42/BCM_C_INT# DOCK_SMB_DAT
A3
USH_SMBDAT (69) BC_CLK_ECE1117 BC_DAT_ECE1117 B21 GPIO47/LSBCM_D_CLK GPIO3/I2C1A_DATA DOCK_SMB_CLK
1 2 (69) BC_DAT_ECE1117 B4
R2784 2K2R2J-2-GP BC_INT#_ECE1117 A19 GPIO46/LSBCM_D_DAT GPIO4/I2C1A_CLK LCD_SMBDAT GPIO112 R2717
(69) BC_INT#_ECE1117 A4 2 1 4K7R2J-2-GP
USH_SMBCLK BEEP GPIO45/LSBCM_D_INT# GPIO5/I2C1B_DATA LCD_SMBCLK GPIO113 R2718
1 2 A16 B5 2 1 4K7R2J-2-GP
R2785 2K2R2J-2-GP (82) BEEP SIO_SLP_S5# GPIO32/GPTP_IN3/BCM_E_CLK GPIO6/I2C1B_CLK BAY_SMBDAT GPIO114 R2719
(19,36) SIO_SLP_S5# B16 B7 2 1 4K7R2J-2-GP
HOST_DEBUG_TX ACAV_IN_NB GPIO31/GPTP_OUT2/BCM_E_DAT GPIO12/I2C1H_DATA/I2C2D_DATA BAY_SMBCLK GPIO115 R2720
1 2 (40) ACAV_IN_NB A15 A7 2 1 4K7R2J-2-GP
R2702 10KR2J-3-GP GPIO30/GPTP_IN2/BCM_E_INT# GPIO13/I2C1H_CLK/I2C2D_CLK GPU_SMBDAT
B48
HOST_DEBUG_RX GPIO130/I2C2A_DATA GPU_SMBCLK +3.3V_RUN
1 2 B49
R2704 10KR2J-3-GP GPIO131/I2C2A_CLK CHARGER_SMBDAT
A47 CHARGER_SMBDAT (40)
MSCLK SIO_EXT_SMI# GPIO132/I2C1G_DATA CHARGER_SMBCLK
1 2 A6 B50
R2714 10KR2J-3-GP (18) SIO_EXT_SMI# SIO_RCIN# GPIO11/SMI# GPIO140/I2C1G_CLK CARD_SMBDAT CHARGER_SMBCLK (40)
A27 B52
(22) SIO_RCIN# LPC_LDRQ#_MEC GPIO61/LPCPD# GPIO141/I2C1F_DATA/I2C2B_DATA CARD_SMBCLK
B29 A49
IRQ_SERIRQ LDRQ# GPIO142/I2C1F_CLK/I2C2B_CLK USH_SMBDAT
A28 B53
(21,77,78) IRQ_SERIRQ PLT_RST# SER_IRQ GPIO143/I2C1E_DATA USH_SMBCLK
(18,66,71,77,78,82) PLT_RST# B30
LRESET# GPIO144/I2C1E_CLK
A50 0109
CLK_PCI_MEC A29
(18) CLK_PCI_MEC PCI_CLK
1 2 MSDATA LPC_LFRAME# B31 DEVICE_DET# R2733 2 DY 1 100KR2J-1-GP
(21,71,77,78) LPC_LFRAME# LFRAME#
R2747 10KR2J-3-GP LPC_LAD0 A30
(21,71,77,78) LPC_LAD0 LAD0
1 2 DDR_ON LPC_LAD1 B32 A59
(21,71,77,78) LPC_LAD1 LAD1 BGPO0
R2748 100KR2J-1-GP LPC_LAD2 A31 B63 LAT_ON_SW#
(21,71,77,78) LPC_LAD2 LAD2 VCI_IN2#
1 2 PCH_ALW_ON LPC_LAD3 B33 A60
(21,71,77,78) LPC_LAD3 LAD3 VCI_OUT ALWON (36)
R2749 100KR2J-1-GP CLKRUN# A32 A63 VCI_IN1#
(19,77,78) CLKRUN# CLKRUN# VCI_IN1#
1 DY 2 DOCK_POR_RST# SIO_EXT_SCI# A33 B67 POWER_SW_IN#
R2750 100KR2J-1-GP (22) SIO_EXT_SCI# GPIO100/EC_SCI# VCI_IN0# +1.05V_RUN_VTT RTC_AUX_S5
B1 ACAV_IN (28,40)
EN_INVPWR VCI_OVRD_IN DOCK_PWR_SW#
1 2 A1
R2751 100KR2J-1-GP R2711 VCI_IN3# R2706 VCI_IN1# R2724 2 1 100KR2J-1-GP
1 2 1.05V_0.8V_PWROK 0R0402-PAD-2-GP MEC_XTAL1 A61 B51 +PECI_VREF 1 2
R2752 10KR2J-3-GP MEC_XTAL2 2 MEC_XTAL2_R XTAL1 PECI_VREF PECI_EC_R 0R0402-PAD-2-GP LAT_ON_SW# R2725
1 A62 A48 1 2 H_PECI (5) 2 1 100KR2J-1-GP
RESET_OUT# EC_32KHZ_ECE5048_R XTAL2 PECI R2707 43R2J-GP
1 DY 2 1 2 B62
1
(78) EC_32KHZ_ECE5048 GPIO160/32KHZ_OUT
C2712
SCD1U16V2KX-3GP
R2753 8K2R2J-3-GP R2710 0R0402-PAD-2-GP B17 R1205 close to DOCK_PWR_SW# R2781 2 1 100KR2J-1-GP
CPU1.5V_S3_GATE I2S_DAT
1 2 B27 SIO_B27 R2708 1 2 100KR2J-1-GP
U51 & least 250 mils
VSS_RO
VR_CAP
I2S_CLK
NC#B34
NC#A64
NC#B68
R2754 100KR2J-1-GP B28 SIO_B28 R2709 1 2 100KR2J-1-GP
2
AGND
PCH_RSMRST# I2S_WS
1 2
GND
VSS
VSS
R2755 10KR2J-3-GP
1 2 AUX_ON_R
R2756 2K7R2F-GP MEC5055-LZY-AUS00-GP +3.3V_M +3.3V_RUN
B34
A64
B68
B66
B11
B60
B12
B54
C1
+3.3V_ALW
1
1
15mil
15mil
R2732 R2729
B 32 KHZ Clock R2730 100KR2J-1-GP 10KR2J-3-GP B
+VR_CAP
MEC_XTAL1 10KR2J-3-GP 1 2
71.05055.B03 R2726 0R0402-PAD-2-GP
2
RUNPWROK
2
MEC_XTAL2 FWP# (28) PCH_PWRGD#
+3.3V_ALW Q2701
1
1
Q2703 Q2702 PROCHOT#_EC G
X2701 C2713 R2731 RESET_OUT# G G
(36) RUN_ON_ENABLE#
1
SC4D7U6D3V3KX-GP 10KR2J-3-GP DY D
2
R2766 H_PROCHOT# (5,40)

1219 1 4 1219 D D DY
10KR2J-3-GP S
2
1
1
C2724
SC39P50V2JN-1GP
C2723
SC39P50V2JN-1GP
S S
2N7002K-2-GP
2
JTAG_RST# 2 3 2N7002K-2-GP 2N7002K-2-GP 84.2N702.J31

2
84.2N702.J31 84.2N702.J31 2ND = 84.2N702.031

2
SCD1U16V2KX-3GP
C2718
2ND = 84.2N702.031 2ND = 84.2N702.031 3rd = 84.2N702.W31

1
1
R2760
100KR2J-1-GP
C2717 X-32D768KHZ-40GPU 3rd = 84.2N702.W31 3rd = 84.2N702.W31

DY DY SCD1U16V2KX-3GP 82.30001.841
2nd = 82.30001.A41
2
2
1
+1.05V_RUN_VTT
1
FLASH KBC ROM R2727
+3.3V_ALW +3.3V_ALW
Stuff: R2766, C2717, R2746, RN2701, R2747
JTAG Debug port DY 10KR2J-3-GP
DY: R2760, C2718.
2
+3.3V_ALW +3.3V_ALW 0220 PROCHOT#_EC
BOARD_ID rise time is measured from 5%~68%.
1
2
130KR2F-GP
R2734
R2735 C2722 REV R2735 R2728
1
Place closely pin A29

10KR2J-3-GP
R2767
10KR2J-3-GP
R2778
10KR2J-3-GP
R2779
10KR2J-3-GP
R2786
33KR2F-GP
DY 100KR2J-1-GP
1
DB2 DB2 DB2 DB2 240K 4700P X00

R2746 CLK_PCI_MEC
2
1
49D9R2F-GP DB2 130K 4700P X01
BOARD_ID SYSTEM_ID
2
DB2 62K 4700P X02

2
1
11
1 JTAG_PU 33K 4700P A00 R3725
1
1
A A
JTAG_TDI C2722 C2721
DY 10R2J-2-GP
2 8.2K 4700P
3 JTAG_TMS SC4700P50V2KX-1GP SC4700P50V2KX-1GP
2
1CLK_PCI_MEC_R 2
4 JTAG_CLK 4.3K 4700P
5 JTAG_TDO
<Core Design>
DB2 6 MSCLK 2K 4700P
7 MSDATA
8 HOST_DEBUG_TX 1K 4700P
9 HOST_DEBUG_RX Wistron Corporation
10 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
12 1 DY 2 USB_PWR_SHR_EN# (78,82) Taipei Hsien 221, Taiwan, R.O.C.
SYSTEM_ID for BID function C2720
ACES-CON10-28-GP R2715 EC5048_TX *Pop R2734 130k for non-vPro DY SC4D7P50V2CN-1GP Title
20.K0460.010 0R2J-2-GP
KBC - MEC5055
2
A2 A00
Austin 13
Place near KBC Date: Tuesday, February 26, 2013 Sheet 27 of 106
5 4 3 2 1
5 4 3 2 1
SSID = Thermal
+FAN1_VOUT Layout note: FAN1
15 mial; at least 5
+FAN1_VOUT 1
+3.3V_RUN
CH551H-30PT-GP
D2802
SC2200P50V2KX-2GP
RTC_AUX_S5 FAN1_TACH_FB 2
C2810
3
FAN1_DET# 4
1
1 2 6
1
C2827
SCD1U16V2KX-3GP
SC1U6D3V2KX-GP C2828 DY C2811
+3.3V_M C2826 SC10U10V5KX-2GP ACES-CON4-29-GP
2
Vinafix.com
SC10U10V5KX-2GP
2
83.R5003.C8F
20.F1639.004
2ND = 83.R5003.H8H 2nd = 20.F1804.004
+5V_RUN
3rd = 83.R5003.G8H
D FAN1_DET# 2 1 D
R2819 10KR2J-3-GP AFTP2801 1FAN1_TACH_FB
+FAN1_VOUT
FAN1_TACH_FB 2 1 AFTP2802 1+FAN1_VOUT
1
C2818
SC10U10V5KX-2GP
C2823
SCD1U16V2KX-3GP
R2810 10KR2J-3-GP
AFTP2803 1FAN1_DET#
FAN1_TACH_FB
THERM_VDD_PWRGD 2 1
2
R2833 10KR2J-3-GP
+3.3V_M Layout Note:
BC_INT#_EMC4022 2 1 Routing together; Trace width
R2812 10KR2J-3-GP / Spacing = 10 / 10 mil
1 2 THERM_VDD
R2809 22R2J-2-GP
1
C2824
SCD1U16V2KX-3GP
16
10
CPU sensor:
2
3
4
5
C2825 U2801
SC1U6D3V2KX-GP
Layout Note:
VDD_L
RTC_PWR3V
TACH/GPIO1
VDD
VDD_H
VDD_H
FAN_OUT
FAN_OUT
2
2
84.M3904.B11
REM_DIODE1_N_4022 2ND = 84.03904.U11 1.Place C2803 as close as possible to Q2803
3rd = 84.03904.L06 2.Place C2830 as close as possible to Q2805
E
1
1
R2832 C2829 B Q2803 DY C2803 3.Place C2831 as close as possible to Q2810
1KR2J-1-GP SC2200P50V2KX-2GP MMBT3904-7-F-1-GP SC100P50V2JN-3GP
2
(27) PCH_PWRGD# 2 13V_PWROK# 12 23
C
THERM_VDD_PWRGD 3V_PWROK# DN1/THERM REM_DIODE1_P_4022
13 24
VDD_PWRGD DP1/VREF_T Skin Temp Sensor: SODIMM Sensor:
21 26 REM_DIODE2_N
E
(27,40) ACAV_IN
2
POWER_SW_IN#_L ACAVAIL_CLR DN2/DP4 C2813 MMBT3904-7-F-1-GP
(27) POWER_SW_IN# 1 2 20 27
+3.3V_M R2831 0R0402-PAD-2-GP POWER_SW# DP2/DN4 R2811 SC2200P50V2KX-2GP Q2805 C2830 Q2810
R2807 FAN1_DET# VCP_4021 1
B DY SC100P50V2JN-3GP B DY C2831
MMBT3904-7-F-1-GP SC100P50V2JN-3GP
15 25 2
1
(78) FAN1_DET# THERMTRIP2# GPIO3/PWM/THERMTRIP_SIO VIN 10KR2J-3-GP
1 2 17 28 84.M3904.B11
C
THERMTRIP2# VSET REM_DIODE2_P
(36) PURE_HW_SHUTDOWN#
19
SYS_SHDN# VCP
31 2ND = 84.03904.U11
8K2R2J-3-GP 3rd = 84.03904.L06
BC_INT#_EMC4022 9 32 VSET_4021 84.M3904.B11
+1.05V_RUN_VTT (27) BC_INT#_EMC4022 ATF_INT#/BC_IRQ# ADDR_MODE/XEN
SMDATA/BC_DATA
2ND = 84.03904.U11
C
1
C2833
SCD1U16V2KX-3GP
MMBT3904-7-F-1-GP 2 DY 1 3rd = 84.03904.L06
SMCLK/BC_CLK
RTC_AUX_S5
2
1
C2832
SCD1U16V2KX-3GP
1 2 THERM_B1 B Q2809 R2818
R2826 R2825 953R2F-GP
2K2R2J-2-GP 47KR2J-2-GP Layout Note:
E
2
Please Place C2829 and C2813
NC#18
NC#29
NC#30
TEST1
TEST2
TEST3
2
84.M3904.B11
GND
(5) H_THERMTRIP# as close as possible to U2801 (EMC4021)
2ND = 84.03904.U11
C 3rd = 84.03904.L06 C
EMC4021-1-EZK-TR-GP
18
29
30
7
8
14
22
11
33
74.04021.073 VCP2 2 1 AD_IA (40)
R2824 4K7R2J-2-GP
R2818
3VSUS_THRM_1 1 2 THERM_VDD
R2820 4K7R2J-2-GP
783 ohm for 85 degree C.
* 953 ohm(88 degree C)
1.24k ohm(92 degree C)
(27) BC_DAT_EMC4022
(27) BC_CLK_EMC4022
THERM_TEST1
THERM_TEST2
1
R2821 R2806
10KR2J-3-GP 10KR2J-3-GP
B B
A A
<Core Design>
Wistron Corporation
Title
Thermal, Fan controller

A2 Austin 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = AUDIO
Vinafix.com
D D
(Blanking)
C C
B B
A <Core Design> A
Wistron Corporation
Title
Audio Codec 92HD94

A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
(Blanking)
C C
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C
(Blanking) C
B B
A <Core Design> A
Wistron Corporation
Title
LAN Chip
A3 Austin 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = SDIO
1 2 +VDDH_SD +OZ_AVDD
+1.5V_RUN
L3202
Vinafix.com
C3202
SC4D7U6D3V3KX-GP
BLM18BD601SN1D-GP
SCD1U16V2KX-3GP
C3205
SC4D7U6D3V3KX-GP
C3240
SCD1U16V2KX-3GP
68.00082.531 68.00143.181
C3237
D 2ND = 68.00909.061 2ND = 68.00335.061 D
1
3rd = 68.00217.471 L3203 3rd = 68.00214.211
+3.3V_RUN 1 2 +3.3VDDH
BLM18PG471SN1D-GP
2
1 2 +PE_VDDH
L3201
C3234
SCD01U50V2KX-1GP
C3203
SC4D7U6D3V3KX-GP
C3201
SC4D7U6D3V3KX-GP
C3217
SCD1U16V2KX-3GP
C3235
SCD01U50V2KX-1GP
BLM18BD601SN1D-GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
68.00082.531
C3216
C3218
1
1
2ND = 68.00909.061
3rd = 68.00217.471
+OZ_DVDD +SKT_VCC
C3204
SC4D7U6D3V3KX-GP
SCD1U16V2KX-3GP
C3206
SC4D7U6D3V3KX-GP
C3239
SCD1U16V2KX-3GP
C3244
1
1
2
2
U3201
32
16
10
17
9
8
Layout Note:
3.3VCCD
LDO_1.5VIN
CORE_1.2VCCD
PE_3.3VCCA
PE_1.2VCCA
MMI_IO_VOUT
Layout Note: Place near U3201
MMI_3.3VOUT 15 3D3V_RUN_CARD
C Differential R3204 C
impedance 1 2 PE_REXT 3 PE_REXT

11
of 85 Ohm 191R2F-GP MS_CD#
12 SD/MMCCD#
SD_CD# SD/MMCCD# (74)
4 30 SDW P
(20) MMI_RXN_C_PCH_TXN6 PE_RXM SD_WPI SDW P (74)
(20) MMI_RXP_C_PCH_TXP6 5 PE_RXP 0110

Place near U3201 18 SD/MMCCLK_R R3212 1 2 10R2F-L-GP SD/MMC_CLK SD/MMC_CLK (74)
MMI_CLK SD/MMCCMD_R R3213 1 33R2J-2-GP SD/MMCCMD
SD_CMD/MS_BS 19 2 SD/MMCCMD (74)
(20) PCH_RXP_C_MMI_TXP6 C3228 1 2 SCD1U16V2KX-3GPPCIE_PRX_MMITX_P6_C 6 20 SD/MMCDAT7_R R3211 1 2 33R2J-2-GP SD/MMCDAT7 SD/MMCDAT7 (74)
PE_TXP MMI_D7 SD/MMCDAT6_R R3210 1 33R2J-2-GP SD/MMCDAT6
MMI_D6 21 2 SD/MMCDAT6 (74)
(20) PCH_RXN_C_MMI_TXN6 C3224 1 2 SCD1U16V2KX-3GPPCIE_PRX_MMITX_N6_C 7 22 SD/MMCDAT5_R R3208 1 2 33R2J-2-GP SD/MMCDAT5 SD/MMCDAT5 (74)
PE_TXM MMI_D5 SD/MMCDAT4_R R3207 1 33R2J-2-GP SD/MMCDAT4
MMI_D4 23 2 SD/MMCDAT4 (74)
24 SD/MMCDAT3_R R3206 1 2 33R2J-2-GP SD/MMCDAT3
1
MMI_D3
25
SD/MMCDAT3 (74) Layout Note:
(20) CLK_PCIE_MMI PE_REFCLKP MS_D2
MS_D1 27 Single end impedance
2 29 SD/MMCDAT0_R R3202 1 2 33R2J-2-GP SD/MMCDAT0 SD/MMCDAT0 (74) of 50 Ohm
(20) CLK_PCIE_MMI# PE_REFCLKM MMI_D0 SD/MMCDAT2_R R3205 1
SD_D2 26 2 33R2J-2-GP SD/MMCDAT2 SD/MMCDAT2 (74)
28 SD/MMCDAT1_R R3203 1 2 33R2J-2-GP SD/MMCDAT1 SD/MMCDAT1 (74)
SD_D1
(18) PLTRST_MMI# 13 PE_RST#
(20) MMICLK_REQ# 31 MULTI_IO2 MULTI_IO1 14
33 GND
OZ600FJ0LN-GP
B B
71.00600.B03
Pin Name Current(MAX) mA
3.3VCCD(pin16) 800 mA
PE_VCCA(pin32) 150 mA
LDO_1.5VIN(pin9) 150 mA
MMI_3.3VOUT(pin15) SD3.0 spec is 800 mA
CORE_1.2VCCD(pin10) 100 mA
PE_1.2VCCA(pin8) 100 mA
MMI_IO_VOUT(pin17) 100 mA
A <Core Design> A
Wistron Corporation
Title
Card Reader
A3
Austin 13 A00
5 4 3 2 1
A B C D E
Vinafix.com
4 4
3 3
(Blanking)
2 2
1 <Core Design> 1
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
A B C D E
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = Reset.Suspend
ROSA Run Power 1

R3610
2 PURE_HW_SHUTDOWN# (28)
+3.3V_ALW2
(41) 3V_5V_EN 0R0402-PAD-2-GP
Vinafix.com
1
1 2 ALWON (27)
1 2 RUN_ON_ENABLE# R3602 R3603
RUN_ON_ENABLE# (27) DY
1
200KR2J-L1-GP C3612 2KR2J-1-GP
D R3606 Rds(on) = 11 ~ 14mOhm DY D
SCD01U50V2KX-1GP
100KR2J-1-GP +15V_ALW AO4468 MAX 11.6A
2
D G S +5V_ALW +5V_RUN
U3601 5V_S0
1
8 D S 1
Q3602 R3604 7 D S 2 5V_S0 Comsumption +5V_ALW_PCH
2N7002KDW-GP 470KR2J-2-GP 6 D S 3
5 D G 4
Peak current 6A
84.2N702.A3F +5V_ALW +5V_ALW_PCH
2N7002K MAX 300mA
1
2
2nd = 84.DM601.03F AO4468L-GP
Rds(on) = 3~4 Ohm
1
S G D 3rd = 84.2N702.E3F 84.04468.A37
SC10U6D3V5KX-1GP
C3603
4th = 84.2N702.F3F 2nd = 84.08884.037 DY R3635
20KR2J-L2-GP Q3617
R3655 5V_RUN_ENABLE
2
(19,45,47,78) SIO_SLP_S3# 1 2 SIO_SLP_S3#_R S
1
0R0402-PAD-2-GP C3608 D
1
C3614
SCD1U16V2KX-3GP
R3656 SC220P50V2KX-3GP +15V_ALW R3633
2
1 DY 2 R2401 G 20KR2J-L2-GP
(45,47,78) RUN_ON
0R2J-2-GP 2 1 5V_ALW_PCH_ENABLE
2
100KR2J-1-GP 2N7002K-2-GP
Rds(on) =11 ~ 14mOhm 84.2N702.J31
AO4468 MAX 11.6A 2ND = 84.2N702.031
+3.3V_ALW +3.3V_RUN 3D3V_S0 3rd = 84.2N702.W31
D
+15V_ALW U3602
8 D S 1 3D3V_S0 Comsumption Q3616
7 D S 2 2N7002K-2-GP
Peak current 2.5A
1
6 D S 3
84.2N702.J31
1
5 D G 4 C3615
R3613 2ND = 84.2N702.031 SC330P50V2KX-3GP
2
470KR2J-2-GP AO4468L-GP 3rd = 84.2N702.W31
84.04468.A37
S
1
2nd = 84.08884.037
2
1
SC10U6D3V5KX-1GP
C3604
3.3V_RUN_ENABLE
DY R3636 ALW_ON_3.3V#
2
1
20KR2J-L2-GP
C3605
D
SC220P50V2KX-3GP
2
Q3618
C 2N7002K-2-GP C
84.2N702.J31 +15V_ALW
2ND = 84.2N702.031 ALW_ON_3.3V#
3rd = 84.2N702.W31 +3.3V_ALW2
+3.3V_ALW_PCH
G
2
1 2
R3609
RUN_ON_ENABLE# R3608 D G S 100KR2J-1-GP
100KR2J-1-GP +3.3V_ALW +3.3V_ALW +3.3V_ALW_PCH
1
6
4
+1.05V_M +1.05V_RUN Q3604 U3603
+15V_ALW
1D05V_S0 2N7002KDW-GP 1 D D 6
2 D D 5
84.2N702.A3F
U3607 TPCA8062-H-GP MAX 28A 1 23.3V_ALW_ENABLE 3 G S 4
3
8 D S 1
Rds(on) = 4.1~5.6m Ohm S G D 2nd = 84.DM601.03F
1
SC10U6D3V5KX-1GP
7 D S 2 3rd = 84.2N702.E3F R3631 C3611 AO6402A-GP
1
C3606
R3614 6 D S 3 MAX Current 6A 1 2 10KR2J-3-GP 84.06402.B3D
(27) PCH_ALW_ON 4th = 84.2N702.F3F
1
SCD01U50V2KX-1GP
330KR2J-L1-GP 5 D G 4 R3652 0R0402-PAD-2-GP 2ND = 84.P2703.03D R3634
2
C3620 1 DY 2 PCH_ALW_ON_R 3.3V_ALW_ENABLE_R 3rd = 84.03456.D3D 20KR2J-L2-GP
(19,27) SIO_SLP_S5#
TPCA8062-H-GP SC10U6D3V5KX-1GP R3653 0R2J-2-GP AO6402A MAX 7A
2
2
1.05V_RUN_ENABLE
2
84.08062.037 Rds(on) = 27~40m Ohm
2nd = 84.00460.037
1
3rd = 84.00312.037
D
C3619
Q3619 SC100P50V2JN-3GP
2
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.2N702.W31
G
RUN_ON_ENABLE# +1.35V_MEM +1.35V_CPU_VDDQ
U3608
8 D S 1
7 D S 2
B D S B
6
D G
3 TPCA8062-H-GP MAX 28A
5 4
C3621 Rds(on) = 4.1~5.6m Ohm
+3.3V_ALW2 2 1 TPCA8062-H-GP
+15V_ALW 84.08062.037
1 2SUS_ON_3.3V# 2nd = 84.00460.037
SC220P50V2KX-3GP 3rd = 84.00312.037
R3611 D G S 3D3V_M
2
100KR2J-1-GP 2 R3657 1
R3612 RUN_ON_CPU1.5VS3 (37)
DY
6
470KR2J-2-GP
Q3605 +3.3V_ALW +3.3V_ALW +3.3V_M 1MR2J-1-GP
2N7002KDW-GP R3648
Q3601
1
330KR2J-L1-GP
84.2N702.A3F U3604 RUN_ON_CPU1.5VS3 2
1 6 1 +15V_ALW
1
S G D 2nd = 84.DM601.03F 1 D D 6
3rd = 84.2N702.E3F 2 D D 5 2 5 CPU1.5V_S3_GATE_R 1 2
4th = 84.2N702.F3F 3.3V_SUS_ENABLE 3 G S 4 R3649 0R0402-PAD-2-GP CPU1.5V_S3_GATE (27)
1 2 RUN_ON_CPU1.5VS3# 3 4 1 2
+3.3V_ALW2
1
C3607
SC10U6D3V5KX-1GP
C3613 R3650 0R2J-2-GP SIO_SLP_S3# (19,45,47,78)

AO6402A-GP DY
1
84.06402.B3D R3651
2N7002KDW-GP
SC220P50V2KX-3GP
(78) SUS_ON 1 DY 2 2ND = 84.P2703.03D DY R3639 100KR2J-1-GP

2
R3637 0R2J-2-GP 3rd = 84.03456.D3D 20KR2J-L2-GP 84.2N702.A3F

2
(19,46,78) SIO_SLP_S4# 1
R3638
DY 2
0R2J-2-GP
2nd = 84.DM601.03F
AO6402A MAX 7A
2
3rd = 84.2N702.E3F
PR4622 Rds(on) = 27~40m Ohm 4th = 84.2N702.F3F
2 1
(19,45,78) SIO_SLP_A#
0R0402-PAD-2-GP
+3.3V_ALW_PCH +5V_RUN +1.5V_RUN +3.3V_RUN +1.05V_RUN +1.35V_CPU_VDDQ +0.675V_DDR_VTT

1
1
R3641 R3642 DY R3643 R3644 DY R3645 R3646 R3647
+1.5V_CPU_VDDQ_CHG
DY 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP
A A
+1.05V_RUN_CHG
+3.3V_ALWPCH 2
+5V_RUN_CHG 2
+1.5V_RUN_CHG2
+3.3V_RUN_CHG2
2
+DDR_CHG
Q3609 Q3610 Q3611 Q3612 Q3613 <Core Design>
Q3614 Q3615
ALW_ON_3.3V# G RUN_ON_ENABLE# G G G G G G
(5) RUN_ON_CPU1.5VS3#
DY Wistron Corporation
D D DY D D D D D
DY
S S S S S S S Taipei Hsien 221, Taiwan, R.O.C.
2N7002K-2-GP 2N7002K-2-GP Title

2N7002K-2-GP 2N7002K-2-GP 2N7002K-2-GP 2N7002K-2-GP 2N7002K-2-GP
84.2N702.J31 84.2N702.J31
84.2N702.J31 84.2N702.J31 84.2N702.J31 84.2N702.J31 84.2N702.J31 2ND = 84.2N702.031 2ND = 84.2N702.031 Power Plane Enable
2ND = 84.2N702.031 2ND = 84.2N702.031 2ND = 84.2N702.031 2ND = 84.2N702.031 2ND = 84.2N702.031 3rd = 84.2N702.W31 3rd = 84.2N702.W31 Size Document Number Rev
A2 A00
3rd = 84.07002.I31 3rd = 84.07002.I31 3rd = 84.07002.I31 3rd = 84.07002.I31 3rd = 84.07002.I31 Austin 13
4th = 84.2N702.W31 4th = 84.2N702.W31 4th = 84.2N702.W31 4th = 84.2N702.W31 4th = 84.2N702.W31 Date: Tuesday, February 26, 2013 Sheet 36 of 106
5 4 3 2 1
5 4 3 2 1
SSID = Reset.Suspend
Close to CPU
S3 Power Reduction Circuit Processor VREF_DQ Implementation
Vinafix.com
D
+V_DDR_SMREF +V_DDR_REF D
R3723
0R2J-2-GP
1 2
+1.35V_MEM DY +1.35V_CPU_VDDQ +V_SM_VREF_CNT
R3722
1
0R2J-2-GP
1 2 R3704
DY
1
1KR2F-L-GP
R3701
Q3708
DY 1KR2J-1-GP
2
S
SCD1U16V2KX-3GP
D
C3752
DY
1
G R3703
R3702 1KR2F-L-GP
DY 1KR2J-1-GP
2
2N7002K-2-GP
2
84.2N702.J31
2 2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31
(36) RUN_ON_CPU1.5VS3
C C
B B
+5V_ALW _PCH
1201
1
R3720
33R2J-2-GP
U3711
2
2 +3.3V_ALW _PCH
U3711_VDD RESET#/RESET +3.3V_ALW
3 VDD
GND 1
1
1
C3751
SCD1U16V2KX-3GP
R3719
RT9818A-44GU3-GP 100KR2J-1-GP
2
74.09818.NBB
2ND = 74.76144.0BB
2
U3710
RSMRST# 1 5
A VCC
(27) PCH_RSMRST# PCH_RSMRST# 2 B
3 4 PCH_RSMRST#_Q PCH_RSMRST#_Q (19)
GND Y
A 73.01G08.EHG <Core Design> A
2ND = 73.7SZ08.DAH
3rd = 73.7SZ08.EAH
Wistron Corporation
1 2 Taipei Hsien 221, Taiwan, R.O.C.
R1913 DY 0R2J-2-GP
Title
S3 Power Reduction
A3 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Support
Vinafix.com
D
+5V_ALW D
2
84.03904.L06
1
PR3802 2nd = 84.03904.P11 +3.3V_ALW
15KR2F-GP PR3803
2
10KR2J-3-GP
1
PQ3802_1 1 PMBS3904-1-GP +3.3V_ALW
1
PQ3802
PR3804
2
2
PD3803
1
PR3811 PSID_DISABLE#_R_C 1 DY 2 PSID_DISABLE# (78) BAV99-12-GP
100KR2J-1-GP 75.00099.E7D PR3806
2nd = 75.03101.07D 2K2R2J-2-GP
10KR2J-3-GP
3rd = 75.00099.Q7D
G
1
3
PQ3801
2
FDV301N-NL-GP
PR3801 PR3807
PS_ID_R 1 2 PS_ID_R2 D S PS_ID 1 2
D
PSID_EC (27)
0R0603-PAD-2-GP
84.00301.A31 33R2J-2-GP
Layout Note: 2nd = 84.3K329.031
PSID Layout width = 4mil
K
PR3808
PD3804 1 2
PESD24VS1UB-GP
DY
DY 33R2J-2-GP
C C
A
X01_1122
DCIN1 PL3802
NP1 ACMS160808A600-GP
1 1 AFTP3803 1 2
68.00115.081
2 2nd = 68.00230.091 +DC_IN AD+
3 3rd = 68.00335.101 PU3801
4 +DC_IN_C 1 S D 8
S D
PC3803
PC3804
PC3806
5 2 7
SC10U25V5KX-GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
1
PC3801
SC1U25V3KX-1-GP
PL3803 S D
PR3812
240KR3-GP
NP2 3 6
100KR2F-L1-GP
K
1
1
ACMS160808A600-GP G D
PR3809
4 5
ACES-CON5-20-GP EC3801 EC3802 1 2 EC3803 PD3801 PC3802
SC10U25V5KX-GP
SC1KP50V2KX-1GP
20.F1878.005 DY DY 68.00115.081 SCD1U25V3KX-GP 1SMB22AT3G-GP-U1 SCD1U25V3KX-GP AO4407AL-GP

2
2
2ND = 20.F1763.005 2nd = 68.00230.091 83.22R03.03G
2
3rd = 68.00335.101 2nd = 83.P6SBM.AAG 84.04407.G37
2
A
2nd = 84.03604.A37
PQ3805
1
R2
PQ3804 E Id=-9.6A 1212
C AD_OFF_L B
B R1 DY
R1
C AD_OFF_R PR3810 Qg=-25nC
DY E 47KR3J-L-GP Rdson=18~30mohm
R2 PDTA124EU-1-GP
2
PDTC124EU-1-GP 84.00124.K1K
B B
84.00124.H1K 2nd = 84.05124.A11
AFTP3801 1 +DC_IN_C 2nd = 84.05124.011
AFTP3802 1 PS_ID_R
(78) AC_DIS
A <Core Design> A
Wistron Corporation
Title
Size Document Number

DCIN Rev
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Support
Vinafix.com Batt Connecter

BT+
D D
SMF18AT1G-GP
K
1
PD3902
EC3903
SC2200P50V2KX-2GP DY BATT1
2
9
A
1
2
R3901 1 2 33R2J-2-GP PBAT_SMBCLK1 3
(27) PBAT_SMBCLK
R3902 1 2 33R2J-2-GP PBAT_SMBDAT1 4
(27) PBAT_SMBDAT
R3903 1 2 33R2J-2-GP BAT_IN#_1 5
(78) PBAT_PRES#
6
PH in EC page 7
8
10
SC56P50V2GN-GP
SC56P50V2GN-GP
ALP-CON8-3-GP-U1
EC3901
EC3902
1
1
DY DY 20.81157.008
2nd = 20.81153.008
2
1 AFTP3906
C C
AFTP3902 1 BAT_IN#_1
AFTP3903 1 PBAT_SMBDAT1
AFTP3904 1 PBAT_SMBCLK1
AFTP3905 1 BT+
B B
Placement: Close to Batt Connector
X01_1122
PBAT_SMBCLK
PBAT_PRES#
PBAT_SMBDAT
1
1
TVNS52301AB0-GP
TVNS52301AB0-GP
TVNS52301AB0-GP
D3902 D3903 D3901
83.52301.0AF 83.52301.0AF 83.52301.0AF

2nd = 83.ESD5B.0AF 2nd = 83.ESD5B.0AF 2nd = 83.ESD5B.0AF
2
<Core Design>
A A
Wistron Corporation
Title
BATT CONN
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = Charger
AD+
PU4007 +SDC_IN DCBATOUT BT+
Vinafix.com
8 D S 1
D S PR4012
7 2 PU4005
6 D S 3 1 2 1 S D 8
5 D G 4 2 S D 7
D01R3721F-GP-U AD+ 3 S D 6
1
AO4407AL-GP 4 G D 5
SC2200P50V2KX-2GP
D D
GAP-CLOSE-PWR
GAP-CLOSE-PWR
SCD1U25V2ZY-1GP
2
2
PR4002
PC4002
84.04407.G37
100KR2J-1-GP
1
PC4025
AO4407AL-GP
2nd = 84.03604.A37
84.04407.G37
1ISL88731_CSSN
1
1
PG4005
PG4003
1224 2nd = 84.03604.A37
2
PR4003 AD+_G_2 PR4026
3KR5J-GP 470KR2J-2-GP
2
DY DY
10KR2F-2-GP
PR4001
2
2
DC_IN_D
PQ4002
PR4019
1AD+_G_1
3 4 10R2J-2-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
AD+ ACAV_IN 2 5
2
1 6 1 2
PC4032
PC4033
PR4017 84.2N702.A3F
1
1 2 2N7002KDW-GP 2nd = 84.DM601.03F PC4017
3rd = 84.2N702.E3F SCD047U50V3KX-GP 0220
ISL88731_CSSP
0R2J-2-GP 4th = 84.2N702.F3F CHG_AGND
2
1
1212 PC4005
1
1
SCD1U50V3KX-GP PC4015
SC22U25V5MX-GP
SC22U25V5MX-GP
SC22U25V5MX-GP
SC22U25V5MX-GP
1
PR4035 PU4001 SC1U10V3KX-3GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC2200P50V2KX-2GP
SC220P50V2JN-3GP
2
1
226KR3F-1-GP
PC4036
PC4037
PC4021
PC4022
PC4019
PC4011
NC#1
5
6
7
8
1
ISL88731_DCIN
PC4040
PC4041
22 28 PR4020
DCIN CSSP
D
D
D
D
33R3F-L-GP PU4003
DY DY
2
ISL88731_ACIN 2 FDMC8884-GP-U
2
ACIN ISL88731_CSSN_R CHG_AGND
27 84.08884.A37
SCD01U50V2KX-1GP
2
1
CSSN ISL88731_VCC
+5V_ALW 11 26 2nd = 84.00412.037
1
VDDSMB VCC ISL88731_LDO
G
PC4016
PR4014 0R3J-L1-GP 4
1
S
S
S
49K9R2F-L-GP PC4020 PR4024
SCD1U16V2KX-3GP 25 ISL88731_BST 1 2ISL88731_BST1 1
DY 2 1 2
2
3
2
1
BOOT ISL88731_LDO PC4007
21
2
ISL88731_ACOK VDDP PD4001 SC1U25V5KX-1GP

13
ACOK ISL88731_DHI 1SS400PT-GP
1
CHG_AGND 24
UGATE PL4001 +VCHGR1
CHG_AGND 10 0R3J-L1-GP 1 2 PC4009
(27) CHARGER_SMBCLK SCL PR4011 PC4010 DY SC3300P50V3KX-1GP PR4016
2
23 ISL88731_LX 1 2 SCD1U50V3KX-GP ISL88731_LX1 1 2 1 2
PHASE IND-5D6UH-48-GP-U1
1 2
9 PC4012 SC220P50V2JN-3GP 68.5R610.10X D01R3721F-GP-U
C
(27) CHARGER_SMBDAT SDA
20 ISL88731_DLO DY 2nd = 68.5R610.10U
C
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
GAP-CLOSE-PWR
GAP-CLOSE-PWR
5
6
7
8
2
LGATE
1
D
D
D
D
PC4003
PC4004
PC4035
PC4038
PC4039
PU4004
14 19 FDMC8884-GP-U
NC#14 PGND DY
PG4007
PG4001
PR4018 84.08884.A37
2
18 ISL88731_CSIP_R 2 1 10R2J-2-GP 2nd = 84.00412.037
CSOP
G
CHG_AGND 4
S
S
S
PR4030 17 PC4008
ISL88731_CSIP
ISL88731_ICM CSON SCD22U50V3ZY-1GP
1 2 8
3
2
1
(28) AD_IA ICM
2
0R0402-PAD-2-GP ISL88731_CSIN
1ISL88731_CCV1
1 2 ISL88731_CCV 6
PR4015 4K7R2J-2-GP ISL88731_CCI VCOMP
5 16
SCD01U50V2KX-1GP
ISL88731_CCS NC#5 NC#16

4
1
ISL88731_REF ICOMP +3.3V_ALW

PC4023
3
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
PROCHOT_GATE (78)
1
VREF
PC4018
SCD1U16V2KX-3GP
PR4025 ISL88731_DAC 7 PR4009

16KR2F-GP DY 12
NC#7
15 PBATT_SENSE_R 1 2
DY
SC1U10V3KX-3GP
GND
GND VFB BT+ +3.3V_ALW

PC4014
PC4024
PC4001
DY
2
1
PC4013
SCD1U16V2KX-3GP
SCD1U50V3KX-GP
0R0402-PAD-2-GP
2
PC4031
This Resistor ISL88731CHRTZ-GP
29
1
must be 1% DY DY 74.88731.C73
2
PR4022
tolerance.
2
1 2 100KR2J-1-GP
2
PG4004 +3.3V_ALW2
GAP-CLOSE-PWR PU4009 PQ4403
2
5 1 G ACAV_IN
ISL88731_LDO CHG_AGND VCC A
150KR2F-L-GP
2 PQ4009_P1 D
B
PR4029
PQ4404
1
G PQ4009_P4 4 3 S
PR4010 Y GND
10KR2F-2-GP (5,27) H_PROCHOT# D U74LVC1G08G-AL5-R-GP-U 2N7002K-2-GP
2
PR4007 73.01G08.EHG 84.2N702.J31
1PWR_CHG_CMPIN
PR4027 0R2J-2-GP S 2ND = 73.7SZ08.DAH 2ND = 84.2N702.031
2
1 2ISL88731_ACOK 3rd = 73.7SZ08.EAH 3rd = 84.2N702.W31

(27,28) ACAV_IN 2N7002K-2-GP
0R0402-PAD-2-GP 1 2PWR_CHG_CMPOUT 84.2N702.J31
1
2ND = 84.2N702.031
150KR2F-L-GP
B 3rd = 84.2N702.W31 B
1
PR4008
PWR_CHG_CMPIN
PR4033
15K8R3F-GP PR4005
2
1M8R2F-GP
2
1
PR4006
+5V_ALW 66K5R2F-GP PC4034
SCD01U25V2KX-3GP
2
PR4004 SC100P50V2JN-3GP
PC4028
2
AD_IA 1 2 PWR_CHG_IOUT
1
1
1
PC4027
SC100P50V2JN-3GP
20KR2F-L-GP
2
(5,27) H_PROCHOT#
SC220P50V2JN-3GP
D
PU4008
LM393PWR-GP PQ4001
1
5
6
7
8
+5V_ALW 2N7002K-2-GP
D
PC4026
84.2N702.J31
2IN-
2IN+
2OUT
VCC
PQ4406 ISL88731_REF PU4008 2nd source 74.00393.E2G 2ND = 84.2N702.031

2
2N7002K-2-GP 3rd = 84.2N702.W31

need BATCH RUN in EC
1
84.2N702.J31
1
1OUT
2ND = 84.2N702.031 PR4441

GND
1IN+
S
1IN-
3rd = 84.2N702.W31 220KR2J-L2-GP PR4032

74.00393.C2G 10KR2J-3-GP
S
4
3
2
1
PR4036
2
PWR_CHG_CMPOUT +DC_IN 0R0402-PAD-2-GP (27) DYN_TUR_CURRNT_SET#

1 2
ACAV_IN_NB (27)
1
ISL88731_REF
PR4028
232KR2F-GP
PR4034 PR4023
1MR2F-GP
DY41K2R2F-GP
1
PR4021
2
47KR2J-2-GP
DC_IN_V_ACAVINNB EC Code for BQ24727 (ROSA CC)

SC100P50V2JN-3GP
2
1
+DC_IN_REF
1
SC100P50V2JN-3GP
PC4029
PR4031
22K6R2F-1-GP
H_PROCHOT# DYN_TUR_CURRNT_SET#
42K2R2F-L-GP
1
1
PR4013
2
PC4030
65W 1
2
A A
2
2
90W 0
<Core Design>
Wistron Corporation
Title
CHARGER ISL88731
A2 A00
Austin 13
5 4 3 2 1
A B C D E
SSID = PWR.Plane.Regulator_5v3p3v
Vinafix.com PWR_5V3D3V_VCLK
4 4
+3.3V_ALW2 PC4104 PC4102 PC4103
DCBATOUT PWR_DCBATOUT_5V DCBATOUT PWR_DCBATOUT_3D3V
1
SC1KP50V2KX-1GP
SCD1U25V3KX-GP
SCD1U25V3KX-GP
1
1
PG4144 PG4111
2
1 2 1 2
2
PR4132 PD4102
3PC4102_2 2
3PC4103_2 2
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP 0R2J-2-GP BAT54-7-F-GP
PG4102 PG4112 DY
1 2 1 2
DY
3
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
PG4103 PG4113 PR4131
1 2 1 2 PR4127 0R2J-2-GP PD4103 PD4101
PWR_5V_EN1 1 2 PWR_5V_EN1_R 2 1 BAT54S-7-F-GP BAT54S-7-F-GP
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP X03 2/10 DY 75.00054.B7D 75.00054.B7D
PG4104 PG4114 0R0402-PAD-2-GP 2nd = 75.00054.C7D 2nd = 75.00054.C7D
1
1 2 1 2 3rd = 75.00054.M7D 3rd = 75.00054.M7D
1
PR4133 +15V_ALW 15V_PWR 5V_PWR
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP 0R0402-PAD-2-GP PG4105
PG4106 PG4115 GAP-CLOSE-PWR-3-GP
1 2 1 2
2
PR4130 1 2 PC4108_1
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP PWR_3D3V_EN2 1 2
PG4107 PG4118 3V_5V_EN (36)
1
1 2 1 2 0R0402-PAD-2-GP PC4106
PD4104 SC1U25V3KX-1-GP PC4108 PC4107
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP BZT52C15S-GP SCD1U25V3KX-GP SCD1U25V3KX-GP
2
PG4108 PG4135 83.15R03.C3F
1 2 1 2 2nd = 83.15R03.E3F
A
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
PG4109
1 2
GAP-CLOSE-PWR-3-GP
PG4110 DCBATOUT
1 2 PWR_DCBATOUT_5V
PWR_DCBATOUT_3D3V PC4112 PC4113
SC10U25V5KX-GP
SCD01U50V2KX-1GP
GAP-CLOSE-PWR-3-GP
1
3 PC4109 PC4110 PC4111 3
PC4129 PC4130 PC4114 PC4115 PC4116
DY
1
1
SC10U25V5KX-GP
SCD1U25V3KX-GP
SC10U25V5KX-GP
5
6
7
8
1
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U25V3KX-GP
D
D
D
D
D
PU4103 5V_PWR +5V_ALW
2
D 8
D 7
D 6
D 5
SIR172DP-T1-GE3-GP 84.00172.037 PG4119
2
PU4105
12
Design Current = 7.664A 2nd = 84.07698.037 1 2
FDMC8884-GP-U PU4101
11.496A<OCP< 13.75A 84.08884.A37 GAP-CLOSE-PWR-3-GP
VIN
G
S
S
S
2nd = 84.00412.037 PG4120
4 PR4108 PR4109 SCD1U25V3KX-GP Design Current = 12A 1 2
G
4
3
2
1
+3.3V_ALW 3D3V_PWR PC4117 1D5R3F-GP 1D5R3F-GP PC4118
S G
S
S
S
PG4136 2 1PWR_3D3V_VBST2_1 1 2 PWR_3D3V_VBST2

9 17 PWR_5V_VBST1 1 2PWR_5V_VBST1_1 1 2
18A<OCP< 21.6A GAP-CLOSE-PWR-3-GP
1
2
3
SCD1U25V3KX-GP VBST2 VBST1 PG4121

1 2
3D3V_PWR PWR_3D3V_DRVH2 10 16 PWR_5V_DRVH1 5V_PWR 1 2
PL4102 DRVH2 DRVH1 PL4101
GAP-CLOSE-PWR-3-GP
PG4137 2 1 PWR_3D3V_LL2 8 18 PWR_5V_LL1 1 2 GAP-CLOSE-PWR-3-GP
IND-2D2UH-46-GP-U SW2 SW1 IND-1D5UH-34-GP PG4122
1 2
1
68.2R210.20B PWR_3D3V_DRVL211 15 PWR_5V_DRVL1 1 2
1
DRVL2 DRVL1
GAP-CLOSE-PWR-3-GP
PG4138
2nd = 68.2R21B.10J
PR4110
D 68.1R510.10J
2nd = 68.1R51A.10E GAP-CLOSE-PWR-3-GP
DY
8
7
6
5
5
6
7
8
1 2 PG4116 2D2R5F-2-GP 14 PWR_5V_VO1 PG4117 PG4123
DY
1
1
D
D
D
D
VO1
PC4120
SCD1U16V2KX-3GP
D
D
D
D
PU4106 84.00460.037 PU4104 PR4111 PT4103 1 2

2
1
GAP-CLOSE-PWR-3-GP
SIR460DP-T1-GE3-GP
GAP-CLOSE-PWR-3-GP
SE220U6D3VM-30-GP
GAP-CLOSE-PWR-3-GP PC4119 PT4101 PWR_3D3V_FB2 4 2 PWR_5V_FB1 2nd = 84.00312.A37 2D2R5F-2-GP 77.52271.09L
FDMC8878-GP
DY
2
VFB2 VFB1
SCD1U16V2KX-3GP
SE220U6D3VM-30-GP
PG4139 84.08878.A30 2nd = 77.92271.03L

1PWR_3D3V_SNUB
GAP-CLOSE-PWR-3-GP
DY
2
1 2 2nd = 84.00780.037 PG4124
2
2
74.51225.073
2nd = 77.92271.03L
77.52271.09L
1 2
1PWR_5V_SNUB
S
S
S
PWR_3D3V_EN2 PWR_5V_EN1
G
GAP-CLOSE-PWR-3-GP G
S
S
S
G
6 20
PG4140 EN2 EN1
GAP-CLOSE-PWR-3-GP
1
2
3
4
4
3
2
1
1 2 PG4125
S PWR_3D3V_CS2 5
CS2 CS1
1 PWR_5V_CS1 1 2
GAP-CLOSE-PWR-3-GP
1
1
PG4141 GAP-CLOSE-PWR-3-GP
3D3V_TER
1 2 PR4102 19 PWR_5V3D3V_VCLK PR4103 PG4126

PC4121 DY 124KR2F-GP VCLK 61K9R2F-GP PC4123 1 2
DY
2
GAP-CLOSE-PWR-3-GP SC330P50V3KX-GP SC560P50V-GP
2
PG4142 7 21 GAP-CLOSE-PWR-3-GP
2
2
PGOOD GND PG4127
1 2
VREG3
VREG5
1 2
GAP-CLOSE-PWR-3-GP
PG4143 GAP-CLOSE-PWR-3-GP
1
1
2 1 2 TPS51225RUKR-GP PG4128 2
3
13
PR4113 5V_PWR_2 PR4114 1211 1 2
1
PR4112 3D3V_PWR_2
GAP-CLOSE-PWR-3-GP
DY0R2J-2-GP 0R2J-2-GP
DY
1PWR_5V3D3V_VREG3
6K65R2F-GP PG4101 PR4115 GAP-CLOSE-PWR-3-GP

1 2 15K4R2F-GP PG4129
2
1 2
1 2
PWR_3D3V_FB2_R PWR_5V_FB1_R 1 2
PC4124 GAP-CLOSE-PWR-3-GP
2
DYSC18P50V2JN-1-GP PC4125
SC18P50V2JN-1-GP DY GAP-CLOSE-PWR-3-GP
PG4130
2
2
X01 12/13 1 2
1
1
GAP-CLOSE-PWR-3-GP
1
PR4117 PC4127 PR4121 PG4131

SC1U6D3V2KX-GP
10KR2F-2-GP
PC4126
10KR2F-2-GP
DY PC4128 1 2
SC4D7U6D3V3KX-GP
SC22U6D3V5MX-2GP
3D3V_PWR_2 +3.3V_ALW2
2
+3.3V_ALW GAP-CLOSE-PWR-3-GP
2
2
PR4116 PG4132
1 2 1 2
1
PR4119 0R0402-PAD-2-GP GAP-CLOSE-PWR-3-GP

100KR2J-1-GP PG4133
1 2
2
GAP-CLOSE-PWR-3-GP
(27) PWR_5V3D3V_PGOOD PG4134
1 2
GAP-CLOSE-PWR-3-GP
PG4145
1 2
GAP-CLOSE-PWR-3-GP
PG4146
1 2
GAP-CLOSE-PWR-3-GP
PG4147
1 2
GAP-CLOSE-PWR-3-GP
PG4148
1 1
I/P cap: 10U 25V K0805 X5R/ 78.10622.51L 1 2
Inductor: 2.2U PCMC063T-2R2MN(Rdc=18~20m ohm, Idc=8A,Isat=14A)/68.2R210.20B
I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L GAP-CLOSE-PWR-3-GP
O/P cap: MP6VLPS220MC4R5 /CHIP CAP POL 220U 6.3V M 6.3*4.5 /220U/6.3V(ESR=17m ohm)/77.52271.09L Inductor: CHIP IND 1.50UH PCMC104T-1R5MN Cyntec 3.8mohm/4.2mohm Isat =33Arms 68.1R510.10J
H/S:SIS412DN SIZE:3*3/Id=7A(30m ohm,Qg=12nC) /84.00412.037
O/P cap: MP6VLPS220MC4R5 /CHIP CAP POL 220U 6.3V M 6.3*4.5 /220U/6.3V(ESR=17m ohm)/77.52271.09L
L/S:SIS780DN/ POWERPAK 121Id=9.5A/ (14.5~17.5m ohm,Qg=11nC)/84.00780.037 H/S: FET MOS SIR172DP-T1-GE3 NC POWERPAK 8P/Id=12.9A(10.3~12.4m ohm,Qg=98nC)/84.00172.037 <Core Design>
L/S: FET MOS SIR460DP-T1-GE3 NC SO8/Id=19.4A(4.9~6.1m ohm,Qg=16.8nC)/84.00460.037

Wistron Corporation
Title
TPS51125_5V/3D3V
A2 A00
Austin 13
A B C D E
5 4 3 2 1
SSID = CPU.Regulator
+1.05V_RUN_VTT
1 2 Volterra's suggestion:
(8) VR_SVID_ALERT# PR4224 DY 75R2F-2-GP
(8) H_CPU_SVIDDAT
H_CPU_SVIDDAT 1 2 VCC 26x22uF(0805) 1-PHASE VCC
PR4225 130R2F-1-GP
(8) H_CPU_SVIDCLK
H_CPU_SVIDCLK 1 2 boot voltage=0V VCCAXG 23x22uF(0805) for 1-PHASE VCCAXG
PR4226 54D9R2F-L1-GP
PR4259 1 2 0R2J-2-GP 1.05V_0.8V_PWROK_R
(27) 1.05V_0.8V_PWROK PR4265 1 2 0R2J-2-GP
(78) IMVP_VR_ON DY
Vinafix.com
PR4211
PR4201
PR4205
PR4262
PR4209
PR4210
PR4204
PR4208
1
PR4228
PR4207
+1.8V_RUN +3.3V_ALW
1
825R2F-GP
D
+5V_ALW D
21D5R2F-1-GP
61K9R2F-GP
280R2F-1-GP
20KR2F-L-GP
402R2F-GP
1
825R2F-GP
191R2F-GP
1
PR4231
2
1
0R0402-PAD-2-GP
0R0402-PAD-2-GP
PC4211 10R2F-L-GP
2
PR4260 SC1U6D3V2KX-GP
PWR_VCORE_VR_ENABLE
866KR2F-GP
PWR_VCORE_R_OSC
PWR_VCORE_R_SEL0
PWR_VCORE_R_SEL1
PC4237
PWR_VCORE_R_SEL6
PWR_VCORE_VR_READY2
PWR_VCORE_VR_READY1
PWR_VCORE_VR_TT#
PWR_VCORE_R_SEL4
1 2
PWR_VCORE_VIN_UVLO_R
1
SCD1U16V2KX-3GP
1
PC4214
SCD1U16V2KX-3GP
PR4263
100KR2F-L1-GP
GND_1318
2
2
1 2
GND_1318
PR4223
49
48
47
46
45
44
43
42
41
40
39
38
37
0R0402-PAD-2-GP PU4201
R_SEL6
VR_READY2
VR_READY1
VR_TT#
R_SEL4
ALERT#
VDIO
VCLK
VR_ENABLE
R_SEL0
R_SEL1
GND
R_OSC
+1.8V_RUN
PWR_VCORE_VDD3 1 36 PWR_VCORE_R_SEL2
VDD3 R_SEL2 PWR_VCORE_R_SEL3
2 35
VDD R_SEL3 PWR_VCORE_R_REF
3 34
PWR_VCORE_VIN_UVLO VDD R_REF
4 33
PWR_VCORE__PWM3 VIN_UVLO IPH2_2 PWR_VCORE_R_SEL5
5 32 PWR_AXG_IPH2_1_R (44)
PWR_VCORE__PWM2 PWM1_3 R_SEL5 PWR_AXG_PWM2_2
6 31
PWR_VCORE__PWM1 PWM1_2 PWM2_2 PWR_AXG_PWM2_1 PR4229
7 30
(43) PWR_VCORE__PWM1 PWR_VCORE__TP_FAULT#1 PWM1_1 PWM2_1 PWR_AXG_TS_FAULT#2 PWR_AXG_PWM2_1 (44) 1K96R2F-1-GP
8 29
(43) PWR_VCORE__TP_FAULT#1 TS_FAULT#1 TS_FAULT#2 PWR_AXG_IPH2_1 PWR_AXG_TS_FAULT#2 (44)
9 28 1 2 1 2
IPH1_3 IPH2_1 PWR_AXG_MRAMP2 PR4246
10 27
PWR_VCORE_IPH1_1 IPH1_2 MRAMP2
1 2 1 2 11 26
1
IPH1_1 SENSE2+ 1KR2F-3-GP
PR4257
PC4201
PC4229 PWR_VCORE_MRAMP1
SENSE1+
12 25
A2_OUT1
A3_OUT1
A3_OUT2
A2_OUT2
SENSE1-
MRAMP1 SENSE2-
A_ERR1
A_ERR2
PR4261
PR4219
PR4256 PR4216 PR4218 PR4212
A2_IN1
A3_IN1
A3_IN2
A2_IN2
DY
1
C 750R2F-GP 1K96R2F-1-GP PR4215 0R2J-2-GP 0R0402-PAD-2-GP C
DY
2
1
1
SC10P50V2JN-4GP
PR4258
13KR2F-GP
15K4R2F-GP
SC10P50V2JN-4GP
0R2J-2-GP
DY DY
2
(43) PWR_VCORE_IPH1_1_L
VT1318MFQX-1-GP
2
13
14
15
16
17
18
19
20
21
22
23
24
0R0402-PAD-2-GP
0R0402-PAD-2-GP
2
2
74.01318.B73
PWR_VCORE_A_ERR1
PWR_VCORE_A2_IN1
PWR_VCORE_A2_OUT1
PWR_VCORE_A3_IN1
PWR_VCORE_A3_OUT1
PWR_AXG_A3_OUT2
PWR_AXG_A3_IN2
PWR_AXG_A2_OUT2
PWR_AXG_A2_IN2
PWR_AXG_A_ERR2
PC4231
SC22P50V2JN-4GP GND_1318
2 1 1 2
PR4252
PC4236 GND_1318 0R0402-PAD-2-GP
PC4232 PR4234 SC33P50V2JN-3GP PWR_AXG_SENSE2_P 1 2 VCC_AXG_SENSE (9)
2 1 VCORE_IN1_R0 2 1 1 2 VCORE_IN1_L0 1 2
DY DY PR4235 PWR_AXG_SENSE2_N 1 2 VSS_AXG_SENSE (9)
SC22P50V2JN-4GP 6K81R2F-1-GP PC4238
SC680P50V3JN-GP 15KR2F-GP PR4254
X01 12/21
PR4251 0R0402-PAD-2-GP
1 2 1 2VCORE_IN1_R1 1 2 2 1 (8) VCCSENSE 1 2 PWR_VCORE_SENSE_P
PR4237 PR4264
487R2F-GP PR4236 PR4233 0R0402-PAD-2-GP PC4235 SC22P50V2JN-4GP PC4233 SC22P50V2JN-4GP
953R2F-GP 7K5R2F-1-GP 10KR2F-2-GP
1 2 1 2
PR4250
1 2 PWR_VCORE_SENSE_N
(8) VSSSENSE
0R0402-PAD-2-GP PC4218 PR4244 PC4234
1 2 AXG_IN2_L1 1 2 1 2 AXG_IN2_R0 1 2 1 2
DY DY
PR4255 SC1000P50V3JN-GP-U 6K81R2F-1-GP SC22P50V2JN-4GP PR4240
30K1R2F-L-GP 665R2F-2-GP
X01 12/21
1 2 1 2AXG_IN2_R1 1 2
1 2VCORE_IPH1_R0 1 2 PR4245 10KR2F-2-GP
PG4201 PR4249 PR4239
1 2 PR4238 PC4213 7K68R2F-GP 300R2F-GP
2K7R2F-GP SC3300P50V2KX-1GP X03 2/21
GAP-CLOSE-PWR-3-GP
B GND_1318 B
1 2 AXG_IPH2_R0 1 2
PC4219 SCD01U16V2KX-3GP PR4243

3K24R2F-GP
+3.3V_RUN
VCC_CORE
PR4202
1 2 PWR_VCORE_MRAMP1 1 2 PWR_VCORE_VR_READY1
PR4222
10KR2F-2-GP
43KR2F-GP
PR4203
1 2
PWR_VCORE_VR_READY2 IMVP_PWRGD (78)
1 2
PR4253
10KR2F-2-GP 0R0402-PAD-2-GP
VCC_GFXCORE
1 2 PWR_AXG_MRAMP2
PR4227
56K2R2F-2-GP
+1.05V_RUN_VTT
PR4206
1 2 PWR_VCORE_VR_TT#
62R2J-GP
1
PC4202
SC47P50V2JN-3GP
2
A A
<Core Design>
Wistron Corporation
Title
VT1318+1323_CPU_CORE1+1(1/3)
A2 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
+5V_ALW
Layout Note:
Small Cap close IC
PC4304
PC4305
PC4306
PC4307
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PC4308
PC4309
1
1
PC4310
SCD1U16V2KX-3GP
2
2
+1.8V_RUN
C1
C2
C3
C4
PU4301
1
VDDH
VDDH
VDDH
VDDH
PC4302 A1 B4 PW R_CORE_BT1
(42) PW R_VCORE__TP_FAULT#1 TS_FAULT# BST
SC4D7U6D3V3KX-GP
2
1
A4 PC4301
VCC SCD22U10V3KX-2GP
H4
2
VX#H4
VX#H3 H3
VX#H2 H2
PW R_VCORE_PU4301_VDD B1 H1 PL4301 VCC_CORE
C VDD VX#H1 C
VX#F4 F4
F3 PW R_CORE_VX1 1 2
VX#F3 IND-D1UH-26-GP
VX#F2 F2
(42) PW R_VCORE_IPH1_1_L B2 ISENSE VX#F1 F1
VX#D4 D4 68.R1010.10T
+1.8V_RUN B3 D3 2nd = 68.R1010.10X
(42) PW R_VCORE__PW M1 PWM VX#D3
VX#D2 D2
VX#D1 D1
PR4301
PC4303
1 2 1 2 A2 GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SCD1U25V2KX-GP
10R2F-L-GP
VT1323SFCX-1-GP
E1
E2
E3
E4
G1
G2
G3
G4
J1
J2
J3
J4
74.01323.A7Z
PG4301
1 2
B B
GAP-CLOSE-PW R-3-GP
GND_1323S_1
<Core Design>
A A
Wistron Corporation
Title
VT1318+1326_CPU_CORE2+1(2/3)
A3 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
+5V_ALW
Layout Note:
Small Cap close IC
PC4403
PC4404
PC4405
PC4406
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC1U6D3V2KX-GP
PC4407
1
1
PC4408
SCD1U16V2KX-3GP
2
2
+1.8V_RUN
C1
C2
C3
C4
C PU4401 C
1
VDDH
VDDH
VDDH
VDDH
PC4401 A1 B4 PW R_AXG_BT3
(42) PW R_AXG_TS_FAULT#2 TS_FAULT# BST
SC4D7U6D3V3KX-GP
2
D.C. = 22A
1
A4 VCC
H4 PC4409 P.C. =33A
VX#H4 SCD22U10V3KX-2GP
H3
2
VX#H3 VCC_GFXCORE
VX#H2 H2 PL4401
PW R_AXG_PU4401_VDD B1 H1
VDD VX#H1
VX#F4 F4
F3 PW R_AVG_VX1 1 2
VX#F3 IND-D1UH-26-GP
VX#F2 F2
(42) PW R_AXG_IPH2_1_R B2 ISENSE VX#F1 F1
VX#D4 D4 68.R1010.10T
+1.8V_RUN B3 D3 2nd = 68.R1010.10X
(42) PW R_AXG_PW M2_1 PWM VX#D3
VX#D2 D2
VX#D1 D1
PR4401
PC4402
1 2 1 2 A2 GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SCD1U25V2KX-GP
10R2F-L-GP
VT1323SFCX-1-GP
E1
E2
E3
E4
G1
G2
G3
G4
J1
J2
J3
J4
74.01323.A7Z
B PG4401 B
1 2
GAP-CLOSE-PW R-3-GP
GND_1323S_3
A <Core Design> A
Wistron Corporation
Title
VT1318+1323_CPU_CORE1+1(3/3)
A3 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p05v
PG4505
1 2
+3.3V_RUN
GAP-CLOSE-PWR-3-GP
PG4520
2
1 2 +1.05VTTP +1.05V_RUN_VTT
PR4507
10KR2J-3-GP GAP-CLOSE-PWR-3-GP PG4501
PG4521 1 2
1
PR4510 1 2
GAP-CLOSE-PWR-3-GP
Vinafix.com 1 2 PWR_1D05V_STAT 5V_PWR_1D05V PG4502

(27,48) 1.05V_VTTPWRGD Layout Note: GAP-CLOSE-PWR-3-GP +5V_ALW 1 2
0R0402-PAD-2-GP 140mil PG4522
2
1 2 GAP-CLOSE-PWR-3-GP
DY PC4520 PG4503
SC22U6D3V5MX-2GP
D D
PC4503
SC2200P50V2KX-2GP GAP-CLOSE-PWR-3-GP 1 2
SC4D7U6D3V3KX-GP
1
PC4509
PG4523
1
SCD1U16V2KX-3GP
PC4510
EC4501
SCD1U16V2KX-3GP
PG4504
GAP-CLOSE-PWR-3-GP 1 2
2
PG4524
PG4506
GAP-CLOSE-PWR-3-GP 1 2
PU4501 GAP-CLOSE-PWR-3-GP
PG4507
Layout Note: B5 B2 PWR_1D05V_VX 1 2
VDD VX#B2
Diff. pair C5
VDD VX#B3
B3
VX#B4
B4 D.C. =5.95A GAP-CLOSE-PWR-3-GP
PG4525
PWR_1D05V_VSENSE+ A2 C2 9.35A < OCP < 11.05 A 1 2
PWR_1D05V_VSENSE- SENSE+ VX#C2
1 2 2 1 A3 C3
PR4502
SENSE- VX#C3
C4
Layout Note: +1.05VTTP GAP-CLOSE-PWR-3-GP
VX#C4 PL4501
2K74R2F-GP PR4503 400mil PG4526
6K81R2F-1-GP PWR_1D05V_STAT A4 1 2
STAT
A1 1 2
PU4501_OE A5 AGND
(78) CPU_VTT_ON OE COIL-D2UH-2-GP PG4527
B1 X03 2/16
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
PR4508 GND
PC4513
PC4514
C1 1 2
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
0R0402-PAD-2-GP GND
PC4519
PC4518
68.R2010.20B
DY 2
1
SCD1U16V2KX-3GP
EC4502
SCD1U16V2KX-3GP
EC4503
1 GAP-CLOSE-PWR-3-GP
(19,36,47,78) SIO_SLP_S3#
1
PR4509 0R2J-2-GP 2nd = 68.R2010.10I
PC4515
SCD1U16V2KX-3GP
VT386FCX-ADJ-1-GP PG4528
1
PC4522
SCD1U16V2KX-3GP
1 2
2
DY 74.00386.A3Z
2
PR4506 GAP-CLOSE-PWR-3-GP
2
150R2F-1-GP AGND_1D05V_386 PG4529
1 2 1 2 1 2
DY
VCCIO_SENSE_1
1
PC4521 GAP-CLOSE-PWR-3-GP
SC3300P50V2KX-1GP PR4501 PG4530
25K5R2F-GP 1 2
1 2 +1.05VTTP
GAP-CLOSE-PWR-3-GP
2
PC4501
SC4700P50V2KX-1GP
C C
PG4517
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
PC4517
1 2
SC22U6D3V5MX-2GP
PC4516
PC4504
PC4505
PC4507
PC4508
PC4511
PC4512
PC4506
1
1
1
GAP-CLOSE-PWR-3-GP
1
SCD1U16V2KX-3GP
PC4502
AGND_1D05V_386 DY DY
2
2
2
2
2
VCCIO_SENSE_C PR4504 1 2 0R0402-PAD-2-GP VCCIO_SENSE (8)
PR4505 1 2 0R0402-PAD-2-GP VSSIO_SENSE (8)
Layout Note:
Close CPU output
I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L

O/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L
Inductor: CHIP IND 0.20UH PCMB053T-R20MS(5*5*3)(Rdc=3.5~3.9m ohm,Idc=21A,Isat=14.5A)/68.R2010.20B
B B
+3.3V_ALW 1D05_M_PWR +1.05V_M
PG4532 PG4508
2 1 1 2
GAP-CLOSE-PWR GAP-CLOSE-PWR-3-GP
PG4534 PG4509
2 1 1 2
PC4524 PC4523
PC4530 Design Current =4.719A
GAP-CLOSE-PWR
1
GAP-CLOSE-PWR-3-GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
PG4533 7A<OCP<8.5A PG4510

SCD1U16V2KX-3GP
2 1 DY 1 2
2
GAP-CLOSE-PWR GAP-CLOSE-PWR-3-GP
PG4511
1 2
PC4527
PU4502 SCD1U25V3KX-GP GAP-CLOSE-PWR-3-GP
PWR_1D05V_VDD 9 1D05_M_PWR PG4512
VDD PL4502
10 3 PWR_1D05V_BOOT 1 2 1 2
VDD BOOT
PR4516
2 1 PWR_1D05V_EN 4 1 PWR_1D05V_LX 1 2 GAP-CLOSE-PWR-3-GP
(19,36,78) SIO_SLP_A# EN LX#1 PG4513
11
GAP-CLOSE-PWR-3-GP
0R0402-PAD-2-GP LX#11 PC4525 PC4532 PC4533 PC4536
PWR_1D05V_PWRGD
1
5 12 1 2
1
PGOOD LX#12 COIL-D47UH-13-GP
2
1 2
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
(19,36,47,78) SIO_SLP_S3# DY PWR_1D05V_REFIN 68.R4710.20J
6 DY GAP-CLOSE-PWR-3-GP
PG4531
PR4512 REFIN 2nd = 68.R4710.20N
7 PWR_1D05V_FB DY PG4514
GND
GND
10KR2J-3-GP
2
1
FB PWR_1D05V_COMP PR4514
8
PWR_1D05V_SNUB
1 2
DY COMP
1PWR_1D05V_FB_R
2D2R5F-2-GP
2
1
PC4528
(36,47,78) RUN_ON
2 DY 1 SCD01U50V2KX-1GP PC4535 GAP-CLOSE-PWR-3-GP
2
2
13
PR4513 RT8085AGQW-GP
1
PR4511 PG4515
0R2J-2-GP 74.08085.043
SCD01U50V2KX-1GP
1 2
13KR2F-GP
2
GAP-CLOSE-PWR-3-GP
1PWR_1D05V_COMP_L
+3.3V_ALW PG4516
1
PC4526 1 2
DY X01_1126
1
1
1
10KR2J-3-GP
PR4515 GAP-CLOSE-PWR-3-GP
PC4529
DY
SC22P50V2JN-4GP
A PR4519 76K8R2F-GP PC4531 A

SC560P50V-GP
SC56P50V2GN-GP
2
2
2
I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L

PR4518
2
(27) 1.05V_A_PWRGD
2 1 PC4534 O/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L
Inductor: CHIP IND 0.47UH PCMB042T-R47MS 5*5*3)
SC1KP50V2KX-1GP
0R0402-PAD-2-GP
(Rdc=7.4~8.5m ohm,Idc=13A,Isat=12A)/ 68.R4710.20J <Core Design>
2
PR4517
100KR2F-L1-GP
Wistron Corporation
2
Title
1D05V_PCH & VCCP_CPU

A2 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p35v0p675v DCBATOUT PWR_DCBATOUT_1D35V

PG4601
2 1
GAP-CLOSE-PWR
PR4604 PG4609
PWR_1D35V_VCC5 2 1 2 1
+5V_ALW
5D1R2F-GP
GAP-CLOSE-PWR
1
PC4610 PG4602
SC1U10V2KX-1GP 2 1
2
PWR_DCBATOUT_1D35V
Vinafix.com
GAP-CLOSE-PWR
1
SC1KP50V2KX-1GP
PC4616 PR4601 PG4603
16K5R2F-2-GP
2 1
2
PR4611 GAP-CLOSE-PWR
PWR_1D35V_PVCC5 1 2
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U50V3KX-GP
D +5V_ALW D
PC4614
PC4613
PC4617
D
2
0R0603-PAD-2-GP
5
6
7
8
D
D
D
D
PC4618 PU4602
1
PWR_1D35V_CS SC1U10V2KX-1GP FDMC8884-GP-U
2
+3.3V_ALW 84.08884.A37
2nd = 84.00412.037
G
4
S
S
S
PR4602
13
11
12
10KR2J-L-GP PU4601
3
2
1
PC4605 1D35V_PWR +1.35V_MEM
CS
VDDP
VDD
PWR_DCBATOUT_1D35V PR4612 1D35V_PWR +1.35V_MEM
Cyntec. 1.0uH, 10x11.5x4mm Design Current =9.1A
(27) 1.35V_SUS_PWRGD 2 18 PWR_1D35V_VBST 1 2PWR_1D35V_VBST_1 1 2 G S PG4618
10
BOOT 2D2R3-1-U-GP DCR=3~3.3mohm 14A<OCP<16.4A PG4604 2 1
PGOOD SCD1U25V3KX-GP 2 1
1 2 PWR_1D35V_TON 9 17 PWR_1D35V_UGATE Idc=18A, Isat=28A GAP-CLOSE-PWR
PR4603 TON UGATE GAP-CLOSE-PWR PG4619
PWR_1D35V_EN 8 1D35V_PWR PG4605 2 1
620KR2F-GP S5 PL4601 2 1
PWR_0D675V_EN 7 16 PWR_1D35V_PHASE 1 2 GAP-CLOSE-PWR
S3 PHASE IND-1D5UH-23-GP GAP-CLOSE-PWR PG4620
1D35V_PWR 19 68.1R510.10K PG4606 2 1
1
VLDOIN
PT4601
2nd = 68.1R51A.10F 2 1
SE330U2VDM-L-GP
1
PC4612 PWR_1D35V_LGATE GAP-CLOSE-PWR

15 D
1
LGATE
PC4606
SCD1U16V2KX-3GP
SC10U6D3V5MX-3GP PR4605 PC4601 GAP-CLOSE-PWR PG4621
2
DY
5
6
7
8
SC4D7U10V5KX-4GP
2D2R5F-2-GP PG4607 79.33719.L01 PG4608
74.08207.C73 2 1
2
D
D
D
D
PU4603 2nd = 77.23371.13L 2 1
2
GAP-CLOSE-PWR-3-GP
1 14 FDMC8878-GP GAP-CLOSE-PWR
+0.675V_DDR_VTT +0D675V_DDR_P VTTGND PGND
1
84.08878.A30 GAP-CLOSE-PWR PG4622
PWR_1D35V_SW_1
2nd = 84.00780.037 PG4610 2 1
PG4616 +0D675V_DDR_P 5 PWR_1D35V_VDDQ 2 1
1
VDDQ
G
S
S
S
2 1 GAP-CLOSE-PWR
20 6 PWR_1D35V_FB DY PC4602 GAP-CLOSE-PWR PG4623
4
3
2
1
1
GAP-CLOSE-PWR VTT FB SC330P50V2KX-3GP PG4615 2 1
2
1
PG4617 2 PR4606 2 1
VTTSNS DY
VTTREF
2 1 30KR2F-GP PC4603 GAP-CLOSE-PWR

SC18P50V2JN-1-GP GAP-CLOSE-PWR PG4624
R1 G S
GND
GND
2
1
1
PC4604
SCD1U16V2KX-3GP
GAP-CLOSE-PWR PC4611 PC4615 PG4611 2 1
2
2 1
DY
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
RT8207MZQW-GP-U GAP-CLOSE-PWR
2
21
C GAP-CLOSE-PWR PG4625 C
1
PG4612 2 1
R2 PR4607 2 1
1PWR_1D35V_VTTREF
30KR2F-GP GAP-CLOSE-PWR
GAP-CLOSE-PWR
PR4608 PG4613
2
1 2 +V_DDR_REF 2 1
0R0603-PAD-2-GP PR4609 GAP-CLOSE-PWR

PG4614
1 2 PWR_0D675V_EN
(78) 0.675V_DDR_VTT_ON 2 1
0R0402-PAD-2-GP
PC4607 Vout=0.75*(1+R1/R2) GAP-CLOSE-PWR
SCD033U16V2KX-GP
1
PC4608
2
DYSCD1U16V2KX-3GP
2
I/P cap: 10U 25V K0805 X5R/ 78.10622.51L
Inductor: PCMC063T-1R5MN/ Id=12A(11.1~13.3m ohm,Qg=7.3nC) 68.1R510.10K
O/P cap: EL330U2V EEFSX0D331ER
PR4610 330U/2V (ESR:9 mohm ,I rms:3A)
0R0402-PAD-2-GP
1 2 PWR_1D35V_EN H/S:FDMC8884 NC MLP3.3X3.3
(19,36,78) SIO_SLP_S4# Id=9A(22~30m ohm,Qg=12nC) 84.08884.A37
PR4613 1 2 0R2J-2-GP
DY
1
(27) DDR_ON
PC4609
SCD1U16V2KX-3GP
L/S:FDMC7696 NC MLP3.3X3.3
DY
Id=12A(11.1~13.3m ohm,Qg=7.3nC) 84.07696.037
2
B B
A A
<Core Design>
Wistron Corporation
Title
VT385_1D5V_S3/RT9026_0D75V_S0
A2 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
X03 2/16
Vinafix.com RT8068A for 1D8V_S0
PG4701 D.C. =0.883A
1 2
D 1.29A < OCP <1.52A D
GAP-CLOSE-PW R-3-GP PU4701
PG4702 1D8V_PW R +1.8V_RUN
1 2 PW R_1D8V_PVDD 10 1
PVIN LX#1 PL4701
PR4701 PG4704
GAP-CLOSE-PW R-3-GP 1 2 PW R_1D8V_SVIN 9 2 PW R_1D8V_PHASE 1 2 1 2
PG4703 2D2R2F-GP PVIN LX#2 IND-1D5UH-71-GP-U
1
1 2 8 3 PR4703 GAP-CLOSE-PW R-3-GP
SVIN LX#3
1
PC4705
SC22P50V2JN-4GP
PC4703 68.1R510.20J 102KR2F-GP PG4705
GAP-CLOSE-PW R-3-GP SC1U6D3V2KX-GP 7 2nd = 68.1R51B.10Q 1 2
2
PW R_1D8V_EN NC#7
5
R1
2
EN
1
PC4701 PC4702 6 PC4706 PC4707 GAP-CLOSE-PW R-3-GP
FB
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
4 PG4706
DY
2
PGOOD
11 1 2
2
2
GND
RT8068AZQW ID-GP-U PW R_1D8V_FB GAP-CLOSE-PW R-3-GP
74.08068.A43 PG4707
1 2
1
GAP-CLOSE-PW R-3-GP
PR4704
51KR2F-L-GP
(36,45,78) RUN_ON
PR4726 1 DY 2 0R2J-2-GP R2
+3.3V_RUN
2
PR4722 1 2 0R0402-PAD-2-GP
(19,36,45,78) SIO_SLP_S3#
1
1
PC4704
SC22P50V2JN-4GP
PR4724
DY 10KR2F-2-GP
C C
2
Vo=0.6*(1+(R1/R2))
(78) 1.8V_RUN_PW RGD I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L
O/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L
Inductor: CHIP CHOKE 1.5UH PCMB042T-1R5MS4*4*2)(Rdc=38~46m ohm,Idc=4A,Isat=6A)ohm,Idc=21A,Isat=14.5A)/
68.1R510.20J
+3.3V_ALW
APL5930KAI for 1D5V_S0
1
PC4721
SC10U6D3V5MX-3GP
B B
2
Idesign =0.186A
PG4709
1 2
1D5V_PW R +1.5V_RUN
Vo(cal.)=1.51V GAP-CLOSE-PW R-3-GP
PR4727 1 DY 2 0R2J-2-GP PG4710
(36,45,78) RUN_ON PU4702
PW R_1D5V_EN 1 2
(19,36,45,78) SIO_SLP_S3# 1 2
PR4721 9 1 GAP-CLOSE-PW R-3-GP
VIN#9 GND PC4722
1
PW R_1D5V_ADJ
1
1
+3.3V_RUN PC4723 8 EN FB 2 PR4725
470KR2J-2-GP +1.5V_RUN_PW ROK 7 3 R1 DY DY PC4725
SC470P50V2JN-GP POK VOUT#3 PC4720
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
6 4 15KR2F-GP
SC68P50V2JN-1GP
2
VCNTL VOUT#4
2
2
1
VIN#5 5 +3.3V_ALW
+5V_RUN +5V_ALW
PR4729
10KR2F-2-GP 2
0R0402-PAD-2-GP
APL5930KAI-TRG-1-GP PW R_1D5V_ADJ
PWR_1D5V_VDD
1
1 PR4723
0R2J-2-GP
74.05930.B3D
1
PR4730
2
2nd = 74.07175.031
DY R2 PR4728
16K9R2F-GP
2
A <Core Design> A
1
PC4719 out=0.8V*(R1+R2)/R2
SC1U6D3V2KX-GP
Wistron Corporation
2

Title
RT8068A_1D8V_S0/APL5930_1D5V
A3 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_vccsa
Vinafix.com
D D
+VCC_SA
2
SCD1U10V2KX-L1-GP
2
PR4812
PC4837 DY
PR4829
1
100R2F-L1-GP-U
PW R_VCCSA_VID1 1 2 VCCSA_SEL1 (9)
0R0402-PAD-2-GP
1
PR4811 PR4810
(9) VCCSA_SENSE 2 1 PW R_VCCSA_VID0
0R0402-PAD 1 2 VCCSA_SEL0 (9)
0R0402-PAD-2-GP
1
DY PC4838
SCD1U10V2KX-L1-GP
2
PC4817
2
SC68P50V2JN-1GP
PR4825
1
+5V_ALW 1 2 1.05V_VTTPW RGD (27,45)
PR4814
0R0402-PAD-2-GP
1
1 2
C C
DY
SC2D2U10V3KX-L-GP
10R3F-GP
1
PC4814
1
SC1U10V2KX-1GP
2
PC4816 PC4835
SC1U6D3V2KX-GP
2
PU4801
2
7 VID1 1 2 +3.3V_RUN
VCCUSA_SENSE 8 6 PR4813 10KR2J-L-GP
PW R_VCCSA_FB VOUT VID0 PW R_VCCSA_EN
9 FB EN 5 PR4830
+5V_ALW PW R_VCCSA_VIN PW R_VCCSA_SVIN 10 4 PW R_VCCSA_PG 1 2
SVIN PG VCCSAPW ROK (27)
PG4801 11 3
PVIN LX#3 0R0402-PAD
1 2 12 PVIN LX#2 2
13 GND LX#1 1
GAP-CLOSE-PW R-3-GP
1
PG4802 PC4813 PC4812 PC4811

1 2 SY8037DDCC-GP
PL4801
SCD1U10V2KX-L1-GP
SC10U10V3MX-GP
SC10U10V3MX-GP
+VCC_SA
74.08037.B43
2
GAP-CLOSE-PW R-3-GP
PG4803 PW R_VCCSA_SW 1 2
1 2 COIL-D47UH-13-GP
68.R4710.20J Design Current =4 A
GAP-CLOSE-PW R-3-GP 2ND = 68.R4710.20N 6.6A<OCP< 7.8A
PC4815
SC22U6D3V5MX-2GP
PC4818
SC22U6D3V5MX-2GP
PC4819
SC22U6D3V5MX-2GP
PC4808
SCD1U25V3KX-L-GP
PG4804
1 2
1
GAP-CLOSE-PW R-3-GP DY
2
B B
VCCSA
VID0 VID1 ULV
L L 0.9V
L H 0.85V
H L 0.775V
H H 0.75V
A <Core Design> A
Wistron Corporation
Title
SY8037DDCC_VCCSA
A3 A00
Austin 13
5 4 3 2 1
SSID = VIDEO 11/29 LCD POWER
+3.3V_ALW +15V_ALW
0104
+LCDVDD +3.3V_ALW +LCDVDD_LCD +LCDVDD
LCD1
38
U4901
31 39 1 D D 6
SCD1U25V3KX-GP
2 D D 5 R4904
1
10KR2J-3-GP
R4914
470KR2J-2-GP
R4910
C4911
1 3 G S 4 1 2
1
32
2
3
DCBATOUT_LCD Vinafix.com BLON_OUT_C 1
RN4901
8 BLON_OUT
R4912
130R2J-GP
AO6402A-GP
84.06402.B3D
0R3J-0-U-GP
2
4 LCD_TST_C 2 7 LCD_TST (78) 2ND = 84.P2703.03D
2
5 CAM_MIC_CBL_DET# (18) 3 6 3rd = 84.03456.D3D
6 LCD_BRIGHTNESS LCD_BRIGHTNESS 4 5 BKLT_CTRL Prepare for
7 BLON_OUT_C
69.42001.271
1 4M7R6J-GP
R4909
8 +CAMERA_VDD_LCD
1
9 USB_CAMERA#_R SRN100J-4-GP Q4905
10 USB_CAMERA_R 2N7002KDW -GP C4912
33 11 DMIC_CLK_C 84.2N702.A3F SCD022U25V2KX-GP
2
12 DMIC_DATA_C 2ND = 84.DM601.03F
2
13 LCD_CBL_DET# (18) 3rd = 84.2N702.E3F
3
14 LVDSA_CLK_C 4th = 84.2N702.F3F
15 LVDSA_CLK#_C
16
17 LVDSA_DATA2_C RN4910
18 LVDSA_DATA2#_C LVDS_DDC_CLK_R 3 2 D4901
34 19 LVDS_DDC_DATA_R 4 1 +3.3V_RUN 1 Q4906
(17,78) ENVDD_PCH
20 LVDSA_DATA1_C 3
21 LVDSA_DATA1#_C SRN2K2J-1-GP 3 LCDVDD_EN 1 R1
22 2 DCBATOUT DCBATOUT_LCD
23 LVDSA_DATA0_C 2 R2
(78) LCD_VCC_TEST_EN
24 LVDSA_DATA0#_C RN4903 LTC043ZUB-FS8-GP Q4903
25 LVDS_DDC_DATA 3 2 BAT54CPT-2-GP 84.00043.011 6 D D 1
LVDS_DDC_DATA_R (17)
26 LVDS_DDC_CLK 4 1 LVDS_DDC_CLK_R (17) 75.00054.K7D 2ND = 84.05143.011 5 D D 2
1
C4906
35 27 LCD_TST_C 2ND = 75.00054.A7D 3rd = 84.00143.E1K 4 S G 3
SC1KP50V2KX-1GP
1
28 +3.3V_RUN_LCD SRN33J-5-GP-U R1=4.7KΩ R4913
29 100KR2J-1-GP SI3457CDV-T1-GE3-GP C4909
+LCDVDD R2=47KΩ
2
30 C4902 84.03457.A3D SCD1U25V3KX-GP
2
1
2
SCD1U16V2KX-3GP
C4904 0104 2nd = 84.00658.B3D

R4911
2
+3.3V_RUN_LCD +3.3V_RUN +CAMERA_VDD_LCD +CAMERA_VDD
SC1U6D3V2KX-GP
36 40
VSB_N_001 1 2 Q4903_G
2
37 R4901 R4902
1 2 1 2
D
IPEX-CON30-8-GP 47KR2J-2-GP
20.F2089.030 0R3J-0-U-GP 0R3J-0-U-GP Q4904

2ND = 20.F2173.030 Prepare for 69.41001.201 2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.2N702.W31
S
D4903 D4902 (27) EN_INVPW R 1 2 VSB_N_002
1 1 R4906 0R0402-PAD-2-GP
PANEL_BKEN_PCH (17) L_BKLT_CTRL (17)
1
BLON_OUT 3 BKLT_CTRL 3 DY C4901
SCD01U50V2KX-1GP
2
1
2 2
R4934
BAT54CPT-2-GP
PANEL_BKEN_EC (78)
R4931 BAT54CPT-2-GP
BIA_PW M_EC (27)
Webcam PWR CTRL
100KR2J-1-GP
75.00054.K7D 10KR2J-3-GP 75.00054.K7D +3.3V_RUN +CAMERA_VDD
Q4902
2ND = 75.00054.A7D 2ND = 75.00054.A7D
2
DMP2130L-7-GP
S
C4903 D
D
R4921 R4923 SCD1U16V2KX-3GP 84.02130.031 C4905
1
G
0R0402-PAD-2-GP 0R0402-PAD-2-GP 2ND = 84.00102.031
SCD1U16V2KX-3GP
LVDSA_CLK#_C 1 2 LVDSA_CLK# (17) LVDSA_DATA1#_C 1 2 LVDSA_DATA1# (17) 3rd = 84.03413.B31 C4910
G
SC10U10V5KX-2GP
2
CCD_OFF
(78) CCD_OFF
2
RN4908
DMIC_DATA_C 2 3 AUD_DMIC_IN0 (82,97) Close to LCD connector
DMIC_CLK_C 1 4 AUD_DMIC_CLK (82,97)
DY 68.02002.021 DY 68.02002.021
FILTER-4P-70-GP FILTER-4P-70-GP SRN33J-5-GP-U
TR4906 TR4908 0226
1
FILTER-4P-6-GP
LVDSA_CLK_C 1 2 LVDSA_CLK (17) LVDSA_DATA1_C 1 2 LVDSA_DATA1 (17) USB_CAMERA_R 2 1 USB_PP12 USB_PP12 (18)
R4922 R4924
0R0402-PAD-2-GP 0R0402-PAD-2-GP USB_CAMERA#_R 3 4 USB_PN12 USB_PN12 (18)
R4919 R4925 TR4901
0R0402-PAD-2-GP 0R0402-PAD-2-GP 69.10103.041
LVDSA_DATA2#_C 1 2 LVDSA_DATA2# (17) LVDSA_DATA0#_C 1 2 LVDSA_DATA0# (17) 2nd = 68.00201.141
0226
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA0#
2
LVDSA_DATA0
LVDSA_DATA1#
<Core Design>
LVDSA_DATA1
LVDSA_DATA2#
DY 68.02002.021 DY 68.02002.021 LVDSA_DATA2
FILTER-4P-70-GP
TR4907
FILTER-4P-70-GP
TR4909
Wistron Corporation
EC4901
EC4902
EC4903
EC4904
EC4905
EC4906
EC4907
EC4908
0102
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
1

1
Title
2
LVDSA_DATA2_C 1 2 LVDSA_DATA2 (17) LVDSA_DATA0_C 1 2 LVDSA_DATA0 (17)

LCD Connector
R4920 R4926 Size Document Number Rev
0R0402-PAD-2-GP 0R0402-PAD-2-GP A3
Austin 13 A00
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title

CRT Rev
A3 Austin 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO HDMI & HDMI CONNECTOR

Hot plug +3.3V_RUN
Vinafix.com
D D
1
R5107
Q5102 1MR2J-1-GP
G
2
(82) HPD_HDMI_CON D
S HDMI_PCH_DET (17)
1
2N7002K-2-GP
R5114 84.2N702.J31
20KR2J-L2-GP 2ND = 84.2N702.031
3rd = 84.2N702.W31
2
+5V_RUN
3
D5101
BAW 56-5-GP
C
83.00056.Q11 C
2nd = 83.3X102.011
HDMI DDC
D5101_2
3rd = 83.00056.R11
1
+3.3V_RUN D5101_1
3
4
RN5113
SRN2K2J-1-GP
Q5104
HDMI_DDC_CLK
2
1
4 3 HDMI_CON_CLK (82)
5 2
(17) HDMI_DDC_CLK 84.2N702.A3F
(17) HDMI_DDC_DATA 6 1 2nd = 84.DM601.03F
3rd = 84.2N702.E3F
HDMI_DDC_DATA 2N7002KDW -GP 4th = 84.2N702.F3F
HDMI_CON_DATA (82)
B B
<Core Design>
A A
Wistron Corporation
Title
HDMI Level Shifter/Connector

A3
Austin 13
Tuesday, February 26, 2013
A00
Date: Sheet 51 of 106
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title

ITP/Fan Connector Rev
A3
Austin 13 A00
5 4 3 2 1
Pin name Function
S1 Ground
SSID = SATA S2 A+
SATA HDD Connector S3

S4
A-
Ground
+3.3V_RUN_HDD
R5601 S5 B-
+3.3V_RUN 1 2
0R0603-PAD-2-GP
Vinafix.com S6 B+
1
C5602
C5609 SC3D3P50V2CN-GP S7 Ground
SC68P-GP
2
HDD1 P1 3.3V power
P1 23 P2 3.3V power
+5V_RUN_HDD V33 23
P2 V33 24 24
P3 P3 3.3V power
R5602 V33
NP1 NP1
+5V_RUN 1 2 P7 V5 NP2 NP2 P4 Ground
0R0603-PAD-2-GP P8
SC10U6D3V5KX-1GP
V5
P9 V5
P5 Ground
1
C5607
R5603 C5608
1 2 SCD1U16V2KX-3GP P13 V12 GND S1 P6 Ground
0R0603-PAD-2-GP P14 S4
2
V12 GND
P15 V12 GND S7 P7 5V power
GND P4
SCD01U50V2KX-1GP P5 P8 5V power
C5617 1 SATA_TXP0_C GND HDD_DET# (21)
(21) SATA_TXP0 2 S2 A+ GND P6
(21) SATA_TXN0 C5618 1 2 SATA_TXN0_C S3 P10 P9 5V power
SCD01U50V2KX-1GP A- GND
GND P12
C5615 1 2 SATA_RXP0_C S6 P10 Ground
(21) SATA_RXP0 C5616 1 SATA_RXN0_C B+
(21) SATA_RXN0 2 S5 B- DAS/DSS P11 FFS_INT2_Q (79)
P11 Reserved Reserve for FFS INT pin
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP SKT-SATA7P-15P-84-GP P12 Ground
22.10300.D01
P13 12V power
P14 12V power
P15 12V power
<Core Design>
Wistron Corporation
Title
HDD/ODD
A3
Austin 13 A00
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
ESATA
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
(Blanking)
C C
B B
A <Core Design> A
Wistron Corporation
Title
MIC/SPEAKER/AUDIO JACK
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Magnetic/RJ45
A3 Austin 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = Flash.ROM +3.3V_M
+3.3V_M
1
C6001 C6002
SCD1U16V2KX-3GP SCD1U16V2KX-3GP
Vinafix.com
2
2
2
R6004
4K7R2J-2-GP
R6005
4K7R2J-2-GP
D R6003 D
4K7R2J-2-GP DY SPI Flash ROM(8M) for PCH
1
SPI_HOLD#
U6001 +3.3V_M
(21) SPI_CS0# R6015 1 2 47R2J-2-GP SPI_CS0#_R 1 8

SPI_DIN_64 CS# VCC
2 DO/IO1 HOLD#/IO3 7
(78) SPI_W P#_SEL 1 DY 2 SPI_W P#_SEL_R 3 6 SPI_CLK64
R6001 0R2J-2-GP WP#/IO2 CLK SPI_DO64
4 GND DI/IO0 5
1
W 25Q64FVSSIG-GP
EC6002 DY 72.25Q64.F01 EC6003 EC6001
SC4D7P50V2CN-1GP 2ND = 72.25640.D01 SC4D7P50V2CN-1GP DY DY SC10P50V2JN-4GP
2
RN6002
2 3 SPI_DIN_64
(21) SPI_SO_R 1 4 SPI_DIN_32
C C
SRN33J-5-GP-U
RN6003
2 3 SPI_CLK32
(21) SPI_CLK_R 1 4 SPI_CLK64
SRN33J-5-GP-U
RN6004
2 3 SPI_DO64
(21) SPI_SI_R 1 4 SPI_DO32
SRN33J-5-GP-U
+3.3V_M
SPI Flash ROM(4M) for PCH

1
R6016
DY 4K7R2J-2-GP
U6002 +3.3V_M
2
(21) SPI_CS1# R6014 1 2 47R2J-2-GP SPI_CS1#_R 1 8

SPI_DIN_32 S# VCC SPI_HOLD#
2 DQ1 HOLD#/DQ3 7
SPI_W P#_SEL_R 3 6 SPI_CLK32
W#/VPP/DQ2 C SPI_DO32
4 VSS DQ0 5
B B
1
1
N25Q032A13ESEC0F-GP-U
EC6004 DY 72.25Q32.E01 EC6005 EC6006
SC4D7P50V2CN-1GP 2nd = 72.25320.C01 SC4D7P50V2CN-1GP DY DY SC10P50V2JN-4GP
2
2
SSID = RBATT +3.3V_ALW 2
RTC_AUX_S5 D6001
2
+RTC_VCC
3 R6002 RTC1
1KR2J-1-GP 3
1 RTC_PW R 1 2 1
2
C6003 CH715FPT-GP 2
A SC1U6D3V2KX-GP 4 <Core Design> A
1
83.R0304.B81
2nd = 83.00040.E81 1 ACES-CON2-20-GP
3rd = 83.R2004.C81 AFTP6001
Wistron Corporation
20.F1639.002 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2nd = 20.F1841.002 Taipei Hsien 221, Taiwan, R.O.C.
Title
+RTC_VCC
AFTP6002
1
Flash/RTC
A3 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C
(Blanking) C
B B
A <Core Design> A
Wistron Corporation
Title
USB3.0 Power SW
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
(Reserved)USB3.0 CONN
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
(Reserved)
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
(Resersed)WLAN
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = WWAN Mini Card Connector(WWAN)

Place near MINI Card CONN
Vinafix.com
3D3V_WWAN_AOAC
3D3V_WWAN_AOAC
WWAN1
53
PTC6602
WWAN NP1
ST330U6VDM-2-GP
SCD047U10V2KX-2GP
SCD047U10V2KX-2GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
1
1
WWAN_WAKE#
C6613
C6609
C6612
C6608
D (27,82) PCIE_WAKE# 1 2 1 2 D
WWAN R6606 0R2J-2-GP 3 4
MSATA_WWAN
MSATA_WWAN
MSATA_WWAN
MSATA_WWAN
77.23371.20L 5 6
2
2
2nd = 77.22271.27L 7 8 UIM_PWR
9 10 UIM_DATA
11 12 UIM_CLK R6604 1 2 33R2J-2-GP UIM_CLK_L
13 14 UIM_RESET WWAN
1
15 16 UIM_VPP
WWAN C6607
17 18 SC100P50V2JN-3GP
2
19 20 WWAN_RADIO_DIS#
PLT_RST#_R 1 WWAN_RADIO_DIS# (78)
21 22 2
C6625 SATA_RXP1_C PLT_RST# (18,27,71,77,78,82)
(21) SATA_RXP1 1 2 SCD01U50V2KX-1GP 23 24 R6609 0R0402-PAD-2-GP
(21) SATA_RXN1 C6626 1 2 SCD01U50V2KX-1GP SATA_RXN1_C 25 26
3D3V_WWAN_AOAC 27 28
PCH_SMBCLK_R R6619 1 20R2J-2-GP
C6627 SATA_TXN1_C
29 30
PCH_SMBDATA_R
DY PCH_SMBCLK (14,15,20,71,79,82)
1 2 SCD01U50V2KX-1GP 31 32 R6620 1 DY 20R2J-2-GP
SCD1U16V2KX-3GP
(21) SATA_TXN1 PCH_SMBDATA (14,15,20,71,79,82)
1
SATA_TXP1_C
C6606
(21) SATA_TXP1 C6624 1 2 SCD01U50V2KX-1GP 33 34
35 36 USB_PN5_C R6607 1 2 0R0402-PAD-2-GP USB_PN5 (18)
MSATA_WWAN
(18) PCIE_MCARD2_DET# 1 2 PCIE_MCARD2_DET#_R 37 38 USB_PP5_C R6608 1 2 0R0402-PAD-2-GP USB_PP5 (18)

2
R6611 39 40 USB_MCARD2_DET#
3D3V_WWAN_AOAC USB_MCARD2_DET# (22)
0R0402-PAD-2-GP 41 42 LED_WWAN_OUT#
43 44
45 46
47 48
49 50
(78) HW_GPS_DISABLE2# 51 52
NP2
54
SKT-MINI52P-163-GP
62.10043.K91
2ND = 20.80966.052
USB_MCARD2_DET# 1 DY 2PCIE_MCARD2_DET#
R6610 0R2J-2-GP
C C
+3.3V_ALW2 +15V_ALW
1
R6617 11/29
100KR2J-1-GP R6603 +3.3V_ALW 3D3V_WWAN_AOAC +3.3V_RUN 3D3V_WWAN_AOAC
WWAN WWAN100KR2J-1-GP
2
3.3V_WWAN_ENABLE# U6602
D Q6602
1 WWAN D 6
1
2 D D 5 R6613 G
3.3V_WWAN_ENABLE 3 G S 4 1 2 R6614
MSATA
0R3J-0-U-GP
100KR2J-1-GPWWAN D WIRELESS_LED# (68,78,82)
AO6402A-GP
C6601 84.06402.B3D S WWAN
2
6
1
2ND = 84.P2703.03D LED_WWAN_OUT#
1219
SC4700P50V2KX-1GP
Q6601 WWAN 3rd = 84.03456.D3D 2N7002K-2-GP
SIM1 WWAN 2N7002KDW-GP 84.2N702.J31
2
11 14 84.2N702.A3F 2ND = 84.2N702.031
12 8 2nd = 84.DM601.03F 3rd = 84.2N702.W31
1
3
5 3rd = 84.2N702.E3F
4th = 84.2N702.F3F
1 UIM_PWR
WWAN 6 UIM_VPP
2 UIM_RESET
(78) MCARD_WWAN_PWREN
4
1
7 UIM_DATA
10 3 UIM_CLK R6602
100KR2J-1-GP
B
9 13 WWAN B
CARDBUS8P-6-GP
2
62.10034.641
DATA and CLK need keep away at least 12mil
GND 1 AFTP6607
UIM_PWR 1 AFTP6608
UIM_VPP 1 AFTP6609
UIM_RESET 1 AFTP6610
UIM_CLK 1 AFTP6611
UIM_DATA 1 AFTP6612 3D3V_WWAN_AOAC
1219
1
D6602
WWAN R6612
UIM_RESET 1 6 UIM_VPP 1KR2J-1-GP
ESD_I/O1 ESD_I/O4 UIM_PWR
2 5
UIM_CLK 3
GND DY
VP
4 UIM_DATA
2
ESD_I/O2 ESD_I/O3
IP4220CZ6-1-GP
U6605_D
75.04220.07C
WWAN WWAN WWAN
SC1U6D3V2KX-GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
C6617
C6620
C6618
C6616
C6619
1
D
2
WWAN
WWAN WWAN
Layout Close to SIM1 Connector
G
A A
3.3V_WWAN_ENABLE#
U6605
2N7002K-2-GP <Core Design>
84.2N702.J31
2ND = 84.2N702.031
Wistron Corporation
Title
WWAN CONN/SIM SOCKET

A2
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
(Blanking)
C C
B B
<Core Design>
A
Wistron Corporation A
Title
Reserved
A4
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = User.Interface
All LED signal traces 10 mils width
+5V_ALW
FRONT POWER LED PLED1 0109 (27) KBC_PWRBTN#
R6801
3
+3.3V_ALW
1203
3
2K A1 2 1 PWRBT1
1219
LED-W-27-GP 5 6
Q6812 Vinafix.com
83.01221.R70
2nd = 83.00110.R70
330R2J-3-GP
SW-TACT4-14-GP
4
1
G R6802
D R6811 PSLED1 D
100KR2J-1-GP D K A 2 1
S LED-W-45-GP
2
330R2J-3-GP
(78) BREATH_LED# 83.19213.H70 62.40009.D71
2N7002K-2-GP 2nd = 62.40089.441
84.2N702.J31
2nd = 83.00191.F70
2ND = 84.2N702.031
KBC_PWRBTN# 1
3rd = 84.2N702.W31 AFTP6801
SATA HDD LED(White) +5V_ALW

0109
Q6805 HDLED1
R2
E R6808
3
SATA_LED#_C B
SC220P50V2KX-3GP
R1
C SATA_LED_R 1 1 2 SATA_LED_MB 1A K2
PDTA143ET-GP EC6810 LED-W-27-GP

84.00143.M11 330R2J-3-GP 83.01221.R70
2nd = 84.02143.011
DY 2nd = 83.00110.R70
2
3rd = 84.00143.K11
R1=R2=4.7K
+3.3V_ALW X01_1122
(21) SATA_ACT#
1
100KR2J-1-GP
1
+3.3V_RUN
R6812
C Q6806 C
R6809
4 3 100KR2J-1-GP
2
5 2
2
6 1 LED_SATA_DIAG_OUT# (78)
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F
Battery LED2(WHITE_LED) 0109
R6805
1 2 BAT_WHITE
(78) BAT2_LED#
WHITE
330R2J-3-GP +5V_ALW
LED-OW-4-GP
BAT_WHITE 2
-
B + B
1
BAT_AMBER 3
-
R6806 CHLED1
1 2 BAT_AMBER 83.01222.K70
(78) BAT1_LED#
2nd = 83.00326.G70
Battery LED1(AMBER_LED) 330R2J-3-GP ORANGE
WLAN_LED
+3.3V_ALW
11/29
+5V_ALW
Q6811
0109
1
A A
G Q6810 WLED1
R2
R6810 E R6804
3
100KR2J-1-GP D WIRELESS_LED#_Q B <Core Design>

R1
C WLAN_LED 1 2 WLAN_LED_R 1A K2
S
2
(66,78,82) WIRELESS_LED#
PDTA143ET-GP
84.00143.M11 330R2J-3-GP
LED-W-27-GP
Wistron Corporation
2N7002K-2-GP
2nd = 84.02143.011
83.01221.R70 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
84.2N702.J31 Taipei Hsien 221, Taiwan, R.O.C.
3rd = 84.00143.K11 2nd = 83.00110.R70
2ND = 84.2N702.031 R1=R2=4.7K Title
3rd = 84.2N702.W31
LED Bard/Power Button
Custom
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
TP_PW R +5V_RUN
SSID = KBC SSID = Touch.Pad 1
R6908
DY 2
TP_PW R
Layout:
KBC SMSC ECE1117 TP_PW R 0R2J-2-GP
+3.3V_RUN
Close each VCC pin. U6901 TouchPad Connector R6909
1 2
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
+3.3V_ALW 4 11 KSO0
VCC KSO00
1
2
1
24 13 KSO1 C6901 0R0402-PAD-2-GP
Vinafix.com
VCC KSO01
2
37 12 KSO2 RN6901 SCD1U16V2KX-3GP
VCC KSO02
C6902
C6906
KSO3
C6903
14 SRN4K7J-8-GP
2
KSO03 KSO4 TPAD1
16
1
KSO04 KSO5
D
KSO05 17 5 D
15 KSO6 3rd = 68.00217.631
4
3
KSO06 KSO11
38 GPIO10 KSO11 5 2ND = 68.00909.051 1
KB_LED_DET# 39 10 KSO12 68.00084.881
KB_BL_CTRL GPIO11 KSO12 KSO13 L6901 1
40 GPIO12/PWM1 KSO13 7 (27) CLK_TP_SIO 2 BLM18AG601SN-3GP TP_CLK 2
CAP_LED# 41 6 KSO14 (27) DAT_TP_SIO L6902 1 2 BLM18AG601SN-3GP TP_DATA 3
GPIO13/PWM2 KSO14
SC10P50V2JN-4GP
SC10P50V2JN-4GP
42 8 KSO15 68.00084.881 4
GPIO14/PWM3 KSO15 KSO16
43 9 2ND = 68.00909.051
EC6902
EC6903
GPIO15/PWM4/BC_INT_DN3#/SMB_INT_DN3# KSO16
SC10P50V2JN-4GP
SC10P50V2JN-4GP
44 3 KSO17 1 TP6901 TPAD14-OP-GP 3rd = 68.00217.631 1 6
GPIO20/PWM7 KSO17 KSO18 TP6902 TPAD14-OP-GP AFTP6905
2 1
EC6904
EC6905
GPIO01/KSO18
1
+3.3V_ALW 1 KSO19 1 TP6903 TPAD14-OP-GP ACES-CON4-50-GP
2
GPIO00/KSO19 KSO20
GPIO23/KSO20/PWM8 47
46
20.K0722.004
2
GPIO22/KSO21/PWM9
GPIO21/KSO22 45 2nd = 20.K0397.004
1 TP_PW R
AFTP6920 1 TP_CLK
31 AFTP6932 1 TP_DATA
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
GPIO04/BC_DAT_DN1/SMB_DAT_DN1/TP_DAT
1
30 AFTP6929
GPIO03/BC_CLK_DN1/SMB_CLK_DN1/TP_CLK
R6903
R6904
R6912
DY DY
36 GPIO07/BC_DAT_DN2/SMB_DAT_DN2/PS2_DAT
35
BC link GPIO06/BC_CLK_DN2/SMB_CLK_DN2/PS2_CLK
2
34
KB Backlight Connector
(27) BC_DAT_ECE1117 BC_DAT_UP/SMB_DAT_UP
33 18 KSI0
(27) BC_CLK_ECE1117 BC_CLK_UP/SMB_CLK_UP KSI0
32 20 KSI1
(27) BC_INT#_ECE1117 BC_INT_UP#/SMB_INT_UP# KSI1
23 KSI2 +5V_RUN +5V_KB_BL
C KSI2 KSI3 C
KSI3 19
2 1 KBC_SMB_ADDR 28 25 KSI4 F6901
R6911 10KR2J-3-GP SMB_ADDR KSI4 KSI5
KBC_TEST_PIN
48 OCS_TRM KSI5 22
KSI6
1 DY 2
MAX 260mA
2 DY 1 29 TEST_PIN KSI6 26
1
R6910 10KR2J-3-GP 27 KSI7 FUSE-D5A6V-2-GP C6905
KSI7 SCD1U16V2KX-3GP
KBC_VR_CAP
KBL
21 1 KBL 2 R6902
2
VR_CAP +3.3V_ALW 0R2J-2-GP
1
49 KBLIT1
C6904 GND
5
1
SC4D7U6D3V3KX-GP 1
2
ECE1117-HZH-GP R6914 Q6903

Pin28 SMBus Address select strap pin. KBL100KR2J-1-GP KBL G KB_LED_DET 2
10K pull ground=0111 000b
71.01117.003 3 KBL
1
10K pull VCC=0111 001b JOENS KB KB_LED_DET# D 4
2
R6913
KB_BL_CTRL#
6
Pin29 has a weak internal pull-down S KBL100KR2J-1-GP PTW O-CON4-14-GP
2N7002K-2-GP 20.K0613.004
2
84.2N702.J31 2nd = 20.K0589.004
Internal KeyBoard Connector 2nd = 84.2N702.031 1
3rd = 84.2N702.W31 AFTP6935
D
KB1 1 AFTP6917
31 Q6901
1 P8503BMG-GP
KB_DET# (22) KB_BL_CTRL
KSI7
G KBL 84.P8503.031
2 1 2ND = 84.03404.C31
1
3 KSI6 1 AFTP6921
S
B KSI4 AFTP6930 R6901 B
4 1
5 KSI2 1 AFTP6923 100KR2J-1-GPKBL
6 KSI5 1 AFTP6907 +5V_KB_BL 1
7 KSI1 1 AFTP6919 KB_LED_DET 1 AFTP6936
2
8 KSI3 1 AFTP6912 KB_BL_CTRL# 1 AFTP6937
9 KSI0 1 AFTP6924 AFTP6938
10 KSO5 1 AFTP6915
11 KSO4 1 AFTP6908
12 KSO11 1 AFTP6914
13 KSO6 1 AFTP6928
14 KSO12 1 AFTP6910
15 KSO3 1 AFTP6909
16 KSO1
KSO2
1 AFTP6904
AFTP6911
CAP LED CONTROL
17 1
KSO0 AFTP6931 +5V_RUN
18
KSO16
1
AFTP6906
High Active from KBC GPIO. Q6902
19 1
20 KSO20 1 AFTP6926
R2
E CAP_LED_R
21 KSO19 1 AFTP6934 CAP_LED# 1 2Q6902_B B R6906
R1
22 KSO17 1 AFTP6916 R6905 0R2J-2-GP C CAP_LED_Q 1 2
23 KSO18 1 AFTP6925
24 KSO13 1 AFTP6922 PDTA143ET-GP 1KR2J-1-GP
25 KSO15 1 AFTP6933 84.00143.M11
26 KSO14 1 AFTP6918 2nd = 84.02143.011
27 AFTP6927CAP_LED_R CAP_LED_R 3rd = 84.00143.K11
28 R1=R2=4.7K
29 1 2
30 1 CAP_LED:(X01 Low actived) R6907 DY 100R2J-2-GP
32 AFTP6913
Connect to KB driving internal LED directly.(MAX 25mA)
A <Core Design> A
ACES-CON30-10-GP
20.K0592.030
2nd = 20.K0565.030 Wistron Corporation
Title
Key Board/Touch Pad

A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = User.interface
Vinafix.com
D D
AFTP80 AFTE14P-GP 1 +3.3V_ALW

AFTP81 AFTE14P-GP 1 LID_CLOSE#_1
+3.3V_ALW
C C
+3.3V_ALW
1
C7002
SCD1U16V2KX-3GP DY LID1
1
5
2
R7001 AFTP82 1
100KR2J-1-GP AFTE14P-GP 1
2
(78) LID_CL# LID_CL# 1 2 LID_CLOSE#_1 3
R7002 10R2F-L-GP 4
1
C7001 6
SCD047U16V2KX-1-GP
2
ACES-CON4-39-GP
20.K0422.004
2nd = 20.K0382.004
3rd = 20.K0465.004
B B
A <Core Design> A
Wistron Corporation
Title
Hall Sensor
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = DEBUG PORT

Debug Connector
+3.3V_RUN
DB1
11
LPC_LAD[3..0] 1
(21,27,77,78) LPC_LAD[3..0]
Vinafix.comLPC
LPC_LAD0 R7104 1 2 0R2J-2-GP LPC_LAD0_R 2
LPC_LAD1 R7105 1 LPC 2 0R2J-2-GP LPC_LAD1_R 3
D LPC_LAD2 R7106 1 LPC 2 0R2J-2-GP LPC_LAD2_R 4 D
LPC_LAD3 R7107 1 LPC 2 0R2J-2-GP LPC_LAD3_R 5 LPC
R7108 1 LPC 2 0R2J-2-GP LPC_LFRAME#_R 6
(21,27,77,78) LPC_LFRAME#
(18,27,66,77,78,82) PLT_RST# 7
8
1 2 CLK_PCI_LPC_R 9
(20,77) CLK_PCI_TPM_TCM R7103 0R2J-2-GP
LPC 10
12
PAD-10P-177042-GP
ZZ.00PAD.Y41
DB1 P/N:20.D0183.110
CPU XDP
+3.3V_ALW
XDP1
2
NP1
R5840 61
DY 1KR2J-1-GP 1 2
62
XDP_PREQ# 3 4 CFG16
1
(5) XDP_PREQ# XDP_PRDY# CFG17 CFG16 (7)

(5) XDP_PRDY# 5 6 CFG17 (7)
SYS_PW ROK_XDP 7 8
XDP_OBS0 9 10 CFG0
(5) XDP_OBS0 CFG0 (7)
C XDP_OBS1 11 12 CFG1 C
13 14
XDP_OBS2 15 16 CFG2
XDP_OBS3 17 18 CFG3
19 20
CFG10 21 22 CFG8
(7) CFG10 CFG11 CFG9 CFG8 (7)
(7) CFG11 23 24 CFG9 (7)
25 26 +1.05V_RUN_VTT
Place R near XDP1 CONN XDP_OBS4 27 28 CFG4
XDP_OBS5 29 XDP 30 CFG5
within 2" (5) XDP_OBS5
31 32
CFG5 (7)
1
XDP_OBS6 33 34 CFG6 C5802
XDP_OBS7 35 36 CFG7 XDP SCD1U16V2KX-3GP
37 38
2
+1.05V_RUN_VTT R5803 1 2 1KR2J-1-GP H_CPUPW RGD_XDP CLK_XDP
(5,22) H_CPUPW RGD
R5804 1
XDP 0R2J-2-GP CFD_PW RBTN#_XDP
39 40
CLK_XDP#
(19) SIO_PW RBTN#_R XDP 2 41 42
43 44
CFG0 R5809 1 XDP 2 1KR2J-1-GP XDP_HOOK2 45 46 XDP_RST#_R R5805 1 XDP 2 1KR2J-1-GP PLTRST_XDP# (18)
R5806 1 XDP 2 0R2J-2-GP SYS_PW ROK_XDP 47 48 XDP_DBRESET# XDP_DBRESET# (5,19)
(19,78) SYS_PW ROK
49 50
R5810 1 XDP 2 0R2J-2-GP SMBDATA_XDP 51 52 XDP_TDO XDP_TDO (5)
(14,15,20,66,79,82) PCH_SMBDATA
R5811 1 XDP 2 0R2J-2-GP SMBCLK_XDP 53 54 XDP_TRST#
(14,15,20,66,79,82) PCH_SMBCLK XDP_TRST# (5)
55 56 XDP_TDI
XDP_TCLK XDP_TMS XDP_TDI (5)
(5) XDP_TCLK 57 58 XDP_TMS (5)
59 60
63
64
NP2
B PAD-60P-GP B
ZZ.00PAD.Q81
XPD Conn 20.F0971.060
CLK_XDP 1 XDP 2 CLK_CPU_ITP (20)

R5807 0R2J-2-GP
CLK_XDP# 1 XDP 2 CLK_CPU_ITP# (20)
R5808 0R2J-2-GP
(7) CLK_XDP_ITP 1
R5841
DY 2
0R2J-2-GP
(7) CLK_XDP_ITP# 1
R5842
DY 2
0R2J-2-GP
<Core Design>
A A
Wistron Corporation
Title
Dubug connector
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
SD CONN
Vinafix.com SD/MMC Card Connector
D 3D3V_RUN_CARD D
3D3V_RUN_CARD
CARD1
P13 SD_VCC XD_CD 1

XD_R/B 2
10KR2J-3-GP
P22 MS_VCC XD_RE 3
C3207
SC4D7U6D3V3KX-GP
C3245
SCD1U16V2KX-3GP
R3201
XD_CE 4
1
18 XD_VCC XD_CLE 5
1
XD_ALE 6
XD_WE 7
(32) SD/MMCDAT0 P4 8
2
SD_DAT0 XD_WP_IN
(32) SD/MMCDAT1 P3
2
SD_DAT1
(32) SD/MMCDAT2 P25 SD_DAT2 XD_D0 10
(32) SD/MMCDAT3 P23 SD_DATA3 XD_D1 11
XD_D2 12
(32) SD/MMC_CLK P10 SD_CLK XD_D3 13
(32) SD/MMCCD#
(32) SDWP
P1
P2
SD_CD XD_D4 14
15
Layout Note:Close to Card Reader CONN
SD_WP XD_D5
(32) SD/MMCCMD P19 SD_CMD XD_D6 16
C 17 C
XD_D7
Note: The trace need to route as P9 MS_BS
daisy-chain and the trace of SD signals P16 MS_INS SD_WP_COM/SDIO_GND P26
need to route as short as possible P20 MS_SCLK SD_CD_COM/SDIO_GND P27
SD_GND P7
P12 MS_DATA0 SD_GND P15
P11 MS_DATA1
P14 MS_DATA2 MS_GND P6
P18 MS_DATA3 MS_GND P24
XD_GND 9
(32) SD/MMCDAT4 P21 MMC_DATA4 XD_GND 19
(32) SD/MMCDAT5 P17 MMC_DATA5
(32) SD/MMCDAT6 P8 MMC_DATA6 NP1 NP1
(32) SD/MMCDAT7 P5 MMC_DATA7 NP2 NP2
CARD-PUSH-46P-2-GP
B
20.I0135.001 B
1225
SD/MMCDAT0
SD/MMCDAT1
SD/MMCDAT2
SD/MMCDAT3
SD/MMC_CLK R7401 1 DY 2 33R2J-2-GP SD/MMC_CLK_R
SD/MMCCMD
<Core Design>
SD/MMCDAT4
SD/MMCDAT5
SD/MMCDAT6
SD/MMCDAT7 Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
1
1
SC10P50V2JN-4GP
EC7401
SC10P50V2JN-4GP
EC7402
SC10P50V2JN-4GP
EC7403
SC10P50V2JN-4GP
EC7404
SC10P50V2JN-4GP
EC7405
SC10P50V2JN-4GP
EC7408
SC10P50V2JN-4GP
EC7409
SC10P50V2JN-4GP
EC7410
SC10P50V2JN-4GP
EC7411
SC10P50V2JN-4GP
EC7412
DY DY DY DY DY DY DY DY DY DY Title
2
Card Reader CONN

A4
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
<Core Design>
A A
Wistron Corporation
Title
(Reserved)
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = TPM
3D3V_RUN_TPM TPM Chip

Vinafix.com U7701
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
3D3V_SB3V
SCD1U16V2KX-3GP
+3.3V_RUN 3D3V_RUN_TPM 10 1
VCC ATEST#1
1
D D
C7708
C7707
C7706
19 VCC ATEST#2 2
C7709
R7715 24 3 TCM_BA1
VCC ATEST#3
SC4700P50V2KX-1GP
1 2 3D3V_RUN_TPM
2
C7711
SCD1U16V2KX-3GP
C7710
5 7 TPM_PP 1 DY 47KR2F-GP
2
3D3V_RUN_TPM 0R0402-PAD-2-GP 3D3V_SB3V SB3V NC#7 R7724
12 NC_12 1 TP7701
1
R7716 NBO#12
NBO#13 13
1 2 NBO#14 14
8 TESTL
0R0402-PAD-2-GP TCM_BA0 9 26 LPC_LAD0
TESTBL LAD0 LPC_LAD0 (21,27,71,78)
23 LPC_LAD1
LAD1 LPC_LAD1 (21,27,71,78)
20 LPC_LAD2
LAD2 LPC_LAD2 (21,27,71,78)
TP7702 1 NC_6 6 GPIO-EXPRESS-00 LAD3 17 LPC_LAD3
LPC_LAD3 (21,27,71,78)
CLKRUN# 15
(19,27,78) CLKRUN# CLKRUN#
(18,27,66,71,78,82) PLT_RST# 16 LRESET#
(20,71) CLK_PCI_TPM_TCM 1 2CLK_PCI_TPM_TCM_R 21 LCLK GND 4
R7725 0R0402-PAD-2-GP 22 11
(21,27,71,78) LPC_LFRAME# LFRAME# GND
(21,27,78) IRQ_SERIRQ 27 SERIRQ GND 18
SP_TPM_LPC_EN_R 28 25
LPCPD# GND
AT97SC3204-X2A1D-AB-GP
2 71.97324.A0W
(78) SP_TPM_LPC_EN 3
DY 1
D7703
C
BAS16-6-GP C
83.00016.K11
2ND = 83.00016.F11 3D3V_RUN_TPM
CLK_PCI_TPM_TCM R7717
1 2
1
0R0402-PAD-2-GP
R7720
33R2J-2-GP DY
3D3V_RUN_TPM
1
1 DY 2
2
R7719 R7721
R7718 DY 10KR2J-3-GP DY 10KR2J-3-GP
1
EC7713 4K7R2J-2-GP
SC22P50V2JN-4GPDY
2
TCM_BA0
2
TCM_BA1
1
R7722 R7723
4K7R2J-2-GP 4K7R2J-2-GP
2
B B
A A
<Core Design>
Wistron Corporation
Title
TPM/TCM
Custom A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = SIO
+3.3V_ALW
BC_CLK_ECE5048
BC_CLK_ECE5048 (27)
BC_DAT_ECE5048
Vinafix.com BC_INT#_ECE5048
BC_DAT_ECE5048 (27)
BC_INT#_ECE5048 (27)
C7803
SC10U6D3V5KX-1GP
+3.3V_RUN
1
C7802
SCD1U16V2KX-3GP
C7804
SCD1U16V2KX-3GP
C7805
SCD1U16V2KX-3GP
C7806
SCD1U16V2KX-3GP
C7807
SCD1U16V2KX-3GP
D DY D_CLKRUN# R7807
D
1 2 100KR2J-1-GP
2
D_SERIRQ R7808 1 2 100KR2J-1-GP
LPC_LAD0 LPC_LAD0 (21,27,71,77)
LPC_LAD1 D_DLDRQ1# R7809 1 2 100KR2J-1-GP
LPC_LAD1 (21,27,71,77)
LPC_LAD2 LPC_LAD2 (21,27,71,77)
LPC_LAD3 EXPRESS_DET# R7810 1 2 100KR2J-1-GP
LPC_LAD3 (21,27,71,77)
LPC_LDRQ1# SMART_DET# R7811 1 2 100KR2J-1-GP
LPC_LDRQ1# (21)
PCMCIA_DET# R7812 1 2 100KR2J-1-GP
A17
A43
A54
B30
A30
B31
A29
B29
B28
A25
A24
A27
A26
B26
B25
A23
A22
B5
U7801 MCARD_PCIE_SATA# R7813 1 2 100KR2J-1-GP
VCC1
VCC1
VCC1
VCC1
VCC1
BC_CLK
BC_INT#
DLAD0
DLAD1
DLAD2
DLAD3
LAD0
LAD1
LAD2
LAD3
LDRQ0#
LDRQ1#
BC_DAT
R7826 SP_TPM_LPC_EN R7814 2 10KR2J-3-GP
0R0402-PAD-2-GP
1 DY
R7841 1 2 PM_LANPHY_ENABLE (22)
0R0402-PAD-2-GP
B52 B47 LAN_DISABLE# 1 2 LAN_DISABLE#_R (82)
SIO_GPIOA1 GPIOA0 GPIOG0/TACH5 CHARGE_EN
A49 A45
+3.3V_ALW GPIOA1 GPIOG1 SYS_LED_MASK#
B53 B48
PROCHOT_GATE GPIOA2 GPIOG2 DYN_TURB_PWR_ALRT#
(40) PROCHOT_GATE A50 A46
GPIOA3 GPIOG3 SIO_EXT_WAKE#_R R7802 1
(70) LID_CL# B54 B49 2 0R0402-PAD-2-GP SIO_EXT_WAKE# (22)
DOCK_SMB_ALERT# GPIOA4 GPIOG4 WIRELESS_LED#
A51 A47 WIRELESS_LED# (66,68,82)
GPIOA5 GPIOG5 USB_PWR_SHR_VBUS_EN
B55 B50 USB_PWR_SHR_VBUS_EN (82)
R7834 DYN_TURB_PWR_ALRT# GPIOA6 GPIOG6 WLAN_RADIO_DIS#
1 2 10KR2J-3-GP A52 A48 WLAN_RADIO_DIS# (82)
GPIOA7 GPIOG7/TACH6
R7835 1 2 100KR2J-1-GP HW_GPS_DISABLE2# B13 WIRELESS_ON#/OFF
GPIOH0 BT_RADIO_DIS# RUN_ON R7816
A33 A13 BT_RADIO_DIS# (82) 1 2 100KR2J-1-GP
R7836 PROCHOT_GATE GPIOB0 GPIOH1 WWAN_RADIO_DIS#
1 2 100KR2J-1-GP USB3.0 power switch on DB is active low. B36 A53 WWAN_RADIO_DIS# (66)
ESATA_USB_PWR_EN# GPIOB1 SYSOPT1/GPIOH2 SYS_PWROK CPU_VTT_ON R7817
(82) ESATA_USB_PWR_EN# B44 B57 SYS_PWROK (19,71) 1 2 100KR2J-1-GP
R7837 CPU_DETECT# GPIOB2 SYSOPT0/GPIOH3 DGPU_SELECT#
1 2 100KR2J-1-GP (82) AUD_HP_NB_SENSE A41 B14 1 TP7821
GPIOB3 GPIOH4 0.675V_DDR_VTT_ON R7818
(49) CCD_OFF B43 A14 1 2 100KR2J-1-GP
R7838 GPIOD3 GPIOB4 GPIOH5 CPU_VTT_ON
1 2 100KR2J-1-GP (49) LCD_VCC_TEST_EN A40 B17 CPU_VTT_ON (45)
GPIOB5 GPIOH6 PCH_DPWROK_SIO R7803 1 SLICE_BAT_ON
(66) MCARD_WWAN_PWREN B42 B18 DY 2 0R2J-2-GP PCH_DPWROK (19) R7819 1 2 100KR2J-1-GP
R7839 WWAN_RADIO_DIS# GPIOB6 GPIOH7
1 2 100KR2J-1-GP (82) AUD_NB_MUTE# A39
GPIOB7 SUS_ON R7821
B63 SIO_SLP_A# (19,36,45) 1 2 100KR2J-1-GP
R7840 USB_PWR_SHR_EN# GPIOI1 0.675V_DDR_VTT_ON
1 2 100KR2J-1-GP A60 0.675V_DDR_VTT_ON (46)
DOCK_DET# GPIOI2/TACH0 LCD_TST R7823
B41 A61 SIO_SLP_S4# (19,36,46) 1 2 100KR2J-1-GP
GPIOC0 GPIOI3
A38 B65 SIO_SLP_S3# (19,36,45,47)
GPIOC1 GPIOI4 SYS_LED_MASK# R7822
C A34 A62 IMVP_PWRGD (42) 1 2 10KR2J-3-GP C
R7842 ESATA_USB_PWR_EN# GPIOC2 GPIOI5 IMVP_VR_ON_R
1 2 100KR2J-1-GP B37 B66 R7804 1 2 0R0402-PAD-2-GP IMVP_VR_ON (42)
GPIOC3 GPIOI6 DGPU_PWR_EN R7824
(49) PANEL_BKEN_EC A35 A63 1 2 100KR2J-1-GP
R7843 USB_PWR_SHR_VBUS_EN GPIOC4 GPIOI7
1 2 100KR2J-1-GP (17,49) ENVDD_PCH B38
LCD_TST GPIOC5 GFX_MEM_VTT_ON R7825
(49) LCD_TST A36 B67 AUX_EN_WOWL (82) 1 2 100KR2J-1-GP
R7844 SIO_FAN1_DET# GPIOC6/TACH4 GPIOJ0
1 2 10KR2J-3-GP (38) PSID_DISABLE# A37 A64 WLAN_LAN_DISB# (82)
GPIOC7 GPIOJ1/TACH1 CHARGE_EN R7847
A5 SIO_SLP_LAN# (19,82) 1 2 100KR2J-1-GP
R7845 ZODD_WAKE# GPIOJ2/TACH2
1 2 10KR2J-3-GP B6 SIO_SLP_SUS# (19)
PBAT_PRES# GPIOJ3 SIO_GPIOJ4
(39) PBAT_PRES# B40 A6 1
R7846 LOM_SMB_ALERT# GPIOD0 GPIOJ4
1 2 10KR2J-3-GP B32 B7 TP7856 TPAD14-OP-GP
SLICE_BAT_ON GPIOD1 GPIOJ5
A31 A7
R7853 LOM_ENERGY_DET GPIOD3 GPIOD2 GPIOJ6
1 2 10KR2J-3-GP B33 B8
EXPRESS_DET# GPIOD3 GPIOJ7
B15
R7854 DOCK_SMB_ALERT# SMART_DET# GPIOD4 ME_FWP
1 2 10KR2J-3-GP A15 A8 ME_FWP (21)
PCMCIA_DET# GPIOD5 GPIOK0 MASK_SATA_LED#
B16 B9 1 TP7857 TPAD14-OP-GP
R7850 PBAT_PRES# GPIOD6 GPIOK1/TACH3
1 2 100KR2J-1-GP A16 B10 1.8V_RUN_PWRGD (47)
GPIOD7 GPIOK2
A10 LED_SATA_DIAG_OUT# (68)
R7855 DOCK_DET# GPIOK3 TEMP_ALERT#_R
1 2 10KR2J-3-GP B11 R7805 1 2 0R0402-PAD-2-GP TEMP_ALERT# (22)
GPIOK4 RUN_ON
A1 A11 RUN_ON (36,45,47)
R7815 WIRELESS_ON#/OFF USB_PWR_SHR_EN# GPIOE0/RXD GPIOK5
1 2 100KR2J-1-GP (27,82) USB_PWR_SHR_EN# B2 B12 AC_DIS (38)
GFX_MEM_VTT_ON GPIOE1/TXD GPIOK6
A2 A12 SPI_WP#_SEL (60)
MCARD_PCIE_SATA# GPIOE2/RTS# GPIOK7
B3
+5V_ALW CPU_DETECT# GPIOE3/DSR# SUS_ON
(5) CPU_DETECT# A3 B60 SUS_ON (36)
DGPU_PWR_EN GPIOE4/CTS# GPIOL0/PWM7
B45 A57
SIO_FAN1_DET# GPIOE5/DTR# GPIOL1/PWM8
(28) FAN1_DET# 2 DY 0R2J-2-GP
1 A42
GPIOE6/RI# GPIOL2/PWM0
B64 BAT1_LED# (68) Trace width 10 mils
R7801 TP7872 1 DP_HDMI_HPD B4 B68
R7856 SIO_GPIOA1 GPIOE7/DCD# GPIOL3/PWM1
1 2 10KR2J-3-GP A9 BAT2_LED# (68) Trace width 10 mils
GPIOL4/PWM3
B1
ZODD_WAKE# GPIOL5/PWM2 USH_PWR_ON TP7854
A59 A18 1
LOM_SMB_ALERT# GPIOF0 GPIOL6
B62 A44
GPIOF1 GPIOL7/PWM5
(19) SUSACK# A58
LOM_ENERGY_DET GPIOF2 CLK_SIO_14M
B61 A32 CLK_SIO_14M (20)
TP7855 GPIOF4 GPIOF3/TACH8 14_318MHZ/GPIOM0 HW_GPS_DISABLE2#
1 A56 B34 HW_GPS_DISABLE2# (66)
VGA_ID GPIOF4/TACH7 GPIOM1
B59 B35 EC_32KHZ_ECE5048 (27)
TP7801 3.3V_RUN_GFX_ON GPIOF5 CLK32K/GPIOM2
1 A55 B39 BREATH_LED# (68)
SLP_ME_CSW_DEV# GPIOF6 GPIOM3/PWM4
B58 B51
DCLKRUN#
DLFRAME#
(22) SLP_ME_CSW_DEV#
DSER_IRQ
GPIOF7 GPIOM4/PWM6
TEST_PIN
CLKRUN#
CAP_LDO
DLDRQ1#
LFRAME#
LRESET#
SER_IRQ
PWRGD
PCICLK
OUT65
GND
VSS
B ECE5048-LZY-GP B
71.05048.003
B56
B19
B46
A28
B20
A19
B24
B23
A21
B22
B21
A20
A4
C1
B27
SP_TPM_LPC_EN
(77) SP_TPM_LPC_EN
R7806 1 2 1KR2F-3-GP SIO_TEST_PIN
C7801 1 2 SC4D7U6D3V3KX-GP CAP_LDO
CLK_PCI_5048
(18) CLK_PCI_5048
(19,27,77) CLKRUN#
D_CLKRUN#
+3.3V_ALW D_DLDRQ1#
(21,27,71,77) LPC_LFRAME#
(18,27,66,71,77,82) PLT_RST#
(21,27,77) IRQ_SERIRQ
D_SERIRQ
1
(5,27) RUNPWROK
R7832
100KR2J-1-GP
2
VGA_ID
1
CLK_PCI_5048 CLK_SIO_14M
DY R7833
100KR2J-1-GP ME_FWP PCH has internal 20K PD.
(suspend power rail)
2
ME_FWP
DY R7830
10R2F-L-GP
DY R7829
10R2F-L-GP
1CLK_PCI_5048_R 2
CLK_SIO_14M_R2
A A
1
VGA_ID0 R7831
DY 1KR2F-3-GP
Discrete 0
2
<Core Design>
1
C7811 C7810
UMA 1 DY SC4D7P50V2CN-1GP DY SC4D7P50V2CN-1GP
Wistron Corporation
2

Title
SIO - ECE5048
A2 A00
Austin 13
5 4 3 2 1
5 4 3 2 1
SSID = User.interface
Vinafix.com
D Free Fall Sensor D
Note
- no via, trace, under the sensor (keep out area around 2mm)
- stay away from the screw hole or metal shield soldering joints
- design PCB pad based on our sensor LGA pad size (add 0.1mm)
- solder stencil opening to 90% of the PCB pad size
+3.3V_RUN
- mount the sensor near the center of mass of the NB as possible as you can
R7901
3D3V_RUN_FFS 1 2
0R0603-PAD-2-GP +3.3V_RUN
U7901
C7903
1
C7901
SC10U6D3V3MX-GP
10 RES#10 VDD_IO 1
1
C7902
SCD1U16V2KX-3GP
13 R7902
RES#13
SCD1U16V2KX-3GP
100KR2J-1-GP
15 RES#15 VDD 14 DY
16
2
RES#16 +3.3V_RUN
2
(14,15,20,66,71,82) PCH_SMBCLK 4 SCL/SPC INT1 11
6 9 HDD_FALL_INT
(14,15,20,66,71,82) PCH_SMBDATA SDA/SDI/SDO INT2 HDD_FALL_INT (18)
1
3D3V_RUN_FFS 7 8 R7903
SDO/SA0 CS 100KR2J-1-GP
C 5 2 C
2
GND NC#2 FALL_INT2
12 GND NC#3 3
LNG3DMTR-GP
Q7901
1
74.LNG3D.0BZ 2N7002KDW -GP
+3.3V_RUN 84.2N702.A3F +5V_RUN
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
1
4th = 84.2N702.F3F
6
R7906
100KR2J-1-GP
DY R7904
100KR2J-1-GP
DY
2
FFS_INT2
FFS_INT2_Q (56)
Note
1 2 R7905
DY 0R2J-2-GP
(1) Keep all signals are the same trace width. (included VDD, GND).
(2) No VIA under IC bottom. FFS_INT2 (22)
B B
A <Core Design> A
Wistron Corporation
Title
Free Fall Sensor

A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = User.Interface
Vinafix.com
D D
IO BD CONN
IOBD1
HDMI BD CONN
102 101
+5V_ALW 2 1 +15V_ALW +5V_ALW +3.3V_RUN
4 3 HDMIB1
6 5 +3.3V_ALW NP1
8 7 1 30
10 9
12 11 2 29 HDMI_DATA2_R (17)
14 13 ESATA_USB_PW R_EN# (78) 3 28 HDMI_DATA2_R# (17)
16 15 +5V_RUN +5V_RUN 4 27
(27) BEEP 18 17 5 26 HDMI_DATA1_R (17)
(20) PCH_RXP_C_LAN_TXP7 20 19 6 25 HDMI_DATA1_R# (17)
(20) PCH_RXN_C_LAN_TXN7 22 21 AUD_NB_MUTE# (78) 7 24
24 23 8 23
LAN PCIE (20) LAN_RXP_C_PCH_TXP7 26 25
AUX_EN_W OW L (78)
HOST_DEBUG_TX (27)
(18) USB_OC#0
(51) HPD_HDMI_CON 9 22
HDMI_DATA0_R (17)
HDMI_DATA0_R# (17)
C 28 27 10 21 C
(20) LAN_RXN_C_PCH_TXN7 HOST_DEBUG_RX (27)
30 29 AUD_HP_NB_SENSE (78) (18) USB_PP0 11 20 HDMI_CLK_R (17)
(20) PCIE_RXN2 32 31 +3.3V_RUN (18) USB_PN0 12 19 HDMI_CLK_R# (17)
(20) PCIE_RXP2 34 33 MSCLK (27) 13 18
36 35 14 17
WLAN PCIE (20) PCIE_TXN2 38 37
MSDATA (27)
PLT_RST# (18,27,66,71,77,78) D8201
(78) USB_PW R_SHR_VBUS_EN
15 16
HDMI_CON_CLK (51)
HDMI_CON_DATA (51)
(27,78) USB_PW R_SHR_EN#
(20) PCIE_TXP2 40 39 W LAN_RADIO_DIS# (78) 1 SIO_SLP_LAN# (19,78) NP2
42 41 W LAN_LAN_DISB# (78)
44 43 AUX_ON 3 PSC-CONN30C-1-GP
(18) USB3_RX3_P
(18) USB3_RX3_N 46 45 BT_RADIO_DIS# (78) 20.F0922.030
1
48 47 LAN_DISABLE#_R (78) 2 AUX_ON_R (27)
(18) USB3_TX3_N 50 49 W IRELESS_LED# (66,68,78)
(18) USB3_TX3_P 52 51 AUD_DMIC_CLK (49,97) R8202 DY BAT54CPT-2-GP
54 53 10KR2J-3-GP 75.00054.K7D
USB 3.0 56 55
AUD_DMIC_IN0 (49,97)
2ND = 75.00054.A7D
2
(18) USB3_RX2_P PCIE_W AKE# (27,66)
(18) USB3_RX2_N 58 57 LANCLK_REQ# (20)
60 59 HDA_SPKR (21)
(18) USB3_TX2_N 62 61 HDA_CODEC_RST# (21)
(18) USB3_TX2_P 64 63 HDA_SDIN0 (21)
(20) LAN_SMBDATA 66 65 HDA_CODEC_SDOUT (21)
(20) LAN_SMBCLK 68 67 HDA_CODEC_SYNC (21)
(22) USB_MCARD1_DET# 70 69 HDA_CODEC_BITCLK (21)
72 71 PCH_SMBDATA (14,15,20,66,71,79)
74 73
WLAN PCIE CLK (20) CLK_PCIE_MINI2
(20) CLK_PCIE_MINI2# 76 75
PCH_SMBCLK (14,15,20,66,71,79)
MINI2CLK_REQ# (20)
78 77 USB_OC#1 (18)
(18) USB_PN2 80 79 USB_OC#0 (18)
(18) USB_PP2 82 81 CRT_DDC_DATA (17)
84 83 CRT_DDC_CLK (17)
B B
(18) USB_PN1 86 85 CRT_VSYNC_CON_1 (17)
(18) USB_PP1 88 87 CRT_HSYNC_CON_1 (17)
90 89
(18) USB_PN4 92 91
PCIE_MCARD1_DET# (22)
CRT_BLUE (17)
CRT Bus
(18) USB_PP4 94 93
96 95 CRT_RED (17)
98 97
LAN PCIE CLK (20) CLK_PCIE_LAN
(20) CLK_PCIE_LAN# 100 99 CRT_GREEN (17)
104 103
MLX-CONN100D-1-GP
20.F1355.100
GND 18 pins
Power 17 pins
<Core Design>
A A
Wistron Corporation
Title

IO Board Connector Rev
A3 Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3 Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3 Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
<Core Design>
A A
Wistron Corporation
Title
Reserved
A3 Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title

Reserved Rev
A3 Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title

Reserved Rev
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reverved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3 Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C
(Blanking) C
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
H4 H5
H2 H3 H6 H7 H8 H9 H10 H11
HOLE256R126-GP HOLE256R126-GP HOLE355X355R126-GP HT10X10BE10R32-L-5-GP HOLE197R166-1-GP HOLE256R126-GP HOLE197R166-1-GP HOLE197R166-1-GP HOLE256R126-GP HOLE197R166-1-GP
1
ZZ.00PAD.V71
Vinafix.com
D D
X01_1219
BOM need to stuff 34.49U23.001
34.4T025.001 34.4T025.001 34.4H602.001

H13 H14 SPR1 SPR2 SPR3 SPR4
H15
H12 HOLE355X355R126-GP HOLE355X355R126-GP HOLE237R95-GP H16 H17 H18 H19 H20 SPRING-52-GP SPRING-52-GP SPRING-64-GP SPRING-9-GP
HOLE256R126-GP HOLE HOLE HOLE HOLE HOLE
DY DY 34.49U23.001
1
1
1
1
1
H16,H17 GNDPADSR197_99-S
H18,H19,H20 GNDPADS79X119-NP
C C
RF Request
+1.35V_MEM +1.35V_MEM +1.35V_MEM +1.35V_MEM +1.35V_MEM +1.35V_MEM +1.05V_RUN_VTT +1.05V_RUN_VTT +1.05V_RUN_VTT +5V_RUN +5V_RUN +5V_RUN
EC9727
EC9734
EC9749
EC9750
EC9751
EC9752
EC9724
EC9725
EC9726
EC9730
EC9731
EC9732
1
1
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
DY DY
DY DY DY DY DY DY DY DY DY DY
2
EMI Request
EC9738
SCD1U16V2KX-3GP
AUD_DMIC_CLK AUD_DMIC_IN0 2 1 +1.35V_MEM +1.35V_MEM +1.35V_MEM +1.35V_MEM +1.05V_M +1.05V_M +1.05V_M +1.05V_M
+3.3V_RUN DY +5V_ALW
47R2J-2-GP
47R2J-2-GP
EC9753 EC9733
EC9754
EC9755
EC9756
EC9757
EC9758
EC9759
EC9760
1
1
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
2 1
B +3.3V_RUN DY +5V_RUN B
R9701
R9702
EC9740 SCD1U25V2KX-GP SCD1U16V2KX-3GP

DY DY DY DY DY DY DY DY DY DY
2
2
2 1
+5V_ALW DY +DC_IN
2
EC9741 SCD1U25V2KX-GP
2
+5V_ALW DY1 DCBATOUT
AUD_DMIC_CLK1
AUD_DMIC_IN01
+5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW
1
1
EC9719
SCD1U16V2KX-3GP
EC9720
SCD1U16V2KX-3GP
EC9766
EC9767
EC9768
EC9769
EC9770
EC9771
EC9772
EC9773
EC9774
EC9775
EC9776
EC9777
EC9778
EC9779
EC9780
EC9728
EC9729
1
1
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
DY DY
2
DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY
2
2
+3.3V_ALW +3.3V_ALW +3.3V_ALW +3.3V_ALW +3.3V_ALW +3.3V_ALW +3.3V_ALW +3.3V_ALW
EC9781
EC9782
EC9783
EC9784
EC9785
EC9786
EC9787
EC9735
1
1
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
DY DY DY DY DY DY DY DY
2
2
(49,82) AUD_DMIC_CLK <Core Design>
A (49,82) AUD_DMIC_IN0 A
(17,49) LVDS_DDC_DATA_R
(17,49) LVDS_DDC_CLK_R +1.05V_RUN_VTT +1.05V_RUN_VTT Wistron Corporation
EC9761
EC9762

1
1
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
Title
DY DY UNUSED PARTS/EMI Capacitors
2

A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Cheif River Platform Power Sequence

(AC mode) red word: KBC GPIO
(DC mode) red word: KBC GPIO
+RTC_VCC
+RTC_VCC T1 >9ms
T1 >9ms
RTC_RST#
RTC_RST#
DCBATOUT
T2
Vinafix.com DCBATOUT
3D3V_AUX_S5
T2
Within logic high level and disable if +3.3V_ALW2

D it is less than the logic low level. D
KBC GPIO34 control power on by 3V_5V_EN
3V_5V_EN Sense the power button status
Press Power button
KBC_PWRBTN# Platform to KBC PSL_IN2
+5V_ALW T3
V5REF_Sus must be powered up before EC_ENABLE#_1(GPIO31) keep low
VccSus3_3, or after VccSus3_3 within +3.3V_ALW T4 3D3V_AUX_KBC
0.7 V. Also, V5REF_Sus must power
down after VccSus3_3, or before
T3 KBC GPIO34 control power on by 3V_5V_EN
VccSus3_3 within 0.7 V.
PCH_ALW_ON S5_ENABLE
+3.3V_ALW_PCH T5 5V_S5 T4
KBC GPIO126 to PCH V5REF_Sus must be powered up before
+5V_ALW & +3.3V_ALW need meet 0.7V difference
VccSus3_3, or after VccSus3_3 within
PCH_RSMRST# T6 >?ms 0.7 V. Also, V5REF_Sus must power
3D3V_S5 T5
KBC GPIO151 to PCH down after VccSus3_3, or before
+5V_ALW & +3.3V_ALW need meet 0.7V difference
Not floating. VccSus3_3 within 0.7 V.
AC_PRESENT T7 >?ms +5VA_PCH_VCC5REFSUS T6
T7 >16ms KBC GPIO20 to PCH

PM_PWRBTN#
Sense the power button status
KBC GPIO43 to PCH

This signal has an internal PM_RSMRST# T8 >10ms
pull-up resistor and has an
internal 16 ms de-bounce on the PCH to KBC GPIO00
input.
PCH_SUSCLK_KBC T9 >5ms
Press Power button
RTC_AUX_S5
PWRBT1 to KBC VCI_IN0# and Thermal POWER_SW#
AC KBC_PWRBTN#
DC PCH_RSMRST#
T9 >?ms KBC GPIO152 to PCH T10
PCH to KBC GPIO44
AC SIO_PWRBTN#
PM_SLP_S4#
T11 PCH to KBC GPIO01
PCH to SIO GPIOI3 PM_SLP_S3# >30us
SIO_SLP_S4# KBC GPIO23 to LAN
T11 PCH to SIO GPIOI4 PM_LAN_ENABLE
SIO_SLP_S3# >30us
Enable by PM_SLP_S4#
KBC GPIO23 to LAN 1D5V_S3 T12
C
SIO_SLP_A# C
DDR_VREF_S3(0.75V) T13
+5V_RUN & +3.3V_RUN need meet 0.7V difference
5V_S0 T14
SIO_SLP_LAN# V5REF must be powered up before
Enable by SIO_SLP_S4# Vcc3_3, or after Vcc3_3 within 0.7 V.
3D3V_S0 T15
Also, V5REF must power down after
+1.35V_MEM T12 Vcc3_3, or before Vcc3_3 within 0.7 V.
Enable by 0.675V_DDR_VTT_ON +5VS_PCH_VCC5REF T16
+0.675V_DDR_VTT T13
+5V_RUN & +3.3V_RUN need meet 0.7V difference 1D5V_S0 T17
+5V_RUN T14
1D8V_S0 T18
V5REF must be powered up before +3.3V_RUN T15
Vcc3_3, or after Vcc3_3 within 0.7 V. 0D75V_S0 T19
Also, V5REF must power down after
Vcc3_3, or before Vcc3_3 within 0.7 V.
+5VS_PCH_VCC5REF T16 1D8V_S0 & 1D5V_S3 power ready
Enable by CPU1.5V_S3_GATE RUNPWROK T20
+1.35V_CPU_VDDQ T17
1D05V_VTT T21
+1.8V_RUN T18 VT357FCX PGOOD
1.05VTT_PWRGD T22
+1.5V_RUN T19
1D8V_S0 & 1D5V_S3 power ready 0D85V_S0 T23
RUNPWROK T20
0D85V_S0
1D05V_VTT T21 T24 TPS51461RGER PGOOD
VT357FCX PGOOD D85V_PWRGD
1.05VTT_PWRGD T22
SetVID ACK
CPU SVID BUS 50us< T25 <2000us
0D85V_S0 T23
VCC_CORE
0D85V_S0
T24 TPS51461RGER PGOOD VCC_GFXCORE
1.05V_0.8V_PWROK T26
<5ms
ISL95831 PGOOD to system
SetVID ACK
CPU SVID BUS 50us< T25 <2000us IMVP_PWRGD
VCC_CORE
CLK_EXP_P
B
VCC_GFXCORE B
ALL_SYS_PWRGD=D85V_PWRGD
T26 This signal represents the Power T27 >99ms KBC GPIO77 to PCH
<5ms
ISL95831 PGOOD to system Good for all the non-CORE and PWROK
non-graphics power rails.
IMVP_PWRGD T28 >0us
D85V_PWRGD
2ms< T29 <650ms PCH to CPU
VDDPWRGOOD
CLK_EXP_P
T30 >1ms
ALL_SYS_PWRGD=D85V_PWRGD
This signal represents the Power T27 >99ms KBC GPIO77 to PCH T31 >2ms
Good for all the non-CORE and
1D8V_S0
non-graphics power rails.
PWROK 5ms< T32 <650ms PCH to CPU
T28 >0us
D85V_PWRGD H_CPUPWRGD
2ms< T29 <650ms PCH to CPU
VDDPWRGOOD SYS_PWROK T33 >0ms
T34 >1ms+60us
T30 >1ms
1ms< T35 <100ms PCH to all system
T31 >2ms
1D8V_S0 PLT_RST#
5ms< T32 <650ms PCH to CPU T36 <200us
H_CPUPWRGD DMI
SYS_PWROK T33 >0ms

T34 >1ms+60us
1ms< T35 <100ms PCH to all system
PLT_RST#
T36 <200us
DMI
A A
<Core Design>
Wistron Corporation
Title
Power Sequence
A1
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Wistron HURON RIVER POWER UP SEQUENCE DIAGRAM

5V_S5 DCBATOUT
-6
AC
Adapter in
AD+ Vinafix.com
-3.1 -3.1 -3.1
Page38 VDDP VIN
D 1D5V_S3 D
PWR_5V3D3V_ENC 3V_5V_EN S5_ENABLE VOUT
3
PM_SLP_S4#
EN
-3.2 -3.3 DDR_VREF_S3
PWR_CHG_ACOK REF
SWITCH ENC 5V_S5 15V_S5
LL1 PUMP
Page40
3D3V_S5 TPS51116RGER
LL2
0D75V_S0
5V_AUX_S5 VTT
RT8223MGQW VREG5
DC/DC 3D3V_AUX_S5 -5
-6.1 (3V/5V) VREG3 3 RUNPWROK
PGD
DCBATOUT 3V_5V_POK PM_SLP_S4#
VIN PGOOD -2 Page46
5
Page41
4 5V_S5 3D3V_S5
DC BQ24745 5V_S0
BT+ PM_SLP_S3#
Battery Charger SWITCH
Page39 -3 BJT
Page37
3D3V_AUX_KBC VDD VIN 1D8V_S0
-3.1 4 VOUT
Page40 ACOK 3D3V_S0
S5_ENABLE SWITCH
-4 Page37 PM_SLP_S3# TPS53311RGTR
EN
RUNPWROK
AC_IN# GPIO34 PGD
C GPIO70 1D5V_S0 C
Page47
SWITCH
Page37 5
1 SLP_S4# SLP_S3#
-1 KBC
KBC_PWRBTN#
GPIO6 NPCE795P -2.1
11 AND GATE
Power Button PM_RSMRST# 0D75V_EN
PM_SLP_S4# GPIO43 RSMRST# B VDDPWRGOOD
GPIO44 PM_PWRBTN# PM_DRAM_PWRGD Y SM_DRAMPWROK
PM_SLP_S3# GPIO20 PWRBTN# DRAMPWRGD A
GPIO01
2 H_CPUPWRGD H_CPUPWRGD_R
PROCPWRGD UNCOREPWRGOOD
Page27 Cougar Point 12
GPIO77 PCH Sandy Bridge
13 CPU
S0_PWR_GOOD
APWROK
PWROK PLT_RST# BUF_CPU_RST#
PLTRST# RSTIN#
SYS_PWROK SVID
SYS_PWROK
SVID
10
8
5V_S5 DCBATOUT
B B
V5IN VIN 1D05_VTT
VOUT
5 AND GATE 10
S0_PWR_GOOD
RUNPWROK TPS51218DSCR A SYS_PWROK
EN 1.05VTT_PWRGD IMVP_PWRGD Y
Page45 PGOOD B
5V_S5 DCBATOUT 5a
VDDP VIN 0D85_S0 -5

VOUT
5a -7 3D3V_AUX_S5
1.05VTT_PWRGD RT8208BGQW RTC_AUX_S5
EN D85V_PWRGD
Page48 PGOOD -8
+RTC_VCC
6
DCBATOUT RTC battery
8 VIN VCC_CORE
OUTPUT
A
SVID A
SVID VCC_GFXCORE
VR OUTPUT
6 7 ISL95831HRTZ
<Core Design>
D85V_PWRGD IMVP_VR_ON 9
VR_ON IMVP_PWRGD
Page42 & 43 & 44 PGOOD Wistron Corporation
Title
Power Up Sequence: -8 ~ 13 Size

Power Up Sequence Diagram
Document Number Rev
A2
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
DCBATOUT +PWR_SRC
OUT1 +5V_ALW OUT DCBATOUT_LCD
OUT2 +3.3V_ALW PA102FMG
OUT3 EN_INVPWR EN
TPS51225 +5V_ALW2 +3.3V_ALW
OUT4 +3.3V_ALW_PCH
+3.3V_ALW2
Vinafix.com
+1.35V_MEM
OUT
OUT5 +15V_ALW
Thermal OUT AO6402
D
3V_5V_EN EN PG PWR_5V3D3V_PGOOD +1.35V_CPU_VDDQ D
TPCA8062 EN
EMC4021 PURE_HW_SHUTDOWN# ‧ CPU1.35V_S3_GATE ‧ EN
+3.3V_ALW SIO_SLP_S3#
EN_INVPWR DY
SIO_SLP_A# +5V_ALW
DY OUT PCH_ALW_ON‧ ‧
+1.05V_RUN ALWON CPU1.35V_S3_GATE +5V_ALW_PCH
RUN_ON
DY ‧ RT8085 KBC SIO_SLP_S5# OUT
SIO_SLP_S3# ‧ EN PG 1.05V_A_PWRGD PCH_ALW_ON DY
2N7002
MEC5055
DDR_ON ACAV_IN EN
+5V_ALW AUX_ON
OUT1 +1.35V_MEM
OUT2
AD+ SW
+0.675V_DDR_VTT
AO4407
OUT3 DCBATOUT
DDR_ON +VDDR_REF
DY SW
RT8207
SIO_SLP_S4# ‧ S5 SW ‧ AO4407
AO4407 +DC_IN
S3 PG 1.35V_SUS_PWRGD
C C
CHARGER
‧ SIO_SLP_S4# SIO_SLP_LAN# DC
AC
ISL88731 Battery
ACAV_IN
ACOK +VCHGR Adapter In
‧ SIO_SLP_A# SIO_SLP_S5# ‧
PCH +3.3V_ALW
‧ ‧ SIO_SLP_S3# ENVDD_PCH
OUT +3.3V_LAN
AO6402
AUX_ON EN +3.3V_ALW
+1.5V_RUN
+3.3V_RUN OUT
‧ RUN_ON
APL5930
OUT +LCDVDD
+3.3V_ALW EN
‧ ENVDD_PCH AO6402
OUT +1.8V_RUN
RUN_ON EN
DY RT8068 LCD_VCC_TEST_EN +5V_ALW
‧ SIO_SLP_S3# ‧ EN PG 1.8V_RUN_PWRGD +5V_RUN
‧ SIO_SLP_S3# ‧ BAT54CPT
OUT
SI4178
B B
+5V_ALW ‧ RUN_ON RUN_ON DY ‧ EN
+1.05V_RUN_VTT
OUT SIO_SLP_S3# ‧
CPU_VTT_ON
VT386FCX ‧ SIO_SLP_S4# +3.3V_ALW +3.3V_ALW
SIO_SLP_S3# 1.05V_VTTPWRGD +3.3V_RUN
DY ‧ EN PG
OUT +3.3V_SUS OUT
SIO_SLP_S5# AO6402
SIO_SLP_S3#
1.05V_VTTPWRGD SI4178
SIO_SLP_LAN# ‧ EN
SIO_SLP_A# EN
DY
ENVDD_PCH
SIO_SLP_S4# +5V_ALW
‧ B AND-GATE LCD_VCC_TEST_EN +3.3V_RUN
OUT 1.05V_0.8V_PWROK 0.675V_DDR_VTT_ON SIO OUT +5V_USB_PWR_1 +CAMERA_VDD
A U74LVCIG08G RUN_ON
SUS_ON TPS2000
OUT
USB_PWR_SHR_EN# EN
1.8V_RUN_PWRGD ECE5048 DMP2130
VCCSAPWROK CCD_OFF EN
CPU_VTT_ON
+5V_ALW ESATA_USB_PWR_EN#
OUT IMVP_VR_ON +5V_ALW
+VCC_SA
AUX_EN_WOWL
SY8037 IMVP_PWRGD
MCARD_WWAN_PWREN OUT1 +5V_USB_PWR_2
EN PG VCCSAPWROK
A TPS2560 OUT2 +5V_USB_PWR_3 A
MCARD_WWAN_PWREN EN
+5V_ALW +3.3V_ALW <Core Design>
+3.3V_ALW +3.3V_WLAN
VT1318 OUT1 +VCC_CORE Wistron Corporation
+3.3V_PCIE_WWAN OUT 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
VT1323 OUT2 +VCC_GFXCORE OUT Taipei Hsien 221, Taiwan, R.O.C.
IMVP_VR_ON AO6402
DY AO6402 Title
VT1323 EN Power Block Diagram
1.05V_0.8V_PWROK ‧ EN PG IMVP_PWRGD MCARD_WWAN_PWREN EN Size Document Number Rev
A2
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
SMBus Block Diagram

+3.3V_ALW_PCH +3.3V_RUN
Vinafix.com +3.3V_RUN
SRN2K2J-1-GP
D
SRN2K2J-1-GP ‧ D
DIMM 1
SMBCLK MEM_SMBCLK
‧ ‧ DDR_XDP_WAN_FFS_SMBCLK
‧ SCL
SMBDATA MEM_SMBDATA
‧ ‧ DDR_XDP_WAN_FFS_SMBDATA
‧ SDA
+3.3V_ALW_PCH 2N7002KDW +3.3V_LAN
DIMM 2
PCH SRN2K2J-1-GP
+3.3V_ALW_PCH +3.3V_LAN
SRN2K2J-2-GP ‧
‧
SCL
SDA
‧ ‧
SCL
‧ ‧ LAN_SMBCLK LAN
‧ ‧ LAN_SMBDATA
SDA Minicard
SML0CLK SML0_CLK
SML0DATA SML0_DATA
‧
WWAN
SMB_CLK
C C
SML1DATA SML1CLK +3.3V_ALW_PCH 2N7002KDW 2N7002KDW
‧ SMB_DATA
SML1_DATA SML1_CLK
SRN2K2J-1-GP XDP
‧ SMB_CLK
‧ ‧ ‧
DY ‧ SMB_DATA
‧ ‧ ‧
0R2J-2-GP
Free Fall
GPIO144/I2C1E_CLK SIO_LAN_SMBCLK
‧
GPIO143/I2C1E_DATA SIO_LAN_SMBDAT
‧ +3.3V_ALW sensor
‧ SMB_CLK
SRN2K2J-2-GP
‧ SMB_DATA
B
+3.3V_ALW B
+3.3V_ALW
GPIO004/I2C1A_CLK DOCK_SMBCLK
GPIO003/I2C1A_DATA DOCK_SMDATA
SRN2K2J-2-GP 0R2J-2-GP DY
SRN2K2J-2-GP
+3.3V_ALW
GPIO006/I2C1B_CLK LCD_SMBCLK
GPIO005/I2C1B_DATA LCD_SMDATA Minicard
SRN2K2J-2-GP
GPIO154/I2C1C_DATA/PS2_CLK1B PBAT_SMBCLK
‧ WLAN_SMBCLK WLAN
GPIO155/I2C1C_CLK/PS2_DAT1B PBAT_SMBDAT
‧
CLK_SMB
DAT_SMB
BAT CONN WLAN_SMBDATA
SMB_CLK
SMB_DATA
SRN33J-7-GP
KBC +3.3V_ALW
+3.3V_ALW
GPIO142/I2C1F_CLK/I2C2B_CLK CARD_SMBCLK
GPIO141/I2C1F_DATA/I2C2B_DATA CARD_SMBDAT SRN2K2J-2-GP
SRN2K2J-2-GP
A <Core Design> A
GPIO131/I2C2A_CLK CHARGER_SMBCLK
‧ SCL
Charger
GPIO132/I2C1G_DATA CHARGER_SMBDAT
‧ SDA Wistron Corporation
SRN33J-7-GP Taipei Hsien 221, Taiwan, R.O.C.
+3.3V_ALW
GPIO013/I2C1H_CLK/I2C2D_CLK BAY_SMBCLK Title
GPIO012/I2C1H_DATA/I2C2D_DATA BAY_SMBDAT
Power Block Diagram Rev
SRN2K2J-2-GP
A3
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Thermal Block Diagram

REM_DIODE1_N_4021
DN1/THERM ‧
Vinafix.com
UMA DP1/VREF_T ‧
SC2200P50V2KX-2GP
‧
MMBT3904-7-F-1-GP Audio Block Diagram
REM_DIODE1_P_4021
D Place under CPU D
+3.3V_ALW
Thermal
KBC EMC4021 REM_DIODE1_N_4021
DN2/DP4 ‧ ‧ ‧ RIGHT-/RIGHT+ AUD_SPK_R
MEC5055 100KR2J-1-GP SC2200P50V2KX-2GP MMBT3904-7-F-1-GP SC2200P50V2KX-2GP MMBT3904-7-F-1-GP

LEFT-/LEFT+ AUD_SPK_L SPEAKER
BC_INT#_EMC4021 DP2/DN4 ‧ ‧ ‧
GPIO024 ‧ BC_CLK_EMC4021
ATF_INT#/BC_IRQ# REM_DIODE1_P_4021
GPIO023 SMCLK/BC_CLK Place near VCORE VR Place near SODIMM
BC_DAT_EMC4021
GPIO022 ‧ ACAV_IN
SMDATA/BC_DATA
VCI_OVRD_IN
POWER_SW_IN#
‧ 0R2J-2-GP POWER_SW_IN#_L
ACAVAIL_CLR
+1.05V_RUN_VTT
VCI_IN0# ‧ FAN1_DET#
POWER_SW# +3.3V_SUS
MIC2_L/RING2 RING2
GPIO3/PWM/THERMTRIP_SIO
PAGE27 FAN1_TACH_FB MIC2_R/SLEEVE SLEEVE
TACH/GPIO1
8K2R2J-3-GP 2K2R2J-2-GP
CPU
MMBT3904 THERM_B1 Ivy Bridge
KBC_PWRBTN# THERMTRIP2#
THERMTRIP2#
‧ C
B
E
H_THERMTRIP#
Combo
THERMTRIP#
0R2J-2-GP PAGE5
HP_OUT_L AUD_HP1_JACK_L
Jack
PURE_HW_SHUTDOWN#
CHARGER SYS_SHDN# AUD_HP1_JACK_R
HP_OUT_R
PAGE28
ISL88731 TPS51225
PAGE40
5V/3D3V
C C
EN PAGE41
+3.3V_ALW 0R2J-2-GP
SIO Codec
ECE5048 10KR2J-3-GP ALC3223
SIO_FAN1_DET# 0R2J-2-GP FAN1_DET#
GPIOE6 ‧ DY ‧
PAGE78
+3.3V_SUS
+FAN1_VOUT 10KR2J-3-GP
‧
DET#
‧
TACH
FAN
PAGE27
B B
A A
<Core Design>
Wistron Corporation
Title

Power Block Diagram Rev
A2
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
ADAPTER
EN_INVPWR
PA102FMG DCBATOUT_LCD
Vinafix.com
D DCBATOUT D
BATTERY
3V_5V_EN
CHARGER
TPS51225
+3.3V_ALW2 +5V_ALW2 +15V_ALW

+5V_ALW
1.05V_0.8V_PWROK
SIO_SLP_S3#
SIO_SLP_S5#
0.675V_DDR_VTT_ON
+3.3V_ALW
C C
CPU_VTT_ON
PCH_ALW_ON
1.05V_VTTPWRGD
MCARD_WWAN_PWREN
SIO_SLP_S3#
SIO_SLP_S3#
SIO_SLP_S4#
SIO_SLP_S3#
IMVP_VR_ON
SIO_SLP_A#
ESATA_USB_PWR_EN#
SIO_SLP_S4#
SIO_SLP_S3#
AUX_EN_WOWL
SIO_SLP_S3#
RUN_ON
RUN_ON
USB_PWR_SHR_EN#
SUS_ON
RUN_ON
DDR_ON
RUN_ON
SIO_SLP_A#
PCH_ALW_ON
SIO_SLP_S5#
VT386FCX 2N7002
AUX_ON
AO6402
S5 S3
SY8037 RT8068 APL5930 RT8085
VT1318
AO4468 AO6402
VT1323 AO4468 AO6402
RT8207
VT1323
TPS2000 TPS2560 +1.05V_RUN_VTT +5V_ALW_PCH +1.8V_RUN +1.5V_RUN +1.05V_RUN AO6402 SI3456
AO6402
+VCC_SA +3.3V_WLAN
+3.3V_SUS
+5V_RUN
+3.3V_PCIE_WWAN
+VCC_GFXCORE +VCC_CORE +3.3V_LAN +3.3V_M +3.3V_RUN
+3.3V_ALW_PCH
+5V_USB_PWR_1
B B
LCD_VCC_TEST_EN
+VDDR_REF +1.35V_MEM +0.675V_DDR_VTT
ENVDD_PCH
ENVDD_PCH
+5V_USB_PWR_2 +5V_USB_PWR_3
CPU1.35V_S3_GATE
SIO_SLP_S3#
BAT54CPT DMP2130
AO6402 +CAMERA_VDD
TPCA8062
+LCDVDD
+1.35V_CPU_VDDQ
A A
<Core Design>
Wistron Corporation
Title

Power Rail Diagram Rev
A2
Austin 13 A00
5 4 3 2 1
5 4 3 2 1
Version Date Page Function Change Item
X01 1126 45 Power PR4515 84K5R2F-GP change to 76K8R2F-GP(64.76825.6DL)

V change to 1.0608V
X01 1122 68 EE Change Q6806 from 84.2N702.J31 to 84.2N702.A3F. And Delete D6804 by LED leackage
X01 1122 38 EE
Vinafix.com
Change PL3802 from 68.00084.771 to 68.00115.081.
Add PL3803 becuz each 3A only.
D Sourcer : EOL concern, pls downsize to 3216 D
X01 1122 38 EMC Change D3901,D3902,D3903 from 83.02025.0AF to 83.52301.0AF.
X01 1122 97 ME Change SPR4 from 34.17S03.001 to 34.49U23.001.

此此此此此此此此09年
34.17S03.001此年年年年34.49U23.001（（兩兩此兩兩兩兩兩此兩兩兩兩兩兩兩）
X01 1126 66 EE Re-connect SIM1 for correction.Delete R6605
X01 1129 66,68 EE Delete R6603 imnstead of Q6602 for leackage
Delete R6811 imnstead of Q6811 for leackage
X01 1129 49 EE Change U4901.1 form +3.3V_RUN to +3.3V_ALW by Leackage
C C
X01 1129 66 EE Stuff R6612,U6605 for Discharge
X01 1201 37 EE change U3711 form 74.00863.07B to 74.09818.NBB
X01 1203 68 EE Add Q6812,R6811
X01 1205 68 EE Change D6602 from 83.00005.BAE to 83.04220.0AE

OBS REASON:For contract issue,replaced by 75.00005.07C Too expensive, pls change to 83.04220.0AE
X01 1211 41 Power Change PR4115 form 64.15025.6DL to 64.15425.6DL for rise 5V to meet EA measurment
X01 1212 40 Power Change PR4035 form 64.21535.55L to 64.22635.55L for remove ADP shutdown issue
X01 1212 38 Power Change PC3805 to PR3812 form 78.10324.2FL to 64.10035.6DL for remove ADP shutdown issue
B B
X01 1219 68 ME Change PWRBT1 form 62.40076.001 to 62.40009.D71
X01 1219 97 ME Change SPR4 form 34.17S03.001 to 34.49U23.001
X01 1219 66 ME Change SIM1 form 62.10034.591 to 62.10034.641
X01 1219 66 EE Change D6602 form 83.04220.0AE to 75.04220.07C (OBS REASON)
X01 1219 27 EE Change C2723 and C2724 form 78.22034.1FL to 78.39034.1FL (Base on vendor recommend and Korbel also use 39pF)
X01 1219 27 EE Change R2735 form 64.13035.6DL to 64.62025.6DL for upgrade PCB version
X01 1219 68 EE Add AFTP6801
X01 1224 40 Power Del pg4006 pg4002 pg4008 pg4009 for pu4005 modify high limit
X01 1225 74 EMI Add R7401

<Core Design>
A X01 1228 21 EE Change R2116,R2121,R2127,R2128,R2136 from 63.R0034.1DL to 63.22034.1DL for enhance LPC waveform A
X01 0102 49 EMC Add EC4901~EC4908 and stuff 78.4R774.1FL Wistron Corporation
X01 0102 47 Power Add PU4702 2nd =74.07175.031 Title
Change History
X01 0104 49 EE Add R4901,R4902,R4904 prepare for 0603 fuse. Size Document Number Rev
A3
Austin 13 A00
X01 0104 46,41 Power PU4603, PU4106 84.07696.037 change to 84.08878.A30 Date: Tuesday, February 26, 2013 Sheet 104 of 106
5 4 3 2 1
5 4 3 2 1
Version Date Page Function Change Item
X01 0109 27 EE Dummy R2733 to prevent S5 leackage
X01 0109 68 EE Change R6801 R6802 R6804 R6805 R6806 R6808 from 1.2K (63.12234.1DL) to 330R (63.33134.1DL) for Brightness Tunning
X01 0109 32 EE Vinafix.com

Change R3212 from 33R(63.33034.1DL) to 10R(64.10R05.6DL) follow Korbel
D D
X01 0117 66 EE Change R6612 from 100R(63.10134.1DL) to 1K(63.10234.1DL) prevent De-rating issue.
A00 0206 5 EE Change Q511 from 84.00138.03K to 84.2N702.J31
0ohm change to pad.

Charger :PR4030, PR4009, PR4036,PR4027,
5/3.3v : PR4127, PR4130, PR4116
A00 0218 Power CPU :PR4251, PR4250
1.05V_VTT : PR4510 , PR4508,
1.05V_M: PR4516, PR4518
1.35V : PR4610, PR4609, PR4608, PR4611
1.8V : PR4722
VCCSA : PR4825, PR4829, PR4810
C C
A00 0220 71 EE Change XDP1 form 20.F0971.060 to ZZ.00PAD.Q81

Change DB1 from 20.D0183.110 to ZZ.00PAD.Y41
A00 0220 27 EE Change R2735 to 64.33025.6DL for XB
A00 0220 EE Change to 0 ohm pad.

R1928, R1934, R1936, R2309, R2705, R2701, R2831, R3610, R3655, PR4622, R3652, R3649, PR4730
R4921, R4922, R4923, R4924, R4919, R4920, R4925, R4926, R6609,
A00 0220 40 EE Add PC4040,PC4041
A00 0226 49 EE Delete R4903,R4908
B B
A00 0226 78 EE Chnage R7826,R7841 to SHORT PAD
<Core Design>
A A
Wistron Corporation
Title
Change History
A3
Austin 13 A00
5 4 3 2 1
5
AUSTIN CLK Block Diagram 4 3 2 1
CPU PCH
Ivy Bridge Panther Point
Vinafix.com
M_A_DIMA_CLK_DDR0
CK0 SA_CK0
M_A_DIMA_CLK_DDR#0
CK0# SA_CLK#0
D DDR3 DIMM1 D
M_A_DIMA_CLK_DDR1 CLK_EXP_P
CK1 SA_CK1 BCLK CLKOUT_DMI_P
M_A_DIMA_CLK_DDR#1 CLK_EXP_N
CK1# SA_CLK#1 BCLK# CLKOUT_DMI_N
CLK_PCIE_MINI2#
CLKOUT_PCIE5N PIN 11
M_B_DIMB_CLK_DDR0
WLAN
CK0 SB_CK0 CLK_PCIE_MINI2
CLKOUT_PCIE5P PIN 13
M_B_DIMB_CLK_DDR#0
CK0# SB_CLK#0
DDR3 DIMM2
M_B_DIMB_CLK_DDR1
CK1 SB_CK1
M_B_DIMB_CLK_DDR#1
CK1# SB_CLK#1
CLK_PCIE_LAN#
CLKOUT_PCIE1N PIN 44
LAN CHIP
CLK_PCIE_MMI CLK_PCIE_LAN
CardReader PE_REFCLKP CLKOUT_PCIE1P PIN 45
O2 CLK_PCIE_MMI#
PE_REFCLKM
OZ600FJ0 Intel WG82579LM
C XTALI
C
XTAL_IN
TPM X501
25MHz
AT97SC3204 LCLK CLK_PCIE_MMI#R2018 PCI_TPM_TCM
CLKOUTFLEX2/GPIO66
XTALO
33R2J-2-GP XTAL_OUT
R1806 CLK_PCI_LOOPBACK_R
CLKOUT_PCI4
22R2J-2-GP
AUDIO
CLK_PCI_LOOPBACK CLKIN_PCILOOPBACK
HDA_BITCLK R2126 HDA_CODEC_BITCLK
92HD93
HDA_BCLK BITCLK
33R2J-2-GP
RTC_X1
RTCX1
B MEC_XTAL1 B
X2101
CLKOUT_PCI1 PCI_MEC R1805 CLK_PCI_MEC
PCI_CLK
KBC SMSC XTAL1
22R2J-2-GP
32.768KHz
MEC5055 X2701
32MHz
RTC_X2 EC_32KHZ_ECE5048_R GPIO160/32KHZ_OUT
RTCX2
XTAL2 MEC_XTAL2
XTAL25_IN
XTAL25_IN
R1817 EC_32KHZ_ECE5048
22R2J-2-GP
CLK32K/GPIOM2SUPER IO
X2001
25MHz CLKOUTFLEX1/GPIO65 SIO_14M R2016 CLK_SIO_14M ECE5048
14_318MHZ/GPIOM0
22R2J-2-GP
XTAL25_OUT CLKOUT_PCI0 PCI_5048 R1817 CLK_PCI_5048
XTAL25_OUT PCICLK
22R2J-2-GP
A A
<Core Design>
Wistron Corporation
Title

CLK Diagram Rev
A2
Austin 13 A00
5 4 3 2 1

Latitude 3330 12275-1 - AUSTIN13 - CHIEFRIVER - MB - A00 - 0226

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Latitude 3330 12275-1 - AUSTIN13 - CHIEFRIVER - MB - A00 - 0226

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5 4 3 2 1

Austin 13" Schematics Document

Austin 13 Block Diagram Project Code: 91.4LA01.001 INPUTS

Vinafix.com Intel CPU

BGA1023 GFX DC/DC

FDIx4x2 DMIx4 SYSTEM DC/DC

BGA989 PCIE x 1 USB2.0 x 1

INT 2 SATA GenIII x 1

SPI BUS HDA

Name Schematics Notes Pin Name Configuration Schematic Notes

CFG[2] PCI-Express Static 1: Normal Operation.

USB Table PCIE Table SATA Table

PCI EXPRESS -- GRAPHICS

JTAG & BPM

(22,71) H_CPUPW RGD 1 2 H_CPUPW RGD_R B46 UNCOREPWRGOOD

R518 3rd = 73.7SH09.0AG

75R2J-1-GP Open Drain Buffer

Open Drain Buffer (36) RUN_ON_CPU1.5VS3#

DDR SYSTEM MEMORY B

M_A_DQ38 AT48 AK55 M_A_DQS#7 M_B_DQ39 BE53

TPAD14-OP-GP TP715 1 VCC_VAL_SENSE H43

PEG IO AND DDR IO

VCCPLL Output Decoupling Recommendation: BC43 TP_VDDQ_SENSE 1 TP901 TPAD14-OP-GP

BA43 TP_VDDQ_VSS 1 TP902 TPAD14-OP-GP

A13 AM38 BG17 M4

AE8 VSS36 VSS126 AU1 F19 VSS216 VSS285 T55

NCTF TEST PIN：

From CPU BG7 +DIMM0_1_CA_CPU S D +V_DDR_REFB_M3

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

DDRM1 & M3 solution

M_A_DQS#7 DQS6# VSS

M_A_DQS2 DQS1 VSS

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

SSID = MEMORY DM2

VTT2. M_B_DQ53 DQ52 VSS

M_B_DQ56 DQ55 VSS

VREFDQ multiple methods M3

SRN2K2J-1-GP (49) L_BKLT_CTRL P45 L_BKLTCTL SDVO_STALLN AM42

Digital Display Interface

AH49 LVDSB_DATA1 DDPC_2N BA47

(82) CRT_BLUE N48 CRT_BLUE DDPD_CTRLCLK M43

T42 CRT_IRTN DDPD_3N BJ42

BJ16 TP4 RSVD5 AT10

B SRN8K2J-2-GP-U Taipei Hsien 221, Taiwan, R.O.C.

A18 DSW ODVREN

System Power Management

+3.3V_RUN R1905 1 2 1KR2J-1-GP

(71,78) SYS_PW ROK 1 2 SYS_PW ROK_R P12 N3 CLKRUN# CLKRUN# (27,77,78)

(27) ME_SUS_PW R_ACK 1 2 ME_SUS_PW R_ACK_R K16 F4 SIO_SLP_S3# SIO_SLP_S3# (36,45,47,78)

(27) AC_PRESENT AC_PRESENT H20 G16 SIO_SLP_SUS# SIO_SLP_SUS# (78)

PM_RI# A10 K14 SIO_SLP_LAN# SIO_SLP_LAN# (78,82)

PCH (DM I/FDI/PM)

10KR2J-3-GP 2 1 R2011 MINI2CLK_REQ#

(32) PCH_RXN_C_MMI_TXN6 BJ38

PCIECLKRQ4#/GPIO26 CLKIN_SATA_P SRN10KJ-5-GP

SSID = PCH Layout Note:

(82) HDA_SPKR T10 SPKR SATA1RXN AM10 SATA_RXN1 (66)

R2123 Layout Note: HDA_RST# K34 HDA_RST#