VISION 2K11

A Paper Presentation

On

“TRIGATE TRANSISTORS”

Presented by

Ms. Patil Amruta S. Ms. Rajput Trupti R.

T.Y(B.Tech) Electronics T.Y(B.Tech) Electronics

WALCHAND COLLEGE OF ENGINEERING, SANGLI.

 ABSTRACT

The Moore’s law has been saturated but we expect to continue driving the leading edge
of Moore’s prediction well into the foreseeable future with the Tri-gate Transistors. They are
likely to play a critical role in energy efficient performance capabilities because they offer
considerably lower leakage and consume much less power than today's planar transistors.It’s the
way to reach the processors’ clock-speeds up to 20 to 50 GHz. It is one of the major
breakthroughs in the VLSI technology.
Index:

1. Introduction

2. Tri-gate transistor

3. Structure

4. Fabrication

5. V-I Characteristics

6. Enhancement In Design

7. Features

9. Future

10. Conclusion
  Introduction:

Our brain contains around 100 billion cells called neurons—the tiny switches that let you
think and remember things. Computers contain billions of miniature brain cells as well. They're
called transistor. These are the microscopic, silicon-based switches that process the ones and
zeros of the digital worlds and are the fundamental building block of all semiconductor chips.
With traditional planar transistors, electronic signals travel as if on a flat, one-way road. The
observation made in 1965 by Gordon Moore, co-founder of Intel, that the number of transistors
per square inch on integrated circuits had doubled every year since the integrated circuit was
invented. Moore predicted that this trend would continue for the foreseeable future. In
subsequent years, the pace slowed down a bit, but data density has doubled approximately every
18 months, and this is the current definition of Moore's Law.
The scaling of planar transistors requires the scaling of gate oxides and source-drain
junctions. However, as these transistor elements become harder to scale, so does the transistor
gate length. The scaling of planar transistors is getting more difficult due to the worsening
electrostatics and short-channel performance with reducing gate-length dimension. Both
transistor off-state leakage (which increases with reducing gate length dimension) and gate oxide
leakage (which increases with decreasing gate dielectric thickness) are contributing to the
increase in power dissipation with scaling. Engineers have recently predicted that trend would
soon end, because electricity tends to leak out of tiny wires as chip geometry shrinks below 90
nanometers. But this is not the fact, we have some of solutions in our hand.

One solution is to build chips with multiple cores that run at slower speeds, since chips
leak more electricity and run less efficiently as they run faster than 2 GHz. Another solution
could be carbon nano-tubes, But the problem with carbon nano-tubes is that no one knows how
to put them in a particular spot except by moving them one at a time. Even our smallest chips
have millions of transistors, so that is an insurmountable challenge. Therefore Tri-gate
Transistor solution is the best and as compared to carbon nano-tubes, it is far easier to build.
  Tri-gate transistor:

A tri-gate transistor is a component in the standard CMOS (complementary metal oxide

semiconductor) design, but acts as a better "traffic cop" to control the flow of electrons,
surrounding each wire on three sides instead of just one. It's better to wrap the gate around, just
like it's easier to block a garden hose by squeezing on all sides than just holding your thumb on
one side. Tri-gate transistors are likely to play a critical role in energy efficient performance
capabilities because they offer considerably lower leakage and consume much less power than
today's planar transistors. Compared to today's 65nm transistors, integrated tri-gate transistors
can offer a 45 percent increase in drive current (switching speed) or 50 times reduction in off-
current, and 35 percent reduction in transistor switching power. Increased performance and
reduced energy consumption improve the experience for users of PCs and other devices.

 Structure of tri-gate transistor:

Tri-gate transistor employs a novel 3-D structure, like a raised, flat plateau with vertical
sides, which allows electronic signals to be sent along the top of the transistor and along both
vertical sidewalls as well. The tall picket-fence-like structures running from left to right are the
transistor gates. The smaller structures that intersect them are called sources and drains. Usually,
the gates, sources and drains exist on a flat plane. The top-gate transistor has physical gate length
LG and physical gate width WSi, while the side-gate transistor has physical gate length L G and
physical gate width His. This effectively triples the area available for electrical signals to travel,
like turning a one-lane road into a three-lane highway, but without taking up more space. They
operate more efficiently at nanometer-sized geometries. The 3-D structure apparently reduces the
distance that electrons travel, generates less heat and costs less to produce than existing chip.
These results give us high confidence that we can continue Moore's Law scaling well into the
next decade.
  Tri gate transistor fabrication:

The design is radically different from existing transistors. This tri gate transistor, which
can be fabricated either on the SOI(silicon on insulator) substrate in which an insulation barrier
is placed between the CMOS gate and the base substrate, the CMOS circuit can perform faster
switching due to decreased capacitance. Capacitance is the tendency for a circuit to store an
electrical charge. Impurities embedded within the silicon substrate lead to increased capacitance,
thus slowing the overall response time of the transistor due to having to discharge the circuit
before the nest switching operation can be performed. The insulator provides a boundary layer,
thus limiting capacitance transfer to the substrate material.A reduction in capacitance also allows
for the gateway path to operation with less voltage, thus increasing power consumption
efficiency. Another technique used is standard bulk-silicon substrate, has a gate electrode on the
top and two gate electrodes on the sides of the silicon body.

Tri-Gate CMOS transistors have been fabricated, as well as simulated down to Lg=30nm to
explore the fabrication and design space at these dimensions.To get body widths of the same
approximate size as the polysilicon gate, the body was first fabricated by treating it in a similar
manner to polysilicon, using aggressive poly-silicon lithography and etch techniques to get body
thicknesses equal to gate lengths. The body was then doped to obtain acceptable threshold
voltages (Vt) using conventional boron implants. No halo implants were used for setting Vt, nor
were there any angled implants used anywhere in the process. This is in contrast to Double-Gate
(DG), and this is possible since the Tri-Gate very much resembles bulk transistor from the
processing point-of-view.However, to get the right Vt’s, it was found necessary to protect the tri-
gate bodies from boron outdiffusion into the surrounding oxide by an N2O oxidation before gate
definition. The gate stack included polysilicon gates, and a conventional physical oxide thickness
of 15 Angstroms. Raised source/drains are used to reduce parasitic resistances and the transistor
was silicided using nickel. CMOS Tri-Gate transistors were fabricated down to 30nm.

 V-I characteristics:
V-I characteristics of CMOS devices using trigate transistor at Lg=60nm.This device has
body dimensions of HSi=36nm and WSi=55nm, The NMOS device had a subthreshold slope
(S/S) = 68 mV/decade,DIBL=41mV/V, Ion=1.14mA/mm and Ioff=70nA/mm at Vcc=1.3V. The
PMOS device showed S/S=69.5 mV/decade, DIBL=48mV/V, Ion=520mA/mm and Ioff =
24nA/mm at Vcc=1.3V

In case of NMOSFET,
  If the gate-source voltage (VGS) is less than the so-called threshold voltage (Vt) no
current will flow between the source and the drain (IDS = 0). This is the cut-off region of
operation.
 If VGS > Vt, but the source-drain voltage (VDS) is small, the device will operate in the
region called triode or linear region. In this region the current increases in response to
increasing both VGS and VDS.
 If VGS > Vt and VDS is large, the device will operate in the saturation region.In this
region, the ideal transistor has an IDS that only increases with increasing VGS.
The characteristics of a PMOSFET are the same as those of a NMOSFET,but because the
conduction is due to holes, all current/voltage has the opposite orientation

 Enhancing Design Through Innovative Integration:

For faster and cooler operation of the non-planar transistors, the tri-gate design can be
further enhanced by integrating it with several advanced semiconductor technologies:

 Strain engineering:
Strain engineering refers to a general strategy employed in semiconductor manufacturing
to enhance device performance. Performance benefits are achieved by modulating strain in the
transistor channel, which enhances electron mobility or hole mobility and thereby conductivity
through the channel. PMOS performance is best served by applying compressive strain to the
channel, whereas NMOS receives benefit from tensile strain. Intel has been using strain
engineering and is applying the technique to the non-planar tri-gate architecture.

 High-k/metal gate stack:

 Current generation CMOS gate controllers operate with only a three atom thick dielectric
layer for switching control.Thinner gates produce faster switching but are also responsible for
current leakage, thus slowing the overall transistor efficiency due to capacitance issues.The tri-
gate CMOS transistors use a high-k (dielectric constant) material such as Zirconium Dioxide
(ZrO2) to replace the transistor’s traditional silicon dioxide dielectric, and also replace the
conventional polysilicon gate electrode with metal gate electrodes.

The use of the high-k/metal-gate stack reduces the gate oxide leakage compared to the
standard SiO2/polysilicon gate stack. The use of metal electrodes eliminates polysilicon
depletion and enhances transistor performance. In addition, the use of metal electrodes with
close-to-midgap workfunctions also allows the reduction of substrate doping concentrations, thus
enhancing transistor mobilities, lower power and higher frequency designs. and hence overall
transistor performance.

 Dual epitaxial raised source/drain structure:

The integrated CMOS tri-gate transistor uses a unique raised source/drain structure built
up through epitaxial deposition of silicon for the NMOS transistor and SiGe for the PMOS
transistor. The source and drain regions are raised with respect to the plane of the gate oxide-
silicon substrate interface to reduce parasitic resistance, which improves device performance.
 An increase in the thickness of the electrical passage layer offers massive reduction in
resistance, upwards of 30% in some situations. Thin passage ways have high resistance values
due to electrons literally "crowding" the path, thus causing an electrical bottleneck. Higher
voltages can be used to push the electrons through, but this also serves to increase the power
demands of the transistor circuit. By increasing the transfer area, more electrons can pass through
with less restriction, thus leading to decreases in resistance, switching latency, and power
consumption.

 Features of trigate transistor:

 Compared to today's 65nm transistors, integrated tri-gate transistors can offer a 45

percent increase in drive current (switching speed) or 50 times reduction in off-current,
and 35 percent reduction in transistor switching power.

 The tri-gate is built on an ultra-thin layer of fully depleted silicon for reduced current
leakage. This allows the transistor to turn on and off faster, while dramatically reducing
power consumption.

 It also incorporates a raised source and drain structure for low resistance, which allows
the transistor to be driven with less power.

 The design is also compatible with the use of a high K gate dielectric for even lower
leakage.

 Tri-gate transistors show excellent DIBL, high sub threshold slope, high drive and much
better short channel performance compared to CMOS bulk transistor.
  The drive current is almost increased by 30%. The thickness requirement of the Si layer
is also relaxed by about 2-3 times that of a CMOS bulk transistor.

 Limitations:

 Ideal model

Current model of tri-gate is not perfect .Scientists are looking for ways to build the perfect
transistor, pictures in a simplified model here,where the electron flow through source and drain
should be completely wrapped by gate.

 Velocity Saturation

Velocity saturation occurs when a maximum value is reached where any increase in voltage does
not result in a linear increase in current, thereby going against Ohm's law. This effect becomes
more prominent as transistors get smaller, as in the case of tri-gate transistors.

 Sub-Threshold Swing

The sub-threshold swing is the gate voltage required to change, by one magnitude, the drain
current. As transistors get smaller, the gate length likewise decreases and subsequently this
results in an increase in the sub-threshold swing. Any increase in voltage usage results in power
wastage, which is released in form of heat.
  DIBL

Drain Induced Barrier Lowering (DIBL) is where threshold voltages are reduced at high drain
voltages. As the channel length is reduced in size, the barrier lowering increases. This effect
remains in operation even where there is no application of a reverse bias current. With increased
3-D dimensions in tri-gate transistors, DIBL becomes a problem that takes into consideration this
new design when scaling.

 Punch Through

This is an extreme case where the drain and source regions merge to form a single depletion
region. When this occurs, the gate field is dependent on the drain-source voltage. This effect
results in increased current as the drain-source voltage increases, thereby limiting the maximum
operating voltage.

 Speed Limitations

At the nanoscale, the operating speed is affected by the RC time constant and carrier mobility.
The use of high-k dielectrics means that higher polarization will be experienced. In turn, this
creates phonon vibrations which interfere with electron mobility, thereby resulting in reduced
performance.
  FUTURE:

We expect to continue driving the leading edge of Moore’s prediction well into the
foreseeable future. With the improvement in tri gate transistors physical limits of atomic
structures or power density could be reached by 2020.

Transistor dimensions scale

It will drastically improve device complexity and integrate many capabilities onto a chip. The
cumulative impact of these increases in capability, power the economy and the Internet, running
everything from digital phones and PCs to stock markets and spacecraft, and enable today’s
information-rich, converged digital world.

Passionate overclockers will always want challenge and try every possible way to
overclock your computer’s processor. No any processor’s clock speed would make them
satisfied and might put a stop in their overclocking run.A Japanese company, Unisantis, has
announced a research agreement, going to work with Singapore’s Institute of Microelectronics
(IME) to come out with tri-gate transistors which will be able to bring the clock speed of
processor for a big jump over 20GHz and even possible up to 50GHz. Also the tri-gate structure
is a promising approach for extending the TeraHertz transistor architecture.

Trigate transistor is one of the major breakthroughs in the VLSI technology. This is to
develop low power micro processors and flash memories. It will also help to increase the battery
life of the mobile devices.
  Conclusion:

The pursuit of Moore’s Law has taken us in some very interesting new directions i.e
Trigate transistors. As they tend to be taller and narrower than planar ones, allowing more
transistors to be packed into the same area on the chip. Tri-gate transistors are likely to play a
critical role in future energy efficient performance capabilities because they offer considerably
lower leakage and consume much less power than today's planar transistors. It is expected that
tri-gate technology could become the basic building block for future microprocessors sometime
beyond the 32nm process technology node. The companies claim processor clock-speeds could
reach between 20GHz and 50GHz by using these tri-gate transistors .To continue the incredible
advances in speed, remarkable switching speed, low power dissipation, battery life and cost, the
technology of tri-gate transistors is best option.
References:

 www.wekipedia.com

 www.intel.com

 www.seminarprojects .com