Daewoo Cp775 2594st, 2896st, 2898st, 28g2st, 25g1st, 29g1st SM

Service Manual
59 / 66 Cm STEREO Colour Television

CHASSIS : CP-775
MODEL :2594ST / 2896ST

2898ST / 28G2ST
25G1ST / 29G1ST
Specifications
CRT 25” : A59EAK071X11 (PHILIPS)

28” : A66EAK071X11 (PHILIPS)
System TF : PAL - B/G for West Europe, NTSC-3.58 / 4.43 (Play back)
TA : PAL - B/G, SECAM-L/L’ for France, NTSC-3.58 / 4.43 (Play back)
TU : PAL- I for U.K, NTSC-3.58 / 4.43 (Play back)
TK : PAL/SECAM - B/G, D/K, NTSC-3.58/4.43(play back) for East Europe & CIS
Main Voltage 230V AC, 50Hz
Power Consumption Stand-by mode : 10 Watts
Normal operating mode : 25” = 75 Watts
28” = 75 Watts
Sound output 5 + 5 Watts, 10 % THD at RF 60 % mod. (1 )
Speaker 12W 4 ohm x 2 EA
Antenna 75 ohm unbalanced input
Impedance
Tuning system VS( voltage synthesis ) tuning
Tuner 3303KHC (TF, TA, TK, TI Model)
BAND I : CH2 - CH4
BAND III : CH5 - CH12
CABLE BAND : S1’ - S3’ , S1 - S20
HYPER BAND : S21 - S41
BAND IV, V : CH21 - CH69
DT2-IV17D (TU Model )
BAND IV, V : CH21 - CH69
Number of 70 programs
program
Aux. Terminal 21 pin EURO-SCART jack ( AV input, TV output, RGB input )
21 pin EURO-SCART jack ( AV input, S-VHS input )
RCA type AV input jack
Headphone jack (3.5 mm )
Remote controller R-28B03 or R-35D05 with 2 “AA” type batteries
Teletext 8 pages memory TOP & FLOF
- West option :English, German/Dutch/Flemish, French, Italian,
Spanish/Portuguese, Swedish/Finnish/Danish, Czech/Slovak
- East option : Polish, Czech/Slovak, Rumanian, Hungarian, Servo-croat,
German/Dutch/Flemish, French, Italian
- Turkish option : Turkish, English, German/Dutch/Flemish, French,
Italian, Spanish/Portuguese, Swedish/Finnish/Danish
- Cyrillic option: Russian, Lettish/Lithuanian, Estonian, Ukranian,
Czech/Slovak, Servo-croat, English
OSD language -East,West,Turkish Version : English,French,German,Italian,Spanish
-Cyrillic Version : Russian, English, German
1
21 PIN EURO-SCART
PIN Signal Designation Matching Value

1 Audio Out(linked with 3) 0.5Vrms,lmp<1 (RF 60% MOD)
2 Audio In(linked with 6) 0.5Vrms,lmp>10
3 Audio Out(linked with 1) 0.5Vrms,lmp<1 (RF 60% MOD)
4 Audio Earth
5 Blue Earth
6 Audio in (linked with 2) 0.5Vrms,lmp>10
7 Blue in 0.7Vpp 3 ,lmp75
8 Slow(Function) Switching TV:0-2V,PERI:9.5-12V,lmp>10
9 Green Earth
10 NC
11 Green In 0.7Vpp 3 ,lmp75
12 NC
13 Red Earth
14 NC
15 Red In, C In 0.7Vpp 3 ,lmp75
16 Rapid(Blanking) switching Logic 0:0-0.4V,Logic 1:1-3V,Imp 75
17 Video Earth
18 Rapid Blanking Earth
19 Video Out 1Vpp 3 ,lmp75
20 Video In, Y In 1Vpp 3 ,lmp75
21 Common Earth
20 18 16 14 12 10 8 6 4 2
21 19 17 15 13 11 9 7 5 3 1
2
Safety Instruction
WARNING: Only competent service personnel may carry out work involving the testing or repair of
this equipment.
X-RAY RADIATION PRECAUTION

1. Excessive high voltage can produce potentially 2. The only source of X-RAY Radiation in this TV
hazardous X-RAY RADIATION.To avoid such receiver is the picture tube.For continued X-RAY
hazards, the high voltage must not exceed the RADIATION protection,the replacement tube
specified limit. The nominal value of the high must be exactly the same type tube as specified
voltage of this receiver is 26 at max beam in the parts list.
current. The high voltage must not, under any
circumstances, exceed 29.5 (25"), 30 (28").
Each time a receiver requires servicing, the high
voltage should be checked. It is important to use
an accurate and reliable high voltage meter.
SAFETY PRECAUTION
1. Potentials of high voltage are present when this 2. If any Fuse in this TV receiver is blown, replace it
receiver is operating. Operation of the receiver with the FUSE specified in the Replacement
outside the cabinet or with the back board Parts List.
removed involves a shock hazard from the 3. When replacing a high wattage resistor(oxide
receiver. metal film resistor)in circuit board, keep the
1) Servicing should not be attempted by anyone resistor 10mm away from circuit board.
who is not thoroughly familiar with the 4. Keep wires away from high voltage or high
precautions necessary when working on high- temperature components.
voltage equipment. 5. This receiver must operate under AC230 volts,
2) Discharge the high potential of the picture tube 50Hz. NEVER connect to DC supply or any other
before handling the tube. The picture tube is power or frequency.
highly evacuated and if broken, glass
fragments will be violently expelled.
PRODUCT SAFETY NOTICE

Many electrical and mechanical parts in this have identified by designated symbol on the parts list.
special safety-related characteristics. These Before replacing any of these components, read the
characteristics are often passed unnoticed by a parts list in this manual carefully. The use of
visual inspection and the X-RAY RADIATION substitute replacement parts which do not have the
protection afforded by them cannot necessarily be same safety characteristics as specified in the parts
obtained by using replacement components rated list may create X-RAY Radiation.
for higher voltage,wattage,etc. Replacement parts
which have these special safety characteristics are
identified in this manual and its supplements,
electrical components having such features are
3
Alignment Instructions
1. AFT
1.1 Standard B/G,D/K,I and L

1) Set a Signal Generator with
- RF FREQUENCY = 38.9 MHz,
- RF OUTPUT LEVEL = 80 5 dBuV
- System = PAL / SECAM - B/G, D/K, I
2) Connect the Signal Generator RF Output to P101 (Tuner IF Output).
There must be no signal input to the tuner.
3) Press the “AFT” KEY and wait until the TV screen display “AFT OK”.
1.2 Standard SECAM-L’ (France VHF-Low)

Above mentioned “1.1” adjustment has to be done in advance.
1) Set a Signal Generator with
- RF FREQUENCY = 34.5 MHz,
- RF OUTPUT LEVEL = 80 5 dBuV
- System = SECAM - L’
2) Connect the Signal Generator RF Output to P101 (Tuner IF Output).
There must be no signal input to the tuner.
3) Press the “L’ AFT” KEY and wait until the TV screen display “L AFT OK”.
2. AGC
1) Set a Pattern Generator with RF LEVEL 63 2 dBuV .
2) Connect a OSCILLOSCOPE PROBE to P101 (TUNER AGC INPUT).
3) Adjust AGC UP/DOWN KEY the voltage drop 1V dc over below its maximum voltage.
Alternative Method
1) Set a Pattern Generator with
- RF LEVEL 80 5 dBuV
- PAL CROSSHATCH
( without SOUND CARRIER )
2) Connect a OSCILLOSCOPE
( Bandwidth 100MHz ) PROBE
to P101 (TUNER IF OUTPUT).
3) Use AGC UP/DOWN KEY to obtain
an envelop amplitude 200 + 50 mVp-p.
3. SCREEN
1) Apply a COLOR BAR pattern signal.
2) Set the CONTRAST, BRIGHTNESS Black level
to MAX, COLOR to MIN.
3) Set the R,G,B LEVEL to CENTER (31/63) 140 5Vdc
with R,G,B UP/DOWN KEY.
4) Connect a OSCILLOSCOPE PROBE
to P906 ( CRT CATHOD R, G, B ).
5) Adjust the SCREEN VOLUME on FBT
such that the highest black level voltage GND
140 5Vdc.
5
4. WHITE BALANCE
1) Set the TV to NOR I mode.
2) Set the R,G,B LEVEL to CENTER with R,G,B UP/DOWN KEY .
3) Adjust the R,G,B UP/DOWN KEY of the other color which did not appear
on the screen to obtain WHITE.
5. FOCUS
1) Apply a RETMA PATTERN signal.
2) Adjust the FOCUS VOLUME on FBT to obtain optimal resolution.
6. GEOMETRY
6.1 VERTICAL CENTER

2) Pressing the V-SIZE UP/DOWN KEY, the
lower half of the screen is blanked.
3) Adjust the border line of blanked picture
coincident with the mechanical center marks
of the CRT using the V-SIZE UP/DOWN KEY.
6.2 VERTICAL SIZE

The VERTICAL CENTER adjustment
has to be done in advance.
3) Adjust the upper part of the picture
with the V-SIZE UP/DOWN keys.
6.3 VERTICAL SLOPE

The VERTICAL SIZE adjustment
has to be done in advance.
2) Adjust the lower part of the picture
with the V-SLOPE UP/DOWN keys.
6.4 VERTICAL S-CORRECTION

1) Apply a CROSSHATCH PATTERN signal.
2) Adjust the S-COR UP/DOWN KEY to obtain
the same distance between horizontal lines.
6.5 HORIZONTAL CENTER

2) Adjust picture centering with CENTER
LEFT/RIGHT keys.
6
7. EW
7.1 WIDTH
2) Pressing the EW KEY, the WIDTH OSD appear in the screen.
3) Adjust the over to make a perfect circle with VOL-UP/DOWN KEY.
7.2 PARA
2) Pressing the EW KEY, the PARA OSD appear in the screen.
3) Adjust the vertical line to straight with VOL-UP/DOWN KEY.
7.3 CORNER
2) Pressing the EW KEY, the CORNER OSD appear in the screen.
7.4 TRAPI
2) Pressing the EW KEY, the TRAPI OSD appear in the screen.
7
If EEPROM (I702) has been changed ;
- Option data has to be changed and
- all alignment function has to be readjusted .
The initial state of adjustment are as follows; Service Remocon
28TAF 28TUF 28TFF

POWER
TUNER 3303KHC DT21V17D 3303KHC
N O R M AL EW
OPT
LANGAGE French English English SVC ION
W/B RGB = 32 32 32
PR
AGC 11 9 10 VOL VOL

PR
V-CENTER 30 37 30 SEARCH
EFFECT TREBLE
STOP
V-SIZE 52 54 52 MIN MAX

MODE BASS
V-SLOPE 27 28 27
RCH
MIN MAX
SEA
WOOFER BAL
S-COR 15 15 15
L R
H-CENTER 43 42 42
TEM
MAX MAX MAX

SY S
WIDTH 63 63 62
SE T
CONT BRI COL

CH
MIN MIN MIN

PARA 36 38 37
CORNER 30 28 30 AUTO
AFT AFT-L' TEST AV TTX
TRAPI 29 28 29
+ + + + +
V- CENTER V- SIZE V- SLOPE S-COR. SUB BRI.
- - - -
H-CENTER
+ + + L R
R G B
AGC
- - - +
R-30SVC
REMOTE CONTROLLER R-30SVC
8
SIF ADJUSTMENT
1. APPARATUS CONNECTION & PRESETTING
* CONNECTION * PRESET
1) Connect H-out of LSW-480 to X-axis of the 1) Oscilloscope Scaling
oscilloscope and V-out of LSW-480 to Y-axis a) Put the scale of X and Y of the oscilloscope
of the oscilloscope. to D.C. level
2) Connect the sweep signal output to TP1. b) Set the horizontal time display to X-Y.
3) Set ATTENUATOR of LSW-480 to 20dB. c) Put the horizontal axis (x) to 1V / div. and the
4) Supply 12V D.C. voltage(B+) to TP3. vertical axis (Y) to 2V / div.
5) Supply 3V D.C. voltage(B+) to TP4. 2) LSW-480 MARKER FREQ. SETTING
6) Connect the test point of LSW-480 to TP2.
fp(n+1) fs fc fp-2 fp fs(n-1)
7) Adjust L109(AFT COIL) so that the P marker
31.9 33.4 34.47 36.9 38.9 40.4
point is located on the reference level.
PIF SWEEP MAKER (LSW-480) OSCILLOSCOPE
GENERATOR
H-OUTPUT X
V-OUTPUT Y
OUTPUT
FROM TP
TP1 (TUNER IF) TP2 (I603 #12)
TP3 (TUNER B+) TP3 (I603 #3)
DC POWER SUPPLY DC POWER SUPPLY

(+12V) (+3V)
- Connection For SIF Adjustment -
X
P
(38.9 MHZ)
9
IC Description
DW5255S*(Micro-controller & West/East Teletext Decoder)

(1) General Description
The TDA5255 contains a slicer for VPS and TTX, an accelerating acquisition hardware module, a display
generator for “LEVEL 1” TTX data and a 8 bit u-controller running at 333 nsec cycle time.
The controller with dedicated hardware guarantees flexibility, does most of the internal processing of TTX
acquisition , transfers data to/from the external memory interface and receives/transmits data via I2C and
UART user interfaces.
The Slicer combined with dedicated hardware stores TTX data in a VBI 1Kbyte buffer.
The u-controller firmware does the total acquisition task ( hamming- and parity -checks,
page search and evaluation of header control bits) once per field.
(2) Feature
• Acquisition:
- feature selection via special function register
- simultaneous reception of TTX and VPS
- fixed framing code for VPS and TTX
- programmable framing code window for TTX
- Acquisition during VBI
- direct access to VBI RAM buffer
- Acquisition of packets x/26, x/27, 8/30 (firmware)
- assistance of all relevant checks (firmware)
- 1-bit framing-code error tolerance (switchable)
• . Display:
- features selectable via special function register
- 50/60 Hz display
- level 1 serial attribute display pages
- blanking and contrast reduction output
- 8 direct addressable display pages
- 12 x 10 character matrix
- 96 character ROM (standard G0 character set)
- 143 national option characters for 11 languages
- 288 characters for X/26 display
- 64 block mosaic graphic characters
- 32 free addressable characters for OSD in expanded character ROM + 32 inside OSD box
- double height (TOP/BOTTOM)
- conceal/reveal
- transparent foreground/background -inside/outside of a box
- cursor (colour changes from foreground to background colour)
- flash (flash rate 1s)
- programmable horizontal und vertical sync delay
- hardware assisted fast display page erase
- full screen background colour in outer screen
• Synchronization:
display synchronization to sandcastle or Horizontal Sync (HS) and Vertical Sync (VS) with startstop-oscillator or
display synchronization to sandcastle or Horizontal Sync and Vertical Sync with external clock
independent clock systems for acquisition, display and controller
• Controller:
- 8 bit configuration
- 18 MHz internal clock
- 0.33 us instruction cycle
- eight 16-bit data pointer registers (DPTR)
10
- two 16-bit timers
- watchdog timer
- serial interface (UART)
- 256 bytes on-chip RAM
- 1 Kbyte on-chip extended RAM (access via MOVX)
- 8 Kbyte on-chip ACQ-buffer-RAM (access via MOVX)
- 6 channel 8-bit pulse width modulation unit
- 2 channel 14-bit pulse width modulation unit
- 4 multiplexed ADC inputs with 8-bit resolution
- one 8-bit I/O port with open drain output and optional I2C emulation
- two 8-bit multifunctional I/O ports
- one 4-bit port working as digital or analog inputs
- one 2-bit I/O port with optional address latch enable function
• P-SDIP 52 package
• 5 V supply voltage
(3) Block Diagram
11
Pin Name Symbol Description
1 P3.1 SYS SECAM-L’ OUT for switching SAW filter L9461
- SECAM-L’ : H
- SECAM- L : L
2 P0.7/Open Drain BUSSTOP I2C BUS STOP IN for Computer controlled
alignment in Factory ( Active Low )
3 P0.6/Open Drain SDA Serial data IN/OUT for I2C
4 P0.5/Open Drain SCL Serial clock IN/OUT for I2C
5 P0.4/Open Drain OPTION #5 #6 Teletext
6 P0.3/Open Drain OPTION H H West Teletext
L H East Teletext
H L Turkish Teletext
7 P0.2/Open Drain OPTION #7 #8 #17 Tuning / Sound System
8 P0.1/Open Drain OPTION L H H B/G (2-G, NICAM)
H H H B/G, D/K (2-C, NICAM)
L L H I/I (NICAM)
H L H I (UHF only, NICAM)
H H L L/L’ B/G (2-C, NICAM)
L H L B/G L/L’ (2-C, NICAM)
9 P0.0/Open Drain LED LED drive OUT
- Stand-by mode : H
- Operating mode : L
( IR reception : pulse )
10 VSS VSS ground
11 VCC VCC Power Supply
12 XTAL1 OSCIN Input to inverting osc. Amplifier
13 XTAL2 OSCOUT Output of inverting osc. Amplifier
14 P4.0/ALE Not Used
15 RESET RST RESET IN (ACTIVE LOW)
16 P1.7/14BIT PWM VT TUNING VOLTAGE OUT
17 P1.6/14BIT PWM OPTION TUNING SYSTEM
18 P1.5/14BIT PWM F/SW F/SW IDENT IN for stopping OSD
display in RGB mode
- H : TV /AV mode
- L : RGB mode
19 P1.4/14BIT PWM OPTION ATS OPTION H : ON
L : OFF
20 P1.3/14BIT PWM MUTE AUDIO MUTE OUT
21 P1.2/14BIT PWM GND GND
22 P1.1/8BIT PWM Not Used
23 P1.0/8BIT PWM Not Used
12
Pin Name Symbol Description
24 VSSA VSSA Analog GND for Slicer
25 FIL3 FIL3 PLL Loop Filter I/O for Phase Shifting
26 FIL2 FIL2 PLL Loop Filter I/O for TTX Slicing

27 FIL1 FIL1 PLL Loop Filter I/O for VPS Slicing
28 VCCA VCCA Analog Supply for Slicer
29 IREF IREF Reference Current for Slicer PLLs
30 CVBS CVBS CVBS IN
31 P2.3/8 bit ADC Not Used
32 P2.2/8 bit ADC AGC IF AGC INPUT for Auto Tuning System
33 P2.1/8 bit ADC KS Local KEY SCAN IN
34 P2.0/8 bit ADC S/SW S/SW IDENT IN for Automatic
switching between TV/AV mode
- H : AV / RGB mode
- L : TV mode
35 VSS VSS-OSD VSS Ground
36 P3.3/INT1 IR REMOTE IR IN
37 VDD VCC-OSD VDD Power Supply
38 LCIN OSCIN-OSD LCIN CLOCK IN for OSD
39 LCOUT LCOUT CLOCK OUT for OSD
40 P3.7/TXT I/O BL BAND VHF-L OUT ( Active High )
41 P3.6/RXD BH BAND VHF-H OUT ( Active High )
42 P3.5/T1 BU BAND UHF OUT ( Active High )
43 P3.4/T0 POWER POWER CONTROL OUT
44 P3.2/INT0 Not Used
45 HS/SC HSYNC HOR. SYNC. IN (Active High)
46 P4.7/VS VSYNC VERT. SYNC. IN (Active High)
47 R R RED OUT
48 G G GREEN OUT
49 B B BLUE OUT
50 BLANK BL BLANK OUT
51 COR COR Not Used
(CONTRAST REDUCTION OUT)
52 P3.0 T1C2/PWM1 EVEN/ODD EVEN/ODD OUT for non-interlacing
in TTX mode
13
CAT24C08P (E2 PROM)
(1) Typical Features
• IC Bus compatible
• Low power CMOS Technology
• 16 Byte page write Buffer
• Self-Timed Write cycle with Auto-Clear
• 100,000 program/Erase cycles
• 100 Year Data Retention
• Optional High Endurance Device Available
(2) Description
The CAT24C08P is a 8K bit serial CMOS E2 PROM internally organized as 1024x8bits.
The CAT 24C08P features a 16 byte page write
buffer.
(3) Block Diagram
EXTERNAL
D OUT SENSE AMPS

AKC SHIFT REGISTERS
Vcc
Vgg WORD ADDRESS COLUMN
BUFFERS DECODERS
SDA START/STOP
LOGIC
2
XDEC 64
TEST CONTROL
LOGIC
DATE IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
SEL STATE COUNTERS
A0 SLAVE
A1 ADDRESS
A2 COMPARATORS
(4) Pin Description
PIN SYMBOL DESCRIPTION

1-3 A0, A1, A2 Device Address lnputs
4 Vss Ground
5 SDA Serial Data/Address
6 SCL Serial Clock
7 TEST Connect to Vss
8 Vcc +5V Power supply
14
TDA8375A (Single chip TV Processor for Negative modulation IF )

The TDA8375A is I2C-bus controlled single chip TV processors which are intended to be applied in PAL/NTSC
television receiver.
The IC is mounted in a S-DIL 56 envelope.
(2) Feature
• IF
- Vision IF amplifier with high sensitivity and good figures for differential phase and gain
- PLL demodulator with high linearity offering the possibility for (single standard) intercarrier stereo audio application .
- Alignment PLL via I2C
- [TDA8375A] Multistandard IF with negative and positive modulation, switchable via I2C
• Video
- Integrated luminance delay line
- Integrated chroma trap and bandpass filters (auto calibrated)
- Asymmetrical peaking circuit in the luminance channel
- Black stretching of non standard CVBS or luminance signals
• Colour
- SECAM interface for application with SECAM add-on TDA8395.
• RGB
- RGB control (brightness, contrast, saturation)
- Black current stabilization and white point adjustment
• Input / Output
- Flexible video source select with CVBS input for the internal signal and two external video inputs(one switchable for
CVBS or Y/C).
- The output signal of the video source select is externally available ( also as CVBS when Y/C input is used).
- External audio input.
- Linear RGB input with fast blanking.
• Synchronization and Deflection
- Horizontal synchronization with two control loops and alignment free horizontal oscillator.
- Slow start and slow stop of the horizontal drive output to enable low stress start-up and switch-off from the line circuit
at nominal line supply voltage.
- Vertical count-down circuit for stable behavior with provisions for non-standard signals.
- Vertical geometry control.
- Vertical drive optimized for DC coupled vertical output stages.
• Control
- Full I2C bus control, as well for customer controls as for factory alignment.
- All automatic controls have an option for forced mode.
• Power consumption
- Low power consumption (900 mW at 8.0 Volts).
• Packaging
- SDIL-56 (Shrinked Dual In Line, 56 pins).
15
(3) Block Diagram
16
No Name Description
1 SOUND IF INPUT not used.
2 EXT AUDIO INPUT not used.
3 VCO REF FILTER The IF VCO tuned circuit is applied to these pin.
4 Its resonance frequency must be two times the IF-frequency and in between a
range of 64-120MHz.
This range is suitable for the IF standards as 33.4, 38.9, 45.75 and 58.75MHz.
The VCO frequency can be adjusted by I2C bus so a fixed coil can be used.
5 PLL LOOP FILTER The PLL loopfilter is a first order filter with R=390 ohm and C = 100nF in
series to ground.
The loopfilter bandwidth is 60kHz and is optimal for both fast catching and
sufficient video suppression for optimal sound performance.
Sound performance can theoretically be improved by adding a small
capacitor (approx.0- 4.7nF) between pin 5 and ground.
This however must be evaluated further because the normal video signal
response should not be effected.
6 IF VIDEO OUTPUT Although the video output impedance is low it is recommended to avoid
high frequency current in the output due to for instance sound trap filters.
This can be achieved by means of an emitter follower at the video output with
a 1 resistor in series with the base.
7 BUS INPUT : SCL Serial clock line
8 BUS INPUT : SDA Serial data line
9 BANDGAP The bandgap circuit provides a very stable and temperature independent
DECOUPLING reference voltage.
This reference voltage (6.7V) ensures optimal performance of the TDA8375
and is used in almost all functional circuit blocks.
10 CHROMA INPUT The supplied C S-VHS input burst amplitude should be nominally 300mVpp
(assumed is a colour bar signal with 75% saturation and with chroma/burst
ratio of 2.2/1 ). The C S-VHS input is internally clamped to 4V via 50 .
The external AC coupling capacitor with 50 forms a high pass filter.
A recommended coupling capacitor is 1 nF; the high pass filter cut off
frequency is then approximately 3KHz.
11 Y/CVBS INPUT The Y S-VHS signal of 1Vpp ( inclusive sync amplitude) is AC coupled to pin11.
12 MAIN The TDA8375 has a main supply pin 12 and a horizontal supply pin 37. Both
37 POSITIVE SUPPLY pins have to be supplied simultaneously.
Notice that the IC has not been designed to use this pin 37 as start pin.
(pin 37 supplies the horizontal oscillator, PHI-1 and PHl-2)
(pin 12 supplies the rest of the circuits in the IC)
The nominal supply voltage is 8V. With min/max values of 7.2-8.8V.

Also in stand-by condition the IC must be supplied with 8V.
A voltage detection circuit is connected to both pins.
- pin12 if V12 <6.8V than a power on reset, POR, is generated. The Hout
output is disabled immediate.
- pin37 if V37 <5.8V than the horizontal output is disabled immediate.
17
No Name Description
13 INT CVBS INPUT It is recommended that the CVBS1 int and CVBS2 ext input amplitudes are
17 EXT CVBS INPUT 1 Vpp (inclusive sync amplitude).
This, because the noise detector switches the 1 loop to slow mode
(i.e. auto 1mode when FOA, FOB = 0,0) when noise level exceeds
100mVrms (i.e. at S/N of 20dB).
14 GROUND All internal circuits are connected to this ground pin 14.
15 AUDIO OUTPUT not used.
16 DECOUPLING Voltage variations at pin 16, which can be due to external leakage current or
FILTER TUNING crosstalk from interference sources, should be less than 50mV to ensure that
tuning of filters/delay cells remains correct.
18 BLACK CURRENT For correct operation of the loop CURRENT information is supplied to the
INPUT black current input pin.
19 BLUE OUTPUT The RGB outputs are supplied to the video output stages from pins 21, 20
20 GREEN OUTPUT and 19 respectively.
21 RED OUTPUT For nominal signals (i.e. CVBS/S-VHS, -(R-Y)/- (R-Y), TXT inputs) and for
nominal control settings, then the RGB output Signal amplitudes is
typically 2VBLACK_WHITE.
22 V-GUARD INPUT/ Vertical Guard
BEAM CURRENT With this function, the correct working of the vertical deflection can be
LIMITER monitored. If the vertical deflection fails, the RGB outputs are blanked to
prevent damage to the picture tube.
Beam current limitinq
The beam current limiting function is realised by reducing the contrast (and
finally the brightness) when the beam current reaches s too high level. The
circuit falls apart in two functions:
- Average beam current limiting (ABL): reacting on the average content of
the picture
- Peak white limiting (PWL): reacting on high local peaks in the RGB signal.
23 RED INPUT The Rin, Gin, Bin input signals (nominal signal amplitude of 700mV) are
24 GREEN INPUT AC coupled to pin 23, 24 and 25 respectively.
25 BLUE INPUT Clamping action occurs during burstkey period.
26 RGB INSERTION The table below a survey is given of the three modes which can be selected
SWITCH INPUT with a voltage on RGB insertion switch input pin ;
Vpin26 I2C function Selected RGB signal
0.9V-3V IE1=0 RGB(internal)
IE1=1 Rin,Gin,Bin
(fast insertion on pin23,24,25)
> 4V IE1=X OSD can be inserted at the RGBout pins
27 LUMINANCE INPUT An nominal input signal amplitude of 1 Vblack-white MUST be DC coupled
to the luminance input pin 27.
The pin is internally AC coupled to the luminance clamp via a capacitor of
50pF; clamping action occurs during burstkey period.
28 LUMINANCE The luminance output signal is approximately l V black-white with typical
OUTPUT output impedance of 25O ohm.
18
No Name Description
29 B-Y OUTPUT The maximum output impedance of pins 29 and 30 is 500 when PAL/NTSC
30 R-Y OUTPUT signals are identified. When SECAM is identified by the SECAM add-on and
no PAL/NTSC is already identified by the ASM, then the ASM sets the
-(B-Y)/-(R-Y) output switch open (via DEMSW).
This enables the -(B-Y)/-(R-Y) outputs of the TDA8395 to be directly connected
to pins 29 and 3O respectively.
31 B-Y INPUT The -(B-Y),-(R-Y) output signals (supplied from baseband delay line) are AC
32 R-Y INPUT coupled, via a coupling capacitor of 10nF or greater, to the -(B-Y)/-(R-Y) inputs;
both inputs are clamped during burstkey period.
33 SECAM REF The SECAM reference output is directly connected to pin l of the TDA8395 for
OUTPUT SECAM decoding ; it also can be used as a reference for comb filter applications.
34 X-TAL 3.58 To ensure correct operation of both:
35 X-TAL 4.43 - colour processing internal circuits,
- sync calibration internal circuits,
it is only allowed to have 3.6MHz Xtals on pin34: both 4.4MHz,3.6MHz Xtals
are allowed on pin 35.
If pin 35 is not used: then it is left open in application (also XA,XB=O,1 ).
36 LOOP FILTER One of the important aspects of the PLL is the 1oop filter connected to pin 36;
BURST PHASE it influences the dynamic performance of the loop.
DETECTOR
38 CVBS OUTPUT The output amplitude is 1Vpp (transfer gain ratio between CVBS1int or
CVBS2ext or CVBS3ext/Ys-vhs and CVBSout is 1).
The maximum output impedance is 250 ohm.
39 BLACK PEAK For the correct working of the black stretcher an external time constant should
HOLD CAPACITOR be added at the black peak hold capacitor input.
40 HOR OUTPUT This open collector output is meant to drive the horizontal output stage.
The output is active low, i.e. the line transistor should conduct during the low
period of the output.
41 SANDCASTLE Pin 41 is a combined input/output pin.
OUTPUT/ The pin provides a three level sandcastle pulse.
FLYBACK INPUT Both burstkey pulse and vertical blanking pulse are always available, the line
blanking pulse is only present when the external flyback pulse is fed to this pin.
The line flyback pulse, fed to this pin is used for two functions:
- input signal for the PHI-2 1oop and
- RGB line blanking. (without flyback pulse blanking occurs only during the
burstkey pulse)
To ensure correct working of the delay line and SECAM add-on, the output
should not be loaded with more than:
- Sandcastle input delay line TDA 4665
- Sandcastle input SECAM add-on TDA 8395
42 PHI-2 FILTER / The loopfilter is a first order filter.
FLASH PROTECT This pin requires a capacitor (C) only.
A flash protection becomes active when this pin is forced >6V. The horizontal
drive is switched-off immediately.
Once the voltage is <6V the horizontal drive is switched-on again via the slow
start procedure.
19
No Name Description
43 PHI-1 FILTER The loopfilter connected to pin 43 is suitable for various signal conditions as
strong/weak and VCR signal.
This is achieved by switching of the loopfilter time constant by changing the
PHI-1 output current.
Via I2C bus FOA/B, different time constants can be chosen, including an
automatic mode which gives optimal performance under varying conditions.
44 GROUND To this pin are connected the IC-substrate and horizontal output.
45 EAST-WEST DRIVE The EW drive is a current output.
The output is single-ended and is fed directly to the EW-input terminal
46 VERT DRIVE + The vertical drive has a current output. The output is balanced which ensures
47 VERT DRIVE - a good common mode behavior with temperature and makes the output signal
less sensitive for disturbances.
48 IF INPUT The PLL frequency range is 32-60MHz with corresponding VCO frequency
49 64-120MHz.
The IF input impedances is 2 in parallel with 3pF and matches the required
load for commonly used SAW filters.
A DC coupling is allowed, so no series capacitors between SAW filter and IF
input are necessary.
50 EHT/OVERVOLTAGE The input range for EHT tracking is 1.2 ~ 2.8V, for a compensation of +/- 5%
PROTECT INPUT on vertical and/or EW.
The tracking on EW can be switched on/off by HCO.
The overvoltage protection is activated when the voltage on pin 50 exceeds
3.9V typical.
51 VERT This pin requires a capacitor to ground of l00nF +/- 5%.
SAWTOOTH The optimal sawtooth amplitude is 3.5V and is determined by the external
CAPACITOR capacitor and charge current.
The sawtooth bottom-level is 2V.
52 REFERENCE This pin requires a resistor to ground.
CURRENT INPUT The optimal reference current is 100 . which is determined by this resistor.
53 AGC The AGC capacitor value is 2.2 and has been defined for an optimal
DECOUPLING compromise between AGC speed and tilt for all AGC modes
CAPACITOR (negative/positive modulation).
54 TUNER AGC This output is used to control (reduce) the tuner gain for strong RF signals.
OUTPUT The tuner AGC is an open collector output which is acting as a variable
current source to ground.
55 AUDIO not used.
DEEMPHASSIS
56 DECOUPLING This pin requires a capacitor of 10 connected to ground.
SOUND The pin acts as a low pass filter needed for the DC feedback loop.
DEMODULATOR
20
TDA4665(Base Band Delay Line)
(1) Features
• Two comb filters, using the switched-capacitor technique,for one line delay time (64µs)
• Adjustment free application
• No crosstalk between SECAM colour carriers
• Handles negative or positive colour-difference input signals
• Clamping of AC-coupled input signals(±(R-Y)and±(B-Y))
• VCO without external components
• 3MHz internal clock signal derived from a 6MHz VCO, line-locked by the sandcastle pulse (64µs line)
• Sample-and -hold circuits and low-pass filters to suppress the 3 MHz clock signal
• Addition of delayed and non-delayed output signals
• Output buffer amplifiers
• Comb filtering functions for NTSC colour-difference signals to suppress cross-colour

The TDA4661 is an integrated baseband delay line circuit with one line delay. It is suitable for decoders
with colour-difference signal outputs±(R-Y)and±(B-Y).
(3)Block Diagram
(4) Pin Description

SYMBOL PIN DESCRIPTION SYMBOL PIN DESCRIPTION
Vp2 1 +5V supply voltage for digital part Vp1 9 +5V supply voltage for analog part
n.c. 2 not connected GND1 10 ground for analog part (0V)
GND2 3 ground for digital part (0V) V0 (R-Y) 11 ± (R-Y) output signal
i.c. 4 internally connected V0 (B-Y) 12 ± (B-Y) output signal
SAND 5 sandcastle pulse input n.c. 13 not connected
n.c. 6 not connected V1 (B-Y) 14 ± (B-Y) input signal
i.c. 7 internally connected n.c. 15 not connected
i.c. 8 internally connected V1 (R-Y) 16 ± (R-Y) input signal
21
TDA8395 (Secam Decoder)
(1) Features
Fully integrated filters
Alignment free
For use with baseband delay
(2) Description
The TDA8395 is a self-calibrating,fully integrated SECAM decoder. The IC should preferably be used
in conjunction with the PAL/NTSC decoder TDA8362 and with the switch capacitor baseband delay
circuit TDA4665. The IC incorporates HF and LF filters, a demodulator and an identification circuit
(Iuminance is not processed in this IC).
A highly stable reference frequency is required for calibration and a two-level sandcastle pulse for
blanking and burst gating.
(3) Block Diagram
CLOCHEref PLLref GND

Vp TEST
100 nF 220 nF
7 8 3 6 2
BANDGAP TUNING TUNING

TDA8395
CVBS 16 CLOCHE DE-

ACC PLL
FILTER EMPHASIS
9 –(R-Y)
IDENT- OUTPUT
INTERFACE CONTROL
IFICATION STAGE 10
–(B-Y)
1 15
fref/IDENT SAND
(4) Pin Description

SYMBOL PIN DESCRIPTION
fp1/IDENT 1 reference frequency input/identification input
TEST 2 test output
Vp 3 positive supply voltage
n.c. 4 not connected
GND 6 ground
CLOCHEref 7 Cloche reference filter
PLL ref 8 PLL reference
-(R-Y) 9 -(R-Y) output
-(B-Y) 10 -(B-Y) output
SAND 15 sandcastle pulse input
CVBS 16 video (chrominance) input
22
TDA6106Q ( Video Output Amplifier )
The TDA6106Q is a monolithic video output amplifier (5MHz bandwidth) in a SIL 9 MPpackage, using high-voltage
DMOS technology, and is intended to drive the cathode of CRT directly .
To obtain maximum performance, the amplifier should be used with black-current control.
(2) Feature
• Black - current measurement output for automatic black current stabilization (ABS)
• Single supply voltage of 200V
• Internal protection against positive appearing CRT flash-over discharge
• Protection against ESD
• Internal 2.5V reference circuit
• Controllable switch-off behavior
(3) Block Diagram
(4) Pin Description

1 N.C
2 N.C
3 V in inverting input
4 GND ground, substrate
5 I om Black-current measurement output
6 V dd supply voltage high
7 N.C
8 V oc cathode output
9 V of feedback/transient output
23
TDA8351 (DC-coupled vertical deflection circuit)
The TDA8351 is power circuit for use in 90 and 110 color deflection systems for field frequencies of 50 to 120 Hz.
The circuit provides a DC driven vertical deflection output circuit, operating as a high efficient class G system.
(2) Feature
• High efficient fully DC-coupled vertical output bridge circuit
• Vertical fly-back switch
• Guard circuit
• Protection against : - short circuit of the output pins (7 and 4)
- short circuit of the output pins to Vp
• Temperature (thermal) protection
• High EMC immunity because of common mode inputs
• A guard signal in zoom mode.
(3) Block Diagram
(4) Pin Description

1 I drive (pos) input power stage (positive); include Ii(sb) signal bias
2 I drive (neg) input power stage (negative); include Ii(sb) signal bias
3 Vp operating supply voltage
4 V o(b) output voltage B
5 GND ground
6 V fb input fly-back supply voltage
7 V o(a) output voltage A
8 V o(guard) guard output voltage (Not used)
9 V I(fb) input feedback voltage
24
STR-S5707 (Hybrid IC for a Switching Regulator)
The STR-S5707 is a Hybrid IC with a built in power transistor and a separate excitation control IC,
designed for converter type switching mode power supply applications.
The IC is capable of quasi-resonant mode and requires small number of external component.
(2) Feature
• Small SIP isolated package : Resin sealed type (transfer mold)
• Lower power dissipation at a lighter load
• Many protection function : - Pulse-by-pulse over current protection
- Over-voltage protection with a latch
- Thermal protection with a latch
• These protection functions are incorporated and can be latched with an external signal.
(3) Block Diagram
(4) Pin Description
PIN NAME SYMBOL DESCRIPTION

1 Collector C Collector of power Tr
2 Ground GND ground (Emitter of power Tr)
3 Base B Base of power Tr
4 Sink SINK Base current (IS) input
5 Over-current OCP over-current sensing signal input
protection
6 Inhibit INH input for synchronizing OFF time
Latch and latch circuit operation
7 Sensing SENS constant voltage control signal input
8 Drive DRIVE Base drive current (ID) output
9 Vin VIN supply voltage for control circuit
25
Electrical Characteristics of Control Part (Ta=25 )
Description Terminal Symbol Rating Unit
MIN TYP MAX
On-state Voltage 9-2 VIN(ON) 7.6 8 8.4 V
Off-state Voltage 9-2 VIN(OFF) 4.6 4.9 5.2 V
Operating Circuit Current 9-2 IIN(ON) 15 28 mA
Stand-by Circuit Current 9-2 IIN(OFF) 200 A
On Time TON 33 41
Off Time TOFF 45 55
OCP terminal Threshold Voltage 6-2 VOCP -1.12 -1 -0.88 V
INH terminal Threshold Voltage 1 8-2 VINH-1 0.65 0.75 0.85 V
INH terminal Threshold Voltage 2 8-2 VINH-2 1.4 2..0 V
INH terminal Threshold Voltage 3 8-2 VLatch 3.2 5.1 5.8 V
OVP Operating Voltage 9-2 VIN(OVP) 9.2 10.7 V
Latch Circuit Sustaining Current 9-2 IH 500 A
Latch Circuit Cancellation Voltage 9-2 VIN(La.OFF) 2.5 3.1 V
MIC Thermal Shutdown Tj(TSD) 125 150
Starting Temp
Fixed Reference Voltage 7-2 VS 32.0 V
Temperature Coefficient of 7-2 +2.5 mV/
Reference Voltage
Electrical Characteristics of Power Transistor Part(Trl) (Ta=25 )

Description Terminal Symbol Rating Unit
MIN TYP MAX
Collector Saturation Voltage 1-2 VCE(sat) 0.4 V
Collector Cutoff Current 1-2 ICEX 100 A
Base-Emitter saturation voltage 3-2 VBE(sat) 1.5 V
DC Current Gain hFE 29 61
Thermal Resistance j-F 1.3 /W
Switching Time 1-2 ts 15
1-2 tf 0.5
26
TDA8138 (5.1V+12V regulator with Disable and Reset)
The TDA8138 is a monolithic dual positive voltage regulator designed to provide fixed precision output voltages of
5.1V and 12V at currents up to 1A.
A internal reset cuicuit generates a reset pulse when the output 1 decrease below the regulated voltage value.
Output 2 can be disabled by TTL input.
Shot circuit and themal protections are included.
(2) Feature
• output currents up to 1A
• ixed precision Output 1 voltage 5.1V 2%
• fixed precision Output 2 voltage 12V 2%
• output 1 with Reset facility
• output 2 with Disable by TTL input
• short circuit protection at both outputs
• thermal protection
• low drop output voltage
(3) Block Diagram (4) Pin Description

1 V in 1 input 1
2 V in 2 input 2
3 Ce Delay capacitor
4 V dis disable
5 GND ground
6 RST reset
7 n.c
8 V out 2 output 2 (12V)
9 V out 1 output 1 (5.1V)
27
TDA1519B (BTL or STEREO audio amplifier)
(1) Features
Thermally protected
Requires very few external
Reverse polarity safe
components for Bridge Tied Load
Capability to handle high energy on outputs (VP
(BTL)
= 0 V)
Stereo or BTL application
No switch-on/switch-off plop
High output power
Protected against electrostatic discharge
Low offset voltage at output (important for BTL)
Identical inputs (inverting and non-inverting)
Fixed gain
Compatible with TDA1519A (except output
Good ripple rejection
power)
Mute/stand-by switch
Load dump protection
SC and DC short-circuit-safe to ground and VP
The TDA1519B is an integrated class-B dual output amplifier in a 9-lead single in-line (SIL) plastic medium
power package. The device is primarily developed for car radio applications.
(3) Block Diagram (4) Pin Description
PIN NAME DESCRIPTION

1 mute switch
1 NINV non-inverting input
Cm
60k 2 GND1 ground (signal)
VA
4
3 RR supply voltage ripple
183
rejection
power stage 4 OUT1 output 1
18.1 k
5 GND2 ground (substrate)
Vp
6 OUT2 output 2
+ 8 7 Vp positive supply voltage

stand–by
switch
– 8 M/SS mute/stand-by switch
VA stand–by
reference
voltage 9 INV inverting input
15k
x1 +
+ mute
3 switch
–
mute
15k reference
voltage
TDA1519B
18.1 k
power stage
183
6
9 VA
Cm
60k
+
input mute switch
reference
voltage
signal power
ground Vp ground
(substrate)
2 7 5
28
MSP3410 (Multistandard Sound processor for NICAM & 2-Carrier
(1) Features
• Asingle-chip Multistandard Sound Pressor for applications in analog and digital TV sets
• TWO selectable analog inputs
• Automatic Gain control for analog input
• All demoudlation and filtering is performed on chip and is individually programmable
• Adjustment of volume, balance, loudness, treble, bass, base width enlargement, pseudo stereo
• Independent input selection for speaker-out and scart-out
(2) Block Diagram
29
(3) Description
• Analog Sound IF - Input Section

The input pins ANA_IN1+, ANA_IN2+ and ANN_IN-offer the possibility to connect two different sound IF sources to
the MSP 3410. By means of bit [8] of AD_CV either terrestrial or satellite sound IF signals can be selected. The analog-
to-digital conversion of the preselected sound IF signal is done by a flash-converter, whose output can be used to con-
trol an analog automatic gain circuit (AGC), providing optimum level for a wide range of input levels. It is possible to
switch between automatic gain control and a fixed (setable) input gain. In the optimum case, the input range of the AD
converter is completely covered by the sound if source. Some combinations of SAW filters and sound IF mixer IC’s
however show large picture components on their outputs. In this case filtering is recommended. It was found, that the
high pass filters formed by the coupling capacitors at pins ANA_IN1+ and ANA_IN2+ are sufficient in most cases.
• Quadrature Mixers
The digital input coming from the integrated A/D converter may contain audio information at a frequency
range of theoretically 0 to 9 MHz corresponding to the selected standards. By means of two
programmable quadrature mixers two different audio sources, for example NICAM and FM-mono, may be
shifted into baseband position. In the following the two main channels are provided to process either:
- NICAM (channel 1) and FM mono (channel 2) simultaneously or alternatively
- FM2 (channel 1) and FM1 (channel2).
Two independent digital oscillators are provided to generate two pairs of sin/cos-functions. Two
programmable increments, to be divided up into Low- and High part, determine frequency of the oscillator,
which corresponds to the frequency of the desired audio carrier.
• Lowpass Filtering Block for Mixed Sound IF Signals

By means of decimation filters the sampling rate is reduced. Then, data shaping and/or FM bandwidth limitation is
performed by a linear phase Finite Impulse Response (FIR-filter). Just like the oscillators’ increments the filter
coefficients are programmable and are written into the IC by the CCU via the control bus. Thus, for example, different
NICAM versions can easily be implemented. Two not necessarily different sets of coefficients are required, one for
channel 1 (NICAM or FM2) and one for channel 2 (FM1=FM-mono).
Since both MSP channels are designed to process the German FM Stereo System with the same FIR coefficient set
(despite 7 dB power level difference of the two sound carriers), the MSP channel 1 has an internal overall gain of 6
dB. To process two carriers of identical power level these 6 dBs have to be taken into account by decreasing the
values of the channel 1 coefficient set.
• CORDIC Block
The filtered sound IF signals are demodulated by transforming the incoming signals from Cartesian into polar format
by means of a CORDIC processor block. On the output, the phase and amplitude is available for further processing.
AM signals are derived from the amplitude information whereas the phase information serves for FM and NICAM
(DQPSK) demodulation.
• Differentiators
FM demodulation is completed by differentiation the phase information output of the CORDIC block.
• Lowpass Filer Block for Demodulated Signals

The demodulated FM and AM signals are further lowpass filtered and decimated to a final sampling
frequency of 32 kHz. The usable bandwidth of the final baseband signals is about 15 kHz.
30
• DQPSK-Decoder
In case of NICAM-mode the phase samples are decoded according the DQPSK-Coding scheme. The
output of this block contains the original NICAM-bitstream, which is available at the N-Bus interface.
• NICAM-Decoder
Before any NICAM decoding can start, the MSP must lock to the NICAM frame structure by searching and
synchronizing to the so-called Frame Alignment Words (FAW).
To reconstruct the original digital sound samples the NICAM-bitstream has to be descrambled,
deinterleaved and rescaled. Also bit error detection and correction (concealment) is performed in this
NICAM specific block.
To facilitate the Central Control Unit CCU to switch the TV-set to the actual sound mode, control
information on the NICAM mode and bit error rate are supplied by the the NICAM-Decoder, It can be read
out via the I2C-Bus.
• Analog Section and SCART Switches

The analog input and output sections offer a wide range of switching facilities, which are shown in Fig.
To realize a TV-set with 3 pairs of SCART-inputs and two pairs of SCART-outputs no external switching
hardware is required.
The switches are controlled by the ACB bits defined in the audio processing interface (see chapter
“programming the audio processing part”).
If the MSP 3410 is switched off by first pulling STANDBYQ low and then disconnecting the 5V but keeping
the 8V power supply (‘Standby’-mode), the switches S1, S2 and S3 maintain their position and function.
This facilitates the copy from selected SCART-inputs to SCART-outputs in the TV-sets standby mode.
Fig. SCART-Switching Facilities Bold lines determine the default configuration
31
In case of power-on start or starting from standby, the IC switches automatically to the default
configuration, shown in the figure above. This action takes place after the first I2C transmission into the
DFP part. By transmitting the ACB register first, the default setting mode can be changed.
• MSP 3410 Audio Baseband Processing

By means of the DFP processor all audio baseband functions are performed by digital signal processing
(DSP). The DSP functions are grouped into three processing parts: Input preprocessing, channel selection
and channel postprocessing.
The input preprocessing is intended to prepare the various signals of all input sources in order to form a
standardized signal at the input to the channel selector. The signals can be adjusted in volume, are
processed with the appropriate deemphasis and are dematrixed if necessary.
Having prepared the signals that way, the channel selector makes it possible to distribute all possible
source signals to the desired output channels.
Of special importance is the ability to route in an external coprocessor for special effects like graphic
equalizer, surround processing and sound field processing. Routing can be done with each input source
and output channel via the I2S inputs and outputs.
All input and output signals can be processed simultaneously with the exception that FM2 cannot be
processed at the same time as NICAM. Note that the NICAM input signals are only available in the MSP
3410 version. While processing the adaptive deemphasis, no dual carrier stereo (German or Korean) or
NICAM processing is possible. Identification values are not valid either.
• Dual Carrier FM Stereo/Bilingual Detection

In the German and Korean TV standard, audio information can be transmitted in three modes: Mono,
stereo or bilingual. To obtain information about the current audio operation mode, the MSP 3410 detects
the so-called identification signal. Information is supplied via the Stereo Detection Register to an external
CCU.
32
(4) Pin Description
PIN PIN NAME DESCRIPTION

1 AUD_CL_OUT Audio clock output
2 CW_CL Pay-TV control clock
3 CW_DA Pay-TV control data
4 D_CTR_OUT1 Digital control output 1
5 D_CRT_OUT0 Digital control output 0
6 ADR_SEL Control bus address select
7 STANDBYQ Standby (low-active)
8 D_CTR_IN 0 For future use
2
9 I C_CL I2C clock
10 I2C_DA I2C clock
11 I2S_CL I2S clock
12 I2S_WS I2S wordstrobe
13 I2S_DA_OUT I2S data output
14 I2S_DA_IN I2S data input
15 S_DA_IN SBUS data input
16 S_ID SBUS ident
17 S_CL SBUS clock
18 DVSUP Digital power supply +5V
19 DVSS Digital ground
20 S_DA_OUT SBUS data output (FM/NICAM-test)
21 FRAME NBUS frame
22 N_CL NBUS clock
23 N_DA NBUS data
24 RESETQ Power-on-reset
25 DACA_R Analog output AUX, right
26 DACA_L Analog output AUX, left
27 VREF2 Reference ground2 high voltage part
28 DACM_R Analog output MAIN, right
29 DACM_L Analog output MAIN, left
30 TESTIO2 Test pin 2
31 C_DACS_R SCART output capacitor to ground
32 C_DACS_L SCART output capacitor to ground
33 SC2_OUT_R SCART output2, right
34 SC2_OUT_L SCART output2, left
35 VREF1 Reference ground1 high voltage part
36 SC1_OUT_R SCART output, right
37 SC1_OUT_L SCART output, left
38 CAPL_A Volume capacitor AUX
39 AHVSUP Analog power supply 8V
40 CAPL_M Volume capacitor MAIN
33
PIN PIN NAME DESCRIPTION
41 AHVSS Analog ground
42 AGNDC Analog reference voltage high voltage part
43 PDMC1 Capacitor to BAGNDI
44 PDMC2 Capacitor to BAGNDI
45 BAGNDI Buffered AGNDC
46 SC3_IN_L Scart input3 in, left
47 SC2_IN_R Scart input3 in, right
48 ASG2 Analog Shield Ground2
51 ASG1 Analog Shield Ground1
54 VREFTOP Reference voltage IF A/D converter
55 MONO_IN Mono input
56 AVSS Analog ground
57 AVSUP Analog power supply +5V
58 ANA_IN1+ IF input1
59 ANA_IN1- IF common
60 ANA_IN2+ IF input (if ANA_IN1+is used only, connect to
AVSS with 50pF Capacitor
61 TESTIO1 Test pin1
62 XTAL_IN Crystal oscillator
63 XTAL_OUT Crystal oscillator
64 DMA_SYNC DMAC-sync: signal
34
TDA4445B (Quasi Parallel Sound Processor)
(1) Features
• Very high input sensitivity
• Excellent signal to noise ratio
• Fast averaged AGC
• IF amplifier can be switched off for VTR mode
• Output signal stabilized against supply voltage variations
• Very few external components
• Targeting bistandard applications
• Low AM distortion

The TDA4445B is quasi parallel sound processor with quadrature intercarrier demodulator.
(3)Block Diagram
(4)Pin Description
PIN DESCRIPTION
1, 16 IF input
3 IF AGC time constant
8, 9 Tuned circuit
11 Supply voltage
12 Sound-IF-output
13 Ground
2,4,7,10
not be connected
14,15
5 Average capacitor
6 AF output
35
GMS30112-R098 (4-bit Single Chip Microcomputer for Remote control)
The GMS30112-R098 is 4-bit single chip CMOS microcomputer.
(2) Feature
• program memory : 1024 bytes
• data memory : 32 x 4 bits
• 43 types of instruction set
• 3 levels of subroutine nesting
• 1 bit output port for a large current (REMOUT signal)
• operating frequency : 300kHz - 1 MHz
• instruction cycle : 12.5 usec @ 480kHz
• CMOS process ( single 3.0 V power supply )
• stop mode (through internal instruction)
• released stop mode by key input (masked option)
• built in capacitor for ceramic oscillation circuit (masked option)
• built in a watch dog timer(WDT)
• low operating voltage (2.0 V to 4.0 V)
(3) Block Diagram
36
(4) Pin Description

1,2,3,4 K0,K1,K2,K3 4 bit input port with built in pull up resistor
5,6,7,8,9,10 D0,D1,D2,D3,D4,D5 10 bit output port which can be set or reset pin
by pin independently.
The output structure is N-channel open drain.
11 REMOUT remote control signal output port which has
high current driving capability
12 OSC 2 oscillator output
13 OSC 1 oscillator input
14 Vdd 2-4V power supply
15 RESET reset signal input which is a low active
16 GND ground
17,18,19,20 R0,R1,R2,R3 4 bit programmable I/O port
37
IC DC Voltage charts
Input signal PAL/CH5-Video : 8 step colour bar (87% AM)
Audio : 1 KHz sinewave (60% FM)
User’s control condition Contrast, Brightness, Colour, Volume Controls-max.

Line voltage AC 230V, 50Hz
All the voltage in each point are measured with Multimeter
1. TDA 8375A (I501)

Pin No. 1 2 3 4 5 6 7 8 9 10
V(DC) 0 0 3.6 3.6 2.7 3.3 3.7 3.4 6.6 4
Pin No. 11 12 13 14 15 16 17 18 19 20
V(DC) 3.5 8 4 0 3.4 3.6 3.5 5.1 3.8 3.9
Pin No. 21 22 23 24 25 26 27 28 29 30
V(DC) 4 1.9 3.5 3.5 3.5 0.3 2.8 2.8 1.8 1.8
Pin No. 31 32 33 34 35 36 37 38 39 40
V(DC) 4 4 1.6 2.6 2.6 4.9 8 8 4 1.5
Pin No. 41 42 43 44 45 46 47 48 49 50
V(DC) 0.5 4.5 4 0 0.5 2.2 2.2 4 4 1.7
Pin No. 51 52 53 54 55 56
V(DC) 3.8 3.9 3 3 3.5 3.8
2. DW 5255S (I701)
Pin No. 1 2 3 4 5 6 7 8 9 10
V(DC) 0 5 3.4 3.6 5 5 5 5 0 0
Pin No. 11 12 13 14 15 16 17 18 19 20
V(DC) 5 2.6 2.6 5 5 4.1 0 5 5 0
Pin No. 21 22 23 24 25 26 27 28 29 30
V(DC) 5 5 5 0 2.6 2.6 2.6 5 1.5 1.5
38
Pin No. 31 32 33 34 35 36 37 38 39 40
V(DC) 0.5 2.5 5 0 0 5 5 2.7 2.8 3.2
Pin No. 41 42 43 44 45 46 47 48 49 50
V(DC) 0 0 4.7 5 0.4 1.3 0 0 0 0
Pin No. 51 52
V(DC) 0 0
3. TDA 4665 (I503)

Pin No. 1 2 3 4 5 6 7 8 9 10
V(DC) 5 0 0 0 0.6 0 0.3 0 5 0
Pin No. 11 12 13 14 15 16
V(DC) 2.9 2.9 0 1.3 0 1.3
4. TDA 4445B (I603)

Pin No. 1 2 3 4 5 6 7 8 9 10
V(DC) 4.5 0 2.5 0 4 4 0 4.7 4.7 0
Pin No. 11 12 13 14 15 16
V(DC) 12 5.3 0 0 0 4.5
5. TDA 4445B (I602)

Pin No. 1 2 3 4 5 6 7 8 9 10
V(DC) 4.5 0 2.6 0 4 4 0 4.8 4.8 0
Pin No. 11 12 13 14 15 16
V(DC) 12 3.7 0 0 0 4.5
39
6. TDA 8395 (I502)
Pin No. 1 2 3 4 5 6 7 8 9 10
V(DC) 1.6 1.2 8 0 0 0 3.3 4.3 1.7 1.7
Pin No. 11 12 13 14 15 16
V(DC) 0 0 0 0 0.5 3.4
7. TDA 8138 (I802)

Pin No. 1 2 3 4 5 6 7 8 9
V(DC) 12 4.5 3 4.5 0 5 0 12 5
8. TDA 8351 (I301)

Pin No. 1 2 3 4 5 6 7 8 9
V(DC) 2.3 2.3 16 8.3 0 4.6 8.3 0.6 7.1
9. TDA 1519B (I601)

Pin No. 1 2 3 4 5 6 7 8 9
V(DC) 1.9 0 6.4 6.4 0 6.5 13.3 12.7 1.9
10. MSP 3410 (I602)

Pin No. 1 2 3 4 5 6 7 8 9 10
V(DC) 0 0 0 0 0 0 4.9 0 3.6 3.4
Pin No. 11 12 13 14 15 16 17 18 19 20
V(DC) 2.5 2.5 2.5 2.5 2.5 4.9 3.8 4.9 0 3.8
Pin No. 21 22 23 24 25 26 27 28 29 30
V(DC) 0 2.5 0.5 5 0.1 0.1 0 1.5 1.7 0
Pin No. 31 32 33 34 35 36 37 38 39 40
V(DC) 3.8 3.8 3.8 3.8 0 3.8 3.8 7.1 8 6.2
40
Pin No. 41 42 43 44 45 46 47 48 49 50
V(DC) 0 3.7 3.8 3.8 3.8 3.8 3.8 0 3.8 3.8
Pin No. 51 52 53 54 55 56 57 58 59 60
V(DC) 0 3.8 3.8 2.7 4 0 5 1.5 1.5 0.1
Pin No. 61 62 63 64
V(DC) 0 2.5 2.5 0.1
41
Circuit Description
Vision IF amplifier, AFC, video demodulator

The IF signal from the tuner is fed through a SAW filter to the differential IF input (pin 48 and 49).
The first IF stage consists of 3 AC-coupled amplifiers with a total gain control range of over 66 dB.
The reference carrier for the video demodulator is obtained by a PLL carrier regenerator
(eliminating notch filter compromises, as in reference tuned circuits for passive carrier regeneration).
Only an oscillator coil is needed( pin 3 and 4) that can be aligned via l2C-bus to the double IF frequency.
The AFC information is derived from the VCO control voltage of the IF-PLL
and can be read via I2C-bus.
Bit AFB toggles when the picture carrier is exactly at the desired IF frequency (= half the aligned IF-PLL frequency).
AFA is active in a window around this point.
For fast search-tuning applications this window can be increased by a factor 3 (AFW bit).
Tuner A.G.C.
The automatic gain control (A.G.C.) circuit operates on top sync level at negative modulated signals
or on peak white level at positive modulation, selected by MOD bit.
The tuner A.G.C. is controlled via pin 54.
The tuner A.G.C. take over point (T.O.P.) can be set over a wide range: 0.8 mVrms .. 80 mVrms
IF input signal amplitude.
The tuner AGC output may have to operate above Vcc of TDA8375A.
Therefore pin 54 is an open collector output, that can operate from 0.3 up to Vcc+ 1 Volt
(at > 2 mA sink current)
Source select switch

TDA8375A input switch can select one of the following sources ;
pin 13 front-end : CVBS l int
pin17 : CVBS 2 ext
pin 11.pinlO : Y (S-VHS), C (S-VHS)
Selected signal is available at the CVBS output pin 38, in case of Y/C input Y+C are added.
It drive teletext and the TDA8395 SECAM add-on.
For S-VHS applications, the Y,C input can be selected, independent of the CVBS source switch.
TDA8375A Y,C inputs are selected, while the source switch outputs CVBS l int or CVBS 2 ext on CVBS out.
Horizontal synchronization and protection

The synchronization separator adapts its slicing level in the middle between top-sync and black level of the CVBS signal.
The separated synchronization pulses are fed to the first phase detector and to the coincidence detector.
The -1 loop gain is determined by the components at pin 43 (C+RC).
The coincidence detector detects whether the horizontal line oscillator is synchronized to the incoming video.
The line oscillator is a VCO-type, running at twice the line frequency.
It is calibrated with the X-tal oscillator frequency of the colour decoder and has a maximum deviation of 2% of the
nominal frequency, so no alignment is-needed.
Calibration is done at start up( the TDA8375A must first know what colour X-tals are connected, bits XA and XB) and
after synchronization loss ( -1 coincidence detector “Sync Locked” bit SL).
The second phase detector -2 locks the phase of the horizontal driver pulses at output pin 40 to the horizontal
flyback pulse at input pin 41 .
This compensates for the storage time of the horizontal deflection transistor.
The - 2 loop filter (C) is externally connected to pin 42.
The horizontal phase can be given a static off set via I2C-but (HSH “horizontal shift”)
A dynamic correction is possible by current feedback into the - 2 loop filter capacitor.
To protect the horizontal deflection transistor, the ho rizontal drive is switched off immediately when a power
42
failure ( “ Power-On Reset “ bit POR ) is detected.
The power failure may have corrupted the contents of the internal data registers, so the TDA8375A should be
started up again.
The TDA8375A has a separate supply input (pin 37) that only used as a clean supply voltage for thehorizontal
oscillator circuits.
Vertical synchronization
The vertical sawtooth generator drives the vertical output.
It uses an external capacitor at pin 51 and a current reference resistor at pin 52.
The TDA8375A vertical drive has differential current outputs for DC-coupled vertical output stage, like the TDA8351 .
At TDA8351 input pins l and 2 this current is converted into a drive voltage via a resistor.
Geometry processing
With the TDA8375A is possible to implement automatic geometry alignment, because all parameters are adjusted
via the I2C bus.
The deflection processor of the TDA8375A offers the following five controls;
- Horizontal shift
- Vertical slope.
- Vertical amplitude
- Vertical S-correction
- vertical shift
Colour decoder
The colour decoder contains an alignment-free X-tal oscillator, a dual killer circuit and colour difference demodulators.
Together with the TDA8395 SECAM add-on a multi standard PAL/SECAM/NTSC decoder can be built with
automatic recognition.
Which standard can be decoded depends on the external Xtals used.
Two Xtal pins (34and 36) are present so normally no external switching is required.
The I.C. must be told which X-tals are connected (bits XA and XB).
This is important, because the X-tal frequency of the colour decoder is also used to calibrate many internal circuit.
The burst phase detector locks the Xtal oscillator with the chroma burst signal.
The phase detector operates during the burst key period only, to prevent disturbance of the PLL by the chroma signal.
Two gain modes provide:
- Good catching range when the PLL is not Locked.
- Low ripple voltage and good noise immunity once the PLL has locked
The killer circuit switches-off the R-Y and B-Y demodulators at very low input signal conditions (chroma burst amplitude).
A hysteresis prevents on/off switching at low, noisy signals.
Color standard pin34 pin35 XA XB

PAL4.43/SECAM + NTSC-4.43 none 4.43 1 0
PAL4.43/SECAM + NTSC-M 3.58 4.43 1 1
Integrated video filters

The TDA8375A has alignment-free internal luminance delay, chroma bandpass and chroma trap.
They are implemented as gyrator circuits tuned by tracking to the frequency of the chroma Xtal oscillator.
The chroma trap in the Y signal path is by-passed when Y/C input is selected (S-VHS ).
For SECAM an extra luminance delay is build-in, for correct delay of the luminance signal.
43
RGB output and black current stabilization
The colour difference signals (R-Y, B-Y) are matrixed with the luminance signal (Y) to obtain the RGBout output
signals (pins 19, 20, 21).
In the TDA8375A the matrix type automatically adapts to the decoded standard (NTSC,PAL) .
Linear amplifiers are used to interface external RGB in signals (pins 23,24,25) from the SCART connector.
These signals overrule the internal RGB signals when the data insertion pin 26 (FBI) is switched to a level between
1.0V and 3.0V.
The contrast and brightness control and the peak white limiter operate on both internal and external RGB signals
R,G and B each have their own, independent gain control to compensate for the difference in phosphor efficiencies
of the picture tube: so called “white point” adjustment.
The nominal amplitude is about 2V black to white, at nominal input signals and control settings.
TDA8375A has a black current stabilization loop, that automatically adjust the black level to the cut-off voltage of the
picture tubes three gun cathodes.
Since no current is flowing when the voltage the cathode is equal to the cut-off voltage of the tube, the loop stabilizes
at a very small gun current.
This “black current” of the three guns is measured internally and compared with a reference current, to adjust the
black level of RGBout.
The black level loop is active during 4 lines at the end of the vertical blanking.
In the first line the leakage current is measured (max. acceptable 100 A).
In the next three lines the black levels of the three guns are adjusted.
The nominal value of the ‘black current’ is 10 A.
The ratio of the ‘black currents’ for the 3 guns tracks automatically with the white point adjustment, so the
back-ground colour is the same as the adjusted white point.
At switch-on of the TV receiver the black current stabilization circuit is not yet active and RGBout are blanked.
Before the first measurement pulses appear, 0.5 sec delay ensures that the vertical deflection is active, so the pulses
will not be visible on the screen.
During the measuring lines RGBout will supply 4V pulses to the video output stages.
The TDA8375A waits until the black current feedback input (pin 18) exceeds 200 A, which indicates that the picture tube
is warm-up.
Then the black current stabilization circuit is active.
After a waiting time of about 1.0 sec, the blanking of RGBout is released.
Tuning
The AFC information of the TDA8375A is not available as an analogue voltage.
Automatic following (=frequency tracking, AFC) can be done via the I2C-bus by software.
The TDA8375A AFC window is typically 80 kHz wide.
This value is made higher than the 62.5 kHz tuning step, to prevent an automatic following loop from continuously
adapting the tuning frequency..
With this AFC window ( 40 kHz) the maximum tuning error is less than 62.5 kHz.
For high speed search-tuning-algorithms, the AFC window can be widened to 240 kHz via bit AFW.
TDA8395 SECAM decoder

The TDA8395 is an alignment-free SECAM colour decoder, including a Cloche filter, demodulator and line
identification circuit.
The Cloche filter is a gyrator-capacitor type.

Its frequency is calibrated in the vertical retrace period.
The calibration reference( pin 1 ) is obtained from the TDA8375A color X-tal oscillator (pin 33).
Pin 7 is a decoupling for the Cloche reference.
44
The voltage change at this pin due to leakage currents should be lower than 10 mV, during field scan, resulting in a
capacitor of minimal 100 nF.
Pin 8 is the reference capacitor for the PLL.
The voltage variation during field scan at this pin should be lower than 2 mV , resulting in a capacitor of 220 nF.
The sandcastle input (pin 15) is connected to TDA8375A pin 41 and is used for generation of the blanking periods and
provides clock information for the identification circuit.
The CVBS source select output (TDA8375A pin 38) supplies SECAM chroma to pin 16 of the TDA8395.
This is demodulated by a PLL demodulator, that uses the reference frequency at pin l and a bandgap reference to
obtain the desired demodulation characteristic.
If the digital line identification in theTDA8395 detects SECAM, pin 1 will sink a current of 150 (A out of TDA8375A
SECAMref pin 33.
When the TDA8375A has not detected PAL or NTSC, it will respond by increasing the voltage at pin 33 from 1.5V to 5V.
Now the TDA8375A color difference outputs pin 30 and 29 are made high-ohmic and the TDA8395 output pin 9 and 10
are switched on.
These outputs will be disconnected and high-ohmic when no SECAM is detected for two frame periods, the decoder
will be initialized before trying again.
SECAM-L and -L’ application

For SECAM-L and L’ the TDA8375A has to be switched to positive modulation via I2C-bus bit MOD.
SECAM-L’ signals only occur in VHF band l and have their picture and sound carrier interchanged, compared to
SECAM-L/PAL channels.
For SECAM-L’ the IF picture carrier is situated at 34.5 MHz and the AM-sound carrier at 41MHz.
Therefore the IF-PLL reference has to be tuned away from 38.9 to 34.5 MHz.
This can be done via I2C-bus sub-address 15hex (IF-PLL).
The AM sound output is inserted at TDA8375A external audio input pin via the SCART plug.
When bit MOD selects positive modulation for SECAM-L/L’, the TDA8375A automatically switches to external audio.
Base band delay line TDA4665

TDA4665 is an integrated double baseband delay line of 64 S.
It couples to the TDA8375A and TDA8395 without any switches or alignments.
The TDA4665 consist of two main blocks:
- Two delay lines of 64 sec in switched capacitor technique
- Internal clock generation of 3 MHz, line locked to the sandcastle pulse
The TDA4665 operates according to the mode demanded by the colour transmission standard:
- For PAL it operates as geometric adder to satisfy the PAL demodulation requirements
- In NTSC mode it reduces cross-colour interference (comb-filtering)
- For SECAM it repeats the colour difference signal on consecutive horizontal scan lines.
A sandcastle pulse is connected to pin 5.

The top pulse voltage (should not exceed 5 V) can be directly coupled to the 5 V sandcastle output of the TDA8375A.
The R-Y and B-Y colour difference signals (from TDA8375A pins 30 and 29) are AC-coupled and clamped by the
input stages at pins 16 and 14.
An internal 6 MHz Current controlled oscillator is line locked via a PLL to the sandcastle pulse at pin 5.
This clock drives the delay lines to obtain the required 64 sec.
Sample and hold low pass filters supress the clock signal.
The original and the delayed signals are added, buffered and fed to the output pins 11 and 12.
These are AC-coupled to the R-Y and B-Y colour difference input pin 32 and 31 of TDA8375A.
45
The TDA4665 needs a 5 V supply voltage on pin 1 for the digital part and on pin 9 for the analog part.
TDA8351 vertical deflection.

The TDA8351 is a vertical deflection circuit.
It can be used in 90 deflection systems with frame frequencies from 50 up to 120 Hz
With its bridge configuration the deflection output can be DC coupled with few external components.
Only a supply voltage for the scan and a second supply for the flyback are needed.
The TDA8351 can drive max.2A.
The vertical drive currents of TDA8375A pins 47 and 46 are connected to input pins 1 and 2 of the TDA8351.
The currents are converted into a voltage by a resistor between pins 1 and 2.
Pin2 is on a fixed DC level (internal bias voltage) and on pin l the drive voltage can be measured (typical 1.8 Vpp).
The drive voltage is amplified by ‘A’ and fed to two amplifiers ‘B’ and ‘C’, one is inverting and the other is a non
inverting amplifier.
The outputs (pins 4 and 7) are connected to the series connection of the vertical deflection coil and feedback resistor .
The voltage across feed back resistor is fed via pin 9 to correction amplifier ‘D’, to obtain a deflection current which is
proportional to the drive voltage.
The supply voltage for the TDA8351 is 16V at pin 3.

The flyback generator has a separate supply voltage of 45V on pin 6.
Horizontal deflection
The circuit contains horizontal drive, line output transformer.
The horizontal driver pulses from the TDA8375A are amplified in the horizontal drive circuit, to get sufficient base-drive
current for the high voltage switching transistor Q401.
During the horizontal scan period( =52 s) Q401 will conduct, and a sawtooth current flows from +132V through the
primary winding of the FBT to ground.
After this time Q401 is switched off and the energy stored in the FBT during the scan period will be transformed to the
flyback capacitor CT.
This energy transfer will take place in a cosine shape because the primary of the FBT and CT from a resonant circuit.
The time the energy is transferred from FBT to CT. and back to the FBT, is called the flyback time and will take place
in about 12 s.
The flyback peak voltage is about 9 times the scan voltage.
In series with the horizontal deflection coil there is a (damped) linearity corrector coil.
During the scan there is some loss in the resistance of the deflection coil.
In the first part of a line the linearity corrector stores some energy in a permanent magnet until it is saturated.
This improves the linearity of the horizontal scan speed.
The required S correction for the picture tube can be adjusted with the value of C408.
The beam current limiting information (BeamCurr) is derived from the foot of the H.V winding of the FBT.
This is connected via resistor to +8V.
As the beam current increase, the voltage on line BeamCurr decreases.
BeamCurr is damped by a integration filter before it is fed back to TDA8375A pin 22.
The TDA8375A will decrease the contrast (and eventually the brightness) to limit the average beam current.
EW drive
The DC voltage on pin 45 is determined by the East-West driver stage input and may range from 1 to 8 volts.
To prevent distortion, the voltage must always be >1volt.
Because the DC voltage on pin 45 is equal to the minimal output voltage of the East-West driver stage (reached for iew =
0), it is recommended to choose this level close to 1 volt for maximum range.
46
Video amplifiers
Three TDA6106Q integrated video amplifiers drive cathode of the picture tube directly.
They are protected against CRT flashover discharges and ESD (electro static discharge).
The three video amplifiers, have a beam current output I black, used by the TDA8375A black current loop to control
the black level on the cathodes.
The outputs can be connected together because the black current 100p sequentially controls the black level for each
cathode.
The amplification of the TDA6106Q is set by the resistors between pin 3 and 9 and between pin 3 (negative-input) and
the TDA8375A output.
There are no alignment any more on the CPT panel, because of the automatic black current stabilization and because
the white point adjustment can be done in the TDA8375A via I2C bus.
Power Supply STR-S5707

(1) VIN terminal, start-up circuit
A start-up circuit is to start and stop a operation of a control IC by detecting a voltage appearing at a VIN terminal
(pin-9).
At start up of a power supply, when a voltage at the VIN terminal reaches to 8V (typical) by charging up C812 by
the function of a start-up resistor, R802, a control circuit starts operating by the function of the start-up circuit.
After the control circuit starts its operation, power source is obtained by smoothing voltage appearing at winding of
pin6-7 of T802.
(2) Oscillator, F/B terminal voltage (Pin 7)

A oscillator generates pulse signals which turns a power transistor on and off by making use of charge and discharge
of C1 and C2 incorporated in the Hybrid IC.
Constant voltage control of a switch-mode power supply is performed by changing both ON-time and OFF-time except
when the load is light (ex. remote control stand-by mode of TVs).
The ON-time is controlled by changing a current charged by C1, which is as the result of that the detection winding of
pin5-7 of T802, which detects a change of voltage in a secondary side, connected to the sensing terminal (Pin 7) has the
current in accordance with an output signal from an output voltage detection circuit (an error amplifier) built in.
As an AC input voltage to the power supply gets the higher and a load current the smaller, the current flowing to the
SENS terminal gets the larger, and the ON-time gets the shorter.
(3) Function of INH terminal (Pin 6), control of OFF-time

Signal to the INH terminal is used as inputs to COMP.1 and COMP.2 inside of the control IC.
A threshold voltage of COMP.1, VTH1 is set at 0.75V (Ta=25°) and an input signal to a drive circuit becomes almost
0V (the power transistor is in OFF mode) when a voltage at the INH terminal reaches the VTH1.
A threshold voltage of COMP.2, VTH2, is set at 1.5V (Ta=25°).
When the INH terminal voltage reaches VTH2, an output from COMP.2 reverses (the power transistor is in on mode).
Quasi-resonant operation
By inputting the voltage of winding of pin6-7 of T802 which is synchronized with the energy discharge time of a
secondary winding, pin14(or 15)-16 of T802, to the INH terminal through D805 and RC803, quasi-resonant operation
can be achieved.
When the power transistor turns off and a voltage higher than VTH2 is applied to the INH terminal, C3 immediately
discharges and then starts charging again.
Even after the discharge of energy of a secondary winding is completed, VINH does not immediately increases.
When it gets lower than VTH1, the transistor turns on.
47
Stand-By Mode
While being in remote control stand-by mode, the output voltage is kept on providing to the secondary side and
the power transistor operates at A class mode.
(4) Drive circuit

The STR-S5707 applies the proportional drive system in order to minimize turn-on and saturation loss, and storage time.
(5) OCP (over-current protection) function

Over-current protection is performed pulse by pulse by directly detecting collector current of the power transistor.
Detecting voltage is set to -1V below a reference point of GND (ground).
(6) Latch circuit

It is a circuit which sustains an output from the oscillator low and stops operation of the power supply when over-voltage
protection (OVP) circuit and thermal shutdown (TSD) circuit are in operation.
As the sustaining current of the latch circuit is 500 A maximum when VIN terminal voltage is 4V, the power supply
circuit sustains the off state as long as current of 500 A minimum flows to VIN terminal from a start-up resistor.
In order to prevent a malfunction to be caused by a noise and so on, delay time is provided by C1 incorporated in the
IC and, therefore, the latch circuit operates when the OVP or TSD circuit is in operation, or an external signal input is
provided for about 10 sec or longer.
In addition, even after the latch circuit start operating, the constant voltage regulator (Reg) circuit is in operation and the
circuit current is at high level.
As a result, VIN terminal voltage rapidly decreases.
When VIN terminal voltage becomes lower than the shutdown voltage, VIN(OFF) (4.9V typical), it starts increasing as the
circuit current is below 500 A.
When it reaches the ON-state voltage, VIN (ON) (8V typical), VIN terminal voltage starts decreasing because the circuit
current increases again.
When the latch circuit is on, VIN terminal voltage increases and decreases within the range from 4.9V typical to
8V typical and is prevented from abnormally rising.
Cancellation of the latch is done by decreasing VIN terminal voltage below 3.3V.
The power supply can be restarted after disconnecting an AC input to the power supply once.
(7) Thermal shutdown circuit

It is a circuit to trigger the latch circuit when the frame temperature of the IC exceeds 150 (typical).
Although the temperature is actually sensed at the control chip, it works against overheating of the power transistor
as the power transistor and the control IC are mounted on the same lead frame.
(8) Over-voltage protection circuit

It is a circuit to trigger the latch circuit when VIN terminal voltage exceeds 11V (typical).
Although it basically functions as protection of VIN terminal against over-voltage, since VIN terminal is usually supplied
from the drive winding of the transformer and the voltage is proportional to the output voltage, it also functions against
the over-voltage of secondary output which causes when the control circuit opens or in some other events.
48
THE DIFFERENT PARTS FOR CRT (CP-775)
No LOC. NAME 28” (V/COLOR 28”(PHILIPS) 25”(PHILIPS) 25”(ORION) 29”(ORION)

(2896ST, 2898ST) (2896ST, 2898ST) (2594ST) (25G1ST) (29G1ST)
1 C402 C MYLAR 1.6KV 7200PF 1.6KV 8200PF
CMYH3C722J CMYH3C822J
2 C404 C MYLAR 1.6KV 4700PF 1.6KV 8200PF
CMYH3C472J CMYH3C822J
3 C408 C MYLAR 400V 0.27MF 400V 0.33MF 400V 0.47MF
CMYE2G274J CMYE2G334J CMYE2G474J
4 D406 DIODE BYW95C
DBYW95C - - -
5 C409 C CERA 250V 47MF
CEXF2E470V
6 J802 WIRE COPPER AWG22 1/0.65 TIN
COATING
85801065GY
7 R333 R C-FILM 1/4W 2K OHM 1/4W 3K OHM
RD-4Z202J - RD-4Z302J-
8 R919 R FUSIBLE 1W 0.68 1W 3.3
RF01Z688J - RF01Z339J -
9 V901 CRT A66ECY13X611 A66EAK071X11 A59EAK071X11 A59KTB96X01 P38 A68KTB190X006 P38
4859613360 4859622160 4859622260 4859608962 4859618060
10 ZDC10 COIL DC-2701 DC-2501 DC-2500 DC-2901
DEGAUSSING 58G0000103 58G719M096 58G0000092 58G0000094
11 L401 COIL TRL-330 TRL-200D
H-LINEARITY 58G0000025 58G0000039
12 P501A CONN AS YH025-06+YST025+ YH025-06+YST025+
ULW=400 USW=500
4850706S02 4850706S18
13 ZCG10 CRT 2801H-1015-2P 2501H-1015-2P 2901H-1015-2P
GROUND AS 48519A5510 48519A4010 48519A4210
49
THE DIFFERENT PARTS FOR SYSTEM (CP-775)
No LOC. NAME TF TU TK TA
COATING
85801065GY
2 J702 WIRE COPPER
3 J703 WIRE COPPER AWG221/0.65 TIN

COATING
85801065GY
COATING
85801065GY
5 J705 WIRE DOPPER AWG22 1/0.65 TIN
COATING
85801065GY
6 J706 WIRE COPPER
7 SF01 FILTER SAW G3962M G3962M G3962M G3962M

5PG3962M - - 5PG3962M - - 5PG3962M - - 5PG3962M - -
8 SF02 FILTER SAW G9251M K9260M K9260M G9251M
5PG9251M - - 5PK9260M - - 5PK9260M - - 5PG9251M - -
9 SF03 FILTER SAW L9461M
5PL9461M - -
10 Z502 FILTER CERA MKT40MA100P MKT40MA100P MKT40MA100P
5PMKT40MA - 5PMKT40MA - 5PMKT40MA -
11 I502 IC TDA8395 TDA8395
1TDA8395 - - 1TDA8395 - -
12 I604 IC TDA4445B
TDA4445B -
13 U100 TUNER 3303KHC DT2-IV17D 3303KHC 3303KHC
VATACTOR 4859714430 4859716130 4859714430 4859714430
14 P801 CORD POWER CW4232+BL102NG CW3222/240V 5A KKP419C+BL102NG CW4232+BL102NG
AS +TUBE=2500 +HOUS=2200 +TUBE+2100 +TUBE=2500
4859903110 4859905110 4859902910 4859903110
15 D601 DIODE 1S2186
D1S2186 - - -
16 D602 DIODE 1S2186
D1S2186 - - -
50
MECHANICAL EXPLODED VIEW
2896
23 4857817611 CLOTH BLACK 6 FELT TO.7 200 20

22 7122401612 SCREW TAPPING 9 T2S TRS 4 16 MFZN C/B+M/F
21 4852148901 COVER BACK 1 HIPS BK
20 CRT 1
19 4856015700 SCREW CRT FIXING 4 SWRM+SK-5L=27
18 4856215402 WASHER RUBBER 4 CR
17 MAIN PCB AS 1 CP-775
16 4854934001 BUTTON 1 ABS BK
14 7121401611 SCREW TAPPING 20 T2S PAN 4 16 MFZN BRKT+M/F
13 4853414501 BRKT CRT 4 ABS NC
12 4853311601 RETAINER BACK 7 HIPS NC
11 4852062401 MASK FRONT 1 HIPS BK
10 7122401212 SCREW TAPPING 8 T2S TRS 4 12 MFZN SPK+M/F
9 SPK 2
8 4852535101 GRILL SPK R 1 EGI TO.5
7 4857923300 DOOR LOCK 1 LA701(KIFCO)
29 4858213800 BAG POLY 1 PE FILM TO.06 250 350 6 4855617401 MARK BRAND 1 AL(SILVER)
28 4858215400 PE FILM 1 5 4855058201 DECO CTRL 1 PVC TO.3
27 6520010100 STAPLE PIN 12 18M/M JDO 4 4852820601 DOOR 1 PC SMOG
26 4858037300 BOX CARTON 1 DW-3 3 4856717900 SPRING 1 SWPA( 6.4 16 TO.5)
25 4858164200 PAD 1 EPS 2895 2 4854849201 BUTTON POWER 1 ABS BK
24 4855415800 SPEC PLATE 1 150ART P/E FILM 1 4852534901 GRILL SPK L 1 EGI TO.5
54
2898

22 7122401612 SCREW TAPPING 9 T2S TRS 4 16 MFZN C/B+M/F
21 4852148901 COVER BACK 1 HIPS BK
20 CRT 1
19 4856015700 SCREW CRT FIXING 4 SWRM+SK-5L=27
18 4856215402 WASHER RUBBER 4 CR
17 MAIN PCB AS 1 CP-775
16 4854934001 BUTTON 1 ABS BK
14 7121401611 SCREW TAPPING 20 T2S PAN 4 16 MFZN BRKT+M/F
13 4853414501 BRKT CRT 4 ABS NC
12 4853311601 RETAINER BACK 7 HIPS NC
11 4852062411 MASK FRONT 1 HIPS BK
10 7122401212 SCREW TAPPING 8 T2S TRS 4 12 MFZN SPK+M/F
9 SPK 2
8 4852535001 GRILL SPK R 1 PS SHEET TO.45
7 4857923300 DOOR LOCK 1 LA701(KIFCO)
29 4858213800 BAG POLY 1 PE FILM TO.06 250 350 6 4855617401 MARK BRAND 1 AL (SILVER)
28 4858215400 PE FILM 1 5 4855058201 DECO CTRL 1 PVC TO.3
27 6520010100 STAPLE PIN 12 18M/M JDO 4 4852820601 DOOR 1 PC SMOG
26 4858037300 BOX CARTON 1 DW-3 3 4856717900 SPRING 1 SWPA( 6.4 16 TO.5)
25 4858164200 PAD 1 EPS 2895 2 4854849201 BUTTON POWER 1 ABS BK
24 4855415800 SPEC PLATE 1 150ART P/E FILM 1 4852535000 GRILL SPK L 1 PS SHEET TO.45
55
25G1
56
29G1
57
2594
58
28G2
59
DTY-28G6
DTY-28G7
Electrical Parts List
Components marked with this symbol must only be replaced by a component having
identical physical characteristics.
LOC. PART-CODE PART-NAME PART-DESCRIPTION REMARK

ZAC10 PSACPW0069 ACCESSORY AS DTY-2896TAF
M821 4858211400 POLY BAG P.E FILM T0.03X600X550
10 47P7500001 BATTERY AAM 1.5V
10000 48586A1617 MANUAL INSTRUCTION ALL
ZBC10 PSBCSH0031 COVER BACK AS DTY-2896TF
M211 4852148901 COVER BACK HIPS BK
M541 4855415800 SPEC PLATE 150ART P/E FILM (C/TV)
M781 4857817611 CLOTH BLACK FELT T0.7 L=200
ZCA10 PSCACA0069 CABINET AS DTY-2896TAF
M211A 7122401612 SCREW TAPPING T2S TRS 4X16 MFZN BK
M251 4852534901 GRILL SPKR L EGI T0.5
M252 4852535101 GRILL SPKR R EGI T0.5
M281 4852820601 DOOR PC SMOG
M352 97P4602700 CLAMP CORD NYLON 66 BLK 5280N
M481 4854849201 BUTTON POWER ABS BK
M481A 4856717900 SPRING SWPA
M491 4854934001 BUTTON ABS BK
M501 4855058201 DECO CTRL PVC T0.3
M561 4855617401 MARK BRAND AL (SILVER)
M681 4856812001 TIE CABLE NYLON66 DA100
M791 4857923300 DOOR LOCK LA701(KIFCO)
P405 4850706S10 CONN AS 35135-06+HS30052+ULW=500
SP01B 7122401212 SCREW TAPPING T2S TRS 4X12 MFZN BLACK
SP01C 7122401212 SCREW TAPPING T2S TRS 4X12 MFZN BLACK
V901 4859622160 CRT A66EAK071X11
V901A 4856215402 WASHER RUBBER CR
V901B 4856015700 SCREW CRT FIX SWRM+SK5 L=27
ZFM10 PSFMSJ0031 MASK FRONT AS DTY-2896TF
M201 4852062401 MASK FRONT HIPS BK
M331 4853311601 RETAINER BACK HIPS NC
M341 4853414501 BRKT CRT ABS NC
M341A 7121401611 SCREW TAPPING T2S PAN 4X16 MFZN
ZMP10 PSMPMS0069 PCB MAIN MANUAL AS DTY-2896TAF
10 2193102005 SOLDER BAR SN:PB=63:47 S63S-1320
20 2193011101 SOLDER WIRE RS 60-1.2 1.6A
30 2291050615 FLUX SOLDER DF-2012U
60
40 2291050301 FLUX SOLVENT IM-1000

60 2224050026 BOND SILICON RTV 122 CARTRIDGE
90 2291051001 FLUX KILLER KFT-7
C302 CEYD1H689W C ELECTRO 50V RHD 6.8MF (16X35.5)
C402 CMYH3C722J C MYLAR 1.6KV BUP 7200PF J
C404 CMYH3C472J C MYLAR 1.6KV BUP 4700PF J
C408 CMYE2G274J C MYLAR 400V PU 0.27MF J
C417 CMYB2G472J C MYLAR 100V 0.1MF J (TP)
C666 CEXF1E102V C ELECTRO 25V RSS 1000MF (13X20) TP
C801 CL1JB3474M C LINE ACROSS AC250V 0.47MF U/C/SNDFIS
C805 CEYN2G181P C ELECTRO 400V LHS 180MF (25X35)
C821 CH1FFE472M C CERA AC 4.0KV 4700PF M KD AC250V
C965 CCYB3D102K C CERA 2KV B 1000PF K
D403 DBY228—— DIODE BY228 (TAPPING)
D404 DBYW95C—- DIODE BYW95C (TAPPING)
D707 DKLR114L— LED KLR114L
F801 5FSCB4022R FUSE CERA SEMKO F4AH 4A 250V MF51
G971 4SG0D00103 SPARK GAP S-23 900V-1.5KV
HP01 4859102130 JACK EARPHONE YSC-1537
I301 1TDA8351— IC VERTICAL TDA8351
I301A 4857024403 HEAT SINK AL EX
I301B 7174301011 SCREW TAPPTITE TT2 RND 3X10 MFZN
I501 1TDA8375A- IC VCD TDA8375A
I502 1TDA8395— IC TDA8395
I503 1TDA4665V4 IC DELAY TDA4665/V4
I601 1TDA1519B- IC AMP TDA1519B
I601A 4857026401 HEAT SINK AL EX (BK)
I601C 4856815900 CLAMP WIRE EGI T0.4+PVC COATING
I601D 7128261011 SCREW TAPPING T2S WAS 2.6X10 MFZN
I602 1MSP3410D- IC AUDIO MSP3410D
I603 1TDA4445B- IC TDA4445B
I604 1TDA4445B- IC TDA4445B
I700 1UPC574J— IC UPC574J
I701 1DW5255S1- IC MICOM DW5255S1
I702 124LC08B— IC MEMORY 24LC08B
61
I703 1TFMW5380- IC PREAMP TFMW5380
I801 1STRS5707- IC POWER STR-S5707
I801A 4857025403 HEAT SINK AL050P-H24 T=2
I802 1TDA8138— IC REGULATOR TDA8138
I802A 4857025401 HEAT SINK A1050P-H24 T2
I803 1KA7808—- IC REGULATOR KA7808
I901 1TDA6106Q- IC AMP TDA6106Q
JPA01 4859200401 SOCKET RGB SR-21A1 (ANGLE TYPE)
JPA02 4859200401 SOCKET RGB SR-21A1 (ANGLE TYPE)
JPA03 4859108450 JACK PIN BOARD YSC03P-4120-14A
LF801 5PLF24A1— FILTER LINE LF-24A1
L103 58C9780027 COIL CHOKE TRF-1201B (0.97 UH)
L109 58M38R9006 COIL DET TRF-1490
L110 58E0000S37 COIL AFT TRF-A001
L401 58H0000025 COIL H-LINEARITY TRL-330
L402 58C7070085 COIL CHOKE TLN-3062A
L802 58C9430599 COIL CHOKE AZ-9004Y(94MH)
M351 4853530901 HOLDER LED HIPS BK
M721 4857235402 SHIELD CASE SPTH-C T0.25
PWC1 4859903110 CORD POWER AS CW4232+BL102NG+TUBE=2500
A000 4859903511 CORD POWER CW4232 H03VVH2-F=2250
P401A 4850704S04 CONN AS YH025-04+YST025+ULW=400
P402 4859240120 CONN WAFER YFW500-06
P501A 4850706S02 CONN AS YH025-06+YST025+ULW=400
P801 4859242220 CONN WAFER YFW800-02
P802 4859242220 CONN WAFER YFW800-02
P903 4859238620 CONN WAFER YPW500-02
P904 4859275220 CONN WAFER YF254-05R (ANGLE)
Q401 T2SD1880— TR 2SD1880
Q401A 4857024500 HEAT SINK AL EX B/K
Q401B 7174300811 SCREW TAPPTITE TT2 RND 3X8 MFZN
Q403 T2SB546K— TR 2SB546-K
Q403A 4857024902 HEAT SINK AL EX
Q403B 7174300811 SCREW TAPPTITE TT2 RND 3X8 MFZN
R406 RF-2Y479J- R FUSIBLE 1/2 4.7 OHM J
R801 DEC140M290 POSISTOR ECPCC140M290
R819 RX10B339JN R CEMENT 10W 3.3 OHM J BENCH 4P
SCT1 4859302930 SOCKET CRT ISHS-09S
62
SF01 5PG3962M— FILTER SAW G 3962-M
SF02 5PG9251M— FILTER SAW G 9251-M
SF03 5PL9461M— FILTER SAW L 9461-M
SW801 5S40101143 SW PUSH PS3-22SP (P.C.B)
T401 50D19A1—- TRANS DRIVE TD-19A1
T402 50H0000181 FBT 1352.5008E
T802 50M0000101 TRANS SMPS 2094.0008C
U100 4859714430 TUNER VARACTOR 3303KHC-3X1289
X501 5XE4R4336E CRYSTAL QUARTZ HC-49/U 4.433619MHZ 30PPM
Z502 5PMKT40MA- FILTER CERA MKT40MA100P
ZMP10 PSMPJ20069 PCB CHIP MOUNT B AS DTY-2896TAF
CCA01 HCQK471JCA C CHIP CERA 50V CH 470PF J 2012
CCA05 HCFK103ZCA C CHIP CERA 50V Y5V 0.01MF Z 2012
CCA10 HCBK102KCA C CHIP CERA 50V X7R 1000PF Z 2012
CCA11 HCBK102KCA C CHIP CERA 50V X7R 1000PF Z 2012
CCA16 HCBK102KCA C CHIP CERA 50V X7R 1000PF K 2012
CC101 HCQK220JCA C CHIP CERA 50V CH 22PF J 2012
CC102 HCBK102KCA C CHIP CERA 50V X7R 1000PF K 2012
63
CC111 HCBK473KCA C CHIP CERA 50V X7R 0.047MF K 2012
CC501 HCFK104ZCA C CHIP CERA 50V Y5V 0.1MF Z 2012
CC529 HCQK100DCA C CHIP CERA 50V CH 10PF D 2012
CC532 HCBH224KCA C CHIP CERA 25V X7R 0.22MF K 2012
64
RCA02 HRFT473JCA R CHIP 1/10 47K OHM J 2012
RCA10 HRFT750JCA R CHIP 1/10 75 OHM J 2012
65
RC101 HRFT183JCA R CHIP 1/10 18K OHM J 2012
RC103 HRFT682JCA R CHIP 1/10 6.8K OHM J 2012
RC306 HRFT471JCA R CHIP 1/10 470 OHM J 2012
66
67
ZMP10 PSMPJ00069 PCB MAIN (RHU) AS DTY-2896TAF
C405 CMXE2G273J C MYLAR 400V PU 0.027MF J (TP)
C413 CEXF2C470V C ELECTRO 160V RSS 47MF (13X25) TP
C416 CCXB3D681K C CERA 2KV B 680PF K (TAPPING)
C806 CCXB3D102K C CERA 2KV B 1000PF K (TAPPING)
ZMP10 PSMPJB0069 PCB MAIN M-10 AS DTY-2896TAF
68
P101 485923162S CONN WAFER YW025-03 (STICK)
P702 485923182S CONN WAFER YW025-OF(STICK)
R407 RS02Z561JS R M-OXIDE FILM 2W 560 OHM J SMALL
R410 RS02Z223JS R M-OXIDE FILM 2W 22K OHM J SMALL
R700 RS02Z912JS R M-OXIDE FILM 2W 9.1K OHM J SMALL
R701 RS02Z912JS R M-OXIDE FILM 2W 9.1K OHM J SMALL
R804 RF02Z338J- R FUSIBLE 2W 0.33 OHM J (TAPPING)
R920 RF01Z129JA R FUSIBLE 1W 1.2 OHM J A CURVE
ZMP10 PSMPJR0069 PCB MAIN RADIAL AS DTY-2896TAF
CA10 CBXF1H104Z C CERA SEMI 50V F 0.1MF Z (TAPPING)
CA11 CCXF1H473Z C CERA 50V F 0.047MF Z (TAPPING)
C102 CEXF1H479V C ELECTRO 50V RSS 4.7MF (5X11) TP
C104 CEXF1H100V C ELECTRO 50V RSS 10MF (5X11) TP
C105 CMXM2A104J C MYLAR 100V 0.1MF J (TP)
C111 CEXD1H109F C ELECTRO 50V RND 1MF (5X11) TP
C301 CMXM2A223J C MYLAR 100V 0.022MF J TP
C411 CEXF2C229V C ELECTRO 160V RSS 2.2MF (8X11.5)TP
C501 CCXF1H473Z C CERA 50V F 0.047MF Z (TAPPING)
C504 CEXF1E101V C ELECTRO 25V RSS 100MF (6.3X11) TP
69
C509 CMXL2E104K C MYLAR 250V MEU 0.1MF K
C601 CXCH1H680J C CERA 50V CH 68PF J (TAPPING)
C602 CEXF1H470V C ELECTRO 50V RSS 47MF (6.3X11) TP
C706 CMXB1H224J C MYLAR 50V EU 0.22MF J (TP)
70
C803 CCXF3A472Z C CERA 1KV F 4700PF Z (T)
C804 CCXF3A472Z C CERA 1KV F 4700PF Z (T)
C807 CCXB3A471K C CERA 1KV B 470PF K (T)
C808 CEXF2A100V C ELECTRO 100V RSS 10MF (6.3X11) TP
C809 CCXB3A471K C CERA 1KV B 470PF K (T)
C811 CEXF1E221V C ELECTRO 25V RSS 220MF (8X11.5) TP
C812 CEXF1E221V C ELECTRO 25V RSS 220MF (8X11.5) TP
F801A 4857415001 CLIP FUSE PFC5000-0702
F801B 4857415001 CLIP FUSE PFC5000-0702
QA01 TKTA1266Y- TR KTA1266Y (TP)
QA02 TKTC3198Y- TR KTC3198Y
QA03 TKTC3198Y- TR KTC3198Y
Q301 TKTC3198Y- TR KTC3198Y
Q402 T2SD1207T- TR 2SD1207-T (TAPPING)
Q406 TKTA1266Y- TR KTA1266Y (TP)
Q604 TKTC3197— TR KTC3197 (TP)
71
Q711 TKTC3202Y- TR KTC3202Y (TP)
SW700 5S50101090 SW TACT SKHV17910A
ZMP10 PSMPJA0069 PCB MAIN AXIAL AS DTY-2896TAF
A001 4859801393 PCB MAIN 330X246 D1B
DA01 D1N4148—- DIODE 1N4148 (TAPPING)
DA02 DMTZ5R6B— DIODE ZENER MTZ 5.6-B(TAPPING)
DA03 DMTZ12C—- DIODE ZENER MTZ-12C
D101 D1N4148—- DIODE 1N4148 (TAPPING)
D301 DMTZ220—- DIODE ZENER MTZ 22-D
D302 DUZ5R1BM— DIODE ZENER UZ-5.1BM
D405 D1N4936GP- DIODE 1N4936GP (TAPPING)
D407 DBYV95C—- DIODE BYV95C (TAPPING)
D501 DMTZ5R1B— DIODE ZENER MTZ 5.1-B (TAPPING)
72
D506 DUZ5R1BM— DIODE ZENER UZ-5.1BM
D601 D1SS85TA- DIODE 1SS85TA
D602 D1SS85TA- DIODE 1SS85TA
D708 DMTZ5R6B— DIODE ZENER MTZ 5.6-B(TAPPING)
D801 D1S1888—- DIODE 1S1888 (TAPPING)
LA01 5CPZ109M04 COIL PEAKING 1UH 10.5MM K (LAL04TB)
LA10 5CPZ100K04 COIL PEAKING 10UH 10.5MM K (LAL04TB)
LA12 5CPZ100K04 COIL PEAKING 10UH 10.5MM K (LAL04TB)
L101 5CPZ470K02 COIL PEAKING 47UH K (AXIAL 3.5MM)
L301 5CPZ100K04 COIL PEAKING 10UH 10.5MM K (LAL04TB)
L601 5CPZ479K02 COIL PEAKING 4.7UH K (AXIAL 3.5MM)
L606 RD-4Z102J—- R CARBON FILM 1/4 IK OHM J
73
L804 5MC0000100 COIL BEAD MD-5 (HC-3550)
RA01 RD-4Z101J- R CARBON FILM 1/4 100 OHM J
RA05 RD-4Z103J- R CARBON FILM 1/4 10K OHM J
R301 RD-4Z472J- R CARBON FILM 1/4 4.7K OHM J
R302 RD-2Z129J- R CARBON FILM 1/2 1.2 OHM J
R303 RD-2Z129J- R CARBON FILM 1/2 1.2 OHM J
R304 RD-2Z220J- R CARBON FILM 1/2 22 OHM J
R333 RD-4Z302J- R CARBON FILM 1/4 3K OHM J
74
R818 RC-2Z565J- R CARBON COMP 1/2 5.6M OHM J
R913 RC-2Z332J- R CARBON COMP 1/2 3.3K OHM J
R917 RD-4Z105J- R CARBON FILM 1/4 1M OHM J
Z502 5PMKT40MA- FILTER CERA MKT40MA100P
ZSP10 PSSPPW0069 SPEAKER AS DTY-2896TAF
P601A 4850704N10 CONN AS YH025-04+YST025+ULW=700
SP01 4858313010 SPEAKER SP-58126F03
ZCG10 48519A5510 CRT GROUND AS 2801H-1015-2P
ZDC10 58G0000103 COIL DEGAUSSING DC-2701
ZPK10 PSPKCP0069 PACKING AS DTY-2896TAF
M641 6520010100 STAPLE PIN 18M/M J D O
M801 4858037300 BOX CARTON DW-3
M811 4858164200 PAD EPS 2895
M822 4858215400 BAG P.E PE FILM
ZTR10 48B3228B03 TRANSMITTER REMOCON R-28B03
75
ENGINEER NOTE
DAEWOO ELECTRONICS CO., LTD.
686, AHYEON-DONG, MAPO-GU,
SEOUL, KOREA.
C.P.O. BOX 8003 SEOUL KOREA
TELEX : DWELEC K28177-8
F A X : (02) 364-5588,5305
T E L : (02) 360-7360 4, 7315 7
S/M NO : CP775P-011 PRINTED DATE: DEC. 1997

CP-775 CHASSIS SCHEMATIC DIAGRAM
52
WAVE FORMS
53

Daewoo Cp775 2594st, 2896st, 2898st, 28g2st, 25g1st, 29g1st SM

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Daewoo Cp775 2594st, 2896st, 2898st, 28g2st, 25g1st, 29g1st SM

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Service Manual

59 / 66 Cm STEREO Colour Television

MODEL :2594ST / 2896ST

CRT 25” : A59EAK071X11 (PHILIPS)

PIN Signal Designation Matching Value

X-RAY RADIATION PRECAUTION

PRODUCT SAFETY NOTICE

1.1 Standard B/G,D/K,I and L

1.2 Standard SECAM-L’ (France VHF-Low)

6.1 VERTICAL CENTER

6.2 VERTICAL SIZE

6.3 VERTICAL SLOPE

6.4 VERTICAL S-CORRECTION

6.5 HORIZONTAL CENTER

The initial state of adjustment are as follows; Service Remocon

28TAF 28TUF 28TFF

AGC 11 9 10 VOL VOL

V-SIZE 52 54 52 MIN MAX

MAX MAX MAX

CONT BRI COL

MIN MIN MIN

V- CENTER V- SIZE V- SLOPE S-COR. SUB BRI.

REMOTE CONTROLLER R-30SVC

PIF SWEEP MAKER (LSW-480) OSCILLOSCOPE

TP1 (TUNER IF) TP2 (I603 #12)

TP3 (TUNER B+) TP3 (I603 #3)

DC POWER SUPPLY DC POWER SUPPLY

- Connection For SIF Adjustment -

DW5255S*(Micro-controller & West/East Teletext Decoder)

(3) Block Diagram

26 FIL2 FIL2 PLL Loop Filter I/O for TTX Slicing

(3) Block Diagram

D OUT SENSE AMPS

SEL STATE COUNTERS

(4) Pin Description

PIN SYMBOL DESCRIPTION

(1) General Description

The nominal supply voltage is 8V. With min/max values of 7.2-8.8V.

(2) General Description

(4) Pin Description

(3) Block Diagram

CLOCHEref PLLref GND

BANDGAP TUNING TUNING

CVBS 16 CLOCHE DE-

(4) Pin Description

(3) Block Diagram

(4) Pin Description

PIN SYMBOL DESCRIPTION

(3) Block Diagram

(4) Pin Description

PIN SYMBOL DESCRIPTION

(3) Block Diagram

(4) Pin Description

PIN NAME SYMBOL DESCRIPTION

Electrical Characteristics of Power Transistor Part(Trl) (Ta=25 )

(3) Block Diagram (4) Pin Description

PIN SYMBOL DESCRIPTION

(3) Block Diagram (4) Pin Description