ISSN 2347 - 3983

Volume 9. No. 6, June 2021

International
Soham Bhattacharya Journal
et al., International ofofEmerging
Journal Trends
Emerging Trends in Engineering
in Engineering Research, 9(6), Research
June 2021, 806 – 814
Available Online at http://www.warse.org/IJETER/static/pdf/file/ijeter28962021.pdf
https://doi.org/10.30534/ijeter/2021/28962021

A Review on Reversible Computing and it’s applications on

combinational circuits
Soham Bhattacharya1, Anindya Sen2
1,2
Heritage Institute of Technology, Kolkata, West Bengal, India,
Department of Electronics and Communication Engineering.
1
[email protected]
2
[email protected]

ABSTRACT the question that why computers use most energy. From the
Thermodynamics concept, he proposed that the amount of
In this era of nanometer semiconductor nodes, the transistor energy dissipated for every irreversible bit operation is at
scaling and voltage scaling are not any longer in line with least KTln2 joules, where, K denotes the Boltzmann’s
each other, leading to the failure of the Dennard scaling. constant and T denotes the absolute temperature at which
Thus, it poses a severe design challenge. Reversible operation is performed. This is known as the ‘Landauer
computing plays a vital role in applications like low power Principle’. A circuit is alleged to be reversible if the input is
recoverable from the output. Reversible computing holds up
CMOS, nanotechnology, quantum computing, optical
for each forward and backward movement method in concert
computing, digital signal processing, cryptography,
generates inputs from the outputs. The primitive combinable
computer graphics and many more. The primary reasons for logic circuits scatter energy for all of data that's lost
designing reversible logic are diminishing the quantum cost, throughout the activity. This can be as a result of per the
profundity of the circuits and the garbage outputs. It is actual fact of second law of thermodynamics; data once lost
impossible to determine the quantum computing without cannot be recovered by any methods. In 1973, Bennett[4]
implementing the reversible computation. This paper will showed that circuits built using reversible logic gates
represent the literature survey based on several papers on escaped the energy dissipation problem.
combinational circuits using reversible computing and also
the future scope is to be discussed. In the online Conference of Physics and Engineering Issues
in Adiabatic/Reversible Classical Computing (October 5-9,
Key words: Logic circuits, Reversible logic, Garbage 2020), it had been proclaimed that need for reversible
outputs, Quantum cost, Constant Input, Hardware computing has become widely recognized. Today’s
Complexity. approach towards general digital computation based on
standard combinational and sequential digital architectures
1. INTRODUCTION: constructed out of standard (irreversible) Boolean logic
elements implemented using CMOS (complementary
As the transistors get smaller, the power density of those metal/oxide/semiconductor) transistor technology, is
transistors remains constant so that the used power is approaching fundamental cut-off points to additional
proportional with area and this law is called as Dennard’s enhancements for its energy effectiveness and power-limited
Scaling or MOSFET scaling. performance. The final (2015) edition of the International
Dennard's scaling failed mainly due to the fact that supply Technology Roadmap for Semiconductors (ITRS),
voltage remained constant but the power densities furthermore recent editions of its successor roadmap, the
subsequently increase on the chip. Therefore, a major International Roadmap for Devices and Systems (IRDS),
quantity of on-chip resources has to stay in power-gated suggest that a sensible limit will be reached by round the
situation, so as to avoid thermal emergencies. In this year 2030. By the end of the CMOS roadmap, logic signal
scenario, transistor and voltage scaling don’t seem to be in energies at the gate of a minimum-sized transistor basically
line with one another [1]. In recent years, reversibility cannot diminish a lot further without crossing paths of
assumes a major role when computations with least energy fundamental limits on efficiency and stability arising from
dissipation are examined. The primary reason for conspiring thermal fluctuations. Even moving to “Beyond CMOS”
reversible logic is to cut back the number of reversible gates, switching devices cannot improve this situation
garbage outputs, constant inputs, area, power, delay, and considerably, since identical elementary thermodynamic
quantum cost and hardware complexity of the reversible limits still continue to apply.
circuits. In 1991, Landauer [2, 3] proposed the answer for Hence, there is an expanding need to investigate new
fundamental standards for the designing execution of general
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computing systems (at all scales from tiny embedded 2. THE CONCEPT
devices to large-scale supercomputers and data centres) in
search of novel ideas for computation which will transcend Reversibility in computing gives the idea that the
the above limits that are inherent to the standard irreversible information about computational states can never be lost and
digital paradigm. The area of ideas that have been be used when needed. Logical reversibility is the process in
contemplated include a diversity of concepts for “physical” which any early stage can be recovered in computing
computing (computing that leverages fundamental physics to backwards or un-computing the results. Physical
do computing in a very additional direct approach than in the reversibility is referred to no energy dissipation of heat.
traditional digital paradigm), including numerous analog and After Physical, logical reversibility is achieved [5]. The most
stochastic computing ideas likewise, quantum computing prominent application of reversible computing stays in
(for issues amenable to quantum speedups). quantum computing. Quantum networks comprise of
quantum logic gates; each gate performs an elementary
Accordingly, we see the fundamental science and designing unitary operation on one, two or more two–state quantum
of reversible computers as being at present a very ready area systems, which are called qubits. Each qubit is
of focus for future large-scale federal research initiatives, for correspondent to the classical bit values 0 and 1. [6]
the following reasons: Reversible logic elements are utilized for recovering the
state of inputs from the outputs. An NXN reversible network
1. The reversible computing field is absolutely fundamental is represented as :
for there to be any expectation of propelling ordinary general Iv = (I1, I2, I3, ......... IN)
digital computing beyond the energy-efficiency limits that Ov = (O1, O2, O3, ...... ON)
apply to the conventional computing paradigm, which will Where, Iv and Ov clarifies the input and output vectors
definitely be reached in the near future. respectively. Figure 1 shows the symbol of reversible logic
gates with input and output vectors.
2. There is a spread of important foundational physical
science analysis within the reversible computing field that
might have the potential revolutionary impact that still must
be done.

3. This field has so far been forward-looking for the industry

to invest in directly, although at least one major industrial
Fig. 1 represents the symbol of Reversible logic gate with
research lab is presently considering starting up a project to
input and output vectors.
investigate the boundaries of computing, including
reversible computing.
3. BACKGROUND
4. To have designs with minimal power consumption for
By Moore’s Law, the number of transistors will be doubled
transistors has been recently dominated by the
for every eighteen months. For every eighteen months, it is
semiconductor industry as mandated by the growing
possible to create higher performance general purpose
electronic industry especially dominated by cell phone. On
processors. In 1980, Toffoli[7] stated that utilizing invertible
the other hand the requirement for more dense transistors as
logic gates, it is feasible to create a sequential PC with zero
per Moore’s law continues to rise.
internal power dispersal preferably. The basis of heat
dissipation are as follows: Increase in the number of
The 8086 microprocessors had fewer than 30,000
transistors on chip.[8], High Power dissipation leads to:
semiconductors, contrasted with current CPU and GPU's
Reduced time of operation, Reduced mobility and reliability,
which comprises of billions of semiconductors prompting
High efforts for cooling, Increasing operational costs.
complex administration of cost, and power. There are
billions of semiconductors on a chip; yet, those
Several parameters to determine the complexity and
semiconductors can't be utilized all the while. This reality
performance of circuits[9,10] are:
has had a major effect in how CPUs are planned, and this
A. The number of reversible gates (N).
issue will just increase later on. A processor which can
B. Constant inputs: Number of inputs which are to be
utilize just 5% of its transistors at some given time will
maintained constant at 0 or 1 for synthesizing the given logic
fluctuate with the processor which can utilize half of its
function.
semiconductors in a few attributes, primarily timing and
C. Garbage output: Number of unused outputs used
power [1], subsequently researchers are thinking about the
in the reversible gates. Garbage outputs are not avoidable as
utilization of reversible gates.
these are very essential to achieve reversibility. The

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following formula which is used to deterine the relation

between number of garbage outputs and constant inputs:
Input + Constant input = output + garbage output.
D. Quantum cost : Cost of the circuit with respect to
the cost of a primitive gate. Some properties of quantum Fig.4 shows functional block diagram of 2X2 Feynmann
cost: gate.
a. V*V = NOT
b. V*V+ = V+ *V = 1 The functional block diagram of 3X3 Double Feynmann
c. V+*V+ = NOT gate is illustrated in Fig. 5.
E. Hardware Complexity: It determines the number
of logic operations in the circuit. That means number of
AND, OR and EX-OR operations performed in the circuit.
F. Flexibility: It determines the universality of
reversible logic gate for realizing more functions.

For achieving an optimized reversible circuit, the following Fig.5 shows functional block diagram of 3X3 Double
points are needed to be considered: Feynmann gate.
 Minimum delay.
 Minimum garbage outputs. The functional block diagram of 3X3 Peres gate is illustrated
 Feedbacks/Loops are not considered. in Fig. 6.

4. SOME BASIC REVERSIBLE LOGIC

GATES

To implement the combinational circuits, the following Fig.6 shows functional block diagram of 3X3 Peres gate.
functional block diagrams of some basic reversible gates like
Not, Toffoli, Feynmann, Double Feynmann, Peres, Fredkin, The functional block diagram of 4X4 HNG gate is illustrated
HNG, TSG, DKG, NFT, RMUX1, TKS, BVF and TR are in Fig. 7.
shown below.

The functional block diagram of 1X1 NOT Gate is

illustrated in Fig. 2.

Fig.7 shows functional block diagram of 4X4 HNG gate.

Fig. 2 shows functional block diagram of 1X1 NOT gate.
The functional block diagram of 3X3 Fredkin gate is
The functional block diagram of 3X3 Toffoli gate is
illustrated in Fig. 8.
illustrated in Fig. 3.

Fig.3 shows functional block diagram of 3X3 Toffoli

gate.

The functional block diagram of 2X2 Feynmann gate is Fig.8 shows functional block diagram of 3X3 Fredkin gate.
illustrated in Fig. 4..
The functional block diagram of 4X4 TSG gate is illustrated
in Fig. 9.

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Fig. 13 shows functional block diagram of 3X3 TKS gate.

The functional block diagram of 4X4 BVF gate is illustrated

in Fig. 14.

Fig.9 shows functional block diagram of 4X4 TSG gate.

The functional block diagram of 4X4 DKG gate is illustrated Fig. 14 shows functional block diagram of 4X4 BVF gate.
in Fig. 10.
The functional block diagram of 3X3 TR gate is illustrated
in Fig. 14.

Fig. 10 shows functional block diagram of 4X4 DKG gate.

The functional block diagram of 3X3 NFT gate is illustrated Fig. 15 shows functional block diagram of 3X3 TR gate.
in Fig. 11.
5. A DETAILED ANALYSIS OF
COMBINATIONAL CIRCUITS USING REVERSIBLE
GATES

In 2012, the comparison between the reversible and

conventional logic gates had been showed [11]. The authors
collated the 4-bit reversible adder or subtractor circuit with
the help of DKG gate. The comparison is based on low
Fig. 11 shows functional block diagram of 3X3 NFT gate. power consumption, delay, and number of gates, garbage
outputs and constant inputs. The authors described that a 4x4
The functional block diagram of 3X3 RMUX1 gate is DKG gate can operate like a full adder and a full subtractor.
illustrated in Fig. 12.
In 2013, a work described how the Reversible BVF gate can
be useful to implement a one-bit reversible comparator [12].
The design is functional for the future computing techniques
like ultra low power digital circuits and quantum computers.
In [13], the authors proposed the transistor implementation
of the reversible gates could be done by using a combination
of CMOS-GDI circuit and TG Circuits, which provides the
optimal solution for combinational logic, saving one-third of
Fig. 12 shows functional block diagram of 3X3 RMUX1 the power, half the area and ten percentage in delay relative
gate. to a CMOS implementation. GDI circuits provide some
measure of enhanced hazard tolerance and are suited for low
The functional block diagram of 3X3 TKS gate is illustrated voltage operation mostly. The authors used the transistor
in Fig. 13. implementation of reversible gates by using Tanner tools
and H-spice tools. Moreover, the authors proposed the
design of GDI and TG based reversible comparator circuit in
90nm technology.

In 2014, the authors in [14] proposed the design of different

combinational circuits like serial adder, ripple carry adder,
half adder and multiplexer using a method of applications of
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reversible logic gates called as Quantum Cellular Automata of proposed reversible multiplexers with the existing one.
(QCA). The authors also gave the comparison of the The authors showed the quantum cost of 4:2, 8:3 and 16: 4
quantum cost of the proposed designs due to Coplanar reversible encoders is 8, 19 and 48 respectively. The
Architecture. A comparative table of various QCA structures presentation of all the encoders using RTL view and also the
like Half Adder, Full Adder, Ripple Carry Adder, 2:1 waveforms had been done.
Multiplexer, CDM and CSM were designed, simulated and
analyzed with respect to parameters like number of cells and In 2016, the authors in [21] proposed a tremendous
simulation time for the proposed coplanar based structure. reduction in power consumption and delay of the reversible
From the paper, it had been showed that the coplanar full adder circuits compared to the recently proposed one.
architecture had reduced number of cells and simulation The authors have designed the circuits using the 6T
time than the previous structure. The table also gave a clear (Transistor) approach. So, the number of transistors is also
review on the percentage of reduced area between previous reduced. Various voltages are applied to different
and proposed structures. Authors in [15] proposed that technologies such as 0.35um, 0.18um, 0.6um, for the
Reversible computing plays a vital role in Quantum designer to choose the better architecture for the required
computing had been described. The authors utilized the power dissipation and delay easily.
possibility of reversible logic to break the ordinary speed- The authors in [22] proposed a logarithmic depth quantum
power compromise, thereby getting a step closer to realise carry look ahead adder, which demonstrates two versions of
Quantum computing devices. Various combinational and addition namely in place and out-of-place method of
sequential circuits such as a 4-bit Ripple-carry Adder, (8-bit addition for n-bit numbers, but the design is not optimized in
X 8-bit) Wallace Tree Multiplier, and the Control Unit of an terms of gates, garbage outputs, quantum cost and
8-bit GCD processor using Reversible gates were used in the delay.
paper. The power and speed parameters for the circuits had The authors in [23] proposed a novel methodology for
been specified, and differentiated with their conventional reversible carry look-ahead adder, where presentation of
non-reversible peers. The comparative study that the circuits improved designs of both in-place and out of place designs
designed using reversible logic gates were much faster and of reversible carry look-ahead adder had been made.
power efficient. Simulations of the designs were done using Also, in 2016, the authors in [24] proposed the different
Xilinx 9.2 software. The authors in [16] described the design designs of ripple carry adder using Peres and HNG
of High speed low power reversible logic BCD adder which reversible gates. The modelling was done in Verilog HDL
was implemented using HNG gate. The design helped in and the functional verification and synthesis was created
reducing the number of reversible gates and also the cost of using Xilinx ISE. The authors also did a look up table for the
the circuit. Also, in [17], the VHDL implementation of delay calculation of the Conventional ripple carry adder and
Reversible Full Adder using a newly proposed Peres Gate reversible ripple carry adder using Peres and HNG gates
had been indicated. The authors found that the PERES full including gate count, garbage output and Quantum cost. The
adder is better than the irreversible full adder in terms of conventional ripple carry adder had a delay of 8.162ns,
garbage outputs. By using proposed PERES full adder, it whereas the reversible ripple carry adder using Peres and
was proclaimed that a design of large reversible systems can HNG gates were of 7.798ns and 7.644ns respectively. So,
be done and from there, the power consumption can be from the comparative table presented by the authors, it is
calculated and can be compared with the irreversible full seen that the reversible ripple carry adder using HNG gate
adder. A proposition in [18] of a modified Fredkin gate can had lesser delay in terms of the other two designs.
be utilized for implementing different types of reversible
multiplexers such as 2:1, 4:1, 8:1 and 16:1 reversible In 2017, the authors in [25] proposed that different
multiplexers. The authors gave a comparison between combinational circuits such as half adder, full adder, full
quantum cost and power consumption of proposed reversible subtractor, multiplexer, comparator and decoder can be
multiplexers with existing one. implemented using reversible logic gates. The authors
In 2015, the authors in [19] presented a comparative study of proposed a reversible decoder using Fredkin gate with
efficacy of various reversible full adder and reversible full minimum quantum cost. A comparative chart in line with
subtractor gate and their quantum cost values for obtaining quantum cost, garbage outputs, and number of gates was
energy efficient logic design. The article also gave a novel also presented. The circuit had been implemented and
design approach for implementing reversible combinational simulated using Xilinx software. The authors also delivered
circuits using the existing as well as newly improved the design of Programmable Read Only Memory (PROM)
reversible logic gates, in which the design and the using reversible decoder on Field Programmable Gate Array
implementations were done using HDL language called as (FPGA – SPARTAN 3E) which had less heat dissipation and
Verilog. low power consumption in [26]. The circuit was designed in
In [20], the authors proposed different types of reversible terms of quantum cost, garbage outputs and number of gates.
encoders such as 4:2, 8:3 and 16:4, using Feynman and In the same year, proposition of the design of 2:4 decoder
Fredkin gate. They were also compared with quantum cost using CMOS BSIM4 model had been showed [27]. The
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designed circuit was implemented using Tanner EDA tools subtractor, complex adders, parity generators, multiplexers
and the paper also gave a clear review on garbage outputs, and decoders using Toffoli, HNG, NFT and Fredkin gates
quantum cost, and constant inputs. [34, 35]. Moreover, several implementations of reversible
gates have been done using VHDL in 2012 [36], where the
In 2018, the authors in [28] presented some of the authors proposed that reversible logic is of substantial
combinational as well as sequential circuits using Xilinx significance. In [37], the authors presented that the
ISE. The authors also gave a clear comparison based on reversible circuits are designed using parity preserving gates,
power supply, delay and temperature etc of the reversible which contains the property of detecting not more than a
circuits with respect to conventional circuits. single error in the circuit's primary output. The authors
A presentation of the comparison of different reversible presented the design and FPGA synthesis of optimized data
logic at two subsequent levels i.e. gates structural level and selectors. The low switching power consumption
circuit design level, to provide a better solution for designing characteristics of data selectors, which were typically around
logic circuits had been expressed [29]. From the paper, it is 1 to 3μW that finds its use in low power applications, which
known basic gates are 50% efficient at gate level and 33% at are targeted ultra-speed, had been highlighted by the authors.
design level analysis in terms of gate cost, as compared to The authors in [38] proposed a new reversible ternary full-
the most efficient gates proposed in the literature. adder which is called as ‘comprehensive reversible ternary
Moreover, in 2018, the authors in [30] proposed a novel full-adder’, using the ternary logic capabilities over binary
approach to design n-bit arithmetic circuit with reversible logic capabilities. Using the two proposed reversible circuits,
design approach. The authors also presented a comparison the authors introduced a new reversible full adder or full
table in terms of number of reversible gates, number of subtractor. The comparison table displayed there are lower
garbage outputs and number of constant inputs applied for quantum costs in case of the proposed circuits than the
the existing and proposed 1-bit arithmetic circuit, which is a previous circuits.
vital component for ALU applications. The design was
simulated and synthesized using Xilinx Software. The In 2021, author in [39] proclaimed a metric to measure the
authors in [31] proposed a novel approach for the Reversible energy-efficiency of integrated circuits known as Q-Factor
realization of 3:8 size decoder circuits with optimized (a dimensionless parameter). Q = 1 is meant to be all energy
performance parameters as compared to the earlier designs. input will be dissipated as waste heat, whereas, Q >1 is
The comparison had been done with respect to total number meant to be of greater energy efficiency. The author gave a
of Reversible logic gates, constant inputs, garbage outputs clear table of Q- factor for conventional Business as Usual
and quantum cost. The design is efficient for low power (BAU) semiconductor nodes and Reversible Adiabatic-
applications. CMOS nodes and beyond. The comparison table for
transportation to IC technology with the actual energy
In 2019, the authors [32] proposed Half Adder, Half efficiency was given. In case of transportation, the actual
Subtractor and Full Adder circuit using TSG, HNG and energy efficiency was 20 percent and that of IC Technology
Peres gates respectively. The authors gave a clear is of 0 percent, as portrayed by the author.
comparison on the Propagation Delay and also the on-chip
power dissipation of the given circuits. The author proposed The below comparison table shows the analysis of the
from the comparison table that in case of low Power mostly used reversible gates for designing various
dissipation, 4X4 reversible Full Adder using HNG gate and combinational circuits based on some of the research articles
4X4 reversible Half Subtractor and 4X4 reversible Half utilized.
Adder using TSG gate as the best. In terms of Delay, for
designing reversible 4X4 Full Adder, HNG gate for lesser
delay and TSG gate for 4X4 reversible Half Subtractor and
4X4 reversible Half Adder are the best for designing these Combinational Circuits Number Names of
combinational circuits. The authors in [33] portrayed the of the
reversible logic cryptography design (RLCD) and using Reversible Reversible
which the encryption and decryption architecture had been Gates Gates
designed. The application specified integrated chip (ASIC) Used
and field-programmable gate array (FPGA) performances 1. Half Adder 1 Peres Gate
were evaluated for both existing and proposed method. 1 HNG Gate
ASIC performances which were more than 7% had been 2. Full Adder 1 Peres Gate
improved in RLCD-LFSR method compared to the 1 HNG Gate
conventional methods. 1 TSG Gate
1 DKG Gate
Moreover, in 2020, the authors gave a clear implementation 3. Half Subtractor 1 TSG Gate
along with the comparison table of the design of full
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3 2 CNOT numerous advantages over conventional gates such as, low

gates & 1 power, low complexity, less delay, high speed etc.
Toffoli Reversible computing has become a new emerging area for
Gate. researchers in recent years in fields like Quantum
4. Full Subtractor 3 1 HNG
Computing, Nanotechnology, Low Power CMOS Design
Gate, 1
Fredkin and many more [40, 41, 42, 43].
Gate & 1
Feynmann ACKNOWLEDGEMENT:
Gate
We would like to thank the whole Electronics and
1 DKG Gate
5. Decoder (2:4) 6 4 Toffoli Communication Department and the VLSI Department
Gates and faculties for their immense support with the Laboratory
2 NOT equipment and software. We would also like to express
Gates gratitude to our families for supporting throughout the
3 Fredkin research.
Gates
6. Multiplexer 1 NFT Gate
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