Rapport 2:VHDL: Réalisé Par: RAIS Aya LAZREK Ghita
Rapport 2:VHDL: Réalisé Par: RAIS Aya LAZREK Ghita
Rapport 2:VHDL: Réalisé Par: RAIS Aya LAZREK Ghita
Additionneur 4 bits
library ieee;
use ieee.std_logic_1164.all;
entity add_simple is
port (a,b,cin:in std_logic;s,cout:out std_logic );
end add_simple;
architecture add_s of add_simple is
begin
s<=a xor b xor cin;
cout <= (a and b) or ((a xor b) and cin );
end add_s;
transcodeur bcd
begin
nb<= not(b)+1;
'0';
entity comparateur is
port (A,B:in std_logic_vector(3 downto
0 );egale,sup,inf:out std_logic);
end comparateur;
architecture architect of comparateur is
begin
egale <='1' when A=B else '0';
inf <='1' when A<B else '0';
sup <='1' when A>B else '0';
end architect ;
compteur arduino 16
Registre à décalage d'un bit
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity regist_decal_1bit is
port(horloge,entree : in std_logic;
sortie: out std_logic_vector(7 downto 0));
end regist_decal_1bit;
architecture arch_regist_decal_1bit of
regist_decal_1bit is
signal data : std_logic_vector(7 downto
0):="11110000";
begin
process(horloge)
begin
if horloge='0' then
data <= entree& data(7 downto 1);
end if;
end process;
process(data)
begin
sortie<=data;
end process;
end arch_regist_decal_1bit;
soustracteur 4 bits
Réalisation d'une bascule JK
library ieee;
use ieee.std_logic_1164.all;
entity bas_jk is
port (J,K,H:in std_logic;
S:out std_logic );
end bas_jk;
architecture comp_bascule_jk of bas_jk is
signal mise:std_logic:='1';
begin
process(H,J,K)
begin
if (H='1') then
if (J='0' and K='0') then mise<=mise;
elsif (J='0' and K='1') then mise<='0' ;
elsif (J='1' and K='0') then mise<='1';
else mise<= not mise ;
end if;
end if;
end process ;
S<=mise;
end comp_bascule_jk;