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Content is final as presented, with the exception of pagination.

Evaluating Megawatt-Scale
Smart Solar Inverters
A COMMISSIONED 2.5-MW dc SUPPLY FOR TESTING GRID-TIE INVERTERS

xxxxxx

By Jesse Leonard, Ramtin Hadidi, J. Utility-scale photovoltaic (PV) plants often

Curtiss Fox, Thomas Salem, Benjamin use megawatt-scale central inverters with high efficiency
Gislason, and Mark H. McKinney and power density. Inverter manufacturers now offer solu-
tions of more than 2 MW for 1,000-Vdc-class PV arrays;
however, certifying inverters at this power level can pres-
Digital Object Identifier 10.1109/MIAS.2017.2740461
ent test equipment design and procurement challenges,
Date of publication: 18 June 2018 particularly with new interconnection requirements such as

2 IEEE Industry Applications Magazine œ september/october 2018 1077-2618/18©2018IEEE

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California Rule 21. dc supply must be able to remain online through all these
This article describes a retrofit of an existing medium- ac side events and not trip offline during the course of
voltage, nine-level Taiwan Electric Company (TECO)- each test. Because many of these tests involve the inverter
Westinghouse VersaBridge series-connected H-bridge tripping offline from full power, the dc supply must be
(SCHB) inverter to supply isolated dc power up to 2,500 A able to accommodate load rejections without long-term
at 1,000 Vdc for central inverter testing with reconfigura- effects. Additional features were added to this design to
tion options for 1,500-Vdc systems. Special attention was help with output overvoltage mitigation during these large
given to load rejection capabilities because the desired load rejection events.
tests involved fast inverter transitions from full power to Commercial, off-the-shelf power electronic grid simula-
zero power. Simulations in PLECS and controller hard- tors and dc supplies are available for low-power applica-
ware-in-the-loop experiments with the RTDS simulator tions but difficult to acquire at megawatt scale [4]. At our
were used for initial controller design. The existing SCHB facility, a high-power grid simulator using SCHB invert-
phase-shifted, pulsewidth modulation (PWM) scheme for ers from TECO-Westinghouse Motor Company has been
series multilevel topology led to a four-phase interleaved developed using four modular power amplifier units
output stage topology in a six-parallel module configura- (PAUs) [5]–[7]. To reduce the costs of adding dc supply
tion without any modifications to the existing VersaBridge capability for inverter testing, a retrofit approach was cho-
controller. Commissioning results are shown along with sen rather than a commercially available solution. An out-
experimental results for the first inverter test article at put stage for one PAU was designed to supply dc power,
2,500 A, 900 V. thus for allowing testing of high-power PV inverters [8].
The first priority was to focus on 1,000-Vdc-class inverters
California Rule 21 in the range of 2.5 MW, with provisions to reconfigure the
Grid integration testing for PV inverters typically involves supply to accommodate the next generation of 1,500-Vdc-
a simulated grid and a dc source. These two systems class PV inverters. The motivation for such a large supply
enable suites of tests, such as those described in UL Stan- is driven by grid integration testing of large central invert-
dard 1741 [1] and IEEE Standard 1547 [2], to be performed ers near 2 MW [9], [10]. Using only one of the PAUs to
on the PV inverter to obtain certification. The latest revi- power the dc supply leaves the other three available for
sion of UL Standard 1741 Supplement A includes voltage operation as an emulated ac grid to which the inverter
and frequency ride-through tables from California Rule output can be connected.
21 [3] (hereinafter referred to as Rule 21) as an example of
testing to an interconnection standard or source require- Retrofit Design Approach with Interleaving
ment document. Frequency ride-through requirements One major goal of the design was to leverage as much
in Rule 21 widen the frequency range within which existing equipment as possible to limit costs and required
an inverter must maintain operation. If the frequency floor space and, most importantly, also to reduce soft-
remains outside the threshold beyond the trip time, ware development and verification testing. This led to a
the inverter must trip as usual. The only difference this design that used one of four existing amplifiers, with an
can cause for a dc supply during testing, compared to a additional output stage to be housed in cabinets adjacent
conventional source requirement, is that the inverter is to the amplifier. Using this approach also allowed the
permitted to reduce its real power output to the point of integration of data acquisition and control with the exist-
ceasing if the frequency reaches 61.5 Hz (or some other ing facility system (as opposed to a commercial solution,
mutually agreed frequency value) [3]. which would likely have required more involved integra-
More drastic differences in comparison to IEEE Stan- tion with proprietary software) [8].
dard 1547-2003 are in the voltage ride-through section
of Rule 21. These differences have since been reconciled Existing Series-Connected H-Bridge Inverter
in the newly published IEEE Standard 1547-2018 revision Four Versabridge PAUs from TECO-Westinghouse were
with Category III ride-through tables. For low-voltage previously commissioned at our facility to act as a grid
conditions, inverters must remain in operation down to simulator. Each PAU has two nine-level SCHB inverters
0.5 per unit (p.u.) ac voltage. This mandatory operation broken up into eight slices with four isolated, series-
is defined as >80% of predisturbance current. Compared connected cells (i.e., power cubes) for each of its three
to the inverter tripping offline, this fast, transient event phases, as shown in Figure 1. Cubes A1, B1, and C1 are
can cause a near-50% load reduction within the inverter the phase output terminals of inverter 1, with the negative
response time, followed by a load increase back to nomi- pole of cubes A4, B4, and C4 tied to neutral. Inverter 2
nal in the same amount of time. If a grid voltage condi- consists of cubes 5–8 parallel to inverter 1, with cube 5 as
tion below 0.5 p.u. occurs, the inverter must momentarily the output terminal. The power cubes have a three-phase
cease but not trip, i.e., export <10% of the predisturbance boost rectifier to produce a regulated 1,000-Vdc link for
current. Additionally, if the grid voltage returns to normal, the output H-bridge, and all of the cubes’ insulated gate
then it must return to service within 2 s. In each case, the bipolar transistors (IGBTs) are 1,700-V, 600-A modules.

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Slice 8

Slice 7 A8

Slice 6 A7

Slice 5 A6

Slice 4 A5 B8

Slice 3 A4 B7

Slice 2 A3 B6

Slice 1 A2 B5 C8
Bridge A
A1 B4 C7
CA AB
4,160-V B3 C6
Input N
BC B2 C5
A
Bridge B
A B1 C4
CA AB
B C C3

B BC C2
C Bridge C
C1 N
CA AB

BC

FIGURE 1. The PAU topology with eight slices, three power cubes, and one transformer per slice. Output H-bridge series connections for ac
output mode are shown between slices 1–4 and 5–8. For the dc supply, these series connections are removed.

The cube dc link voltage set point can also be trimmed Phase-shifted PWM with double-edge sampling
through software up to 1,100 V without accelerated aging enables individual cube control using the existing PAU-
of the dc link capacitors. Cubes are connected in series grid simulator controller system. During previous tests
using modular copper bus bars located on the top of the of the PWM system, the series bus bar connections were
PAU cabinets. This modular slice approach allows easy removed from between the cubes, and the open circuit
access to the output of each set of cube terminals, which output voltages were measured [12]. The default PWM car-
is important for reconfigurability. rier frequency of each H-bridge is 600 Hz.
Figure 3(a) shows a proof-of-concept test that each
Phase-Shifted Carrier PWM H-bridge output (A1–A4) can be individually controlled,
The PAUs use phase-shifted, triangle-carrier PWM to gen- even though they share a common duty cycle from the
erate firing pulses for the H-bridges within a phase leg control packet. Simply by counting how many 12-kHz
[11]. The PWM method, which includes double-edge sam- packets have been sent and adjusting the duty cycle after
pling, has previously been experimentally validated [12]. an S/H occurs for a particular cube, a new duty cycle (and
The PAU control system includes a plastic optical fiber sign) can be sent to the next cube. Recall that all cubes
communication channel to allow external duty cycle input with the same prefix letter receive the same duty cycle
from a grid simulator controller at 12 kHz—sufficient for from the 12-kHz optical-fiber packets (carrying over from
the double-edge sampled 600-Hz carriers with 45° phase the original multilevel ac inverter controller architecture).
shifting. Figure 2 shows the four phase-shifted 600-Hz Considering the point in Figures 2 and 3(a) imme-
triangle carriers for the output H-bridges illustrating the diately prior to the S/H for cube A1, the duty cycle is
double-edge sampling points, denoted by S/H (i.e., sam- negative and of small magnitude. Immediately follow-
ple and hold), as well as vertical lines and asterisk mark- ing cube A1’s S/H, the dc supply controller increases the
ers showing the 12-kHz communication packet timing. duty cycle magnitude but remains negative and sends out

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this new duty cycle twice because

there are two 12-kHz control packets S/H S/H S/H S/H
between the S/H for cubes A1 and 1
A2. This is repeated two more times
for cube A3, now with three dupli-
0
cate packets, and for cube A4, with
two duplicate packets, resulting in
the four consecutive negative pulses –1
with increasing pulsewidth, as seen S/H S/H S/H S/H
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
in Figure 3(a). The sequence is then
Time (s) × 10–3
repeated, but with the sign toggled
to positive, which yields four con- Slice 1, 5 Slice 2, 6 Slice 3, 7 Slice 4, 8
secutive positive voltage pulses with
increasing pulsewidth. FIGURE 2. Phase-shifted 600-Hz carriers for double-edge sampled PWM, with each carrier
It is not likely that the dc supply shifted 45°; the 12-kHz optical fiber packet timing shown as vertical lines [12].
would need to change the amplitude
between four adjacent cubes within
one carrier period, as shown in the proof of concept. But
it does prove the maximum fidelity with which individual D0
D1
cubes can be controlled. More likely, the duty cycle will D2 12-kHz Sync
remain relatively constant until a grid-side test sequence Sign Toggle
VA1
commences and a large change in the dc supply is neces-
sary. Figure 3(b) shows the open circuit voltages on cubes
VA2
A1–A4 under a constant duty cycle amplitude but with
sign toggling still enabled for every tenth control packet,
i.e., 833 µs. VA3
This test also proved that no protection faults were
incurred by operating the PAU with the series bus bar VA4
connections removed from between cube outputs. This 1 kV/div
enabled the next stage of dc supply development for the
PAU, with the freedom to use all 24 cube outputs indi-
vidually with phase-shifted carriers already implemented. (a)

Interleaved Output Modules

Modular converter topologies like the series-connected
H-bridge inverter are made up of repeatable units, or VA1
cells. This multicell approach is the basis for many com-
mon converter topologies [13]. Interleaving PWM carriers VA2
between parallelized cells has the benefit of reducing
output voltage ripple [14], [15]. The design question here VA3
is how to take advantage of the 24 H-bridge outputs from
the existing system and create a new topology to serve
VA4
as a dc supply, ideally without major controller architec-
1 kV/div
ture changes to preserve maintainability and commonal-
ity with the other PAUs. This brings up the relationship
between phase-shifted PWM for both series-connected (b)
cells in multilevel topologies and for parallel connecting
cells in interleaved topologies.
FIGURE 3. An oscilloscope capture of open circuit voltages on cubes
Given that each cube has a 1,000-Vdc link, with a tun- A1, A2, A3, and A4 (channels 1–4, respectively). (a) A proof of
able set point up to 1,100 V, a buck topology is adequate concept for incrementing a magnitude duty cycle with sign toggling
for the 100–1,000-V output voltage range desired. A enabled [12] and (b) a case where the duty cycle magnitude is
­unidirectional supply is also sufficient for inverter test- constant with sign toggling enabled. Sync: synchronization.
ing, which broadens the design possibilities and allows
for additional thermal balancing of the H-bridge IGBTs. was made to create six parallel PAU output modules, each
Because the cubes are already grouped into sets of four supplied by four cubes, as shown in Figure 4. As Figure
in terms of the PWM phase shifting, a design decision 5 illustrates, each of the six output modules is housed in

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a separate cabinet. The topology of

Module 6: C5–C8 +
the output modules (Figure 4), has
Module 5: B5–B8 L5 five main components: ac line reac-
L1 Module 4: A5–A8 L5
DUT
tors, full-bridge rectifiers, a dynamic
L1 Module 3: C1–C4 C1 L5 –
Module 2: B1–B4
brake, a metal oxide varistor (MOV),
R1
L1 C1 L5 and an output choke.
L1 Module 1: A1–A4 C1 L5
R1
Parameters for each compo-
L1 L2 IC1
out L5 R1
L2 R1 nent are given in Table 1. The ac
L1 C1
L2 R1 line reactors used on each phase,
A1 V C1 V
L2 R1 i.e., L1–L4, limit the current slope
L2 L3 between the PAU and the dc supply
L2 L3 capacitors, given a 600-Hz PWM car-
A2 L3 rier frequency. The full-bridge diode
L3 rectifiers enable bipolar switching
L3 L4 of the PAU H-bridges and allow for
L3 L4 asymmetrical voltage pulses and
A3 L4
uniform thermal loading of the PAU
L4
output IGBTs. The dynamic brake,
L4
the IGBT shown in Figure 4 with a
L4
metal plate resistor R1, and the MOVs
A4
limit voltage rise during load rejec-
tion, a frequent event during grid
integration testing, particularly anti-
islanding testing, wherein multiple
FIGURE 4. The interleaved output stage module topology, with each stage having four inputs tests are performed back to back
from four power cubes. DUT: device under test. on the inverter from full power to a
tripped state.
The output choke, L5, serves multiple purposes. The
first is to improve passive paralleling of the six modules,
while the second is transient protection in the event
of a fault within the inverter under test and during the
close-in transition during inverter startup. The additional
inductance between the module dc capacitor and the
inverter bulk capacitors reduces inrush current during
the instance in which the inverter has dc contactors or
circuit breakers between the PV array cable terminals and
the internal inverter capacitors. If the dc supply module
capacitor were connected directly to the inverter, a very
large inrush current could result assuming that a voltage
imbalance were present at the close-in instance.
The dc supply is designed with an operating range
(a) of 100–1,000 Vdc. Over the majority of this range, the ac
current from each PAU cube is discontinuous. The wave
shape depends directly on the dc bus voltage of the dc
supply and the duty cycle of the quasi-square wave cre-
ated by the PAU. Figure 6 shows the ac current waveforms
for various dc bus voltages of the dc supply with respect
to the quasi-square wave input from each PAU cube. The
geometry of these waveforms is used to determine the
peak, the root mean square (rms) values, and dc output
current of the dc supply across most of the dc bus voltage
range. As the dc bus voltage approaches the low and high
(b) limits of its operating range, the ac current drawn from
the PAU cubes through the ac line reactor becomes quasi-
FIGURE 5. (a) A six-module output stage and (b) the cabinet interior. continuous under high loading currents, meaning there is
(Photos courtesy of Jesse Leonard.) no sustained zero current region of the period.

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Controller Architecture
The dc supply controller is based on a National Instru- Table 1. The output stage module components
ments (NI) reconfigurable input/output (RIO) architecture
Component Value
using a PXI (PCI eXtensions for Instrumentation) chassis.
A real-time operating system runs on an NI-8135 Intel- L1–L4 300 µH
based controller, and all time-critical feedback control is C1 4.6 mF
performed by a pair of NI-7842R multifunction RIO field-
L5 200 µH
programmable gate array (FPGA) cards that use Virtex-5
LX50 FPGAs and include analog-to-digital converters with R1 5Ω
signal conditioning to support eight analog inputs each. IGBTs Powerex CM200DX-34SA
An IEEE Standard 1588 precision time protocol card in Diodes Microsemi fast recovery diodes
the same chassis with PXI triggers allows the FPGA cards APTDF400AK120G
to timestamp control variables and analog measurements
for data logging, which are streamed to a RAID disk. This
approach allows for a high degree of time synchroniza-
tion across all of the channels [16]. The dynamic brake
IGBTs are controlled by one of the 7842R cards via plastic
Ipk Ls
optical fiber for firing pulses and gate-driver fault feed- Ls
Vac – Vdc
back. –Vdc

Feedback Controller and Protection

Feedback control for the dc supply is a traditional propor-
tional-integral  controller with a set-point reference and
output voltage feedback. One additional feature is an inte- D_Rise D_Fall
0 T/2
grator reset that improves load rejection performance and (a)
is conducted when a measured output voltage exceeds a
threshold above the reference. This is in conjunction with
dynamic brake control, which triggers a fixed 50% duty
Ipk
cycle if the output measurement exceeds 50 V above the Ls Ls
set point. The brake control also includes a time limiter Vac – Vdc –Vdc
for managing thermal load.
Each cabinet module’s output current and capacitor
voltage are measured along with the supply output volt-
age. This allows for individual cabinet overcurrent protec-
D_Rise D_Fall
tion performed in the FPGA cards. The combination of the 0 T/2
dynamic brake, output MOVs on each module, feedback (b)
controller considerations, and fast observability of each
module’s output current allows the supply to remain
online during an inverter under test load rejection, as well Ipk
as to trip offline in the event of catastrophic test article Ls
Ls
failure. –Vdc
Vac – Vdc

Commissioning Results
After the construction of each cabinet, component clear-
ances were double-checked, followed by high-potential
testing. All of the semiconductors were bypassed using D_Rise D_Fall
0 T/2
shooting wire, and the isolation-to-ground was checked (c)
using an ac high-potential test up to 4 kV. Next, cabinet
by cabinet, the dc capacitor was charged using an aux-
iliary power supply up to 900 V; the power supply was FIGURE 6. AC positive half-cycle current waveforms and quasi-
square wave pulses for various dc bus voltages: (a) a low dc bus
then removed, and the dynamic brake chopper was tested voltage, (b) a medium dc bus voltage, and (c) a high dc bus voltage.
to discharge the capacitor energy. After each cabinet
was tested, the final installation in the single-row lineup precommissioning. Full-power commissioning was com-
was completed, followed by reduced-scale power testing pleted in conjunction with a megawatt-scale PV inverter.
of individual modules. Due to the limited availability of
resistive load banks rated for 1,000 Vdc, this concluded

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were open-circuited for this test. Therefore, using Figure

3, only VA1 and VA3 were applied to the output module
for this test­—nearly identical to Figure 3, although with
IL1 IL3 slightly modified pulsewidths to reach 875 V, the limit for
Vdc the 3.8-Ω, 200-kW resistor bank. Recall the bipolar phase-
shifted voltage outputs of the cubes and the correspond-
ing bipolar interleaved currents, IL1 and IL3. Input inductor
currents reached the expected 200-A peak at an output of
875 V. Current sharing between the inductors is imperfect
because it is not actively managed by the control system;
100 A /div however, this is not expected to be an issue.
500 V/div
Final Commissioning with First PV Inverters
The first test article used with this supply was a 2-MW+
central PV inverter with an operating dc input range of
FIGURE 7. A module commissioning with two input phases 570–950 V. The manufacturer specified a nominal volt-
connected feeding a 3.8-Ω resistive load at 875 V. Line reactor age of 900 V for most testing conditions. The inverter
currents IL1 and IL3 are channels 1 and 2, and channel 3 is the output
voltage. was connected to the grid simulator with a step-up trans-
former, as shown in Figure 8. Nominal ac voltage at the
Reduced Load Two-Phase Commissioning medium-voltage terminals of the isolation transformer
To verify the air-cooling thermal solution for the module’s was 3,397 VLL.
full-bridge diodes, a modified commissioning procedure For the actual testing, the PAUs acted as both the PV
was performed twice on each module to thermally load array and the grid interconnect. PAU 2 and output mod-
the diodes. This approach ensured that the thermal paste ules 1–6 acted as the PV array (the dc supply), while PAUs
application had no major defects and no other component 3 and 4 were used in parallel to provide a simulated grid,
in the cabinet had unexpectedly high temperatures prior as shown in Figure 8. This configuration with a tunable
to running the full supply with a customer test article. 2.5-MW resistive, 2.5-MVA inductive, 2.5-MVA capacitive
This reduced-load thermal commissioning was load bank was used for UL Standard 1741 unintentional
achieved using a set of metal fin resistors arranged in islanding testing, as well as for abnormal grid conditions
series and parallel to obtain a nominal 3.8-Ω, 200-kW and ride-through testing without the RLC load bank con-
resistive load bank. Only two PAU cubes at a time were nected.
connected to a module so that two of the phases could be For the second phase of dc supply commissioning, a
fully loaded while requiring only a 200-kW resistive load. single module (this time with all four input phases) was
The diode-cooling solution was confirmed, and no case connected to the solar inverter and brought online with
temperature exceeded 60 °C. the dc supply regulating to 900 V. Data captures for the
Figure 7 shows the results of one of these two-phase dc breaker close-in sequence were logged without any
commissioning tests on a single output module using significant inrush current. This was due primarily to a
Rogowski coils to measure the line reactor currents, IL1 precharge sequence on the inverter, which waited for a
and IL3, along with the output voltage. Using Figure 4 as <15-V difference across the breaker before closure. Next,
a reference, the cabling between cubes A2, A4, and the the inverter was set to output 400 kW to finalize partial
output module were removed, i.e., terminals A2 and A4 supply commissioning. With regard to L1–L4 currents and
the respective diode bridges, the fol-
lowing applies. Viewed individually,
2.5-MW dc Supply this test was nearly identical to the
Output Smart PAUs 3 and 4 half-load 200-kW test using only two
PAU 2 Modules 1–6 Solar Inverter Isolation phases; although now, with all four
Transformer
phases, the output power capability
Circuit increases to 400 kW nominally, with
Breaker
some overhead margin.
The remaining five modules
were connected to complete the six-
RLC UI
parallel configuration shown in Fig-
Load Bank
ures 4 and 5(a), and the system was
brought up again with the inverter
FIGURE 8. A solar inverter test configuration with an ac interconnection to the grid simulator
and a dc input powered by the dc supply. An RLC load bank for subsequent user interface still serving as the dc load. Figure 9
testing is shown. UI: unintentional islanding; RLC: resistive, inductive, capacitive. shows the four input inductor cur-

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4,000
2,000

IL1 IL2 IL3 IL4 0

–2,000
–4,000
0 0.05 0.1 0.15 0.2
Time (s)
VAN (V) VBN (V) VCN (V)

(a)
100 A /div 1,000
500
0
–500
FIGURE 9. An oscilloscope capture of module input currents IL1, IL2,
IL3, and IL4 (channels 1–4) during a test with all six supply modules –1,000
0 0.05 0.1 0.15 0.2
totaling 2.25 MW, 900 Vdc.
Time (s)
IA (V) IB (V) IC (V)
500
I1 (b)
450 I2
Module Output Current (A)

I3 950 Vdc (V)

400 I4
I5 900
I6
350
850
300
0 0.05 0.1 0.15 0.2
Time (s)
250 (c)
4,000
200
0 20 40 60 80 100 120 140 3,000
Time (s) 2,000
1,000 Idc (A)
FIGURE 10. The individual output currents of each dc supply module 0
during an inverter power ramp test at 900 Vdc and 2,000, 2,160, 0 0.05 0.1 0.15 0.2
and 1,500 kW. Time (s)
(d)
rents from one module during a test at 2.25 MW and 900
Vdc, or 375 kW per module. Comparing Figure 9 with FIGURE 11. A low-voltage ride-through test, 0.55 p.u. ac voltage for
Figure 7 (two-phase, half-load testing), the waveforms for 67 ms returning to 1 p.u. (a) medium-voltage line-neutral voltages,
(b) medium-voltage phase currents, (c) dc voltage, and (d) dc
IL1 and IL3 are very similar in shape and peak value due to
current.
similar output voltage, 900 and 875 V, respectively. The
individual module phases have similar loads, approxi- Standard 1741 anti-islanding and Rule 21 voltage and fre-
mately 100 kW, although, in Figure 9, currents appear quency ride-through protocols.
slightly more balanced than in Figure 7. This operating
mode still has a moment of zero inductor current and Experimental Results with PV Inverters
has not yet reached the point where the H-bridge pole The next set of tests shows the dc supply response to an
switching causes a more rapid drop in inductor current. inverter under abnormal grid conditions. The dc supply
As expected from the two-phase commissioning results, was set to the nominal 900 Vdc, the inverter was brought
diode case temperatures did not exceed 60 °C during to a steady-state 2-MW output power, and the grid simula-
these tests. tor progressed through test sequences to check aspects
As shown in Figure 10, the current sharing between for Rule 21 source requirements. For brevity, only low-
modules was also satisfactory. This test shows module grid voltage conditions are shown here; the high-grid
currents during power ramps from 2,000 to 2,160 kW and voltage condition was also tested for the cease-to-energize
back to 1,500 kW at a 900-V set point. Following commis- requirement with an inverter response similar to a low-
sioning, the dc supply was used to test the inverter for UL voltage condition requiring a cessation.

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3,000 4,000
2,000 2,000
1,000 Pac (kW) 0
0
0 0.5 1 1.5 2 –2,000
Time (s) 0 0.025 0.05 0.075 0.1 0.125 0.15
(a) Time (s)
1,000 VAN (V) VBN (V) VCN (V)
950 Zoom-In Vac (V)
900 (a)
850 1,000
800 500
0 0.5 1 1.5 2
Time (s) 0
(b) –500
2,000
0 0.025 0.05 0.075 0.1 0.125 0.15
0 Idc (A)
Time (s)
–2,000
0 0.5 1 1.5 2 IA (V) IB (V) IC (V)
Time (s)
(c) (b)
1,000
FIGURE 12. A low-voltage momentary cessation test, 0 p.u. ac Vdc (V)
voltage for 67 ms returning to 1 p.u. within 2 s. (a) Power at 950
medium voltage ac, (b) dc supply voltage, and (c) dc supply current.
900
Low-Voltage Ride-Through
850
The following test sequence shows the inverter response 0 0.025 0.05 0.075 0.1 0.125 0.15
to a low-grid voltage condition, 0.55 p.u. for 67 ms. Based Time (s)
on the Rule 21 ride-through table, this is in region LV2 (c)
(0.5–0.7 p.u. grid voltage), so the inverter must continue 4,000
supplying ac power out to a 10-s trip time. As mentioned Idc (A)
previously, ac currents should remain at >80% of the pre- 2,000
disturbance value. Figure 11 shows the line-neutral volt- 0
ages and phase currents at the medium-voltage side of the
transformer as well as the dc supply voltage and current. –2,000
0 0.025 0.05 0.075 0.1 0.125 0.15
The dc voltage swells slightly during the low-grid voltage
Time (s)
condition but remains within the inverter dc input range. (d)
During the low-voltage condition, the inverter continues 100
to supply the required ac current, but due to the near- DutyPAU %
0.5 p.u. grid voltage of the dc and ac power, it is nearly 50 DutyDB %
half of the predisturbance value, as evidenced by the dc
current cut by roughly half. The inverter recovers with a 0
large dc current draw with some overshoot, but the dc 0 0.025 0.05 0.075 0.1 0.125 0.15
supply remains online without tripping and the dc voltage Time (s)
(e)
quickly recovers.

Low-Voltage Momentary Cessation FIGURE 13. A zoom-in plot for low-voltage momentary cessation
testing: 0 p.u. ac voltage for 67 ms returning to 1 p.u. (a) MV L-N
The next test was for the LV3 region (0.5–0 p.u. grid volt- voltages, (b) MV phase currents, (c) dc voltage, (d) dc current, and
age). This region in Rule 21 is unique, and still under some (e) duty cycles for PAU and dynamic brake.
interpretation, in that the inverter must momentarily cease
to energize the grid without tripping so long as the grid a manner different from that of the LV1 and LV2 regions;
voltage recovers to above 0.5 p.u. within 1 s, and if not, this particular inverter returns to service within approxi-
the inverter is allowed to trip. As mentioned previously, mately one 60-Hz cycle. Rather, if the grid voltage recovers
this momentary cessation is <10% of the predisturbance ac from an LV3 region, the inverter has 2 s to return to ser-
current. Additionally, the inverter is allowed to recover in vice. From a dc supply perspective, this potentially mild,

10 IEEE Industry Applications Magazine œ september/october 2018

 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

slow return to service is much easier to handle than the Author Information
near-immediate recovery seen in Figure 11. Jesse Leonard ([email protected]), Ramtin Hadidi,
For this test, the grid voltage was reduced to 0 p.u. for J. Curtiss Fox, Thomas Salem, Benjamin Gislason, and
67 ms then returned back to 1 p.u. (Figure 12 shows the Mark H. McKinney are with the Clemson University
entire sequence and Figure 13 the first 150 ms). Figure Duke Energy eGRID Center, North Charleston, South Caro-
12 clearly illustrates the initial ac power cut to 0 kW, a lina. Leonard, Hadidi, Fox, and Gislason are Members of
momentary cessation followed by a return to service with- the IEEE. McKinney is a Senior Member of the IEEE. This
in 2 s once the grid voltage returns to nominal. article first appeared as “Design and Commissioning of
The more interesting aspect is the dc supply response 2.5  MW dc Supply for Evaluating Megawatt Scale Smart
to the near-immediate 2,000-kW load rejection. First, Solar Inverters” at the 2016 IEEE IAS Annual Meeting. This
recall that this is still a momentary cessation by the invert- article was reviewed by the IAS Power Systems Engineer-
er; the inverter ac and dc breakers remained closed for ing Committee.
the duration of the test. Figure 13 shows the line-neutral
voltages and phase currents at the isolation transformer’s References
medium-voltage terminals, the dc supply voltage and cur- [1] Standard for Inverters, Converters, Controllers and Interconnection
System Equipment for Use with Distributed Energy Resources, UL Stan-
rent, the absolute value of the dc supply duty cycle, and dard 1741, 2010.
the dynamic brake IGBT duty cycle. The absolute value [2] IEEE Standard for Interconnecting Distributed Resources with Electric
is given because the actual duty cycle includes the sign- Power Systems, IEEE Standard 1547, 2018.
[3] California Public Utilities Commission. (2018). Rule 21 interconnec-
toggling feature discussed previously. The dc supply load tion. [Online]. Available: http://www.cpuc.ca.gov/Rule21/
rejection features engage just as the dc current starts to [4] Y. Liu, C. Farnell, J. C. Balda, and H. A. Mantooth, “Design of a 2 MW
drop and the dc voltage begins to rise. dc supply using a 4-stage interleaved dc-dc converter,” in Proc. IEEE
Energy Conversion Congr. and Exposition (ECCE), 2014, pp. 964–970.
The integrator reset goes into effect once the measured [5] M. H. McKinney, J. C. Fox, E. R. Collins, K. Bulgakov, and T. E. Salem,
dc voltage exceeds 50 V above the set point, along with “Design, development, and commissioning of a multimegawatt test facil-
the dynamic brake engaging to bring the stored induc- ity for renewable energy research,” IEEE Trans. Ind. Appl., vol. 52, no. 1,
pp. 11–17, 2016.
tor energy to zero. It appears that there is some dc cur- [6] J. C. Fox and B. Gislason, “Introduction to the Clemson University 15
rent oscillation between the dc supply capacitors and the MW hardware-in-the-loop grid simulator,” in Proc. Power Systems Conf.
inverter capacitors, i.e., a C-L-C circuit; but this quickly (PSC), 2014, pp. 1–5.
[7] E. Ledezma, K. Wang, T. Keister, R. Edwards, R. Pipho, B. Palle, D.
damps out. The output dc voltage never goes beyond Kulkarni, T. E. Salem, J. C. Fox, and L. Parsa, “Development of a modular
1,000 V, remaining within the 1,000-Vdc maximum input configurable multi-megawatt power amplifier,” in Proc. 39th IEEE Indus-
specified by the inverter. Some additional tuning of the trial Electronics Society Annu. Conf. (IECON), 2013, pp. 631–636.
[8] J. Leonard, R. Hadidi, T. Salem, J. C. Fox, B. Gislason, and M. H. McK-
coordination between the integrator reset and the dynam- inney, “Design and commissioning of 2.5 MW dc supply for evaluating
ic brake may help with further d ­ amping of the oscillatory megawatt scale smart solar inverters,” in Proc. IEEE IAS Annu. Meeting,
dc current during these harsh load rejection events. 2016, pp. 1–5.
[9] ASEA Brown Boveri Group. (2014, Nov. 3). ABB delivers packaged
DC voltage ripple predisturbance is within ±10 V of the inverter solutions for 146.4 MW solar project in Honduras. ABB Group.
nominal 900 V. The interleaved topology, even with 600- Zürich, Switzerland. [Online]. Available: http://www.abb.com/cawp/
Hz PWM carriers, creates an output voltage with very low seitp202/a3f977d04099a3fdc1257d8500406b03.aspx
[10] SMA America. (2015, Aug. 18). SMA earns 700 MW order from Swin-
ripple under an inverter load. erton Renewable Energy. SMA America. Rocklin, CA. [Online]. Available:
https://www.sma-america.com/newsroom/current-news/news-details/
Conclusions news/301-sma-earns-700-mw-inverter-order-from-swinerton-renewable-
energy.html
This article showed the design and commissioning of a [11] D. G. Holmes and T. A. Lipo, Pulse Width Modulation for Power Con-
2.5-MW dc supply suitable for testing grid-tie inverters verters: Principles and Practice. Hoboken, NJ: Wiley, 2003.
under demanding grid codes such as Rule 21 as well as [12] J. Leonard, J. C. Fox, R. Hadidi, B. Gislason, and M. H. McKinney,
“Experimental PWM method validation of a 9-level 4.16 kV series con-
anti-islanding tests. The retrofit approach using an exist- nected H-bridge grid simulator,” in Proc. IEEE Power and Energy Conf.
ing medium-voltage multilevel drive with added output Illinois (PECI), 2016, pp. 1–6.
stage lowered the overall project cost while meeting [13] T. Meynard, Analysis and Design of Multicell dc-dc Converters Using
Vectorized Models. Hoboken, NJ: Wiley, 2015.
custom control system and data logging requirements. [14] J. Wang, Y. Li, and Y. Han, “Integrated modular motor drive design
The approach taken here, with the facility team taking with GaN power FETs,” IEEE Trans. Ind. Appl., vol. 51, no. 4, pp. 3198–
on the design and integration role, also allows for future 3207, July-Aug. 2015.
[15] J. C. G. Justino, T. M. Parreiras, and B. J. Cardoso Filho, “Hundreds
upgrades if the need for higher power is required. The kW charging stations for e-buses operating under regular ultra-fast charg-
kinds of holistic design approaches used here, including ing,” IEEE Trans. Ind, Appl., vol. 52, no. 2, pp. 1766–1774, Mar.–Apr. 2016.
the protection and load rejection considerations made for [16] M. H. McKinney, J. C. Fox, and B. Gislason, “Design and validation of
a communication and control system for a 20MVA hardware-in-the-loop
this supply, have already proven themselves to be invalu- renewable energy test facility,” in Proc. Innovative Smart Grid Technolo-
able for large solar inverter certification testing. gies Conf. (ISGT), 2015, pp. 1–5.

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