Enhancing

Power Modules
Dr. Kay Essig
Efficiency ASE
September, 2016
by
Chip Embedding

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3D Integration
Stacked
Embedded TSV
& PoP

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Embedded Technology Introduction
Embedded Components

Passive Active (Die)

Wafer Level Embedded Die in

Formed Placed
Embedded Die Substrate
FOWLP is based on a Embedded die in
reconfigured molded package is based on a
Materials are added wafer infrastructure PCB type of panel
Resistors
to the printed circuit infrastructure
structure to create the
Capacitors passive element.

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Embedded Die Substrate Technology
aEASI - Embedded Active System Integration

Type Schematics Content Status

EAP - Embedded Active Package 1RDL 1Die passed reliability

Lead Frame based single or multi 3RDL 3Die mass production
aEASI dies embedded in organic
laminate material

MOSFET
3.4x3.0 mm²
2 Layer RDL

Chip 1 Chip 2

Leadframe DC/DC Module

4.5x6.6 mm²

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a-EASI Product: DC/DC Converter

• Package: 6.65 x 4.55 x 0.8 mm3, 38L

• Chip Information: 2 MOSFETs + 1 Driver Chip
• Max. average current: 60 A
• Input Voltage range: 4.5 V to 16 V
• Fast switching > 750 kHz
• Power up Blade Server
2 Layer RDL

Chip 1 Chip 2

Leadframe
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Die Attach on L/F - TLPB
Transient Liquid Phase Bonding

High Temp.
Pressure

Die Bond preparation on Die side TLPB process Die Bond on Lead Frame

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Process Flow
Die Attach

Lamination

Lase Drill

Plating

Pattern

S/M

ENIG

Laser Marking

Solder
Printing

Singulation

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Embedded Power Module Manufacturing

Capacity & Yield

Yield = 97.6% in May ’16. Targeting 99% in Q4 ’16.
Important because of 3 KGD are embedded per device
Capacity of 3.3M unit/month (5x6 mm) today.
More than 40 M units delivered

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aEASI - P2 Results Patent pending

Die attach Lamination Laser drill Plating & Patterning S/M, Marking, Singulation

die die die die

X-Ray result
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Embedded Die Power Module
Advantages
• Smaller & Thinner package DrBlade
• Excellent Thermal Dissipation
− 2 sides cooling areas
• Excellent Electrical Performance
− µ-via for Gate and Source, full surface Drain
DC/DC Module
− Low resistance & inductance, good shielding 4.5x6.6 mm²
• Enhanced Reliability
DrMOS
Markets
• Power Devices, MOSFET
• DC/DC Converter Modules
• Fast switching Power & IGBT
DC/DC PQFN
6x6 mm²

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Power Die - Reliability
Power Electronic Packages
Al wire
Crack propagates through Al wire matrix
Increases electrical/thermal resistance
Al wire
Si Chip Soft Solder
Crack formation in solder volume
Increases thermal / electrical resistance

Embedded Power Packages µ-via

Copper filled micro vias on Cu die pad
No crack expected

TLPB / Ag Sintering
High melting point > 300°C
Stable against thermal stress

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Reliability Tests
Test description Abbr. Condition Readout Result

Pre-Conditioning PC MSL3, 3x260°C, Reflow Pass

J-STD-020D
Biased Highly Accelerated HAST Ta=130°C RF=85% 0 h precon Pass
Stress Test JESD22 A110 96 h Pass
Temperature Cycling TC T = - 55°C to 150°C 0 c precon Pass
JESD22 A104 500c Pass
1000c Pass
High Temperature HTSL Ta = 150°C 0 h precon Pass
Storage Life 168 h Pass
JESD22 A103 500 h Pass
1000 h Pass
High Temperature Operating HTOL Ta = 125°C Tj = 150°C 0h Pass
Life JESD22 A108 168 h Pass
500 h Pass
1000 h Pass
Power Temperature Cycling PTC T = - 40°C to 125°C 0 c precon Pass
JESD22 A105 500c Pass
1000c Pass

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PMIC Package Comparison
Standard PQFN Types
• PQFN 6x6 mm² Cu Clip

• PQFN 6x6 mm² Cu Wire Bond

Embedded Die Packages

• aEASI 4.5x6 mm²

• aEASI 4.5x6 mm² cavity

Patent pending

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PMIC Comparison - Thermal Resistance

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 PMIC Comparison - Electrical Performance
nH

mOhm

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Via Resistance & Inductance

• Resistance is analyzed at 0 Hz.

• Inductance is analyzed at 100 MHz.
• Conclusion: More via in parallel to share the current
density introduce lower R & L interconnection

aEASI 4 layers Structure

L (nH)
R (mohm)

Via Count (#) Via Count (#)

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 Electrical & Thermal Performance

LSMOS

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Design Rule
• Detail design rule is available today for customer design study

Unit: um
Symbol Description Normal Advance Prototype

A Die Pad Size 120 110 100

B Die Pad Pitch 180 150 135

Die Pad Material (Cu Thickness) 5 4 3

C Via Diameter (Top Diameter) 70 60 50

D/E Line width/space 60/60 *35um Cu 40/40 *15um Cu 35/35 *12um Cu

RDL Layer 2

Via aspect ratio 1.1 1.2

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Embedding Benefits
Smaller Outline
Lower Thickness
Electrical Performance
• Shorter Tracks
• Lower Resistance & Inductance
• Shielding
Thermal Performance
• More Cooling Areas
Less Delamination (similar materials)
Enhanced Reliability
Less Plagiarism
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Embedded packaging business model

Pre Ass‘y
Embedding
Bump, Grind,
in Substrate
Dice, Sort
Foundry

Module Component
Customer Final Test Test
Process
Flow for
Embedded
Devices

OSAT
Module
Package
Assembly
Assembly

Final Test

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Summary

Embedded Components can have more and more important

benefits than smaller outline
Embedded Power Modules show advantages in Thermal and
Electrical Performance
ASE brought aEASI – Embedded Die Power Modules to HVM
Next Gen. aEASI shows enhanced manufacturability and flexibility

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 Thank You
www.aseglobal.com

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