Infineon TC27xDC DataSheet v01 00 en
Infineon TC27xDC DataSheet v01 00 en
Infineon TC27xDC DataSheet v01 00 en
Microcontroller
Data Sheet
V 1.0, 2017-01
Microcontrollers
Edition 2017-01
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2017 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
TC270 / TC275 / TC277 DC-Step
Revision History
Page or Item Subjects (major changes since previous revision)
V 1.0, 2017-01
The history is documented in the last chapter
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR
development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™
of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2011-11-11
Table of Contents
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Package and Pinning Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 TC275x Pin Definition and Functions: LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 TC275x LQFP176 Package Variant Pin Configuration' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.2 Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.1.3 Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.2 TC277x Pin Definition and Functions: BGA292 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.2.1 TC277xBGA292 Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.2.2 Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
2.2.3 Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
2.3 TC270x Bare Die Pad Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
2.3.1 Pad Openings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
2.3.2 Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
2.3.3 Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
3 Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
3.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
3.3 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
3.4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
3.5 5 V / 3.3 V switchable Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
3.6 3.3 V only Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
3.7 High performance LVDS Pads (LVDSH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
3.8 Medium performance LVDS Pads (LVDSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
3.9 VADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
3.10 DSADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
3.11 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
3.12 Back-up Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
3.13 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
3.14 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
3.14.1 Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
3.15 Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
3.15.1 External Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
3.15.2 Single Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
3.15.3 External Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
3.15.4 Single Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
3.16 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
3.17 EVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
3.18 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
3.19 ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
3.20 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
3.21 JTAG Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
3.22 DAP Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
3.23 ASCLIN SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
3.24 ASCLIN SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
3.25 QSPI Timings, Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
3.26 QSPI Timings, Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
3.27 MSC Timing 5 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
3.28 MSC Timing 3.3 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Summary of Features
1 Summary of Features
The TC27x product family has the following features:
• High Performance Microcontroller with three CPU cores
• Two 32-bit super-scalar TriCore CPUs (TC1.6P), each having the following features:
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle
– Fully pipelined Floating point unit (FPU)
– up to 200 MHz operation at full temperature range
– up to 120 Kbyte Data Scratch-Pad RAM (DSPR)
– up to 32 Kbyte Instruction Scratch-Pad RAM (PSPR)
– 16 Kbyte Instruction Cache (ICACHE)
– 8 Kbyte Data Cache (DCACHE)
• Power Efficient scalar TriCore CPU (TC1.6E), having the following features:
– Binary code compatibility with TC1.6P
– up to 200 MHz operation at full temperature range
– up to 112 Kbyte Data Scratch-Pad RAM (DSPR)
– up to 24 Kbyte Instruction Scratch-Pad RAM (PSPR)
– 8 Kbyte Instruction Cache (ICACHE)
– 0.125Kbyte Data Read Buffer (DRB)
• Lockstepped shadow cores for one TC1.6P and for TC1.6E
• Multiple on-chip memories
– All embedded NVM and SRAM are ECC protected
– up to 4 Mbyte Program Flash Memory (PFLASH)
– up to 384 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 32 Kbyte Memory (LMU)
– BootROM (BROM)
• 64-Channel DMA Controller with safe data transfer
• Sophisticated interrupt system (ECC protected)
• High performance on-chip bus structure
– 64-bit Cross Bar Interconnect (SRI) giving fast parallel access between bus masters, CPUs and memories
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (SFI Bridge)
• Optional Hardware Security Module (HSM) on some variants
• Safety Management Unit (SMU) handling safety monitor alarms
• Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU)
• Hardware I/O Monitor (IOM) for checking of digital I/O
• Versatile On-chip Peripheral Units
– Four Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1
and J2602) up to 50 MBaud
Summary of Features
– Four Queued SPI Interface Channels (QSPI) with master and slave capability up to 50 Mbit/s
– High Speed Serial Link (HSSL) for serial inter-processor communication up to 320 Mbit/s
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices
– One MultiCAN+ Module with 4 CAN nodes and 256 free assignable message objects for high efficiency
data handling via FIFO buffering and gateway data transfer
– 10 Single Edge Nibble Transmission (SENT) channels for connection to sensors
– One FlexRayTM module with 2 channels (E-Ray) supporting V2.1
– One Generic Timer Module (GTM) providing a powerful set of digital signal filtering and timer functionality
to realize autonomous and complex Input/Output management
– One Capture / Compare 6 module (Two kernels CCU60 and CCU61)
– One General Purpose 12 Timer Unit (GPT120)
– Three channel Peripheral Sensor Interface conforming to V1.3 (PSI5)
– Peripheral Sensor Interface with Serial PHY (PSI5-S)
– Optional Inter-Integrated Circuit Bus Interface (I2C) conforming to V2.1
– Optional IEEE802.3 Ethernet MAC with RMII and MII interfaces (ETH)
• Versatile Successive Approximation ADC (VADC)
– Cluster of 8 independent ADC kernels
– Input voltage range from 0 V to 5.5V (ADC supply)
• Delta-Sigma ADC (DSADC)
– Six channels
• Digital programmable I/O ports
• On-chip debug support for OCDS Level 1 (CPUs, DMA, On Chip Buses)
• multi-core debugging, real time tracing, and calibration
• four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface
• Power Management System and on-chip regulators
• Clock Generation Unit with System PLL and Flexray PLL
• Embedded Voltage Regulator
Summary of Features
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering
code identifies:
• The derivative itself, i.e. its function set, the temperature range, and the supply voltage
• The package and the type of delivery.
For the available ordering codes for the TC270 / TC275 / TC277 please refer to the
"AURIX™ TC2x Data Sheet Addendum", which summarizes all available variants.
FPU yes
Data (P / E) 8 Kbyte / -
DMA Channels 64
ADC Channels 48 + 12
Converter 8
DSADC Channels 6
GTM TIM 4
TOM 3
PSM 1
TBU 1
SPE 2
Timer GPT12 2
CCU6 2
STM Modules 3
FlexRay Modules 1
Channels 2
Summary of Features
QSPI Channels 4
ASCLIN Interfaces 4
I2C Interfaces 1
SENT Channels 10
PSI5 Modules 3
PSI5-S Modules 1
HSSL Channels 1
MSC Channels 2
Ethernet Channels 1
FCE Modules 1
IOM 1
Security HSM 1
P11.12
P11.11
P11.10
P14.10
P10.8
P10.7
P10.6
P10.5
P10.4
P10.3
P10.2
P10.1
P10.0
P11.9
P11.6
P11.3
P11.2
P13.3
P13.2
P13.1
P13.0
P14.9
P14.8
P14.7
P14.6
P14.5
P14.4
P14.3
P14.2
P14.1
P14.0
P15.8
P15.7
P15.6
P15.5
P15.4
P15.3
P15.2
P15.1
P15.0
VD DFL3
VD DP3
VFL EX
VEXT
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
P02.0 1 132 P20. 14
P02.1 2 131 P20. 13
P02.2 3 130 P20. 12
P02.3 4 129 P20. 11
P02.4 5 128 P20. 10
P02.5 6 127 P20. 9
P02.6 7 126 P20. 8
P02.7 8 125 P20. 7
P02.8 9 124 P20. 6
VDD/ VDDSB 10 123 VDD
P00.0 11 122 ESR0
P00.1 12 121 PORST
P00.2 13 120 ESR1
P00.3 14 119 P20. 3
P00.4 15 118 P20. 2 / TESTMODE
P00.5 16 117 P20. 1
P00.6 17 116 P20. 0
P00.7 18 115 TCK
P00.8 19 114 TRST
P00.9 20 113 P21. 7 / TDO
P 00.10 21 112 TMS
P 00.11 22 111 P21. 6 / TDI
P 00.12 23 TC27x 110 P21. 5
VDD 24 109 P21. 4
V EXT 25 108 P21. 3
V AREF2 26 107 P21. 2
VAGND 2 27 106 P21. 1
AN47 28 105 P21. 0
AN46 29 104 VDDP 3
AN45 30 103 XTAL2
AN44 31 102 XTAL1
AN39 32 101 VSS
AN38 33 100 VDD
AN37 34 99 VEXT
AN36 35 98 P22. 3
AN35 36 97 P22. 2
AN33 37 96 P22. 1
AN32 38 95 P22. 0
AN29 39 94 P23. 5
AN28 40 93 P23. 4
AN27 41 92 P23. 3
AN26 42 91 P23. 2
AN25 43 90 P23. 1
AN24 44 89 P23. 0
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VD D
V GATE1 P
VEXT
AN21
AN20
AN19
AN18
AN17
AN16
AN13
AN12
AN11
AN10
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
P 33.0
P 33.1
P 33.2
P 33.3
P 33.4
P 33.5
P 33.6
P 33.7
P 33.8
P 33.9
P33. 10
P33. 11
P33. 12
P33. 13
VGATE1 N / P 32.0
P 32.2
P 32.3
P 32.4
VAG ND1
VAREF1
VSSM
VDDM
Figure 2-1 TC275x Logic Symbol for the package variant LQFP176.
Legend:
Column “Ctrl.”:
I = Input (for GPIO port Lines with IOCR bit field Selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bit field selection PCx = 1X000B
O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2)
1)The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a weak
internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, “Introduction Chapter”, “General
Purpose I/O Ports and Peripheral I/O Lines”, Figure: “Default state of port pins during and after reset”.
2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups (PU1) / pull-downs (PD1) are active
during and after reset.
3) If HWCFG[6] is connected to ground, the PD1 / PU1 pins are predominantly in HighZ during and after reset.
• The Emergency Stop function can be enabled/disabled in the SCU (see chapter “SCU”, “Emergency Stop
Control”)
• The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see
chapter “SCU”, “Emergency Stop Control”)
• On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x
Emergency Stop) registers in the port control logic (see chapter “General Purpose I/O Ports and Peripheral I/O
Lines”, “Emergency Stop Register”).
The Emergency Stop function is available for all GPIO Ports with the following exceptions:
• Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode)
• Not available for P40.x (analoge input ANx overlayed with GPI)
• Not available for P32.0 EVR13 SMPS mode.
• Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK)
The Emergency Stop function can be overruled on the following GPIO Ports:
• P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register
P00_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00)
• P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode).
No Overruling in the DXCM (Debug over can message) mode
• P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI
• P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode
• P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI
In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case
of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on.
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Y VSS P32.3 P32.2 P32.0 P33.13 P33.11 P33.9 P33.7 P33.5 P33.3 P33.1 AN5 AN10 VAGND1 VAREF1 VDDM VSSM AN20 AN21 NC Y
VGATE1
W VEXT VSS P32.4 P33.12 P33.10 P33.8 P33.6 P33.4 P33.2 P33.0 AN2 AN8 AN11 AN13 AN16 AN18 AN19 AN24 AN25 W
P
U P23.2 P23.1 U VSS P32.7 P32.6 P33.15 P34.5 P34.3 P34.1 AN1 AN3 AN7 AN9 AN14 AN17 NC U AN28 AN29 U
T P23.4 P23.3 T P23.5 VSS P32.5 P33.14 P34.4 P34.2 VEVRSB AN0 AN4 AN6 AN12 AN15 AN22 AN30 T VAGND2 VAREF2 T
VSS VSS
P P22.0 P22.1 P P22.5 P22.4 VDD VSS (AGBT (AGBT VSS VDD AN34 AN32 P AN37 AN39 P
TX0P) TX0N)
N VDDP3 VDD N P22.7 P22.6 VDD VSS VSS VSS VSS VDD AN38 AN36 N AN45 AN44 N
M XTAL1 XTAL2 M P22.9 P22.8 VSS VSS VSS VSS VSS VSS AN40 AN41 M AN47 AN46 M
VSS VSS
L VSS TRST L P22.11 P22.10 (AGBT VSS VSS VSS VSS VSS VSS (AGBT AN42 AN43 L P00.12 P00.11 L
ERR) CLKN)
VSS
NC
K P21.4 P21.2 K P21.0 TMS VSS VSS VSS VSS VSS VSS (AGBT P00.10 P00.8 K P00.9 P00.7 K
(VDDPSB)
CLKP)
J P21.5 P21.3 J P21.1 TCK VSS VSS VSS VSS VSS VSS P01.7 P00.6 J P00.5 P00.4 J
VDD
H P20.0 P20.2 H P21.6 P21.7 VDD VSS VSS VSS VSS P01.5 P01.6 H P00.3 P00.2 H
(VDDSB)
VDD
G P20.3 P20.1 G PORST ESR1 VDD VSS VSS VSS VSS P01.3 P01.4 G P00.1 P00.0 G
(VDDSB)
E P20.11 P20.10 E P20.9 VSS VDDFL3 P15.5 P14.2 P12.0 P12.1 P11.0 P11.1 P11.7 P11.8 P11.13 VSS P02.9 E P02.5 P02.6 E
D P20.13 P20.12 D VSS VDDFL3 P15.7 P15.8 P14.7 P14.9 P14.10 P11.4 P11.6 P11.5 P11.14 P11.15 VFLEX VSS D P02.3 P02.4 D
17 16 15 14 13 12 11 10 9 8 7 6 5 4
C P20.14 P15.2 P02.1 P02.2 C
B P15.0 VSS VDDP3 P15.3 P14.0 P14.4 P14.3 P14.6 P13.0 P13.2 P11.3 P11.10 P11.12 P10.1 P10.4 P10.5 P10.8 VEXT VSS P02.0 B
A VSS VDDP3 P15.1 P15.4 P15.6 P14.1 P14.5 P14.8 P13.1 P13.3 P11.2 P11.9 P11.11 P10.0 P10.3 P10.2 P10.6 P10.7 VEXT NC A
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Figure 2-2 TC277x Logic Symbol for the package variant BGA292.
Production Device:
This pin is not connected on package level. It can be
connected on PCB level to VDDP or Ground or can be
left unsupplied.
A1, Y1, U4 NC I NC Not Connected.
These pins are not connected on package level and
will not be used for future extensions.
Legend:
Column “Ctrl.”:
I = Input (for GPIO port Lines with IOCR bit field Selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bit field selection PCx = 1X000B
O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2)
O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3)
O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4)
O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5)
O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6)
O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7)
Column “Type”:
LP = Pad class LP (5V/3.3V, LVTTL)
MP = Pad class MP (5V/3.3V, LVTTL)
MP+ = Pad class MP+ (5V/3.3V, LVTTL)
MPR = Pad class MPR (5V/3.3V, LVTTL)
A2 = Pad class A2 (3.3V, LVTTL)
LVDSM = Pad class LVDSM (LVDS/CMOS 5V/3.3V)
LVDSH = Pad class LVDSH (LVDS/CMOS 3.3V)
S = Pad class S (ADC overlayed with General Purpose Input)
D = Pad class D (ADC)
PU = with pull-up device connected during reset (PORST = 0)
PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3)
1)The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a weak
internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, “Introduction Chapter”, “General
Purpose I/O Ports and Peripheral I/O Lines”, Figure: “Default state of port pins during and after reset”.
2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups (PU1) / pull-downs (PD1) are active
during and after reset.
3) If HWCFG[6] is connected to ground, the PD1 / PU1 pins are predominantly in HighZ during and after reset.
• P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI
In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case
of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on.
0.0
X
Legend:
Column “Number”:
Running number of pads in the pad frame
Column “Name”:
Symbolic name of the pad.
The functions mapped on GPIO pads “Px.y” are described in the User’s Manual chapter ”General Purpose I/O
Ports and Peripheral I/O LInes (Ports)”
Column “Type”:
LP = Pad class LP (5V/3.3V, LVTTL)
MP = Pad class MP (5V/3.3V, LVTTL)
MP+ = Pad class MP+ (5V/3.3V, LVTTL)
1)The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a weak
internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, “Introduction Chapter”, “General
Purpose I/O Ports and Peripheral I/O Lines”, Figure: “Default state of port pins during and after reset”.
2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups are active at GPIOs (Px.y) pins during
and after reset. Exceptions are P33.8 (HighZ), P40.x (default configuration during and after reset: analog inputs, port input
funtion disabled), ESR0, P21.6 / P21.7 (port pins overlayed with JTAG functionality).
3) If HWCFG[6] is connected to ground, port pins are predominantly in HighZ during and after reset. Exceptions are P33.8
(HighZ), P40.x (default configuration during and after reset: analog inputs, port input funtion disabled), ESR0, P21.6 / P21.7
(port pins overlayed with JTAG functionality).
• In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In
case of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on.
3 Electrical Specification
Note: DSADC input pins count as analog pins as they are overlaid with VADC pins.
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX.
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX.
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX.
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
Input low threshold variation for VILSD SR -50 - 50 mV max. variation of 1ms;
S pad 2) VDDM=constant
Input capacitance for S pad CINS CC - - 10 pF
Pad set-up time for S pad tSETS CC - - 100 ns
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) VILSD is implemented to ensure J2716 specification. For details of dedicated pins please see AP32286 for details.
Table 3-24 LVDSH - IEEE standard LVDS general purpose link (GPL)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Output impedance R0 CC 40 - 140 Ohm Vcm = 1.0 V and 1.4 V
1)
Rise time trise20 CC - - 0.5 ns ZL = 100 Ohm ±5%
@2 pF
Fall time 1) tfall20 CC - - 0.5 ns ZL = 100 Ohm ±5% @
2 pF
Output differential voltage VOD CC 250 - 400 mV RT = 100 Ohm ±5%
Table 3-24 LVDSH - IEEE standard LVDS general purpose link (GPL) (cont’d)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Output voltage high VOH CC - - 1475 mV RT = 100 Ohm ±5%
(400 mV/2) + 1275 mV
Output voltage low VOL CC 925 - - mV RT = 100 Ohm ±5%
Output offset (Common mode) VOS CC 1125 - 1275 mV RT = 100 Ohm ±5%
voltage
Input voltage range VI SR 0 - 1600 mV Driver ground potential
difference < 925 mV;
RT = 100 Ohm ±10%
0 - 2000 mV Driver ground potential
difference < 925 mV;
RT = 100 Ohm ±20%
Input differential threshold Vidth SR -100 - 100 mV Driver ground potential
difference < 925 mV
Delta output impedance dR0 SR - - 10 % Vcm = 1.0 V and 1.4 V
(mismatch Pd and Pn)
Change in VOS between 0 and dVOS CC - - 25 mV RT = 100 Ohm ±5%
1
Change in Vod between 0 and dVod CC - - 25 mV RT = 100 Ohm ±5%
1
Duty cycle tduty CC 45 - 55 %
1) Rise / fall times are defined for 20% - 80% of VOD
Table 3-25 LVDSH - IEEE standard LVDS reduced link (REDL) (cont’d)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
1)
VOD Fall time tfall10 CC - - 0.5 ns ZL = 100 Ohm ±5% @
2pF
1)
VOD Rise time trise10 CC - - 0.5 ns ZL = 100 Ohm ±5% @
2pF
1) Rise / fall times are defined for 10% - 90% of VOD
The following VADC parameter are valid for VDDM = 2.97 V to 3.63 V.
A/D Converter
RSource R AIN, On
MCS05570
The following DSADC parameter are valid for VDDM = 2.97 V to 3.63 V.
11) 10 kHz bandwidth only with 10Mhz modulator clock frequency reachable
12) Voltage VCM is proportional to VAREF, voltage VCMH is proportional to VDDM.
13) The modulator needs to settle after being switched on and after leaving the overdrive state.
14) SFDR = 20 * log(INL / 2N); N = amount of bits
V CM
37 kΩ
37 kΩ
Gain
V OFFSET
130 kΩ =
Modu -
Input
lator
130 kΩ
Gain
MC_DSADC_MODULATORBLOCK
Note: It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target
system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits
specified by the crystal or ceramic resonator supplier.
The following formula calculates the temperature measured by the DTS in [oC] from the RESULT bit field of the
DTSSTAT register.
(3.1)
DTSSTATRESULT – ( 607 )
Tj = ----------------------------------------------------------------------------
2, 13
4) The current consumption is for 2 pairs of LVDSM differential pads (8 pins). A single pair of LVDSM differential pads (4 pins)
consumes 7 mA.
5) The current consumption is for 6 DS channels with standard performance (MCFG=11b). A single DS channel instance
consumes 6-8 mA.
6) A single converter instance of VADC unit consumes 2 mA.
7) The total current drawn from external regulator is estimated with 72% EVR13 SMPS regulator Efficiency. IDDTOTDCx is
calculated from IDDTOT using the scaled core current [(IDD x VDD)/(VinxEfficiency)] and constitutes all other rail currents and
IDDM.
8) Current at VEVRSB supply pin during normal RUN mode is less than 5 mA at Tj =150 degC. The transition between RUN
mode to STANDBY mode has a duration of less than 100us during which the current is higher but is less than 8 mA at Tj
=150 degC. Once STANDBY mode is entered with only Standby RAM active the current is less than 5mA at Tj = 150 degC.
It is recommended to have atleast 100 nF decoupling capacitor at this pin.
(3.3)
Function 2 defines the typical static current consumption and Function 3 defines the maximum static current
consumption. Both functions are valid for VDD = 1.326 V.
2.97 V
Primary Reset Threshold
0V
1.33 V
1.30 V
1.17 V
Primary Reset Threshold
0V
PORST (output )
PORST (input)
0V
T0 T1 T2 T3 T4
Basic Supply & Clock EVR33 Ramp-up Phase Firmware Execution User Code Execution Power Ramp-down phase
Infrastructure fCPU =100MHz default
on firmware exit Startup_Diag_1 v 0.1
2.97 V
Primary Reset Threshold
0V
PORST (output )
PORST (input)
0V
0V
T0 T1 T2 T3 T4
Basic Supply & Clock EVR13 & EVR 33 Ramp-up User Code Execution
Phase Firmware Execution Power Ramp-down phase
Infrastructure fCPU =100MHz default Startup_Diag_2 v 0.1
on firmware exit
2.97 V
Primary Reset Threshold
0V
1.33 V
1.30 V
1.17 V Primary Reset Threshold
0V
3.63 V
3.30 V
2.97 V
Primary Reset Threshold
0V
PORST (output )
PORST (input)
T0 T1 T2 T3
Basic Supply & Clock Firmware Execution User Code Execution Power Ramp-down phase
Infrastructure fCPU =100 MHz default
on firmware exit Startup_Diag_3 v 0.1
Figure 3-5 External Supply Mode - 5 V, 3.3 V & 1.3 V externally supplied
0V
PORST (output )
PORST (input)
0V
T0 T1 T2 T3 T4
Basic Supply & Clock EVR13 Ramp-up Phase Firmware Execution User Code Execution Power Ramp-down phase
Infrastructure fCPU =100MHz default Startup_Diag_4 v 0.1
on firmware exit
4) The regulator that supplies VEXT should ensure that VEXT is in the operational region before PORST is externally released
by the regulator. Incase of 5V nominal supply, it should be ensured that VEXT > 4V before PORST is released. Incase of
3.3V nominal supply , it should be ensured that VEXT > 3V before PORST is released. The additional minimum PORST hold
time is required as an additional mechanism to avoid consecutive PORST toggling owing to slow supply slopes or residual
supply ramp-ups. It is also required to activate external PORST atleast 100us before power-fail is recognised to avoid
consecutive PORST toggling on a power fail event.
5) This parameter includes the delay of the analog spike filter in the PORST pad.
VD DPR
VDD
tPOA
tPOA
PORST Cold Warm
ESR0
tP I t PI
tP IP
t P OS t P OS
TRST t P OH tP OH
TESTMODE
reset_beh_aurix
Electrical SpecificationEVR
3.17 EVR
Electrical SpecificationEVR
Electrical SpecificationEVR
Electrical SpecificationEVR
Electrical SpecificationEVR
Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the
maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of
VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the
supply pins and using PCB supply and ground planes.
Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the
maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of
VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the
supply pins and using PCB supply and ground planes.
3.20 AC Specifications
All AC parameters are specified for the complette operating range defined in Chapter 3.4 unless otherwise noted
in colum Note / test Condition.
Unless otherwise noted in the figures the timings are defined with the following guidelines:
VEXT/FL EX / VD DP3
90% 90%
10% 10%
VSS
tr tf
rise_fall
VEXT/FL EX / VD D P3
t1
0.9 VD D P
0.5 VD D P
0.1 VD D P
t5 t4
t2 t3
TCK
t6 t7
TMS
t6 t7
TDI
t9 t8 t1 0
TDO
t18
MC_JTAG
t11
0.9 VD D P
0.5 VD D P
0.1 VD D P
t1 5 t14
t1 2 t1 3
MC_DAP0
DAP0
t1 6 t1 7
DAP1
MC_ DAP1_RX
t1 1
DAP1
t1 9
MC_ DAP1_TX
Figure 3-14 DAP Timing Device to Host (DAP1 and DAP2 pins)
Note: The DAP1 and DAP2 device to host timing is individual for both pins. There is no guaranteed max. signal
skew.
t50
ASCLKO
t51 t500 t51
MTSR
t52
t53
MRST Data valid Data valid
t510
ASLSO
ASCLIN_TmgMM.vsd
t50
ASCLKO
t51 t500 t51
MTSR
t52
t53
MRST Data valid Data valid
t510
ASLSO
ASCLIN_TmgMM.vsd
Table 3-59 Master Mode Timing, LVDSM output pads for data and clock
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
1) 2)
SCLKO clock period t50 CC 20 - - ns CL=25pF
Deviation from the ideal duty t500 CC -1 - 1 ns CL=25pF
cycle 3) 4)
MTSR delay from SCLKO t51 CC -3 - 3 ns CL=25pF
shifting edge
SLSOn deviation from the ideal t510 CC 0 - 30 ns CL=25pF; MPsm
programmed position -5 - 7 ns CL=25pF; MPss
-4 - 7 ns MP+ss; CL=25pF
-1 - 15 ns MP+sm; CL=25pF
5)
MRST setup to SCLK latching t52 SR 19 - - ns CL=25pF; LVDSM 5V
edge 5) output and LVDSH
3.3V input
MRST hold from SCLK latching t53 SR -6 5) - - ns CL=25pF; LVDSM 5V
edge output and LVDSH
3.3V input
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended.
3) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX.
4) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
5) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
Table 3-61 Master Mode MP+sm/MPRsm output pads for data and clock
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
1)
SCLKO clock period t50 CC 50 - - ns CL=50pF
Deviation from the ideal duty t500 CC -2 - 3+0.01 * ns 0 < CL < 200pF
cycle 2) 3) CL
MTSR delay from SCLKO t51 CC -10 - 10 ns CL=50pF
shifting edge
SLSOn deviation from the ideal t510 CC -10 - 10 ns MP+sm; CL=50pF
programmed position -13 - 1 ns MPss; CL=50pF
0 - 40 ns MP+m, MPm, LPm;
CL=50pF
MRST setup to SCLK latching t52 SR 50 4)5) - - ns CL=50pF
edge 4)
MRST hold from SCLK latching t53 SR -10 4)5) - - ns CL=50pF
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
t50
t500
0.5 VEXT/FLEX
SCLK1)2)
t51 SAMPLING POINT
t52
t53
MRST 1) Data valid Data valid
t510
0.5 VEXT/FLEX
SLSOn2)
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay).
2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0.
QSPI_TmgMM.vsd
t55 t55
t56 t56
t57 t57
MTSR 1) Data Data
valid valid
t60 t60
1)
MRST 0.5 VEXT/FLEX
t58
t61 t59
SLSI
Table 3-66 Master Mode Timing, LVDSM output pads for data and clock
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
1)
SCLKO clock period t50 CC 20 - - ns CL=25pF
Deviation from the ideal duty t500 CC -2 - 2 ns CL=25pF
cycle 2) 3)
MTSR delay from SCLKO t51 CC -5 - 5 ns CL=25pF
shifting edge
Table 3-66 Master Mode Timing, LVDSM output pads for data and clock (cont’d)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
SLSOn deviation from the ideal t510 CC -2 - 55 ns CL=25pF; MPsm
programmed position -9 - 12 ns CL=25pF; MPss
-7 - 12 ns MP+ss; CL=25pF
-2 - 26 ns MP+sm; CL=25pF
MRST setup to SCLK latching t52 SR 20 - - ns CL=25pF; LVDSM 5V
edge 4) output and LVDSH
3.3V input
MRST hold from SCLK latching t53 SR -6 - - ns CL=25pF; LVDSM 5V
edge output and LVDSH
3.3V input
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
Table 3-68 Master Mode MP+sm/MPRsm output pads for data and clock
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
1)
SCLKO clock period t50 CC 100 - - ns CL=50pF
Deviation from the ideal duty t500 CC -3 - 7 ns 0 < CL < 200pF
cycle 2) 3)
MTSR delay from SCLKO t51 CC -17 - 17 ns CL=50pF
shifting edge
SLSOn deviation from the ideal t510 CC -17 - 17 ns MP+sm; CL=50pF
programmed position -22 - 2 ns MPss; CL=50pF
0 - 70 ns MP+m; MPm; LPm;
CL=50pF
MRST setup to SCLK latching t52 SR 85 4)5) - - ns CL=50pF
edge 4)
MRST hold from SCLK latching t53 SR -10 4)5) - - ns CL=50pF
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
t50
t500
0.5 VEXT/FLEX
SCLK1)2)
t51 SAMPLING POINT
t52
t53
MRST1) Data valid Data valid
t510
0.5 VEXT/FLEX
SLSOn2)
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay).
2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0.
QSPI_TmgMM.vsd
t55 t55
t56 t56
t57 t57
MTSR 1) Data Data
valid valid
t60 t60
1)
MRST 0.5 VEXT/FLEX
t58
t61 t59
SLSI
The following section defines the timings for 5V pad power supply.
Note: Pad asymmetry is already included in the following timings.
Note: Load for LVDS pads are defined as differential loads in the following timings.
4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
6) From FCLP rising edge.
7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care
that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in
the middle of the bit are not violated.
ALT1
FCLN ALTx LVDSM
FCLP ALTy
FCLND
FCLN
ALT7
PAD
ALT1
SON ALTx LVDSM
SOP ALTy
SOND
SON
ALT7
PAD
ALT1
EN0 ALTx
CMOS
ALTy
EN1
ALT7
PAD
EN2
ALT1
ALTx
EN3 CMOS
ALTy
MSC ALT7
PAD
_DoublePath_4a.vsd
Table 3-75 MPss clock/data (LVDS pads in CMOS mode, option EN01)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
1) 2) 3)
FCLPx clock period t40 CC 2 * TA - - ns MPss; CL=50pF
Deviation from ideal duty cycle t400 CC -2 - 6+0.035 * ns MPss; 0 < CL < 100pF
4) 5)
CL
SOPx output delay 6) t44 CC -4 - 7 ns MPss; CL=50pF
Table 3-75 MPss clock/data (LVDS pads in CMOS mode, option EN01) (cont’d)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
6)
ENx output delay t45 CC -5 - 7 ns MP+ss/MPRss;
CL=50pF
-2 - 15 ns MP+sm/MPRsm;
CL=50pF
-4 - 10 ns MPss; CL=50pF
0 - 30 ns MPsm; CL=50pF;
except pin P13.0
0 - 31 ns MPsm; CL=50pF; pin
P13.0
6 - 45 ns MPm/MP+m/MPRm;
CL=50pF
-11 - 2 ns MP+ss/MPRss;
CL=0pF
-4 - 7 ns MP+sm/MPRsm;
CL=0pF
-10 - 2 ns MPss; CL=0pF
-1 - 16 ns MPsm; CL=0pF
-2 - 18 ns MP+m/MPm/MPRm;
CL=0pF
SDI bit time t46 CC 8 * tMSC - - ns Upstream Timing
7)
SDI rise time t48 SR - - 200 ns Upstream Timing
7)
SDI fall time t49 SR - - 200 ns Upstream Timing
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) TA depends on the clock source selected for baud rate generation in the ABRA block of the MSC.
3) FCLP signal high and low can be minimum 1 * TMSC.
4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
6) From FCLP rising edge.
7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care
that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in
the middle of the bit are not violated.
t40
t400
FCLP
t44 t44
SOP
t45 t45
EN 0.5 VEXT/FLEX
t48 t49
0.9 VEXT/FLEX
SDI 0.1 VEXT/FLEX
The following section defines the timings for 3.3V pad power supply.
Note: Pad asymmetry is already included in the following timings.
Note: Load for LVDS pads are defined as differential loads in the following timings.
Table 3-79 MPss clock/data (LVDS pads in CMOS mode, option EN01)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
1) 2) 3)
FCLPx clock period t40 CC 2 * TA - - ns MPss; CL=50pF
Deviation from ideal duty cycle t400 CC -5 - 7+0.07 * ns MPss; 0 < CL < 100pF
4) 5)
CL
Table 3-79 MPss clock/data (LVDS pads in CMOS mode, option EN01) (cont’d)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
6)
SOPx output delay t44 CC -7 - 12 ns MPss; CL=50pF
6)
ENx output delay t45 CC -9 - 12 ns MP+ss/MPRss;
CL=50pF
-4 - 26 ns MP+sm/MPRsm;
CL=50pF
-7 - 17 ns MPss; CL=50pF
0 - 54 ns MPsm; CL=50pF;
except pin P13.0
0 - 58 ns MPsm; CL=50pF; pin
P13.0
4 - 77 ns MPm/MP+m/MPRm;
CL=50pF
-19 - 4 ns MP+ss/MPRss;
CL=0pF
-7 - 12 ns MP+sm/MPRsm;
CL=0pF
-17 - 4 ns MPss; CL=0pF
-2 - 28 ns MPsm; CL=0pF
-4 - 31 ns MP+m/MPm/MPRm;
CL=0pF
SDI bit time t46 CC 8 * tMSC - - ns Upstream Timing
7)
SDI rise time t48 SR - - 200 ns Upstream Timing
7)
SDI fall time t49 SR - - 200 ns Upstream Timing
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) TAmin = TMAX. When TMAX = 100 MHz,t40 = 20 ns
3) FCLP signal high and low can be minimum 1 * TMSC.
4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
6) From FCLP rising edge.
7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care
that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in
the middle of the bit are not violated.
t40
t400
FCLP
t44 t44
SOP
t45 t45
EN 0.5 VEXT/FLEX
t48 t49
0.9 VEXT/FLEX
SDI 0.1 VEXT/FLEX
2.0 V 2.0 V
ETH I/O
0.8 V 0.8 V
tR tF
ETH_Testpoints.vsd
t1
t3 t2
ETH_MDC
ETH_MDIO
sourced by controller :
ETH_MDC
t4 t5
ETH_MDIO
(output ) Valid Data
ETH_MDC
t6
ETH_MDIO
(input ) Valid Data
ETH_Timing-Mgmt.vsd
t7
t9 t8
ETH_MII_RX_CLK
ETH_MII_TX_CLK
ETH_MII_RX_CLK
t1 0 t1 1
ETH_MII_RXD[3:0]
ETH_MII_RX_DV Valid Data
ETH_MII_RX_ER
(sourced by PHY )
ETH_MII_TX_CLK
t1 2
ETH_MII_TXD[3:0] Valid Data
ETH_MII_TXEN
(sourced by controller )
ETH_Timing-MII.vsd
t1 3
t1 5 t14
ETH_RMII_REF_CL
ETH_RMII_REF_CL
t1 6 t17
ETHTXEN,
ETHTXD[1:0],
ETHRXD[1:0], Valid Data
ETHCRSDV,
ETH_Timing-RMII .vsd
ETHRXER
Program Flash program and erase operation is only allowed up the TJ = 150°C.
292 x
0 .5 ±0.05
0.15 M C A B
17 ±0. 1 1 .7 MAX 0.08 M C
B A
20
19
0.1 C 18
17
16
15
19 x 0 .8 = 1 5.2
14
13
1 7 ±0.1
CODE 12
11
10
9
8
7
292 x 6
0 .8
0.15 5
4
COPLANARITY 3
SEATIN G PLAN E
2
1
Y W V U T R P N M L K J HG F E D C B A
INDEX
INDEX MARKING
0.8 MARKING
(LASERED )
19 x 0.8 = 15 .2
C 0.33 MIN
STANDOFF
4 History