The document contains questions and answers related to electronics topics like CMOS circuits, MOSFETs, VLSI design, and simulation. Some key points covered are:
1) The speed of CMOS logic gates depends on factors like load capacitance and supply voltage.
2) Dynamic power dissipation in CMOS occurs due to switching transient currents when charging and discharging load capacitance.
3) MOSFETs can be used as active resistors in applications like transmission gates and simulating resistors in integrated circuit designs.
The document contains questions and answers related to electronics topics like CMOS circuits, MOSFETs, VLSI design, and simulation. Some key points covered are:
1) The speed of CMOS logic gates depends on factors like load capacitance and supply voltage.
2) Dynamic power dissipation in CMOS occurs due to switching transient currents when charging and discharging load capacitance.
3) MOSFETs can be used as active resistors in applications like transmission gates and simulating resistors in integrated circuit designs.
The document contains questions and answers related to electronics topics like CMOS circuits, MOSFETs, VLSI design, and simulation. Some key points covered are:
1) The speed of CMOS logic gates depends on factors like load capacitance and supply voltage.
2) Dynamic power dissipation in CMOS occurs due to switching transient currents when charging and discharging load capacitance.
3) MOSFETs can be used as active resistors in applications like transmission gates and simulating resistors in integrated circuit designs.
The document contains questions and answers related to electronics topics like CMOS circuits, MOSFETs, VLSI design, and simulation. Some key points covered are:
1) The speed of CMOS logic gates depends on factors like load capacitance and supply voltage.
2) Dynamic power dissipation in CMOS occurs due to switching transient currents when charging and discharging load capacitance.
3) MOSFETs can be used as active resistors in applications like transmission gates and simulating resistors in integrated circuit designs.
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1)
In accordance to the scaling technology, the total delay of the
logic circuit depends on ______
a. The capacitor to be charged
b. The voltage through which capacitance must be charged c. Available current d. All of the above
2) In CMOS circuits, which type of power dissipation occurs due to
switching of transient current and charging & discharging of load capacitance?
a. Static dissipation b. Dynamic dissipation c. Both a and b d. None of the above
3) In high noise margin (NMH), the difference in magnitude between
the maximum HIGH output voltage of driving gate and the maximum HIGH voltage is recognized by the _________gate.
a. Driven b. Receiving c. Both a and b d. None of the above
4) Which factor/s play/s a crucial role in determining the speed of
CMOS logic gate?
a. Load capacitance b. Supply voltage c. Gain factor of MOS d. All of the above
5) An ideal op-amp has ________
a. Infinite input resistance
b. Infinite differential voltage gain c. Zero output resistance d. All of the above
6) On the basis of an active load, which type of inverting CMOS
amplifier represents low gain with highly predictable small and large signal characteristics?
a. Active PMOS load inverter
b. Current source load inverter c. Push-pull inverter d. None of the above
7) In MOS devices, the current at any instant of time is ______of the voltage across their terminals.
a. constant & dependent
b. constant & independent c. variable & dependent d. variable & independent
8) Which among the following is/are regarded as an/the active
resistor/s?
a. MOS diode b. MOS transistor c. MOS switch d. All of the above
9) In MOS switch, clock feedthrough effect is also known as
__________.
A. charge injection B. charge feedthrough C. charge carrier D. charge ejaculation
a. A & B b. B & C c. C & D d. B & D
10) Which among the following can be regarded as an/the
application/s of MOS switch in an IC design?
a. Multiplexing & Modulation
b. Transmission gate in digital circuits c. Simulation of a resistor d. All of the above 1) In accordance to the scaling technology, the total delay of the logic circuit depends on ______
a. The capacitor to be charged
b. The voltage through which capacitance must be charged c. Available current d. All of the above
2) In CMOS circuits, which type of power dissipation occurs due to
switching of transient current and charging & discharging of load capacitance?
a. Static dissipation b. Dynamic dissipation c. Both a and b d. None of the above
3) In high noise margin (NMH), the difference in magnitude between
the maximum HIGH output voltage of driving gate and the maximum HIGH voltage is recognized by the _________gate.
a. Driven b. Receiving c. Both a and b d. None of the above
4) Which factor/s play/s a crucial role in determining the speed of
CMOS logic gate?
a. Load capacitance b. Supply voltage c. Gain factor of MOS d. All of the above
5) For complex gate design in CMOS, OR function needs to be implemented by _
connection/s of MOS.
a. Series b. Parallel c. Both series and parallel d. None of the above 6) In pull-up network, PMOS transistors of CMOS are connected in parallel with the provision of conducting path between output node & Vdd yielding _____ output.
a. 1 b. 0 c. Both a and b d. None of the above
7) In CMOS inverter, the propagation delay of a gate is the/an
_________ transition delay time for the signal during propagation from input to output especially when the signal changes its value.
a. Highest b. Average c. Lowest d. None of the above
8) In DIBL, which among the following is/are regarded as the
source/s of leakage?
a. Subthreshold conduction b. Gate leakage c. Junction leakage d. All of the above
9) In enhancement MOSFET, the magnitude of output current
__________ due to an increase in the magnitude of gate potentials.
a. Increases b. Remains constant c. Decreases d. None of the above
10) Which type of MOSFET exhibits no current at zero gate voltage?
a. Depletion MOSFET b. Enhancement MOSFET c. Both a and b d. None of the above The utilization of CAD tools for drawing timing waveform diagram and transforming it into a network of logic gates is known as ________. a. Waveform Editor b. Waveform Estimator c. Waveform Simulator d. Waveform Evaluator
2) Which among the following is a process of transforming
design entry information of the circuit into a set of logic equations? a. Simulation b. Optimization c. Synthesis d. Verification
15) In synthesis process, the load attribute specify/ies the existing
amount of _________load on a particular output signal. a. Inductive b. Resistive c. Capacitive d. All of the above 16) Which attribute in synthesis process specify/ies the resistance by controlling the quantity of current it can source? a. Load attribute b. Drive attribute c. Arrival time attribute d. All of the above ANSWER: Drive attribute 17) Which type of digital systems exhibit the necessity for the existence of at least one feedback path from output to input? a. Combinational System b. Sequential system c. Both a and b d. None of the above 22) In fusible link technologies, the undesired fuses are removed by the pulse application of _____voltage & current to device input. a. Low b. Moderate c. High d. All of the above ANSWER: High 24) Before the commencement of design, the clocking strategy determine/s __________ a. Number of clock signals necessary for routing throughout the chip b. Number of transistors used per storage requirement c. Power dissipated by chip & the size of chip d. All of the above ANSWER: All of the above 27) Which type of MOSFET exhibits no current at zero gate voltage? a. Depletion MOSFET b. Enhancement MOSFET c. Both a and b d. None of the above ANSWER: Enhancement MOSFET 28) In enhancement MOSFET, the magnitude of output current __________ due to an increase in the magnitude of gate potentials. a. Increases b. Remains constant c. Decreases d. None of the above ANSWER: Increases 29) In DIBL, which among the following is/are regarded as the source/s of leakage? a. Subthreshold conduction b. Gate leakage c. Junction leakage d. All of the above ANSWER: All of the above 30) Which among the following can be regarded as an/the application/s of MOS switch in an IC design? a. Multiplexing & Modulation b. Transmission gate in digital circuits c. Simulation of a resistor d. All of the above ANSWER: All of the above 31) In MOS switch, clock feedthrough effect is also known as __________. A. charge injection B. charge feedthrough C. charge carrier D. charge ejaculation
a. A & B b. B & C c. C & D d. B & D ANSWER: A & B 32) Which among the following is/are regarded as an/the active resistor/s? a. MOS diode b. MOS transistor c. MOS switch d. All of the above ANSWER: MOS diode 44) After an initialization phase, the simulator enters the ______phase. a. Compilation b. Elaboration c. Execution d. None of the above ANSWER: Execution 46) An event is nothing but ______ target signal, which is to be updated. a. Fixed b. Change on c. Both a and b d. None of the above ANSWER: Change on 47) Which functions are performed by static timing analysis in simulation? a. Computation of delay for each timing path b. Logic analysis in a static manner c. Both a and b d. None of the above ANSWER: Both a and b 59) In signal integrity, which noise/s occur/s due to impedance mismatch, stubs, vias and other interconnection discontinuities? a. Power/Ground Noise b. Crosstalk Noise c. Reflection Noise d. All of the above ANSWER: Reflection Noise 60) In floorplanning, placement and routing are __________ tools. a. Front end b. Back end c. Both a and b d. None of the above ANSWER: Back end 61) In floorplanning, which phase/s play/s a crucial role in minimizing the ASIC area and the interconnection density? a. Placement b. Global Routing c. Detailed Routing d. All of the above ANSWER: Placement 62) In CMOS inverter, the propagation delay of a gate is the/an _________ transition delay time for the signal during propagation from input to output especially when the signal changes its value. a. Highest b. Average c. Lowest d. None of the above ANSWER: Average 63) In pull-up network, PMOS transistors of CMOS are connected in parallel with the provision of conducting path between output node & Vdd yielding _____ output. a. 1 b. 0 c. Both a and b d. None of the above ANSWER: 1 64) For complex gate design in CMOS, OR function needs to be implemented by _______ connection/s of MOS. a. Series b. Parallel c. Both series and parallel d. None of the above ANSWER: Parallel 65) In MOS devices, the current at any instant of time is ______of the voltage across their terminals. a. constant & dependent b. constant & independent c. variable & dependent d. variable & independent ANSWER: constant & independent 66) On the basis of an active load, which type of inverting CMOS amplifier represents low gain with highly predictable small and large signal characteristics? a. Active PMOS load inverter b. Current source load inverter c. Push-pull inverter d. None of the above ANSWER: Active PMOS load inverter 67) An ideal op-amp has ________ a. Infinite input resistance b. Infinite differential voltage gain c. Zero output resistance d. All of the above ANSWER: All of the above 68) Stuck open (off) fault occur/s due to _________ a. An incomplete contact (open) of source to drain node b. Large separation of drain or source diffusion from the gate c. Both a and b d. None of the above ANSWER: Both a and b 84) Which level of routing resources are supposed to be the dedicated lines allowing output of each tile to connect directly to every input of eight surrounding tiles? a. Ultra-fast local resources b. Efficient long-line resources c. High speed, very long-line resources d. High performance global networks ANSWER: Ultra-fast local resources 87) In a chip, which type/s of pad design/s is/are adopted to solve the problem of pin count? a. Input pad design b. Output pad design c. Three state pad design d. All of the above ANSWER: Three state pad design 88) The power consumption of static CMOS gates varies with the _____ of power supply voltage. a. square b. cube c. fourth power d. 1/8 th power ANSWER: square 89) Which factor/s play/s a crucial role in determining the speed of CMOS logic gate? a. Load capacitance b. Supply voltage c. Gain factor of MOS d. All of the above ANSWER: All of the above 90) In high noise margin (NMH), the difference in magnitude between the maximum HIGH output voltage of driving gate and the maximum HIGH voltage is recognized by the _________gate. a. Driven b. Receiving c. Both a and b d. None of the above ANSWER: Receiving 91) In CMOS circuits, which type of power dissipation occurs due to switching of transient current and charging & discharging of load capacitance? a. Static dissipation b. Dynamic dissipation c. Both a and b d. None of the above ANSWER: Dynamic dissipation 92) In accordance to the scaling technology, the total delay of the logic circuit depends on ______ a. The capacitor to be charged b. The voltage through which capacitance must be charged c. Available current d. All of the above ANSWER: All of the above 93) In two-stage op-amp, what is the purpose of compensation circuitry? a. To provide high gain b. To lower output resistance & maintain large signal swing c. To establish proper operating point for each transistor in its quiescent state d. To achieve stable closed-loop performance ANSWER: To achieve stable closed-loop performance 94) According to the principle of current mirror, if gate-source potentials of two identical MOS transistors are equal, then the channel currents should be _______ a. Equal b. Different c. Both a and b d. None of the above ANSWER: Equal 95) PSSR can be defined as the product of the ratio of change in supply voltage to change in output voltage of op-amp caused by the change in power supply & _______ of op-amp. a. Open-loop gain b. Closed-loop gain c. Both a and b d. None of the above ANSWER: Open-loop gain 96) Which among the following serves as an input stage to most of the op-amps due to its compatibility with IC technology? a. Differential amplifier b. Cascode amplifier c. Operational transconductance amplifiers (OTAs) d. Voltage operational amplifier ANSWER: Differential amplifier 97) Which among the following is/are responsible for the occurrence of ‘Delay Faults’? a. Variations in circuit delays & clock skews b. Improper estimation of on-chip interconnect & routing delays c. Aging effects & opens in metal lines connecting parallel transistors d. All of the above ANSWER: All of the above 98) Due to the limitations of the testers, the functional test is usually performed at speed _______the target speed. a. Lower than b. Equal to c. Greater than d. None of the above ANSWER: Lower than
