Hi3518E V200 Economical HD IP Camera SoC

Brief Data Sheet

Issue 02

Date 2015-12-28
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 Hi3518E V200
Hi3518E V200 Economical HD IP Camera SoC
Brief Data Sheet
Key Specifications z Echo cancellation, noise suppression, and automatic gain
Security Engine
Processor Core
z AES, DES, 3DES, and RSA encryption/decryption
z ARM926@540 MHz, 32 KB I-cache, 32 KB D-cache algorithms implemented by hardware
Video Encoding z Hash digest tamper proofing implemented by hardware
z H.264 main/high profile L4.0 z Integrated 512-bit OTP storage space and hardware
z H.264 baseline encoding random number generator
z MJPEG/JPEG baseline encoding Video Interfaces
Video Encoding Performance z VI interfaces
z A maximum of 2-megapixel resolution for H.264 − 8-, 10-, 12-, or 14-bit RGB Bayer/RGB-IR inputs,
encoding maximum clock frequency of 100 MHz
z Real-time H.264 & JPEG encoding of multiple streams: − BT.601, BT.656, and BT.1120 VI interfaces
720p@30 fps+VGA@30 fps+QVGA@30 fps+720p@1 − 4-Lane MIPI/HiSPI/LVDS VI interfaces
fps JPEG snapshot − Compatibility with mainstream HD CMOS sensors
z 2 megapixels@5 fps JPEG snapshot provided by Sony, Aptina, OmniVision, and Panasonic
z CBR or VBR with the output bit rate ranging from 2 kbit/s − Various sensor levels supported
to 100 Mbit/s − Programmable sensor clock output
z Encoding frame rate ranging from 1/16 fps to 30 fps − Maximum input resolution of 2 (1920*1080)
z Encoding of eight ROIs megapixels
z OSD overlaying of eight regions before encoding z VO interfaces
− One BT.656 VO interface supporting 8-bit serial LCD
Intelligent Video Analysis
outputs
z Integrated IVE, supporting various intelligent analysis
Audio Interfaces
applications such as motion detection, perimeter defense,
z Integrated audio CODEC that supports 16-bit audio inputs
and video diagnosis
and outputs
Video and Graphics Processing z Mono-channel differential microphone inputs for reducing
z Video pre-processing, including 3D denoising, image the background noises
enhancement, and edge enhancement z I2S input
z Anti-flicker for output videos and graphics Peripheral Interfaces
z 1/15x to 16x video scaling z POR
z 1/2x to 2x graphics scaling z One integrated high-precision RTC
z OSD overlaying of eight regions before encoding z One 4-channel SAR ADC
z Hardware graphics overlaying for videos at the video layer z Three UART interfaces
and graphics layer 1 during post-processing z IR interfaces, I2C interfaces, SPI master interfaces, and
ISP GPIO interfaces
z 2x2 Pattern RGB-IR sensor z Four PWM interfaces
z Adjustable 3A (AE, AF, and AWB) functions z Two SDIO interfaces, one of which supports SD 3.0
z Highlight compensation, backlight compensation, gamma z One USB 2.0 interface that supports the host/device mode
correction, and color enhancement z RMII in 10/100 Mbit/s full-duplex or half-duplex mode,
z Defect pixel correction, denoising, and digital image TSO network acceleration, and PHY clock output
stabilization External Memory Interfaces
z Anti-fog z DDR2 SDRAM interface
z Lens distortion correction − Embedded 512 Mbits, 16-bit DDR2 SDRAM
z Picture rotation by 90° or 270° − Maximum frequency of 360 MHz
z Mirroring and flipping z SPI NOR flash interface
z Build-in WDR and tone mapping − 1-, 2-, or 4-bit SPI NOR flash interface
z ISP tuning tools for the PC z SPI NAND flash interface
− Maximum capacity of 4 Gbits
Audio Encoding/Decoding
z eMMC 5.0 interface
z Voice encoding/decoding complying with multiple
− Maximum capacity of 64 GB
protocols by using software
z Booting from the SPI NOR flash, SPI NAND flash, or
z G.711, ADPCM, and G.726 protocols supported
eMMC

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 Hi3518E V200
Hi3518E V200 Economical HD IP Camera SoC
Brief Data Sheet
SDK
z Linux 3.4-based SDK
z High-performance H.264 PC decoding library
Physical Specifications
z Power consumption
− Typical power consumption of 700 mW (including
DDR2 SDRAM)
− Multi-level power saving mode
z Operating voltages
− 1.1 V core voltage
− 3.3 V I/O voltage and 3.8 V margin voltage
z Package
− Body size of 10 mm x 10 mm (0.39 in. x 0.39 in.), 0.65
mm (0.03 in.) ball pitch, TFBGA RoHS package with
192 pins

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 Hi3518E V200
Hi3518E V200 Economical HD IP Camera SoC
Brief Data Sheet

Functional Block Diagram

ARM Subsystem Image Subsystem

TDE + IVE LCD/

DDRC ARM926@540MHz BT656
(32K ICache/32K DCache)
VPSS + VGS
MIPI/
ISP LVDS/
SDIOx2 (3A\WDR) Hispi

FMC
AMBA3.0 BUS

eMMC RTC

I2C/I2S
Video Subsystem
MAC
H264 BP/MP/HP SSP
MJPEG/JPEG
Encoder GPIOs
USB 2.0
Host/Device IR
AES/DES/3DES/RSA/
HASH/OTP/TRNG UARTx3
Audio
I2S
CODEC PWMx4
SAR-
ADCx4

Hi3518E V200 is a new-generation SoC designed for the HD IP camera. It has an integrated new-generation ISP and H.264 encoder.
It uses the optimized picture processing algorithm before encoding, advanced low-power technology, and low-power architecture
design. These designs and functions enable Hi3518E V200 to feature industry-leading low bit rate, high picture quality, and low
power consumption. It supports 90° or 270° rotation and lens distortion correction by using hardware, which meets requirements in
various surveillance application scenarios. It also supports 3A algorithms, which allow customers to design various types of IP
cameras including the movement of the integrated camera. Hi3518E V200 integrates the POR, RTC as well as audio CODEC and
supports various sensor levels and clock outputs, which significantly reduces the EBOM costs for the Hi3518E V200 HD IP camera.
Similar to other HiSilicon DVR and NVR SDKs, the Hi3518E V200 SDK supports rapid mass production and the system layout of
IP cameras, DVRs, and NVRs.

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Copyright © HiSilicon Technologies Co., Ltd
 Hi3518E V200
Hi3518E V200 Economical HD IP Camera SoC
Brief Data Sheet
Hi3518E V200 Economical HD IP Camera Solution

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 Hi3518E V200
Hi3518E V200 Economical HD IP Camera SoC
Brief Data Sheet

Acronyms and Abbreviations

3DES triple data encryption standard

ADPCM adaptive differential pulse code modulation

AE automatic exposure

AES advanced encryption standard

AF automatic focus

AWB automatic white balance

CBR constant bit rate

CODEC coder/decoder

DDR double data rate

DES data encryption standard

DVR digital video recorder

EBOM engineering bill of materials

eMMC embedded multimedia card

GPIO general-purpose input/output

HD high definition

HiSPI high-speed serial pixel interface

I2C inter-integrated circuit

I2S inter-IC sound

IR infrared

ISP image signal processor

IVE intelligent video engine

LCD liquid crystal display

LVDS low-voltage differential signaling

MIPI mobile industry processor interface

NVR network video recorder

OSD on-screen display

OTP one-time programming

POR power-on reset

PWM pulse-width modulation

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Copyright © HiSilicon Technologies Co., Ltd
 Hi3518E V200
Hi3518E V200 Economical HD IP Camera SoC
Brief Data Sheet
RGB red-green-blue

RMII reduced media independent interface

RoHS Restriction of Hazardous Substances

ROI region of interest

RSA Rivest-Shamir-Adleman

RTC real-time clock

SAR ADC successive approximation register analog-to-digital converter

SDIO secure digital input/output

SDK software development kit

SDRAM synchronous dynamic random access memory

SoC system-on-chip

SPI serial peripheral interface

TFBGA thin & fine-pitch ball grid array

TSO TCP segmentation offload

UART universal asynchronous receiver transmitter

VBR variable bit rate

VGA video graphics array

VI video input

VO video output

WDR wide dynamic range

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