Phy Interface Pci Express Sata Usb3 1 Architectures 4 2
Phy Interface Pci Express Sata Usb3 1 Architectures 4 2
Phy Interface Pci Express Sata Usb3 1 Architectures 4 2
For the
PCI Express, SATA, and USB 3.03.1
Architectures
Version 4.20
Notice: Implementations developed using the information provided in this specification may
infringe the patent rights of various parties including the parties involved in the development of
this specification. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights (including without limitation rights under any party’s patents) are granted herein.
All product names are trademarks, registered trademarks, or service marks of their respective
owners
Contributors
Jeff Morris Jim Choate
Andy Martwick Paul Mattos
Brad Hosler Dan Froelich
Matthew Myers Duane Quiet
Bob Dunstan Hajime Nozaki
Saleem Mohammad Peter Teng
Sue Vining Karthi Vadivelu
Tadashi Iwasaki Mineru Nishizawa
Yoichi Iizuka Takanori Saeki
Rahman Ismail Andrew Lillie
Ben Graniello Frank Kavanagh
Table of Contents
1 Preface ...................................................................................................................................... 7
1.1 Scope of this Revision ...................................................................................................... 7
1.2 Revision History ............................................................................................................... 7
2 Introduction .............................................................................................................................. 9
2.1 PCI Express PHY Layer ................................................................................................. 11
2.2 USB PHY Layer ............................................................................................................. 11
2.3 SATA PHY Layer ........................................................................................................... 12
3 PHY/MAC Interface .............................................................................................................. 12
4 PCI Express and USB PHY Functionality ............................................................................. 16
4.1 Transmitter Block Diagram (2.5 and 5.0 GT/s) .............................................................. 17
4.2 Transmitter Block Diagram (8.0/10 GT/s) ...................................................................... 17
4.3 Receiver Block Diagram (2.5 and 5.0 GT/s) .................................................................. 18
4.4 Receiver Block Diagram (8.0/10.0 GT/s) ....................................................................... 19
4.5 Clocking .......................................................................................................................... 20
5 SATA PHY Functionality ...................................................................................................... 20
5.1 Transmitter Block Diagram (1.5, 3.0, and 6.0 GT/s) ..................................................... 21
5.2 Receiver Block Diagram (1.5, 3.0 and 6.0 GT/s) ........................................................... 22
5.3 Clocking .......................................................................................................................... 22
6 PIPE Interface Signal Descriptions ........................................................................................ 23
6.1 PHY/MAC Interface Signals .......................................................................................... 23
6.2 External Signals .............................................................................................................. 49
7 PIPE Operational Behavior .................................................................................................... 51
7.1 Clocking .......................................................................................................................... 51
7.2 Reset................................................................................................................................ 51
7.3 Power Management – PCI Express Mode ...................................................................... 52
7.4 Power Management – USB Mode .................................................................................. 54
7.5 Power Management – SATA Mode ................................................................................ 55
7.6 Changing Signaling Rate, PCLK Rate, or Data Bus Width ............................................ 56
7.6.1 PCI Express Mode ................................................................................................... 56
7.6.2 USB Mode ............................................................................................................... 56
7.6.3 SATA Mode ............................................................................................................ 57
7.6.4 Fixed data path implementations ............................................................................. 58
7.6.5 Fixed PCLK implementations ................................................................................. 58
7.7 Transmitter Margining – PCI Express Mode and USB Mode ........................................ 59
7.8 Selectable De-emphasis – PCI Express Mode ................................................................ 59
7.9 Receiver Detection – PCI Express Mode and USB Mode .............................................. 60
7.10 Transmitting a beacon – PCI Express Mode ............................................................... 61
7.11 Transmitting LFPS – USB Mode ................................................................................ 61
7.12 Detecting a beacon – PCI Express Mode .................................................................... 62
7.13 Detecting Low Frequency Periodic Signaling – USB Mode....................................... 62
7.14 Clock Tolerance Compensation .................................................................................. 62
7.15 Error Detection ............................................................................................................ 64
7.15.1 8B/10B Decode Errors ............................................................................................. 65
7.15.2 Disparity Errors ....................................................................................................... 65
7.15.3 Elastic Buffer Errors ................................................................................................ 66
7.16 Loopback ..................................................................................................................... 67
7.17 Polarity Inversion – PCI Express and USBModes ...................................................... 69
7.18 Setting negative disparity (PCI Express Mode) .......................................................... 69
7.19 Electrical Idle – PCI Express Mode ............................................................................ 70
Table of Figures
Figure 2-1: Partitioning PHY Layer for PCI Express.................................................................... 10
Figure 2-2 Partitioning PHY Layer for USB ................................................................................. 10
Figure 3-1: PHY/MAC Interface ............................................................................................... 12
Figure 4-1: PHY Functional Block Diagram................................................................................. 16
Figure 4-2: Transmitter Block Diagram ................................................................................... 17
Figure 4-3: Transmitter Block Diagram (8.0/10 GT/s) ............................................................ 17
Figure 4-4: Receiver Block Diagram ......................................................................................... 18
Figure 4-5: Receiver Block Diagram (8.0 GT/s) ....................................................................... 19
Figure 4-6: Clocking and Power Block Diagram ...................................................................... 20
Figure 5-1: PHY Functional Block Diagram................................................................................. 20
Figure 5-2: Transmitter Block Diagram (1.5, 3.0, and 6.0 GT/s) ............................................ 21
Figure 5-3: Receiver Block Diagram (1.5, 3.0 and 6.0 GT/s) ................................................... 22
Figure 5-4: Clocking and Power Block Diagram .......................................................................... 22
Figure 6-1 – PCI Express 3.0 Example Timings For BlockAlignControl ..................................... 48
Figure 7-1 PCI Express P2 Entry and Exit with PCLK as PHY Output ....................................... 53
Figure 7-2PCI Express P2 Entry and Exit with PCLK as PHY Input ........................................... 54
Figure 7-3 Change from PCI Express 2.5 Gt/s to 5.0 Gt/s with PCLK as PHY Input. ................. 58
Figure 7-5 – PCI Express 3.0 Successful Equalization Evaluation Request ................................. 71
Figure 7-6 – PCI Express 3.0 Equalization Evaluation Request Resulting in Invalid Feedback .. 72
Figure 7-7 – PCI Express 3.0 TxDataValid Timing for 8 Bit Wide TxData Interface .................. 81
Figure 7-8 – PCI Express 3.0 TxDataValid Timing for 16 Bit Wide TxData Interface ................ 81
Figure 7-9 – PCI Express 3.0 RxDataValid Timing for 16 Bit Wide RxData Interface ............... 81
Table of Tables
Table 3-2. PCI Express Mode - Possible PCLK rates and data widths ........................................ 15
3-3. USB Mode – Possible PCLK rates and data widths.............................................................. 15
Table 6-1: Transmit Data Interface Signals................................................................................... 23
Table 6-2: Receive Data Interface Signals .................................................................................... 24
Table 6-3: Command Interface Signals ......................................................................................... 26
Table 6-4: Status Interface Signals ................................................................................................ 44
Table 6-5: External Signals ........................................................................................................... 49
1 Preface
1.1 Scope of this Revision
The PCI Express, SATA and USB SuperSpeed PHY Interface Specification has definitions of all
functional blocks and signals. This revision includes support for PCI Express implementations
conforming to the PCI Express Base Specification, Revision 3.0, SATA implementations
conforming to the SATA specification, revision 3.0, and USB implementations conforming to the
Universal Serial Bus Specification, Revision 3.0.
0.95 4/25/03 Updates to reflect 1.0a Base Spec. Added multilane suggestions.
1.86 2/27/2006 Fixed up more areas based on feedback. Added a section on how
to handle CLKREQ#.
1.87 9/28/2006 Removed references to Compliance Rate determination. Added
sections for TX Margining and Selectable De-emphasis. Fixed up
areas (6.4) based on feedback.
1.90 3/24/2007 Minor updates, mostly editorial.
2.7 12/31/200 Initial draft of updates to support the USB specification, revision
3.0.
7
2.71 1/21/2008 Updates for SKP handling and USB SuperSpeed PHY power
management.
2.75 2/8/08 Additional updates for SKP handling.
2.90 8/11/08 Added 32 bit data interface support for USB SuperSpeed mode,
support for USB SuperSpeed mode receiver equalization training,
and support for USB SuperSpeed mode compliance patterns that
are not 8b/10b encoded.
Solid enough for implementation architectures to be finalized.
3.0 3/11/09 Final update
4.0 4/13/11 Draft 3 update adding PCI Express 3.0 rev .9.
4.0 9/1/11 Draft 6 update adding updates based on PCI Express 3.0 rev .9
feedback.
4.1 12/7/11 Initial draft with per lane clocking option
4.1 12/12/11 Draft 2. Updates for initial review feedback and addition of several
example timing diagrams for PCI Express 3.0 related signals.
4.1 5/21/12 Updated for Draft 2 feedback from various reviewers.
4.2 7/1/13 Added support for USB 3.1 – preliminary review release based on
USB 3.1 specification revision .9
2 Introduction
The PHY Interface for the PCI Express, SATA, and USB SuperSpeed Architectures (PIPE) is
intended to enable the development of functionally equivalent PCI Express, SATA and USB
SuperSpeed PHY's. Such PHY's can be delivered as discrete IC's or as macrocells for inclusion in
ASIC designs. The specification defines a set of PHY functions which must be incorporated in a
PIPE compliant PHY, and it defines a standard interface between such a PHY and a Media
Access Layer (MAC) & Link Layer ASIC. It is not the intent of this specification to define the
internal architecture or design of a compliant PHY chip or macrocell. The PIPE specification is
defined to allow various approaches to be used. Where possible the PIPE specification references
the PCI Express base specification, SATA 3.0 Specification or USB 3.10 Specification rather
than repeating its content. In case of conflicts, the PCI-Express Base Specification, SATA 3.0
specification and USB 3.10 Specification shall supersede the PIPE spec.
This spec provides some information about how the MAC could use the PIPE interface for
various LTSSM states, Link states and other protocols. This information should be viewed as
‘guidelines for’ or as ‘one way to implement’ base specification requirements. MAC
implementations are free to do things in other ways as long as they meet the corresponding
specification requirements.
One of the intents of the PIPE specification is to accelerate PCI Express endpoint, SATA device
and USB SuperSpeed device development. This document defines an interface to which ASIC
and endpoint device vendors can develop. Peripheral and IP vendors will be able to develop and
validate their designs, insulated from the high-speed and analog circuitry issues associated with
the PCI Express, SATA or USB SuperSpeed PHY interfaces, thus minimizing the time and risk
of their development cycles.
The PIPE specification defines two clocking options for the interface. In the first alternative the
PHY provides a clock (PCLK) that clocks the PIPE interface as an output. In the second
alternative PCLK is provided to each lane of the PHY as an input. The alternative where PCLK
is provided to each lane of the PHY was add in the 4.1 revision of the PIPE specification. It
allows the controller or logic external to the PHY to more easily adjust timing of the PIPE
interface to meet timing requirements for silicon implementations. A PHY is only required to
support one of the timing alternatives. The two clocking options shall be referenced as “PCLK as
PHY Output” and “PCLK as PHY Input” respectively.
Figure 2-1 shows the partitioning described in this spec for the PCI Express Base Specification.
Figure 2-2 shows the paortitioning described in this spec for the USB 3.10 Specification.
To higher link,
transaction layers
Logical
Sub-block PHY/MAC Interface
Physical Layer
Specification
(Chapter 4
of base spec) Physical Coding 8b/10b code/decode
Sublayer elastic buffer
(PCS) Rx detection
Rx Tx
Channel
To higher link,
transaction layers
PHY/MAC Interface
8b/10b code/decode
Physical Coding 128b/130b code/decode
Sublayer (8 GT/s)
(PCS) elastic buffer
Rx detection
Physical
Layer
(Chapter 6) Analog buffers
Physical Media
Attachment Layer SERDES
(PMA) 10-bit interface or
130-bit interface (8 GT/s)
Rx Tx
Channel
Figure 2-22-2 Partitioning PHY Layer for USB SuperSpeed
3 PHY/MAC Interface
Figure 3-1 shows the data and logical command/status signals between the PHY and the
MAC layer. These signals are described in Section 5. Full support of PCI Express mode,
USB mode, or Sata mode at all rates require different numbers of control and status signals
to be implemented.requires 56 control signals and 6 Status signals. Full support of USB
SuperSpeed mode requires 16 control signals and 7 status signals. Full support of SATA at
all rates requires 19 control signals and 6 Status signals. Refer to Section 6.1 for details on
which specific signals are required for each operating mode.
CLK
32, 16 or 8
TxData
4, 2 or 1
TxDataK
Variable Tx+,Tx-
To Data Link Layer
Command
Variable Status
This specification allows several different PHY/MAC interface configurations to support various
signaling rates. For PIPE implementations that support only the 2.5 GT/s signaling rate in PCI
Express mode implementers can choose to have 16 bit data paths with PCLK running at 125
MHz, or 8 bit data paths with PCLK running at 250 MHz.
PIPE implementations that support 5.0 GT/s signaling and 2.5 GT/s signaling in PCI Express
mode, and therefore are able to switch between 2.5 GT/s and 5.0 GT/s signaling rates, can be
implemented in several ways. An implementation may choose to have PCLK fixed at 250 MHz
and use 8-bit data paths when operating at 2.5 GT/s signaling rate, and 16-bit data paths when
operating at 5.0 GT/s signaling rate. Another implementation choice is to use a fixed data path
width and change PCLK frequency to adjust the signaling rate. In this case, an implementation
with 8-bit data paths would provide PCLK at 250 MHz for 2.5 GT/s signaling and provide PCLK
at 500 MHz for 5.0 GT/s signaling. Similarly, an implementation with 16-bit data paths would
provide PCLK at 125 MHz for 2.5 GT/s signaling and 250 MHz for 5.0 GT/s signaling.
For PIPE implementations that support only 5.0 GT/s (USB SuperSpeed mode) and/or 10 GT/s
USB mode implementers can choose from options shown in table
3-3. A PIPE compliant MAC or PHY is only required to support one option for each USB
transfer speed that it supports..
For SATA PIPE implementations that support only the 1.5 GT/s signaling rate implementers can
choose to have 16 bit data paths with PCLK running at 75 MHz, or 8 bit data paths with PCLK
running at 150, 300 or 600 MHz. The 300 and 600 Mhz options requires the use of TxDataValid
and RxDataValid signals to toggle the use of data on the data bus.
SATA PIPE implementations that support 1.5 GT/s signaling and 3.0 GT/s signaling in SATA
mode, and therefore are able to switch between 1.5 GT/s and 3.0 GT/s signaling rates, can be
implemented in several ways. An implementation may choose to have PCLK fixed at 150 MHz
and use 8-bit data paths when operating at 1.5 GT/s signaling rate, and 16-bit data paths when
operating at 3.0 GT/s signaling rate. Another implementation choice is to use a fixed data path
width and change PCLK frequency to adjust the signaling rate. In this case, an implementation
with 8-bit data paths could provide PCLK at 150 MHz for 1.5 GT/s signaling and provide PCLK
at 300 MHz for 3.0 GT/s signaling. Similarly, an implementation with 16-bit data paths would
provide PCLK at 75 MHz for 1.5 GT/s signaling and 150 MHz for 3.0 GT/s signaling. The full
set of possible widths and PCLK rates for SATA mode are shown in Table 3-1 SATA Mode –
Possible PCLK rates and data widths
. A PIPE compliant MAC or PHY is only required to support one option for each SATA transfer
speed that it supports.
TxDataValid/RxDataValid
is asserted every PCLK to
indicate valid data.
1.5 GT/s SATA 150 Mhz 8 bits
Table 3-13-1 SATA Mode – Possible PCLK rates and data widths
Table 3-1 SATA Mode - Possible PCLK rates and data widths
Note: In SATA Mode if the PHY elasticity buffer is operating in nominal empty mode – then
RxDataValid may also be used when the EB is empty and no data is available.
The full set of possible widths and PCLK rates for PCI Express mode is shown in Table 3-2. A
PIPE compliant MAC or PHY is only required to support one option for each PCI Express
transfer speed that it supports.
Table 3-23-33-2. PCI Express Mode - Possible PCLK rates and data widths
RxDataValid is in a mode that does not use RxDataValid the PHY shall keep RxData valid
asserted.
There may be PIPE implementations that support multiples of the above configurations. PHY
implementations that support multiple configurations at the same rate must support the width and
PCLK rate control signals. A PHY that supports multiple rates in either PCI Express Mode or
SATA Mode or USB Mode must support configurations across all supported rates that are either
fixed data path width or fixed PCLK rate.
CLK
PCLK
PLL
32, 16 or 8
TxData
4, 2 or 1
TX BLOCK Tx+, Tx-
TxDataK
Command Variable
Variable Status
32, 16 or 8
RxData
4, 2 or 1
RX BLOCK Rx+, Rx-
RxDataK
Sections below provide descriptions of each of the blocks shown in Figure 4-1: PHY Functional
Block Diagram. These blocks represent high-level functionality that is required to exist in the
PHY implementation. These descriptions and diagrams describe general architecture and
behavioral characteristics. Different implementations are possible and acceptable.
x8
TxDataK
TxOnesZeroes (USB Only) 8b10b encoding
Bit rate clk / 10
TxCompliance
Loopback path x 10
from receiver
Bit rate clk
Parallel to Serial (2.5G or 5G)
TxMargin
TxElecIdle Transmitter Differential
TxDeemph (PCI Express Only)
TxDetectRx Driver TxSwing (PCI Express Only)
D+ D-
x8
TxDataK
128b130b encoding
TxSyncHeader Bit rate clk / 10
TxStartBlock
Loopback path X130/x132
from receiver
TxMargin (PCIe
TxElecIdle Transmitter Differential only)
TxDetectRx Driver TxDeemph
D+ D-
Recovered
Bit Clock
Data Recovery
Circuit (DRC)
x 10 Recovered
Symbol Clock
Buffer Overflow/Underflow
Elastic Buffer
SKP added/removed Receiver RxStatus
Status
Loopback path
to transmitter x 10
Decode Error
x8
8.0/10.0 GHz
Clock Recovery
Circuit
Recovered
Bit Clock
Data Recovery
Circuit (DRC)
x 10 Recovered
Symbol Clock
Buffer Overflow/Underflow
Elastic Buffer
SKP added/removed Receiver RxStatus
Status
Loopback path
to transmitter x130
Decode Error
128b 130b Decode
400/500 Disparity Error
128b 132b Decode
MHz
x128
Optional 8->16, 32
PCLK
Data
X32 or X16 or x8
4.5 Clocking
Bit Rate Clk
2.5, 5.0 or
8.0 GT/s
PCLK
CLK
PLL
Max PCLK
CLK
PCLK
PLL
32, 16 or 8
TxData
4, 2 or 1
TX BLOCK Tx+, Tx-
TxDataK
Command 15
6 Status
32, 16 or 8
RxData
4, 2 or 1
RX BLOCK Rx+, Rx-
RxDataK
Sections below provide descriptions of each of the blocks shown in Figure 5-1: PHY Functional
Block Diagram. These blocks represent high-level functionality that is required to exist in the PHY
implementation. These descriptions and diagrams describe general architecture and behavioral
characteristics. Different implementations are possible and acceptable.
x8
TxDataK
8b10b encoding
Bit rate clk / 10
TxCompliance
Loopback path x 10
from receiver
Bit rate clk (1.5G,
Parallel to Serial 3.0G or 6.0G)
D+ D-
Figure 5-25-2: Transmitter Block Diagram (1.5, 3.0, and 6.0 GT/s)
Recovered
Bit Clock
Data Recovery
Circuit (DRC)
x 10 Recovered
Symbol Clock
Buffer Overflow/Underflow
Elastic Buffer
SKP added/removed Receiver RxStatus
Status
Loopback path
to transmitter x 10
Decode Error
Figure 5-35-3: Receiver Block Diagram (1.5, 3.0 and 6.0 GT/s)
5.3 Clocking
The PHY input and output signals are described in the following tables. Note that Input/Output is
defined from the perspective of a PIPE compliant PHY component. Thus a signal described as an
“Output” is driven by the PHY and a signal described as an “Input” is received by the PHY. A
basic description of each signal is provided. More details on their operation and timing can be
found in following sections. All signals on the ‘parallel’ side of a PIPE implementation are
synchronous with PCLK, with exceptions noted in the tables below.
Table 6-15-1: Transmit Data Interface Signals
Active
Name Direction Description
Level
Tx+, Tx- Output N/A The PCI Express, SATA or USB SuperSpeed
differential outputs from the PHY. All
transmitters shall be AC coupled to the media.
See section 4.3.1.2 of the PCI Express Base
Specification or section 6.2.23.2.1 of the USB
3.10 Specification.
TxData[31:0] Input N/A Parallel PCI Express, SATA or USB
for 32-bit SuperSpeed data input bus. For the 16-bit
interface interface, 16 bits represent 2 symbols of
TxData[15:0] transmit data. Bits [7:0] are the first symbol to
for 16-bit be transmitted, and bits [15:8] are the second
interface symbol. For the 32-bit interface, 32 bits
TxData[7:0] represent the 4 symbols of transmit data. Bits
for 8-bit [23:16] are the third symbol to be transmitted,
interface and bits [31:24] are the fourth symbol. Bit zero
is the first to be transmitted.
TxDataK[3:0] Input N/A Data/Control for the symbols of transmit data.
for 32-bit For 32-bit interfaces, Bit 0 corresponds to the
interface low-byte of TxData, Bit3 corresponds to the
TxDataK[1:0] upper byte. For 16-bit interfaces, Bit 0
for 16-bit corresponds to the low-byte of TxData, Bit 1 to
interface the upper byte. A value of zero indicates a data
TxDataK for byte, a value of 1 indicates a control byte. Data
8-bit bytes are scrambled and control bytes are not.
interface
Not used in PCI Express mode at 8 GT/s.
Not used in USB mode at 10 GT/s.
TxDataValid Input N/A PCI Express Mode and SATA Mode and USB
Mode:
This signal allows the MAC to instruct the PHY
to ignore the data interface for one clock cycle.
A value of one indicates the phy will use the
data, a value of zero indicates the phy will not
use the data.
It is recommended that the MAC assert
TxDataValid at all times when the PHY is in
a mode that does not require the signal. All
PCI Express modes at 8 GT/s and all USB
modes at 10 GT/s use TxDataValid. Refer
to Table 3-1, Table 3-2, and
RxDataK[3:0] Output N/A Data/Control bit for the symbols of receive data.
for 32-bit For 32-bit interfaces, Bit 0 corresponds to the
interface low-byte of RxData, Bit3 corresponds to the
RxDataK[1:0] upper byte. For 16-bit interface, Bit 0
for 16-bit corresponds to the low-byte of RxData[15:0], Bit
interface 1 to the upper byte. A value of zero indicates a
RxDataK for data byte; a value of 1 indicates a control byte.
8-bit
interface Not used in PCI Express mode at 8 GT/s or
USB Mode at 10 GT/s.
Sata Mode:
Loopback support is optional for SATA PHYs.
Loopback is only valid in Sata Mode when
EncodeDecodeBypass is asserted. The RX
elasticity buffer must be active during
loopback. If the PHY runs out of data to
transmit during loopback – it must transmit
ALIGNs.
0 ALIGN
1 D24.3
2 D10.2
3 Reserved
Sata Mode:
Value Description
0 Use 1.5 GT/s signaling rate
1 Use 3.0 GT/s signaling rate
2 Use 6.0 GT/s signaling rate
3 Reserved
USB Mode:
Value Description
0 Use 5.0 GT/s signaling rate
1 Use 10.0 GT/s signaling rate
2 Reserved
3 Reserved
SATA Mode:
0 37.5 Mhz
1 75 Mhz
2 150 Mhz
3 300 Mhz
4 600 Mhz
5 Reserved
6 Reserved
7 Reserved
USB Mode:
0 125 Mhz
1 250 Mhz
2 312.5 Mhz (10 GT/s)
3 500 Mhz
4 625 Mhz (10 GT/s)
5 1250 Mhz (10 GT/s)
6 Reserved
7 Reserved
[5:0] C-1
[11:6] C0
[17:12] C+1
Value Description
0 -6dB de-emphasis
1 -3.5dB de-emphasis
2 No de-emphasis
3 Reserved
USB Mode:
[1:0] C-1
[3:2] C0
[5:4] C1
00 - No change
01 – Increment
10 – Decrement
11 - Reserved
USB Mode[3:0]:
Provides the sync header for the MAC to use
with the next 128b block. The MAC reads this
value when the RxStartBlock signal is
asserted.
This signal is only used at the 10.0 GT/s
signaling rate.
1
For definition of datastream see the PCI Express 3.0 base specification.
EncodeDecodeBy Input N/A PCI Express Mode, USB Mode, and SATA
pass Mode:
SATA Mode:
Active
Name Direction Description
Level
RxValid Output High Indicates symbol lock and valid data on
RxData and RxDataK.
When BlockAlignControl=0:
1. - RxValid is constantly high indicating that
the block aligner is conceptually in the
“Locked” state (see PCI Express or USB
3.1Base Spec). RxValid can be dropped on
detecting an incorrect sync header or
detecting underflow/overflow. If de-
asserted it must not re-assert while
BlockAlignControl is de-asserted.
For example:
1.5 GT/s with 8-bit data path PCLK=150MHz,
the nominal spacing is 4 PCLK’s.
Sata Mode:
The time the signal is asserted must match the
actual idle time on the analog bus within -
16/+0 ns.
RxStatus[2:0] Output N/A Encodes receiver status and error codes for
the received data stream when receiving data.
[2] [1] [0] Description
0 0 0 Received data OK
0 0 1 PCI Express Mode: 1 SKP added
USB SuperSpeed Mode: 1 SKP
Ordered Set added
Sata Mode: 1 ALIGN added
Asserted with first byte of Align
that was added. An align may only
be added in conjunction with
receiving one or more aligns in the
data stream and only when the
elasticity buffer is operating in half
full mode
0 1 0 PCI Express Mode: 1 SKP
removed
USB SuperSpeed Mode: 1 SKP
Ordered Set removed
SATA Mode: 1 or more ALIGNs
removed
This status is asserted with first
non ALIGN byte following an
ALIGN. This status message is
applicable to both EB buffer
modes.
0 1 1 PCI Express and USB SuperSpeed
Modes:
Receiver detected
SATA Mode: Misalign
Signaled on the first symbol of an
ALIGN that was received
misaligned in elasticity buffer
nominal half full mode. Signaled
on the first data following an align
in elasticity buffer nominal empty
mode.
1 0 0 Both 8B/10B (128B/130B2) decode
error and (optionally) Receive
Disparity error Note: This error is
never reported if
EncodeDecodeBypass is asserted.
1 0 1 Elastic Buffer overflow
1 1 0 Elastic Buffer underflow.
This error code is not used if the
elasticity buffer is operating in the
nominal buffer empty mode.
1 1 1 Receive disparity error (Reserved
if Receive Disparity error is
reported with code 0b100)
2
Disparity errors are not reported when the rate is 8.0 GT/s. Not used if EncodeDecodeBypass
is asserted.
©2007 - 2013, 2008, 2009 Intel Corporation—All rights reserved. Page 48 of 90
PHY Interface for the PCI Express, SATA, and USB 3.10 Architectures
BlockAlignControl
Error ts
RxValid
Detec
MAC
RxStartBlock
Sync Header
Error
Note:
BlockAlignControl assertion and RxValid deassertion. The PHY will attempt to re-do block alignment.
The BlockAlignControl assertion does not require the PHY to force the block aligner into the unaligned state.
There is no requried relationship between the de-assertion of RxValid and RxStartBlock.
Errors in SKP ordered sets shall be reported as 128/130 decode errors. An error in a SKP ordered
set shall be reported if there is an error in the first 4N+1 symbols of the skip ordered set.
Max PCLK Output Rising Parallel interface data clock. This fixed rate
Edge clock operates at the following rate:
SATA Mode:
Max rate supported Max PCLK
1.5 GT/s 150 MHz.
3.0 GT/s 300 MHz.
6.0 GT/s 600 MHz.
This clock is provided whenever PCLK is
active.
USB Mode:
Max rate supported Max PCLK
5.0 GT/s 500 MHz.
10.0 GT/s 1250 MHz.
This clock is provided whenever PCLK is
active.
DataBusWidth[1 Output N/A This field reports the width of the data bus that
:0] the PHY is configured for.
7.1 Clocking
There are three clock signals used by the PHY Interface component. The first (CLK) is a
reference clock that the PHY uses to generate internal bit rate clocks for transmitting and
receiving data. The specifications for this signal are implementation dependent and must be fully
specified by vendors. The specifications may vary for different operating modes of the PHY.
This clock may have spread spectrum modulation that matches a system reference clock (for
example, the spread spectrum modulation could come from REFCLK from the Card Electro-
Mechanical Specification).
The second clock (PCLK) is an output from the PHY in “PCLK as PHY Output” mode and an
input to each PHY lane in “PCLK as PHY Input ” mode and is the parallel interface clock used to
synchronize data transfers across the parallel interface. This clock runs at a rate dependent on the
Rate, PCLK Rate, and PHY Mode control inputs and data interface width. The rising edge of this
clock is the reference point. This clock may also have spread spectrum modulation.
The third clock (MAX PCLK) is a constant frequency clock with a frequency determined by the
maximum SATA signaling rate supported by the PHY and is only required in “PCLK as PHY
Input ” modeSATA Mode or in all modes for a PHY that supports PCI Express 3.0..
7.2 Reset
When the MAC wants to reset the PHY (e.g.; initial power on), the MAC must hold the PHY in
reset until power and CLK to the PHY are stable. The PHY signals that PCLK and/or Max PCLK
areis valid (i.e. PCLK and/or Max PCLK has been running at its operational frequency for at least
one clock) and the PHY is in the specified power state by the deassertion of PhyStatus after the
MAC has stopped holding the PHY in reset. While Reset# is asserted the MAC should have
TxDetectRx/Loopback deasserted, TxElecIdle asserted, TxCompliance deasserted, RxPolarity
deasserted, PowerDown = P1 (PCI Express mode) or PowerDown = P2 (USB SuperSpeed Mode)
or PowerDown set to the default value reported by the PHY (SATA Mode), TxMargin = 000b,
TxDeemp = 1, PHY Mode set to the desired PHY operating mode, and Rate set to 2.5GT/s
signaling rate for a PHY in PCI Express mode or 5.0 GT/s or 10 GT/s (highest supported) for a
PHY in USB SuperSpeed 3.0 mode or any rate supported by the PHY in SATA mode. The state
of TxSwing during Reset# assertion is implementation specific. RxTermination is asserted in USB
SuperSpeed 3.0 mode.
Reset#
PhyStatus
Reset
Four standard power states are defined, P0, P0s, P1, and P2. P0 state is the normal operational
state for the PHY. When directed from P0 to a lower power state, the PHY can immediately take
whatever power saving measures are appropriate. A PHY is allowed to implement up to 4
additional PHY specific power states. A MAC may use any of the PHY specific states as long as
the PCI Express base specification requirements are still met.
In states P0, P0s and P1, PCLK the PHY is required to be keptep PCLK operational. For all state
transitions between these three states and any PHY specific states where PCLK is operational, the
PHY indicates successful transition into the designated power state by a single cycle assertion of
PhyStatus. Transitions into and out of P2 or a PHY specific state where PCLK is not operational
are described below. For all power state transitions, the MAC must not begin any operational
sequences or further power state transitions until the PHY has indicated that the initial state
transition is completed.
Mapping of PHY power states to states in the Link Training and Status State Machine (LTSSM)
found in the base specification are included below. A MAC may alternately use PHY specific
states as long as the base specification requirements are still met.
P0 state: All internal clocks in the PHY are operational. P0 is the only state where the PHY
transmits and receives PCI Express signaling.
P0 is the appropriate PHY power management state for most states in the Link Training and
Status State Machine (LTSSM). Exceptions are listed below for each lower power PHY
state.
P0s state: PCLK output must stay operational. The MAC may move the PHY to this state
only when the transmit channel is idle.
P0s state can be used when the transmitter is in state Tx_L0s.Idle.
While the PHY is in either P0 or P0s power states, if the receiver is detecting an electrical
idle, the receiver portion of the PHY can take appropriate power saving measures. Note that
the PHY must be capable of obtaining bit and symbol lock within the PHY-specified time
(N_FTS with/without common clock) upon resumption of signaling on the receive channel.
This requirement only applies if the receiver had previously been bit and symbol locked
while in P0 or P0s states.
P1 state: Selected internal clocks in the PHY can be turned off. PCLK output must stay
operational. The MAC will move the PHY to this state only when both transmit and receive
channels are idle. The PHY must not indicate successful entry into P1 (by asserting
PhyStatus) until PCLK is stable and the operating DC common mode voltage is stable and
within specification (as per the base spec).
P1 can be used for the Disabled state, all Detect states, and L1.Idle state of the Link Training
and Status State Machine (LTSSM).
P2 state: Selected internal clocks in the PHY can be turned off. The parallel interface is in
an asynchronous mode and PCLK output is turned off. The MAC must ensure that the PHY
is in 2.5 GT/s signaling mode prior to moving the PHY to P2 state or direct the signaling
mode change and PHY power state change at the same time.
PCLK as PHY Output: When transitioning into P2, the PHY must assert PhyStatus before PCLK
is turned off and then deassert PhyStatus when PCLK is fully off and when the PHY is in the P2
state. When transitioning out of P2, the PHY asserts PhyStatus as soon as possible and leaves it
asserted until after PCLK is stable.
PCLK as PHY Input: When transitioning into P2, the PHY must assert PhyStatus for one input
PCLK cycle when it is ready for PCLK to be removed. When transitioning out of P2, the PHY
must assert PhyStatus for one input PCLK cycle as soon as possible once it has transitioned to P0
and is ready for operation.
PHYs should be implemented to minimize power consumption during P2 as this is when the
device will have to operate within Vaux power limits (as described in the PCI Express Base
Specification).
PCLK
PowerDown P0 P2
PhyStatus
P2 Entry
PCLK
PowerDown P2 P1
PhyStatus
P2 Exit
Figure 7-1 PCI Express P2 Entry and Exit with PCLK as PHY Output
PCLK
PhyStatus
Figure 7-2PCI Express P2 Entry and Exit with PCLK as PHY Input
There is a limited set of legal power state transitions that a MAC can ask the PHY to make.
Referencing the main state diagram of the LTSSM in the base spec and the mapping of LTSSM
states to PHY power states described in the preceding paragraphs, those legal transitions are: P0
to P0s, P0 to P1, P0 to P2, P0s to P0, P1 to P0, and P2 to P0. The base spec also describes what
causes those state transitions.
Transitions to and from any pair of PHY power states including at least one PHY specific power
state are also allowed by PIPE (unless otherwise prohibited). However, a MAC must ensure that
PCI Express specification timing requirements are met.
Four power states are defined, P0, P1, P2, and P3. The P0 state is the normal operational state for
the PHY. When directed from P0 to a lower power state, the PHY can immediately take
whatever power saving measures are appropriate.
In states P0, P1 and P2, the PCLK must bePHY is required to keptep PCLK operational. For all
state transitions between these three states, the PHY indicates successful transition into the
designated power state by a single cycle assertion of PhyStatus. Transitions into and out of P3
are described below. For all power state transitions, the MAC must not begin any operational
sequences or further power state transitions until the PHY has indicated that the initial state
transition is completed.
Mapping of PHY power states to states in the Link Training and Status State Machine found in
the USB specification are included below.
P0 state: All internal clocks in the PHY are operational. P0 is the only state where the PHY
transmits and receives USB SuperSpeed signaling.
P0 is the appropriate PHY power management state for all cases where the link is in U0 and
all other link state except those listed below for P1, P2, and P3.
P1 state: PCLK output must stay operational. The MAC will move the PHY to this state
only when the PHY is transmitting idles and receiving idles. The P1 state can be used for the
U1 link state.
P2 state: Selected internal clocks in the PHY can be turned off. PCLK output must stay
operational. The MAC will move the PHY to this state only when both transmit and receive
channels are idle. The PHY must not indicate successful entry into P2 (by asserting
PhyStatus) until PCLK is stable and the operating DC common mode voltage is stable and
within specification (as per the base spec).
PCLK as PHY Output: When transitioning into P3, the PHY must assert PhyStatus before
PCLK is turned off and then deassert PhyStatus when PCLK is fully off and when the PHY is
in the P3 state. When transitioning out of P3, the PHY asserts PhyStatus as soon as possible
and leaves it asserted until after PCLK is stable.
PCLK as PHY Input: When transitioning into P3, the PHY must assert PhyStatus for one
input PCLK cycle when it is ready for PCLK to be removed. When transitioning out of P3,
the PHY must assert PhyStatus for one input PCLK cycle as soon as possible once it has
transitioned to P0 and is ready for operation.
PHYs should be implemented to minimize power consumption during P3 as this is when the
device will have to operate within power limits described in the USB 3.0 Specification.
A minimum of five power states are defined, POWER_STATE_0 and a minimum of four additional
states that meet minimum requirements defined in section 6.1. POWER_STATE_0 state is the
normal operational state for the PHY. When directed from POWER_STATE_0 to a lower power
state, the PHY can immediately take whatever power saving measures are appropriate.
For all state transitions between POWER_STATE_0 and lower power states that provide PCLK,
the PHY indicates successful transition into the designated power state by a single cycle assertion
of PhyStatus. The PHY must complete transmitting all data transferred across the PIPE interface
before the change in the PowerDown signals before assertion of PhyStatus. Transitions into and
out of power states that do not provide PCLK are described below. For all power state
transitions, the MAC must not begin any operational sequences or further power state transitions
until the PHY has indicated that the initial state transition is completed. Power state transitions
between two power states that do not provide PCLK are not allowed.
Mapping of PHY power states to link states in the SATA specification is MAC specific.
POWER_STATE_0 : All internal clocks in the PHY are operational. POWER_STATE_0 is the
only state where the PHY transmits and receives SATA signaling.
POWER_STATE_0 is the appropriate PHY power management state for most link states in the
SATA specificationWhen transitioning into a power state that does not provide PCLK , the
PHY must assert PhyStatus before PCLK is turned off and then deassert PhyStatus when
PCLK is fully off and when the PHY is in the low power state. The PHY must leave PCLK
on for at least one cycle after asserting PhyStatus. When transitioning out of a state that does
not provide PCLK , the PHY asserts PhyStatus as soon as possible and leaves it asserted until
after PCLK is stable.
Transitions between any pair of PHY power states (except two states that do not provide PCLK)
are allowed by PIPE. However, a MAC must ensure that SATA specification timing
requirements are met.
There are instances where LTSSM state machine transitions indicate both a speed change and/or
width and/or PCLK rate change and a power state change for the PHY. One of these instances is
when the LTSSM transitions to Detect. In this case, the MAC must change (if necessary) the
signaling rate to 2.5 GT/s and change the width and/or PCLK rate if necessary before changing
the power state to P1. Another instance is when the LTSSM transitions to L2.Idle. Again, the
MAC must change (if necessary) the signaling rate to 2.5 GT/s and change the width and/or
PCLK rate if necessary before changing the power state to P2.
Some PHY architectures may allow a speed change and a power state change to occur at the same
time as a rate and/or width and/or PCLK rate change. If a PHY supports this, the MAC must
change the rate and/or width and/or PCLK rate at the same PCLK edge that it changes the
PowerDown signals. This can happen when transitioning the PHY from P0 to either P1 or P2
states. The completion mechanisms are the same as previously defined for the power state
changes and indicate not only that the power state change is complete, but also that the rate and/or
width and/or PCLK rate change is complete.
The signaling rate of the link, PCLK rate, or the Data Bus Width can be changed only when the
PHY is in the P0 or P2 power state and TxElecIdle and RxStandby are asserted. Any
combination of at least two of the rate and width and PCLK rate, can be changed simultaneously.
The MAC is not allowed to change only one of the three. When the MAC changes the Rate
signal, and/or the Width signal, and/or the PCLK rate signal in PCLK as PHY Output mode, the
PHY performs the rate change and/or the width change and/or the PCLK rate change and signals
its completion with a single cycle assertion of PhyStatus. The MAC must not perform any
operational sequences, power state transitions, deassert TxElecIdle or RxStandby, or further
signaling rate changes until the PHY has indicated that the signaling rate change has completed.
The sequence is the same in PCLK as PHY Input mode except the MAC needs to know when the
input PCLK rate can be safely changed. After the MAC changes PCLK_Rate the change to the
PCLK can happen only after the PclkChangeOk output has been driven high by the PHY. The
MAC changes the input PCLK, and then handshakes by asserting PclkChangeAck. The PHY
responds by asserting PhyStatus for one input PCLK cycle and de-asserts PclkChangeOk on the
trailing edge of PhyStatus. Note: PclkChangeOk is only used by the PHY if the MAC changes
PCLK_Rate. The MAC de-asserts PclkChangeAck when PclkChangeOk is sampled low and
may de-assert TxElecIdle and/or RxStandby after PhyStatus is sampled high.
Some PHY architectures may allow a speed change and a power state change to occur at the same
time as a rate and/or width and/or PCLK rate change. If a PHY supports this, the MAC must
change the rate and/or width and/or PCLK rate at the same PCLK edge that it changes the
PowerDown signals. This can happen when transitioning the PHY from P0 to either P2 or P3
states. The completion mechanisms are the same as previously defined for the power state
changes and indicate not only that the power state change is complete, but also that the rate and/or
width and/or PCLK rate change is complete.
Some PHY architectures may allow a speed change and a power state change to occur at the same
time as a rate and/or width and/or PCLK rate change. If a PHY supports this, the MAC must
change the rate and/or width and/or PCLK rate at the same PCLK edge that it changes the
PowerDown signals. The completion mechanisms are the same as previously defined for the
power state changes and indicate not only that the power state change is complete, but also that
the rate and/or width and/or PCLK rate change is complete.
PCLK
TxElecIdle
PhyStatus
Rate
Figure 7-3 shows logical timings for an implementation that changes PCLK frequency when the
MAC changes the signaling rate and PCLK is a PHY Input.
TxElecIdle
RxStandbyStatus
PCLK
PclkChangeOk
PclkChangeAck
PhyStatus
Figure 7-37-2 Change from PCI Express 2.5 Gt/s to 5.0 Gt/s with PCLK as
PHY Input.
PCLK
TxElecIdle
PhyStatus
Rate
TxData[7:0] Useable
TxData[15:8] Useable
RxData[7:0] Useable
RxData[15:8] Useable
There is a limited set of legal TxMargin[2:0] and Rate combinations that a MAC can select.
Refer to the PCIe Base Specification for a complete description of legal settings when the PHY is
in PCI Express Mode. Refer to the USB specification for a complete description of the legal
settings when the PHY is in USB SuperSpeed mode.
PCLK
PowerDown[1:0] P0 P0
< 128ns
New value at
Tx pins within 128ns
There is a limited set of legal TxDeemph and Rate combinations that a MAC can select. Refer to
the PCIe Base Specification for a complete description.
The MAC must ensure that TxDeemph is selecting -3.5db whenever Rate is selecting 2.5 GT/s.
PCLK
PowerDown[1:0] P0 P0
< 128ns
New value at
Tx pins within 128ns
7.9 Receiver Detection – PCI Express Mode and USB SuperSpeed Mode
While in the P1 power state and PCI Express mode or in the P2 or P3 power state and USB
SuperSpeed mode, the PHY can be instructed to perform a receiver detection operation to
determine if there is a receiver at the other end of the link. Basic operation of receiver detection
is that the MAC requests the PHY to do a receiver detect sequence by asserting
TxDetectRx/Loopback. When the PHY has completed the receiver detect sequence, it asserts
PhyStatus for one clock and drives the RxStatus signals to the appropriate code. After the
receiver detection has completed (as signaled by the assertion of PhyStatus), the MAC must
deassert TxDetectRx/Loopback before initiating another receiver detection, a power state
transition, or signaling a rate change.
Once the MAC has requested a receiver detect sequence (by asserting TxDetectRx/Loopback), the
MAC must leave TxDetectRx/Loopback asserted until after the PHY has signaled completion by
the assertion of PhyStatus. When receiver detection is performed in USB SuperSpeed mode with
the PHY in P3 the PHY asserts PhyStatus and signals the appropriate receiver detect value until
the MAC deasserts TxDetectRx/Loopback.
PCLK
TxDetectRx/Loopback
PhyStatus
PowerDown[1:0] 10b
PowerDown[1:0] P2
TxElecIdle
Beacon Transmit
PowerDown[1:0] P2
TxElecIdle
LFPS Transmit
PowerDown[1:0] P2
RxElecIdle
Beacon Receive
PowerDown[1:0] P2
RxElecIdle
LFPS Receive
For the Nominal Empty buffer model the PHY attempts to keep the elasticity buffer as close to
empty as possible. In Nominal Empty mode the PHY uses the RxDataValid interface to tell the
MAC when no data is available. The Nominal Empty buffer model provides a smaller worst case
and average latency then the Nominal Half Full buffer model, but requires the MAC to support
the RxDataValid signal.
Two models are defined for the elastic buffer operation in the PHY. The PHY may support one
or both of these models. The Nominal Empty buffer model is only supported in USB SuperSpeed
or SATA Mode.
For the Nominal Half Full buffer model, the PHY is responsible for inserting or removing SKP
symbols, ordered sets, or ALIGNs in the received data stream to avoid elastic buffer overflow or
underflow. The PHY monitors the receive data stream, and when a Skip ordered-set or ALIGN is
received, the PHY can add or remove one SKP symbol (PCI Express Mode at 2.5 or 5 GT/s) or
four SKP symbols (PCI Express Mode at 8 GT/s) or one SKP ordered set (USB SuperSpeed
Mode at 5 GT/s) or one ALIGN from each SKP or ALIGN as appropriate to manage its elastic
buffer to keep the buffer as close to half full as possible. In USB SuperSpeed mode at 5 GT/S the
PHY shall only add or remove SKP ordered sets. In USB mode at 10 GT/s the PHY shall only
add or remove multiples of two SKP symbols. Whenever a SKP symbol(s) or an ordered set is
added to or removed, the PHY will signal this to the MAC using the RxStatus[2:0] signals.
These signals have a non-zero value for one clock cycle and indicate whether a SKP symbol or
ordered set was added to or removed from the received SKP ordered-set(s). In PCI Express
Mode, RxStatus shall be asserted during the clock cycle when the COM symbol of the SKP
ordered-set is moved across the parallel interface. In SATA Mode whenever a ALIGN symbol is
added or removed, the PHY will signal this to the MAC using the RxStatus[2:0] signals. These
signals have a non-zero value for one clock cycle and indicate whether an ALIGN was added or
removed. RxStatus shall be asserted during the clock cycle when the first symbol of the ALIGN
is moved across the parallel interface.
In USB SuperSpeed mode for the Nominal Empty buffer model the PHY attempts to keep the
elasticity buffer as close to empty as possible. This means that the PHY will be required to insert
SKP ordered sets into the received data stream when no SKP ordered sets have been received.
The Nominal Empty buffer model provides a smaller worst case and average latency then the
Nominal Half Full buffer model, but requires the MAC to support receiving SKP ordered sets any
point in the data stream.
In SATA mode for the Nominal Empty buffer model the PHY attempts to keep the elasticity
buffer as close to empty as possible. In Nominal Empty mode the PHY uses the RxDataValid
interface to tell the MAC when no data is available. The Nominal Empty buffer model provides a
smaller worst case and average latency then the Nominal Half Full buffer model, but requires the
MAC to support the RxDataValid signal.
Starting with this version of the specification a PHY and MAC are allowed to support the
Nominal Empty buffer model in USB mode using the RxDataValid signal. Inserting SKPs in the
data stream when no SKPs have been received is not recommended. The figure below shows a
sequence where a PHY operating in PCI Express Mode added a SKP symbol in the data stream.
PCLK
RxVali d
PCLK
RxData[7:0] Active
RxVali d
If an error occurs during a SKP ordered-set or ALIGN, such that the error signaling and SKP or
ALIGN added/removed signaling on RxStatus would occur on the same CLK, then the error
signaling has precedence.
Note that the PHY does not signal 128/130B (PCI Express) or 128/132B (USB) header errors.
The raw received header bits are passed across the interface and the controller is responsible for
any block header error detection/handling.
PCLK
RxVali d
PCLK
RxVali d
Disparity Error
7.15.3 Elastic Buffer Errors
For elastic buffer errors, an underflow should be signaled during the clock cycle or clock cycles
when a spurious symbol is moved across the parallel interface. The symbol moved across the
interface should be the EDB symbol (for PCIe or SATA) or SUB symbol (for USB). In the timing
diagram below, the PHY is receiving a repeating set of symbols Rx-a thru Rx-z. The elastic
buffer underflows causing the EDB symbol (for PCIe) or SUB symbol (for USB) to be inserted
between the Rx-g and Rx-h Symbols. The PHY drives RxStatus to indicate buffer underflow
during the clock cycle when the EDB (for PCIe) or SUB (for USB) is presented on the parallel
interface.
Note that underflow is not signaled when the PHY is operating in Nominal Empty buffer mode.
In this mode SKP ordered sets are moved across the interface whenever data needs to be inserted
or the RxDataValid signal is used. The RxDataValid method is preferred.
PCLK
RxVali d
PCLK
RxVali d
7.16 Loopback
For USB SuperSpeed and PCI Express Modes the PHY must support an internal
loopback as described in the corresponding base specification.
For SATA the PHY may optionally support an internal loopback mode when
EncodeDecodeBypass is asserted.
The PHY begins to loopback data when the MAC asserts TxDetectRx/Loopback while doing
normal data transmission (i.e. when TxElecIdle is deasserted). The PHY must, within the
specified receive and transmit latencies, stop transmitting data from the parallel interface, and
begin to loopback received symbols. While doing loopback, the PHY continues to present
received data on the parallel interface.
The PHY stops looping back received data when the MAC deasserts TxDetectRx/Loopback.
Transmission of data on the parallel interface must begin within the specified transmit latency.
The timing diagram below shows example timing for beginning loopback. In this example, the
receiver is receiving a repeating stream of bytes, Rx-a thru Rx-z. Similarly, the MAC is causing
the PHY to transmit a repeating stream of bytes Tx-a thru Tx-z. When the MAC asserts
TxDetectRx/Loopback to the PHY, the PHY begins to loopback the received data to the
differential Tx+/Tx- lines. Timing between assertion of TxDetectRx/Loopback and when Rx data
is transmitted on the Tx pins is implementation dependent.
PCLK
TxDetectRx/Loopback
TxElecIdle
Tx+/Tx- T x-g/T x-h T x-I/Tx-j T x-k/T x-l Tx-m/T x-n T x-o/T x-p Rx-g/Rx-h Rx-I/Rx-j
Loopback start
The next timing diagram shows an example of switching from loopback mode to normal mode
when the PHY is operating in PCI Express Mode.
In PCI Express Mode, when the MAC detects an electrical idle ordered-set, the MAC deasserts
TxDetectRx/Loopback and asserts TxElecIdle. The PHY must transmit at least three bytes of the
electrical idle ordered-set before going to electrical idle. (Note, transmission of the electrical idle
ordered-set should be part of the normal pipeline through the PHY and should not require the
PHY to detect the electrical idle ordered-set). The base spec requires that a Loopback Slave be
able to detect and react to an electrical idle ordered set within 1ms. The PHY’s contribution to
this time consists of the PHY’s Receive Latency plus the PHY’s Transmit Latency (see section
6.13).
When the PHY is operating in USB SuperSpeed Mode, the device shall only transition out of
loopback on detection of LFPS signaling (reset) or when VBUS is removed. When valid LFPS
signaling is detected, the MAC transitions the PHY to the P2 power state in order to begin the
LFPS handshake.
PCLK
RxVali d
TxDetectRx/Loopback
TxElecIdle
Loopback end
7.17 Polarity Inversion – PCI Express and USB SuperSpeed Modes
To support lane polarity inversion, the PHY must invert received data when RxPolarity is
asserted. Inversion can happen in many places in the receive chain, including somewhere in the
serial path, as symbols are placed into the elastic buffer, or as symbols are removed from the
elastic buffer. Inverted data must begin showing up on RxData[] within 20 PCLKs of when
RxPolarity is asserted.
PCLK
RxValid
RxCodeErr
RxDispErr
RxPolarity
Polarity inversion
7.18 Setting negative disparity (PCI Express Mode)
To set the running disparity to negative, the MAC asserts TxCompliance for one clock cycle that
matches with the data that is to be transmitted with negative disparity. For a 16-bit interface, the
low order byte will be the byte transmitted where running disparity is negative. The example
shows how TxCompliance is used to transmit the PCI Express compliance pattern in PCI Express
mode. TxCompliance is only used in PCI Express mode.
PCLK
TxCompliance
Byte transmitted
with negative disparity
Loopback
Setting negativeend
disparity
TxDataK[0]
TxDataK[1]
TxElecIdle
Electrical Idle
PowerDown[2:0] P0
TxElecIdle
TxDataValid
TxStartBlock
Sync Sync
TxSyncHeader[1:0] Hdr Hdr
Note:
TxDataValid can assert earlier before TxElecIdle toggles or at the latest the same clock when TxElecIdle toggles.
TxDataValid can de-assert anytime after TxElecIdle asserts as long as it does not overlap with the next Electrical Idle exit sequence.
TxElecIdle must de-assert at the same clock TxStartBlock asserts.
Figure 7-4 – PCI Express 3.0 TxDataValid Timings for Electrical Idle Exit
and Entry.
Note: Figure 7-4 only shows two blocks of TxData and thus TxDataValid does not de—assert
during the data. Other examples in the specification show longer sequences where TxDataValid
de-asserts.
PCLK
PowerDown P0
LinkEvaluation
Feedback
InvalidRequest
TS Requested
Coeff Req #1 Coeff Req #2
Coeff
Note:
RxEqEval can de-assert at the same clock the corresponding PhyStatus de-asserts or later as long as RxEqEval de-asserts prior to the next RX Equalization Request.
Back-to-back RxEqEval request can happen as close as one clock apart (i.e. RxEqEval can de-assert for one clock before it re-asserts again to start the next RX Equalization request.
PCLK
PowerDown P0
RxEqEval
PhyStatus
LinkEvaluation
Feedback
InvalidRequest
TS Requested
Valid Coeff to Link Partner Hold Prior Coeff to Link Partner
Coeff
Note:
InvalidRequest assertion happens after the de-assertion of RxEqEval.
InvalidRequest must de-assert at the same clock RxEqEval for the next RX Equalization request asserts.
InvalidRequest could be asserted for as little as one PCLK pulse.
Note: If a race condition occurs where the MAC aborts by deasserting RxEqEval on same cycle
as the PHY asserts PhyStatus then the PHY shall not take any further action.
Transmit Latency Time for data moving between the parallel interface and the
PCI Express, SATA or USB SuperSpeed serial lines.
Timing is measured from when the data is transferred across
the parallel interface (i.e. the rising edge of PCLK) and
when the first bit of the equivalent 10-bit symbol is
transmitted on the Tx+/Tx- serial lines. The PHY reports
the latency for each operational mode the PHY supports.
latency separately.
Power State After Reset The PHY power state immediately following reset. The
state after reset needs to provide PCLK and have common
mode off.
SuperSpeed Mode. having been in the P1 state. Time is measured from when
the MAC sets the PowerDown signals to P0 until the PHY
asserts PhyStatus. PHY asserts PhyStatus when it is ready
to begin data transmission and reception.
P2 to P0 transition time. USB Amount of time for the PHY to return to P0 state, after
SuperSpeed Mode. having been in the P2 state. Time is measured from when
the MAC sets the PowerDown signals to P0 until the PHY
asserts PhyStatus. PHY asserts PhyStatus when it is ready
to begin data transmission and reception.
P3 to P0 transition time USB Amount of time for the PHY to go to P0 state, after having
SuperSpeed Mode. been in the P3 state. Time is measured from when the
MAC sets the PowerDown signals to P0 until the PHY
deasserts PhyStatus. PHY asserts PhyStatus when it is
ready to begin data transmission and reception.
Power state transition times Amount of time for the PHY to transition to a new power
between two power states that state. Time is measured from when the MAC sets the
provide PCLK. PowerDown signals to POWER_STATE_X until the PHY
asserts PhyStatus. PHY asserts PhyStatus when it is ready
to begin data transmission and reception. The PHY reports
this transition between each pair of power states it supports
in each PHY mode it supports.
Power state transition times Amount of time for the PHY to go to a power state
between a power state without providing PCLK, after having been in a power state that
PCLK and a power state with does not provide PCLK. Time is measured from when the
PCLK. MAC sets the PowerDown signals to the new power state
until the PHY deasserts PhyStatus. The PHY reports this
time for each possible transition between a power state that
does not provide PCLK and a power state that does provide
PCLK. The PHY reports this transition time between each
pair of power states it supports in each PHY mode it
supports.
Reset to ready time Timed from when Reset# is deasserted until the PHY
deasserts PhyStatus.
Supported power states. The PHY lists each power state it supports for each PHY
mode it supports. For each power state supported it reports
whether PCLK is provided, the exit latency, and the
common mode state.
Note: This is done for all states not already listed
separately.
Simultaneous Rate and Power The PHY reports if it supports simultaneous rate and power
State Change state changes for each PHY mode it supports.
Data Rate change time. PCI Amount of time the PHY takes to perform a data rate
Express Mode and SATA Mode. change. Time is measured from when the MAC changes
Rate to when the PHY signals rate change complete with
the single clock assertion of PhyStatus. There may be
separate values for each possible change between different
supported rates for each supported PHY mode.
Transmit Margin values supported. Transmitter voltage levels.
PCI Express Mode and USB [2] [1] [0] Description
SuperSpeed Mode. 0 0 0 TxMargin value 0 =
0 0 1 TxMargin value 1 =
0 1 0 TxMargin value 2 =
0 1 1 TxMargin value 3 =
1 0 0 TxMargin value 4 =
1 0 1 TxMargin value 5 =
1 1 0 TxMargin value 6 =
1 1 1 TxMargin value 7 =
Max Equalization Settings for C-1 Reports the maximum number of settings supported by the
PHY for the 8.0 GT/s equalization. The maximum number
of settings must be less than 64.
Max Equalization Settings for C0 Reports the maximum number of settings supported by the
PHY for the 8.0 GT/s equalization. The maximum number
of settings must be less than 64.
Max Equalization Settings for C1 Reports the maximum number of settings supported by the
PHY for the 8.0 GT/s equalization. The maximum number
of settings must be less than 64.
Default Equalization settings for Reports the recommended setting values for C-1, C0, C1 for
full swing preset Pn. each full swing preset.
Default Equalization settings for Reports the recommended setting values for C-1, C0, C1 for
half swing preset Pn. each half swing preset.
Default Equalization settings for Reports the recommended setting values for C-1, C0, C1 for
recommended TX EQ value of 0 the USB 3.1 0 dB preshoot and -2.5 dB de-emphasis
dB preshoot and -2.5 dB de- recommended TX EQ setting.
mephasis.
Default Equalization settings for Reports the recommended setting values for C-1, C0, C1 for
recommended TX EQ value of 2.7 the USB 3.1 0 dB preshoot and -2.5 dB de-emphasis
dB preshoot and -3.3 dB de- recommended TX EQ setting.
mephasis.
Dynamic Preset Coefficient A PHY indicates if it dynamically updates coefficients.
Update Support
Figure of Merit range If the PHY reports link equalization feedback in the Figure
of Merit format it reports the maximum value it will report.
The maximum value must be less than 256.
Figure of Merit for BER target If the PHY reports link equalization feedback in the Figure
of Merit format it reports the minimum value that the PHY
estimates corresponds to a link BER of E-12.
Default Link Partner Preset[3:0] If the PHY prefers the link parter to start with a specific
preset during link evaluation it reports the preferred starting
preset.
PowerDown[2:0] P0
TxElecIdle
TxDataValid ‘1’
4 Blocks 4 Blocks
TxStartBlock
TxSyncHeader[1:0]
Figure 7-7 – PCI Express 3.0 TxDataValid Timing for 8 Bit Wide TxData
Interface
PowerDown[2:0] P0
TxElecIdle
TxDataValid ‘1’
8 Blocks 8 Blocks
TxStartBlock
Figure 7-8 – PCI Express 3.0 TxDataValid Timing for 16 Bit Wide TxData
Interface
PowerDown P1 P0
RxElecIdle
Bl De
oc la
k y
Lo
ck
BlockAlignControl
RxValid
Relation
No
RxDataValid
RxStartBlock
RxSyncHeader
RxData
Notes:
RxValid assertion indicates that PHY has achieved block alignment.
RxValid assertion aligns with the first RxStartBlock.
RxDataValid can assert before RxValid toggles or at the latest the same clock when RxValid toggles.
There is no required relationship between BlockAlignControl de-assertion and RxStartBlock.
Figure 7-9 – PCI Express 3.0 RxDataValid Timing for 16 Bit Wide RxData
Interface
There are situations, such as upconfigure, when a MAC must start transmissions on idle lanes
while some other lanes are already active. In any such situation the MAC must wait until the
cycle after TxDataValid is de-asserted to allow the PHY to transmit the backlog of data due to
128b/130b to start transmissions on previously idle lanes.
When the MAC and higher levels have determined that the link should transition to L0s, the
MAC transmits an electrical idle ordered set and then has the PHY transmitter go idle and enter
P0s. Note that for a 16-bit or 32-bit interface, the MAC should always align the electrical idle on
the parallel interface so that the COM symbol is in the low-order position (TxDataK[7:0]).
PCLK
TxDataK[0]
TxDataK[1]
TxElecIdle
PhyStatus
L0 to L0s
To cause the link to exit the L0s state, the MAC transitions the PHY from the P0s state to the P0
state, waits for the PHY to indicate that it is read to transmit (by the assertion of PhyStatus), and
then begins transmitting Fast Training Sequences (FTS). Note, this is an example of L0s to L0
transition when the PHY is running at 2.5GT/s.
PCLK
PhyStatus
TxData[7:0] FTS
TxDataK[0]
TxData[15:8] FTS
TxDataK[1]
TxElecIdle
Tx+/Tx- Active
L0s to L0
After the MAC has had the PHY send PM_Active_State_Request_L1 messages, and has received
the PM_Request_ACK message from the upstream port, it then transmits an electrical idle
ordered set, and has the PHY transmitter go idle and enter P1.
PCLK
TxDataK[0]
TxDataK[1]
TxElecIdle
PhyStatus
L0 to L1
To cause the link to exit the 1 state, the MAC transitions the PHY from the P1 state to the P0
state, waits for the PHY to indicate that it is ready to transmit (by the assertion of PhyStatus), and
then begins transmitting training sequence ordered sets (TS1s). Note, this is an example when the
PHY is running at 2.5GT/s.
PCLK
PhyStatus
TxDataK[0]
TxDataK[1]
TxElecIdle
Tx+/Tx- Active
L1 to L0
8.3 Receivers and Electrical Idle – PCI Express Mode Example
This section only applies to a PHY operating to 2.5GT/s. Note that when operating at 5.0 GT/s or
8 GT/s signaling rates, RxElecIdle may not be reliable. MACs should refer to the PCI Express
Revision 3.0 Base Specification or USB 3.0 Specification for methods of detecting entry into the
electrical idle condition. Refer to Table 6-4 for the definition of RxElecIdle when operating at 5.0
GT/s. This section shows some examples of how PIPE interface signaling may happen as a
receiver transitions from active to electrical idle and back again. In these transitions there may be
a significant time difference between when RxElecIdle transitions and when RxValid transitions.
The first diagram shows how the interface responds when the receive channel has been active and
then goes to electrical idle. In this case, the delay between RxElecIdle being asserted and RxValid
being deasserted is directly related to the depth of the implementations elastic buffer and symbol
synchronization logic. Note that the transmitter that is going to electrical idle may transmit
garbage data and this data will show up on the RxData[] lines. The MAC should discard any
symbols received after the electrical idle ordered-set until RxValid is deasserted.
PCLK
RxValid
RxElecIdle
Rx+/Rx- Data
The second diagram shows how the interface responds when the receive channel has been idle
and then begins signaling again. In this case, there can be significant delay between the
deassertion of RxElecIdle (indicating that there is activity on the Rx+/Rx- lines) and RxValid
being asserted (indicating valid data on the RxData[] signals). This delay is composed of the
time required for the receiver to retrain as well as elastic buffer depth.
PCLK
RxValid
RxElecIdle
Rx+/Rx- Data
The general usage model is that to stop REFCLK the MAC puts the PHY into the P2 power state,
then deasserts CLKREQ#. To get the REFCLK going again, the MAC asserts CLKREQ#, and
then after some PHY and implementation specific time, the PHY is ready to use again.
CLKREQ# in L1
If the MAC is moving the link to the L1 state and intends to deassert CLKREQ# to stop
REFCLK, then the MAC follows the proper sequence to get the link to L1, but instead of
finishing by transitioning the PHY to P1, the MAC transition the PHY to P2. Then the MAC
deasserts CLKREQ#.
When the MAC wants to get the link alive again, it can:
Assert CLKREQ#
Wait for REFCLK to be stable (implementation specific)
Wait for the PHY to be ready (PHY specific)
Transition the PHY to P0 state and begin training.
CLKREQ# in L2
If the MAC is moving the link to the L1 state and intends to deassert CLKREQ# to stop
REFCLK, then the MAC follows the proper sequence to get the link to L2. Then the MAC
deasserts CLKREQ#.
When the MAC wants to get the link alive again, it can:
Assert CLKREQ#
Wait for REFCLK to be stable (implementation specific)
Wait for the PHY to be ready (PHY specific)
Transition the PHY to P0 state and begin training.
Delayed CLKREQ# in L1
The MAC may want to stop REFCLK after the link has been in L1 and idle for awhile. In this
case, the PHY is in the P1 state and the MAC must transition the PHY into the P0 state, and then
the P2 state before deasserting CLKREQ#. Getting the link operational again is the same as the
preceding cases.
The figure shows an example 4-lane implementation of a multilane PIPE solution with PCLK as a
PHY input. The signals that can be shared are shown in the figure as “Shared Signals” while
signals that must be replicated for each lane are shown as ‘Per-lane signals’.
CLK
Max PCLK
PLL
Shared Signals
Shared
Signals
To Data Link Layer
4-lane
implementation
TxDataValid TxDeemph[17:0]
PCLK PowerDown[1:0]
PhyStatus
RxPresetHint[2:0]
RxEqEval
LinkEvaluationFeedbackFigureMerit[7:0]
LinkEvaluationFeedbackDirectionChange[7:0]
InvalidRequest
TxSyncHeader[1:0]
RxSyncHeader[1:0]
RxStandby
RxStandbyStatus
FS[5:0]
LF[5:0]
A MAC must use all “Per-Lane Signals or Shared Signals” that are inputs to the PHY consistently
on all lanes in the link. A PHY in “PCLK as PHY Output ” mode must ensure that PCLK and
Max PCLK are synchronized across all lanes in the link. A MAC must provide a synchronized
PCLK as an input for each lane when controlling a PHY in “PCLK as PHY Input ” mode with no
more than 300 ps of skew on PCLK across all lanes.
It is recommended that a MAC be designed to support both PHYs that implement all signals per
lane and those that implement the “Per-Lane or Shared Signals” per link. A “Variable” PHY
must implement the signals in “Per-Lane Signals or Shared Signals” per lane. A “Fixed” PHY
may implement the signals in “Per-Lane Signals or Shared Signals” as either Shared or Per-Lane.
A “Fixed” PHY should implement all the signals in “Per-Lane Signals or Shared Signals”
consistently as either Shared or Per-Lane.
In cases where a multi-lane has been ‘trained’ to a state where not all lanes are in use (like a x4
implementation operating in x1 mode), a special signaling combination is defined to ‘turn off’ the
unused lanes allowing them to conserve as much power as the implementation allows. This
special ‘turn off’ signaling is done using the TxElecIdle and TxCompliance signals. When both
are asserted, that PHY can immediately be considered ‘turned off’ and can take whatever power
saving measures are appropriate. The PHY ignores any other signaling from the MAC (with the
exception of Reset# assertion) while it is ‘turned off’. Similarly, the MAC should ignore any
signaling from the PHY when the PHY is ‘turned off’. There is no ‘handshake’ back to the MAC
to indicate that the PHY has reached a ‘turned off’ state.
There are two normal cases when a lane can get turned off:
1. During LTSSM Detect state, the MAC discovers that there is no receiver present and will
‘turn off’ the lane.
2. During LTSSM Configuration state (specifically Configuration.Complete), the MAC will
‘turn off’ any lanes that didn’t become part of the configured link.
As an example, both of these cases could occur when a x4 device is plugged into a x8 slot. The
upstream device (the one with the x8 port) will not discover receiver terminations on four of its
lanes so it will turn them off. Training will occur on the remaining 4 lanes, and let’s suppose that
the x8 device cannot operate in x4 mode, so the link configuration process will end up settling on
x1 operation for the link. Then both the upstream and downstream devices will ‘turn off’ all but
the one lane configured in the link.
When the MAC wants to get ‘turned off’ lanes back into an operational state, there are two cases
that need to be considered:
1. If the MAC wants to reset the multi-lane PIPE, it asserts Reset# and drives other interface
signals to their proper states for reset (see section 6.2). Note that this stops signaling
‘turned off’ to all lanes because TxCompliance is deasserted during reset. The multi-lane
PHY asserts PhyStatus in response to Reset# being asserted, and will deassert PhyStatus
when PCLK is stable.
2. When normal operation on the active lanes causes those lanes to transition to the LTSSM
Detect state, then the MAC sets the PowerDown[1:0] signals to the P1 PHY power state
at the same time that it deasserts ‘turned off’ signaling to the inactive lanes. Then as with
normal transitions to the P1 state, the multi-lane PHY will assert PhyStatus for one clock
when all internal PHYs are in the P1 state and PCLK is stable.