Introduction to

VLSI Fabrication
Technologies

Emanuele Baravelli
 Organization

z Materials Used in VLSI Fabrication

z VLSI Fabrication Technologies

z Overview of Fabrication Methods

z CMOS Process Stages

 Main Categories of Materials
Materials can be classified into three main
groups regarding their electrical conduction
properties:

z Insulators
z Conductors
z Semiconductors
 Conductors
Conductors are used in IC design for electrical
connectivity. The following are good conducting
elements:

z Silver
z Gold
z Copper
z Aluminum
z Platinum
 Insulators

z Insulators are used to isolate conducting and/or

semi-conducting materials from each other.

z MOS devices and Capacitors rely on an

insulator for their physical operation.

z The choice of the insulators (and the

conductors) in IC design depends heavily on
how the materials interact with each other,
especially with the semiconductors.
 Semiconductors
z The basic semiconductor
material used in device
fabrication is Silicon
z The success of this material is
due to:
- Phisical characteristics
- Abundance in nature and very low
cost
- Relatively easy process
- Reliable high volume fabrication
z Other semiconductors (e.g. GaAs) are used for
special applications
 Organization

z Materials Used in VLSI Fabrication

z VLSI Fabrication Technologies

z Overview of Fabrication Methods

z CMOS Process Stages

 Overview of Processing
Technologies
Although a number of processing technologies are
available, the majority of the production is done with
traditional CMOS. Other processes are limited to
areas where CMOS is not very suitable (like high
speed RF applications)
Bipolar: GaAs: 2%
2%
BiCMOS: SOI: 1%
5%

CMOS: 90%
 CMOS technology
z An Integrated Circuit (IC) is an
electronic network fabricated in a
single piece of a semiconductor
material

z The semiconductor surface is

subjected to various processing
steps in which impurities and other
materials are added with specific
geometrical patterns

z The fabrication steps are sequenced

to form three dimensional regions
that act as transistors and
interconnects that form the network
Simplified View of MOSFET
 CMOS Process
The CMOS process allows fabrication of nMOS
and pMOS transistors side-by-side on the same
Silicon substrate.
 Organization

z Materials Used in VLSI Fabrication

z VLSI Fabrication Technologies

z Overview of Fabrication Methods

z CMOS Process Stages

Fabrication process sequence
z Silicon manifacture
z Wafer processing
- Lithography
- Oxide growth and
removal
- Diffusion and ion
implantation
- Annealing
- Silicon deposition
- Metallization
z Testing
z Assembly and packaging
 Single Crystal Growth (I)

z Pure silicon is melted

in a pot (1400º C) and
a small seed
containing the desired
crystal orientation is
inserted into molten
silicon and slowly
(1mm/minute) pulled
out
 Single Crystal Growth (II)

z The silicon crystal (in some

cases also containing doping) is
manufactured as a cylinder
(ingot) with a diameter of
8-12 inches (1”=2.54 cm).

z This cylinder is carefully sawed

into thin (0.50-0.75 mm thick)
disks called wafers, which are
later polished and marked for
crystal orientation.
 Lithography (I)
Lithography: process used to transfer patterns to
each layer of the IC
Lithography sequence steps:
z Designer:
- Drawing the “layer” patterns on a
layout editor
z Silicon Foundry:
- Masks generation from the layer
patterns in the design data base
- Printing: transfer the mask pattern
to the wafer surface
- Process the wafer to physically
pattern each layer of the IC
 Lithography (II)
1. Photoresist application: 1. Photoresist coating
Photoresist
- the surface to be patterned is
spin-coated with a light-sensitive SiO2
Substrate
organic polymer called photoresist
2. Exposure
Opaque
Printing (exposure):
Ultra violet light
2.
- the mask pattern is developed on the photoresist, Mask
with UV light exposure
- depending on the type of photoresist (negative or Unexposed Exposed

positive), the exposed or unexposed parts become

resistant to certain types of solvents
Substrate
3. Development:
-
3. Development
the soluble photoresist is chemically removed
- The developed photoresist acts as a mask for
patterning of underlying layers and then is removed.
Substrate
 Oxide Growth / Oxide Deposition
z Oxide can be grown from silicon through
heating in an oxidizing atmosphere
- Gate oxide, device isolation
- Oxidation consumes silicon
z SiO2 is deposited on materials other than silicon through
reaction between gaseous silicon compounds and oxidizers
- Insulation between different layers of metallization
Field oxide

XFOX
0.54 XFOX Silicon surface
0.46 XFOX

Silicon wafer
 Etching
z Once the desired shape is patterned with
photoresist, the etching process allows
unprotected materials to be removed
- Wet etching: uses chemicals
- Dry or plasma etching: uses ionized gases
Diffusion and Ion Implantation
Doping materials are added to
change the electrical characteristics
of silicon locally through:
z Diffusion: dopants deposited on silicon move
through the lattice by thermal diffusion (high
temperature process)
- Wells
z Ion implantation: highly energized donor or
acceptor atoms impinge on the surface and
travel below it
- The patterned SiO2 serves as an
implantation mask
- Source and Drain regions
 Annealing

Thermal annealing is a high temperature

process which:
z allows doping impurities to diffuse further into the
bulk

z repairs lattice damage caused by the collisions

with doping ions
 Silicon Deposition and
Metallization
z Films of silicon can be added on the
surface of a wafer
- Epitaxy: growth of a single-crystal
semiconductor film on a crystalline
substate
- Polysilicon: polycrystalline film with
a granular structure obtained through
deposition of silicon on an
amorphous material
- MOSFET gates

z Metallization: deposition of metal layers

by evaporation
- interconnections
 Organization

z Materials Used in VLSI Fabrication

z VLSI Fabrication Technologies

z Overview of Fabrication Methods

z CMOS Process Stages

 1. Epitaxial growth
z A p-silicon epitaxial layer is grown on the
surface of a p-type wafer
z The epi layer is used as the base layer to
build the devices

p-epitaxial layer Diameter = 75 to 230mm

< 1mm
P+ -type wafer
 2. N-well Formation
z The first mask defines the n-well regions for pMOS
transistors
z n-well’s are formed by ion implantation or
deposition and diffusion
z Lateral diffusion limits the proximity between
structures
Physical structure cross section Mask (top view)
n-well mask
Lateral
diffusion

n-well

p-type epitaxial layer

 3. Active area definition
z Active area:
- planar section of the surface where transistors are built
- defines the gate region (thin oxide)
- defines the n+ or p+ regions
z A thin layer of SiO2 is grown over the active region and
covered with silicon nitride

Stress-relief oxide Silicon Nitride Active mask

n-well

p-type
 4. Isolation
z Parasitic (unwanted) FET’s exist between unrelated transistors
(Field Oxide FET’s)
z Source and drains are existing source and drains of wanted
devices
z Gates are metal and polysilicon interconnects
z The threshold voltage of FOX FET’s must be higher than Vdd
in order to keep them off
Parasitic FOX device

n+ n+ n+ n+

p-substrate (bulk)
 4.1 Channel-stop implant
z Increases the threshold voltage by raising the
impurity concentration in the substrate in areas
where transistors are not required
z The silicon nitride (over n-active) and the photoresist
(over n-well) act as masks for the channel-stop
implant

Implant (Boron) channel stop mask = ~(n-well mask)

resit

n-well

p+ channel-stop implant
p-type
 4.2 Local oxidation of silicon
(LOCOS)
z The photoresist mask is removed

z The SiO2/Si3N4 layers will now act as masks

z Thick silicon dioxide is grown outside the active areas

z This further increases the threshold voltage of parasitic

transistors
patterned active area
Field oxide (FOX)

n-well
active area after LOCOS

p-type
 5. Gate oxide growth
z The nitride and stress-
relief oxide are removed
n-well
z The devices threshold
voltage is adjusted by p-type

adding charge at the tox

Gate oxide
tox
silicon/oxide interface
n-well

z The well controlled gate p-type

oxide is grown with
thickness tox
 6. Polysilicon deposition and
patterning
z A layer of polysilicon is deposited
over the entire wafer surface
z The polysilicon is then patterned
by a lithography sequence
z All the MOSFET gates are defined in a single step
z The polysilicon gate can be doped (n+) while is being
deposited to lower its parasitic resistance
Polysilicon mask
Polysilicon gate

n-well

p-type
 7. Source/Drain Implantation
z Photoresist is patterned to
cover all but the desired
active area

z The Source and Drain

regions of the pMOS or
nMOS device are doped by
ion implantation

z The polysilicon serves as a

mask to the underlying
channel
 9. Annealing
z After the implants are completed a thermal annealing
cycle is executed
z This allows the impurities to diffuse further into the
bulk
z The remaining process steps must be kept at as low
temperature as possible

n-well
n+ p+
p-type
 10. Oxide Deposition and
Contact Cuts
z The surface of the IC is covered by a layer of field
oxide
z Contact cuts are defined by etching SiO2 down to the
surface to be contacted
z These allow metal to contact diffusion and/or
polysilicon regions
Contact mask

n-well
n+ p+
p-type
 11. Metallization
z A first level of metallization is applied to the wafer
surface and selectively etched to produce the
interconnects
z Another layer of thick metal 2
Via metal 1
oxide is added
z Via openings
are created n-well
n+ p+
z Metal 2 is deposited p-type

and patterned
z Several other layers of Metal can be added
 12. Over glass and pad
openings
z A protective layer is added
over the surface. It
consists of:
- A layer of SiO2
- Followed by a layer of silicon
nitride
z The SiN layer acts as a
diffusion barrier against
contaminants
(passivation)
z Finally, contact cuts are
etched to allow for wire
bonding
 Advanced CMOS processes
z Shallow trench isolation
z source-drain halos (series
resistance)
z Self-aligned silicide (spacers)
z …
n+ poly p+ poly
Silicide Oxide spacer

n+ p-doping
n+ p+ n-doping
p+
n-well
Shallow-trench isolation
Source-drain
p-type substrate extension
 Links
z http://humanresources.web.cern.ch/Humanresou
rces/ external/training/tech/special/ELEC2002/
ELEC-2002_11Apr02_3.ppt

z http://lsmwww.epfl.ch/Education/

z http://lsiwww.epfl.ch/LSI2001/teaching/webcours
e/toc.html

z www.latticepress.com/prologvol1.html