Objective: ASIC Engineer

Glenn Kojiro Okamoto

born US citizen
available now

SKILLS:

• Synopsys ( Formality & Design Verifyer/verplex formal

verification using svf file output from Design Compiler, dc_shell Design
Compiler synthesis, Verilog Cycle Simulator (VCS), VHDL System Simulator
(VSS), DFTMAX Ultra (streaming and non-streaming, compressed and non-
compressed) scan insertion and Design Time static timing, pt_shell Prime Time
static timing, tmax Tetramax, DFT/BSD Compiler/DFTMAX Ultra Synthesis (to
include low power synthesis), Star Memory System (SMS)), Memory Built-In
Self Test (bist), Memory Built-In Self-Repair (bisr),DFTMAX Ultra streaming
and non-streaming ATPG scan test pattern generator,Synplicity for Xilinx FPGA)
• Cadence (Conformal Logical Equivalence Checker (LEC)
(Verplex), RTL Compiler synthesis, Encounter Timing System (ETS), Encounter
Test scan wgl generation, Verilog XL, NC-Verilog, Specman)
• Mentor Graphics (Modelsim, DFTAdvisor, TestKompress,
Fastscan, BSDArchitect, MBISTArchitect, Logicvision (LBIST and memory
bist))
• IBM (booledozer synthesis and static timing, booleseye formal
verification, einstimer static timing, testbench ATPG scan test pattern generator)
• Processor-microcode data & instruction ram tests, efuse tests
• Wrote and ran makefiles, perl, awk, bash, c-shell scripts (Small
electronics company, Volt, Kawasaki LSI); rexx, k-shell scripts (IBM); python,
c#, c++ programs (school graphical editor programs); c programs (called by
SystemVerilog programs, IBM simulation)
• Wrote, synthesized, & sim’d VHDL, Verilog, SystemVerilog,
Specman, Unified/Open Verilog Methodology/Components
(UVM/OVM/UVC/OVC), Reuse Methodology, random test data, self-checking
testbenches, large designs and test environments
• Matlab with Signal Processing Toolbox, Simulink
 • Atrenta Spyglass, Avago Cross-checks and TRC, all for rtl and
gate checks
• Xilinx ISE FPGA programming
• Altera MaxPlus2, Quartus2 FPGA & CPLD design, sim, timing,
synthesis, programming using 10Gbps high speed SERDES
• Filters, JPEG, MPEG, Image Processing (compression, etc.),
Video Processing (compression, etc.), Thresholding, Detection of edges (and
other objects)
• Used: Tektronix logic analyzers & oscilloscopes, Agilent pulse
pattern generators & arbitrary waveform/function generators, Signal generators,
Verigy LTX MX mixed signal chip mass production tester, spectrum analyzers,
Leader & Rohde & Schwarz digital tv signal generators (ATSC, DVB-T, DVB-H,
ISDB-T), multimeters, soldering, Windows-PC-based Labview software, usb-to-
gpib cable converters, Windows-PC-based JTAG control software, usb-to-jtag
cable converters, impedance matching
• Checked files in/out using Microsoft Visual Source Safe,
Synchronicity Design Sync, Microsoft Sharepoint, VCS, Subversion, CDR
(Avago)
• Microsoft Office (Project, Word, Excel spreadsheets, Visio for
diagrams, PowerPoint for diagrams)
• Lotus SmartSuite/Notes
• Used Windows 8/7/Vista/XP/… PC, red-hat linux PCs, IBM
RS/6000 AIX 4 workstation, Sun Solaris 9 unix workstations
• AutoCAD and OrCAD for electronics diagrams
• Bug tracking with Problem Management System (IBM), email
(Avago), Bugzilla 3.6.3 (installed, opened problem, searched for problems,
assigned problems, reported problems fixed)

WORK EXPERIENCE:

19 November 2018 – 30 April 2020 Hcl Asic Engineer at customer worksite, Intel, 75
reed rd, Hudson, MA 19227

Synopsys Design Compiler to successfully synthesize rtl into tech-independent

gate-level netlist
 Verdi to successfully generate & view simulation waveforms, schematics

ipgen & collage to successfully generate, integrate, connect memory repair

(mra), memory test (cabist) engines, satellites, collars; taps, clock control &
distribution units (ccdu’s), clock mux’s (mucc), process monitor ring oscillators
(idv’s), voltage droop monitors (vdm’s), voltage (on-die) droop inducer (odi’s),
clock edge adjuster (micro breakpoints) (ubp)physical design partitions
converged array memory bist (cabist) to generate cabist
rtldebug.bman to successfully generate & view simulation waveforms, schematic
Design-For-Debug, Design-For-Test overall strategy documentation

24 April – 25 October 2017 Aricent ASIC Engineer contractor at customer worksite,

Chandler, AZ

• Synopsys Design Compiler synthesis of verilog and vhdl rtl

• Synopsys Design Compiler Ultra streaming and non-streaming,
compressed and uncompressed scan insertion (successfully generated test patterns
then simulated them with unit-delay) with DC
• Synopsys Formality to verify functional logic unchanged by dft
insertion
• Synopsys Tetramax/DFTMAX Ultra streaming and non-streaming,
compressed and uncompressed scan test pattern STIL generation (successfully
generated test patterns then simulated them with unit-delay and min/typ/max SDF
delay, chain test passed 1st time on tester)
• Mentor Tessent/Testkompress edt generation, compressed scan
insertion, and test pattern generation
• Generated Mentor Mbist Architect memory test pattern STIL for
various
• Synopsys Verilog Cycle Simulation (VCS) with unit-delay and
min/typ/max SDF delay that passed sim for , chain test passed 1st time on tester
• Inserted DFT using DC scripts (which I wrote) and DC
topographical mode and read and wrote ddc files to do dft insertion completely in
physical design environment to avoid losing floorplanning info
 • Used inway flow for dft insertion (iwdc, edt_ip)

16 May – 21 August 2016 independent ASIC Engineer contractor, worked from Santa
Clara, CA, client=Synaptics

• Synopsys Tetramax/DFTMAX scan test pattern generation

(successfully generated test patterns)
• Synopsys Verilog Cycle Simulation (VCS)

1 February-18 March 2016 independent ASIC Engineer contractor, worked from Santa
Clara, CA, client=ST Microelectronics

• Synopsys Tetramax/DFTMAX scan test pattern generation

(successfully generated test patterns)
• Synopsys BSD Compiler (successfully generated boundary scan
chains connected to pre-existing TAP)
• Synopsys Verilog Cycle Simulation (VCS)

22 December 2015-12 April 2016 independent ASIC Engineer contractor, worked from
Santa Clara, CA, client=Esencia Tech
• Synopsys Tetramax/DFTMAX scan test pattern generation for 2
post-tapeout chips (passed zero delay sim, passed min/max SDF delay sim, passed
on tester)
• Synopsys Verilog Cycle Simulation (VCS) (passed zero delay sim,
passed min/max SDF delay sim)

23 December 2015-31 January 2016 independent ASIC Engineer contractor, worked

from Santa Clara, CA, client=Energous

• Synopsys Formality passed rtl=synthesized gate-level netlist in

functional mode; passed synthesized gate-level netlist=final gate-level netlist in
all modes (no scan reordering)
 • Synopsys Design Compiler/DFT Compiler/DFTMAX Synthesis
and Scan Insertion (passed post-place & route, min & max delay, sdf VCS scan
stil sim)
• Synopsys Tetramax/DFTMAX scan test pattern generation (passed
post-place & route, min & max delay, sdf VCS scan stil sim)
• Generated successful functional and scan mode sdc for use by
place & route
• Synopsys PrimeTime static timing for functional, test, internal, and
I/O paths
• Synopsys Verilog Cycle Simulation (VCS) using post-place &
route, min & max delay sdf & zero delay all passed

16 September 2012-27 November 2013 independent ASIC Engineer contractor at

customer worksites, Allentown, PA, and Milpitas & San Jose, CA,
client=LSI/Avago/Intel

• Used Synopsys Formality to Verify mbist synthesis & to verify

that test insertion left unchanged functional logic
• Ran Synopsys Virage Virage Memory (Star Memory System
(SMS)) memory built-in-self-test (mbist) with efuse-based ram repair for mbist
wrapper and controller insertion and testbench generation
• Ran scan compression insertion & testbench-generation using
Mentor Graphics TestKompress and DFTAdvisor.
• Ran Synopsys PrimeTime to including SDC generation, checking,
& sbpf-to-sdf conversion
• Ran gate-level verilog sim using Synopsys Verilog Cycle
Simulator (VCS) & Cadence NCsim in both command mode and gui mode (with
waveforms). Included Value Change Dump (VCD) file generation
• Wrote & ran perl, tcl, linux shell scripts

25 June 2012-13 September 2012 independent ASIC Engineer contractor, at customer

worksites, Santa Clara, CA, and Grenoble, France, client=ST Microelectronics
 • Synopsis Tetramax path delay, transition faults; scan patterns,
coverage
• Cadence NCSim and Synopsis Verilog Cycle Simulator (VCS)
with SDF Gate-Level Simulation for Loopback & Scan to include UVM &
SystemVerilog & simvision

25 April 2011-15 June 2012 Kelly ASIC Engineer contractor at customer worksite, Santa
Clara, CA

• Cadence NCSim with SDF

• Synopsys Prime Time
• Wrote & ran TCL, TK, perl, assembly language code for ram test,
efuse ram repair
• Made Verigy 93k test patterns
• Wrote & used Altera Quartus2 fpga programming Verilog using
Altera Stratix IV GT 100G board with fpga connected to demo board using
10Gbps high speed SERDES
• Lab selection & use of meters, fans, power supplies, fpga, boards
• Contract originally 6 months extended several times for total of 14
months
• Mentor Graphics Testkompress, fastscan, path delay, transition
faults; scan patterns, coverage

20 August 2007-14 January 2011 Maxlinear ASIC Engineer, Carlsbad, CA,

• Verified RTL=gate level functional logic using Cadence

Conformal Logical Equivalence Checker (LEC).
• Ran chip and module level Cadence RTL Compiler synthesis.
• For both usb/i2c/jtag controlled bench test & for production tester:
Functional speed ram and rom built-in-self-test (mbist) design, architecture,
insertion, (to include ram retention test, march test for bridging, transition, and
stuck faults) using Mentor Graphics MBIST Architect and ran Synopsys Virage
ram built-in-self-test (uses physical info) with ram repair. Generated high yield,
low test time, high coverage mbist WGL & EVO (Verify’s LTX-format) (both
with or without loops, pin checks, branches) for 4 different chips sold to
customers (3 in mass production, 1 sampling). Ran usb/i2c/jtag controlled mbist
bench tests.
• Ran scan compression insertion using Mentor Graphics
TestKompress and DFTAdvisor. Assisted in scan insertion using Cadence RTL
Compiler. Generated transition-fault, stuck fault, bridge fault, iddq (low current
test) scan pattern WGL and EVO (Verigy’s LTX-format) using Mentor Graphics
TestKompress, Fastscan, Cadence Encounter Test, and perl to include JTAG
controlled scan testing (JTAG generated using Mentor Graphics BSDArchitect.
Generated high yield, low test time, high coverage scan patterns for 5 different
chips sold to customers (4 in mass production, 1 sampling).
• Attached eval boards to Verge’s LTX protoboard and ran transition
fault scan, stuck fault scan, functional-speed ram/rom test, dc io test digital test
programs on Verigy’s LTX MX Tester both on protoboards, load boards, probe
cards, and in bench testing.
• Architected system test (DVB-T modulated (with or without noise
injection) rf input to chip, read out Bit Err (BER), Packet Error (PER), Signal-
Noise-Ratio (SNR, CN ratio), PLL Lock check, FEC lock check, etc.).
• Designed, inserted, generated WGL and EVO (Verigy’s LTX
format) for, and ran in usb & i2c-controlled benchtest and on Verigy’s LTX MX
Tester, High-Speed USB 2, Full-Speed/Low-Speed USB1 loopback and dc i/o
tests.
• For both usb/i2c/jtag bench test & for production tester: DC io test
design, architecture, insertion (Mentor Graphics BSDArchitect used for JTAG).
Generated high yield, low test time, high coverage dc iotest WGL & EVO
(Verigy’s LTX-format) for 5 different chips sold to customers (4 in mass
production, 1 sampling). Ran usb/i2c/jtag controlled dc io bench tests.
• Ran chip-level Cadence Encounter Timing System (ETS) static
timing. Including SDC generation, checking.
• Ran RTL & gate-level verilog & vhdl sim using Cadence NCsim
in both command mode and gui mode (with waveforms). Included Value Change
Dump (VCD) file generation for backend dynamic and static IR drop and power
analysis and smaller Toggle Count File (TCF) for static IR drop and power
analysis.
• Used Microsoft Visual Source Safe (VSS), Synchronicity
DesignSync, and Microsoft Sharepoint to check in files and documents.
• Assisted in hiring and fast digital-test training and working for 3
DFT engineers, 8 test engineers.
 • Reviewed & gave suggestions for loadboards, probecards,
customer eval boards, engineering eval boards, daughterboards, motherboards.
• Used Synopsys Synplify & Xilinx ISE to compile Xilinx FPGA
programs I wrote and to program Xilinx FPGAs.
• Used Source III VTRAN to convert file formats to/from Value
Change Dump (vcd) and Extended Value Change Dump (evcd) to/from WGL
• Used Synopsys Virage Memory Built-In Self-Test (bist) &
Memory Built-In Self-Repair (bisr)
• Worked on 65nm, 110nm, 130nm chips digital base-band clock
speeds up to 256 MHz, 480 Mbps high-speed USB i/o

26 June 2006-25 June 2007 Volt ASIC Engineer contractor at customer worksite, Fort
Collins, CO
• Proved rtl=gate level functional logic using Synopsys Formality
• Encrypted QPI, FBD, PCIE serdes component design for use in
customer chips.
• Worked with transistor-level circuit design and simulation
• Fort Collins, CO dc and ac test vector generation ATPG using
Synopsys Tetramax and Mentor Graphics Fastscan, dc and ac jtag and functional
loopback test vector generation, reported and fixed problems in gate-level netlist
that I received, test vector simulation using Cadence NC verilog and Synopsys
vcs, ran Spyglass, worked on 90nm chip with 12 GHz Quick Path
Interface/Common System Interface (CSI) for serdes i/o, pcie2 serdes i/o, fully
buffered dimm (fbd) serdes i/o

6-17 February 2006 Oxford ASIC Engineer contractor at customer worksite, Newport
Beach, CA
• Scan insertion, ATPG, and ram bist ram wrapper generation and
ram bist insertion fixes using Mentor Graphics DFTAdvisor and MBISTArchitect,
reported and fixed problems in gate-level netlist that I received, JTAG and ram
BIST simulation using Modelsim

6 March 2000-30 April 2004 Megachips Kawasaki ASIC Engineer, Wakefield, MA

• formal verification proving rtl=gate functional logic using
Synopsys/Avanti/Chrysalis Design Verifyer and Verplex
 • Hierarchical and flat, with timing constraints I generated, Synopsys
Design Compiler synthesis of vhdl and Verilog rtl into gate level logic
• (the following were performed for chips that went into mass
production and whose high level logic was designed by customer companies such
as Xerox (http://www.xerox.com, Rochester, NY), Westell
(http://www.westell.com, Chicago, IL), CoaxMedia (http://www.coaxmedia.com,
Atlanta, GA), Transition Networks (http://www.lanart.com, Boston, NY):
• gate-level simulation for test vector generation and verification
using Cadence Verilog XL, Cadence NC Verilog, Model Technologies' VHDL
vsim;
• conversion of non-scan flip-flops to edge-triggered mux scan flip-
flops (mux: I0=functional input data, I1=scan input data, Select=scan mode) using
Synopsys Test/DFT Compiler,
• Synopsys Tetramax used to automatically generate scan test
vectors,
• ram Built-In-Self-Test (bist) insertion and ram test vector
generation,
• conversion of unshared functional io to shared ram test chip i/o and
ram test vector generation,
• conversion of functional io without jtag to functional io with jtag,
• nandtree (for testing chip inputs) insertion and automatically
generated nandtree test vectors,
• static timing using Synopsys Prime Time and Design Time,
• Microsoft Excel spreadsheets,
• Microsoft Visio to draw diagrams,
• used gcc

July 1989-January 2000 IBM ASIC Engineer, Poughkeepsie, NY

• Proved rtl=gate level functional logic using IBM Booleseye
• Synthesis (with timing constraints I generated) of RTL (some of
which I primarily wrote) into gate level logic
• Altera MaxPlus2 FPGA & CPLD design, sim, timing, synthesis,
programming; ASIC fifo rtl design, clock design, rtl and gate sim, formal
verification, timing, logic bist sim, wrote and ran sim testcases in c
 • Clock designer including test clocks muxed with functional clocks,
clock gating, floorplanning clock distribution to minimize clock skew
• IBM’s ASX spice simulator
• Worked with latch circuits

EDUCATION:
• 1993-1994 Master of Science (MS) Computer Engineering,
GPA=3.7, Syracuse, NY (to include transistor-level digital circuit design, A in C+
+ class (Object Oriented Analysis))
• 1989-1995 Master of Science Electrical Engineering (MSEE),
GPA=3.4, NC A&T State University, Greensboro, NC (to include transistor-level
digital circuit design, simulation with spice, use of AutoCAD and OrCAD for
electronics drawings)
• 1980-1984 Bachelor of Science (BS) dual concentration Electrical
Engineering + Chemistry, GPA=3.4, US Military Academy, West Point, NY

DESIGNS:
• digital mass production test interface (Small electronics company)
• pci interface fifo (IBM)
• on-chip-memory & processor bus interface (IBM)
• clocks to include PLLs (IBM, Kawasaki LSI, Small electronics
company)
• encryption/decryption (school)

REFERENCES:

NC Lam, Mosys technical leader, 408-472-3106, [email protected]

3301 Olcott Street
Santa Clara, CA 95054
Jianguang Wang, Mosys co-worker, 408-832-5731, [email protected]
3301 Olcott Street
Santa Clara, CA 95054

Chao Zhang, LSI co-worker, 610-712-2388, [email protected]

1110 American Parkway
NE Lehigh Valley Central Campus
Mailstop 10B-374C
Allentown, PA 18109