DDR3L SDRAM Data Sheet Addendum

4Gb: x4, x8, x16 DDR3L SDRAM Addendum
Description
DDR3L SDRAM Data Sheet Addendum

MT41K1G4 – 128 Meg x 4 x 8 banks
MT41K512M8 – 64 Meg x 8 x 8 banks
MT41K256M16 – 32 Meg x 16 x 8 banks
Description • Self refresh temperature (SRT)

• Automatic self refresh (ASR)
DDR3L SDRAM (1.35V) is a low voltage version of the • Write leveling
DDR3 (1.5V) SDRAM. Refer to DDR3 (1.5V) SDRAM • Multipurpose register
(Die Rev.: E) data sheet specifications when running in • Output driver calibration
1.5V compatible mode.
Features Options Marking
• VDD = V DDQ = 1.35V (1.283–1.45V) • Configuration
• Backward compatible to V DD = V DDQ = 1.5V ±0.075V – 1 Gig x 4 1G4
– Supports DDR3L devices to be backward com- – 512 Meg x 8 512M8
patible in 1.5V applications – 256 Meg x 16 256M16
• Differential bidirectional data strobe • FBGA package (Pb-free) – x4, x8
• 8n-bit prefetch architecture – 78-ball (8mm x 10.5mm) Rev. P DA
• Differential clock inputs (CK, CK#) • FBGA package (Pb-free) – x16
• 8 internal banks – 96-ball (8mm x 14mm) Rev. P TW
• Nominal and dynamic on-die termination (ODT) • Timing – cycle time
for data, strobe, and mask signals – 938ps @ CL = 14 (DDR3-2133) -093
• Programmable CAS (READ) latency (CL) – 1.07ns @ CL = 13 (DDR3-1866) -107
• Programmable posted CAS additive latency (AL) – 1.25ns @ CL = 11 (DDR3-1600) -125
• Programmable CAS (WRITE) latency (CWL) • Special Options
• Fixed burst length (BL) of 8 and burst chop (BC) of 4 – Premium Lifecycle Product (PLP) X
(via the mode register set [MRS]) • Operating temperature
• Selectable BC4 or BL8 on-the-fly (OTF) – Commercial (0°C ≤ T C ≤ +95°C) None
• Self refresh mode – Industrial (–40°C ≤ T C ≤ +95°C) IT
• TC of 0°C to +95°C • Revision P
– 64ms, 8192-cycle refresh at 0°C to +85°C
– 32ms at +85°C to +95°C
Table 1: Key Timing Parameters
Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)
-093 1, 2 2133 14-14-14 13.09 13.09 13.09
-107 1 1866 13-13-13 13.91 13.91 13.91
-125 1600 11-11-11 13.75 13.75 13.75
Notes: 1. Backward compatible to 1600, CL = 11 (-125).

2. Backward compatible to 1866, CL = 13 (-107).
PDF: X26P4QTWDSPK-13-10329
4gb_1_35v_ddr3l_xit_addendum.pdf - Rev. A 02/16 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Description
Table 2: Addressing
Parameter 1 Gig x 4 512 Meg x 8 256 Meg x 16

Configuration 128 Meg x 4 x 8 banks 64 Meg x 8 x 8 banks 32 Meg x 16 x 8 banks
Refresh count 8K 8K 8K
Row address 64K (A[15:0]) 64K (A[15:0]) 32K (A[14:0])
Bank address 8 (BA[2:0]) 8 (BA[2:0]) 8 (BA[2:0])
Column address 2K (A[11, 9:0]) 1K (A[9:0]) 1K (A[9:0])
Page size 1KB 1KB 2KB
Figure 1: DDR3L Part Numbers

Example Part Number: MT41K256M16TW-107 XIT:P
- :
MT41K Configuration Package Speed Revision
{
Configuration Mark :P Revision
1 Gig x 4 1G4
512 Meg x 8 512M8 Temperature Mark
256 Meg x 16 256M16 Commercial None
Industrial temperature IT
Package Rev. Mark
78-ball 8mm x 10.5mm FBGA P DA Mark Special Options
96-ball 8mm x 14mm FBGA P TW X Premium Lifecycle Product (PLP)
Mark Speed Grade

-093 tCK = .938ns, CL = 14
-107 tCK = 1.07ns, CL = 13
-125 tCK = 1.25ns, CL = 11
Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on
http://www.micron.com for available offerings.
FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.
Revision History
Revision History
Rev. A – 02/16
• Initial release based on the 4Gb x4, x8, x16 DDR3L SDRAM, Rev. N 12/15 data sheet
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

DDR3L SDRAM Data Sheet Addendum

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DDR3L SDRAM Data Sheet Addendum

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4Gb: x4, x8, x16 DDR3L SDRAM Addendum

DDR3L SDRAM Data Sheet Addendum

Description • Self refresh temperature (SRT)

Table 1: Key Timing Parameters

Notes: 1. Backward compatible to 1600, CL = 11 (-125).

Parameter 1 Gig x 4 512 Meg x 8 256 Meg x 16

Figure 1: DDR3L Part Numbers

MT41K Configuration Package Speed Revision

Mark Speed Grade

FBGA Part Marking Decoder

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

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