UCC1837

UCC2837
UCC3837
8-Pin N-FET Linear Regulator Controller
FEATURES DESCRIPTION
• On Board Charge Pump to Drive The UCC3837 Linear Regulator Controller includes all the features re-
External N-MOSFET quired for an extremely low dropout linear regulator that uses an external
N-channel MOSFET as the pass transistor. The device can operate from
• Input Voltage as Low as 3V
input voltages as low as 3V and can provide high current levels, thus pro-
• Duty Ratio Mode Over Current viding an efficient linear solution for custom processor voltages, bus ter-
Protection mination voltages, and other logic level voltages below 3V. The on board
• Extremely Low Dropout Voltage charge pump creates a gate drive voltage capable of driving an external
N-MOSFET which is optimal for low dropout voltage and high efficiency.
• Low External Parts Count The wide versatility of this IC allows the user to optimize the setting of
both current limit and output voltage for applications beyond or between
• Output Voltages as Low as 1.5V
standard 3-terminal linear regulator ranges.
This 8-pin controller IC features a duty ratio current limiting technique that
provides peak transient loading capability while limiting the average
power dissipation of the pass transistor during fault conditions. See the
Application Section for detailed information.

BLOCK DIAGRAM
VDD CS CAP
1 8 2

CHARGE LEVEL
5 VOUT
PUMP SHIFT

CURRENT SENSE
AMPLIFIER ERROR AMPLIFIER
140mV
6 FB
+

UVLO
CURRENT SENSE 1.5V REF
COMPARATOR
100mV 3 GND
TIMER
+

7 4
CT COMP UDG-99145

SLUS228A - AUGUST 1999

 UCC1837
UCC2837
UCC3837
ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAM
All pins referenced to GND . . . . . . . . . . . . . . . . . –0.3V to +15V
CS, CT, FB . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to VDD + 0.3V DIL-8, SOIC-8 (Top View)
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C J or N Package, D Package
Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10sec.) . . . . . . . . . . . . . +300°C
Currents are positive into, negative out of the specified terminal.
Consult Packaging Section of Databook for thermal limitations
and considerations of packages.

ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = –55°C to 125°C for the UCC1837, –25°C to 85°C
for the UCC2837 and 0°C to 70°C for UCC3837; VDD = 5V, CT = 10nF, CCAP = 100nF.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Input Supply
Supply Current VDD = 5V 1 1.5 mA
VDD = 10V 1.2 2 mA
Under Voltage Lockout
Minimum Voltage to Start 2.00 2.65 3.00 V
Minimum Voltage After Start 1.6 2.2 2.6 V
Hysteresis 0.25 0.45 0.65 V
Reference ( Note 1 )
VREF 25°C 1.485 1.5 1.515 V
0°C to 70°C 1.470 1.5 1.530 V
–55°C to 125°C 1.455 1.5 1.545 V
Current Sense
Comparator Offset 0°C to 70°C 90 100 110 mV
Comparator Offset –55°C to 125°C 85 100 115 mV
Amplifier Offset 120 140 160 mV
Input Bias Current VCS = 5V 0.5 5 µA
Current Fault Timer
CT Charge Current VCT = 1V 16 36 56 µA
CT Discharge Current VCT = 1V 0.4 1.2 1.9 µA
CT Fault Low Threshold 0.4 0.5 0.6 V
CT Fault Hi Threshold 1.3 1.5 1.7 V
Fault Duty Cycle 2 3.3 5 %
Error Amplifier
Input Bias Current 0.5 2 µA
Open Loop Gain 60 90 dB
Transconductance –10µA to 10µA 2 5 8 mMho
Charge Current VCOMP = 6V 20 40 60 µA
Discharge Current VCOMP = 6V 10 25 40 µA

2
 UCC1837
UCC2837
UCC3837
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = –55°C to 125°C for the UCC1837, –25°C to 85°C
for the UCC2837 and 0°C to 70°C for UCC3837; VDD = 5V, CT = 10nF, CCAP = 100nF.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
FET Driver
Peak Output Current VCAP = 10V, VOUT = 1V 0.5 1.5 2.5 mA
Average Output Current VOUT = 1V 25 100 175 µA
Max Output Voltage VDD = 4.5V, IOUT = 0µA 8.4 9.7 V
VDD = 4.5V, IOUT = 10µA, 0°C to 70°C 8 9 V
VDD = 4.5V, IOUT = 10µA, –55°C to 125°C 7.5 9 V
Charge Pump
CAP Voltage VDD = 4.5V, C/S = 0V 11 12.5 V
VDD = 12V, C/S = 0V 15 16.5 V

Note 1: This is defined as the voltage on FB which results in a DC voltage of 8V on VOUT.

PIN DESCRIPTIONS
CAP: The output of the charge pump circuit. A capacitor CT: The input to the duty cycle timer circuit. A capacitor
is connected between this pin and GND to provide a is connected from this pin to GND, setting the maximum
floating bias voltage for an N-Channel MOSFET gate ON time of the over current protection circuits. See the
drive. A minimum of a 0.01µF ceramic capacitor is rec- Application Section for programming instructions.
ommended. CAP can be directly connected to an exter- FB: The inverting terminal of the voltage error amplifier,
nal regulated source such as +12V, in which case the used to feedback the output voltage for comparison with
external voltage will be the source for driving the the internal reference voltage. The nominal DC operating
N-Channel MOSFET. voltage at this pin is 1.5V
COMP: The output of the transconductance error ampli- GND: Ground reference for the device. For accurate out-
fier and current sense amplifier. Used for compensating put voltage regulation, GND should be referenced to the
the small signal characteristics of the voltage loop (and output load ground.
current loop when Current Sense Amplifier is active in
over curret mode). VDD: The system input voltage is connected to this
point. VDD must be above 3V. VDD also acts as one
CS: The negative current sense input signal. This pin side of the Current Sense Amplifier and Comparator.
should be connected through a low noise path to the low
side of the current sense resistor. VOUT: This pin directly drives the gate of the external
N-MOSFET pass element. The typical output impedance
of this pin is 6.5kΩ.

APPLICATION INFORMATION
Topology and General Operation tions of the UCC3837 itself. The charge pump output has
Unitrode Application Note U-152 is a detailed design of a a typical impedance of 80kΩ and therefore the loading of
low dropout linear regulator using an N-channel the IC and the external gate drive reduces the voltage
MOSFET as a pass element, and should be used as a from its ideal level. The UCC3837 can operate in several
guide for understanding the operation of the circuit states including having the error amplifier disabled (shut
shown in Fig. 1. down), in normal linear regulation mode, and in overdrive
mode where the linear regulator is responding to a tran-
Charge Pump Operation sient load or line condition. The maximum output voltage
The internal charge pump of the UCC3837 is designed to available at VOUT is shown in Fig. 2 for these various
create a voltage equal to 3 times the input VDD voltage modes of operation.
at the CAP pin. There is an internal 5V clamp at the input The charge pump output is designed to supply 10µA of
of the charge pump however that insures the voltage at average current to the load which is typically the
CAP does not exceed the ratings of the IC. This CAP MOSFET gate capacitance present at the VOUT pin.The
voltage is used to provide gate drive current to the exter- capacitor value used at CAP is chosen to provide holdup
nal pass element as well as bias current to internal sec-
3
 UCC1837
UCC2837
UCC3837
APPLICATION INFORMATION

R1 15
5V 0.020
14 OVERDRIVE
UCC3837 13 LINEAR REGULATOR
C1
330µF CS 8 12
Q1
E/A DISABLED
1 VDD IRL2203N 11
OR EQUIVALENT

VOUT
VOUT 5
3.3V 10
2 CAP
ON/OFF R2 C3 9
1.8k 1000µF
Q1 0.1µF
FB 6 8

R3 7
1.5k
GND 3 6
7 CT
0.1µF 5
4 COMP 3 4 5 6 7 8 9 10 11 12
RCOMP VDD
10k

CCOMP Figure 2. Typical VOUT(max) vs. VDD.

820pF

UDG-99137 mode of operation is linear, and therefore the channel re-

sistance is higher than the manufacturer’s published
Figure 1. Typical application 5V to 3.3V, 5A RDS(on) value. The MOSFET should only be operated in
the non-linear (switch) mode under transient conditions,
of the CAP voltage should the external load exceed the when minimum dropout voltage is required.
average current, which occurs during load and line tran-
Disabling the UCC3837
sient conditions. The value of CAP also determines the
startup time of the linear regulator. The voltage at CAP Grounding the CAP pin will remove the drive voltage and
charges up with a time constant determined by the effectively disable the output voltage. The device used to
charge pump output impedance (typically 80kΩ) and the short the output of CAP should have a very low leakage
value of the capacitor on CAP. current when in the OPEN state, since even a few
microamps will lower the charge pump voltage.
An external voltage such as +12V may be tied to the
CAP pin directly to insure a higher value of VOUT, which A second method of disabling the UCC3837 is to place a
may be useful when a standard level MOSFET is used or short circuit across CCOMP. This will have an advantage
when VDD is very low and the resulting VOUT voltage of a quicker restart time as the voltage at CAP will not be
may need to be higher. With an external source applied completely discharged. The charge pump will be loaded
to CAP, the maximum voltage at VOUT will be approxi- down by the typical 40µA charging current of the error
mately 1V below the external source.The external +12V amplifier with this configuration, resulting in a lower volt-
source should be decoupled to GND using a minimum of age at CAP.
a 0.01µF capacitor. Compensating the Error Amplifier
Choosing a Pass Element Using a MOSFET as an external pass element intro-
The UCC3837 is designed for use with an N-channel duces a pole in the control loop that is a function of the
MOSFET pass element only. The designer may choose UCC3837 output impedance, ROUT, typically 6.5kΩ, and
a logic level or standard gate level MOSFET depending the MOSFET input gate capacitance. Fig. 3 indicates
on the input voltage, the required gate drive, and the that in the normal operation of a linear regulator using a
available voltage at VOUT as discussed previously. MOSFET, the gate capacitance can be predicted directly
MOSFET selection should be based on required dropout from the MOSFET characteristic charge curve, using the
voltage and gate drive characteristics. A lower RDS(on) relationship:
MOSFET is used when low dropout is required, but this ∆Qgth
type of MOSFET will have higher gate capacitance which C IN =
∆Vgth
may result in a slower transient response.
This pole can be canceled by programming a zero fre-
A MOSFET used in linear regulation is typically operated
quency on the output of the UCC3837 error amplifier
at a gate voltage between the threshold voltage and the
equal to the pole frequency. Therefore:
gate plateau voltage in order to maintain high gain. This
4
 UCC1837
UCC2837
UCC3837
APPLICATION INFORMATION (cont.)
For the application circuit shown in Fig. 1, the voltage at
the error amplifier output will increase quickly by 400mV
due to the 40µA current through RCOMP. The error am-
plifier will then slew at approximately 50mV per micro-
second as the 40µA charges CCOMP.
From the IRL2203N data sheet, the typical required gate
voltage at room temperature, to deliver 5A is 2.6V. The
threshold for the device is approximately 1.5V. From the
gate charge curve for the IRL2203N, approximately 7nC
charge is required to change the gate voltage from 1.5V
to 2.6V. With 1.5mA gate drive current, the required time
UDG-97046
to charge the gate is therefore 4.7µs.

Figure 3. MOSFET turn-on characteristics. Overcurrent Protection and Thermal Management:

Overcurrent protection is provided via the UCC3837’s in-
1
F POLE = ternal current amplifier and overcurrent comparator. If at
2 • π • C IN • ROUT any time the voltage across the current sense resistor
1 crosses the comparator threshold, the UCC3837 begins
F ZERO = F POLE =
2 • π • RCOMP • CCOMP to modulate the output driver at a 3% duty cycle. During
the 3% on time, if the current forces 140mV across the
1 sense amplifier, the UCC3837 will enter a constant out-
RCOMP CCOMP =
2 • π • F POLE put current mode. Fig. 4 illustrates the cyclical retry of
the UCC3837 under fault conditions. Note that the initial
where CIN is the MOSFET input capacitance and ROUT is
fault time is longer than subsequent cycles due to the
the output impedance of VOUT.
fact that the timing capacitor is completely discharged
The value of CCOMP should be large enough that and must initially charge to the reset threshold of 0.5V.
parasitics connected to COMP do not effect the zero fre-
quency. A minimum of 220pF is recommended.
Transient Response
The transient performance of a linear regulator built us-
ing the UCC3837 can be predicted by understanding the
dynamics of the transient event. Consider a load tran-
sient on the application circuit of Fig. 1, where the output
current steps from a low value to a high value. Initially,
the output voltage will drop as a function of the output
capacitors ESR times the load current change. In re-
sponse to the decrease in feedback voltage at FB, the
UCC3837 error amplifier will increase its charge current
to a typical value of 40µA. The output of the amplifier will
therefore respond by first stepping the voltage propor-
tional to 40µA times RCOMP, and then ramping up pro-
portional to 40µA and the value of CCOMP. Dynamic
response can therefore be improved by increasing
RCOMP and decreasing CCOMP .
The value of VOUT will increase the same amount as the
UDG-97046
increase in the error amplifier output. The UCC3837 out-
put gate drive current, however, is internally limited to
1.5mA. The response of the voltage at the gate of the ex- Figure 4. Load current, timing capacitor voltage and
ternal pass element is therefore a function of the 1.5mA output voltage under fault conditions.
drive current and the external gate charge, as obtained
from the MOSFET data sheet gate charge curve.
5
 UCC1837
UCC2837
UCC3837

Fault time duration is controlled by the value of the timing heat sink need only have adequate thermal mass to ab-
capacitor, CT, according to the following equation: sorb the maximum steady state power dissipation and
∆V 1. 5 − 0. 5 (1) not the full short circuit power. With a 5.25V input and a
t FAULT = CT • = CT • = 27.8 • 10 3 • CT maximum output current of 5A, the power dissipated in
I 36 • 10 −6
the MOSFET is given by:
Fig. 5 provides a plot of fault time vs. timing capacitance. P = (V IN − V SENSE − VOUT ) • IOUT (4)
The fault time duration is set based upon the load capac-
itance, load current, and the maximum output current. P = ( 5 . 25 − ( 5 • 0. 02) − 3 . 3) • 5 = 9 . 25W
The “on” or fault time must be of sufficient duration to
Given that the thermal resistivity of the MOSFET is spec-
charge the load capacitance during a normal startup se-
ified as 1°C/W for the TO-220 package style and assum-
quence or when recovering from a fault. If not, the
ing an ambient temperature of 50°C and a case to heat
charge accumulated on the output capacitance will be
depleted by the load during the “off” time. The cycle will sink resistivity of θCS = 0.3°C/W, the heat sink required
then repeat, preventing the output from turning on. to maintain a 125°C junction temperature can be calcu-
lated as follows:
30 T J = T A + P (θ JC + θCS + θ SA ) (5)

25 125 = 50 + 9 . 25 • (1 + 0.3 + θ SA )
θ SA ≤ 6 . 8 ° C
FAULT TIME (ms)

20 W
15 Based on this analysis, any heatsink with a thermal re-
sistivity of 6.8 °C/W or less should suffice. The current in
10 the circuit of Fig. 1, under short circuit conditions, will be
limited to 7A at a 3% duty cycle, resulting in a MOSFET
5 power dissipation of only:
0 P= [(V IN (max ) ) ]
− IOUT • (R SENSE ) • IOUT • Duty (6)
0 0.2 0.4 0.6 0.8 1
CT (uF)
P= [(5. 25 − 7 • (0 . 02)) • 7] • 0 . 03 = 1. 07W
Figure 5. Fault time vs. timing capacitance.
Without switchmode protection, the short circuit power
To determine the minimum fault time, assume a maxi- dissipation would be 35.8W, almost four times the nomi-
mum load current just less than the trip limit. This leaves nal dissipation.
the difference between the IMAX and ITRIP values as the
current available to charge the output capacitance. The Using Printed Circuit Board Etch as a Sense Resistor
minimum required fault time can then be calculated as Unitrode Design Note DN-71 discusses the use of
follows: printed circuit board copper etch as a low ohm sense re-
COUT • VOUT (2) sistor. This technique can easily be applied when using
t FAULT (min) = the UCC3837. The application circuit shown in Fig. 1 can
I MAX − ITRIP
be used as an example. This linear regulator is designed
The minimum timing capacitor can be calculated by sub- with a 5A average load current, demanding a 20mΩ
stituting equation (1) for tFAULT in equation (2) and solv- sense resistor to result in a 100mV current sense com-
ing for CT. parator signal for the UCC3837. The maximum ambient
temperature of the linear regulator is 70°C.
COUT • VOUT (3)
CT (min) = Using DN-71, a 1 ounce outer layer etch of 0.05 inches
27 . 8 • 10 • (I MAX − ITRIP )
3
wide and 1.57 inches long results in a resistance of
20mΩ at an ambient temperature of 70°C and an operat-
Switchmode protection offers significant heat sinking ad-
ing current of 5A. Because the resistivity of copper is a
vantages when compared to conventional, constant cur-
function of temperature, the current limit at lower temper-
rent solutions. Since the average power during a fault
atures will be higher, as shown in Fig. 6.
condition is reduced as a function of the duty cycle, the

6
 UCC1837
UCC2837
UCC3837
APPLICATION INFORMATION
RESISTANCE SHORT CIRCUIT LIMIT To illustrate the importance of these concepts, consider
the effects of a 1.5" PCB trace located between the out-
21 9
put capacitor and the UCC3837 feedback reference. A

SHORT CIRCUIT CURRENT

COPPER RESISTANCE [mW]

20 0.07" wide trace of 1oz. copper results in an equivalent

8
resistance of 10.4mΩ. At a load current of 3A, 31.2mV is
19 dropped across the trace, contributing almost 1% error to
7
18 the DC regulation. Likewise, the inductance of the trace
6 is approximately 3.24nH, resulting in a 91mV spike dur-
17 ing the 100ns it takes the load current to slew from
5 200mA to 3A.
16
The dropout voltage of a linear regulator is often a key
15 4 design parameter. Calculations of the dropout voltage of
0 20 40 60 80 a linear regulator based on the UCC3837 Controller
AMBIENT TEMPERATURE [°C] should consider all of the following:
• Sense resistor drop, including temperature and
Figure 6. Copper resistance and short circuit limit
tolerance effects,
for example resistor.
• Path resistance drops on both the input and output
Practical Considerations voltages,
In order to achieve the expected performance, careful at- • MOSFET resistance as a function of temperature and
tention must be paid to circuit layout. The printed circuit gate drive, including transient performance,
board should be designed using a single point ground,
referenced to the return of the output capacitor. All • Ground path drops.
traces carrying high current should be made as short and
wide as possible in order to minimize parasitic resistance
and inductance effects.

UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 FAX (603) 424-3460

7
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

UCC2837D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2837

UCC2837DTR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2837

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-Nov-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC2837DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-Nov-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC2837DTR SOIC D 8 2500 853.0 449.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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