5 4 3 2 1

Foxconn Precision Co. Inc.

D G41M01 Schematic D

Fab.A
Data: 2008/7/15
Page Index
01. Index Page 25. ICH7 -1
02. Topology 26. ICH7 -2
03. Rest Map 27. ICH7 -3
04. Clock Distribution 28. REAR USB
C
05. Power Delivery Map 29. TPM C

06. Power Sequence 30. PCIE1X

07. BLANK 31. PCI Slot
08. CK505 ClockGen 32. LAN-RTL8101E/RTL8111C
09. Power / MISC Connectors 33. AUDIO 662
10. Voltage Regulator Down 11 34. AUDIO PORT
11. OUTPUT CAP 35. Super I/O ITE8718F/GX
12. 1D25V 1D5V FSB 36. Keyboard / Mouse / Fan
13. STR1D8V 3D3_DUAL 37. Serial / Parallel
14. LGA775 -1 38. FRONT USB
B

15. LGA775 -2 39. changlist B

16. Broadwater -GMCH -1 40. SWITCH

17. Broadwater -GMCH -2
18. Broadwater -GMCH -3
19. DDR2 Channel A Termination
20. DDR2 Channel A DIMM1, 2
21. DDR2 Channel B Termination
22. DDR2 Channel B DIMM1, 2
23. PCI Express x16 Gfx Slot
A 24. VGA Connector A

FOXCONN PCEG
Title
Index Page
Size Document Number Rev
C G41M01 A

Date: Monday, July 21, 2008 Sheet 1 of 38

5 4 3 2 1
 5 4 3 2 1

Yorkfield
Wolfdale
VRD 11.1 LGA775 Processor
3 Phase PWM
D Socket T D

800/1066/1333/1600(oc) FSB
CK-505 Clock

PCI Express x 16 Channel A DDR2

PCI Express x16 Port DDR2 667/800/1066
External Graphics
DIMM1
Card

GMCH DDR2 667/800/1066 Channel B DDR2

VGA Connector
Eaglelake DIMM1

C C

Back Panel
PCIe port
USB2.0 Port 7 LAN
4 Lanes
USB2.0 Port 8 Realtek
Direct Media Interface (DMI)
USB2.0 Port 5 Controller Link
USB2.0 Port 6
PCI Slot 1X2
SPI Flash

Header ICH7
USB2.0 Port 1
USB2.0 Port 2

USB2.0 Port 3
B
USB2.0 Port 4 B

Serial ATA

LPC I/F
SATA Connector 1
IDE AHCI, RAID0,1,5,10

SATA Connector 2

SPI Flash SATA Connector 3

(BIOS) SATA Connector 4

PCI Express x 1

HDA Codec
TPM Realtek ALC662/888
TPM
LPC I/F
Super I/O
IT8720/FX
A A

Floppy
IR/CIR Serial & Parallel
Drive Connector
FOXCONN PCEG
Title
TOPOLOGY
Size Document Number Rev
C G41M01 A

Date: Monday, July 21, 2008 Sheet 2 of 38

5 4 3 2 1
 5 4 3 2 1

CPU
(Cedar Mill/Presler/Conroe/Allendale)

CPU_PWRGD

CPURST#
D
LGA775 processor D

ATX
Power
Vtt_PwrGd CK505

Translation PWRGD_3V
PWRGD_PS PWROK CPURST#
Circuitry PCI Express x16
PS_ON#
GMCH
Broadwater
C
RSTIN# C

ICH7
ICH_PWRGD
CK_PWRGD
SLP_M#
PCIRST#

PLTRST#

Front Panel PWROK ACZ_RST#

RST# Audio
FR_RST SYS_RESET# LAN_RSTSYNC

B B
SW_ON PWRBTN#
RSMRST#

RCIN#

SLP_S3#

RST#
TPM

RST#
RST#
Power on/off KBRST PCI Slot 1
circuit RSMRST#
Super IO
RST# PCIe Slot
SLP_S3# PCIe LAN
PSOUT
PSIN RST#
A IDE Controller A

PSOUT#

RSMRST circuit FOXCONN PCEG

Title
Reset Map
Size Document Number Rev
C G41M01 A

Date: Monday, July 21, 2008 Sheet 3 of 38

5 4 3 2 1
 5 4 3 2 1

14.318MHz

CPU

D
CPU 200/266/333 MHz Diff Pair D

MCH 200/266/333 MHz Diff Pair

PCI Express 100 MHz Diff Pair PCI Express x16 Gfx Channel A DDR2
DIMM1
GMCH
DOT 96 MHz Diff Pair Broadwater

Channel B DDR2
DIMM1
PCI Express/DMI 100 MHz Diff Pair
C C
CK-505

PCI Express/DMI 100 MHz Diff Pair

USB/SIO 48 MHz

ICH 33 MHz

REF 14 MHz
SPI Clock SPI

ICH7
Azalia Bit Clock

B
PCI 33 MHz PCI Slot 1 B

TPM 33 MHz TPM

32.768KHz

HD Audio

SIO 33 MHz Super I/O

SATA 100 MHz Diff Pair

PCI Express 100 Mhz Diff Pair
A A

FOXCONN PCEG
Title
Clock Distribution
Size Document Number Rev
C G41M01 A

Date: Monday, July 21, 2008 Sheet 4 of 38

5 4 3 2 1
 5 4 3 2 1

3.3V Super I/O

ATX P/S 3.3V
Icc(Max)=50mA
Proceessor
Vccp (CPU Vcore)
5V 5VSB VRD 11 3.3SBV
12V Voltage=1.15~1.5V 5V
Switching Icc(Max)=50mA(S0)
Icc(Max)=125A
Three Phase
5VDUAL 3-Phases Swithing 3.3SBV
D
DDR2 Channel A Icc(Max)= Icc(Max)=38mA(S3)
D

1.2V FSB 5VSB

Vdd (Core)=1.8V 10A Vtt=5.3A
Ivdd(Max)=TBD(per channel)
USB2.0 10 Ports 5VDUAL
+5V DUAL=5A(S0, S1) Icc(Max)=
Vtt (Core) Broadwater GMCH 4.345A(S0,S1)
Single Phase Switch +5V DUAL=20mA(S3)
0.9V 22mA(S3)
Ivterm(Max)=200mA 5V to 1.8V
Ivdd(Max)=TBD FSB_Vtt
(per channel) Linear 1.8V PS2
LDO 1.2V FSB Vtt
to 1.2V +5V DUAL=345mA(S0, S1)
1.8V to 0.9V Icc(Max)=1.3A
6A +5V DUAL=2mA(S3)
Ivterm(Max)=1.2A
DDR2 Channel B
1.8V VCCSM FWH
Vdd (Core)=1.8V 1.8V VCC_SMCLK
Ivdd(Max)=TBD(per channel) 3.3V=107mA(S0, S1)

GMCH 1.25 V Vcore (Core Logic) PCI Express X16

Vtt (Core) 3.3V 21.34A 1.25V
0.9V Switching Icc(Max)=18.8A(Integrated)
slot (1)
Ivterm(Max)=200mA 12V
*1.25V (DMI&PCIe) +12V=5.5A
(per channel) VCCA_EXP 2.5A
3.3VSB
C
1.25V C
Icc(Max)=0.375A(wake)
VCC_CL 3.8A
Icc(Max)=0.02A(no wake)

+3.3V=3A
3.3V VCCA_DAC 70mA
3.3V VCC3_3 15.8mA
PCI Express X1
Per slot (1)
+12V=0.5A
HDA Codec
3.3VSB
Vcc LDO Icc(Max)=0.375A(wake)
5V 12V ICH7 Icc(Max)=0.02A(no wake)
Icc(Max)=200mA to 5V
1.25V VCCDMI 40mA
Vcc +3.3V=3A
3.3V Linear 1.25V 1.2V VCC_CPU_IO 14mA
Icc(Max)=40mA to 1.05V
V_1P05V_ICH 1.05V (Core) VCC1_05
2A 1.17A PCI Per Slot (X2)
1.5V (USB &SATA) VCC1_5A -12V
B -12V B
Linear 1.8V 1.12A Icc(Max)=0.1A
to 1.5V 1.5V (PCIe)VCC1_5B
V_1P5V_ICH 0.77A 5V
2.2A 1.5V VCCGLAN1_5 5V Icc(Max)=5A
74mA
3.3V
RTC
5VSB RTC=5uA Icc(Max)=7.6A
Battery
12V
3.3V VccCL3_3 12mA Icc(Max)=0.5A
5V_STBY to 3.3SB 3.3V VccSUS3_3 141mA
1.5A 3.3V VccLAN (10/100) 12mA 3.3VSB
3.3V VccSUSHDA 4mA Icc(Max)=0.375A(wake)
3.3V VCC3_3 310mA Icc(Max)=0.02A(no wake)

3.3V
3.3V VccGLAN3_3 1mA
3.3V VccHDA 4mA

Nineveh GbE Lan

3.3V STBY
A IO LED 15.5nA A

1.8V ANALOG 418.2mA BJT

CK505
1.0V Internal 1.8
to 1.0 VR core Vdd (Core) FOXCONN PCEG
277.2mA 3.3V Title
Ivdd(Max)=250mA Power Delivery Map
Size Document Number Rev
C G41M01 A

Date: Monday, July 21, 2008 Sheet 5 of 38

5 4 3 2 1
 5 4 3 2 1

S0->S5
+12V_SYS +12V_SYS
S5->S0
D D
+5V_DUAL +5V_SYS +5V_SYS +5V_DUAL

+3D3V_DUAL +3D3V_SYS +3D3V_SYS +3D3V_DUAL

+1D8V_STR +1D8V_STR

VTT_DDR
VTT_DDR
VTT_VR VTT_VR

Vcc Vcc

1ms to 10ms
Vcc_PWRGD
Vcc_PWRGD
VRM_OUTEN
VRM_OUTEN
VIDPWRGD VIDPWRGD PS_ONJ
C
PS_ONJ C

S0->S3 S3->S0
+12V_SYS +12V_SYS

+5V_SYS +5V_DUAL +5V_DUAL +5V_SYS

+3D3V_SYS +3D3V_DUAL +3D3V_DUAL +3D3V_SYS

B B

+1D8V_STR +1D8V_STR +1D8V_STR +1D8V_STR

VTT_DDR
VTT_DDR
VTT_VR VTT_VR

Vcc Vcc

1ms to 10ms
Vcc_PWRGD
Vcc_PWRGD
VRM_OUTEN
VRM_OUTEN
VIDPWRGD PS_ONJ VIDPWRGD
PS_ONJ

A A

FOXCONN PCEG
Title
Power Sequence
Size Document Number Rev
C G41M01 A

Date: Monday, July 21, 2008 Sheet 6 of 38

5 4 3 2 1
 5 4 3 2 1

3D3V_SYS 3D3V_SYS

FB17 0 Dummy
FB18 0 3D3V_CLK +/-5%
+/-5% CP2 3D3V_CLK_SATA_25M

4.7uFC106

10nFC113

10nFC116
25V, X7R, +/-10%
6.3V, X5R, +/-10%

16V, Y5V, +80%/-20%

CP3 3D3V_CLK X_COPPER

4.7uFC107

10nFC120

10nFC127

10nFC129

10nFC143

10nFC115
25V, X7R, +/-10%

25V, X7R, +/-10%

25V, X7R, +/-10%

25V, X7R, +/-10%

25V, X7R, +/-10%

6.3V, X5R, +/-10%

1
Dummy X_COPPER * * * Dummy

1
* * * * * *

2
2

2
3D3V_SYS
D Change to 0Ohm RES or not D

FB19 0
3D3V_CLK_48M +/-5%

10nFC132
CP6 3D3V_CLK_REF_A

25V, X7R, +/-10%

10nFC133

10nFC123
25V, X7R, +/-10%
16V, Y5V, +80%/-20%
Dummy X_COPPER

1
* C131

1
* 4.7uF
6.3V, X5R, +/-10% * *

2
3D3V_CLK 3D3V_CLK Dummy
TBD

R83 3D3V_CLK
*4.7K
+/-5%

* R86 R82
4.7K Reserved U8 4.7K
+/-5% +/-5%
1 64 dummy
**RLATCH 25Mhz_0F_2x
2 GND GND 63
3D3V_CLK 3 62 3D3V_CLK_SATA_25M
24M_1394 VDD VDD25Mhz_STB 3D3V_CLK_SATA_25M
4 **GSEL/24.576Mhz VDDSATA_STB 61
30
34
CK_33M_PCI2
CK_33M_SIO
CK_33M_PCI2
CK_33M_SIO
*1 RN17
2 33
3D3V_CLK 5
6
VDDPCI SATACLKT_LR 60
59
SATA_100M_P_ICH
SATA_100M_N_ICH
CK_SATA_100M_P_ICH
CK_SATA_100M_N_ICH
25
25

*
CK_33M_TPM 3 4 +/-5% R90 4.7K Dummy GND SATACLKC_LR
28 CK_33M_TPM 7 58

*
CK_33M_ICH 5 6 +/-5% **DOC1 GND R87 33 +/-5%
26 CK_33M_ICH 7 8 8 PCICLK0 REF0_2x/FSLC 57 CK_14M_ICH 24
9 56 ICS_FSBSEL2
ICS_FSBSEL1 *Freerun/PCICLK1_2x GND X2
10 FSLB/PCICLK2_2x X1 55
8,12,24 ICH_SYS_RSTJ 11 SELRSET/RESET#/PCICLK32 X2 54 1 2
12 53 3D3V_CLK_REF_A
***

*
CK_33M_PCI1 R93 33 +/-5% R94 4.7K Dummy PCICLK4 VDDREF_STB CP4 C108 C109
30 CK_33M_PCI1 13 **DOC0 SDATA 52 SMB_DATA_MAIN 19,21,35
27pFXTAL-14.318MHz

RTM875T-531
CK_48M_ICH 3D3V_CLK_48M
C
24
34
CK_48M_ICH
CK_48M_SIO
CK_48M_SIO
R96 33
R10033
+/-5%
+/-5% ICS_FSBSEL0
+/-5% 14
15
VDD48
FSLA/USB_48MHz
SCLK
GND
51
50
CP5
X_COPPER
SMB_CLK_MAIN 19,21,35 * +/-5% * 27pF
+/-5%
C

16 49 200M_P_CPU X_COPPER
CK_200M_P_CPU 12
1=24MHz 4.7K
* +/-5% *SEL24_48#/24_48Mhz CPUT_LR0 200M_N_CPU
17 GND CPUC_LR0 48 CK_200M_N_CPU 12
0=48MHz R101 VRMPWRGD 18 47 3D3V_CLK
96M_P_GMCH Vtt_PwrGd/WOL_STOP# VDDCPU 200M_P_GMCH
14 CK_96M_P_GMCH 19 DOT96T_LR/PCIeT_LR0 CPUT_LR1 46 CK_200M_P_GMCH 14
96M_N_GMCH 20 45 200M_N_GMCH
14 CK_96M_N_GMCH DOT96C_LR/PCIeC_LR0 CPUC_LR1 CK_200M_N_GMCH 14
21 44 3D3V_CLK
GND VDDI/O
31 CK_PE_100M_P_LAN 22 PCIeT_LR1 GNDA 43
31 CK_PE_100M_N_LAN 23 42 3D3V_CLK_REF_A
PCIeC_LR1 VDDA_STB
29 CK_PE_100M_P_1PORT_2 24 PCIeT_LR2 PCIeT_LR8 41
29 CK_PE_100M_N_1PORT_2 25 PCIeC_LR2 PCIeC_LR8 40
26 39 PE_100M_P_GMCH
GND PCIeT_LR7 CK_PE_100M_P_GMCH 14
PE_100M_P_16PORT 27 38 PE_100M_N_GMCH
22 CK_PE_100M_P_16PORT PCIeT_LR3 PCIeC_LR7 CK_PE_100M_N_GMCH 14
PE_100M_N_16PORT 28 37
22 CK_PE_100M_N_16PORT

**
R324 0 PCIeC_LR3 GND
14 DPL_REFSSCLKINP
Dummy 29 PCIeT_LR4 PCIeT_LR6 36
R354 0
Dummy 30 35
14 DPL_REFSSCLKINN PCIeC_LR4 PCIeC_LR6
31 34 PE_100M_P_ICH CK_PE_100M_P_ICH 24
3D3V_CLK GND PCIeT_LR5 PE_100M_N_ICH
32 VDDPCIEX PCIeC_LR5 33 CK_PE_100M_N_ICH 24

RTM875T-531-VA-GRT

3D3V_CLK

FSB_VTT

*R102
8.2K
+/-5%

VRMPWRGD VRMPWRGD 9,12,24

RN19
B *1 2 FSBSEL0
FSBSEL0 12,14
B
3 4 FSBSEL2
5 6 FSBSEL2 12,14
FSBSEL1
7 8 FSBSEL1 12
470
+/-5%

FSBSEL1
ICS_FSBSEL0 R95 2.2K
* * * +/-5% FSBSEL0

ICS_FSBSEL1 R88 +/-5% FSBSEL1_1 R92

CK_33M_PCI1 2.2K
* 0
CK_33M_PCI2 ICS_FSBSEL2 R99 2.2K +/-5% FSBSEL2
FSBSEL1_1 14
Reserved
CK_48M_SIO

C
*
CK_48M_ICH FSBSEL2 R97 1K +/-5%
Dummy Q8
B Dummy
MMBT3904-7-F
CK_33M_SIO

E
CK_33M_ICH

CK_14M_ICH

CK_33M_TPM
50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

C126 C112
50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

* 10pF
Dummy * 10pF
Dummy *
C134
10pF
*
C130
22pF
*
C114
10pF
*
C121
10pF
*
C122
10pF
*
C117
10pF
50V, NPO, +/-5%
Dummy Dummy Dummy Dummy Dummy
A A

BSEL TABLE

FS_C FS_B FS_A FSB Frequency

0 0 1 133MHz(533)
0 1 0 200MHz(800) FOXCONN PCEG
0 0 0 266MHz(1066) Title

1 0 0 333MHz(1333) BLANK
Size Document Number Rev
1 1 0 400MHz(1600) C G41M01 A

Date: Monday, October 06, 2008 Sheet 7 of 38

5 4 3 2 1
 5 4 3 2 1

3D3V_SYS 3D3V_SYS 5V_SYS 5V_SB -12V_SYS 12V_SYS

25V, X7R, +/-10%

25V, X7R, +/-10%

C392 C416 C413 C424

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

1
0.1uF 0.1uF 0.1uF 0.1uF
5V_SB -12V_SYS 3D3V_SYS 3D3V_SYS 12V_SYS 5V_SB * * * * * C417 * C423
0.1uF 0.1uF

2
5V_SYS
5V_SYS
*R339
4.7K 13 +3.3V3 +3.3V1
PWR1
1 5V_SYS
D +/-5% 14 2 D
-12V +3.3V2

34 PS_ONJ
15
16
GND4
PSON
GND1
+5V1
3
4 *R380
4.7K
place at power connecter
17 5 +/-5%
C414 GND5 GND2
18 GND6 +5V2 6
0.1uF
* 16V, Y5V, +80%/-20%
19
20
GND7 GND3
RSVD PWR0K
7
8 PWRG_ATX
PWRG_ATX 10,11,34
21 9 C415
+5V3 +5V_AUX 0.1uF
22
23
+5V4
+5V5
+12V_1
+12V_2
10
11
* 16V, Y5V, +80%/-20%
24 GND8 +3.3V4 12
Dummy
Header_2x12

5V_SYS 3D3V_SB 5V_SYS

5V_SB

R334 R362 3D3V_SYS 3D3V_SYS 12V_SYS

C 330 * 8.2K
*R376 C

25V, X7R, +/-10%

25V, X7R, +/-10%

+-5% +/-5% R335 4.7K C393

16V, Y5V, +80%/-20%

330 +/-5% C95 C209

1
+-5% 10nF 0.1uF 0.1uF
1
FP1
2
* * *
HDD_LEDJ 3 4 Dummy
25 HDD_LEDJ

2
5 6 PBTNJ_SIO
PBTNJ_SIO 34
7,12,24 ICH_SYS_RSTJ 7 8
9 X C412 C456
220pF 220pF
Header_2X5_K10 * Dummy * Dummy
C411 C445 5V_SYS 5V_SYS 1D1V_MCH
220pF 220pF
* 50V, NPO, +/-5%50V, NPO, +/-5% * C226 C154

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

0.1uF C227 0.1uF
* *

16V, Y5V, +80%/-20%

Dummy Dummy TBD 3D3V_SYS 0.1uF
*
R337
* 10K
+/-5%

C
Q25 MMBT3904-7-F Reserved
Front Panel Switch/LED

*
B PWR_LED 34
R338 1K+/-1%
HD_LED+ 1 2 Power Reserved

E
HD_LED- 3 4 Power LED(Green)
B
GND 5 6 Power button Change to 5% or not
B
Reset button 7 8 Power
NC 9 10 Key

SPEAKER HEADER
SPEAKER
1 1
5V_SYS
Confirm must use or not

3 3
4 4
5V_SYS RN14
*1 2
Header_1X4_K2
@SPEAKER
3 4 BUZ
5 6
7 8 +
*R73
4.7K 100 Ohm BUZZER
+/-5% +/-5% -

Buzzer
D15
C

1 @Buzzer
24 SPKR
*

3 R72 2.2K B Q5 C102

+/-5% MMBT3904-7-F 1uF
34 SIO_BEEP 2
* +/-10%
E

A A
BAT54C

32 BEEP_PC
FOXCONN PCEG
Title
Power/MISC Connectors
Size Document Number Rev
Custom G41M01 A

Date: Thursday, September 18, 2008 Sheet 8 of 38

5 4 3 2 1
 5 4 3 2 1

12V_VRM
VIN
PD3 VIN

16V, Y5V, +80%/-20%

5V_SYS
BAT54HT1G * PR14
12V_VRM A C 2.2 C255
* 0.1uF

1
PR26
* *PR29 PR13 PC11
* PC10

D
2.2 10K 2.2 220nF 4.7uF
+/-1% PQ7 16V, Y5V, +80%/-20%

2
1
PU3
4 8 PR16 2.2 G VCCP

BST
VTT_OUT_RIGHT VCC DRVH AOD452 PL3

*
PC30 PR28
* * PC28 PR15 10K 300nH@100KHz

DS
* 1uF 1K 0.1uF 7 P_PHASE1 2 1

D
SW

*
10V, Y5V, +80%/-20%+/-1% 16V, Y5V, +80%/-20% 2

GND
*
PWM

DAC
PR18 2.2 3 5 PQ9 PQ8 PR17
EN DRVL 2.2
D NCP5359DR2G P_DRVL1 D
G G
Output Ecap

6
1

1
PU4
* PC13

35
36
34
1uF AOD472 AOD472 CP25 CP24

S
*
PR35 0 39
* PC12 COPPER COPPER VCCP

VPP/TEST
VCC

12VMON

2
7,12,24 VRMPWRGD VRM_EN VR_RDY P_DRVON 1nF
1 29

2
ENABLE DRVON P_PWM1 50V, X7R, +/-10%
12 VID0 2 VID0 G1 30
3 21 P_ISEN1+
12 VID1

*
VID1 CS1N P_CS1 PR24 100KOhm 12V_VRM P_ISEN1-
12 VID2 4 VID2 CS1 22
12 VID3 5
6
VID3 PR19
dummy
* PC17
0.1uF PD2 VIN
P_ISEN1+
PEC12 PEC10 PEC9 PEC11
12 VID4 * PR10

*
VID4
12 VID5 7 P_ISEN1- 910 Ohm PC20 470nF 16V, Y5V, +80%/-20% BAT54HT1G VIN * 820uF * 820uF * 820uF * 820uF

* *
VID5 +/-1% dummy +/-20% +/-20% +/-20% +/-20%
12 VID6 8 VID6 A C 2.2 Dummy Dummy
9 31 P_PWM2 +/-10%
12 VID7
* VID7 G2

1
P_PSI_N P_ISEN2+
PR40 0 37 23 PR9 PC7
* PC2 C243

D
13 PSI# PSI CS2N
dummy 15 DIFFOUT CS2 24 P_CS2 PR23 100KOhm
dummy
* PC14
2.2 220nF
PQ2
4.7uF
* 0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

2
*

1
PR42 75 PC32 680pF PR37 6.49KOhm
PC31 1.8nF COMP 16 PR21 0.1uF PU2

*
*

*
+/-1% 50V, X7R, +/-10% +/-1% 50V, X7R, +/-10% COMP P_ISEN2- 910 Ohm PC19 470nF 16V, Y5V, +80%/-20% PR6 2.2 VCCP PEC8 PEC6 PEC5 PEC7
4 8 G

BST
*
VCC DRVH
+/-1% dummy AOD452 PL2 * 820uF * 820uF * 820uF * 820uF

*
PR43 1K +/-1% PC33 22pF +/-10% PR5 10K 300nH@100KHz +/-20% +/-20% +/-20%
Dummy +/-20%

DS
**
50V, NPO, +/-5% 32 P_PWM3 7 P_PHASE2 2 1

D
*

G3 SW

*
PR33 100KOhm VFB 17 25 P_ISEN3+ 2

GND
5V_SYS

*
dummy PR36 5.6K VFB CS3N P_CS3 PR22 100KOhm PR12 2.2 PWM PQ6 PQ4 PR2
26 3 5
*PR38 +/-1% 18 VDRP
CS3 dummy
* PC16 EN DRVL 2.2
100KOhm PR20 0.1uF NCP5359DR2G P_DRVL2 G G

6
*

1
P_ISEN3-
dummy PR39 51.1Ohm PC29 680pF 910 Ohm PC18 470nF 16V, Y5V, +80%/-20%
* PC9

*
+/-1% dummy 50V, X7R, +/-10% +/-1% dummy 1uF AOD472 AOD472 CP21 CP23

S
*

PR30 475 dummy +/-10%

* PC4 COPPER COPPER

2
*
Place close * +/-1% 33 P_PWM4 PR34 0 1nF

2
G4
to inductor T PRT1
+/-5% PR31 * PC27
22pF * CS4N
CS4
27
28 VCCP
50V, X7R, +/-10%

4.7K 1K 50V, NPO, +/-5% P_ISEN2-

VCCP 5V_SYS 12V_VRM P_ISEN2+
*

PR27 475 19
+/-1% VDFB PD1 VIN C194 C196 C192
PR46 PR32 *PR41 BAT54HT1G * PR7 VIN
* 10uF
* 10uF
* 10uF
*

100 Ohm DAC PC15 10nF PR25 1K 470 Ohm

20 CSSUM 2.2K A C 2.2 +/-10% +/-10%
Dummy +/-10%
Dummy
*

25V, X7R, +/-10% +/-1% +/-1% C67

*

1
VCC_SENSE_R
PR47 0 13 VSP 40 PR11 PC6
* PC1
* 0.1uF

D
12 VCC_SENSE VR_HOT 2.2 220nF 4.7uF 16V, Y5V, +80%/-20%

ROSC

AGND
IMON
* PC34
* PQ1 16V, Y5V, +80%/-20%

2
ILIM

1
10nF 14 38 PR44 PU1
C 25V, X7R, +/-10% VSN NTC 1K Dummy PR4 2.2 VCCP C
4 8 G

BST
VSS_SENSE dummy NCP5392MNR2G VCC DRVH AOD452 PL1
12 VSS_SENSE
12
11

10

41

*
PR3 10K 300nH@100KHz C198 C197 C193

DS
P_PHASE3
7 2 1
* 10uF
* 10uF
* 10uF

D
SW

*
PR45
* PC36
*
PC35 2 +/-10% +/-10%
Dummy +/-10%
Dummy

GND
*
100 Ohm 0.1uF 0.1uF PR8 2.2 PWM PQ3 PQ5 PR1
3 EN DRVL 5
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
dummy dummy *PR48
20K NCP5359DR2G P_DRVL3 G G
2.2

6
1

1
+/-1%
* PC8
1uF AOD472 AOD472 CP20 CP22

S
* PC3 COPPER COPPER

2
*PR49 1nF

2
18K 50V, X7R, +/-10% C187 C164 C165
+/-1%
P_ISEN3- * 10uF
+/-10%
Dummy * 10uF
+/-10% * 10uF
+/-10%
P_ISEN3+

VTT_OUT_RIGHT

VTT_OUT_RIGHT 5V_SB
*R233
1K
Input LC circuit +/-5%
12V_VRM VIN
PWR2
L13
1.2uH@100KHz *R232
4.12K *R228
20K
CP13 VTT_PWRGD 12
*
C170
10uF
*
C171
10uF
*
C166
10uF
*

+/-1% +/-1% Q19 VRM_EN +/-10%

Dummy +/-10%
Dummy +/-10%
2

PC5 PEC4 PEC3 PEC2 PEC1 2N7002

*

* *
* 100nF * 1000uF * 1000uF * 1000uF * 1000uF R241 100KOhm C258

C
+80%~-20% +/-20% +/-20% +/-20% +/-20% +/-1% X_COPPER
2.2uF
dummy C272 Dummy B Q20 6.3V, Y5V, +80%/-20%
MMBT3904-7-F
1

E
Header_2X2 2.2uF C182 C172 C188
6.3V, Y5V, +80%/-20%
* 10uF
+/-10%
Dummy * 10uF
+/-10% * 10uF
+/-10%

P_CS1 P_ISEN1+ P_CS2 P_ISEN2+ P_CS3 P_ISEN3+ C186 C184 C183

B B
* 10uF
+/-10%
Dummy * 10uF
+/-10% * 10uF
+/-10%
Dummy
* PC25
10pF *
PC26
10pF *
PC23
10pF
PC24
10pF * PC21
10pF * PC22
10pF *
50V, NPO, +/-5% 50V, NPO, +/-5% 50V, NPO, +/-5% 50V, NPO, +/-5% 50V, NPO, +/-5% 50V, NPO, +/-5%

Dummy Dummy Dummy Dummy Dummy Dummy

PR50 49.9K VFB

+/-1%
Near NCP5392
1

5V_SYS
* PC37
150pF FSB_VTT
50V, NPO, +/-5%
2

PR52
9.1K *PR54
C

+/-1% 5V_SYS PQ10 680

B Q10 5V_SYS
MMBT3904-7-F IO 1 P_PSI_N
P_PSI_N 12
5 VCC
* * C230
E

PR53 PC38
COMP
1K 0.1uF
*PR56 *PR57 * PC39
*

16V, Y5V, +80%/-20% 0.1uF

dummy 1K 1K 16V, Y5V, +80%/-20%
PR51 33nF OI 2 PSI#
33K +/-10% 4 C
C

GND 3
PR59 5.1KOhm
+/-1% B Q17 Q15 B
12,14 HCPURSTJ MMBT3904-7-F
MMBT3904-7-F 74V1G66CTR
C267 5V_SYS
E

* 10uF
+/-10%
*

PR55 1K
C

B Q14 Q16 B PR58 1K HCPURSTJ

MMBT3904-7-F
MMBT3904-7-F
E

A A

FOXCONN PCEG
Title
VRD11.1-NCP5392
Size Document Number Rev
Custom G41M01 D

Date: Thursday, September 18, 2008 Sheet 9 of 38

5 4 3 2 1
 5 4 3 2 1

12V_SYS
C289
D23
A C 1125V_PHASE * L25

*
*
12V_SYS R244 10 LS4148-F 1uH@1KHz
+/-5% 1uF
16V, X7R, +/-10%

close to Q61 Drain

C286 1uF 16V, X7R, +/-10%

*
R248 C254 EC37 C262

1
14.3K
* 0.1uF * 330uF
* 4.7uF

D
5
D D
+/-1% U12 25V, X7R, +/-10% 16V, +/-20% 25V, Y5V, +80%/-20%
1 Q11

VCC

2
Rocset BOOT R164
2.2
7 COMP/OCSET UGATE 2
+/-5% *R165
10K
G
AOD452
L23 Need to change to RUBYCON
1D1V_MCH
+/-5%

*
S
6 8 1125V_PHASE 16MBZ470MEFC8X11.5 1D1V_MCH
FB PHASE

GND
LGATE 4
R163 2.5uH@100KHz

D
R245 APW7120KE-TRL 2.2

1
1.02KOhm
+/-1%
Q13 +/-5%
*
C213
0.1uF *
EC34
1000uF *
EC33
1000uF * C214
10uF EC35

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

*

10V, Y5V, +80%/-20%

2.2uF C207

2.2uF C195

2.2uF C205

1uF C210

1uF C203

1uF C199
G C219 +/-20% +/-20% 1000uF

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

2
1

1
AOD472
* 2.2nF
50V, X7R, +/-10%
+/-20%
* * * * * *

S
Near MOSFET

2
VOUT= 0.8V(1+R638 / R658)
R638,R658 must
R246 less than 1k
Pull FB trace out after Cout

R247 383Ohm C294

*
+/-1%

*
220 18nF
+/-1% 50V, X7R, +/-10%

Dummy Dummy
1D125V FOR CHIP
C C

12V_SYS
2D5V_REF
1D8V_STR
3D3V_SB 2D5V_REF
50 mils
1

* R317
* C399

*R349
33 Ohm
910 Ohm
+/-1%
0.1uF
2

+/-1% 25V, X7R, +/-10%

D

U17A 1D5V_CORE
4

Q22
@1.5V 1D5V_REF 3 +
2

Q31
C428 1 2
1 G
P3055LDG 1A
-
1

1uF
* *R340 TL431NSL 50 mils
S

10V, Y5V, +80%/-20% 100 Ohm Dummy LM324DR2G R278

11

Dummy +/-1% R316 C402 1K

*
2

+/-1% *
1.5KOhm 0.1uF
16V, Y5V, +80%/-20%
+/-1%
Can change to 0402 or not EC43 C375
Dummy
* 1000uF
+/-20% * 0.1uF
16V, Y5V, +80%/-20%

2D5V_REF
1D8V_STR
B B
12V_SYS 50 mils
*R315
1K
+/-1%

D
U17B 1D05V_SYS
1D5V_SYS

4
Q21
@1.05V 1.8V 5 +
6
7 G
P3055LDG 1A
-
50 mils

S
LM324DR2G R250

11
R314 C401 1K
* 750
* 0.1uF +/-1%
+/-1% 16V, Y5V, +80%/-20%
2D5V_REF Can change to 0402 or not EC42 C290
Dummy
1D8V_STR * 1000uF
+/-20% * C306
10uF * 0.1uF
16V, Y5V, +80%/-20%

3D3V_SB 12V_SYS 50 mils

*R357
13K
FSB_VTT 10V, Y5V, +80%/-20%
Dummy Dummy
Need to Check Change to Dummy
+/-1%
R359
*
D

1K U17C
4

+/-5% Q9
1D5V_CORE Reserved VREF1D2 1.8V
@1.2V 10 +
8,11,34 PWRG_ATX 8 G
9 P3055LDG
C

-
*R353 *R352
S

470
Dummy 470 B Q32 LM324DR2G R114
11

+/-5% +/-5% MMBT3904-7-F R344 C419 1K

* 12KOhm
* 1uF +/-1%
6.3A 50 mils
E

+/-1% 10V, Y5V, +80%/-20%

Can change to 0402 or not
Dummy EC27 C140 C139 1D05V_SYS
C

C426B Q33
* 1000uF
+/-20% * 10uF
* 0.1uF
10V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
MMBT3904-7-F R331
* 1uF
*

A 10V, Y5V, +80%/-20% Dummy A

E

1K
+/-5%
TBD

FSB_VTT FSB_VTT

C136 C137 FOXCONN PCEG

* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% Title
1D125V 1D5V FSB
FSB_VTT Size
C
Document Number
G41M01
Rev
A

Date: Thursday, September 25, 2008 Sheet 10 of 38

5 4 3 2 1
 5 4 3 2 1

DDR_VTT
D D
VCC_DUAL
D31 D30
12V_SYS 1 1
3 3 C408 18V_PHASE * L34
1.8V Voltage

*
5V_SB 2 2 1uF
16V, X7R, +/-10% 1uH@1KHz

*
R329 10 1.8V Power requires 1D8V_STR 3D3V_SYS
BAT54C +/-5% BAT54C
17A maximum current
close to Q61 Drain
5V_SB C405

*
1uF
R321 16V, X7R, +/-10% EC50 U19

1
*R369 Open 14.3K
* C440 * 470uF
* C434
* C439 del 1000uf 1 8 VTT_DDR

D
VIN VCNTL

5
4.7K +/-1% U16 0.1uF 6.3V, +/-20% 10uF 10uF 7
+/-5% L Q34 EC48 R365 VCNTL
1 6
*

VCC

2
BOOT VCNTL
L
Open
Rocset R370
2.2
25V, X7R, +/-10% 10V, Y5V, +80%/-20% 10V, Y5V, +80%/-20% * 1000uF 100KOhm
VCNTL 5
H
7 COMP/OCSET UGATE 2
+/-5% *R358
10K
G
AOD452 1D8V_STR
+/-20%
Dummy +/-1%
4
C

L32 VOUT

16V, Y5V, +80%/-20%

Open +/-5%

*
S
L B Q35 6 8 18V_PHASE 3 2
MMBT3904-7-F FB PHASE REFEN GND

GND
L 4 RT9173 C422 EC45 C410
E

LGATE R364 2.5uH@100KHz

1
*R361 C429
* 0.1uF * 1000uF
* 4.7uF
C

D
First H Need to Apply
*R308 APW7120KE-TRL 2.2 100KOhm
* 0.1uF +/-20% Dummy

3
*

R374 1K B Q36 82.5Ohm Q24 +/-5% C381 EC47 EC46 +/-1% 16V, Y5V, +80%/-20%
24 SLP_S4J

2
S5
+/-5%
L
MMBT3904-7-F +/-1%
R313
+/-5%
0 G C438 * 0.1uF * 1000uF
+/-20%
16V, Y5V, +80%/-20%
* 1000uF
+/-20%
E

1
S0 H Don't in CIS
AOD472
* 2.2nF
50V, X7R, +/-10%

S
Near MOSFET Need to Check Change to Dummy

2
S3 H

VOUT= 0.8V(1+R638 / R658)

R638,R658 must less than 1k
Pull FB trace out after Cout
*
R305 115 Ohm
C +/-1% C
*

R309 220 +/-1%

Dummy C398Dummy
18nF
*
50V, X7R, +/-10%

*R307
442 Ohm
R306
1.02KOhm
+/-1% +/-1%

@mem ov
24 1D8V_GPIO10
@mem ov
24 1D8V_GPIO14

1D8V_STR

5V_SB

PWOK+
27 PWOK+
5V_SB 12V_SYS 5V_SYS
U15
3D3V_SB
B B
Vin 3
EC51
Vout 2 Max. output current = 3A R345 * * 1000uF
1K +/-20%
1 +/-5% 5V_SB

S
ADJ
PWOK+
*R328 * G Q37

A
AZ1084D-ADJTRE1 301 R351 LS4148-F
+/-1% 1K D33
Dummy
Q28 P3055LDG VCC_DUAL
+/-5%
3D3VADJ 2N7002

D
EC49 C400 EC24 PWOKJ

C
* 1000uF
+/-20% * 1uF
10V, Y5V, +80%/-20%
* 1000uF 915 series failure issue

*R330
499
+/-20%
5V_SB
+/-1%
Q27
2N7002 5V_SB
L
8,10,34 PWRG_ATX

1
H
R350 * * C427
10uF

S
1K

2
+/-5% G Q30 10V, Y5V, +80%/-20%

FDN340P
Vout=Vref(1+R2/R1)+IadjR2

D
Q29
R1 is Up Resistor. 2N7002

Iadj=50uA
Vref=1.25V

A A

3D3V_DUAL 5V_DUAL

FOXCONN PCEG
Title
STR 1D8V 3D3V_DUAL 5V_DUAL
Size Document Number Rev
C G41M01 A

Date: Thursday, September 18, 2008 Sheet 11 of 38

5 4 3 2 1
 5 4 3 2 1

HAJ[35..3]
14 HAJ[35..3]

HDJ[63..0]
HDJ[63..0] 14 U11A
HAJ3 L5 D2 3 OF 7
HAJ4 A03# ADS# HADSJ 14 U11C
P6 A04# BNR# C2 HBNRJ 14
2 OF 7 HAJ5 M5 D4 P2 F26 TESTHI_0
U11B A05# HIT# HITJ 14 25 SMIJ SMI# TESTHI00
HAJ6 L4 H4 TP_RSPJ K3 W3 TESTHI_1
A06# RSP# TP15 25 A20MJ A20M# TESTHI01
HAJ7 M4 G8 R3 P1 DPSLP#
A07# BPRI# HBPRIJ 14 25 FERRJ FERR#/PBE# TESTHI11
HDJ0 B4 G16 HDJ32 HAJ8 R4 B2 K1 W2 TESTHI_12
D00# D32# A08# DBSY# HDBSYJ 14 25 INTR LINT0 TESTHI12
HDJ1 C5 E15 HDJ33 HAJ9 T5 C1 L1 F25
D01# D33# A09# DRDY# HDRDYJ 14 25 NMI LINT1 TESTHI02 FSB_VTT
HDJ2 A4 E16 HDJ34 HAJ10 U6 E4 N2 G25
D02# D34# A10# HITM# HITMJ 14 25 IGNNEJ IGNNE# TESTHI03
HDJ3 C6 G18 HDJ35 HAJ11 T4 AB2 HIERRJ M3 G27
D03# D35# A11# IERR# 25 STPCLKJ STPCLK# TESTHI04
HDJ4 A5 G17 HDJ36 HAJ12 U5 P3 G26
HDJ5 D04# D36# HDJ37 HAJ13 A12# INIT# INITJ 25 TESTHI05 R197
D
B6 D05# D37# F17 U4 A13# LOCK# C3 HLOCKJ 14 13 HVCCA A23 VCCA TESTHI06 G24 * D
HDJ6 B7 F18 HDJ38 HAJ14 V5 E3 B23 F24 TESTHI_2_7 51 Ohm
D06# D38# A14# TRDY# HTRDYJ 14 13 HVSSA VSSA TESTHI07
HDJ7 A7 E18 HDJ39 HAJ15 V4 AD3 TP_BINITJ VCC_PLL D23 AK6 FORCEPHJ +/-5%
D07# D39# A15# BINIT# TP14 RSVD5 FORCEPH
HDJ8 A10 E19 HDJ40 HAJ16 W5 G7 C23 G6
D08# D40# A16# DEFER# HDEFERJ 14 13 HVCCIOPLL VCCIOPLL RSVD11
HDJ9 A11 F20 HDJ41 N4 F2 HGTLREF_1_2
HDJ10 D09# D41# HDJ42 RSVD1 EDRDY# TP_MCERRJ R356 0
B10 D10# D42# E21 14 HREQJ[4..0] P5 RSVD2 MCERR# AB3 TP22 TESTHI13 L2 CPU_SLPJ 25,34
HDJ11 C11 F21 HDJ43 HREQJ0 K4 VID0 AM2 AH2 Dummy
D11# D43# REQ0# 9 VID0 VID0 RSVD12
HDJ12 D8 G21 HDJ44 HREQJ1 J5 U2 TP_APJ0 VID1 AL5 N1
D12# D44# REQ1# AP0# TP35 9 VID1 VID1 PWRGOOD CPU_PWRG 24
HDJ13 B12 E22 HDJ45 HREQJ2 M6 U3 TP_APJ1 VID2 AM3 AL2 PROCHOTJ
D13# D45# REQ2# AP1# TP32 9 VID2 VID2 PROCHOT#
HDJ14 C12 D22 HDJ46 HREQJ3 K6 VID3 AL6 M2
D14# D46# REQ3# 9 VID3 VID3 THERMTRIP# THERMTRIPJ 25
HDJ15 D11 G22 HDJ47 HREQJ4 J6 F3 HBR0J VID4 AK4
D15# D47# HAJ[35..3] REQ4# BR0# HBR0J 14 9 VID4 VID4
HDBIJ0 A8 D19 HDBIJ2 R6 G3 TESTHI_8 VID5 AL4
14 HDBIJ0 DBI0# DBI2# HDBIJ2 14 14 HAJ[35..3] 14 HADSTBJ0 ADSTB0# TESTHI08 9 VID5 VID5
C8 G20 G5 G4 TESTHI_9 VID6 AM5 A13 HCOMP0 FSB_VTT
14 HDSTBNJ0 DSTBN0# DSTBN2# HDSTBNJ2 14 34 PECI PCREQ# TESTHI09 9 VID6 FC11 COMP0
B9 G19 H5 TESTHI_10 VID7 AM7 T1 HCOMP1
14 HDSTBPJ0 DSTBP0# DSTBP2# HDSTBPJ2 14 TESTHI10 9 VID7 FC12 COMP1
HAJ17 AB6 VID_SELECT AN7 G2 HCOMP2
HDJ16 G9 D16# D48# D20 HDJ48 HAJ18 W6
A17#
A18# DP0# J16 TP_DPJ0
TP7 7 CK_200M_P_CPU F28
FC16
BCLK0
COMP2
COMP3 R1 HCOMP3 * R178
HDJ17 F8 D17 HDJ49 HAJ19 Y6 H15 TP_DPJ1 G28 J2 HCOMP4 49.9
D17# D49# A19# DP1# TP6 7 CK_200M_N_CPU BCLK1 COMP4
HDJ18 F9 A14 HDJ50 HAJ20 Y4 H16 TP_DPJ2 T2 DPRSTP# +/-1%
D18# D50# 4 mils width, 10 mils spacing A20# DP2# TP5 COMP5
HDJ19 E9 C15 HDJ51 HAJ21 AA4 J17 TP_DPJ3 AE8
D19# D51# A21# DP3# TP4 TP30 SKTOCC#
HDJ20 D7 C14 HDJ52 HAJ22 AD6 N5
HDJ21 D20# D52# HDJ53 HAJ23 A22# HGTLREF_1_2 RSVD13
E10 D21# D53# B15 AA5 A23# GTLREF1 H2 RSVD14 AE6
HDJ22 D10 C18 HDJ54 HAJ24 AB5 H1 HGTLREF_0_3 AL1 C9 H_TEST
D22# D54# A24# GTLREF0 34 THERMDA THERMDA RSVD15
HDJ23 F11 B16 HDJ55 HAJ25 AC5 E24 AK1 G10 HGTLREF_0_3
D23# D55# A25# CS_GTLREF TP3 34 THERMDC THERMDC RSVD16
HDJ24 F12 A17 HDJ56 HAJ26 AB4 D16
HDJ25 D24# D56# HDJ57 HAJ27 A26# RSVD17
D13 D25# D57# B18 AF5 A27# AN3 VCCSENSE RSVD18 A20
HDJ26 E13 C21 HDJ58 HAJ28 AF4 G23 AN4 E23
HDJ27 D26# D58# HDJ59 HAJ29 A28# RESET# HCPURSTJ 9,14 VSSSENSE RSVD19
G13 D27# D59# B21 AG6 A29# 9 VCC_SENSE AN5 VCC_MB_REG RSVD21 F23
HDJ28 F14 B19 HDJ60 HAJ30 AG4 B3 AN6 J3
D28# D60# A30# RS0# HRSJ0 14 9 VSS_SENSE VSS_MB_REG RSVD24
HDJ29 G14 A19 HDJ61 HAJ31 AG5 F5
HDJ30 D29# D61# HDJ62 HAJ32 A31# RS1# HRSJ1 14 Changed pin name MS_ID1
F15 D30# D62# A22 AH4 A32# RS2# A3 HRSJ2 14 MSID1 V1
HDJ31 G15 D31# D63# B22 HDJ63 HAJ33 AH5 A33# F29 from RSV
RSVD9 MSID0 W1 MS_ID0
HDBIJ1 G11 C20 HDBIJ3 HAJ34 AJ5
14 HDBIJ1 DBI1# DBI3# HDBIJ3 14 A34#
G12 A16 HAJ35 AJ6
14 HDSTBNJ1 DSTBN1# DSTBN3# HDSTBNJ3 14 A35# THERMDA/THERMDC
E12 C17 AC4 Y1 CPU_BOOT
14 HDSTBPJ1 DSTBP1# DSTBP3# HDSTBPJ3 14 RSVD3 1. width=10 mils, spacing=10 mils. BOOTSELECT
AE4 V2 TP_CPU_V2
RSVD4 2. route the lines in parallel LL_ID0 TP27
AD5 AA2 TP_CPU_AA2 R184
14 HADSTBJ1 ADSTB1# LL_ID1 TP17 *
Socket-IntelPrescottCPU 51 Ohm
Socket-IntelPrescottCPU +/-5%
C 1 OF 7 C
Socket-IntelPrescottCPU

* *
R193 62 HTCK
VTT_OUT_RIGHT +/-5%

R188 62 HTRSTJ

*
R187 62 HTDO +/-5%
VTT_OUT_LEFT VTT_OUT_RIGHT +/-5% Dummy
VTT_OUT_RIGHT
In Design Guide is NC
Place at CPU end of route RN29 VID2
*

R172 62 +/-5% HBR0J 7 8 680 VID4 U11D 4 OF 7 FSB_VTT

5 6 +/-5% VID5 HTCK
3 4 AE1 TCK VTT1 A29
Place at CPU end of route * VID0 HTDI AD1 B25
1 2 RN24 HBPM2J HTDO TDI VTT2
7 8 AF1 TDO VTT3 B29
51 HBPM3J HTMS AC1 B30
RN27 VID3 5 6 +/-5% HTDI HTRSTJ TMS VTT4
7 8 3 4 AG1 TRST# VTT5 C29
RN28 TESTHI_9 680 VID6 * HTMS A26
51 7 8 TESTHI_8 5 6 +/-5% VID7 1 2 VTT6
5 6 3 4 VTT7 B27
+/-5% TESTHI_10 * VID1 HBPM0J AJ2 C28
* 3 4 H_TEST 1 2 RN25 HBPM1J HBPM1J BPM0# VTT8
1 2 7 8 AJ1 BPM1# VTT9 A25
51 HBPM0J HBPM2J AD2 A28
FSB_VTT 5 6 +/-5% HBPM5J HBPM3J BPM2# VTT10
3 4 AG2 BPM3# VTT11 A27
* HBPM4J HBPM4J AF2 C30
1 2 1D5V_CORE HBPM5J BPM4# VTT12
AG3 BPM5# VTT13 A30
RN23 TESTHI_12 Place BPM termination near CPU C25
* **

51 7 8 R198 51 Ohm +/-5% DPSLP# ICH_SYS_RSTJ AC2

VTT14
C26
7,8,24 ICH_SYS_RSTJ
+/-5% 5 6 TESTHI_1 DBR# VTT15
C27 VRMPWRGD 7,9,24
3 4 R103 51 Ohm +/-5% TESTHI_0 CP8 VTT16
*1 2
VTT_OUT_LEFT
X_COPPER
AK3
AJ3
ITPCLKOUT0
ITPCLKOUT1
VTT17
VTT18
B26
D27 *R200
0
D28 +/-5%
*

R176 49.9 +/-1% HCOMP4 R104 51 Ohm +/-5% TESTHI_2_7 FSBSEL0 VTT19 Dummy
B 7,14 FSBSEL0 G29 BSEL0 VTT20 D25 B
Dummy 10 mils width VCC_PLL FSBSEL1 H30 D26
7 mils spacing to low speed signals 7 FSBSEL1 FSBSEL2 BSEL1 VTT21
7,14 FSBSEL2 G30 BSEL2 VTT22 B28
14mils spacing to high speed signals VTT_OUT_RIGHT R175 C141 C138 D29 VTT_PWRGD 9
VTT23

1
max. 1200mils
* 51 Ohm
+/-5%
10uF
* * 10nF
25V, X7R, +/-10% VTT24 D30
AM6 VTT_OUT_RIGHT VTT_OUT_LEFT
**

R174 49.9 +/-1% HCOMP2 10V, Y5V, +80%/-20% Reserved VTTPWRGD

2
R214 130 +/-1% FORCEPHJ AA1 VTT_OUT_RIGHT
R141 49.9 +/-1% HCOMP0 TP_CPU_G1 VTT_OUT1 VTT_OUT_LEFT
TP_CPU_G1 13 VTT_OUT2 J1
R210 130 +/-1% PROCHOTJ F27
reserve for Kentsfield CPU support placed near pin D23, within 500 mils VTT_SEL
10 mils width
Socket-IntelPrescottCPU
7 mils spacing to low speed signals
14mils spacing to high speed signals VTT_OUT_RIGHT
max. 1200mils
* **

R185 62 +/-5% HIERRJ PROCHOTJ R209 0 +/-5%

**

R177 49.9 +/-1% HCOMP3 Dummy ICH_THRM_UP 24,34 VTT_OUT_RIGHT VTT_OUT_LEFT

R179 49.9 +/-1% HCOMP1 R225 62 +/-5% HCPURSTJ
Place at CPU end of route Stuff to enable Thermal event C270 C251
R201
680 Ohm VID_SELECT * 0.1uF
* 0.1uF

+/-1% 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%

*

VID_SELECT R159 0 +/-5% Dummy Dummy

Dummy P_PSI_N 9

VTT_OUT_RIGHT
MSID0: NC = 2005 Mainstream / Value, 2006 65W FMB meet the 0.63Vtt value before
Vss = 2005 Performance FMB
Double check??? MSID1: Vss = 2005 Performance,2005 Mainstream/Value,2006 65W FMB BIOS GPIO setting. This is a Intel spec. VTT_OUT_RIGHT

VTT_OUT_RIGHT
GPIO26: Default low
* R230
Dummy GPIO13: Default input R218 O.667*VTT
*R229
1K
100 Ohm

*R213
49.9
+/-1%
*

A MS_ID0 R192 0 dummy dummy R231 0

Dummy 57.6 Ohm A
+/-5% VTT_PWRGD 9 +/-1%
C

R224
*

*
Q18
B Dummy
MMBT3904-7-F * C275
0.1uF
O.635*VTT R202 10
+/-1%
HGTLREF_1_2
*

MS_ID1 R182 0 dummy 16V, Y5V, +80%/-20% R203 10 HGTLREF_0_3 C241

E

0
dummy +/-1%
*R226 *R234 C247
* *R211 * 220pF
10V, Y5V, +80%/-20%

576 Ohm 1.3K +/-5% 1uF 100 Ohm 50V, NPO, +/-5%
*R208 *
Dummy
* R212 C242 +/-1% +/-1%
10V, Y5V, +80%/-20% +/-1%
51 Ohm R181
Dummy
51 BOM
Ohm Note:
C261
1uF * 100 Ohm
+/-1% * 220pF
50V, NPO, +/-5% 24 GTL_GPIO13 FOXCONN PCEG
1.Stuff R108 for 95W YORKFIELD support 24 GTL_GPIO26
Title
2.Stuff R109 for 65W CONROE/WOLFDALE support GTLREF voltage should be 0.63*VTT
3.Empty Q6 for VTT tool test 12 mils width, 15 mils spacing LGA775-1
divider should be within 1.5" of the GTLREF pin Size Document Number Rev
4.Reserve R110 and R111 for CPU support before CONROE 0.22nF caps should be placed near CPU pin
place series resistor as close to divider
C G41M01 A

Date: Thursday, September 18, 2008 Sheet 12 of 38

5 4 3 2 1
 5 4 3 2 1

VCCP VCCP VCCP

U11G 7 OF 7
U11E 5 OF 7 U11F 6 OF 7 FSB_VTT
AG22 VCCP1 VCCP93 AK12 AF9 VCCP185 VSS41 AL23 H22 VSS126 VSS211 D5
K29 VCCP2 VCCP94 AH22 AF22 VCCP186 VSS42 A12 H21 VSS127 VSS212 A9
AM26 VCCP3 VCCP95 T29 AH11 VCCP187 VSS43 L25 H20 VSS128 VSS213 D3 PLL Supply Filter
AL8 VCCP4 VCCP96 AM14 AJ14 VCCP188 VSS44 J7 H19 VSS129 VSS214 B1
AE12 AM25 AH19 R105
VCCP5 VCCP97 VCCP189 VSS45 AE28 H18 VSS130 VSS215 B5
0
AE11 VCCP6 VCCP98 AE9 AH29 VCCP190 VSS46 AE29 AB7 VSS131 VSS216 B8 Dummy
W23 Y29 AH27 +/-5%
VCCP7 VCCP99 VCCP191 VSS47 K5 H17 VSS132 VSS217 AJ4
W24 VCCP8 VCCP100 AK25 AG28 VCCP192 VSS48 J4 AJ24 VSS133 VSS218 AE26
D W25 VCCP9 VCCP101 AK19 AL26 VCCP193 VSS49 AE30 AM17 VSS134 VSS219 AH1 D
T25 AG15 AM12 TP_CPU_E29
VCCP10 VCCP102 VCCP194 VSS50 AN20 AC3 VSS135 VSS220 E29 TP2
Y28 VCCP11 VCCP103 J22 J24 VCCP195 VSS51 AF10 H14 VSS136 VSS221 V7
AL18 VCCP12 VCCP104 T24 J13 VCCP196 VSS52 AE24 P28 VSS137 VSS222 C13
AC25 VCCP13 VCCP105 AG21 T28 VCCP197 VSS53 AM24 V6 VSS138 VSS223 AK24
W30 AM21 W28 HVCCIOPLL
VCCP14 VCCP106 VCCP198 VSS54 AN23 AK2 VSS139 VSS224 AB30 12 HVCCIOPLL
Y30 VCCP15 VCCP107 J25 J12 VCCP199 VSS55 H9 P27 VSS140 VSS225 L6
AN14 VCCP16 VCCP108 U30 J27 VCCP200 VSS56 H8 P26 VSS141 VSS226 L7
AD28 AL21 AG19 HVCCA
VCCP17 VCCP109 VCCP201 VSS57 H13 AM28 VSS142 VSS227 AB29 12 HVCCA
Y26 VCCP18 VCCP110 AG25 AL9 VCCP202 VSS58 AC6 AJ13 VSS143 VSS228 M1
AC29 VCCP19 VCCP111 AJ18 AD30 VCCP203 VSS59 AC7 W4 VSS144 VSS229 AB28
M29 J19 AF21 EC26
VCCP20 VCCP112 VCCP204 VSS60 AH6 P25 VSS145 VSS230 E8
U24
J23
VCCP21 VCCP113 AH30
J15
Y24
AK14
VCCP205 VSS61 C16 AJ20 VSS146 VSS231 AG20 * 100uF
+/-20%
Dummy
VCCP22 VCCP114 VCCP206 VSS62 AM16 W7 VSS147 VSS232 AN17
AC27 VCCP23 VCCP115 AG12 J9 VCCP207 VSS63 AE25 P23 VSS148 VSS233 AB27
AM18 VCCP24 VCCP116 AJ22 M27 VCCP208 VSS64 AE27 AG13 VSS149 VSS234 AB26
AM19 VCCP25 VCCP117 J20 AF14 VCCP209 VSS65 AJ28 AG16 VSS150 VSS235 AN16
AB8 VCCP26 VCCP118 AH18 J30 VCCP210 VSS66 AJ7 AG17 VSS151 VSS236 M7
AC26 AH26 AG18 HVSSA
VCCP27 VCCP119 VCCP211 VSS67 F19 C7 VSS152 VSS237 AB25 12 HVSSA
J8 VCCP28 VCCP120 W27 AA8 VCCP212 VSS68 AH13 Y2 VSS153 VSS238 AB24
J28 AL25 AG8 Notes:
VCCP29 VCCP121 VCCP213 VSS69 AD7 L30 VSS154 VSS239 AB23
1. Cap. should be within 1.5" mils of the VCCA and VSSA pins
T30 VCCP30 VCCP122 AN8 AL29 VCCP214 VSS70 AH16 L29 VSS155 VSS240 N3
AM9 AH14 AD29 2. VCCA route should be parallel and next to VSSA route to
VCCP31 VCCP123 VCCP215 VSS71 AK17 D15 VSS156 VSS241 AA30
minimize loop area
AF15 VCCP32 VCCP124 U27 W8 VCCP216 VSS72 E17 AL27 VSS157 VSS242 F4
3. VCCIOPLL route should be parallel and next to VSSA route
AC8 VCCP33 VCCP125 T23 AH8 VCCP217 VSS73 AH17 Y7 VSS158 VSS243 AG10
to minimize loop area
AE14 VCCP34 VCCP126 R8 N24 VCCP218 VSS74 AH20 L27 VSS159 VSS244 AE13
3. Min. 12 mils trace from the filter to the processor pins
N23 VCCP35 VCCP127 AK22 AN22 VCCP219 VSS75 AE5 AA29 VSS160 VSS245 AF30 4. The inductors should be close to the cap.
C W29 VCCP36 VCCP128 AN29 J14 VCCP220 VSS76 AH23 N6 VSS161 VSS246 H28 C
U29 VCCP37 VCCP129 AG11 K26 VCCP221 VSS77 AE7 N7 VSS162 VSS247 F7
AC24 VCCP38 VCCP130 AK26 AF19 VCCP222 VSS78 AM13 AA28 VSS163 VSS248 AF29
AC23 VCCP39 VCCP131 J10 N8 VCCP223 VSS79 AH24 AN13 VSS164 VSS249 AF28
Y23 VCCP40 VCCP132 AJ15 AF12 VCCP224 VSS80 AJ30 AA27 VSS165 VSS250 G1 TP_CPU_G1 12
AN26 VCCP41 VCCP133 AG26 M28 VCCP225 VSS81 AJ10 AA26 VSS166 VSS251 AF27
AN25 VCCP42 VCCP134 AN9 AK9 VCCP226 VSS82 AF3 P4 VSS167 VSS252 AF26
AN11 VCCP43 VCCP135 AH15 VSS83 AK5 AA25 VSS168 VSS253 AF25
AN18 VCCP44 VCCP136 AF18 VSS84 AJ16 AA24 VSS169 VSS254 AN28
Y27 VCCP45 VCCP137 AL15 C10 VSS1 VSS85 AF6 P7 VSS170 VSS255 AN27
Y25 J26 D12 FSB_VTT
VCCP46 VCCP138 VSS2 VSS86 AK29 E26 VSS171 VSS256 AF24
AD24 VCCP47 VCCP139 J18 VSS87 AJ17 V30 VSS172 VSS257 AF23
AE23 J21 C24 VSS88 F22 R2 AG24

*
VCCP48 VCCP140 VSS4 VSS173 VSS258 R183 49.9 +/-1% PSI#
AE22 VCCP49 VCCP141 AG27 K2 VSS5 VSS89 AH3 V29 VSS174 VSS259 AF17
AN19 VCCP50 VCCP142 AK15 C22 VSS6 VSS90 AK10 V28 VSS175 VSS260 AN24
V8 VCCP51 VCCP143 AF11 AN1 VSS7 VSS91 AM10 R5 VSS176 VSS261 H3
K8 VCCP52 VCCP144 AD23 B14 VSS8 VSS92 F16 V27 VSS177
AE21 AM15 K7 VTT_OUT_RIGHT
VCCP53 VCCP145 VSS9 VSS93 AJ23 R7 VSS178 VSS263 P24
AM30 AF8 AE16 VSS94 F13 E20 AE20

*
VCCP54 VCCP146 VSS10 VTT_OUT_LEFT VSS179 VSS264 R186 49.9 +/-1% HCOMP7
AE19 VCCP55 VCCP147 AK21 B11 VSS11 VSS95 AG7 AN10 VSS180 VSS265 AE17
AC30 VCCP56 VCCP148 AG30 AL10 VSS12 VSS96 F10 V25 VSS181 VSS266 E27 Dummy
AE15 VCCP57 VCCP149 AJ21 AK23 VSS13 VSS97 L26 T3 VSS182 VSS267 T7
10 mils width
M30
K27
VCCP58
VCCP59
VCCP150
VCCP151
AM11
AL11
H12
AF7
VSS14
VSS15
VSS98 AD4
VSS99 H11
*R180
51 Ohm
V24
V23
VSS183
VSS184
VSS268
VSS269
R30
AJ27 7 mils spacing to low speed signals
14mils spacing to high speed signals
M24 AJ11 AK7 +/-5%
VCCP60 VCCP152 VSS16 VSS100 L24 T6 VSS185 VSS270 AB1
max. 1200mils
AN21 VCCP61 VCCP153 K30 H7 VSS17 VSS101 L23 AL7 VSS186 VSS271 AM4
T8 VCCP62 VCCP154 AL14 E14 VSS18 VSS102 AM23 E25 VSS187 VSS272 V26
B AC28 VCCP63 VCCP155 AN30 L28 VSS19 VSS103 A15 U1 VSS188 VSS273 AA23 B
N25 VCCP64 VCCP156 AH25 Y5 VSS20 VSS104 AH10 R29 VSS189 VSS274 AL28
AE18 AL12 E11 R139
VSS105 H29 TP1 R28 AF20

*
VCCP65 VCCP157 VSS21 VSS190 VSS275 24.9 HCOMP8
W26 VCCP66 VCCP158 AJ9 AL16 VSS22 VSS106 B24 R27 VSS191 VSS276 AG23
AD25 AK11 AL24 +/-1%
VCCP67 VCCP159 VSS23 VSS107 L3 R26 VSS192
M8 VCCP68 VCCP160 AG14 AK13 VSS24 VSS108 H27 R25 VSS193
N30 VCCP69 VCCP161 N29 TP21 AL3 VSS25 VSS109 A21 U7 VSS194
AD26 VCCP70 VCCP162 AL30 D21 VSS26 VSS110 AE2 R24 VSS195
AJ26 AJ25 AL20 15 mils width
VSS111 AJ29 R23
*

VCCP71 VCCP163 VSS27 VSS196 7 mils spacing to low speed signals

AM29 VCCP72 VCCP164 AH9 D18 VSS28 VSS112 A24 P30 VSS197
M25 J29 AN2 14mils spacing to high speed signals
VCCP73 VCCP165 VRDSEL VSS29 VSS113 AK27 R115
V3 VSS198 max. 1200mils
M26 VCCP74 VCCP166 J11 AK16 VSS30 VSS114 AK28 P29 VSS199
L8 K25 AK20 1K IMPSEL
VCCP75 VCCP167 VSS31 VSS115 B20 +/-5%
AF16 VSS200 RSVD26 F6
U25 VCCP76 VCCP168 P8 AM27 VSS32 VSS116 AM20 AE10 VSS201
Y8 K23 AM1 PSI#
VCCP77 VCCP169 VSS33 VSS117 H26 Dummy
AF13 VSS202 RSVD28 Y3
HCOMP7 PSI# 9
AJ12 VCCP78 VCCP170 AL19 AL13 VSS34 VSS118 B17 H6 VSS203 RSVD29 AE3
AD27 AM8 AL17 VSS119 H25 A18

*
VCCP79 VCCP171 VSS35 VSS204 R173 51 Ohm IMPSEL
U23 VCCP80 VCCP172 T26 C19 VSS36 VSS120 H24 A2 VSS205 RSVD31 E7
M23 N28 E28 HCOMP8 +/-5%
VCCP81 VCCP173 VSS37 VSS121 AA3 E2 VSS206 RSVD32 B13
AG29 VCCP82 VCCP174 AH12 AH7 VSS38 VSS122 AA7 D9 VSS207 RSVD33 D14
N27 VCCP83 VCCP175 AL22 AK30 VSS39 VSS123 H23 C4 VSS208 RSVD34 E6
AM22 VCCP84 VCCP176 AN15 D24 VSS40 VSS124 AA6 A6 VSS209 RSVD35 D1
U28 VCCP85 VCCP177 AJ8 VSS125 H10 D6 VSS210 RSVD36 E5
K28 VCCP86 VCCP178 U26
U8 VCCP87 VCCP179 AJ19 Socket-IntelPrescottCPU Socket-IntelPrescottCPU
AK18 VCCP88 VCCP180 T27
AD8 VCCP89 VCCP181 AK8
A K24 VCCP90 VCCP182 AN12 A
AH28 VCCP91 VCCP183 AG9
AH21 VCCP92 VCCP184 N26

Socket-IntelPrescottCPU FOXCONN PCEG

Title
LGA775-2
Size Document Number Rev
Custom G41M01 A

Date: Tuesday, September 16, 2008 Sheet 13 of 38

5 4 3 2 1
 5 4 3 2 1

Concurrent SDVO and PCI Express: PCI Express* Static Lane Reversal:
0 = Only SDVO or PCI Express is operational. 0 = GMCH PCI Express lane numbers are reversed (BTX)
1 = Both SDVO and PCI Express are operating 1 = Normal operation (ATX)
HDJ[63..0]
12 HAJ[35..3] 2 OF 10 HDJ[63..0] 12
U9B
HAJ3 L36 F44 HDJ0 TLS confidentiality enable:
HAJ4 FSB_AB_3 FSB_DB_0 HDJ1 1 = Enable TLS U9E 5 OF 10
L37 FSB_AB_4 FSB_DB_1 C44
HAJ5 J38 D44 HDJ2 0 = Disable TLS

**
HAJ6 FSB_AB_5 FSB_DB_2 HDJ3 Note: H_FSBSEL0 HSYNC_P R149 39Ohm
F40 FSB_AB_6 FSB_DB_3 C41 F17 BSEL0 CRT_HSYNC D14 HSYNC 23
HAJ7 H39 E43 HDJ4 For platforms that do not support Intel H_FSBSEL1 G16 C14 VSYNC_P R150 39Ohm
+/-1%
FSB_AB_7 FSB_DB_4 AMT,no action is needed. BSEL1 CRT_VSYNC VSYNC 23
HAJ8 L38 B43 HDJ5 H_FSBSEL2 P15 +/-1%
HAJ9 FSB_AB_8 FSB_DB_5 HDJ6 update: Ref spec update 1.01 TP19 TP_ALLZTEST BSEL2
L43 FSB_AB_9 FSB_DB_6 D40 011808 M20 ALLZTEST
HAJ10 N39 B42 HDJ7 TP16 TP_XORTEST N17 B18
FSB_AB_10 FSB_DB_7 XORTEST CRT_RED RED 23
HAJ11 N35 B38 HDJ8 TP_MCH_K16 K16 D18
FSB_AB_11 FSB_DB_8 TP10 RSVD_29 CRT_GREEN GREEN 23
HAJ12 N37 F38 HDJ9 EXP_SLR F15 C18
FSB_AB_12 FSB_DB_9 EXP_SLR CRT_BLUE BLUE 23
HAJ13 J41 A38 HDJ10 U9A 1 OF 10 TP13 TP_MCH_G15 G15 F13
HAJ14 FSB_AB_13 FSB_DB_10 HDJ11 EXP_RXP0 EXP_TXP0 EXP_SM RSVD_7 CRT_IRTN
D
HAJ15
N40
M45
FSB_AB_14
FSB_AB_15
FSB_DB_11
FSB_DB_12
B37
D38 HDJ12 22
22
EXP_RXP0
EXP_RXN0
EXP_RXN0
F6
G7
PEG_RXP_0
PEG_RXN_0
PEG_TXP_0
PEG_TXN_0
C11
B11 EXP_TXN0
EXP_TXP0
EXP_TXN0
22
22
H17
L17
EXP_SM
ITPM_ENABLE
*R157
150 *R156
150 *R154
150 D
HAJ16 R35 C37 HDJ13 EXP_RXP1 H6 A10 EXP_TXP1 L15 +/ -1% +/ -1% +/ -1%

VGA
FSB_AB_16 FSB_DB_13 22 EXP_RXP1 PEG_RXP_1 PEG_TXP_1 EXP_TXP1 22 CRT_DDC_DATA DDCA_DATA 23 Placed close to
HAJ17 T36 D37 HDJ14 EXP_RXN1 G4 B9 EXP_TXN1 M15
FSB_AB_17 FSB_DB_14 22 EXP_RXN1 PEG_RXN_1 PEG_TXN_1 EXP_TXN1 22 CRT_DDC_CLK DDCA_CLK 23 GMCH within
HAJ18 R36 B36 HDJ15 EXP_RXP2 J6 C9 EXP_TXP2 TP_MCH_M17 M17
FSB_AB_18 FSB_DB_15 22 EXP_RXP2 PEG_RXP_2 PEG_TXP_2 EXP_TXP2 22 TP23
Enable TLS RSVD_8 250 mils
HAJ19 R34 E37 HDJ16 EXP_RXN2 J7 D8 EXP_TXN2 TLS J17 B15 DAC_REFSET
FSB_AB_19 FSB_DB_16 22 EXP_RXN2 PEG_RXN_2 PEG_TXN_2 EXP_TXN2 22 CEN DAC_IREF
HAJ20 R37 J35 HDJ17 EXP_RXP3 L6 B8 EXP_TXP3 TP_MCH_G20 G20
FSB_AB_20 FSB_DB_17 22 EXP_RXP3 PEG_RXP_3 PEG_TXP_3 EXP_TXP3 22 BSCANTEST
HAJ21 R39 H35 HDJ18 EXP_RXN3 L7 C7 EXP_TXN3 TP11 TP_MCH_J16 J16 E15 CK_96M_P_GMCH
HAJ22 U38
FSB_AB_21
FSB_AB_22
FSB_DB_18
FSB_DB_19 F37 HDJ19 22
22
EXP_RXN3
EXP_RXP4
EXP_RXP4 N9
PEG_RXN_3
PEG_RXP_4
PEG_TXN_3
PEG_TXP_4 B7 EXP_TXP4
EXP_TXN3
EXP_TXP4
22
22
R119 * TP12 M16
RSVD_10
RSVD_11
DPL_REFCLKINP
DPL_REFCLKINN D15 CK_96M_N_GMCH
CK_96M_P_GMCH 7
CK_96M_N_GMCH 7
HAJ23 T37 G37 HDJ20 EXP_RXN4 N10 B6 EXP_TXN4 1K TP_MCH_J15 J15
EXP_TXN4 22

*
HAJ24 FSB_AB_23 FSB_DB_20 HDJ21 22 EXP_RXN4 EXP_RXP5 PEG_RXN_4 PEG_TXN_4 EXP_TXP5 TP_MCH_J20 RSVD_12 R120 10K
U34 FSB_AB_24 FSB_DB_21 J33 22 EXP_RXP5 N7 PEG_RXP_5 PEG_TXP_5 B3 EXP_TXP5 22 J20 RSVD_13 DPL_REFSSCLKINP G8 1D1V_MCH
HAJ25 U40 L33 HDJ22 EXP_RXN5 N6 B4 EXP_TXN5 TP_MCH_F20 F20 G9 +/-5% DPL_REFSSCLKINP
FSB_AB_25 FSB_DB_22 22 EXP_RXN5 PEG_RXN_5 PEG_TXN_5 EXP_TXN5 22 DUALX8_ENABLE DPL_REFSSCLKINN DPL_REFSSCLKINP 7
HAJ26 T34 G33 HDJ23 EXP_RXP6 R7 D2 EXP_TXP6 DPL_REFSSCLKINN
FSB_AB_26 FSB_DB_23 22 EXP_RXP6 PEG_RXP_6 PEG_TXP_6 EXP_TXP6 22 DPL_REFSSCLKINN 7
HAJ27 Y36 L31 HDJ24 EXP_RXN6 R6 C2 EXP_TXN6 R169
FSB_AB_27 FSB_DB_24 22 EXP_RXN6 PEG_RXN_6 PEG_TXN_6 EXP_TXN6 22 *
HAJ28 U35 M31 HDJ25 EXP_RXP7 R9 H2 EXP_TXP7 0
FSB_AB_28 FSB_DB_25 22 EXP_RXP7 PEG_RXP_7 PEG_TXP_7 EXP_TXP7 22
HAJ29 AA35 M30 HDJ26 EXP_RXN7 R10 G2 EXP_TXN7
FSB_AB_29 FSB_DB_26 22 EXP_RXN7 PEG_RXN_7 PEG_TXN_7 EXP_TXN7 22
HAJ30 U37 J30 HDJ27 EXP_RXP8 U10 J2 EXP_TXP8 AY4 AN6
EXP_TXP8 22 PLTRSTJ 22,24,28,34

FSB
FSB_AB_30 FSB_DB_27 22 EXP_RXP8 PEG_RXP_8 PEG_TXP_8 CL_DATA RSTINB

PCIE
HAJ31 Y37 G31 HDJ28 EXP_RXN8 U9 K2 EXP_TXN8 AY2 AR4 PWRGD_3V
FSB_AB_31 FSB_DB_28 22 EXP_RXN8 PEG_RXN_8 PEG_TXN_8 EXP_TXN8 22 CL_CLK PWROK PWRGD_3V 24,34
HAJ32 Y34 K30 HDJ29 EXP_RXP9 U6 K1 EXP_TXP9 CL_VREF_MCH AN13 K15 ICH_SYNCJ
FSB_AB_32 FSB_DB_29 22 EXP_RXP9 PEG_RXP_9 PEG_TXP_9 EXP_TXP9 22 CL_VREF ICH_SYNCB ICH_SYNCJ 24
HAJ33 Y38 M29 HDJ30 EXP_RXN9 U7 L2 EXP_TXN9 CL_RST AW2
FSB_AB_33 FSB_DB_30 22 EXP_RXN9 PEG_RXN_9 PEG_TXN_9 EXP_TXN9 22 CL_RSTB
HAJ34 AA37 G30 HDJ31 EXP_RXP10 AA9 P2 EXP_TXP10 PWRGD_3V AN8 3D3V_SYS
FSB_AB_34 FSB_DB_31 22 EXP_RXP10 PEG_RXP_10 PEG_TXP_10 EXP_TXP10 22 CL_PWROK stuff for NO HDMI
HAJ35 AA36 J29 HDJ32 EXP_RXN10 AA10 M2 EXP_TXN10 AU4
FSB_AB_35 FSB_DB_32 22 EXP_RXN10 PEG_RXN_10 PEG_TXN_10 EXP_TXN10 22 HDA_BCLK
F29 HDJ33 EXP_RXP11 R4 T2 EXP_TXP11 R166 AV4
*

MISC
FSB_DB_33 22 EXP_RXP11 PEG_RXP_11 PEG_TXP_11 EXP_TXP11 22 HDA_RSTB
H29 HDJ34 EXP_RXN11 P4 R1 EXP_TXN11 10K AU2
12 HREQJ[4..0] FSB_DB_34 22 EXP_RXN11 PEG_RXN_11 PEG_TXN_11 EXP_TXN11 22 HDA_SDI
HREQJ0 G38 L25 HDJ35 EXP_RXP12 AA7 U2 EXP_TXP12 TP_MCH_AR7 AR7 AV1
HREQJ1 K35
FSB_REQB_0
FSB_REQB_1
FSB_DB_35
FSB_DB_36 K26 HDJ36 22
22
EXP_RXP12
EXP_RXN12
EXP_RXN12 AA6
PEG_RXP_12
PEG_RXN_12
PEG_TXP_12
PEG_TXN_12 V2 EXP_TXN12
EXP_TXP12
EXP_TXN12
22
22
TP39
TP38
TP_MCH_AN10 AN10 JTAG_TDI
JTAG_TDO
HDA_SDO
HDA_SYNC AU3 *R137 *R138
HREQJ2 J39 L29 HDJ37 EXP_RXP13 AB10 W4 EXP_TXP13 TP_MCH_AN11 AN11 2.2K 2.2K
FSB_REQB_2 FSB_DB_37 22 EXP_RXP13 PEG_RXP_13 PEG_TXP_13 EXP_TXP13 22 TP36 JTAG_TCK
HREQJ3 C43 J26 HDJ38 EXP_RXN13 AB9 V3 EXP_TXN13 TP_MCH_AN9 AN9 dummy dummy
FSB_REQB_3 FSB_DB_38 22 EXP_RXN13 PEG_RXN_13 PEG_TXN_13 EXP_TXN13 22 TP37 JTAG_TMS
HREQJ4 G39 M26 HDJ39 EXP_RXP14 AB3 AA4 EXP_TXP14 J11 DDPC_CTRLCLK
FSB_REQB_4 FSB_DB_39 22 EXP_RXP14 PEG_RXP_14 PEG_TXP_14 EXP_TXP14 22 DDPC_CTRLCLK
H26 HDJ40 EXP_RXN14 AA2 Y4 EXP_TXN14 F11 DDPC_CTRLDATA
FSB_DB_40 22 EXP_RXN14 PEG_RXN_14 PEG_TXN_14 EXP_TXN14 22 DDPC_CTRLDATA
J40 F25 HDJ41 EXP_RXP15 AD10 AC1 EXP_TXP15
12 HADSTBJ0 FSB_ADSTBB_0 FSB_DB_41 22 EXP_RXP15 PEG_RXP_15 PEG_TXP_15 EXP_TXP15 22 FSB_VTT
T39 F24 HDJ42 EXP_RXN15 AD11 AB2 EXP_TXN15
12 HADSTBJ1 FSB_ADSTBB_1 FSB_DB_42 22 EXP_RXN15 PEG_RXN_15 PEG_TXN_15 EXP_TXN15 22
G25 HDJ43 R31
FSB_DB_43 HDJ44 DMI_RXP0 C497 0.1uF DMI_TXP0 TP_MCH_R32 RSVD_14 49.9
C39 H24 AD7 AC2 DMI_TXP0 TP25
24 R32 P42

*
********
12 HDSTBPJ0 FSB_DSTBPB_0 FSB_DB_44 HDJ45 24 DMI_RXP0 DMI_RXN0 DMI_RXP_0 DMI_TXP_0 C490 0.1uF DMI_TXN0 RSVD_15 SLPB
12 HDSTBNJ0 B39 FSB_DSTBNB_0 FSB_DB_45 L24 24 DMI_RXN0 AD8 DMI_RXN_0 DMI_TXN_0 AD2 DMI_TXN0 24 U30 RSVD_16 DPRSTPB P43
HDBIJ0 B40 J24 HDJ46 DMI_RXP1 AE9 AD4 C491 0.1uF DMI_TXP1 U31 R196 +/-1%
12 HDBIJ0 FSB_DINVB_0 FSB_DB_46 24 DMI_RXP1 DMI_RXP_1 DMI_TXP_1 DMI_TXP1 24 RSVD_17
K31 N24 HDJ47 DMI_RXN1 AE10 AE4 C492 0.1uF DMI_TXN1 R15
12 HDSTBPJ1 FSB_DSTBPB_1 FSB_DB_47 24 DMI_RXN1 DMI_RXN_1 DMI_TXN_1 DMI_TXN1 24 RSVD_18
J31 C28 HDJ48 DMI_RXP2 AE6 AE2 C493 0.1uF DMI_TXP2 TP_MCH_R14 R14
12 HDSTBNJ1 FSB_DSTBNB_1 FSB_DB_48 24 DMI_RXP2 DMI_RXP_2 DMI_TXP_2 DMI_TXP2 TP24
24 RSVD_19

DMI
C HDBIJ1 F33 B31 HDJ49 DMI_RXN2 AE7 AF2 C494 0.1uF DMI_TXN2 TP_MCH_T15 T15 AN17 C
12 HDBIJ1 FSB_DINVB_1 FSB_DB_49 24 DMI_RXN2 DMI_RXN_2 DMI_TXN_2 DMI_TXN2 TP28
24 RSVD_20 NC1
J25 F35 HDJ50 DMI_RXP3 AF9 AF4 C495 0.1uF DMI_TXP3 TP_MCH_T14 T14 A44
12 HDSTBPJ2 FSB_DSTBPB_2 FSB_DB_50 24 DMI_RXP3 DMI_RXP_3 DMI_TXP_3 DMI_TXP3 TP29
24 RSVD_21 NC2
K25 C35 HDJ51 DMI_RXN3 AF8 AG4 C496 0.1uF DMI_TXN3 TP_MCH_AB15 AB15 BD1
12 HDSTBNJ2 FSB_DSTBNB_2 FSB_DB_51 24 DMI_RXN3 DMI_RXN_3 DMI_TXN_3 DMI_TXN3 TP31
24 RSVD_22 NC3
HDBIJ2 F26 B35 HDJ52 TP_MCH_A45 A45 BD45
12 HDBIJ2 FSB_DINVB_2 FSB_DB_52 1D1V_MCH TP8 RSVD_23 NC4
C32 D35 HDJ53 TP_MCH_B2 B2 BE2
12 HDSTBPJ3 FSB_DSTBPB_3 FSB_DB_53 TP9 RSVD_24 NC5
D32 D31 HDJ54 TP_MCH_BE1 BE1 BE44
TP40

*
12 HDSTBNJ3 HDBIJ3 FSB_DSTBNB_3 FSB_DB_54 HDJ55 GMCH_EXP_COMP R158 49.9 TP_MCH_BE45 BE45 RSVD_25 NC6
12 HDBIJ3 D30 FSB_DINVB_3 FSB_DB_55 A34
HDJ56
7 CK_PE_100M_P_GMCH D9 EXP_CLKP EXP_RCOMPO Y7
+/-1%
TP41
TP_MCH_L13 RSVD_26 NC7 B14 Del circuit for HDMI
FSB_DB_56 B32 7 CK_PE_100M_N_GMCH E9 EXP_CLKN EXP_COMPI Y8 L13 RSVD_27 NC8 B45
J42 F31 HDJ57 Y6 TP_MCH_L11 L11 AK15
TP20

**
12 HADSJ FSB_ADSB FSB_DB_57 HDJ58 R126 0 EXP_ICOMPO RSVD_28 NC9
12 HTRDYJ L40 FSB_TRDYB FSB_DB_58 D28 22 SDVO_CTRLDATA J13 SDVO_CTRLDATA NC10 AD42
J43 A29 HDJ59 R127 0 G13 R160 AN16

*
12 HDRDYJ FSB_DRDYB FSB_DB_59 HDJ60 22 SDVO_CTRLCLK SDVO_CTRLCLK GMCH_EXP_RBIAS 750 NC11
12 HDEFERJ G44 FSB_DEFERB FSB_DB_60 C30 EXP_RBIAS AG1 NC12 W30
K44 B30 HDJ61 TP_MCH_AB13 AB13 +/-1% AW44
12 HITMJ FSB_HITMB FSB_DB_61 TP34 RSVD_1 NC13
H45 E27 HDJ62 TP_MCH_AD13 AD13 R42
12 HITJ FSB_HITB FSB_DB_62 TP33 RSVD_2 NC14
H40 B28 HDJ63 U32
12 HLOCKJ FSB_LOCKB FSB_DB_63 NC15
12 HBR0J L42 FSB_BREQ0B
12 HBNRJ J44 FSB_BNRB AC82G41
H37 B24 HSWING
12 HBPRIJ FSB_BPRIB FSB_SWING HRCOMP
12 HDBSYJ H42 FSB_DBSYB FSB_RCOMP A23
12 HRSJ0 G43 FSB_RSB_0
L44 C22 MCH_GTLREF
12 HRSJ1 FSB_RSB_1 FSB_DVREF 1D1V_MCH
12 HRSJ2 G42 FSB_RSB_2 FSB_ACCVREF B23
D27 AC82G41
9,12 HCPURSTJ FSB_CPURSTB R391
HPL_CLKINP P29 CK_200M_P_GMCH 7
TP_MCH_N25 N25 P30 DMI_RXP0 4.7K
Dummy
TP18 RSVD_3 HPL_CLKINN CK_200M_N_GMCH 7
R392
+/-5%
DMI_RXP1 4.7K
Dummy
AC82G41 +/-5%
R393
DMI_RXP2 4.7K
Dummy
R394
+/-5%
DMI_RXP3 4.7K
Dummy
+/-5%

FSB_VTT
FSB_VTT
DEL R445,R227
B
*R142 *R130 3D3V_SYS B

57.6 Ohm

*
301 +/-1% placed close to GMCH within 500 mils TP_MCH_L13 R136 10K
+/-1% 4 mils width dummy
*

R135 49.9 MCH_GTLREF Del Non-Graphic sku pull down components. 6 mils spacing to static signals
*

R146 49.9 HSWING +/-1% 12 mils spacing to toppling signals

+/-1%
R155 1.02KOhm DAC_REFSET DEL R276, R441
*R140 * * C158 *R123 * C163 +/-1%
C162 1uF 100 Ohm 220pF

*
100 Ohm 0.1uF +/-1% 50V, NPO, +/-5% R116 10K H_FSBSEL0
+/-1% 16V, Y5V, +80%/-20% 10V, Y5V, +80%/-20% dummy 7,12 FSBSEL0

* * *
FSBSEL1_1 R128 1K TP_MCH_J15
HSWING voltage should be 0.25*FSB_VTT 7 FSBSEL1_1 dummy
10 mils width, 10 mils spacing GTLREF voltage should be 0.67*VTT = 0.75V ATX: dummy
max. 3 inches long 12 mils width, 15 mils spacing BTX: pop R125 1K TP_MCH_J20
divider should be within 1.5" of the GTLREF pin FSBSEL2 dummy

*
220pF caps should be placed near MCH pin 7,12 FSBSEL2 R124 1K EXP_SLR
place series resistor as close to divider dummy R122 1K TP_MCH_F20
Resistor and Capacitor next to each other dummy

2x8 PEG port Bifurcation:

0 = 2x8 PCIe Ports Enabled
1 = 1x16 PCIe Port Enabled
FSB_VTT
*

HRCOMP R145 16.5 3D3V_SYS

+/-1%

10 mils width, 7 mils spacing

1D1V_MCH @MEMOC *R106
470 * R121
Dummy DEL R440 ,G41 not support ITPM
@MEMOC +/-5% 10K

*
max. 500 mils ? JP1(P1 & P2) R117 0 EXP_SM MCH Enable Strap
5 on 5 mils in breakout, max 250 mils JP1 22 GMCH_EXP_EN_HDR
R168 R199
* 0: Enable TPM
*

1K PLTRSTJ 2.2KOhm CL_RST 3 1: Disable TPM

*

+/-1% 22,24,28,34 PLTRSTJ +/-1% 3 MEM OC1 R107 10K H_FSBSEL1

0.35V 2 2
Update: Ref to spec update SWAT 080430
1 +/-5%FSBSEL1_1
CL_VREF_MCH R190 1 Jumper_2P_Blu
A 1.1KOhm A
* +/-1% ? Header_1X3
*R170 * C240 @NOmem OC @MEMOC
*

464 0.1uF MEM OC1 R108 0FSBSEL1_1

+/-1% 16V, Y5V, +80%/-20%

JP2
JP2(P1 & P2)
Check DG1.2 3
*

useR2=464ohm????? 3 MEM OC2 R109 10K H_FSBSEL2

2 2
1 +/-5% FSBSEL2
min. 4 mils width
10 mils spacing
1
Jumper_2P_Blu
FOXCONN PCEG
5 mils min. for max. of 300 mils in breakout Header_1X3 Title
@MEMOC @NOmem OC @MEMOC Eaglelake -GMCH -1
*

MEM OC2 R110 0 FSBSEL2

Size Document Number Rev
C G41M01 A

Date: Tuesday, October 07, 2008 Sheet 14 of 38

5 4 3 2 1
 5 4 3 2 1

U9D 4 OF 10
U9C 3 OF 10
18,19 M_MAA_A[14..0] M_DQS_A[7..0] 19 20,21 M_MAA_B[14..0] M_DQS_B[7..0] 21
M_MAA_A0 BC41 BC5 M_DQS_A0 M_MAA_B0 BD24 AW8 M_DQS_B0
DDR_A_MA_0 DDR_A_DQS_0 M_DQS_AJ[7..0] 19 DDR_B_MA_0 DDR_B_DQS_0 M_DQS_BJ[7..0] 21
M_MAA_A1 BC35 BD4 M_DQS_AJ0 M_MAA_B1 BB23 AW9 M_DQS_BJ0
DDR_A_MA_1 DDR_A_DQSB_0 M_DQM_A[7..0] 19 DDR_B_MA_1 DDR_B_DQSB_0 M_DQM_B[7..0] 21
M_MAA_A2 BB32 BC3 M_DQM_A0 M_MAA_B2 BB24 AY6 M_DQM_B0
DDR_A_MA_2 DDR_A_DM_0 M_DATA_A[63..0] 19 DDR_B_MA_2 DDR_B_DM_0 M_DATA_B[63..0] 21
M_MAA_A3 BC32 M_MAA_B3 BD23
M_MAA_A4 DDR_A_MA_3 M_DATA_A0 M_MAA_B4 DDR_B_MA_3 M_DATA_B0
BD32 DDR_A_MA_4 DDR_A_DQ_0 BC2 BB22 DDR_B_MA_4 DDR_B_DQ_0 AV7
M_MAA_A5 BB31 BD3 M_DATA_A1 M_MAA_B5 BD22 AW4 M_DATA_B1
M_MAA_A6 DDR_A_MA_5 DDR_A_DQ_1 M_DATA_A2 M_MAA_B6 DDR_B_MA_5 DDR_B_DQ_1 M_DATA_B2
AY31 DDR_A_MA_6 DDR_A_DQ_2 BD7 BC22 DDR_B_MA_6 DDR_B_DQ_2 BA9
M_MAA_A7 BA31 BB7 M_DATA_A3 M_MAA_B7 BC20 AU11 M_DATA_B3
M_MAA_A8 DDR_A_MA_7 DDR_A_DQ_3 M_DATA_A4 M_MAA_B8 DDR_B_MA_7 DDR_B_DQ_3 M_DATA_B4
BD31 DDR_A_MA_8 DDR_A_DQ_4 BB2 BB20 DDR_B_MA_8 DDR_B_DQ_4 AU7
M_MAA_A9 BD30 BA3 M_DATA_A5 M_MAA_B9 BD20 AU8 M_DATA_B5
M_MAA_A10 DDR_A_MA_9 DDR_A_DQ_5 M_DATA_A6 M_MAA_B10 DDR_B_MA_9 DDR_B_DQ_5 M_DATA_B6
AW43 DDR_A_MA_10 DDR_A_DQ_6 BE6 BC26 DDR_B_MA_10 DDR_B_DQ_6 AW7
M_MAA_A11 BC30 BD6 M_DATA_A7 M_MAA_B11 BD19 AY9 M_DATA_B7
M_MAA_A12 DDR_A_MA_11 DDR_A_DQ_7 M_MAA_B12 DDR_B_MA_11 DDR_B_DQ_7
BB30 DDR_A_MA_12 M_DQS_A[7..0] 19 BB19 DDR_B_MA_12 M_DQS_B[7..0] 21
M_MAA_A13 AM42 BB9 M_DQS_A1 M_MAA_B13 BE38 AT15 M_DQS_B1
D DDR_A_MA_13 DDR_A_DQS_1 M_DQS_AJ[7..0] 19 DDR_B_MA_13 DDR_B_DQS_1 M_DQS_BJ[7..0] 21 D
M_MAA_A14 BD28 BC9 M_DQS_AJ1 M_MAA_B14 BA19 AU15 M_DQS_BJ1
DDR_A_MA_14 DDR_A_DQSB_1 M_DQM_A[7..0] 19 DDR_B_MA_14 DDR_B_DQSB_1 M_DQM_B[7..0] 21
BD9 M_DQM_A1 AR15 M_DQM_B1
DDR_A_DM_1 M_DATA_A[63..0] 19 DDR_B_DM_1 M_DATA_B[63..0] 21
18,19 M_WE_AJ AW42 DDR_A_WEB 20,21 M_WE_BJ BD36 DDR_B_WEB
AU42 BB8 M_DATA_A8 BC37 AY13 M_DATA_B8
18,19 M_CAS_AJ DDR_A_CASB DDR_A_DQ_8 M_DATA_A9 20,21 M_CAS_BJ DDR_B_CASB DDR_B_DQ_8 M_DATA_B9
18,19 M_RAS_AJ AV42 DDR_A_RASB DDR_A_DQ_9 AY8 20,21 M_RAS_BJ BD35 DDR_B_RASB DDR_B_DQ_9 AP15
BD11 M_DATA_A10 AW15 M_DATA_B10
M_BS_A0 DDR_A_DQ_10 M_DATA_A11 20,21 M_BS_B[2..0] M_BS_B0 DDR_B_DQ_10 M_DATA_B11
AV45 DDR_A_BS_0 DDR_A_DQ_11 BB11 BD26 DDR_B_BS_0 DDR_B_DQ_11 AT16
M_BS_A1 AY44 BC7 M_DATA_A12 M_BS_B1 BB26 AU13 M_DATA_B12
M_BS_A2 DDR_A_BS_1 DDR_A_DQ_12 M_DATA_A13 M_BS_B2 DDR_B_BS_1 DDR_B_DQ_12 M_DATA_B13
BC28 DDR_A_BS_2 DDR_A_DQ_13 BE8 BD18 DDR_B_BS_2 DDR_B_DQ_13 AW13
BD10 M_DATA_A14 AP16 M_DATA_B14
18,19 M_BS_A[2..0] DDR_A_DQ_14 M_DATA_A15 DDR_B_DQ_14 M_DATA_B15
18,19 M_SCS_A0J AU43 DDR_A_CSB_0 DDR_A_DQ_15 AY11 20,21 M_SCS_B0J BB35 DDR_B_CSB_0 DDR_B_DQ_15 AU16
18,19 M_SCS_A1J AR40 DDR_A_CSB_1 M_DQS_A[7..0] 19 20,21 M_SCS_B1J BD39 DDR_B_CSB_1 M_DQS_B[7..0] 21
AU44 BD15 M_DQS_A2 BB37 AR20 M_DQS_B2
DDR_A_CSB_2 DDR_A_DQS_2 M_DQS_AJ[7..0] 19 DDR_B_CSB_2 DDR_B_DQS_2 M_DQS_BJ[7..0] 21
AM43 BB15 M_DQS_AJ2 BD40 AR17 M_DQS_BJ2
DDR_A_CSB_3 DDR_A_DQSB_2 M_DQM_A[7..0] 19 DDR_B_CSB_3 DDR_B_DQSB_2 M_DQM_B[7..0] 21
BD14 M_DQM_A2 AU17 M_DQM_B2
18,19 M_SCKE_A[1..0] DDR_A_DM_2 M_DATA_A[63..0] 19 20,21 M_SCKE_B[1..0] DDR_B_DM_2 M_DATA_B[63..0] 21
M_SCKE_A0 BB27 M_SCKE_B0 BC18
M_SCKE_A1 DDR_A_CKE_0 M_DATA_A16 M_SCKE_B1 DDR_B_CKE_0 M_DATA_B16
BD27 DDR_A_CKE_1 DDR_A_DQ_16 BB14 AY20 DDR_B_CKE_1 DDR_B_DQ_16 AY17
BA27 BC14 M_DATA_A17 BE17 AV17 M_DATA_B17
DDR_A_CKE_2 DDR_A_DQ_17 M_DATA_A18 DDR_B_CKE_2 DDR_B_DQ_17 M_DATA_B18
AY26 DDR_A_CKE_3 DDR_A_DQ_18 BC16 BB18 DDR_B_CKE_3 DDR_B_DQ_18 AR21
BB16 M_DATA_A19 AV20 M_DATA_B19
18,19 M_ODT_A[1..0] M_ODT_A0 DDR_A_DQ_19 M_DATA_A20 20,21 M_ODT_B[1..0] M_ODT_B0 DDR_B_DQ_19 M_DATA_B20
AR42 DDR_A_ODT_0 DDR_A_DQ_20 BC11 BD37 DDR_B_ODT_0 DDR_B_DQ_20 AP17
M_ODT_A1 AM44 BE12 M_DATA_A21 M_ODT_B1 BC39 AW16 M_DATA_B21
DDR_A_ODT_1 DDR_A_DQ_21 M_DATA_A22 DDR_B_ODT_1 DDR_B_DQ_21 M_DATA_B22
AR44 DDR_A_ODT_2 DDR_A_DQ_22 BA15 BB38 DDR_B_ODT_2 DDR_B_DQ_22 AT20
AL40 BD16 M_DATA_A23 BD42 AN20 M_DATA_B23
DDR_A_ODT_3 DDR_A_DQ_23 DDR_B_ODT_3 DDR_B_DQ_23
M_DQS_A[7..0] 19 M_DQS_B[7..0] 21
AY37 AR22 M_DQS_A3 AY33 AU26 M_DQS_B3
19 CK_M_200M_P_DDR0_A DDR_A_CK_0 DDR_A_DQS_3 M_DQS_AJ[7..0] 19 21 CK_M_200M_P_DDR0_B DDR_B_CK_0 DDR_B_DQS_3 M_DQS_BJ[7..0] 21
BA37 AT22 M_DQS_AJ3 AW33 AT26 M_DQS_BJ3
19 CK_M_200M_N_DDR0_A DDR_A_CKB_0 DDR_A_DQSB_3 M_DQM_A[7..0] 19 21 CK_M_200M_N_DDR0_B DDR_B_CKB_0 DDR_B_DQSB_3 M_DQM_B[7..0] 21
AW29 AV22 M_DQM_A3 AV31 AV25 M_DQM_B3
19 CK_M_200M_P_DDR1_A DDR_A_CK_1 DDR_A_DM_3 M_DATA_A[63..0] 19 21 CK_M_200M_P_DDR1_B DDR_B_CK_1 DDR_B_DM_3 M_DATA_B[63..0] 21
19 CK_M_200M_N_DDR1_A AY29 DDR_A_CKB_1 21 CK_M_200M_N_DDR1_B AW31 DDR_B_CKB_1
AU37 AW21 M_DATA_A24 AW35 AT25 M_DATA_B24
19 CK_M_200M_P_DDR2_A DDR_A_CK_2 DDR_A_DQ_24 M_DATA_A25 21 CK_M_200M_P_DDR2_B DDR_B_CK_2 DDR_B_DQ_24 M_DATA_B25
19 CK_M_200M_N_DDR2_A AV37 DDR_A_CKB_2 DDR_A_DQ_25 AY22 21 CK_M_200M_N_DDR2_B AY35 DDR_B_CKB_2 DDR_B_DQ_25 AV26
AU33 AV24 M_DATA_A26 AT31 AU29 M_DATA_B26
DDR_A_CK_3 DDR_A_DQ_26 M_DATA_A27 DDR_B_CK_3 DDR_B_DQ_26 M_DATA_B27
AT33 DDR_A_CKB_3 DDR_A_DQ_27 AY24 AU31 DDR_B_CKB_3 DDR_B_DQ_27 AV29
AT30 AU21 M_DATA_A28 AP31 AW25 M_DATA_B28
DDR_A_CK_4 DDR_A_DQ_28 M_DATA_A29 DDR_B_CK_4 DDR_B_DQ_28 M_DATA_B29
AR30 DDR_A_CKB_4 DDR_A_DQ_29 AT21 AP30 DDR_B_CKB_4 DDR_B_DQ_29 AR25
AW38 AR24 M_DATA_A30 AW37 AP26 M_DATA_B30
DDR_A_CK_5 DDR_A_DQ_30 M_DATA_A31 DDR_B_CK_5 DDR_B_DQ_30 M_DATA_B31
AY38 DDR_A_CKB_5 DDR_A_DQ_31 AU24 AV35 DDR_B_CKB_5 DDR_B_DQ_31 AR29
C C
M_DQS_A[7..0] 19 M_DQS_B[7..0] 21
AH43 M_DQS_A4 AR38 M_DQS_B4
DDR_A_DQS_4 M_DQS_AJ[7..0] 19 DDR_B_DQS_4 M_DQS_BJ[7..0] 21
AH42 M_DQS_AJ4 AR37 M_DQS_BJ4
DDR_A_DQSB_4 M_DQM_A[7..0] 19 DDR_B_DQSB_4 M_DQM_B[7..0] 21
AK42 M_DQM_A4 AR43 AU39 M_DQM_B4
DDR_A_DM_4 M_DATA_A[63..0] 19 DDR3_A_CSB1 DDR_B_DM_4 M_DATA_B[63..0] 21
BB40 DDR3_A_MA0
Note: AL41 M_DATA_A32 AT44 AR36 M_DATA_B32
For a single DIMM per channel implementation, DDR_A_DQ_32 M_DATA_A33 DDR3_A_WEB DDR_B_DQ_32 M_DATA_B33
DDR_A_DQ_33 AK43 AV40 DDR3_A_ODT3 DDR_B_DQ_33 AU38
the following second DIMM specific system memory AG42 M_DATA_A34 DDR3_DRAM_PWROK AR6 AN35 M_DATA_B34
signals should be tested pointed. DDR_A_DQ_34 M_DATA_A35 DDR3_A_DRAM_PWROK DDR_B_DQ_34 M_DATA_B35
AG44 BC24 AN37
CK/CKB[5:3] - DDR2 Clock Pairs
CK/CKB[3 and 5] - Channel A DDR3 Clock Pairs
DDR_A_DQ_35
DDR_A_DQ_36 AL42 M_DATA_A36 R189 * DDR3_DRAMRSTB DDR_B_DQ_35
DDR_B_DQ_36 AV39 M_DATA_B36
AK44 M_DATA_A37 0 AW39 M_DATA_B37
CK/CKB[3 and 4] - Channel B DDR3 Clock Pairs DDR_A_DQ_37 M_DATA_A38 DDR_B_DQ_37 M_DATA_B38
CSB[3:2] DDR_A_DQ_38 AH44 DDR_B_DQ_38 AU40
AG41 M_DATA_A39 AU41 M_DATA_B39
CKE[3:2] DDR_A_DQ_39 DDR_B_DQ_39
ODT[3:2] M_DQS_A[7..0] 19 AN29 RSVD_4 M_DQS_B[7..0] 21
AD43 M_DQS_A5 AN30 AK34 M_DQS_B5
DDR_A_DQS_5 M_DQS_AJ[7..0] 19 RSVD_5 DDR_B_DQS_5 M_DQS_BJ[7..0] 21
AE42 M_DQS_AJ5 AJ33 AL34 M_DQS_BJ5
DDR_A_DQSB_5 M_DQM_A[7..0] 19 RSVD_6 DDR_B_DQSB_5 M_DQM_B[7..0] 21
AE45 M_DQM_A5 AK33 AL37 M_DQM_B5
DDR_A_DM_5 M_DATA_A[63..0] 19 RSVD_7 DDR_B_DM_5 M_DATA_B[63..0] 21
AF43 M_DATA_A40 AL35 M_DATA_B40
DDR_A_DQ_40 M_DATA_A41 DDR_B_DQ_40 M_DATA_B41
DDR_A_DQ_41 AF42 DDR_B_DQ_41 AL36
AC44 M_DATA_A42 AK36 M_DATA_B42
DDR_A_DQ_42 M_DATA_A43 DDR_B_DQ_42 M_DATA_B43
DDR_A_DQ_43 AC42 DDR_B_DQ_43 AJ34
AF40 M_DATA_A44 AN39 M_DATA_B44
DDR_A_DQ_44 M_DATA_A45 DDR_B_DQ_44 M_DATA_B45
DDR_A_DQ_45 AF44 DDR_B_DQ_45 AN40
AD44 M_DATA_A46 AK37 M_DATA_B46
DDR_A_DQ_46 M_DATA_A47 MCH_DDR_VREF DDR_B_DQ_46 M_DATA_B47
DDR_A_DQ_47 AC41 BB44 DDR_VREF DDR_B_DQ_47 AL39
M_DQS_A[7..0] 19 M_DQS_B[7..0] 21
Y43 M_DQS_A6 AF37 M_DQS_B6
DDR_A_DQS_6 M_DQS_AJ[7..0] 19 DDR_B_DQS_6 M_DQS_BJ[7..0] 21
Y42 M_DQS_AJ6 AF36 M_DQS_BJ6
DDR_A_DQSB_6 M_DQM_A[7..0] 19 DDR_B_DQSB_6 M_DQM_B[7..0] 21
AA45 M_DQM_A6 MCH_DDR_RPD AY42 AJ35 M_DQM_B6
DDR_A_DM_6 M_DATA_A[63..0] 19 DDR_RPD DDR_B_DM_6 M_DATA_B[63..0] 21
MCH_DDR_RPU BA43
M_DATA_A48 MCH_DDR_SPD DDR_RPU M_DATA_B48
DDR_A_DQ_48 AB43 BC43 DDR_SPD DDR_B_DQ_48 AJ38
AA42 M_DATA_A49 MCH_DDR_SPU BC44 AJ37 M_DATA_B49
DDR_A_DQ_49 M_DATA_A50 DDR_SPU DDR_B_DQ_49 M_DATA_B50
DDR_A_DQ_50 W42 DDR_B_DQ_50 AF38
W41 M_DATA_A51 AE37 M_DATA_B51
DDR_A_DQ_51 M_DATA_A52 DDR_B_DQ_51 M_DATA_B52
DDR_A_DQ_52 AB42 DDR_B_DQ_52 AK40
AB44 M_DATA_A53 AJ40 M_DATA_B53
DDR_A_DQ_53 M_DATA_A54 DDR_B_DQ_53 M_DATA_B54
B DDR_A_DQ_54 Y44 DDR_B_DQ_54 AF34 B
Y40 M_DATA_A55 AE35 M_DATA_B55
DDR_A_DQ_55 DDR_B_DQ_55
M_DQS_A[7..0] 19 M_DQS_B[7..0] 21
T44 M_DQS_A7 AB35 M_DQS_B7
DDR_A DDR_A_DQS_7
DDR_A_DQSB_7 T43 M_DQS_AJ7
M_DQS_AJ[7..0] 19
M_DQM_A[7..0] 19
DDR_B_DQS_7
DDR_B_DQSB_7 AD35 M_DQS_BJ7
M_DQS_BJ[7..0] 21
M_DQM_B[7..0] 21
T42 M_DQM_A7 AD37 M_DQM_B7
DDR_A_DM_7 M_DATA_A[63..0] 19 DDR_B DDR_B_DM_7 M_DATA_B[63..0] 21
V42 M_DATA_A56 AD40 M_DATA_B56
DDR_A_DQ_56 M_DATA_A57 DDR_B_DQ_56 M_DATA_B57
DDR_A_DQ_57 U45 DDR_B_DQ_57 AD38
R40 M_DATA_A58 AB40 M_DATA_B58
DDR_A_DQ_58 M_DATA_A59 DDR_B_DQ_58 M_DATA_B59
DDR_A_DQ_59 P44 DDR_B_DQ_59 AA39
V44 M_DATA_A60 AE36 M_DATA_B60
DDR_A_DQ_60 M_DATA_A61 DDR_B_DQ_60 M_DATA_B61
DDR_A_DQ_61 V43 DDR_B_DQ_61 AE39
R41 M_DATA_A62 AB37 M_DATA_B62
DDR_A_DQ_62 M_DATA_A63 DDR_B_DQ_62 M_DATA_B63
DDR_A_DQ_63 R44 DDR_B_DQ_63 AB38

AC82G41
AC82G41

1D8V_STR DDRII Compensation Group Signals

*R191
1K R171 * 80.6 MCH_DDR_RPD
+/-1% +/-1%

MCH_DDR_VREF
1D8V_STR

*R194 * C244
*

1K 0.1uF R204 80.6 MCH_DDR_RPU

+/-1% 16V, Y5V, +80%/-20% +/-1%
* C239
0.1uF
16V, Y5V, +80%/-20%

A width 10 mils, spacing 10 mils A

*

5 mils width/spacing minimum for max. of 300 mils R206 249 OhmMCH_DDR_SPD
in GMCH break-out area
+/-1%
Placed close to GMCH pin

1D8V_STR
*

R207 80.6 MCH_DDR_SPU

+/-1%
* C256
0.1uF FOXCONN PCEG
16V, Y5V, +80%/-20%
Title
Eaglelake -GMCH -2
Size Document Number Rev
C G41M01 A

Date: Wednesday, September 24, 2008 Sheet 15 of 38

5 4 3 2 1
 5 4 3 2 1

1D1V_MCH 1D1V_PCIEXPRESS

VCCDQ_CRT is very sensitive to 1250mA

1D5V_CORE low frequency noise (noise below 1MHz). U9G 7 OF 10 U9F 6 OF 10
L19
1D1V_MCH 1D1V_MCH 1D1V_MCH #REFDE32 1 COPPER
R144 1 VCCDQ_CRT
* #REFDE12 1 COPPER
(mA)MinVout AA32 AK21 AA19 AA14
VCC_CL_1 VCC_CL_42 VCC_1 VCC_EXP_1

1
VCCDQ_CRT 0.5 1.35V
FB 600 Ohm
* C161
1uF
AA33
AB32
VCC_CL_2
VCC_CL_3
VCC_CL_43
VCC_CL_44
AK22
AK23
AA21
AA23
VCC_2
VCC_3
VCC_EXP_2
VCC_EXP_3
AA15
AB14
#REFDE22 1 COPPER

10V, Y5V, +80%/-20% AB33 AK24 AA25 AC15

2
VCC_CL_4 VCC_CL_45 VCC_4 VCC_EXP_4
AD32 VCC_CL_5 VCC_CL_46 AK25 AA27 VCC_5 VCC_EXP_5 AD14
D
AD33 VCC_CL_6 VCC_CL_47 AK26 AA29 VCC_6 VCC_EXP_6 AD15 D
AE32 VCC_CL_7 VCC_CL_48 AK27 AA30 VCC_7 VCC_EXP_7 AE14

1
AE33
AF32
VCC_CL_8
VCC_CL_9
VCC_CL_49
VCC_CL_50
AK29
AK30
AB20
AB22
VCC_8
VCC_9
VCC_EXP_8
VCC_EXP_9
AE15
AF14
* C224
10uF * C223
10uF * C225
10uF
1D5V_CORE AJ32 AL1 AB24 AF15 10V, Y5V, +80%/-20%

2
VCC_CL_10 VCC_CL_51 VCC_10 VCC_EXP_10 10V, Y5V, +80%/-20% 10V, Y5V, +80%/-20%
AK31 VCC_CL_11 VCC_CL_52 AL10 AB26 VCC_11 VCC_EXP_11 AG15
AL30 VCC_CL_12 VCC_CL_53 AL11 AB29 VCC_12 VCC_EXP_12 AJ10

*
Check footprint 0603??? AM15 VCC_CL_13 VCC_CL_54 AL12 AB30 VCC_13 VCC_EXP_13 AJ11
L22 AM16 AL14 AC16 AJ12
(mA)MinVout VCC_CL_14 VCC_CL_55 VCC_14 VCC_EXP_14
FB 600 Ohm AM17 VCC_CL_15 VCC_CL_56 AL15 AC17 VCC_15 VCC_EXP_15 AJ13
VCCA_EXP 4 1.425V AM20 AL16 AC19 AJ14
VCC_CL_16 VCC_CL_57 VCC_16 VCC_EXP_16
AM21 AL17 AC21 AJ6
*
R143 40.2 R153 1 VCCA_EXP VCC_CL_17 VCC_CL_58 VCC_17 VCC_EXP_17
Dummy AM22 VCC_CL_18 VCC_CL_59 AL19 AC23 VCC_18 VCC_EXP_18 AJ7
+/-1% AM24 AL2 AC25 AJ8
VCC_CL_19 VCC_CL_60 VCC_19 VCC_EXP_19

1
*R152 *
39.2
Dummy
C185
1uF
AM25
AM26
VCC_CL_20
VCC_CL_21
VCC_CL_61
VCC_CL_62
AL20
AL21
AC27
AC29
VCC_20
VCC_21
VCC_EXP_20
VCC_EXP_21
AJ9
AK10
+/-1% 10V, Y5V, +80%/-20% AM29 AL22 AD16 AK11

2
3D3V_SYS VCC_CL_22 VCC_CL_63 VCC_22 VCC_EXP_22
Y32 VCC_CL_23 VCC_CL_64 AL23 AD17 VCC_23 VCC_EXP_23 AK12
L17 Y33 AL24 AD20 AK13 1D1V_MCH
(mA)MinVout VCC_CL_24 VCC_CL_65 VCC_24 VCC_EXP_24
AP1 VCC_CL_25 VCC_CL_66 AL25 AD22 VCC_25 VCC_EXP_25 AK6
R151 1 VCCA_DAC VCCA_DAC 70 2.97V
* AP2
Y31
VCC_CL_26
VCC_CL_27
VCC_CL_67
VCC_CL_68
AL26
AL27
AD24
AD26
VCC_26
VCC_27
VCC_EXP_26
VCC_EXP_27
AK7
AK8

POWER
EC29 AA31 AL29 AD29 AK9
VCC_CL_28 VCC_CL_69 VCC_28 VCC_EXP_28
1

FB 600 Ohm * 220uF

* C173 AB31 VCC_CL_29 VCC_CL_70 AL4 AE16 VCC_29 VCC_EXP_29 U14

1
1uF
10V, Y5V, +80%/-20%
AC31
AD31
VCC_CL_30 VCC_CL_71 AL5
AL6
AE17
AE19
VCC_30 VCC_EXP_30 U15
W15
* C231
10uF * C235
10uF
2

6.3V, +/-20% VCC_CL_31 VCC_CL_72 VCC_31 VCC_EXP_31

AE31 AL7 AE21 Y14

2
VCC_CL_32 VCC_CL_73 VCC_32 VCC_EXP_32 10V, Y5V, +80%/-20% 10V, Y5V, +80%/-20%
AF31 VCC_CL_33 VCC_CL_74 AL8 AE23 VCC_33 VCC_EXP_33 Y15
AG30 VCC_CL_34 VCC_CL_75 AL9 AE25 VCC_34 VCC_EXP_34 AJ1
Stuff for Non-Graphic sku AG31 AM2 AE27 AJ2
VCC_CL_35 VCC_CL_76 VCC_35 VCC_EXP_35
AJ30 VCC_CL_36 VCC_CL_77 AM3 AE29 VCC_36 VCC_EXP_36 AK2
AJ31 AM4 AF16 AK3 Place in 1D1V_MCH_CL plane
VCC_CL_37 VCC_CL_78 VCC_37 VCC_EXP_37 (less than 100 mils from the package)
AK16 VCC_CL_38 VCC_CL_79 AJ15 AF17 VCC_38 VCC_EXP_38 AK4
AK17 VCC_CL_39 VCC_CL_80 AK14 AF19 VCC_39
AK19 VCC_CL_40 VCC_CL_81 AJ27 AF20 VCC_40
AK20 VCC_CL_41 VCC_CL_82 AJ29 AF21 VCC_41
(mA)(mVpp)MinVout Y29 AF22
1D1V_MCH VCCA_HPLL >50 70 1.045V VCC_CL_83 VCC_42
VCC_CL_84 Y30 Place these parts close to AF23 VCC_43

POWER
C W31 VCC_CKDDR ballout in MCH backside AF24 C
*

L18 270nH VCCA_HPLL VCC_CL_85 1D8V_STR VCC_44

AF25 VCC_45
+/-20% 1D1V_MCH AF26
1D8V_STR VCC_46 FSB_VTT
#REFDE5 VCC_DDR_1 AP44 AF27 VCC_47
1

For layout, change it from * C176

2.2uF 2 Dummy
1
VCCA_GPLLD
VCCD_HPLL
B12
U33
VCCDPLL_EXP
VCCD_HPLL
VCC_DDR_2
VCC_DDR_3
AT45
AV44
AF29
AG16
VCC_48
VCC_49

2
1D1V_MCH_CL to 1D1V_MCH. 6.3V, Y5V, +80%/-20% VCCA_GPLL B16 AY40 AG17 FSB_VTT
2

COPPER VCCAPLL_EXP VCC_DDR_4 L35 VCC_50

VCC_DDR_5 BA41 AG20 VCC_51
BB39 0.16uH L0805 1uH AG22 A25
VCC_DDR_6 VCC_52 VTT_FSB_1

1
VCCA_HPLL
VCCA_MPLL
B22
A21
VCCA_HPLL
VCCA_MPLL
VCC_DDR_7
VCC_DDR_8
BD21
BD25 (mA)MinVout
+/-10%
BACK
AG24
AG26
VCC_53
VCC_54
VTT_FSB_2
VTT_FSB_3
B25
B26
* C178
2.2uF * C151
2.2uF * C153
2.2uF
VCCA_DPLLA D20 BD29 VCC_SMCLK 450 1.7V AG29 C24

2
VCCA_DPLLB VCCA_DPLLA VCC_DDR_9 VCC_55 VTT_FSB_4
C20 VCCA_DPLLB VCC_DDR_10 BD34 AJ16 VCC_56 VTT_FSB_5 C26

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

3D3V_SYS BD38 VCC_CKDDR AJ17 D22
R132 VCC_DDR_11 VCC_57 VTT_FSB_6
BE23 AJ19 D23
*

VCC_DDR_12 C481 VCC_58 VTT_FSB_7

E19 VCC3_3 VCC_DDR_13 BE27 AJ21 VCC_59 VTT_FSB_8 D24
C160

(mA)(mVpp)MinVout
1D1V_MCH VCCA_MPLL >102 70 1.045V VCC_HDA VCC_DDR_14 BE31
* 0.1uF AJ23 VCC_60 VTT_FSB_9 E23
0 AR2 VCC_HDA VCC_DDR_15 BE36 Dummy
*R396 *R395 AJ25 VCC_61 VTT_FSB_10 F21
6.3V, X5R, +/-10%

* C155
* 0 0 R25 F22
*

L14 2.2uH VCCA_MPLL +/-5%

0.1uF 25V, Y5V, +80%/-20% +/-5% +/-5% VCC_62 VTT_FSB_11
R26 VCC_63 VTT_FSB_12 G21
+/-20% VCCA_DAC B19 BACK BACK R27 G22
VCCA_DAC_1 VCC_64 VTT_FSB_13
4.7uF

R131 1 16V, Y5V, +80%/-20% D19 BACK R29 H21

VCCA_DAC_2 VCC_65 VTT_FSB_14
VCC_CKDDR_1 AK32 T21 VCC_66 VTT_FSB_15 H22
For layout, change it from VCCA_EXP Place in FSB_VTT plane as close to the GMCH as possible
1D1V_MCH_CL to 1D1V_MCH.
A17 VCC_EXP VCC_CKDDR_2
VCC_CKDDR_3
AL31
AL32
* C480
22uF
T24
T25
VCC_67
VCC_68
VTT_FSB_16
VTT_FSB_17
J21
J22 (less than 100 mils from the package)
1

R134 1
* C156
10uF VCCDQ_CRT B20 VCCDQ_CRT
VCC_CKDDR_4 AM31 6.3V,X5R,+/-20% T26
T27
VCC_69
VCC_70
VTT_FSB_18
VTT_FSB_19
K21
K22
10V, Y5V, +80%/-20% B17 AM30 BACK T29 L21
2

VSS VCCCML_DDR VCC_71 VTT_FSB_20

U21 VCC_72 VTT_FSB_21 L22
U22 VCC_73 VTT_FSB_22 M21
VCCAVRAM_EXP AG2 U23 VCC_74 VTT_FSB_23 M22
U24 VCC_75 VTT_FSB_24 N20
U25 VCC_76 VTT_FSB_25 N21
L24 1D1V_MCH U26 N22 1D8V_STR
(mA)(mVpp)MinVout AC82G41 100nH VCC_77 VTT_FSB_26
U27 P20

*
1D1V_MCH VCCAPLL_EXP 50 20 1.045V VCCCML_DDR VCC_78 VTT_FSB_27
U29 VCC_79 VTT_FSB_28 P21
/VCCDPLL_EXP W19 P22
VCC_80 VTT_FSB_29
B
W21 VCC_81 VTT_FSB_30 P24 B
L21 1 2 L0805 1uH R147 1 VCCA_GPLLD 1D1V_MCH W23 R20
VCC_82 VTT_FSB_31

1
+/-10% W25 R21
* C248
* C260
* C259
* C250
* C257
* C249

*
VCC_83 VTT_FSB_32
1

R148 1 * C179
10uF * C181
0.1uF
VCCAVRAM_EXP R161 0 W27
W29
VCC_84 VTT_FSB_33 R22
R23
2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF

2
10V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% C221 VCC_85 VTT_FSB_34
Y20 R24
2

VCC_86 VTT_FSB_35

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

4.7uF
* 1D5V_CORE Y22
Y24
VCC_87

*
6.3V, X5R, +/-10% R162 0 VCC_88
Dummy Y26 VCC_89
(mA)(mVpp)MinVout dummy T22
L20 1 VCCA_GPLL VCCAPLL_EXP 50 20 1.045V VCC_90
2 L0805 1uH R129 1 T23 VCC_91
+/-10% /VCCDPLL_EXP VCC_HDA INT VRM DISABLE: VCCAVRM_EXP --->1.1V AC4 VCC_92
1

INT VRM ENABLE: VCCAVRM_EXP --->1.5V

R133 1 * C167
10uF * C189
0.1uF for better PCIe Gen2 performance???
AF3
F9
VCC_93
10V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% *R167 refer to EL update summary H4
VCC_94
2

0 052208 VCC_95
L3 VCC_96
If HDMI is not supported,VCC_HDA P3 Connect ground sides of caps with traces to GND balls
should be shorted to GND VCC_97 (less than 100 mils from the package)
V4 VCC_98

L16 1 2 L0805 10uH VCCA_DPLLA AC82G41

+/-20% 1D1V_MCH
* EC31
220uF * C175
0.1uF
6.3V, +/-20% 16V, Y5V, +80%/-20% (mA)(mVpp)MinVout
VCCA_DPLLA/B>102 50 1.045V

1
L15 1 2 L0805 10uH VCCA_DPLLB
1D1V_MCH 1D1V_MCH
* C232
10uF * C212
10uF * C233
10uF * C234
10uF
+/-20%

2
* EC30
* C174

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

220uF 0.1uF
6.3V, +/-20% 16V, Y5V, +80%/-20%
1

1
* C468
10uF * C469
10uF * C472
10uF * C473
10uF * C470
1uF * C476
1uF * C477
1uF * C478
1uF * C471
1uF * C474
1uF * C479
1uF * C475
1uF
2

2
BACK BACK BACK BACK BACK BACK BACK BACK BACK BACK BACK BACK
10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

A A

FOXCONN PCEG
Place these caps close to 1D1V_MCH plane in MCH backside
Title
Eaglelake -GMCH -3
Size Document Number Rev
C G41M01 A

Date: Wednesday, September 24, 2008 Sheet 16 of 38

5 4 3 2 1
 5 4 3 2 1

U9H 8 OF 10 U9I 9 OF 10
U9J 10 OF 10

BD12 VSS_186 VSS_271 W17

A12 VSS_1 VSS_94 AJ36 BD17 VSS_187 VSS_272 L26
A15 VSS_2 VSS_95 AJ39 BD43 VSS_188 VSS_273 L30
A19 VSS_3 VSS_96 AJ44 BD8 VSS_189 VSS_274 L35 VSS_355 A3
A27 VSS_4 VSS_97 AJ45 BE10 VSS_190 VSS_275 L39 VSS_356 A43
A31 VSS_5 VSS_98 AK35 BE15 VSS_191 VSS_276 L4 VSS_357 A6
A36 VSS_6 VSS_99 AK38 BE19 VSS_192 VSS_277 L8 VSS_358 B44
A40 VSS_7 VSS_100 AK39 BE21 VSS_193 VSS_278 L9 VSS_359 BC1
D
A8 VSS_8 VSS_101 AL38 BE25 VSS_194 VSS_279 M1 VSS_360 BC45 D
AA1 VSS_9 VSS_102 AL44 BE29 VSS_195 VSS_280 M24 VSS_361 BD2
AA11 VSS_10 VSS_103 AL45 BE34 VSS_196 VSS_281 M25 VSS_362 BD44
AA12 VSS_11 VSS_104 AN21 BE40 VSS_197 VSS_282 M44 VSS_363 BE3
AA13 VSS_12 VSS_105 AN22 C16 VSS_198 VSS_283 N11 VSS_364 BE43

GND
AA16 VSS_13 VSS_106 AN24 C3 VSS_199 VSS_284 N13 VSS_365 C1
AA17 VSS_14 VSS_107 AN25 C5 VSS_200 VSS_285 N16 VSS_366 C45
AA20 VSS_15 VSS_108 AN26 D11 VSS_201 VSS_286 N26 VSS_367 F1
AA22 VSS_16 VSS_109 AN33 D16 VSS_202 VSS_287 N29 VSS_368 BA5
AA24 VSS_17 VSS_110 AN36 D21 VSS_203 VSS_288 N30 VSS_369 AD30
AA26 VSS_18 VSS_111 AN38 D25 VSS_204 VSS_289 N33 VSS_370 AC30
AA34 VSS_19 VSS_112 AN7 D26 VSS_205 VSS_290 N36 VSS_371 AF30
AA38 VSS_20 VSS_113 AP20 D39 VSS_206 VSS_291 N38 VSS_372 AE30
AA40 VSS_21 VSS_114 AP21 D6 VSS_207 VSS_292 N8
AA44 VSS_22 VSS_115 AP22 D7 VSS_208 VSS_293 P16
AA8 VSS_23 VSS_116 AP24 E3 VSS_209 VSS_294 P17
AB11 VSS_24 VSS_117 AP25 E31 VSS_210 VSS_295 P25
AB12 VSS_25 VSS_118 AP29 E41 VSS_211 VSS_296 P26
AB16 VSS_26 VSS_119 AP45 E5 VSS_212 VSS_297 P31
AB17 VSS_27 VSS_120 AR10 F16 VSS_213 VSS_298 R11
AB19 VSS_28 VSS_121 AR11 F2 VSS_214 VSS_299 R12
AB21 AR13 F30 R16 AC82G41
VSS_29 VSS_122 VSS_215 VSS_300
AB23 VSS_30 VSS_123 AR16 F4 VSS_216 VSS_301 R17
AB25 VSS_31 VSS_124 AR26 F42 VSS_217 VSS_302 R19
AB27 VSS_32 VSS_125 AR3 F45 VSS_218 VSS_303 R2
AB34 VSS_33 VSS_126 AR31 G11 VSS_219 VSS_304 R30
AB36 VSS_34 VSS_127 AR33 G17 VSS_220 VSS_305 R38
AB39 VSS_35 VSS_128 AR35 G24 VSS_221 VSS_306 R45
AB4 VSS_36 VSS_129 AR39 G26 VSS_222 VSS_307 R5

GND
AB6 VSS_37 VSS_130 AR8 G29 VSS_223 VSS_308 R8
GND
AB7 VSS_38 VSS_131 AR9 G3 VSS_224 VSS_309 T10
AB8 VSS_39 VSS_132 AT1 G35 VSS_225 VSS_310 T11
AC20 VSS_40 VSS_133 AT11 H1 VSS_226 VSS_311 T12
AC22 VSS_41 VSS_134 AT13 H11 VSS_227 VSS_312 T13
AC24 VSS_42 VSS_135 AT17 H13 VSS_228 VSS_313 T16
AC26 VSS_43 VSS_136 AT2 H15 VSS_229 VSS_314 T17
AC45 VSS_44 VSS_137 AT24 H16 VSS_230 VSS_315 T19
AC5 VSS_45 VSS_138 AT29 H20 VSS_231 VSS_316 T20
C AD12 VSS_46 VSS_139 AT35 H25 VSS_232 VSS_317 T3 C
AD19 VSS_47 VSS_140 AU20 H30 VSS_233 VSS_318 T30
AD21 VSS_48 VSS_141 AU22 H31 VSS_234 VSS_319 T31
AD23 VSS_49 VSS_142 AU25 H33 VSS_235 VSS_320 T32
AD25 VSS_50 VSS_143 AU30 H38 VSS_236 VSS_321 T33
AD27 VSS_51 VSS_144 AU35 H44 VSS_237 VSS_322 T35
AD3 VSS_52 VSS_145 AU5 H7 VSS_238 VSS_323 T38
AD34 VSS_53 VSS_146 AU6 H8 VSS_239 VSS_324 T4
AD36 VSS_54 VSS_147 AU9 H9 VSS_240 VSS_325 T40
AD39 VSS_55 VSS_148 AV11 J3 VSS_241 VSS_326 T6
AD6 VSS_56 VSS_149 AV13 J37 VSS_242 VSS_327 T7
AD9 VSS_57 VSS_150 AV15 J4 VSS_243 VSS_328 T8
AE1 VSS_58 VSS_151 AV16 J5 VSS_244 VSS_329 T9
AE11 VSS_59 VSS_152 AV2 J8 VSS_245 VSS_330 U1
AE12 VSS_60 VSS_153 AV21 J9 VSS_246 VSS_331 W2
AE13 VSS_61 VSS_154 AV30 K11 VSS_247 VSS_332 W20
AE20 VSS_62 VSS_155 AV33 K13 VSS_248 VSS_333 W22
AE22 VSS_63 VSS_156 AV38 K17 VSS_249 VSS_334 W24
AE24 VSS_64 VSS_157 AV6 K20 VSS_250 VSS_335 W26
AE26 VSS_65 VSS_158 AV8 K24 VSS_251 VSS_336 W44
AE34 VSS_66 VSS_159 AV9 K29 VSS_252 VSS_337 W45
AE38 VSS_67 VSS_160 AW11 K33 VSS_253 VSS_338 W5
AE40 VSS_68 VSS_161 AW17 K45 VSS_254 VSS_339 Y10
AE44 VSS_69 VSS_162 AW20 L10 VSS_255 VSS_340 Y11
AE8 VSS_70 VSS_163 AW22 L16 VSS_256 VSS_341 Y12
AF10 VSS_71 VSS_164 AW24 L20 VSS_257 VSS_342 Y13
AF11 VSS_72 VSS_165 AW26 U11 VSS_258 VSS_343 Y16
AF12 VSS_73 VSS_166 AW3 U12 VSS_259 VSS_344 Y17
AF13 VSS_74 VSS_167 AW30 U13 VSS_260 VSS_345 Y19
AF33 VSS_75 VSS_168 AY1 U16 VSS_261 VSS_346 Y2
AF35 VSS_76 VSS_169 AY15 U17 VSS_262 VSS_347 Y21
AF39 VSS_77 VSS_170 AY16 U19 VSS_263 VSS_348 Y23
AF6 VSS_78 VSS_171 AY21 U20 VSS_264 VSS_349 Y25
AF7 VSS_79 VSS_172 AY25 U36 VSS_265 VSS_350 Y27
AG19 VSS_80 VSS_173 AY30 U39 VSS_266 VSS_351 Y3
AG21 VSS_81 VSS_174 AY45 U44 VSS_267 VSS_352 Y35
AG23 VSS_82 VSS_175 B10 U8 VSS_268 VSS_353 Y39
B
AG25 VSS_83 VSS_176 B21 W1 VSS_269 VSS_354 Y9 B
AG27 VSS_84 VSS_177 B27 W16 VSS_270
AG45 VSS_85 VSS_178 B29
AG5 VSS_86 VSS_179 B34
AH2 VSS_87 VSS_180 BA23
AH3 VSS_88 VSS_181 F8
AH4 VSS_89 VSS_182 BB21
AJ20 VSS_90 VSS_183 BB25
AJ22 VSS_91 VSS_184 BB28
AJ24 VSS_92 VSS_185 BB6
AJ26 VSS_93

UI1_1
1
U9_1
2 2
A D
1 1

FOXCONN

2 5C 5
B CLIP1N
Heatsink 6 6
1
A Heatsink A
2

Clip_2P

For GMCH heatsink hook

CLIP3N
1

2 FOXCONN PCEG
Clip_2P Title
Eaglelake -GMCH -4
Size Document Number Rev
C G41M01 A

Date: Wednesday, September 24, 2008 Sheet 17 of 38

5 4 3 2 1
 5 4 3 2 1

VTT_DDR M_ODT_A[1..0] 15,19

D M_SCKE_A[1..0] 15,19 D

M_BS_A[2..0] 15,19
R268 33 +/-5% M_MAA_A1
M_MAA_A[14..0] 15,19
R264 33 +/-5% M_MAA_A13

R258 33 +/-5% VTT_DDR

M_RAS_AJ 15,19
R259 33 +/-5%
M_WE_AJ 15,19 Need to Check Change to Dummy Need to Check Change to Dummy
R261 33 +/-5%
M_CAS_AJ 15,19 1D8V_STR

C342

C321

C335

C324

C332
C378

C337

C387

C325

C326

C383

C384
RN36
*1 2
M_MAA_A14
M_BS_A2 * * * * *
3 4

16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
M_MAA_A12
5
7
6
8
M_MAA_A11 * * * * * * *

16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
33
+/-5%
VTT_DDR
C C
RN37
*1 2
M_MAA_A9
M_MAA_A7 Reserved Reserved
3 4 M_MAA_A5
5 6 M_MAA_A8 Reserved Reserved
7 8
33
+/-5%
Channel A VTT_0.9V high-frequency decoupling caps.
RN38
Place as close to termination resistors as possible
*1 2
M_MAA_A6
M_MAA_A4
3 4 M_MAA_A3
5 6 M_MAA_A2
7 8 VTT_DDR
33
+/-5%
RN35
*1 2
M_MAA_A0
M_BS_A1
3 4 M_MAA_A10
5 6 M_BS_A0
7 8
33
+/-5% C391 C336

1
4.7uF 4.7uF
B * 6.3V, X5R, +/-10% * 6.3V, X5R, +/-10%
B

VTT_DDR

2
R266 43 Ohm
R267 43 Ohm M_SCKE_A1
M_SCKE_A0

VTT_DDR
Channel A VTT_0.9V Mid Range decoupling caps.
R260
R263
43 Ohm
43 Ohm
Placed in termination Island
M_SCS_A0J 15,19
R262 43 Ohm
M_ODT_A0 15,19
M_SCS_A1J 15,19
R265 43 Ohm
M_ODT_A1 15,19

A A

FOXCONN PCEG
Title
DDR2 Channel A Termination
Size Document Number Rev
Custom G41M01 A

Date: Tuesday, September 16, 2008 Sheet 18 of 38

5 4 3 2 1
 5 4 3 2 1

DIMM1

2 VSS NC_1 68
5 VSS NC/TEST 102
8 VSS NC_2 19 M_ODT_A[1..0] 15,18
11 VSS
14 VSS
17 77 M_ODT_A1
VSS ODT1 M_ODT_A0
20 VSS ODT0 195
23 VSS
26 VSS
29 VSS
32 42 1D8V_STR
VSS CB<0>
35 VSS CB<1> 43
38 VSS CB<2> 48
41 VSS CB<3> 49
D
44 VSS CB<4> 161 D
47 VSS CB<5> 162
1D8V_STR 50
65
VSS
VSS
CB<6>
CB<7>
167
168
* C323
*
0.1uF
C322
0.1uF * C396
0.1uF
66 VSS
79 For EMI
EC40 EC39 VSS
82 VSS
* 1000uF
+/-20%
* 1000uF
+/-20%
85
88
VSS M_DQS_AJ[7..0] 15
16V, Y5V, +80%/-20%
VSS M_DQS_A0 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
91 VSS DQS<0> 7
94 VSS DQS#<0> 6
97 M_DQS_AJ0
VSS M_DQS_A1
100 VSS DQS<1> 16
103 VSS DQS#<1> 15
Place between Ch A DIMM II 106 M_DQS_AJ1
VSS M_DQS_A2
and Ch B DIMM 1 109 VSS DQS<2> 28
112 VSS DQS#<2> 27
115 M_DQS_AJ2 1D8V_STR
VSS M_DQS_A3
118 VSS DQS<3> 37
121 VSS DQS#<3> 36
124 M_DQS_AJ3
VSS M_DQS_A4
127 VSS DQS<4> 84
1D8V_STR 130 83
VSS DQS#<4> M_DQS_AJ4
133
136
VSS
VSS DQS<5> 93 M_DQS_A5 *R271
1K
139 92 +/-1%
EC28 VSS DQS#<5> M_DQS_AJ5
142 VSS
* 1000uF
+/-20%
145
148
VSS DQS<6> 105
104
M_DQS_A6
VSS DQS#<6> M_DQS_AJ6 SMVREF_A
151 VSS
154 114 M_DQS_A7
VSS DQS<7>
Place between GMCH and DIMM 157 VSS DQS#<7> 113
160 M_DQS_AJ7 R269 C329 C316
163
VSS
VSS DQS<8> 46
M_DQS_A[7..0] 15 * 1K
* 0.1uF
* 0.1uF
166 45 +/-1% 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
VSS DQS#<8>
169 VSS
198 125 M_DQM_A0
VSS DM0/DQS9 Dummy
201 VSS NC/DQS9# 126
C 204 VSS
C
1D8V_STR 207 134 M_DQM_A1
VSS DM1/DQS10
210 VSS NC/DQS10# 135
213 VSS
216 146 M_DQM_A2 close to DIMM pin
VSS DM2/DQS11
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

219 147 Width 10 mils minimum, Spacing 10 mils minimum.

VSS NC/DQS11#
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

222 VSS
C296

225 155 M_DQM_A3

VSS DM3/DQS12
C298

C297

228 VSS NC/DQS12# 156

231 VSS
* * * 1D8V_STR
234
237
VSS
VSS
DM4/DQS13
NC/DQS13#
202
203
M_DQM_A4
10V, Y5V, +80%/-20%

51 VDDQ
1uF

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

56 211 M_DQM_A5
VDDQ DM5/DQS14 1D8V_STR
1uF

1uF

62 VDDQ NC/DQS14# 212

72 VDDQ
75 223 M_DQM_A6
VDDQ DM6/DQS15
78 VDDQ NC/DQS15# 224
191 VDDQ
194 232 M_DQM_A7
VDDQ DM7/DQS16
181 VDDQ NC/DQS16# 233

C320

C299
175 VDDQ M_DQM_A[7..0] 15
170 VDDQ DM8/DQS17 164
53 VDD NC/DQS17# 165
59
64
VDD
VDD DQ<0> 3 M_DATA_A0
M_DATA_A[63..0] 15 * *
3D3V_SYS

16V, Y5V, +80%/-20%

0.1uF

16V, Y5V, +80%/-20%

0.1uF
197 4 M_DATA_A1
VDD DQ<1> M_DATA_A2
69 VDD DQ<2> 9
Channel A DIMM 1 1.8V high-frequency decoupling caps. 172 10 M_DATA_A3
place as close to DIMM power pins as possible VDD DQ<3> M_DATA_A4
187 VDD DQ<4> 122
184 123 M_DATA_A5
VDD DQ<5> M_DATA_A6

SPD_PWR
*R273
0
178
189
VDD
VDD
DQ<6>
DQ<7>
128
129 M_DATA_A7
+/-5% 67 12 M_DATA_A8
VDD DQ<8> M_DATA_A9
DQ<9> 13
21 M_DATA_A10
DQ<10> M_DATA_A11
18 RC1 DQ<11> 22
55 131 M_DATA_A12
B RC0 DQ<12> M_DATA_A13 B
238 VDDSPD DQ<13> 132
SMVREF_A 1 140 M_DATA_A14 Channel A DIMM II 1.8V high-frequency decoupling caps.
7,21,35 SMB_CLK_MAIN VREF DQ<14> M_DATA_A15 place as close to DIMM power pins as possible
120 SCL DQ<15> 141
119 24 M_DATA_A16
7,21,35 SMB_DATA_MAIN SDA DQ<16> M_DATA_A17
DQ<17> 25
101 30 M_DATA_A18
SA2 DQ<18> M_DATA_A19
240 SA1 DQ<19> 31
239 143 M_DATA_A20
SA2 SA1 SA0 SA0 DQ<20> M_DATA_A21
DQ<21> 144
0 0 0 190 149 M_DATA_A22
15,18 M_BS_A[2..0] M_BS_A1 BA1 DQ<22> M_DATA_A23
71 BA0 DQ<23> 150
M_BS_A0 33 M_DATA_A24
DQ<24> M_DATA_A25
DQ<25> 34
15,18 M_SCKE_A[1..0] M_SCKE_A1 171 39 M_DATA_A26
M_SCKE_A0 CKE1 DQ<26> M_DATA_A27
52 CKE0 DQ<27> 40
152 M_DATA_A28
DQ<28> M_DATA_A29
DQ<29> 153
158 M_DATA_A30
M_SCS_A1J DQ<30> M_DATA_A31
76 S1# DQ<31> 159
15,18 M_SCS_A1J M_SCS_A0J 193 80 M_DATA_A32
15,18 M_SCS_A0J S0# DQ<32> M_DATA_A33
DQ<33> 81
221 86 M_DATA_A34
15 CK_M_200M_N_DDR2_A CK2#/RFU DQ<34> M_DATA_A35
220 CK2/RFU DQ<35> 87
15 CK_M_200M_P_DDR2_A 138 199 M_DATA_A36
15 CK_M_200M_N_DDR1_A CK1#/RFU DQ<36> M_DATA_A37
137 CK1/RFU DQ<37> 200
15 CK_M_200M_P_DDR1_A 186 205 M_DATA_A38
15 CK_M_200M_N_DDR0_A CK0# DQ<38> M_DATA_A39
185 CK0 DQ<39> 206
15 CK_M_200M_P_DDR0_A 89 M_DATA_A40
15,18 M_MAA_A[14..0] M_MAA_A0 DQ<40> M_DATA_A41
188 A0 DQ<41> 90
M_MAA_A1 183 95 M_DATA_A42
M_MAA_A2 A1 DQ<42> M_DATA_A43
63 A2 DQ<43> 96
M_MAA_A3 182 208 M_DATA_A44
M_MAA_A4 A3 DQ<44> M_DATA_A45
61 A4 DQ<45> 209
M_MAA_A5 60 214 M_DATA_A46
M_MAA_A6 A5 DQ<46> M_DATA_A47
180 A6 DQ<47> 215
M_MAA_A7 58 98 M_DATA_A48
M_MAA_A8 A7 DQ<48> M_DATA_A49
179 A8 DQ<49> 99
A M_MAA_A9 177 107 M_DATA_A50 A
M_MAA_A10 A9 DQ<50> M_DATA_A51
70 A10/AP DQ<51> 108
M_MAA_A11 57 217 M_DATA_A52
M_MAA_A12 A11 DQ<52> M_DATA_A53
176 A12 DQ<53> 218
M_MAA_A13 196 226 M_DATA_A54
M_MAA_A14 A13 DQ<54> M_DATA_A55
174 A14 DQ<55> 227
173 110 M_DATA_A56
15,18 M_BS_A[2..0] M_BS_A2 A15 DQ<56> M_DATA_A57
54 A16/BA2 DQ<57> 111
116 M_DATA_A58
DQ<58> M_DATA_A59
117
15,18 M_CAS_AJ 74 CAS#
DQ<59>
DQ<60> 229 M_DATA_A60
M_DATA_A61
FOXCONN PCEG
15,18 M_RAS_AJ 192 RAS# DQ<61> 230
73 235 M_DATA_A62 Title
15,18 M_WE_AJ WE# DQ<62> M_DATA_A63
DQ<63> 236 DDR2 Channel A DIMM1
Size Document Number Rev
DDR II
C G41M01 A

Date: Tuesday, September 23, 2008 Sheet 19 of 38

5 4 3 2 1
 5 4 3 2 1

M_SCKE_B[1..0] 15,21

M_BS_B[2..0] 15,21

M_MAA_B[14..0] 15,21

M_ODT_B[1..0] 15,21

D D

VTT_DDR

VTT_DDR R294 33 +/-5% M_MAA_B2

R295 33 +/-5% M_MAA_B13

R293 43 Ohm
R292 43 Ohm M_SCKE_B1 RN43
M_SCKE_B0
*1 2 M_RAS_BJ
M_WE_BJ
15,21
15,21
3 4
5 6 M_CAS_BJ 15,21
7 8
33
+/-5%

RN40
*1 2
M_BS_B2
M_MAA_B14
3 4 M_MAA_B12
5 6 M_MAA_B11
7 8
33
+/-5%
C C

RN41
VTT_DDR
*1 2
M_MAA_B9
M_MAA_B7
RN44 3 4 M_MAA_B8
5 6
*1 2 M_SCS_B0J
M_ODT_B0
15,21
15,21
7 8
M_MAA_B6
3 4 33
5 6 M_SCS_B1J 15,21
+/-5%
7 8 M_ODT_B1 15,21
43 Ohm
+/-5% RN42
*1 2
M_MAA_B5
M_MAA_B4
3 4 M_MAA_B3
5 6 M_MAA_B1
7 8
33
+/-5%
RN45
*1 2
M_MAA_B0
M_BS_B1
3 4 M_MAA_B10
5 6 M_BS_B0
7 8
33
+/-5%

B B

VTT_DDR Need to Check Change to Dummy

VTT_DDR Need to Check Change to Dummy 1D8V_STR
C386

C380

C341

C344

C382

C330

C379

C339

C319

C388

C350

C385
C377 C327
* * * * * * * * * * * *
1

* 4.7uF
* 4.7uF
16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF

16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
16V, Y5V, +80%/-20%

0.1uF
6.3V, X5R, +/-10% 6.3V, X5R, +/-10%
2

VTT_DDR

A A
Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Channel B VTT_0.9V Mid Range decoupling caps. Channel B VTT_0.9V high-frequency decoupling caps.
Placed in termination Island Place as close to termination resistors as possible
FOXCONN PCEG
Title
DDR2 Channel B Termination
Size Document Number Rev
C G41M01 A

Date: Tuesday, September 16, 2008 Sheet 20 of 38

5 4 3 2 1
 5 4 3 2 1
DIMM2

2 VSS NC_1 68
5 VSS NC/TEST 102
8 VSS NC_2 19 M_ODT_B[1..0] 15,20
11 VSS
14 VSS
17 77 M_ODT_B1
VSS ODT1 M_ODT_B0
20 VSS ODT0 195
23 VSS
26 VSS
29 VSS
32 VSS CB<0> 42
35 VSS CB<1> 43
38 48 1D8V_STR
VSS CB<2>
41 VSS CB<3> 49
44 VSS CB<4> 161
D
47 VSS CB<5> 162 D
50 VSS CB<6> 167
65 168 C389 C348 C397
VSS CB<7>
66
79
VSS
VSS
* 0.1uF
16V, Y5V, +80%/-20%
* 0.1uF
16V, Y5V, +80%/-20%
* 0.1uF
16V, Y5V, +80%/-20%
82 VSS
85 VSS M_DQS_BJ[7..0] 15
88 VSS
91 7 M_DQS_B0
VSS DQS<0>
94 VSS DQS#<0> 6
97 M_DQS_BJ0
VSS M_DQS_B1
100 VSS DQS<1> 16
103 VSS DQS#<1> 15
106 M_DQS_BJ1
VSS M_DQS_B2
109 VSS DQS<2> 28
112 VSS DQS#<2> 27
115 M_DQS_BJ2
VSS M_DQS_B3
118 VSS DQS<3> 37
121 VSS DQS#<3> 36
124 M_DQS_BJ3
VSS M_DQS_B4
127 VSS DQS<4> 84
130 VSS DQS#<4> 83
133 M_DQS_BJ4
1D8V_STR VSS M_DQS_B5
136 VSS DQS<5> 93
139 VSS DQS#<5> 92
142 M_DQS_BJ5
VSS M_DQS_B6
145 VSS DQS<6> 105
148 VSS DQS#<6> 104
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

151 M_DQS_BJ6
VSS M_DQS_B7
154 VSS DQS<7> 114
C345

C343

C390

C340

157 VSS DQS#<7> 113

160 M_DQS_BJ7
VSS M_DQS_B[7..0] 15
163 VSS DQS<8> 46
* * * * 166
169
VSS
VSS
DQS#<8> 45
1D8V_STR
10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

198 125 M_DQM_B0

VSS DM0/DQS9
1uF

1uF

1uF

1uF

201 VSS NC/DQS9# 126

204 VSS

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
C 207 134 M_DQM_B1 C
VSS DM1/DQS10
210 VSS NC/DQS10# 135

C333

C334

C351

C328
213 VSS
216 146 M_DQM_B2
VSS DM2/DQS11
219 VSS NC/DQS11# 147
222
225
VSS
VSS DM3/DQS12 155 M_DQM_B3 * * * *

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

228 VSS NC/DQS12# 156

1uF

1uF

1uF

1uF
231 VSS
234 202 M_DQM_B4
1D8V_STR VSS DM4/DQS13
237 VSS NC/DQS13# 203
Channel B DIMM1 1.8V high-frequency decoupling caps. 51
place as close to DIMM power pins as possible VDDQ M_DQM_B5
56 VDDQ DM5/DQS14 211
62 VDDQ NC/DQS14# 212
72 VDDQ
75 223 M_DQM_B6
VDDQ DM6/DQS15
78 VDDQ NC/DQS15# 224
191 VDDQ
194 232 M_DQM_B7
VDDQ DM7/DQS16
181 VDDQ NC/DQS16# 233
175 VDDQ M_DQM_B[7..0] 15
170 VDDQ DM8/DQS17 164
53 165 Channel B DIMM II 1.8V high-frequency decoupling caps.
VDD NC/DQS17# place as close to DIMM power pins as possible
59 VDD M_DATA_B[63..0] 15
64 3 M_DATA_B0
VDD DQ<0> M_DATA_B1
197 VDD DQ<1> 4
69 9 M_DATA_B2
VDD DQ<2> M_DATA_B3
172 VDD DQ<3> 10
187 122 M_DATA_B4
VDD DQ<4> M_DATA_B5
184 VDD DQ<5> 123
178 128 M_DATA_B6
VDD DQ<6> M_DATA_B7
189 VDD DQ<7> 129
67 12 M_DATA_B8
SPD_PWR VDD DQ<8> M_DATA_B9
DQ<9> 13
21 M_DATA_B10
DQ<10> M_DATA_B11 1D8V_STR
18 RC1 DQ<11> 22
55 131 M_DATA_B12
RC0 DQ<12> M_DATA_B13
B
238 VDDSPD DQ<13> 132 B
SMVREF_B 1 140 M_DATA_B14
VREF DQ<14> M_DATA_B15
120 SCL DQ<15> 141
7,19,35 SMB_CLK_MAIN 119 24 M_DATA_B16
7,19,35 SMB_DATA_MAIN SDA DQ<16> M_DATA_B17
SPD_PWR 101 SA2
DQ<17>
DQ<18>
25
30 M_DATA_B18 *R398
1K
240 31 M_DATA_B19 +/-1%
SA1 DQ<19> M_DATA_B20
239 SA0 DQ<20> 143
SA2 SA1 SA0 144 M_DATA_B21
0 1 0 DQ<21> M_DATA_B22
15,20 M_BS_B[2..0] 190 BA1 DQ<22> 149
M_BS_B1 71 150 M_DATA_B23 SMVREF_B
M_BS_B0 BA0 DQ<23> M_DATA_B24
DQ<24> 33
34 M_DATA_B25
15,20 M_SCKE_B[1..0] M_SCKE_B1 DQ<25> M_DATA_B26 R397
171 39
M_SCKE_B0 52
CKE1
CKE0
DQ<26>
DQ<27> 40 M_DATA_B27 * 1K
* C317
* C318
152 M_DATA_B28 +/-1% 0.1uF 0.1uF
DQ<28> M_DATA_B29
DQ<29> 153
158 M_DATA_B30
DQ<30> M_DATA_B31
76 S1# DQ<31> 159
15,20 M_SCS_B1J 193 80 M_DATA_B32
15,20 M_SCS_B0J S0# DQ<32> M_DATA_B33 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
DQ<33> 81
221 86 M_DATA_B34
15 CK_M_200M_N_DDR2_B CK2#/RFU DQ<34> M_DATA_B35
220 CK2/RFU DQ<35> 87
15 CK_M_200M_P_DDR2_B 138 199 M_DATA_B36 close to DIMM pin
15 CK_M_200M_N_DDR1_B CK1#/RFU DQ<36> M_DATA_B37 Width 10 mils minimum, Spacing 10 mils minimum.
137 CK1/RFU DQ<37> 200
15 CK_M_200M_P_DDR1_B 186 205 M_DATA_B38
15 CK_M_200M_N_DDR0_B CK0# DQ<38> M_DATA_B39
185 CK0 DQ<39> 206
15 CK_M_200M_P_DDR0_B 89 M_DATA_B40
15,20 M_MAA_B[14..0] M_MAA_B0 DQ<40> M_DATA_B41
188 A0 DQ<41> 90
M_MAA_B1 183 95 M_DATA_B42
M_MAA_B2 A1 DQ<42> M_DATA_B43
63 A2 DQ<43> 96
M_MAA_B3 182 208 M_DATA_B44
M_MAA_B4 A3 DQ<44> M_DATA_B45
61 A4 DQ<45> 209
M_MAA_B5 60 214 M_DATA_B46
M_MAA_B6 A5 DQ<46> M_DATA_B47
180 A6 DQ<47> 215
M_MAA_B7 58 98 M_DATA_B48
M_MAA_B8 A7 DQ<48> M_DATA_B49
179 A8 DQ<49> 99
M_MAA_B9 177 107 M_DATA_B50
M_MAA_B10 A9 DQ<50> M_DATA_B51
A 70 A10/AP DQ<51> 108 A
M_MAA_B11 57 217 M_DATA_B52
M_MAA_B12 A11 DQ<52> M_DATA_B53
176 A12 DQ<53> 218
M_MAA_B13 196 226 M_DATA_B54
M_MAA_B14 A13 DQ<54> M_DATA_B55
174 A14 DQ<55> 227
173 110 M_DATA_B56
15,20 M_BS_B[2..0] M_BS_B2 A15 DQ<56> M_DATA_B57
54 A16/BA2 DQ<57> 111
116 M_DATA_B58
DQ<58> M_DATA_B59
DQ<59> 117
M_DATA_B60
15,20 M_CAS_BJ
15,20 M_RAS_BJ
74
192
CAS#
RAS#
DQ<60>
DQ<61>
229
230 M_DATA_B61 FOXCONN PCEG
73 235 M_DATA_B62
15,20 M_WE_BJ WE# DQ<62> M_DATA_B63 Title
DQ<63> 236
DDR2 Channel B DIMM2
DDR II Size Document Number Rev
C G41M01 A

Date: Tuesday, September 23, 2008 Sheet 21 of 38

5 4 3 2 1
 5 4 3 2 1

D D

* R342
0
+/-5%

3D3V_SB 3D3V_SYS 12V_SYS 12V_SYS 3D3V_SYS 12V_SYS 3D3V_SYS 3D3V_SB

PCI-E1_16X C144 C70

1
B1 12V PRSNT1# A1
* C104
0.1uF * 0.1uF
16V, Y5V, +80%/-20%
* 0.1uF
16V, Y5V, +80%/-20%
B2 A2

2
12V 12V 25V, X7R, +/-10%
B3 RSVD1 12V A3
B4 GND GND A4
24,29,30,35 SMB_CLK_RESUME B5 SMCLK JTAG2 A5
B6 A6 PCIE_RSTJ
24,29,30,35 SMB_DATA_RESUME SMDAT JTAG3 PCIE_RSTJ 29
B7 GND JTAG4 A7
B8 3.3V JTAG5 A8
B9 JTAG1 3.3V A9
B10 A10

*
WAKEJ 3.3VAUX 3.3V R205
24,29 WAKEJ B11 WAKE# PWRGD A11 PLTRSTJ 14,24,28,34
0 +/-5%

All AC Coupling caps. should be placed within 250 mils of the connector KEY 12V_SYS 3D3V_SYS 12V_SYS
B12 RSVD2 GND A12
B13 A13 CK_PE_100M_P_16PORT
GND REFCLK+ CK_PE_100M_P_16PORT 7
EXP_TXP0_C B14 A14 CK_PE_100M_N_16PORT EC21 EC23 EC20
14 EXP_TXP0 CK_PE_100M_N_16PORT 7

*
HSOP0 REFCLK-
C142 0.1uF 16V, X7R, +/-10%
14 EXP_TXN0
EXP_TXN0_C B15 A15 * 270uF * 470uF * 470uF

*
C135 0.1uF 16V, X7R, +/-10% HSON0 GND 16V, +/-20% 6.3V, +/-20% 16V, +/-20%
B16 GND HSIP0 A16 EXP_RXP0 14
SDVO_CTRLCLK B17 A17
14 SDVO_CTRLCLK PRSNT2_B17# HSIN0 EXP_RXN0 14
B18 GND GND A18

EXP_TXP1_C B19 A19

14 EXP_TXP1
*

C145 0.1uF 16V, X7R, +/-10% EXP_TXN1_C HSOP1 RSVD3

C
14 EXP_TXN1 B20 A20 C

*
C146 0.1uF 16V, X7R, +/-10% HSON1 GND
B21 GND HSIP1 A21 EXP_RXP1 14
B22 GND HSIN1 A22 EXP_RXN1 14
EXP_TXP2_C B23 A23
14 EXP_TXP2
*

C147 0.1uF 16V, X7R, +/-10% EXP_TXN2_C HSOP2 GND

14 EXP_TXN2 B24 A24

*
C148 0.1uF 16V, X7R, +/-10% HSON2 GND
B25 GND HSIP2 A25 EXP_RXP2 14
B26 GND HSIN2 A26 EXP_RXN2 14
EXP_TXP3_C B27 A27
14 EXP_TXP3
*

C150 0.1uF 16V, X7R, +/-10% EXP_TXN3_C HSOP3 GND

14 EXP_TXN3 B28 A28

*
C152 0.1uF 16V, X7R, +/-10% HSON3 GND
B29 GND HSIP3 A29 EXP_RXP3 14
B30 RSVD4 HSIN3 A30 EXP_RXN3 14
SDVO_CTRLDATA B31 A31
14 SDVO_CTRLDATA PRSNT2_B31# GND
B32 GND RSVD5 A32

14 EXP_TXP4 B33 A33

*

C157 0.1uF 16V, X7R, +/-10% HSOP4 RSVD

14 EXP_TXN4 B34 A34

*
C159 0.1uF 16V, X7R, +/-10% HSON4 GND
B35 GND HSIP4 A35 EXP_RXP4 14
B36 GND HSIN4 A36 EXP_RXN4 14
14 EXP_TXP5 B37 A37
*

C169 0.1uF 16V, X7R, +/-10% HSOP5 GND

14 EXP_TXN5 B38 A38

*
C168 0.1uF 16V, X7R, +/-10% HSON5 GND
B39 GND HSIP5 A39 EXP_RXP5 14
B40 GND HSIN5 A40 EXP_RXN5 14
14 EXP_TXP6 B41 A41
*

C180 0.1uF 16V, X7R, +/-10% HSOP6 GND

14 EXP_TXN6 B42 A42

*
C177 0.1uF 16V, X7R, +/-10% HSON6 GND
B43 GND HSIP6 A43 EXP_RXP6 14
B44 GND HSIN6 A44 EXP_RXN6 14
14 EXP_TXP7 B45 A45
*

C191 0.1uF 16V, X7R, +/-10% HSOP7 GND

14 EXP_TXN7
* B46 HSON7 GND A46
C190 0.1uF 16V, X7R, +/-10% B47 A47
GND HSIP7 EXP_RXP7 14
14 GMCH_EXP_EN_HDR B48 PRSNT2_B48# HSIN7 A48 EXP_RXN7 14
B49 GND GND A49

14 EXP_TXP8 B50 A50

*

C200 0.1uF 16V, X7R, +/-10% HSOP8 RSVD6

14 EXP_TXN8 B51 A51
*

C202 0.1uF 16V, X7R, +/-10% HSON8 GND

B52 GND HSIP8 A52 EXP_RXP8 14
B53 GND HSIN8 A53 EXP_RXN8 14
14 EXP_TXP9 B54 A54
*

B
C204 0.1uF 16V, X7R, +/-10% HSOP9 GND B
14 EXP_TXN9 B55 A55
*

C206 0.1uF 16V, X7R, +/-10% HSON9 GND

B56 GND HSIP9 A56 EXP_RXP9 14
B57 GND HSIN9 A57 EXP_RXN9 14
14 EXP_TXP10 B58 A58
*

C211 0.1uF 16V, X7R, +/-10% HSOP10 GND

14 EXP_TXN10 B59 A59
*

C208 0.1uF 16V, X7R, +/-10% HSON10 GND

B60 GND HSIP10 A60 EXP_RXP10 14
B61 GND HSIN10 A61 EXP_RXN10 14
14 EXP_TXP11 B62 A62
*

C216 0.1uF 16V, X7R, +/-10% HSOP11 GND

14 EXP_TXN11 B63 A63
*

C215 0.1uF 16V, X7R, +/-10% HSON11 GND

B64 GND HSIP11 A64 EXP_RXP11 14
B65 GND HSIN11 A65 EXP_RXN11 14
14 EXP_TXP12 B66 A66
*

C217 0.1uF 16V, X7R, +/-10% HSOP12 GND

14 EXP_TXN12 B67 A67
*

C218 0.1uF 16V, X7R, +/-10% HSON12 GND

B68 GND HSIP12 A68 EXP_RXP12 14
B69 GND HSIN12 A69 EXP_RXN12 14
14 EXP_TXP13 B70 A70
*

C222 0.1uF 16V, X7R, +/-10% HSOP13 GND

14 EXP_TXN13 B71 A71
*

C220 0.1uF 16V, X7R, +/-10% HSON13 GND

B72 GND HSIP13 A72 EXP_RXP13 14
B73 GND HSIN13 A73 EXP_RXN13 14
14 EXP_TXP14 B74 A74
*

C229 0.1uF 16V, X7R, +/-10% HSOP14 GND

14 EXP_TXN14 B75 A75
*

C228 0.1uF 16V, X7R, +/-10% HSON14 GND

B76 GND HSIP14 A76 EXP_RXP14 14
B77 GND HSIN14 A77 EXP_RXN14 14
14 EXP_TXP15 B78 A78
*

C238 0.1uF 16V, X7R, +/-10% HSOP15 GND

14 EXP_TXN15 B79 A79
*

C237 0.1uF 16V, X7R, +/-10% HSON15 GND

B80 GND HSIP15 A80 EXP_RXP15 14
B81 PRSNT2_B81# HSIN15 A81 EXP_RXN15 14
B82 RSVD7 GND A82

Slot-PCIE-16X
All AC Coupling caps. should be placed within 250 mils of the connector

A A

FOXCONN PCEG
Title
PCI Express x16 Gfx Slot
Size Document Number Rev
C G41M01 A

Date: Tuesday, September 16, 2008 Sheet 22 of 38

5 4 3 2 1
 5 4 3 2 1

D D

L7
RED L4 5V_SYS
14 RED

*
5V_SYS 5V_SYS 100nH
82nH@100MHz

*
C32 R33 C25 C3
C65 C110 1 2 3D3V_SYS * 3.3pF *150
* 22pF
* 10pF F1
* 0.1uF
16V, Y5V, +80%/-20%
* 0.1uF
16V, Y5V, +80%/-20% D3
50V, NPO, +/-0.25pF+/ -1% 50V, NPO, +/-5% 50V, NPO, +/-5% Fuse 1.5A

BAV99
Dummy

L8
L_RED
EMI cap. for RGB layer change GREEN L5 L_GREEN
14 GREEN

*
L_BLUE
100nH
82nH@100MHz
C40 R38 C26 C7 VGA
*

3
VGA
1 2 3D3V_SYS
* 3.3pF 150
50V, NPO, +/-0.25pF+/ -1% * 22pF
50V, NPO, +/-5% * 10pF
50V, NPO, +/-5% 5V_DDCA_CLK 15 SCL GND 5
RGB routing 5V_DDCA_DATA 10 GND
C
1. from GMCH to the first 150 ohm resistor: 7.5 mils(min. 6 mils spacing ) D9 14 VSYNC ID0 4 C
9 NC
2. from the first 150 ohm res. to the second 150 ohm resistor: 4 mils BAV99 13 HSYNC B 3
3. from the second 150 ohm resistor to connector: 4 mils 8 GND
12 SDA G 2
4. spacing minimum 6 mils, 30 mils spacing is recommended 7 GND

16V, Y5V, +80%/-20%

5. R,G,B should be length matched to 700 mils, max. length is 8400 mils 11 ID1 R 1
6 GND
6. R,G,B signals should be ground referenced L9 * C34
0.1uF
BLUE L6 CONN-VGA

16
17
14 BLUE

*
100nH
82nH@100MHz
C41 R39 C27 C4
*

3
1 2 3D3V_SYS
* 3.3pF 150
50V, NPO, +/-0.25pF+/ -1% * 22pF
50V, NPO, +/-5% * 10pF
50V, NPO, +/-5%
3D3V_SYS 5V_SYS
D10
BAV99

RN12
2
4
6
8

2.2K
+/-5% The 150 Ohm resistors near VGA connector and
* 13
5
7

minimizing length to filter. The filters to VGA

connector maximum distance 800 mils.

3D3V_SYS
VSYNC_S

HSYNC_S
B B
D11
BAV99
1 2 5V_SYS
3

Q3
*

DDCA_CLK 2N7002 R21 +/-1% 5V_DDCA_CLK

14 DDCA_CLK
100 Ohm

Q2
*

DDCA_DATA 2N7002 R22 +/-1%5V_DDCA_DATA

14 DDCA_DATA
100 Ohm
3

1 2 5V_SYS
D7
BAV99

14 VSYNC
VSYNC R24
+/-5% * 0
Reserved
VSYNC_S
3

C6
*

R20
+/-5%
0
Reserved
1 2 3D3V_SYS * 10pF
50V, NPO, +/-5%
D2 Dummy
BAV99

A A

For EMI C15,C26 Near by the connector

*

Place between VGA port and Parallel port HSYNC R23 0 HSYNC_S
14 HSYNC
+/-5% Reserved
3

C5
1 2 3D3V_SYS * 10pF
50V, NPO, +/-5% FOXCONN PCEG
D1 Dummy Title
BAV99
VGA Connector
Size Document Number Rev
C G41M01 A

Date: Tuesday, September 16, 2008 Sheet 23 of 38

5 4 3 2 1
 5 4 3 2 1

GPIO[39:36,23:21,19,7:0]: default as inputs and should be

pulled up to Vcc3_3 if unused.
GPIO[31:29,15:8]: default as inputs and should be pulled up to
VccSus3_3 if unused.

double check unused GPIO

pins

SIO PME change to GPIO8

UI1F
UI1C
ICH7
ICH7
D 28,34 L_AD[3..0] Need to Checked D
DMI_TXN0 V26 DMI0RXN USBP0N F1 USBP0N AA5 LDRQ1*/GPIO23 GPIO0/BM_BUSY* AB18 ICH7_GPIO0
14 DMI_TXN0 USBN0 37
DMI_TXP0 V25 DMI0RXP USBP0P F2 USBP0P L_AD0 AA6 LAD0 GPIO6 AC21 ICH7_GPIO6
14 DMI_TXP0 USBP0 37
DMI_RXN0 C305 0.1uF 16V, X7R, +/-10% U28 DMI0TXN USBP1N G4 USBP1N L_AD1 AB5 LAD1 GPIO7 AC18 ICH7_GPIO7

** ** ** **
14 DMI_RXN0 USBN1 37

LPC
DMI_RXP0 C307 0.1uF 16V, X7R, +/-10% DMI_RXP0_ICH U27 DMI0TXP USBP1P G3 USBP1P L_AD2 AC4 LAD2 GPIO8 E21 L_PMEJ
14 DMI_RXP0 DMI_TXN1 USBP2N USBP1 37 L_AD3 ICH7_GPIO9 L_PMEJ 34
14 DMI_TXN1 Y26 DMI1RXN USBP2N H1 USBN2 27 Y6 LAD3 GPIO9 E20 P66DET 25
DMI_TXP1 Y25 DMI1RXP USBP2P H2 USBP2P AC3 LDRQ0* GPIO10 A20 ICH7_GPIO10
14 DMI_TXP1 USBP2 27 34 L_DRQ0J 1D8V_GPIO10 11
DMI_RXN1 C310 0.1uF 16V, X7R, +/-10% W28 DMI1TXN USBP3N J4 USBP3N AB3 LFRAME* GPIO12 F19 LAN_PMEJ
14 DMI_RXN1 USBN3 27 28,34 L_FRAMEJ LAN_PMEJ 31

DMI
DMI_RXP1 C312 0.1uF 16V, X7R, +/-10% DMI_RXP1_ICHW27 DMI1TXP USBP3P J3 USBP3P GPIO13 E19 ICH7_GPIO13

**
14 DMI_RXP1 DMI_TXN2 USBP4N USBP3 27 R256 33+/-5% ICH7_GPIO14 GTL_GPIO13 12
14 DMI_TXN2 AB26 DMI2RXN USBP4N K1 USBN4 37 32 ICH_BCLK U1 ACZ_BCLK GPIO14 R4 1D8V_GPIO14 11
DMI_TXP2 AB25 DMI2RXP USBP4P K2 USBP4P R251 33 +/-5% R5 ACZ_RST* GPIO15 E22 BIOS_WPJ
14 DMI_TXP2 USBP4 37 32 ICH_RSTJ

AUDIO
DMI_RXN2 C315 0.1uF 16V, X7R, +/-10% USBP5N Need to Checked
14 DMI_RXN2 AA28 DMI2TXN USBP5N L4 USBN5 31 T2 ACZ_SDI_0 GPIO16/DPRSLPVR AC22
DMI_RXP2 C313 0.1uF 16V, X7R, +/-10% DMI_RXP2_ICH
AA27 DMI2TXP USBP5P L5 USBP5P T3 ACZ_SDI_1 GPIO18/STPPCI* AC20
14 DMI_RXP2 DMI_TXN3 USBP6N USBP5 31
14 DMI_TXN3 AD25 DMI3RXN USBP6N M1 T1 ACZ_SDI_2 GPIO20/STPCPU* AF21

**
DMI_TXP3 USBP6P USBN6 37 32 ICH_SDIN2 R257 33 +/-5%
14 DMI_TXP3 AD24 DMI3RXP USBP6P M2 T4 ACZ_SDOUT GPIO24 R3

*
DMI_RXN3 C331 0.1uF 16V, X7R, +/-10% USBP7N USBP6 37 32 ICH_SDOUT R253 33 +/-5%
14 DMI_RXN3 AC28 DMI3TXN USBP7N N4 USBN7 31 32 ICH_SYNC R6 ACZ_SYNC GPIO25 D20 R221 1K Reserved
DMI_RXP3 C338 0.1uF 16V, X7R, +/-10% DMI_RXP3_ICH
AC27 DMI3TXP USBP7P N3 USBP7P AC1 CLK14 EL_RSVD/GPIO26 A21 +/-5% ICH_GPIO26
14 DMI_RXP3 USBP7 31 7 CK_14M_ICH GTL_GPIO26 12

USB
EL_STATE0/GPIO27 B21

EPROM
W1 EE_CS EL_STATE1/GPIO28 E23
29 HSI_N0 F26 PERN_1 OC0* D3 W3 EE_DIN GPIO32/CLKRUN* AG18
29 HSI_P0 F25 PERP_1 OC1* C4 Y2 EE_DOUT GPIO33/AZ_DOCK_EN* AC19 Board_ID0 28
HSO_N0_SLOT C276 0.1uF 16V, X7R, +/-10% E28 PETN_1 OC2* D5 ICH_BCLK Y1 EE_SHCLK GPIO34/AZ_DOCK_RST* U2 Board_ID1 28
29 HSO_N0_SLOT
** **

HSO_P0_SLOT C280 0.1uF 16V, X7R, +/-10% USB_OCJ_FRONT 37

29 HSO_P0_SLOT E27 PETP_1 OC3* D4 GPIO35 AD21
H26 PERN_2 OC4* E5 V3 LAN_CLK GPIO38 AD20 ICH7_GPIO38
31 HSI_N2_LAN Board_ID2 28Need to Checked
H25 PERP_2 OC5*/GPIO29 C3 C308 U3 LAN_RSTSYNC GPIO39 AE20 ICH7_GPIO39
31 HSI_P2_LAN

*
HSO_N2
31 HSO_N2_LAN
31 HSO_P2_LAN
C284
C285
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10% HSO_P2
G28
G27
PETN_2
PETP_2
OC6*/GPIO30
OC7*/GPIO31
A2
B3 USB_OCJ_BACK 31
* 22pF
50V, NPO, +/-5%
R220
10K
ICH_LAN_RSTJ
+/-5%
C19
U5
LAN_RST*
LAN_RXD0
CPUPWRGD_GPIO49 AG24 CPU_PWRG 12
PERN_3 LAN_RXD1 THRM* ICH_THRM_UP

LAN
K26 V4 AF20 ICH_THRM_UP 12,34
K25 PERP_3 T5 LAN_RXD2 VRMPWRGD AD22 ICH_VRMPWRGD_UP

MISC
J28 PETN_3 USBRBIAS D1 USBRBIAS_ICH R243 22.6 U7 LAN_TXD0 MCH_SYNC* AH20 ICH_SYNCJ 14
PETP_3 USBRBIAS* LAN_TXD1 PWRBTN*

PCI-EXPRESS
J27 D2 Dummy V6 C23 PWRBTNJ 34
M26 PERN_4 V7 LAN_TXD2 RI* A28 ICH_RIJ_PU
LPCPDJ ICH_RIJ_PU 36
M25 PERP_4 SUS_STAT* A27 LPCPDJ 28
L28 PETN_4 ICH_RTCX1 AB1 RTCX1 SUSCLK C20 TP_SUSCLK VCCRTC

RTC
TP42
L27 PETP_4 CLK48 B2 CK_48M_ICH ICH_RTCX2 AB2 RTCX2 SYS_RST* A22
CK_48M_ICH 7 RTCRSTJ PLTRSTJ ICH_SYS_RSTJ 7,8,12
P26 PERN_5 25 RTCRSTJ AA3 RTCRST* PLTRST* C26 PLTRSTJ 14,22,28,34
P25 PERP_5 WAKE* F20 WAKEJ
USBRBIAS connection SMB_ALERT_PU INTRUDERJ WAKEJ 22,29 R270
C N28 PETN_5 B23 SMBALERT*/GPIO11 INTRUDER* Y5 C
N27 PETP_5 5 mils width, length no longer than 500 mils C22 SMBCLK PWROK AA4 330K
Trace tied together close to pins. 22,29,30,35 SMB_CLK_RESUME NB_RSMRSTJ PWRGD_3V 14,34 +/-5%
T25 PERN_6 22,29,30,35 SMB_DATA_RESUME B22 SMBDATA RSMRST* Y4
PERP_6 SMALERT_ICH LINKALERT* INTVRMEN INTVRMEN

SMB
T24 A26 W4
R28 PETN_6 SMLINK0 B25 SMLINK0 SPKR A19 SPKR
SPKR 8 check pull-up resistor
1D5V_PE_ICH R27 PETP_6 SMLINK1 A25 SMLINK1
SLP_S3* B24 SLP_S3J 34
R227 24.9 DMI_COMP_ICH C25 DMI_ZCOMP ICH_SPI_MOSI P5 SPI_MOSI SLP_S4* D23
+/-1% ICH_SPI_MISO SLP_S4J 11
DMI_IRCOMP SPI_MISO SLP_S5*

SPI
D25 P2 F22 TP44
ICH_SPI_CSJ P6 SPI_CS*
DMI compensation CK_PE_100M_N_ICH AE28 DMI_CLKN ICH_SPI_CLK R2 SPI_CLK TP0/BATLOW* C21 ICH_BATLOW_PU
5 mils width, 7 mils spacing 7 CK_PE_100M_N_ICH
CK_PE_100M_P_ICH AE27 DMI_CLKP 2 of 6 TP45 SPI_ARB P1 SPI_ARB TP1/DPRSTP* AF24
Place the resistor within 500 mils of ICH7 7 CK_PE_100M_P_ICH TP46
TP2/DPSLP* AH25 TP47
TP3 TP_ICH7_F21
1 ? 4 of 6 F21 TP43

1 ?
3D3V_SB

*
7,9,12 VRMPWRGD R291 0 Dummy ICH_VRMPWRGD_UP
+/-5%
R312

1uF C371
3D3V_SYS
*R285 *1K

1
3D3V_SB
100KOhm
+/-1% * +/-5% Need Check??
RN32

10V, Y5V, +80%/-20%

*
2
*
1
3
2
4 SMALERT_ICH
Dummy R310
0
+/-5%
RN39 SMLINK0
5 6
ICH7_GPIO7
ICH_VRMPWRGD_UP
*
1
3
2
4
7 8 SMLINK1
34 RSMRSTJ
RSMRSTJ E C
Q23
NB_RSMRSTJ

ICH_THRM_UP 10K MMBT3906

ICH7_GPIO6
5
7
6
8 +/-5% Dummy *R311
10K

B
+/-5%
10K
+/-5% 3D3V_SB
R320
RN31
*

*
B B
ICH7_GPIO0 R281 10K +/-5%
*
1
3
2 L_PMEJ
4
3D3V_SB
5 6 SMB_ALERT_PU 4.7K

1
7 8 ICH_BATLOW_PU VCCRTC
*

ICH7_GPIO39 R399 10K +/-5% +/-5%

10K Dummy 3
*
+/-5% INTRUDERJ R287 1M
+/-5% D26
BAV99

A 2
3D3V_SB 3D3V_SB Dummy
D25
Dummy
**

R57 10K +/-5% LAN_PMEJ

Chassis Intruder Header 1K WAKEJ LS4148-F
R98 +/-5%

C
* *

INTR ICH7_GPIO9 R222 10K +/-5%

INTRUDERJ Dummy
1
2 SPI_SOCKET_1 *R304
2.2K
LPCPDJ R223 10K +/-5% +/-5%
Header_1X2 Use 3D3V_SYS or not Dummy Dummy
1 VCC 8
Steven Sun Update 2007.03.28 CS
2 DO 7
HOLD
3 WP CLK 6

4 GND DIO 5
Use 3D3V_SYS or not
3D3V_SB W25X80VDAIZ

ICH_RTCX2
7
5
3
1 *

ICH_RTCX1 close to ICH7 RN46 Use 3D3V_SYS or not

10K
3D3V_SB
+/-5%
*

R272 10M
+/-5%
8
6
4
2

A A
X3 XTAL-32.768kHz X3_1 16V, Y5V, +80%/-20%
2 1 3D3V_SB C365 0.1uF *R318
10K
**

16V, Y5V, +80%/-20% +/-5%

Need to Apply C360 C361 C404 0.1uF SPI_SOCKET Reserved
4

* 12pF
* 12pF 8 VCC CS 1
ICH_SPI_CSJ
*

50V, NPO, +/-5% 50V, NPO, +/-5% Crystal Retainer ICH_SPI_HOLDJ 7 HOLD SPI_MISO R296 47 ICH_SPI_MISO
DO 2
**

ICH_SPI_CLK R252 47 +/-5% SPI_CLK 6 CLK +/-5% BIOS_WPJ

ICH_SPI_MOSI R249 47 +/-5% SPI_MOSI WP 3
5 DIO GND 4
This clip is for ICH7
32.768Khz Crystal clip. close to ICH7 within 100 mils Socket
FOXCONN PCEG
Assume Capastor CL value is 12.5 Title
SPI Population Options ICH7 -1
Size Document Number Rev
C G41M01 A

Date: Tuesday, September 16, 2008 Sheet 24 of 38

5 4 3 2 1
 5 4 3 2 1

UI1B 1
SATA_1 3D3V_SYS

ICH7 SATA_TXP0 C431 10nF 25V, X7R, +/-10% SATA_TXP0_C 2

** **
SATA_TXN0 C435 10nF 25V, X7R, +/-10% SATA_TXN0_C 3 8
PIDE_D0 AB15 DD0 SATA0RXN AF3 SATA_RXN0 4
PIDE_D1 AE14 DD1 SATA0RXP AE3 SATA_RXP0 SATA_RXN0 C448 10nF 25V, X7R, +/-10% SATA_RXN0_C 5 9
PIDE_D2 AG13 DD2 SATA0TXN AG2 SATA_TXN0 SATA_RXP0 C452 10nF 25V, X7R, +/-10% SATA_RXP0_C 6
PIDE_D3 SATA0TXP SATA_TXP0
D
PIDE_D4
AF13
AD14
DD3
DD4 RSVD/SATA1RXN
AH2
AE5 SATA_RXN1
7
SATA_3 *R367
8.2K *R366
4.7K D
PIDE_D5 AC13 DD5 RSVD/SATA1RXP AD5 SATA_RXP1 1 CONN-SATA +/-5% +/-5%
PIDE_D6 AD12 DD6 RSVD/SATA1TXN AG4 SATA_TXN1 SATA_TXP1 C418 10nF 25V, X7R, +/-10% SATA_TXP1_C 2

** **
PIDE_D7 AC12 DD7 RSVD/SATA1TXP AH4 SATA_TXP1 SATA_TXN1 C425 10nF 25V, X7R, +/-10% SATA_TXN1_C 3 8
PIDE_D8 AE12 DD8 SATA2RXN AF7 SATA_RXN2 4
PIDE_D9 SATA_RXP2 SATA_RXN1 SATA_RXN1_C

SATA
AF12 DD9 SATA2RXP AE7 C451 10nF 25V, X7R, +/-10% 5 9
PIDE_D10 AB13 DD10 SATA2TXN AG6 SATA_TXN2 SATA_RXP1 C455 10nF 25V, X7R, +/-10% SATA_RXP1_C 6 PIDE
PIDE_D11 AC14 DD11 SATA2TXP AH6 SATA_TXP2 7 P_IDERSTJ 1 2
PIDE_D12 AF14 DD12 IDE RSVD/SATA3RXN AD9 SATA_RXN3 PIDE_D7 3 4 PIDE_D8
PIDE_D13 AH13 DD13 RSVD/SATA3RXP AE9 SATA_RXP3 CONN-SATA PIDE_D6 5 6 PIDE_D9
PIDE_D14 AH14 DD14 RSVD/SATA3TXN AG8 SATA_TXN3 PIDE_D5 7 8 PIDE_D10
PIDE_D15 AC15 DD15 RSVD/SATA3TXP AH8 SATA_TXP3 PIDE_D4 9 10 PIDE_D11
SATACLKN AF1 CK_SATA_100M_N_ICH PIDE_D3 11 12 PIDE_D12
CK_SATA_100M_N_ICH 7
PIDE_DAKJ AF16 DDACK* SATACLKP AE1 CK_SATA_100M_P_ICH PIDE_D2 13 14 PIDE_D13
CK_SATA_100M_P_ICH 7
PIDE_DREQ AE15 DDREQ PIDE_D1 15 16 PIDE_D14
PIDE_IORJ AF15 DIOR* PIDE_D0 17 18 PIDE_D15

*
PIDE_IOWJ AH15 DIOW* SATARBIASN AH10 SATARBIAS_ICH R286 27 19 X
PIDE_RDY AG16 IORDY AG10 +/-1% SATARBIAS connection PIDE_DREQ 21 22
SATARBIASP SATA_LED PIDE_IOWJ Cable detection
SATALED* AF18 5 mils width, length no longer than 500 mils 23 24
PIDE_A0 AH17 DA0 Trace tied together close to pins.
PIDE_IORJ 25 26 high: 40-conductor cable(ATA 33)
PIDE_A1 DA1 R280 10K PIDE_RDY low: 80-conductor cable(ATA 66/100)
AE17 GPIO21/SATA0GP AF19 3D3V_SYS 27 28

*
PIDE_A2 AF17 DA2 GPIO19/SATA1GP AH18 +/-5% PIDE_DAKJ 29 30
GPIO36/SATA2GP AH19 IRQ14 31 32
PIDE_CS1J AE16 DCS1* GPIO37/SATA3GP AE19 PIDE_A1 33 34
PIDE_CS3J PIDE_A0 PIDE_A2 P66DET 24
AD16 DCS3* 35 36
A20GATE AE22 A20GATE 34
PIDE_CS1J 37 38 PIDE_CS3J ?
A20M* AH28 A20MJ 12
PIDE_LED 39 40
IRQ14 AH16 IDEIRQ CPUSLP* AG27 CPU_SLPJ 12,34
SATA_2
IGNNE* C441
INIT3_3V*
AG22
AG21
IGNNEJ 12
SATA_TXP2 C433 10nF 25V, X7R, +/-10% SATA_TXP2_C
1
2
Header_2X20_K20
* 47nF *R368
10K

** **
HOST

INIT* AF22 SATA_TXN2 C436 10nF 25V, X7R, +/-10% SATA_TXN2_C 3 8 16V,X7R,+/-10%
Dummy +/-5%
INITJ 12
INTR AF25 INTR 12 4 HDD1
FERR* AG26 FERRJ SATA_RXN2 C444 10nF 25V, X7R, +/-10% SATA_RXN2_C 5 9
FERRJ 12
NMI AH24 SATA_RXP2 C446 10nF 25V, X7R, +/-10% SATA_RXP2_C 6
NMI 12
RCIN* AG23 KBRSTJ 34 7
SERIRQ AH21 SATA_4
SERIRQ 28,34
SMI* AF23 SMIJ 12 1 CONN-SATA
C STPCLK* AH22 SATA_TXP3 C432 10nF 25V, X7R, +/-10% SATA_TXP3_C 2 C
STPCLKJ 12

** **
3 of 6 THERMTRIP* AF26 THERMTRIPJ
THERMTRIPJ 12
SATA_TXN3 C437 10nF 25V, X7R, +/-10% SATA_TXN3_C 3 8 IDE data lines should be matched to strobes(IORJ, RDY)within +/- 250 mils,
strobes should be matched to their complement within +/- 10 mils
4
SATA_RXN3 C449 10nF 25V, X7R, +/-10% SATA_RXN3_C 5 9
1 ? SATA_RXP3 C453 10nF 25V, X7R, +/-10% SATA_RXP3_C 6
Reserved 7

CONN-SATA

*
R377 33 P_IDERSTJ
34 IDE_RSTJ +/-5%

C457
placed near IDE connector
3D3V_SB * 180pF
+/-5%

VCCRTC

FSB_VTT D20
1 width 20 mils
R112
3
VBAT D19 C A 2
3D3V_SYS
*

R277 62 THERMTRIPJ
B
+/-5% 1K
+/-1%
SD103AW BAT54C *R279
20K
B
+/-1%

C149
*R325 *R326
*

FERRJ
R276
+/-5%
62 R113
1K * 1uF
10V, X5R, +/-10%
10K
+/-5%
10K
+/-5%
+/-1% RTCRST
add 040808
C359
Place at ICH7 end of route
C356 * 1uF
10V, X5R, +/-10% PIDE_LED
+

* 1uF BAT1
1
D28

10V, Y5V, +80%/-20% 3

Dummy Battery Holder HDD_LEDJ 8
2
-

SATA_LED
BAT54A

BAT1_1

LITHIUM BATT

CR2032

Battery
Clear CMOS
For battery cell.
CLR_CMOS CLR_CMOS CMOS CLR_CMOS:2-3
1 1
RTCRSTJ 2
24 RTCRSTJ RTCRST 2
A 3 3 Clear (1-2) A

Header_1X3 Normal (2-3) Default Jumper_2P_Blu

FOXCONN PCEG
Title
ICH7 -2
Size Document Number Rev
C G41M01 A

Date: Tuesday, September 16, 2008 Sheet 25 of 38

5 4 3 2 1
 5 4 3 2 1

UI1E
ICH7
UI1D E4 VSS VSS A4
UI1A ICH7 1D5V_CORE
AG11 VSS VSS A23
C27 VSS VSS B1
ICH7 1D5V_CORE REF5V R14 VSS VSS B8
AD[31..0] R15 VSS VSS B11
AD[31..0] 30
A1 VCC1_5_A R16 VSS VSS B14
30 PAR PAR E10 PAR AD0 E18 AD0 AB10 VCC1_5_A V5REF AD17 R17 VSS VSS B17
30 DEVSELJ DEVSELJ A12 DEVSEL* AD1 C18 AD1 AB17 VCC1_5_A V5REF G10 R18 VSS VSS B20

1
7 CK_33M_ICH A9 PCICLK AD2 A16 AD2 AB7 VCC1_5_A REF5V_SUS T6 VSS VSS B26
30
30
PCIRSTJ
IRDYJ
0
* R219
IRDYJ +/-5%
B18
A7
PCIRST*
IRDY*
AD3
AD4
F18
E16
AD3
AD4
AB8
AB9
VCC1_5_A
VCC1_5_A
V5REF_SUS F6 VCCRTC L31
L0805 10uH
T12
T13
VSS
VSS
VSS
VSS
B28
C2
PMEJ B19 PME* AD5 A18 AD5 AC10 VCC1_5_A VCCRTC W5 1D5V_CORE T14 VSS VSS C6
30
30
PMEJ
SERRJ SERRJ
STOPJ
B10
F15
SERR*
STOP*
PCI AD6
AD7
E17
A17
AD6
AD7
AC17
AC6
VCC1_5_A
VCC1_5_A VCCUSBPLL C1
+/-20% T15
T16
VSS
VSS
VSS
VSS
D10
D13
30 STOPJ

2
30 LOCKJ
LOCKJ E11 PLOCK* AD8 A15 AD8 3D3V_SYS 3D3V_SYS AC7 VCC1_5_A T17 VSS VSS D18
30 TRDYJ TRDYJ F14 TRDY* AD9 C14 AD9 AC8 VCC1_5_A VCCSATAPLL AD2 U4 VSS VSS D21
D 30 PERRJ
PERRJ C9 PERR* AD10 E14 AD10 AD10 VCC1_5_A U12 VSS VSS D24 D
30 FRAMEJ FRAMEJ F16 FRAME* AD11 D14 AD11 C263 C352 AD6 VCC1_5_A VCCDMIPLL AG28 VCCDMIPLL 1D05V_SYS C358 C353 U13 VSS VSS E1

1
AD12
30 GNT0J E7 GNT0* AD13
B12
C13
AD12
AD13 * 0.1uF
* 0.1uF AE10
AE6
VCC1_5_A
VCC1_5_A VCC1_05 L11
* 10uF
10V, Y5V, +80%/-20% * 0.1uF Near AD2 U14
U15
VSS
VSS
VSS
VSS
E2
E8
30 GNT1J D16 GNT1* AD14 G15 AD14 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% AF10 VCC1_5_A VCC1_05 L12 16V, Y5V, +80%/-20% U16 VSS VSS E15

2
D17 GNT2* AD15 G13 AD15 AF5 VCC1_5_A VCC1_05 L14 U17 VSS VSS F3
F13 GNT3* AD16 E12 AD16 AF6 VCC1_5_A VCC1_05 L16 U24 VSS VSS F4
A14 GNT4*/GPIO48 AD17 C11 AD17 AF9 VCC1_5_A VCC1_05 L17 U25 VSS VSS F5
GNT5J D8 GNT5*/GPIO17 AD18 D11 AD18 AG5 VCC1_5_A VCC1_05 L18 U26 VSS VSS F12
AD19 A11 AD19 AG9 VCC1_5_A VCC1_05 M11 V2 VSS VSS F27
D7 REQ0* AD20 A10 AD20 AH5 VCC1_5_A VCC1_05 M18 V13 VSS VSS F28
30 PREQ0J
30 PREQ1J C16 REQ1* AD21 F11 AD21 AH9 VCC1_5_A VCC1_05 P11 V15 VSS VSS G1
30 PREQ2J C17 REQ2* AD22 F10 AD22 F17 VCC1_5_A VCC1_05 P18 V24 VSS VSS G5
30 PREQ3J E13 REQ3* AD23 E9 AD23 G17 VCC1_5_A VCC1_05 T11 V27 VSS VSS G2
30 PREQ4J A13 REQ4*/GPIO22 AD24 D9 AD24 H6 VCC1_5_A VCC1_05 T18 V28 VSS VSS G6
30 PREQ5J C8 GPIO1/REQ5* AD25 B9 AD25 H7 VCC1_5_A VCC1_05 U11 W6 VSS VSS G9
AD26 A8 AD26 J6 VCC1_5_A VCC1_05 U18 W24 VSS VSS G14
30 INTAJ A3 PIRQA* AD27 A6 AD27 J7 VCC1_5_A VCC1_05 V11 W25 VSS VSS G18
30 INTBJ B4 PIRQB* AD28 C7 AD28 1D5V_PE_ICH T7 VCC1_5_A VCC1_05 V12 W26 VSS VSS G21
30 INTCJ C5 PIRQC* AD29 B6 AD29 VCC1_05 V14 Y3 VSS VSS G24
30 INTDJ B5 PIRQD* AD30 E6 AD30 D26 VCC1_5_B VCC1_05 V16 Y24 VSS VSS G25
30 INTEJ G8 GPIO2/PIRQE* AD31 D6 AD31 D27 VCC1_5_B VCC1_05 V17 Y27 VSS VSS G26
30 INTFJ F7 GPIO3/PIRQF* D28 VCC1_5_B VCC1_05 V18 Y28 VSS VSS H3
30 INTGJ F8 GPIO4/PIRQG* C/BE0* B15 CBEJ0 E24 VCC1_5_B AA1 VSS VSS H4
CBEJ1 CBEJ0 30
30 INTHJ G7 GPIO5/PIRQH* C/BE1* C12 CBEJ1 30 E25 VCC1_5_B FSB_VTT AA24 VSS VSS H5
C/BE2* D12 CBEJ2 E26 VCC1_5_B V_CPU_IO AE23 AA25 VSS VSS H24
1 of 6 C/BE3* C15 CBEJ3 CBEJ2 30
F23 VCC1_5_B V_CPU_IO AE26 AA26 VSS VSS H27

POWER
CBEJ3 30
F24 VCC1_5_B V_CPU_IO AH26 3D3V_SYS AB4 VSS VSS H28
1 G22 VCC1_5_B AB6 VSS VSS J1
G23 VCC1_5_B VCC3_3 A5 AB11 VSS VSS J2
H22 VCC1_5_B VCC3_3 AA7 AB14 VSS VSS J5
GNT5J GNT4J BOOT H23 VCC1_5_B VCC3_3 AB12 AB16 VSS VSS J24
0 1 SPI J22 VCC1_5_B VCC3_3 AB20 AB19 VSS VSS J25
1 0 PCI J23 VCC1_5_B VCC3_3 AC16 AB21 VSS VSS J26
1 1 LPC 1D5V_CORE K22 VCC1_5_B VCC3_3 AD13 AB24 VSS VSS K24
VCCDMIPLL LRC Filter K23 VCC1_5_B VCC3_3 AD18 AB27 VSS VSS K27
L22 VCC1_5_B VCC3_3 AG12 AB28 VSS VSS K28
*

GNT5J R216 1K L23 VCC1_5_B VCC3_3 AG15 AC2 VSS VSS L13
+/-5% Reserved M22 VCC1_5_B VCC3_3 AG19 AC5 VSS VSS L15
L0805 1uH M23 VCC1_5_B VCC3_3 AH11 AC9 VSS VSS L24
L30 1 2 VCCDMIPLL N22 VCC1_5_B VCC3_3 B13 AC11 VSS VSS L25
+/-10% N23 VCC1_5_B VCC3_3 B16 AD1 VSS VSS L26
C364 C363 P22 VCC1_5_B VCC3_3 B27 AD3 VSS VSS M3

1
extra one 47uF(backside) in DG0.7
Rated at least 100mA
* 10uF
10V, Y5V, +80%/-20% * 10nF P23
R22
VCC1_5_B
VCC1_5_B
VCC3_3
VCC3_3
B7
C10
AD4
AD7
VSS
VSS
VSS
VSS
M4
M5
C Dummy 25V, X7R, +/-10% R23 VCC1_5_B VCC3_3 D15 AD8 VSS VSS M12 C

2
R24 VCC1_5_B VCC3_3 F9 AD11 VSS VSS M13
R25 VCC1_5_B VCC3_3 G11 AD15 VSS VSS M14
R26 VCC1_5_B VCC3_3 G12 AD19 VSS VSS M15
1D05V_SYS T22 VCC1_5_B VCC3_3 G16 AD23 VSS VSS M16
T23 VCC1_5_B VCC3_3 U6 3D3V_SB AE2 VSS VSS M17
Place LRC near pin AG28 T26 VCC1_5_B VCCSUS3_3 A24 AE4 VSS VSS M24
T27 VCC1_5_B VCCSUS3_3 C24 AE8 VSS VSS M27
T28 VCC1_5_B VCCSUS3_3 D19 AE11 VSS VSS M28
C291 C292 1D5V_CORE U22 VCC1_5_B VCCSUS3_3 D22 AE13 VSS VSS N1
* 0.1uF
* 1uF U23 VCC1_5_B VCCSUS3_3 E3 AE18 VSS VSS N2
10V, X5R, +/-10%

V22 VCC1_5_B VCCSUS3_3 G19 AE21 VSS VSS N5

16V, Y5V, +80%/-20%

VCC1_5_B LC Filter V23 VCC1_5_B VCCSUS3_3 K3 AE24 VSS VSS N6

W22 VCC1_5_B VCCSUS3_3 K4 AE25 VSS VSS N11
L29 0 W23 VCC1_5_B VCCSUS3_3 K5 AF2 VSS VSS N12
Y22 VCC1_5_B VCCSUS3_3 K6 AF4 VSS VSS N13
Near D28, T28,and AD28 Y23 VCC1_5_B VCCSUS3_3 L1 AF8 VSS VSS N14
L28 Dummy
0 1D5V_PE_ICH AA22 VCC1_5_B VCCSUS3_3 L2 AF11 VSS VSS N15
C346 C347 C302 C301 AA23 VCC1_5_B VCCSUS3_3 L3 AF27 VSS VSS N16
EC41 0.1uF 0.1uF 0.1uF 0.1uF C349 AB22 VCC1_5_B VCCSUS3_3 L6 AF28 VSS VSS N17

1
ICH7 Core decoupling caps. * 100uF
Dummy
16V, +/-20% * * * * * 10uF AB23
AC23
VCC1_5_B
VCC1_5_B
VCCSUS3_3
VCCSUS3_3
L7
M6
AG1
AG3
VSS
VSS
VSS
VSS
N18
N24
16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

AC24 VCC1_5_B VCCSUS3_3 M7 AG7 VSS VSS N25

2

AC25 VCC1_5_B VCCSUS3_3 N7 AG14 VSS VSS N26

AC26 VCC1_5_B VCCSUS3_3 P7 AG17 VSS VSS P12
AD26 VCC1_5_B VCCSUS3_3 R7 AG20 VSS VSS P13
Dummy Dummy AD27 VCC1_5_B VCCSUS3_3 V1 AG25 VSS VSS P14
AD28 VCC1_5_B VCCSUS3_3 V5 AH1 VSS VSS P15
VCCSUS3_3 W2 AH3 VSS VSS P3
1D5V_PE_ICH 3D3V_SYS VCCSUS3_3 W7 VSS P4
VSS P16
Place LC near pin D28 VCCSUS1_05 AA2 AH7 VSS VSS P17
C269 VCCSUS1_05 C28 AH23 VSS VSS P24
C273 0.1uF VCCSUS1_05 G20 AH27 VSS VSS P27

*
0.1uF
Reserved * 16V, Y5V, +80%/-20%
5 of 6
VCCSUS1_05
VCCSUS1_05
K7
Y7 AH12 VSS
VSS
VSS
P28
R1
5V_SB 3D3V_SB VSS R11
16V, Y5V, +80%/-20% VSS R12
VSS R13
1 ? 6 of 6
A

Place near B27 D21

* R195 Dummy
10
Place near D28 LS4148-F REF5V_SUS 3D3V_SB
+/-1%
C

B PCI-E decoupling caps. C246 REF5V_SUS

B

0.1uF
* 16V, Y5V, +80%/-20%
C309
0.1uF

place cap. near pin F6 * 16V, Y5V, +80%/-20%

within 40 mils
1D5V_CORE 1D5V_CORE
V5REF_SUS / 3D3V_SB Power Sequencing
Place near V1
C281 C283

*
0.1uF
* 10nF

Reserved 25V, X7R, +/-10% VCCRTC

16V, Y5V, +80%/-20% Reserved LAN decoupling caps. FSB_VTT FSB_VTT
double check in new CRB or DG

Place near A1 Place near C1 C354 C355 C314 C372

*
0.1uF
*
0.1uF
C357
*
0.1uF
* 1uF
10V, Y5V, +80%/-20%

1
5V_SYS 3D3V_SYS

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

3D3V_SB * 4.7uF
6.3V, X5R, +/-10%
3D3V_SYS
A

2
D24
R288 1D5V_CORE 1D5V_CORE
3D3V_SB 1K
Need to Check Change to Dummy

+/-1% LS4148-F
16V, Y5V, +80%/-20%

C311
C

C288 C293 C366 C376 0.1uF Place near W5

*
0.1uF
*
0.1uF
*
C287
10nF REF5V REF5V
* 0.1uF
* 1uF
10V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% Near AE23 and AE26 Place near AH26
Reserved Reserved C370 16V, Y5V, +80%/-20% Reserved
16V, Y5V, +80%/-20% 25V, X7R, +/-10% 0.1uF Reserved
RTC decoupling caps.
* 16V, Y5V, +80%/-20%
CPU decoupling caps.
Place near AH5 Place near AH9 Place near U6
place cap. near pin AD17/G10
Near L1 and K3 within 40 mils
Place near E3
V5REF / 3D3V_SYS Power Sequencing Audio decoupling caps. 3D3V_SYS
3D3V_SYS 1D5V_CORE
A USB decoupling caps. A

3D3V_SYS

VCCDMIPLL C368 C367 C266 C264 C252

* 0.1uF
* 0.1uF
*
0.1uF
*
0.1uF
*
0.1uF

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% C369
C362 0.1uF
* 10nF
* 16V, Y5V, +80%/-20%
25V, X7R, +/-10% Place near AH11 Place near AD2
Dummy
FOXCONN PCEG
Place near AG28
Place near AG15/AB12 Place near A5, B7, C10 Title
ICH7 -3
DMI decoupling caps. SATA decoupling caps. PCI decoupling caps. Size Document Number Rev
IDE decoupling caps. Custom G41M01 A

Date: Tuesday, September 16, 2008 Sheet 26 of 38

5 4 3 2 1
 5 4 3 2 1

Rear Dual USB Connector

D D

SVCC2
U3
USBN3 1 6 USBP3
5V_DUAL
2 5
C31 EC16
* 0.1uF * 470uF
16V, +/-20%
USBN2 3 4 USBP2

16V, Y5V, +80%/-20% IP4220CZ6

Reserved

C C

USB

RN2 1 V0
24 USBP3
USBP3
USBN3
2
4
* 13 2
3
-D0 5 6 7 8
24 USBN3 USBP2 +D0
24 USBP2 6 5 4 G0
USBN2 8 7
24 USBN2
5 V1
6 1 2 3 4
0 -D1
7 +D1
+/-5% 8

CG1
CG2
CG3
CG4
L3 G1
1 5
CONN-USBx2

9
10
11
12
2 6 Reserved

3 7

4 8
B B
Filter 100MHz
Dummy

5V_SYS

for 3D3V_SB / Front panel USB

5V_DUAL 5V_DUAL

S
G AOD452
11 PWOK+
5V_SYS 5V_SB

FDS8958A D Q6

8 1
D1

S1

7 2 PWOK+
D1

G1

A A
6 3
D2

S2

5 4
D2

G2

Q12 FOXCONN PCEG

Title
Id(N MOS) max= 6.9A
Id(P MOS) max= -5A REAR USB
Size Document Number Rev
Custom G41M01 A

Date: Tuesday, September 16, 2008 Sheet 27 of 38

5 4 3 2 1
 5 4 3 2 1

3D3V_SYS

*R282
1K *R254
1K *R290
1K 3D3V_SYS
3D3V_SYS 3D3V_SYS
MH4 MH3 MH1 MH5 MH6 MH2
+/-5% +/-5% +/-5% Mounting Hole Mounting Hole Mounting Hole Mounting Hole Mounting Hole Mounting Hole

Reserved Reserved @3JACK

6
5

6
5

6
5

6
5

6
5

6
5
D D
7 4 7 4 7 4 7 4 7 4 7 4
C406 C125 8 3 8 3 8 3 8 3 8 3 8 3
Board_ID2 C253 10nF 10nF
Board_ID1
Board_ID2
Board_ID1
24
24
*
4.7uF * *
25V, X7R, +/-10% 25V, X7R, +/-10%
9 2 9 2 9 2 9 2 9 2 9 2

1
Board_ID0 Board_ID0 24 Dummy Dummy Dummy
mh40x80_8 mh40x80_8 mh40x80_8 mh40x80_8 mh40x80_8 mh40x80_8

*R283
1K *R255
1K *R289
1K
GND_AUDIO GND_AUDIO GND_AUDIO

+/-5% +/-5% +/-5%

12V_SYS
Dummy Dummy @6JACK

T2 T4
1 1
2 2

T1 T1

C
TPM HEADER 12V_SYS
C

5V_SYS
3D3V_SYS
T1 T3
TPM 1 1
R333 2 2
1 2 0
@TCM
7 CK_33M_TPM LCLK GND * +/-5% T1 T1
24,34 L_FRAMEJ 3 LFRAMEn KEY

14,22,24,34 PLTRSTJ 5 LRESETn NC_3 6

L_AD3 7 8 L_AD2
24,34 L_AD3 LAD3 LAD2 L_AD2 24,34
9 10 L_AD1
VDD LAD1 L_AD1 24,34
L_AD0 11 12
24,34 L_AD0 LAD0 GND R363
*

3D3V_SYS R347@TCM 13 14 @TCM 3D3V_SYS

NC_1 NC_4

3D3V_SB 1K 15 NC_2 SERIRQ 16 1K SERIRQ 25,34 FD3 FD1 FD2 FD4

+/-5% 17 18 +/-5% FMARK FMARK FMARK FMARK
GND CLKRUNin FD40 FD40 FD40 FD40
B 24 LPCPDJ 19 LPCPDn NC_5 20 B

1
Header_2X10_4 (TPM)

Need check?

A A

FOXCONN PCEG
Title
BOARD ID
Size Document Number Rev
Custom G41M01 A

Date: Tuesday, September 16, 2008 Sheet 28 of 38

5 4 3 2 1
 5 4 3 2 1

D D

3D3V_SB 3D3V_SYS 12V_SYS

12V_SYS 3D3V_SYS
12V_SYS 3D3V_SYS 3D3V_SB

C124 C128
PCI-E1_1X 0.1uF 0.1uF

1
C111
B1
B2
12V
12V
PRSNT1#
12V
A1
A2
* 0.1uF * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20%
C B3 A3 C

2
RSVD_1 12V 25V, X7R, +/-10%
B4 GND GND A4
22,24,30,35 SMB_CLK_RESUME B5 SMCLK JTAG2 A5
22,24,30,35 SMB_DATA_RESUME B6 SMDAT JTAG3 A6
B7 GND JTAG4 A7
B8 3.3V JTAG5 A8
B9 JTAG1 3.3V A9
B10 3.3VAUX 3.3V A10
22,24 WAKEJ B11 WAKE# PWRGD A11 PCIE_RSTJ 22
KEY

B12 RSVD_2 GND A12

B13 GND REFCLK+ A13 CK_PE_100M_P_1PORT_2 7
24 HSO_P0_SLOT B14 HSOP0 REFCLK- A14 CK_PE_100M_N_1PORT_2 7
24 HSO_N0_SLOT B15 HSON0 GND A15
B16 GND HSIP0 A16 HSI_P0 24
B17 PRSNT2# HSIN0 A17 HSI_N0 24
B18 GND GND A18

Slot-PCIE-1X

PCI-E x1 Slot 2

B B

A A

FOXCONN PCEG
Title
PCI Express x1 Slot
Size Document Number Rev
Custom G41M01 A

Date: Tuesday, September 23, 2008 Sheet 29 of 38

5 4 3 2 1
 5 4 3 2 1

5V_SYS 5V_SYS

3D3V_SYS 3D3V_SYS 3D3V_SYS 3D3V_SYS

-12V_SYS 5V_SYS 12V_SYS -12V_SYS 5V_SYS 12V_SYS

Note: 20-24 mils PCI1 Note: 20-24 mils PCI2

B1 -12V TRST# A1 B1 -12V TRST# A1
B2 TCK +12V A2 B2 TCK +12V A2
B3 GND1 TMS A3 B3 GND1 TMS A3
B4 TDO TDI A4 B4 TDO TDI A4
B5 +5V1 +5V2 A5 B5 +5V1 +5V2 A5
B6 A6 INTBJ INTBJ 26 B6 A6 INTCJ INTCJ 26
INTCJ +5V3 INTA# INTDJ INTDJ +5V3 INTA# INTAJ
26 INTCJ B7 INTB# INTC# A7 INTDJ 26 26 INTDJ B7 INTB# INTC# A7 INTAJ 26
26 INTAJ INTAJ B8 A8 26 INTBJ INTBJ B8 A8
INTD# +5V4 INTD# +5V4
D
B9 PRSNT1# RSV1 A9 B9 PRSNT1# RSV1 A9 D
B10 RSV2 +5V5 A10 B10 RSV2 +5V5 A10
B11 PRSNT2# RSV3 A11 B11 PRSNT2# RSV3 A11
B12 GND2 GND3 A12 B12 GND2 GND3 A12
B13 A13 3D3V_SB B13 A13 3D3V_SB
GND4 GND5 GND4 GND5
B14 RSV4 SB3V A14 B14 RSV4 SB3V A14
B15 GND6 RESET# A15 PCIRSTJ 26 B15 GND6 RESET# A15 PCIRSTJ 26
7 CK_33M_PCI1 B16 CLK +5V6 A16 7 CK_33M_PCI2 B16 CLK +5V6 A16
B17 GND7 GNT# A17 GNT0J 26 B17 GND7 GNT# A17 GNT1J 26
PREQ0J B18 A18 PREQ1J B18 A18
REQ# GND8 REQ# GND8
B19 +5V7 PCI_PME# A19 PMEJ 26 B19 +5V7 PCI_PME# A19 PMEJ 26
AD31 B20 A20 AD30 AD31 B20 A20 AD30
AD29 AD(31) AD(30) AD29 AD(31) AD(30)
B21 AD(29) +3.3V1 A21 B21 AD(29) +3.3V1 A21
B22 A22 AD28 B22 A22 AD28
AD27 GND9 AD(28) AD26 AD27 GND9 AD(28) AD26
B23 AD(27) AD(26) A23 B23 AD(27) AD(26) A23
AD25 B24 A24 AD25 B24 A24
AD(25) GND10 AD24 AD(25) GND10 AD24
B25 +3.3V2 AD(24) A25 B25 +3.3V2 AD(24) A25
CBEJ3 B26 A26 IDSEL0 CBEJ3 B26 A26 IDSEL3
26 CBEJ3 C/BE#(3) IDSEL 26 CBEJ3 C/BE#(3) IDSEL
AD23 B27 A27 AD23 B27 A27
AD(23) +3.3V3 AD22 AD(23) +3.3V3 AD22
B28 GND11 AD(22) A28 B28 GND11 AD(22) A28
AD21 B29 A29 AD20 AD21 B29 A29 AD20
AD19 AD(21) AD(20) AD19 AD(21) AD(20)
B30 AD(19) GND12 A30 B30 AD(19) GND12 A30
B31 A31 AD18 B31 A31 AD18
AD17 +3.3V4 AD(18) AD16 AD17 +3.3V4 AD(18) AD16
B32 AD(17) AD(16) A32 B32 AD(17) AD(16) A32
B33 C/BE#(2) +3.3V5 A33 B33 C/BE#(2) +3.3V5 A33
26 CBEJ2 B34 A34 FRAMEJ 26 CBEJ2 B34 A34 FRAMEJ
GND13 FRAME# FRAMEJ 26 GND13 FRAME# FRAMEJ 26
IRDYJ B35 A35 IRDYJ B35 A35
26 IRDYJ IRDY# GND14 26 IRDYJ IRDY# GND14
B36 A36 TRDYJ B36 A36 TRDYJ
+3.3V6 TRDY# TRDYJ 26 +3.3V6 TRDY# TRDYJ 26
DEVSELJ B37 A37 DEVSELJ B37 A37
26 DEVSELJ DEVSEL# GND15 26 DEVSELJ DEVSEL# GND15
B38 A38 STOPJ B38 A38 STOPJ
GND16 STOP# STOPJ 26 GND16 STOP# STOPJ 26
LOCKJ B39 A39 LOCKJ B39 A39
26 LOCKJ LOCK# +3.3V7 26 LOCKJ LOCK# +3.3V7
PERRJ B40 A40 PSCLK PERRJ B40 A40 PSCLK
26 PERRJ PERR# SDONE PSDATA 26 PERRJ PERR# SDONE PSDATA
B41 +3.3V8 SBO# A41 B41 +3.3V8 SBO# A41
SERRJ B42 A42 SERRJ B42 A42
26 SERRJ SERR# GND17 26 SERRJ SERR# GND17
B43 A43 PAR B43 A43 PAR
+3.3V9 PAR PAR 26 +3.3V9 PAR PAR 26
CBEJ1 B44 A44 AD15 CBEJ1 B44 A44 AD15
26 CBEJ1 AD14 C/BE#(1) AD(15) 26 CBEJ1 AD14 C/BE#(1) AD(15)
B45 AD(14) +3.3V10 A45 B45 AD(14) +3.3V10 A45
B46 A46 AD13 B46 A46 AD13
AD12 GND18 AD(13) AD11 AD12 GND18 AD(13) AD11
C B47 AD(12) AD(11) A47 B47 AD(12) AD(11) A47 C
AD10 B48 A48 AD10 B48 A48
AD(10) GND19 AD9 AD(10) GND19 AD9
B49 GND20 AD(9) A49 B49 GND20 AD(9) A49

AD8 B52 A52 CBEJ0 AD8 B52 A52 CBEJ0

AD(8) C/BE#(0) CBEJ0 26 AD(8) C/BE#(0) CBEJ0 26
AD7 B53 A53 AD7 B53 A53
AD(7) +3.3V11 AD6 AD(7) +3.3V11 AD6
B54 +3.3V12 AD(6) A54 B54 +3.3V12 AD(6) A54
AD5 B55 A55 AD4 AD5 B55 A55 AD4
AD3 AD(5) AD(4) AD3 AD(5) AD(4)
B56 AD(3) GND21 A56 B56 AD(3) GND21 A56
B57 A57 AD2 B57 A57 AD2
AD1 GND22 AD(2) AD0 AD1 GND22 AD(2) AD0
B58 AD(1) AD(0) A58 B58 AD(1) AD(0) A58
B59 +5V8 +5V9 A59 B59 +5V8 +5V9 A59
ACK64J B60 A60 REQ64_1J ACK64J B60 A60 REQ64_2J
ACK64# REQ64# ACK64# REQ64#
B61 +5V10 +5V11 A61 B61 +5V10 +5V11 A61
B62 +5V12 +5V13 A62 B62 +5V12 +5V13 A62

Slot,PCI CONN Slot,PCI CONN

AD[31..0] AD[31..0]
AD[31..0] 26 AD[31..0] 26

R118
*

IDSEL0 330 AD18

+/-5%

5V_SYS 3D3V_SYS -12V_SYS R111

*
IDSEL3 330 AD17
+/-5%

C94 C201
B CP9 B
0.1uF EC32 0.1uF

2
*
EC22
470uF * 16V, Y5V, +80%/-20%
* 1000uF
+/-20% * 16V, Y5V, +80%/-20% * C103
PSCLK 2 1 SMB_CLK_RESUME 22,24,29,35
16V, +/-20% 0.1uF Del R351,R352

1
X_COPPER
CP10
25V, X7R, +/-10% PSDATA 2 1 SMB_DATA_RESUME 22,24,29,35

X_COPPER

5V_SYS

3D3V_SYS

RN22

*1
RN18
INTBJ
INTBJ 26
*1 2 REQ64_2J
2 INTCJ 3 4 ACK64J
3 4 INTCJ 26 5 6
INTDJ REQ64_1J
5 6 INTDJ 26 7 8
INTAJ
7 8 INTAJ 26
2.7K
8.2K +/-5%
+/-5%

RN30
*1 2 PREQ1J
PREQ2J
26 PCI Slot
26
3 4 3D3V_SYS
5 6 PREQ3J 26
7 8 PREQ0J 26
RN21
8.2K
+/-5%
*1 2
STOPJ
LOCKJ
RN26 3 4 PERRJ
5 6
*1 2
INTGJ
INTHJ
INTGJ
INTHJ
26
26
1394a
7 8
SERRJ
3 4 INTFJ IT8211 8.2K
A A
5 6 INTFJ 26
INTEJ +/-5%
7 8 INTEJ 26
8.2K
+/-5% RN20
Reserved
*1 2
FRAMEJ
IRDYJ
**

R217 8.2K +/-5% 3 4 TRDYJ

PREQ4J 26 5 6
R215 8.2K +/-5% DEVSELJ
PREQ5J 26 7 8
8.2K FOXCONN PCEG
+/-5%
Title
PCI Slot
Size Document Number Rev
C
G41M01 A

Date: Tuesday, September 16, 2008 Sheet 30 of 38

5 4 3 2 1
 5 4 3 2 1

U26 U25 U82 AVDDL VDD33

3D3V_SB
VDD33 U2
RTL8111B-VC-GR EECS 1 8 VDD33 C21
CS VCC

1
*R2 RTL8101E-GR RTL8111C-GR
* C69 EESK 2 7
* 0.1uF

E
0 10uF EEDI/AUX SK DC
3 DI ORG 6

10V, Y5V, +80%/-20%

+/-5% B Q1 EEDO 4 5 16V, Y5V, +80%/-20%

2
@8111C BCP69T1G DO GND Reserved
R7
@8101E @8111C @8111B @8111B AT93C46DN-SH-T

*
@8111B R29
L2

4
C

*
0 VDD33

*
@8111C +/-5%
0 GVDD 4.7uH Dummy
+/-5% Near to pin 200mil
* Dummy C16 C18 Width >40mil
0
2KOhm R25
* 0.1uF
* 1uF CTRL18 L1 AVDDL

VDD33
AVDDH
XTAL2
XTAL1
#R1000#R1001
+/-1% 16V, X7R, +/-10% 10V, Y5V, +80%/-20% +/-5%

DVDD
GVDD

DVDD

DVDD
LED0
LED1
LED2
LED3
@8111B @8111B @8101E C99 C48 C63 C35 EEDI/AUX R32 3.6K +/-1% 33VAUX

CTRL15
D 3D3V_SB D
*R1000 *R1001 * 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF

RSET

1
2.49K 2KOhm
* C78
* C2

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

+/-1% +/-1% 10uF 10uF
C12 VDD33

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

EGND R63 +/-5%

2
@8111C/8111B @8101E U4 XTAL1 Reserved
65

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

*
0

1
VDD15E
RSET
65

VCTRL15
NC22
CKTAL2
CKTAL1
NC21

LED0
LED1
LED2
LED3

NC20
NC19
NC18
VDD33D

VDD15D
33pF

1
+/-5% X1
XTAL-25MHz
* C22
10uF * C64
10uF

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

CTRL18 1 48 EESK
C11

2
AVDDH VCTRL18 EESK EEDI/AUX Reserved Reserved
2 47

2
MDI0+ AVDD33 EEDI/AUX VDD33 XTAL2
3 46

*
MDI0- MDIP0 VDD33C EEDO
4 MDIN0 EEDO 45
AVDDL 5 44 EECS 3D3V_SYS
AVDD18A EECS 33pF

RTL8101E-GR
MDI1+ 6 43 DVDD
MDI1- MDIP1 VDD15C +/-5% @8111B @8111B
7 MDIN1 NC17 42 R48
AVDDL 8 41 DVDD
MDI2+ 9
AVDD18B
NC1
NC16
NC15 40 *1K
+/-5%
MDI2- 10 39 3D3V_SB FB15 +/-5% VDD33
AVDDL NC2 NC14 DVDD AVDDL L12
11 NC3 NC13 38 AVDDL
MDI3+ 12 37 VDD33 0 0
MDI3- NC4 VDD33B R45
13 NC5 ISOLATEB 36 1 2+/-1% +/-5% C36 C60

1
AVDDL
DVDD
14
15
NC6 NC12 35
34
15K Reserved @8111C
VDD33 * * C98
10uF
C97
10uF * 0.1uF
* 0.1uF
LANWAKEB

REFCLK_N

VDD15A NC11
REFCLK_P

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

VDD33 16 33 R53 0 DVDD Dummy
EVDD18A

EVDD18B

2
VDD33A NC10
PERSTB
VDD15B

*
+/-5%
EGNDA

EGNDB

E
HSON
HSOP

@8101E/8111B

MDI0+

MDI1+
HSIN
HSIP

MDI0-

MDI1-
NC7
NC8

NC9

B Q4
BCP69T1G
#U26#U25#U82 @8111B
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

*R30 *R34 *R35 *R37

4
C
49.9 49.9 49.9 49.9 CTRL15 L10 DVDD
+/-1% +/-1% +/-1% +/-1% 0
EVDD18

EVDD18

+/-5% C77 C38 C43 C23 C91 C19 AVDDH FB2 +/-5%
DVDD

DVDD

AVDDH VDD33
@8101E @8101E @8101E @8101E @8101E
* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
EGND

24 LAN_PMEJ

1
* C42 0

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

34 ICH_LAN_PLTRSTJ
C30 C39
* C14 10uF

10V, Y5V, +80%/-20%

C
* 0.1uF
* 0.1uF 10uF C

2
10V, Y5V, +80%/-20%
16V, X7R, +/-10% 16V, X7R, +/-10% C20
24 HSO_P2_LAN

2
24 HSO_N2_LAN
C90 0.1uF 16V, X7R, +/-10%
HSI_N2_LAN 24
@8101E @8101E * 0.1uF
**

16V, Y5V, +80%/-20%

C89 0.1uF 16V, X7R, +/-10%
HSI_P2_LAN 24
EGND

REFCLK- Reserved Reserved Reserved

CK_PE_100M_N_LAN 7
@8101E/8111B
REFCLK+ @8101E
CK_PE_100M_P_LAN 7

ICH_LAN_PLTRSTJ AVDDL AVDDL R64 +/-5% EVDD18

0 #FB23#R1002
C86 3D3V_SB R3 CTRL15
* 180pF
+/-5%
0
+/-5% C10 R1002 FB23
*
C87
0.1uF
*
C88
0.1uF

1
@8111C
* C1
* C8
* 0.1uF 0 FB 100 Ohm

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

10uF 10uF +/-5% +/-25%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

@8111C

2
@8111B @8101E/8111C

AVDDL

R27
0
+/-5% @8111C @8111C
@8101E

C47 C46
0.1uF
* 470pF
* 5V_DUAL

16V, Y5V, +80%/-20% 3D3V_SB

B
MDI0+ 1
U20
1 8 8 MDI0+
Reserved 50V, X7R, +/-10% BACK PANEL ( LAN + 2 USB Connector ) B

MDI0- 2 7 MDI0-
2 7 R59 R58 F3
MDI1+ 3 6 MDI1+ 150 150 Fuse 2.6A
3 6

*
D8 +/-5% +/-5%
MDI1- 4 5 MDI1- LED1 C A SVCC2
4 5 @8111C/8111B Reserved
BACK SLVU2.8-4.TBT LS4148-F
D13 * C84
0.1uF NIC_USB

*
LED2 C A 16V, Y5V, +80%/-20%
24 USB_OCJ_BACK
U21 LS4148-F @8101E 27 SVCC2 R65
1
*

MDI2+ 1 8 MDI2+ LED3 R66 0 22 28 C82 R56 47K

1 8
YLW_LED

MDI2- MDI2-
+/-5% @8111C/8111B
* C83
470pF
21 29
* 0.1uF 56K
+/-5%
+/-5%
USB-2

USB-1

2 2 7 7 30
50V, X7R, +/-10% 16V, Y5V, +80%/-20%
MDI3+ MDI3+ 2
3 3 6 6
9 1
MDI3- 4 5 MDI3- MDI0+ 10 5
4 5 MDI0- RN11
11
* 13
RJ45-MJ2

BACK SLVU2.8-4.TBT MDI1+ 12 2 2 USBP5

MDI1- USBN5 USBP5 24
13 6 4 USBN5 24
MDI2+ 14 6 5 USBP7
AVDDL MDI2- USBN7 USBP7 24
15 3 8 7 USBN7 24
MDI3+ 16 7 U6
MDI3- 17 L11
*

R61 0 0 USBN7 USBP7

18 4 1 6
+/-5% Dummy C85 8 1 +/-5% 5 5V_DUAL

*R62 470pF 2 5
GRN_LED

0
+/-5% * 50V, X7R, +/-10% 20 23
2 6
USBN5 3 4 USBP5
Reserved C245 19 24 3 7
0.1uF 25 IP4220CZ6
* 26 4 8
16V, Y5V, +80%/-20%

A CONN-USBx2_RJ45 * C80
0.1uF Filter 100MHz
A
Dummy
R60 150 +/-5%
16V, Y5V, +80%/-20%

3D3V_SB #NIC_USB1#NIC_USB2

LED0
NIC_USB1
NIC_USB2
add 040808
JFM24U13-21U5-4F RU1-250ARWGF
FOXCONN PCEG
38U1A-2NK1-4F
* C81
0.1uF
Title
Index Page
16V, Y5V, +80%/-20%
Size Document Number Rev
CONN-USBx2_RJ45
@8101E
CONN-USBx2_RJ45
@8111C/8111B
C G41M01 A

Date: Thursday, September 18, 2008 Sheet 31 of 38

5 4 3 2 1
 5 4 3 2 1

5V_DUAL
5V_AUDIO

A
D12 12V_SYS Jack Detect
SD103AW

*
SENSE_A R44 39.2K +/-1%
SURR_JD 33

C
D U7 H78L05AA FB16 D14 @6JACK D
1 OUT IN 3 2 1 C A
R47 5.1KOhm +/-1%
F_JD 33
C101 FB 300 Ohm LS4148-F

GND
10uF
*

* *
10V, Y5V, +80%/-20% R43 10K +/-1%
L1_JD 33
* C79
Dummy *

2
+80/-20% EC13
4.7uF 100uF R68 R46 20K +/-1%
MIC1_JD 33
10
+/-5%

GND_AUDIO

5V_DUAL GND_AUDIO Filtering Power Noise(Improve

background noise caused by MIC-boost)
Jack Detect
EC17 SENSE_B R15 5.1KOhm +/-1%
SURRBACK_JD 33
* 470uF
16V, +/-20%
@6JACK

* * *
R14 10K +/-1%
CEN_JD 33
3D3V_SYS 5V_AUDIO @6JACK

R11 20K +/-1%

MIC2_JD 33
ICH_BCLK
C72 C71 C73 C15 C24 R9 39.2K +/-1%
LINE2_JD 33
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C * * C93
Dummy * * * Dummy * C

Dummy +80/-20% Dummy

4.7uF

GND_AUDIO All of JD resistors should be placed as

25
38
U1

1
9
close as possible to Codec.

DVdd1
DVdd2
AVdd1
AVdd2
3 GPIO1
33 FIO_PRESENCEJ 2 GPIO0
11
ALC662-GR 35
24 ICH_RSTJ RESET# FRONT_L LINE_OUT_L 33
24 ICH_BCLK 6 BCLK FRONT_R 36 LINE_OUT_R 33
10 37
*

*
24 ICH_SYNC R50 22 +/-5% SYNC LINE1-VREFO-R R16 10K +/-1% @883
24 ICH_SDIN2 8 SDATA_IN DCVOL 33 5V_AUDIO
5 34 SENSE_B
24 ICH_SDOUT SDATA_OUT Sense B (JD2)
39 SURR_L 33

*
SURR-OUT-L R28 20K +/-1%
40
*

R52 10K +/-5% Dummy C74 1uF 10V, X5R, +/-10% Dummy JDREF (or NC)
8 BEEP_PC 12 41 SURR_R 33
*

SENSE_A PC_BEEP SURR-OUT-R

13 Sense A (JD1) CEN-OUT 43 CEN 33 Near to Codec
R51

AUX_L 14 44 GND_AUDIO
33 AUX_L LINE2-L LFE-OUT LFE 33
C75 AUX_R 15 45 SURRBACK_L
33 AUX_R LINE2-R SIDESURR-L SURRBACK_L 33
100pF MIC2_L_16 SURRBACK_R
* 33
33
MIC2_L
MIC2_R
MIC2_R_17
16
17
MIC2-L
MIC2-R
SIDESURR-R 46 SURRBACK_R 33

B Dummy 18 28 MIC1_VREFO B
33 CD_L CD_L MIC1-VREFO-L MIC1_VREFO 33
1K+/-1% Dummy

19 27 GND_AUDIO

*
33 CD_GND CD_GND VREF
33 CD_R 20 CD_R LINE1-VREFO 29
21 30 C9
33 MIC1_L MIC1-L MIC2-VREFO 10uF MIC2_VREFO 33
33 MIC1_R 22 MIC1-R LINE2-VREFO 31 LINE2_VREFO 33
23 32 +/-10%
33 LINE1_L LINE_L MIC1-VREFO-R MIC1_VREFO_R 33
33 LINE1_R 24 LINE_R
DVss1
DVss2
AVss1
AVss2

47 SPDIFI(EAPD)
33 SPDIF_OUT 48 SPDIFO
GND_AUDIO #U23#U24 ALC662-GR
4
7
26
42

Add CD-IN Eric

CP1

X_COPPER
CP18
C96 0.1uF
*

Dummy 16V, Y5V, +80%/-20% U23 U24

X_COPPER
GND_AUDIO
C33 0.1uF
ALC888-GR
CP7 ALC662-GR
* * * *

16V, Y5V, +80%/-20%

C119 0.1uF
Dummy 16V, Y5V, +80%/-20% For EMI X_COPPER
A A
C62 0.1uF
Dummy 16V, Y5V, +80%/-20% ALC662-GR ALC888-GR
@662 @888
C100 0.1uF
Dummy 16V, Y5V, +80%/-20% FOXCONN PCEG
GND_AUDIO Title

GND_AUDIO AUDIO 655/861

Size Document Number Rev
Custom
G41M01 A

Date: Tuesday, September 23, 2008 Sheet 32 of 38

5 4 3 2 1
 5 4 3 2 1

**
MIC1_VREFO R18 2.2K +/-5% L_IR_A M_R_A
32 MIC1_VREFO RN13
L_OR_A M_L_A
32 MIC1_VREFO_R
MIC1_VREFO_R R17 2.2K +/-5%
2 *
1
LFE_M
SURR_R_M
CEN_C
SURRBACK_L_C
L_OL_A
SURR_R_C
4 3 CEN_M LFE_C L_IL_A
6 5 SURR_L_M SURR_L_C SURRBACK_R_C

**
EC5 100uF R8 75 +/-5% FB9 FB 600 Ohm M_R_A 8 7 C50 C51 C49 C13 C58 C59 C57 C56 C54 C52 C55 C53
32 MIC1_R * AUDIO

**
150pF 150pF 150pF 150pF 150pF 150pF 150pF 150pF 150pF 150pF 150pF 150pF
MIC-IN 22K

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

EC1 100uF R5 75 +/-5% FB8 FB 600 Ohm M_L_A
32 MIC1_L *

1
GND_AUDIO +/-5%
AUDIO Reserved * * * * * * * * * * * *
D D

2
LINE-IN

**
EC3 100uF R1 75 +/-5% FB11 FB 600 Ohm L_IR_A R36 +/-5% SURRBACK_L_M
32 LINE1_R
** * 2
22K
1
Reserved
EC4 100uF R10 75 +/-5% FB7 FB 600 Ohm L_IL_A
32 LINE1_L * R55
2 +/-5%
1 SURRBACK_R_M
22K Reserved @6JACK @6JACK @6JACK @6JACK
@6JACK @6JACK

*
RN1 GND_AUDIO GND_AUDIO

1
3
5
7
22K
+/-5%

******
2
4
6
8
Reserved EC18 @6JACKR71 75 SURR_L_M FB13 @6JACK FB 600 Ohm SURR_L_C
32 SURR_L *

******
100uF @6JACK +/-5%
EC19 @6JACKR70 75 SURR_R_M FB5 @6JACK FB 600 Ohm SURR_R_C
32 SURR_R 100uF @6JACK +/-5% *
EC14 @6JACKR67 75 CEN_M FB1 @6JACK FB 600 Ohm CEN_C
32 CEN 100uF @6JACK +/-5% *
GND_AUDIO EC15 @6JACKR69 75 LFE_M FB4 @6JACK FB 600 Ohm LFE_C
32 LFE 100uF @6JACK +/-5% *
EC11 @6JACKR41 75 SURRBACK_L_M FB12 @6JACK FB 600 Ohm SURRBACK_L_C
32 SURRBACK_L 100uF @6JACK +/-5% *
EC12 @6JACKR54 75 SURRBACK_R_M FB14 @6JACK FB 600 Ohm SURRBACK_R_C
*
* *

EC2 AUD_FIO_RR6 75 +/-5% FB10 FB 600 Ohm L_OR_A 32 SURRBACK_R 100uF @6JACK +/-5%
32 LINE_OUT_R * AUDIO
* *

100uF

32 LINE_OUT_L
EC6 AUD_FIO_LR12 75 +/-5% FB6
* FB 600 Ohm L_OL_A Front_OUT
100uF
C 1 1 C
R13 R4
22K 22K
+/-5% +/-5%
AUDIO1ACONN-6 Ports Audio
AUDIO1DCONN-6 Ports AudioGND_AUDIO 1 AUDIOA audio
2 Reserved 2 Reserved @6JACK @6JACK M_R_A 5
M_S_A 4
32 MIC1_JD 3
M_L_A 2
GND_AUDIO AUDIO1BCONN-6 Ports Audio
AUDIO1ECONN-6 Ports Audio GND_AUDIO #AUDIO1#AUDIO2
@6JACK @6JACK GND_AUDIO 21 AUDIOB audio 26
SPDIF_OUT L_OR_A 25
5V_SYS 1 1 L_OS_A 24
23 GND_AUDIO
SPDIF_OUT AUDIO1CCONN-6 Ports Audio
AUDIO1FCONN-6 Ports Audio 32 F_JD L_OL_A
32 SPDIF_OUT 3 3 22
4 @6JACK @6JACK GND_AUDIO #AUDIO1#AUDIO2
C76 4
GND_AUDIO 31 AUDIOC audio 36
22pF L_IR_A
32 LINE2_VREFO * 50V, NPO, +/-5%
Header_1X4_K2
L_IS_A
35
34
Dummy 33
AUDIO2 INSULATOR 32 L1_JD L_IL_A GND_AUDIO
32
For EMI GND_AUDIO #AUDIO1#AUDIO2
32 MIC2_VREFO Silk Screen
AUDIO
GND_AUDIO 41 AUDIOD audio
SURRBACK_R_C 45
3

SURRBACK_GND 44
B D18 D16 43 B
BAT54A 32 SURRBACK_JD SURRBACK_L_C
BAT54A 42
GND_AUDIO #AUDIO1#AUDIO2
GND_AUDIO 51 AUDIOE audio
LFE_C 55
2

1
2

CEN_GND 54
32 CEN_JD 53
CEN_C 52
RN15 GND_AUDIO #AUDIO1#AUDIO2
3D3V_SYS 61 AUDIOF audio
8
6
4
2

GND_AUDIO
SURR_R_C 65
SURR_GND 64
7
5
3
1
*

32 SURR_JD 63
SURR_L_C
2.2K *R49
10K
CONN - Audio jack
@3JACK GND_AUDIO
62
#AUDIO1#AUDIO2
+/-5% +/-5%
****

EC7 100uF +/-20% R78 75 +/-5% F_AUDIO Dummy

***
32 MIC2_L
****

1 2 GND_AUDIO C29 1uF 10V, X5R, +/-10% R31 1K +/-1% CD_IN

32 CD_L

***
EC8 100uF +/-20% 8p4r0603h7 R77 75 +/-5% 3 4 1
32 MIC2_R FIO_PRESENCEJ 32
5 6 C28 1uF 10V, X5R, +/-10% R26 1K +/-1% 2
MIC2_JD 32 32 CD_GND
EC9 100uF +/-20% R76 75 +/-5% 7 3
32 AUX_R X
9 10 C17 1uF 10V, X5R, +/-10% R19 1K +/-1% 4
LINE2_JD 32 32 CD_R
EC10 100uF +/-20% R75 75 +/-5%
32 AUX_L Header_2X5_8 Header_1X4
Reserved
*

for ALC880 RN16

1
3
5
7

A 22K A
+/-5%
2
4
6
8

FOXCONN PCEG
Title
Index Page
GND_AUDIO GND_AUDIO Size Document Number Rev
Custom G41M01 A

Date: Tuesday, September 16, 2008 Sheet 33 of 38

5 4 3 2 1
 5 4 3 2 1

For the temperature sensor circuits,

1)Please don't remove the 1uF capacitor(C620)

*
TMPIN2 R378 Dummy SIOVREF
between Vref and AGND. 10K
2)Place R568 close to IT8720F. +/-1%
3)Keep the trace away from +12V, fast data bus, C460

C
If without use these pins, Please pull-up to VCC.
Don't let it floating
nd CRTs.
4)Recommended trace widths and spacings are 12 mils.
* 2.2nF
50V. X7R,B+/-10% Q38
Close to pin MMBT3904-7-F
1.Pin 30:RESETCON# 5)Isolate AGND and DGND. placed near SIO

E
2.Pin 95:VIN3/ATXPG
3.Pin 71:SUSB# 3D3V_SYS 5V_SYS
D D
4..Power On Strapping Options pin RTSBJ
GND_IO
5.Please don't remove the pull-up resistor (R108) SOUTB C407 System temperature sensing

1
of pin38/LDRQ#.
6.Please don't remove any components in the *R299
Dummy *R323
1K *R327
1K
R322
Dummy
R319
Dummy * 0.1uF
16V, Y5V, +80%/-20%
VINx circuits and the FANx control circuits. 10K +/-5% +/-5% 680 680

2
5V_SYS
7.Please don't change the sequence of A20GATE
VIN0~VIN6. KBRSTJ
8.If without use these pins,please pull-up to VCC, L_DRQ0J EMI Cap.
Don't let it floating ,pin 3,pin 30,pin 38,pin 46, C421 C394 C395

1
pin 95,pin 122,pin 124,pin 126. * 0.1uF
* 0.1uF
* 0.1uF

16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% Del Vref circuit

2
placed near pin4,35,99

5V_SYS TMPIN1 1 2Dummy

5V_SB THERMDA 12
C459 #REFDE6 X_COPPER

L33 FB 80Ohm * 3.3nF

+/-10%
VCCP R384 10K VIN0 *
+/-5% TS_D- 1 2Dummy THERMDC 12
1

C465 Close to pin

* 0.1uF
Dummy
C443
10uF * * C454
1uF
* C466 *
#REFDE7 X_COPPER

Note: 0.1uF EC53

2

16V, Y5V, +80%/-20% Place C441,C442 close 16V, Y5V, +80%/-20% 100uF CPU temperature sensing
to Pin99
GND_IO
R383 10K VIN1

35

99

67
1D8V_STR

4
+/-5% C464 U18
1

* 0.1uF

VCC

VCC

AVCC

VCCH
Dummy
16V, Y5V, +80%/-20%
PD[7..0] 36
2

DCDBJ 127 116 PD7

36 DCDBJ DCD1# PD7/GP77/BUSSO2
C RIBJ 128 115 PD6 C
The strap's resistor can be deleted since VIDO 36 RIBJ RI1# PD6/GP76/BUSSO1
GND_IO CTSBJ 1 114 PD5
and COM2 need to be pulled high. 36 CTSBJ CTS1# PD5/GP75/BUSSO0
DTRBJ 126 113 PD4
36 DTRBJ DTR1#/JP4 PD4/GP74/BUSSI2

Parallel Port
3D3V_SYS R379 10K VIN4 RTSBJ 122 112 PD3
36 RTSBJ RTS1#/JP2 PD3/GP73/BUSSI1

Serial Port 1/2

+/-5% DSRBJ 123 111 PD2
36 DSRBJ DSR1# PD2/GP72/BUSSI0
1

C462
* 0.1uF
Dummy
36
36
SOUTB
SINB
SOUTB
SINB
124
125
SOUT1/JP3
SIN1
PD1/GP71
PD0/GP70
110
109
PD1
PD0 5V_SYS 3D3V_SYS
SOUTA DCDAJ 26 108
36 SOUTA STBJ 36
2

16V, Y5V, +80%/-20% SINA RIAJ VIDO1/GP21/DCD2# STB#/GP87/SMBC_M R301

36 SINA 28 VIDO6/GP17/RI2# AFD#/GP86/SMBC_R 107 AFDJ 36
RTSAJ CTSAJ 27 106 IDE_RSTJ R300
330
36 RTSAJ ERRJ 36

*
VIDO0/GP20/CTS2# ERR#/GP83

*
GND_IO DTRAJ DTRAJ 29 105 ICH_LAN_PLTRSTJ 330
+/-5%
36 DTRAJ VDIO7/DTR2#/JP6 INIT#/GP85/SMBD_M INIT 36
RTSAJ 23 104 +/-5%
SLINJ 36
*

R382 30K VIN2 DCDAJ DSRAJ VIDO2/FAN_TAC5/GP24/RTS2# SLIN#/GP84/SMBD_R

12V_SYS 36 DCDAJ 22 VIDO3/FAN_TAC4/GP25/DSR2# ACK#/GP82 103 ACKJ 36
+/-1% R381 RIAJ SOUTA 21 102
* * 36 RIAJ VIDO4/GP26/SOUT2 BUSY/GP81 BUSY 36
1

10K C463 CTSAJ SINA 20 101

36 CTSAJ VIDO5/GP27/SIN2 PE/GP80 PE 36
+/-1% 0.1uF DSRAJ 100
36 DSRAJ SLCT SLCT 36
2

16V, Y5V, +80%/-20% 48

Note: 12,24 ICH_THRM_UP GP50/SO

SPI
25

*
GND_IO GND_IO Recommend Vin4,Vin5,Vin6 monitor the 8 SIO_BEEP GP22/SCK R389 10K
8 PWR_LED 24 GP23/SI PWROK2/GP41 78 5V_SB
5V_SYS

Control
Power-on
voltage signals of less than 4.096V. 77 SUSCJ
5V_SYS SUSC#/GP53

*
Gary 011108 76 R38810K Follow ITE 8720 DEMO SCH
PS_ONJ 8

*
PSON#/GP42 R386
PANSWH#/GP43 75 PBTNJ_SIO 8
R298 72 33 C467
+/-5%
PWRON#GP44 PWRBTNJ 24 power button input
Del VIN5, VIN6 monitor circuit only
R297
4.7K
4.7K 121
2
FAN_CTL4/VID_TURBO
PSI_L/FAN_CTL5/CIRRX2/GP16
SUSB# 71 SLP_S3J 24 * 1uF
10V, Y5V, +80%/-20%
for Clone MB request. 3 CIRTX 35

*
012008 PCIRSTIN#/CIRTX2/SVD R303 10K
31 PECI_RQT/SVC/GP14 RESETCON#/CIRTX1/CE_N 30 5V_SYS
3D3V_SYS 6 85 1 2Dummy
VCORE_GOOD/VID6/GP63 RSMRST#/CIRRX1/GP55 RSMRSTJ 24
5 66 #REFDE8 X_COPPER
VCORE_EN/VID7/GP64 IRTX/GP47 IRTX R385 35
120 70 IRRX 35

*
VDDA_EN/GP65 IRRX/GP46

MISC.
119 68 COPENJ Note:
*R284 12,25 CPU_SLPJ
118
VLDT_EN/GP66
CPU_PG/GP67
COPEN#
3VSBSW#/GP40 79 COPEN# should be connected to GND
when the function is not be used.
10K 84
PCIRST4#/GP10/VDIMM_STR_EN CIRRX 35 1K
PCIRST2#/GP11 34 ICH_LAN_PLTRSTJ 31+/-5%
SERIRQ FLOPPY 33 3D3V_SYS
PCIRST1#/GP12 IDE_RSTJ 25
1 2 DENSELJ 32
1 2 PWROK1/GP13
B X 4 4 B
5V_SYS 5 6 51 R302
RN47 5 6 INDEXJ DENSEL# 1K
7 7 8 8 63 INDEX#
DSKCHGJ
WPJ
*1 2 9
11
9 10 10
12
MOAJ
12 PECI
R348 0
52
55
MTRA#
PWRGD_3V 14,24
INDEXJ 3 4 11 12 DSAJ PECI/AMDSI_C/DRVB# VIN0
5 6 13 13 14 14 54 DRVA# VIN0 98
TRAK0J 15 16 R341 0
Dummy 53 97 VIN1

Floppy I/F
150 7 8
17
15 16
18 DIRJ 57
SST/PECI_AVA/AMDSI_D/MTRB# VIN1
96 VIN2
+/-5% 17 18 STEPJ DIR# VIN2
19 19 20 20 58 STEP# VIN3/ATXPG 95 PWRG_ATX 8,10,11
RDATAJ R360 150 21 22 WDJ 56 94 VIN4
21 22 WEJ WDATA# VIN4/VLDT_12
23 23 24 24 60 WGATE# VIN5/VDDA_25 93

Hardware Monitoring
+/-5% 25 26 TRAK0J 62 92
25 26 WPJ TRK0# VIN6/VDIMM_STR SIOVREF
27 27 28 28 64 WPT# VREF 91
29 30 RDATAJ 61 90 TMPIN1 C461
L_AD3 29 30 HEADJ RDATA# TMPIN1 TMPIN2
L_AD2
31
33
31
33
32
34
32
34 DSKCHGJ
59
65
HDSEL#
DSKCHG#
TMPIN2
TMPIN3
89
88
* 1uF
10V, X5R, +/-10%
L_AD[3..0] L_AD1 87 TS_D-
24,28 L_AD[3..0] L_AD0 Header_2X17_K3 TS_D- closed to pin 91
14,22,24,28 PLTRSTJ 37 LRESET#
L_DRQ0J 38 12 GND_IO
24 L_DRQ0J LDRQ#/JP1 FAN_CTL3/GP36 FANOUT3 35
IT8720 Power On Strapping Options 25,28 SERIRQ 39 SERIRQ FAN_TAC3/GP37 11 FANIN3 35
24,28 L_FRAMEJ 40 LFRAME# FAN_CTL2/GP51 10 FANOUT1 35
Symbol value Description L_AD0 41 LAD0 FAN_TAC2/GP52 9 FANIN1 35
LPC I/F

L_AD1 42 8
LAD1 FAN_CTL1 FANOUT2 35
JP1 1 Disabled. L_AD2 43 LAD2 FAN_TAC1 7 FANIN2 35
Flashseg1_EN L_AD3 44 LAD3 VID0/GP30 19
Pin 38 0 Flash I/F Address Segment 1 is enabled 7 CK_33M_SIO 47 PCICLK VID1/GP31 18
7 CK_48M_SIO 49 CLKIN VID2/GP32 17
JP2 1 Disable VID output pins 24 L_PMEJ 73 PME#/GP54 VID3/GP33 16
VIDO_EN VID4/GP34 14
Pin 122 0 Enable VID output pins VID5/GP35 13
3D3V_SYS
JP3 Use for chip 1 when two IT8718F exit in the
25 KBRSTJ
KBRSTJ 45 KRST#/GP62
VBAT
CHIP_SEL same system. Chip is selected in conjunction
25 A20GATE
A20GATE 46 GA20/JP5
Pin 124 with "Global Configuration Register - Index 22, bit 7
35 KBDATA
KBDATA 80 KDAT/GP61
KB/MS

KBCLK 81 69 1.Closed to pin 69, Vbat should be routed

35 KBCLK KCLK/GP60 VBAT
JP4 1 K8 power sequence function is disabled 35 MSDATA
MSDATA 82 MDAT/GP57 VIDVCC 36 C458 with a minimum trace width of 12 mils.
K8PWR_EN 35 MSCLK
MSCLK 83 MCLK/GP56 * 1uF 2.Isolate the pin69/Vbat of IT8720F and
A Pin 126 0 K8 power sequence function is enabled 10V, X5R,pin VCCRTC of ICH.
+/-10% A

11 The default value of EC Index 15h/16h/17h is 40h(Fan half speed)

GNDD
GNDD
GNDD
GNDD

GNDA

JP3 &
JP5 10 The default value of EC Index 15h/16h/17h is 7Fh(Fan off )
FAN_CTL_SEL
Pin 124 01 The default value of EC Index 15h/16h/17h is 00h(Fan full speed ) IT8720F/FX-L
15
50
74
117

86

& 46 00 The default value of EC Index 15h/16h/17h is 20h #REFDE4

JP5 1 Disable WDT to rest PWROK 2 Dummy

1 FOXCONN PCEG
WDT_EN
Pin46 0 Enable WDT to rest PWROK COPPER Title
Super I/O IT8720H
JP6 1 Disable SVID Function GND_IO
SVID_EN Size Document Number Rev
Pin29 0 Enable SVID Function C G41M01 A

Date: Thursday, September 18, 2008 Sheet 34 of 38

5 4 3 2 1
 5 4 3 2 1
Peak fan current draw: 1.5A
Average fan current draw: 1.1A
Fan start-up current draw: 2.2A
Fan start-up current draw maximum duration: 1.0 second

SM Bus Bridge 5V_SYS

Fan header voltage: 12V +/- 10%

*R236
4.7K
+/-5%

R235
34 FANOUT1
100 +/-1%
If use SUIO power good 3D3V_SYS
D D
12V_SYS
function, dummy Q7,Q6,Q8 R274 2.7K +/-5% SMB_DATA_MAIN
pop R25,R18 R275 2.7K +/-5% SMB_CLK_MAIN

12V_SYS
Near the Memory

CP11

C
D22
7,19,21 SMB_DATA_MAIN SMB_DATA_RESUME 22,24,29,30
R239
X_COPPER * 4.7K
CPU_FAN +/-5% LS4148-F
for Clock Generator/DIMMs/TPM/Clock Buffer 2

A
for PCI-E x16/ICH7/LAN/PCI/PCI-E x1/Riser Card/New Card +12V
CMD 4
1 R238

*
GND 27KOhm
CP12 ? TACH 3
C277 +/-5%
FANIN1 34
Max. output current = 3A
7,19,21 SMB_CLK_MAIN SMB_CLK_RESUME 22,24,29,30
*
EC38
100uF Header_1X4 FAN4P * 47pF
50V, NPO, +/-5%
2
R237
X_COPPER CPU FAN 16V, +/-20%
Dummy 22K
+/-5%
1

5V_SYS 12V_SYS 12V_SYS

C 5V_SYS *R80
4.7K C
+/-5% U17D

4
5V_SB

S
12 @FAN_3PIN

*
+
14 R74 470 G R91

*
C430 R79 15K 13 +/-5% AP3310H 0
34 FANOUT2 - Q7
0.1uF
16V, Y5V, +80%/-20% * @FAN_3PIN
+/-5%
LM324DR2G
+/-5%

11
Dummy IR/CIR 1 5V_SYS @FAN_3PIN @FAN_4PIN

D
1 2 C105 C420

1
3
X 4 CIRRX 34 IRRX * 10uF
* 0.1uF

10V, Y5V, +80%/-20%

5 6 4 @FAN_3PIN @FAN_3PIN
34 IRRX 5 GND
7 8 CIRTX 34

2
IRTX
34 IRTX 9 X
R81 R355
Header_2X5_K3K10 100 36K FAN_PWR
#IR#IR/CIR1 @FAN_4PIN +/-1% +/-5%
C442 C450 1 @FAN_3PIN
* *
470pF 470pF
50V, X7R,50V,
+/-10%
X7R, +/-10% IR/CIR CONNECTOR IR
1
IR/CIR1 R343
22K
Dummy Dummy +/-5%@FAN_3PIN
Need check whether follow up 3
X
2
TF spec?? 4
5 X
Header_1X5_K2 Header_2X5_K3K10
@IR @IR/CIR1

12V_SYS

FAN_PWR D17

C
R84 LS4148-F

5V_DUAL
SYS_FAN1 * 4.7K
+/-5%
+12V 2
CMD 4
B 5V_DUAL
* GND 1
R85 B

*
EC25
Dummy 27KOhm
C45 TACH 3 +/-5% 2
FANIN2 34
100uF

F2 * 0.1uF 16V, +/-20% Header_1X4 FAN4P

*
C118
47pF
R89
22K
Fuse 1.5A 50V, NPO, +/-5% +/-5%
*

1
Co-lay footprint

SYS_FAN1
8
6
4
2

FB3
RN10 KB/MS Max. output current = 3A
4.7K
+/-5% FB 300 Ohm
2
*

16
7
5
3
1

13 5V_SYS

34 KBCLK CLK_NET03 5 11

34 KBDATA
3
1
9
7 *R375
4.7K
2 17 +/-5%R390
4 8 34 FANOUT3
6 10
12 100 +/-1%
14 12V_SYS
12V_SYS
UP DOWN 15
EC52
PS2X2 * 100uF

C
PWR_NET02 16V, +/-20%
Dummy R371D32
SYS_FAN2 * 4.7K
CLK_NET02 +/-5%
34 MSCLK +12V 2 LS4148-F
CMD 4 R372
GND 1
A A
34 MSDATA

*
27KOhm
TACH 3 +/-5% 2
FANIN3 34
C447 R373

*
C37
0.1uF
Header_1X4 FAN4P
* 47pF
50V, NPO, +/-5%
22K
+/-5%
* 16V, Y5V, +80%/-20% 1
50V, NPO, +/-10%
180pF
CN3 FOXCONN PCEG
Title
Keyboard / Mouse / Fan
KB\MS SYS_FAN2 Size
C
Document Number
G41M01
Rev
A

Date: Thursday, September 18, 2008 Sheet 35 of 38

5 4 3 2 1
 5 4 3 2 1

5V_SYS
U14
5V_SYS 20 1 12V_COM
VCC +12V
16 5 NRTSB -12V_COM 5V_SYS 12V_COM

A
34 RTSBJ DA1 DY1

16V, Y5V, +80%/-20%

C403 0.1uF
15 6 NDTRB RN5 RN7 D6 C68
34 DTRBJ DA2 DY2 NSOUTB
13 8
* 0.1uF

8
6
4
2

8
6
4
2
34 SOUTB DA3 DY3

1
NRIB
34
34
RIBJ
CTSBJ
19
18
RY1
RY2
RA1
RA2
2
3 NCTSB * C373 * * C374 LS4148-F
16V, Y5V, +80%/-20%

7
5
3
1

7
5
3
1
NDSRB Reserved

*
17 4 0.1uF 0.1uF

C
34 DSRBJ RY3 RA3 NSINB
34 SINB 14 RY4 RA4 7
12 9 NDCDB 2.2K 2.2K RN3
D 34 DCDBJ RY5 RA9 25V, X7R, +/-10% 25V, X7R, +/-10% D

11 10 -12V_COM @COM2 @COM2

+/-5% +/-5%
*1 2
STB1-
AFD1-
GND -12V @COM2 3 4 INIT1-
GD75232 8p4r0603h7 8p4r0603h7 5 6 SLIN1-
@COM2 7 8
RS232 Drivers and Receivers 2.7K
+/-5%
placed near GD75232 RN9
34 PD[7..0]
PD[7..0]
*1 RN6
*
1
3
2
4
ACK-
BUSY
PD0 2 33 PE
3 4 +/-5% 5 6
PD1 7 8 SLCT
PD2 5 6
PD3 7 8 10K
PD4 +/-5%

*
PD5
PD6
*1 RN8
2 33
R42
+/-5%
10K ERR-

PD7 3 4 +/-5%
5 6
COM2
NDCDB NSINB 7 8
1 2
NSOUTB 3 4 NDTRB
5 6 NDSRB
NRTSB 7 8 NCTSB
NRIB 9

Header_2X5_K10
@COM2 34 STBJ *1 RN4
2 33
STB1-
AFD1-
34 AFDJ 3 4 +/-5% INIT1-
34 INIT 5 6 SLIN1-
NDTRB NRTSB 34 SLINJ 7 8

NSINB NDSRB PRT

NSOUTB NCTSB
STB1- 1
NDCDB NRIB AFD1- 14
P_D0 2
C
* * ERR- 15 C
50V, NPO, +/-10% 50V, NPO, +/-10% 34 ERRJ P_D1 3
180pF 180pF INIT1- 16
CN8 CN9 P_D2 4
@COM2 @COM2 SLIN1- 17
P_D3 5
18
placed near header P_D4 6
placed near header 19
P_D5 7 28
20 27
COM 2 Header P_D6

P_D7
8
21
26

9
22
ACK- 10
34 ACKJ
23
BUSY 11
34 BUSY
24
PE 12
34 PE
25
SLCT 13
34 SLCT

CONN - PrinterPort
CN5
CN4 CN7 CN6 220pF
220pF 220pF 220pF 50V, NPO, +/-10%
50V, NPO, +/-10% 50V, NPO, +/-10% 50V, NPO, +/-10%
* * * *

U5 D5 -12V_SYS 5V_SYS 12V_SYS

B B
5V_SYS 20 1 12V_COM
C A 12V_SYS
VCC +12V C92
2

NRTSA LS4148-F
34 RTSAJ 16 DA1 DY1 5
* 0.1uF
* C66
16V, Y5V, +80%/-20%

34 DTRAJ 15 DA2 DY2 6 NDTRA * C44 0.1uF

13 8 NSOUTA 0.1uF Reserved
1

34 SOUTA DA3 DY3 NRIA 25V, X7R, +/-10%

34 RIAJ 19 RY1 RA1 2
18 3 NCTSA
34 CTSAJ RY2 RA2
25V, X7R, +/-10%

17 4 NDSRA
34 DSRAJ RY3 RA3 NSINA
34 SINA 14 RY4 RA4 7
12 9 NDCDA
34 DCDAJ RY5 RA9 D4
11 10 -12V_COMA C -12V_SYS
GND -12V
GD75232 LS4148-F
placed near GD75232
RS232 Drivers and Receivers

COM1
PRT PORT
11

NDCDA 1
NDSRA 6
NSINA 2
NRTSA 7
NSOUTA 3
NCTSA 8 3D3V_SB
NDTRA 4
NRIA 9 R346
5 * 8.2K
* * +/-5%
50V, NPO, +/-10% 50V, NPO, +/-10% 10
180pF 180pF
CN2 CN1 ICH_RIJ_PU 24

D
Reserved Reserved CONN-COM PORT
D29 Q26
NRIA 1
Update by Steven 053107 3 R336 10K G
*

A NRIB 2 +/-5% 2N7002 A

@ring C409
C

S
1

COM 1 BAT54C * 0.1uF

*
R332
10K
D27

+/-5% @ring
2

@ring LS4148-F
16V, Y5V, +80%/-20%
A

@ring
placed near connector @ring
@ring FOXCONN PCEG
Title
Serial / Parallel
Size Document Number Rev

Ring C
G41M01 A

Date: Tuesday, September 16, 2008 Sheet 36 of 38

5 4 3 2 1
 5 4 3 2 1

5V_DUAL

5V_DUAL
C61
0.1uF
D
* 16V, Y5V, +80%/-20% D

F4
FUSB_PWR Fuse 2.6A

*
EC36 C279

*
* 470uF
16V, +/-20% * 0.1uF R242
+/-5%
10K Reserved
USB_OCJ_FRONT 24
16V, Y5V, +80%/-20%
1
R240 C282
FOR EMI ISSUE 15K 0.1uF
+/-1% *
16V, Y5V, +80%/-20%
2

F_USB1
C RN33 1 2 C
24 USBN1
USBN1
USBP1
2
4
* 13 3
5
4
6
24 USBP1 USBN0 C265 C268 C274 C271
24 USBN0 6 5 7 8 U10
USBP0 6.8pF 6.8pF 6.8pF 6.8pF
24 USBP0 8 7
* +/-0.5pF*
Dummy +/-0.5pF
Dummy
X 10
* +/-0.5pF*
Dummy +/-0.5pF
Dummy USBN0 1 6 USBP0
5V_DUAL
0 Header_2X5_K9
2 5
+/-5%
L26
USBN1 3 4 USBP1
1 5
USB Front Header I
IP4220CZ6
2 6

3 7
5V_SYS
4 8

FUSB_PWR C236
Filter 100MHz 0.1uF
Dummy * 16V, Y5V, +80%/-20%

C278
0.1uF
*
16V, Y5V, +80%/-20%
B B

U13
USBN6 1 6 USBP6
5V_DUAL
2 5

USBN4 3 4 USBP4

FOR EMI ISSUE

IP4220CZ6
F_USB2
RN34 1 2
24 USBN4
USBN4
USBP4
2
4
* 13 3
5
4
6
24 USBP4 USBN6 C295 C300 C304 C303
24 USBN6 6 5 7 8
USBP6 6.8pF 6.8pF 6.8pF 6.8pF
24 USBP6 8 7
* *
+/-0.5pF
Dummy +/-0.5pF
Dummy
X 10
* *
+/-0.5pFDummy
Dummy +/-0.5pF
0 Header_2X5_K9
+/-5%
L27
1 5
USB Front Header II
2 6
A A
3 7

4 8

Filter 100MHz
FOXCONN PCEG
Dummy Title
Serial / Parallel
Size Document Number Rev
add 040808 Custom G41M01 A

Date: Tuesday, September 16, 2008 Sheet 37 of 38

5 4 3 2 1
 5 4 3 2 1

1. Change Lan RTL8111B colay RTL8101E to RTL8111C colay RTL8101E

2. Change Audio ALC888 colay ALC883 to ALC662 colay ALC888
3. Reserved Memory ratio schematic for over clock.
4. Del R108,C139,Q22,Q20,R107 and then connect VRMPWGD directly for VRD11.
5. Add R371,C501 for power button debounce circuit.
6. Reserved U15,U17 for TF spec.
7. Reserved TPM Header for TF spec.
D 8. Reserved U3,U6 for TF spec. D

9. Add R8,R1,R5,R10,R6,R14,R87,R86,R85,R84,R78,R76,R73,R75,R41,R55 for Audio ESD

10. Reserved CIR function for TF spec.
11. Reserved NB FAN.
12. Reserved C307,C314,C324,C318,C348,C350,C360,C357 for TF Front Panel
13. Change R335 to 91ohm,R337 to 115ohm for Memory Power
14. Remove R338 and stuff R332 for FAN half speed when Power on.
15. Reserved R46 for realtek's suggestion
16. Reserved U9,C144,C145 for VCCA_DAC
17. Add RT8111B SCH
18. Del EC72,EC55,EC54,EC73 for placement issue
19. Reserved R40,R25 For EMI
21. Add C16,C17 For RTL8111B LAN Chip EMI
22. Add FB22 For ITE suggestion
23. Reserved C497 for Front Panel ESD
24. Del Power V15SFR SCH
25. Add R208,R220 for further CPU
26. Reserved R321,R109,R320 for PCI RST
27. Disconnect SLP_S4 with CLK Gen
28. Change C368,C371 from 18pF to 12pF
29. Change F_AUDIO Pin7 connect to Audio_GND directly and connect Pin6,Pin10 to codec through the resistor.
After Gerber Out:
C
30. Reserved C506 C
31. Change R363 size from 0402 to 0603
32. Change R111 to 33ohm 1%
33. Add R400 100ohm 1%
34. Dummy Q24 C146
35. Reserved R94 In 8KS2H SKU
36. Reserved R114,C147,R110,Q23,Q26
37. Change R116,R118 to 10K 1%
38. Change C160 to 1uF 0603
39. Reserved Q39
40. Del CP2
41. Del EC29
42. Reserved R356
43. Change PCIe_16x slot to 2EG48211-S7Y-4F
44. Del EC65,EC66
45. Add EC68
46. Change L25,L38 to 630307400-176-G
47. Reserved C451,C396,C375,C381,C430,C441,C355,C436,C447,C448,C397,C385,C446,C427,C405,C401,C395,C353,C390
48. Del RN17
49. Add R401,R402,R403 10K 5%
50. Add JP1,JP2, JP1(P1&P2),JP2(P1&P2)
51. Add R404 470ohm
B
52. Add EC69 B
53. Del EC46,EC47
54. Change L26,L37 to APL1108P-2R5L
55. Change C5,C6,C7 to 10pf
56. Change L8,L9,L10 to GL1608082NJT
57. Reserved C38,C65
58. Change CP14 to L40 10uH
59. Change L23 to 10uH
60. Add C139,C513,C514 10uF
61. Add EC65
62. Del CP24
63. Add R25 for EMC
64. Add R409,R410,R411 for Audio codec ESD protection
65. Change EC55 to 680uF
66. Change L23 from 10uH to 10ohm

A A

FOXCONN PCEG
Title
CHANGE LIST
Size Document Number Rev
C G41M01 A

Date: Monday, July 21, 2008 Sheet 38 of 38

5 4 3 2 1