Manu 2019
Manu 2019
Manu 2019
18th 2019
Abstract— Low power and area efficient 16-bit stage, power gating and clock gating at the logic level and
multiplier has been designed and implemented using the register transfer level, Dynamic scaling of voltage at the
Dadda algorithm. Here, the prime building block having system level. Reduction of power can be achieved on
low power dissipation and area efficient optimized full particular functional part or components of any processor.
adder architecture and Carry Look-Ahead (CLA) adder is
designed and implemented. Designing full adder is done by The design of high speed and low power microprocessors
making use of complex cells in the technology node of require sub-parts that consumes lesser power. Arithmetic and
65nm to reduce the power dissipation and minimum area Logic Unit (ALU) is one part of the microprocessor that
using TSMC 65nm library. The proposed multiplier design consumes majority of the power. Therefore, in order to reduce
is optimized, simulated using ISE simulator and the power dissipation of the ALU, each of its subparts must
synthesized using Cadence Genus EDA tool and results are consume lesser power. An ALU carryout arithmetic operations
demonstrated. The power and area of the Dadda multiplier such as subtraction, addition, division, multiplication, etc., and
designed using proposed full adder is minimum compared logical operations such as Ex-OR, NAND, AND, OR, Logical
to conventional design. The power and area are improved shift, Rotate, etc.
by an amount of 15.32% and 1.91% respectively, than the
conventional-full adder. Dadda Multiplier designed here is Multiplication is the one of the common and prime
used to implement 16-bit ALU the power and area operation used in most of the all-electronic applications and in
obtained are 20.65% and 1.8% lesser than the existing numerous digital communication applications. [6]Multipliers
design. with lesser power consumption, area and low latency are
always used to design an optimized digital circuit in such a
Keywords—Dadda Multiplier, ALU, Carry Look-Ahead Adder way that, in minimum time response maximum throughput can
(CLA), Power, Area. be obtained. Full adders and half adders are the prime building
blocks of any multiplier design. Till now different design
I. INTRODUCTION architectures of half adder and full adder are designed and
Now a days, usage of portable electronic devices area implemented to decrease the power dissipation, area and delay
increasing each day, portable devices require battery for in order to get an efficient multiplier circuit. Along with this,
operating them. So power dissipation becomes the important different algorithms have been introduced to achieve
concern that has to be taken care in designing of such devices optimized power, area and delay such as Dadda algorithm,
i.e., laptops, mobile phones, tablets, notebooks, and many Wallace tree, Booth multiplier and Vedic algorithms. [3]The
more personal electronic devices. The power dissipation plays multipliers used recently are Dadda Algorithm and Reduced-
a fundamental role in VLSI technology. [8]More power sp-D3Lsum (reduced-split pre-charge data driven dynamic sum
dissipation leads to more heating of the circuits resulting in logic) adder logic technique. These designs has lesser power
decreasing battery life span and also need to provide cooling dissipation while operating at higher frequency comparatively,
for the circuit. Therefore, power dissipation affects the battery but still, power dissipation has to be reduced, so it will reduce
life span and overall system cost increases. Most of all digital overall power dissipation in the bigger circuits where
electronic devices discussed are used in the applications like multiplier becomes the prime building block.
DSP’s, microcontrollers, video processing and image II. LITERATURE SURVEY
processing. Various arithmetic and logic operations are used to
perform addition, multiplication, subtraction, division, Study on reduction of power dissipation in the digital
shifting, rotate, etc. The sever necessity for low power system design has being carried out till now. There are two
types of power dissipation in digital systems with CMOS
dissipation had been a high issue in all embedded processor
technology. Switching activity power dissipation called
designs. Power reduction for any system or designs can be
dynamic power dissipation and leakage power dissipation due
satisfied at different design levels, such as threshold voltage to leakage current called static power dissipation in the
scaling and transistor sizing at the semi-conductor chip design transistor. [16]Different techniques have been applied to reduce
Work carried out in Banashree RENEWABLE ENERGY System PVT. Ltd
and Bangalore Institute of Technology
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the dynamic power dissipation such as reducing switching applied for reduction of power. Here, TSMC65nm library is
frequency, reducing switching capacitance, or reducing supply used for designing and implementation. Initially the library was
voltage. Similarly, leakage power reduction is done by analyzed for the complex gates or cells for its functionality.
applying certain techniques such as reducing supply voltage, by Depending on the existing or required functionality, the new
reducing circuit size, by reducing operating temperature or by architecture has been developed for taking into consideration of
increasing transistor threshold voltage. Power, Area and Time delay. Initially, the architecture for full
adder has been developed and verified for the functionality
based on the library cells (technology mapping) and minimal
Power dissipation is a critical designing problem in most of power, the architecture is implemented. The 16-bit multiplier is
the embedded processor design. One of the common and main designed using Dadda algorithm. The multiplier is based on the
part is Arithmetic and Logic Unit in the processor. Usually, optimized full adder architectures designed by analyzing the
ALU’s are implemented using a combinational logic circuit technology library and by using complex gates, so as to
containing more number of functional components for minimize the power dissipation and area which intern reduces
performing different logic and arithmetic operations. ALU’s the overall power and area. A 16-bit Arithmetic and Logical
can be designed with a chain or a tree structure. [16] This can Unit is designed and implemented using the proposed Dadda
be easily modeled or introduced into a processor design Multiplier having the new adder architecture obtained from
environment, so that overall power dissipation is reduced technology mapping technique and CLA which shows power
efficiently for a given application. The results show that the dissipation and area comparatively lower.
power improvement ranges from 43.5% to 49.6% on average
and maximum 46.9% of ALU power reduction can be A. Implementation of Carry Look-Ahead adder (CLA)
obtained. Multiplier with optimized full adder designed using
pass-transistor logic technique since it uses lesser transistors The CLA is faster in operation when it is compared to the
count and small node capacitances and that introduces ripple carry adder. It improves the speed in such a way that, by
minimum delay and speed of operation can be increased. reducing the amount of time required for determining carry
bits. The CLA generates one or more carry bits first and then
To increase speed and to minimize the power the Dadda the sum bit, which reduces the time required for evaluating the
multiplier used with different compressors. The use of result of higher order bits. Here, concept of propagating a carry
compressors in the multipliers not only reduces the vertical i.e., generated from previous stage and generating a carry of
critical path but also reduce the stages of operation that particular stage is used. For every bit to be added, CLA
logic will evaluate whether to generate the carry or propagate
simultaneously. [8]The speed of the Dadda multiplier is
the carry. This lets the circuit to preprocess the two numbers or
improved by introducing different compressors instead of 4:2
bits being added to find out the carry ahead of time.
compressors. In this paper 4:3, 5:3, 6:3 and 7:3 compressors
are used to for reducing the number of stages of addition in the The grouping of the propagate signals and generate signals
multiplication algorithm by reducing the number of half is done to form the higher order bit carry directly. The generate
adders and full adders. [10]Different architectures of full (gi) and propagate (pi) signals are calculated by
adders are designed using two 2-input MUX for generating Consider if ai and bi are two bits, then carry generation and
both sum and carry, two 4-input MUX combination for propagation of carry is given by,
producing sum bit and carry bit, two 2-input XOR gates
followed by two 2-input MUX combination. [1]The model of
4bit multiplier having high speed of operation and low power gi = ( ai & bi ) (1)
using Dadda Algorithm are designed using pass transistor pi = ( ai ^ bi ) (2)
logic. Next, while performing original addition there is no delay
in waiting for the ripple carry effect or time taken for the carry
III. PROPOSED DESIGN METHODOLOGY generated from the initial adder to be passed to the last adder.
Different technology approaches have been involved in
reducing the total power consumption in the VLSI chip design.
Design approaches in each and every category can be even For a 4-bit adder, carry generation at each stage is given by
further classified depending upon the design stages such as
transistor sizing, Logical level, Technology Mapping, power C0 = g0 + p0Cin (3)
gating and RTL level clock gating. Once the optimized logic
equations are obtained, then the equations are mapped on to a C1 = g1 + p1C0 = g1 + p1 (g0 + p0 Cin)
library that contains improved logic gates characteristics in the = g1 + p1g0 + p1 p0 Cin (4)
specified technology node. A typical library contains numerous
logic gates with different transistor sizes having different drive
strengths. Recent technology mapping method uses graph C2 = g2 + p2C1 = g2 + p2g1 + p2 p1 g0 +
covering formulation to target power area and delay. p2 p1 p0 Ci (5)
In this paper, proposed design implementation is based on
the technology mapping technique at logic gate level is often C3 = g3 + p3C2 = g3 + p3g2 + p3 p2 g1 + p3 p2 p1 g0 +
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p3 p2 p1 p0 Cin (6)
Fig.1 shows a 16-bit CLA is designed using four 4-bit CLA
in a ripple carry manner which intern reduces the power
dissipation.
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Table I showing the number of stages of reduction in Dadda multiplier
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IV. EXPERIMENTAL RESULTS AND DISCUSSION 3. ALU with Dadda Multiplier having conventional full adder
The existing design and proposed design are simulated
using ISE simulator and verified for its functionality and then Simulation results for verifying the functionality and
synthesized using the Cadence GENUS EDA tool for the synthesize results of ALU with Dadda Multiplier with
technology node of 65nm using TSMC 65nm library. Conventional full adder and CLA is shows in fig.8
The synthesis result shows the Power, Area and time 16-bit ALU design with existing dadda Multiplier and
delay of each design. By analyzing the results, it is observed carry look-ahead adder is synthesized using TSMC 65nm
that the design proposed has lesser power and area compared library using Cadence GENUS EDA tool and synthesis results
to existing design but with some reasonable increase in the show the power and area of 333536.34nW and 4429.08um2
delay. respectively, with the timing delay of 17301 ps.
The simulation and synthesis is done for both Dadda 4. ALU with Dadda Multiplier with optimized full adder and
Multiplier with proposed full adder and ALU, the results of the carry look ahead adder
experiment are as follows
Simulation results for verifying the functionality and
1. 16-bit Dadda Multiplier with conventional full adder synthesize results of ALU with Dadda Multiplier with
Conventional full adder and CLA is shows in fig.9.
Simulation results for verifying the functionality and
synthesize results of existing 16-bit Dadda Multiplier with 16-bit ALU design with existing dadda Multiplier and
Conventional full adder and CLA is shows in fig 6. carry look-ahead adder is synthesized using TSMC 65nm
library using Cadence GENUS EDA tool and synthesis results
16-bit Dadda multiplier is synthesized using TSMC 65nm show the power and area of 264634.66nW and 4349.16 um2
library using Cadence GENUS EDA tool and synthesis results respectively, with the timing delay of 17301 ps.
show the power and area of 223799.941nW and 2442.24um2
respectively, with the timing delay of 3776 ps. The Table III represents the synthesized results
showing the power, area and timing report of the 16-bit Dadda
2. 16-bit Dadda Multiplier with optimized full adder multiplier with conventional full adder and proposed full
adder. 16-bit ALU results implemented with Dadda multiplier
Simulation results for verifying the functionality and with conventional full adder and proposed full adder.
synthesize results of existing 16-bit Dadda Multiplier with
Conventional full adder and CLA is shows in fig 7.
Fig.9 Simulation results of Arithmetic and Logical Unit with proposed dada
multiplier
Fig.7 Simulation results of 16-bit Dadda Multiplier with optimized full adder
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