8257 DMA Controller:

In microprocessor based systems data transfer can be

controlled by either software or hardware. Upto this point we
have used program instructions to transfer data from I/O
device to memory or from memory to I/O device. To transfer
data by 8257 DMA Controller method microprocessor has to do
following tasks :
1. To fetch the instruction

2. To decode the instruction and

3. To execute the instruction.

To carryout these tasks microprocessor requires considerable

time, so this method of data transfer is not suitable for large
data transfers such as data transfer from magnetic disk or
optical disk to memory. In such situations hardware controlled
data transfer technique is used.
Software Controlled Data Transfer:

In this method programmer executes a series of instructions to

carry out data transfer. The sample flow chart and program
required to transfer data from memory to I/O device is shown
in Fig. 14.59.
Hardware Controlled Data Transfer:

In this technique external device is used to control data

transfer. External device generates address and control signals
required to control data transfer and allows peripheral device
to directly access the memory. Hence this technique is referred
to as Direct Memory Access (DMA) and external device which
controls the data transfer is referred to as DMA controller. Fig.
14.60 shows that how DMA controller operates in a
microprocessor system.
DMA Idle Cycle:

When the system is turned on, the switches are in the A

position, so the buses are connected from the microprocessor
to the system memory and peripherals. Microprocessor then
executes the program until it needs to read a block of data from
the disk. To read a block of data from the disk microprocessor
sends a series of commands to the disk controller device telling
it to search and read the desired block of data from the disk.
When disk controller is ready to transfer first byte of data from
disk, it sends DMA request DRQ signal to the DMA controller.
Then DMA controller sends a hold request HRQ signal to the
microprocessor HOLD input.
The microprocessor responds this HOLD signal by floating its
buses and sending out a hold acknowledge signal HLDA, to the
DMA controller: When the HLDA DMA controller receives the
signal, it sends a control signal to change switch position from A
to B. This disconnects the microprocessor from the buses and
connects 8257 DMA Controller controller to the buses.

DMA Active Cycle:

When DMA controller gets control of the buses, it sends the

memory address where the first byte of data from the disk is to
be written. It also sends a DMA acknowledge, DACK signal to
the disk controller device telling it to get ready for data
transfer. Finally (in case of DMA write operation), it asserts
both the IOR and MEMW signals on the control bus. Asserting
the IOR signal enables the disk controller to output the byte of
data from the disk on the data bus and asserting the MEMW
signal enables the addressed memory to accept data from the
data bus. In this technique data is transferred directly from the
disk controller to the memory location without passing through
the CPU or the DMA controller.
When the data transfer is complete, the 8257 DMA Controller
unasserts the HOLD request signal to the microprocessor and
releases the bus by changing switch position from B to A. After
getting the control of all buses the microprocessor executes the
remaining program.
Features of Microprocessor 8257 DMA Controller:

The Features of Microprocessor 8257 DMA Controller are

follows,
1. It is a programmable; 4-channel, direct memory access
controller. Each channel can be programmed individually.
Therefore, we can interface 4 input/output devices with 8257.
2. Each channel includes a 16-bit DMA address register and a
14-bit counter. DMA address register gives the address of the
memory location and counter specifies the number of DMA
cycles to be performed. As counter is 14-bit, each channel can
transfer 214 (16 kbytes) without intervention of microprocessor.
3. It maintains the DMA cycle count for each channel and
activates a control signal TC (Terminal count) to indicate the
peripheral that the programmed number of DMA cycles are
complete.
4. It provides another control signal MARK to indicate
peripheral that the current DMA cycle is the 128 th cycle since
the previous MARK output.
5. It has priority logic that resolves the peripherals requests.
The priority logic can be programmed to work in two modes,
either in fixed mode or rotating priority mode.
6. It provides inhibit logic which can be used to inhibit
individual channels.
7. It allows data transfer in two modes : burst mode and cycle
steal (single byte transfer) mode.
8. It can execute three DMA cycles : DMA read, DMA write
and DMA verify.
9. Auto load Features of 8257 permits repeat block or block
chaining operations.
10. It operates in two modes : slave and master.
11. When DMA is in master mode, AEN signal provided by 8257
allows to isolate CPU buffers, latches and other devices from
the system bus.
12. Extended write mode of 8257 prevents the unnecessary
occurrence of wait states in the Features of 8257 ; increasing the
system throughput.
13. It operates on single TEL clock and it is completely TEL
compatible.
14. It can be interfaced with all Intel
15. It transfers one byte of data in four clock cycles. Thus giving
high transfer rate such as 500 Kbytes/second at 2 MHz clock
input.
16. Like 8085, Features of 8257 also has READY input which
allows 8257 to interface slower memory or I/O devices that can
not meet bus setup times required by the 8257.
8257 Pin Diagram:

Fig. 14.61 shows 8257 Pin Diagram.

Data Bus (D0-D7) : These are bi-directional tri-state signals
connected to the system data bus. When CPU is having control
of system bus it can access contents of address register, status
register, mode set register, and a terminal count register and it
can also program, control registers of DMA controller, through
the data bus.
During DMA cycles these lines are used to send the most
significant bytes of the memory address from one of the
8257 Pin Description:

Address Bus (A0-A3 and A4-A7) : The four least significant lines

A0-A3 are bi – directional tri – state signals. In the idle cycle they
are inputs and used by the CPU to address the register to be
loaded or read. In the Active cycle they output the lower 4 bits
of the address for DMA operation. A4-A7 are unidirectional lines,
provide 4-bits of address during DMA service.
Address Strobe (ADSTB) : This signal is used to demultiplex
higher byte address and data using external latch.
Address Enable (AEN) : This active high signal enables the 8-bit
latch containing the upper 8-address bits onto the system
address bus. AEN can also be used to disable other system bus
drivers during DMA transfers.
Memory Read and  Memory Write ( MEMR, MEMW) : These
are active low tri-state signals. The MEMR signal used to access
data from the addressed memory location during a DMA read
or memory-to-memory transfer and MEMW signal is used to
write data to the addressed memory location during DMA write
or memory to memory transfer.
I/O Read and I/O Write ( IOR and IOW ) : These are active low
bi-directional signals. In idle cycle, these are an input control
signals used by CPU to read/write the control registers. In the
active cycle IOR signal is used to access data from a peripheral
and IOW signal is used to send data to the peripheral.
Chip Select (CS) : This is an active low input, used to select the
8257 as an I/O device during the idle cycle. This allows CPU to
communicate with 8257 Pin Diagram.
Reset : This active high signal clears, the command, status,
request and temporary registers. It also clears the first/last flip-
flop and sets the Master Register. After reset the device is in
the idle cycle.
Ready : This input is used to extend the memory read and write
signals from the 8257 to interface slow memories or I/O
devices.
Hold request (HRQ) : Any valid DREQ causes 8257 to issue the
HRQ. It is used for requesting CPU to get the control of system
bus.
Hold Ackmiwledge (HLDA) : The active high Hold Acknowledge
from the CPU indicates that it has relinquished control of the
system bus.
DREQ0-DREQ3 : These are DMA request lines, which are
activated to obtain DMA service, until the corresponding DACK
signal goes active.
DACK0-DACK3 : These are used to indicate peripheral devices
that the DMA request is granted.
Terminal Count (TC) : This is active high signal concern with the
completion of DMA service. The TC output signal is activated at
the end of DMA service, i.e. when present cycle is a last cycle
for the current data block.
MARK : This output notifies the selected peripheral that the
current DMA cycle is the 128th cycle since the previous MARK
output. MARK always occurs at 128 (all multiplies of 128) cycles
from the end of the data block.

8257 Block Diagram:

Fig. 14.62 shows the functional 8257 Block
Diagram.

Data Bus Buffer:

It is a tri-state, bi-directional, eight bit buffer which interfaces
the 8257 to the system data bus. In the slave mode, it is used to
transfer data between microprocessor and internal registers of
8257. In master mode, it is used to send higher byte address
(A8-A15) on the data bus.
Read/Write logic:

When the CPU is programming or reading one of the internal

registers of 8257 Pin Diagram (i.e, when the 8257  is in the slave
mode), the Read/Write logic accepts the I/O Read (IOR) or I/O
Write (IOW) signal, decodes the the least significant four
addiess bits (A0 – A3) and either writes the contents of the data
bus into the addressed register (if IOW is low) or places the
contents of the addressed register onto the data bus (if IOR is
low).
During DMA cycles (i.e. when the 8257 is in the master mode)
the Read/Write logic generates the I/O read and memory write
(DMA write cycle ) or I/O write and memory read (DMA read
cycle) signals which control the data transfer between
peripheral and memory device.

8257 DMA Controller Operating Modes:

The 8257 Pin Diagram provides four identical channels, labeled
CH0 to CH3. Each channel has two sixteen bit registers:
1. A DMA address register, and
2. A terminal count register.
3.
DMA address register : Fig. 14.63 shows the format of DMA
address register. It specifies the address of the first memory
location to be accessed. It is necessary to load valid memory
address in the DMA address register before channel is enabled.

Terminal Count Register : Fig. 14.64  shows the format of

Terminal Count register.
Note : N is number of bytes to be transferred.
The value loaded into the low order 14 bits (C 13 — C0) of the
terminal count register specifies the number of DMA cycles
minus one before the terminal count (TC) output is activated.
Therefore, for N number of desired DMA cycles it is necessary
to load the value N-1 into the low order 14-bits of the terminal
count register. The most significant 2 bits of the terminal count
register specifies the type of DMA operation to be performed.
It is necessary to load count for DMA cycles and operational
code for valid DMA cycle in the terminal count register before
channel is enabled.
Control logic:

It controls the sequence of operations during all DMA cycles

(DMA read, DMA write, DMA verify) by generating the
appiopriate control signals and the 16-bit address that specifies
the memory location to be accessed. It consists of mode set
register and status register. Mode set register is programmed
by the CPU to configure 8257 whereas the status register is
read by CPU to check which channels have reached a terminal
count condition and status of update flag.
Mode Set Register:

Fig. 14.65 gives the format of mode set register. Least

significant four bits of mode set register, when set, enable each
of the four DMA channels. Most significant four bits allow four
different options for the 8257 Pin Diagram.
It is normally programmed by the CPU after initializing the DMA
address registers and terminal count registers. It is cleared by
the RESET input, thus disabling all options, inhibiting all
channels, and preventing bus conflicts on power-up.

Status Register:

Fig. 14.66 shows the status register format. As said earlier, it

indicates which channels have reached a terminal count
condition and includes the update flag described previously.
The TC status bit, if one, indicates terminal count has been
reached for that channel. TC bit remains set until the status
register is read or the 8257 is reset. The update flag, however,
is not affected by a status read operation.
The update flag bit, if one, indicates CPU that 8257 is executing
update cycle. In update cycle 8257 loads parameters in channel
3 to channel 2.
Priority Resolver:

It resolves the peripherals requests. It can be programmed to

work in two modes, either in fixed mode or rotating priority
mode.
Operating Modes of 8257:

The Operating Modes of 8257 can be programmed to operate

in following modes :
Rotating Priority Mode :

In rotating priority mode, the priority of the channels has a

circular sequence. In this, channel being serviced gets the
lowest priority and the channel next to it gets the highest
priority as shown in Fig. 14.67.

Thus, with rotating priority in a single chip DMA system, any

device requesting service is guaranteed to be recognized after
no more than Jhree higher priority services have occurred. This
the system.
prevents any one channel from monopolizing
The rotating priority mode can be set by writing
logic ‘1’ in the bit 4 of the mode set register.
Fixed Priority Mode :

In the fixed priority, channel 0 has the highest priority and

channel 3 has the lowest priority. Table 14.5 shows the priority
ratings.

In the fixed priority, after recognition of any one channel for

service, the other channels are prevented from interfering with
that service until it is completed. If bit 4 of mode set register is
logic 0, Operating Modes of 8257 operates in fixed priority
mode.
Extended Write Mode :

Microcomputer systems allow use of various types of memory

and I/O devices with different access time. If a device can not
be accessed within a specific amount of time it returns a “not
ready” indication to the 8257 that causes the 8257 to insert one
or more wait states in its internal sequencing. The extended
write option provides alternative timing for the I/O and
memory write signals which allows the devices to return an
early READY and prevents the unnecessary occurrence of wait
states in the Operating Modes of 8257. It does this by activating
MEMW and IOW signals earlier in the DMA cycle, giving more
setup time.
TC STOP Mode :

If the TC stop bit is set, a channel is disabled (i.e. its enable bit is
reset) after the terminal count (TC) output goes high, thus
automatically preventing further DMA operation on that
channel. To enable DMA operation on the channel it is
necessary to set enable bit of the corresponding channel in the
mode set register. If the TC STOP bit is not set, the occurrence
of the TC output has no effect on the channel enable bits.
Auto Load Mode :

Auto load Mode when enabled, permits block chaining

operations, without immediate software intervention between
blocks. In this mode, channel 2 parameters (DMA starting
address, terminal count and DMA transfer mode) are initialized
as usual for the first data block. These parameters are
automatically duplicated in the channel 3 registers when
channel 2 is initialized. After the first block of DMA cycles is
executed by channel 2 (i.e., after the TC output goes high), the
parameters stored in the channel 3 registers are transferred to
channel 2 during an ‘update’ cycle and next block of DMA cycle
is executed. This repeat block operations can be used in
applications such as CRT refreshing.
During the update cycle, it is necessary to prevent the CPU from
inadvertently skipping a data block by overwriting a starting
address or terminal count in the channel 3 registers before
those parameters are properly auto-loaded into channel 2.
DMA Cycles:

DMA READ : In this cycle, data is transferred from memory to

I/O device.
DMA Write : In this cycle, data is transferred from I/O device to
memory.
DMA Verify : In this cycle, data is not transferred between
memory and I/O It is used by the, peripheral device to verify
the data that has been recently transferred. To avoid
overwriting registers of channel 3, update flag in the
status register can be monitored by the CPU.
Note : 1. In the auto load mode, channel 3 is still available to
the user if the channel 3 enable bit is set, but use of this
channel will change the values to be auto loaded into channel 2
at update time. 2. In the auto load mode, TC stop feature has
no effect on channel 2.
Data Transfer modes in DMA:

1. The 8237 works in two modes i.e., master and slave

modes.
2. In slave mode, the 8237 functions as an input/output
device. In this mode the system buses arc controlled by
 microprocessor and hence the microprocessor is
connected to the system bus.
3. In master mode 8237 becomes the bus master and hence
the microprocessor is isolated from the system bus. This
isolation is done by AEN signal.
4. In minimum configuration, 8237 DMA controller is used to
transfer the data. The peripheral chips are interface as
normal 10 ports. Figure shows the interfacing of DMA
controller with 8086.
5. In minimum mode the HOLD and HLDA signals are used to
bus arbitration and in maximum mode configuration
RQ_0/GT_0; and RQ_1/GT_1.
6. The 8237 outputs only 16-bit memory address but not the
complete 20-bit address of 8086. To store the remaining
four address hits A_16—A_19 a separate page latch is
required.
7. The 8237 is not compatible with 8086 in its maximum
mode configuration. This is because RQ/GT is not
compatible with HRQ and HLDA of 8237.
8. So if 8086 is to be interfaced with DMA controller, then
8089 10 processor is required.
9. The 8089 interfaces to the 8086's local multiplexed buses.
It shares the bus buffers and system controller of the host
system. It is compatible with the RQ/GT signals of 8086
and outputs the complete 20-bit address.
 FIG:Interfacing DMA WITH 8086
Different data transfer modes of 8237 DMA controller:
The 8237 is in the idle cycle if there is no pending request or
the 8237 is waiting for a request from one of the DMA
channels. Once a channel requests a DMA service, the 8237
sends the HOLD request to the CPU using its HRQ pin. If the
CPU acknowledges the hold request on HLDA, the 8237 enters
an active cycle. In the active cycle, the actual data transfer
takes place in one of the following transfer modes as is
programmed.

1. Single Transfer Mode: In this mode, the device transfers

only one byte per request. The word count is decremented
and the address is decremented or incremented
(depending on programming) after each such transfer. The
Terminal Count (TC) state is reached when the count
becomes zero. For each transfer the DREQ must be active
until the DACK is activated, in order to get recognized.
After TC the bus will be relinquished for the CPU. For a
new DREQ to 8237 it will again activate the HRQ signal to
the CPU and the HLDA signal from the CPU will push the
8237 again into the single transfer mode. This mode is also
called as 'cycle stealing'.
2. Block Transfer Mode: In this mode, the 8237 is activated
by DREQ to continue the transfer until a TC is reached, i.e.
a block of data is transferred. The transfer cycle may be
terminated due to EOP (either internal or external) which
forces Terminal Count (TC). The DREO needs to be
activated only till the DACK signal is activated by the DMA
controller. Auto-initialization may be programmed in this
mode.
3. Demand Transfer Mode: In this mode, the device
continues transfers until a TC is reached or an external
EOP is detected or the DREQ signal goes inactive. Thus a
transfer may exhaust the capacity of data transfer of an
I/O device. After the I/O device is able to catch up the
 service may be re-established activating the DREQ signal
again. Only the EOP generated by TC or external EOP can
cause the auto-initialization, and only if it is programmed
for.
4. Cascade Mode: In this mode, more than one 8237 can be
connected together to provide more than four DMA
channels. The HRQ and HLDA signals from additional 8237s
are connected with DREQ and DACK pins of a channel of
the host 8237 respectively. The priorities of the DMA
requests may be preserved at each level. The first device is
only used for prioritizing the additional devices (slave
8237s), and it does not generate any address or control
signal of its own. The host 8237 responds to DREQ
generated by slaves and generates the DACK and the HRQ
signals to coordinate all the slaves. All other outputs of the
host 8237 are disabled.
5. Memory to memory Transfer: To perform the transfer of a
block of data from one set of memory address to another
one, this transfer mode is used. Programming the
corresponding mode bit in the command word, sets the
channel 0 and I to operate as source and destination
channels, respectively. The transfer is initialized by setting
the DREQ0 using software commands. The 8237 sends
HRQ (Hold Request) signal to the CPU as usual and when
the HLDA signal is activated by the CPU. the device starts
operating in block transfer mode to read the data from
memory. The channel 0 current address register acts as a
source pointer. The byte read from the memory is stored
in an internal temporary register of 8237. The channel 1
current address register acts as a destination pointer to
write the data from the temporary register to the
destination memory location. The pointers are
automatically incremented or decremented, depending
upon the programming. The channel 1 word count register
is used as a counter and is decremented after each
transfer. When it reaches zero, a TC is generated, causing
EOP to terminate the service. The 8237 also responds to
external EOP signals to terminate the service. This feature
may be used to scan a block of data for a byte. When a
match is found the process may be terminated using the
external EOP. Under all these transfer modes, the 8237
carries out three basic transfers namely, write transfer,
read transfer and verify transfer. In write transfer, the
8237 reads from an I/O device and writes to memory
under the control of IOR and MEMW signals. In read
transfer, the 8237 reads from memory and writes to an I/O
device by activating the MEMR and IOW signals. In verify
transfers, the 8237 works in the same way as the read or
write transfer but does not generate any control signal.