The RISC-V Processor: Hakim Weatherspoon CS 3410
The RISC-V Processor: Hakim Weatherspoon CS 3410
The RISC-V Processor: Hakim Weatherspoon CS 3410
Hakim Weatherspoon
CS 3410
Computer Science
Cornell University
2
Announcements
Check online syllabus/schedule
• http://www.cs.cornell.edu/Courses/CS3410/2019sp/schedule
• Slides and Reading for lectures
• Office Hours
• Pictures of all TAs
• Project and Reading Assignments
• Dates to keep in Mind
• Prelims: Tue Mar 5th and Thur May 2nd
• Proj 1: Due next Friday, Feb 15th
• Proj3: Due before Spring break
• Final Project: Due when final will be Feb 16th
Schedule is subject to change
3
Collaboration, Late, Re-grading Policies
•“White Board” Collaboration Policy
• Can discuss approach together on a “white board”
• Leave, watch a movie such as Black Lightening, then write up
solution independently
• Do not copy solutions
Late Policy
• Each person has a total of five “slip days”
• Max of two slip days for any individual assignment
• Slip days deducted first for any late assignment,
cannot selectively apply slip days
• For projects, slip days are deducted from all partners
• 25% deducted per day late after slip days are exhausted
Regrade policy
• Submit written request within a week of receiving score
4
Announcements
• Level Up (optional enrichment)
• Teaches CS students tools and skills needed in
their coursework as well as their career, such as
Git, Bash Programming, study strategies, ethics in
CS, and even applying to graduate school.
• Thursdays at 7-8pm in 310 Gates Hall,
starting this week
• http://www.cs.cornell.edu/courses/cs3110/2019sp/levelup/
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Big Picture: Building a Processor
inst
memory
register alu
file
+4 +4
addr
=?
PC din dout
offset control cmp
memory
new target
imm
pc extend
7 7
RISC-V Register File
inst
memory
register alu
file
+4 +4
addr
=?
PC din dout
offset control cmp
memory
new target
imm
pc extend
WE RW RA RB
1 5 5 5
9
RISC-V Register File
• RISC-V register file
• 32 registers, 32-bits each 32 W x0 A 32
• x0 wired to zero x1
• Write port indexed via RW … B 32
- on falling edge when WE=1
• Read ports indexed via RA, RB x31
WE RW RA RB
• RISC-V register file 1 5 5 5
• Numbered from 0 to 31
• Can be referred by number: x0, x1, x2, … x31
• Convention, each register also has a name:
- x10 – x17 a0 – a7, x28 – x31 t3 – t6
8
RISC-V Memory
inst
memory
register alu
file
+4 +4
addr
=?
PC din dout
offset control cmp
memory
new target
imm
pc extend
12
Putting it all together: Basic Processor
inst
memory
register alu
file
+4 +4
addr
=?
PC din dout
offset control cmp
memory
new target
imm
pc extend
Architectures
• von Neumann architecture
• Harvard (modified) architecture
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To make a computer
Need a program
• Stored program computer
• (a Universal Turing Machine)
Architectures
• von Neumann architecture
• Harvard (modified) architecture
15
Putting it all together: Basic Processor
A RISC-V CPU with a (modified) Harvard
architecture
• Modified: instructions & data in common address space,
separate instr/data caches can be accessed in parallel
Registers 00100000001
00100000010
Control 00010000100
ALU data, address,
...
control
Data
CPU 10100010000
Memory
10110000011
00100010101
...
Program
Memory 16
Takeaway
A processor executes instructions
• Processor has some internal state in storage
elements (registers)
A memory holds instructions and data
• (modified) Harvard architecture: separate insts and
data
• von Neumann architecture: combined inst and data
A bus connects the two
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Instruction Processing
Prog
inst
Mem Reg. ALU
File Data
Mem
+4
555
PC
control
Instructions: A basic processor
stored in memory, encoded in binary • fetches
00100000000000100000000000001010 • decodes
00100000000000010000000000000000
00000000001000100001100000101010 • executes
one instruction at a
time
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Levels of Interpretation: Instructions
for (i = 0; i < 10; i++) High Level Language
• C, Java, Python, ADA, …
printf(“go cucs”);
• Loops, control flow, variables
21
Takeaway
A RISC-V processor and ISA (instruction set
architecture) is an example a Reduced
Instruction Set Computers (RISC) where
simplicity is key, thus enabling us to build it!!
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Next Goal
How are instructions executed?
What is the general datapath to execute an
instruction?
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Five Stages of RISC-V Datapath
Prog. inst ALU
Mem Reg.
File Data
Mem
+4
555
PC
control
25
Stage 1: Instruction Fetch
Prog. inst ALU
Mem Reg.
File Data
Mem
+4
555
PC
control
31
Next Goal
• Specific datapaths RISC-V Instructions
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RISC-V Design Principles
Simplicity favors regularity
• 32 bit instructions
Smaller is faster
• Small register file
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Instruction Types
• Arithmetic
• add, subtract, shift left, shift right, multiply, divide
• Memory
• load value from memory to a register
• store value to memory from a register
• Control flow
• conditional jumps (branches)
• jump and link (subroutine call)
34
RISC-V Instruction Types
• Arithmetic/Logical
• R-type: result and two source registers, shift amount
• I-type: result and source register, shift amount in 16-bit
immediate with sign/zero extension
• U-type: result register, 16-bit immediate with sign/zero
extension
• Memory Access
• I-type for loads and S-type for stores
• load/store between registers and memory
• word, half-word and byte operations
• Control flow
• U-type: jump-and-link
• I-type: jump-and-link register
• S-type: conditional branches: pc-relative addresses
35
RISC-V instruction formats
All RISC-V instructions are 32 bits long, have 4
formats
• R-type funct7 rs2 rs1 funct3 rd op
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
37
Arithmetic and Logic
Prog. ALU
Mem Reg.
File
+4
555
PC
control
38
R-Type (2): Shift Instructions
0000000001100010000101000011011
funct7 rs2 rs1 funct3 rd op
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
39
Shift
Prog. ALU
Mem Reg.
File
+4
555
PC
control
40
I-Type (1): Arithmetic w/ immediates
00000000010100101000001010010011
imm rs1 funct3 rd op
12 bits 5 bits 3 bits 5 bits 7 bits
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Arithmetic w/ immediates
Prog. ALU
Mem Reg.
File
+4
555
PC
control
imm
extend
16 12
shamt
op mnemonic description
0110111 LUI rd, imm R[rd] = imm << 16
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Load Upper Immediate
Prog. ALU
Mem Reg.
File
0x50000
+4
555
PC
control 16
imm
extend
16 12
shamt
✔
• R-type: result and two source registers, shift amount
• I-type: result and source register, shift amount in 16-bit
immediate with sign/zero extension
• U-type: result register, 16-bit immediate with sign/zero
extension
• Memory Access
• I-type for loads and S-type for stores
• load/store between registers and memory
• word, half-word and byte operations
• Control flow
• U-type: jump-and-link
• I-type: jump-and-link register
• S-type: conditional branches: pc-relative addresses
45
RISC-V Instruction Types
• Arithmetic/Logical
✔
• R-type: result and two source registers, shift amount
• I-type: result and source register, shift amount in 16-bit
immediate with sign/zero extension
• U-type: result register, 16-bit immediate with sign/zero
extension
• Memory Access
• I-type for loads and S-type for stores
• load/store between registers and memory
• word, half-word and byte operations
• Control flow
• U-type: jump-and-link
• I-type: jump-and-link register
• S-type: conditional branches: pc-relative addresses
46
Summary
We have all that it takes to build a processor!
• Arithmetic Logic Unit (ALU)
• Register File
• Memory