IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 3, NO.

3, SEPTEMBER 1995

Power Estimation Methods

for Sequential Logic Circuits
Chi-Ying Tsui, JosC Monteiro, Massoud Pedram, Member, IEEE, Srinivas Devadas, Member, IEEE,
Alvin M. Despain, Member, ZEEE, and Bill Lin

Abstruct- Recently developed methods for power estimation the increasing scale of integration, we believe that power
have primarily focused on combinational logic. We present a dissipation will assume greater importance, especially in multi-
framework for the efficient and accurate estimation of average chip modules where heat dissipation is one of the biggest
power dissipation in sequential circuits.
Switching activity is the primary cause of power dissipation problems.
in CMOS circuits. Accurate switching activity estimation for Power dissipation of a circuit, like its area or speed, may
sequential circuits is considerably more difficult than that for be significantly improved by changing the circuit architecture
combinational circuits, because the probability of the circuit or the base technology [3]. However, once these architectural
being in each of its possible states has to be calculated. The
Chapman-Kolmogorov equations can be used to compute the or technological improvements have been made, it is the
exact state probabilities in steady state. However, this method switching of the logic that will ultimately determine the power
requires the solution of a linear system of equations of size dissipation.
where N is the number of flip-flops in the machine. Methods for the power estimation of logic-level combi-
We describe a comprehensive framework for exact and ap- national circuits based on switching activity estimation have
proximate switching activity estimation in a sequential circuit.
The basic computation step is the solution of a nonlinear system been presented previously (e.g., [2], [4], [7], [9], [lo], [13]).
of equations which is derived directly from a logic realization of Power and switching activity estimation for sequential circuits
the sequential machine. Increasing the number of variables or the is significantly more difficult, because the probability of the
number of equations in the system results in increased accuracy. circuit being in any of its possible states has to be computed.
For a wide variety of examples, we show that the approximation Given a circuit with N flip-flops, there are 2N possible states.
scheme is within 1-3% of the exact method, but is orders of
magnitude faster for large circuits. Previous sequential switching These state probabilities are, in general, not uniform. As an
activity estimation methods can have significantly greater inac- example, consider the sequential circuit of Fig. 1 and the
curacies. example State Transition Graph of Fig. 2. Assuming that the
circuit was in state R at time 0, and that at each clock cycle
random inputs are applied, at time M (i.e., steady state) the
I. INTRODUCTION probabilities of the circuit being in state R, A, B, C are
i, i, i,
$, and respectively. These state probabilities have to
F OR MANY consumer electronic applications low average
power dissipation is desirable and for certain special be taken into account during switching activity estimation of
applications low power dissipation is of critical importance. the combinational logic part of the machine. Power dissipation
For applications such as personal communication systems and and switching activity of CMOS combinational logic are
hand-held mobile telephones, low-power dissipation may be modeled by randomly applied vector pairs. In the case of
the tightest constraint in the design. More generally, with sequential circuits, the vector pair (211, 212) applied to the
combinational logic is composed of a primary input part and a
present state part (see Fig. l), namely (ilQs1, i2Q.52). Given
Manuscript received June 15, 1994; revised February 20, 1995 and March il@sl, the next state s2 is uniquely determined given the
31, 1995. The work of C.-Y. Tsui and A. M. Despain was supported in part by functionality of the combinational logic. For example, if il
the Advanced Research Projects Agency under Contract J-FBI-91-194. The happens to be 0 and the machine of Fig. 2 is in state R, the
work of M. Pedram was supported in part by the Advanced Research Projects
Agency under Contract F33615-95-C-1627, and by the SRC under Contract machine will move to state B. This correlation between the
94-DJ-559. The work of J. Monteiro’s and S. Devadas was supported in part applied vector pairs has to be taken into account in order to
by the Advanced Research Projects Agency under Contract DABT63-94-C- obtain accurate estimates of the switching activity in sequential
0053, and in part by a NSF Young Investigator Award with matching funds
from Mitsubishi Corporation. circuits.
C.-Y. Tsui is with the Department of Electrical Engineering, Hong Kong A first attempt at estimating switching activity in logic-
University of Science and Technology, Hong Kong. level sequential circuits was presented in [4]. This method can
M. Pedram and A. Despain are with the Department of Electrical Engineer-
ing, University of Southem Califomia, Los Angeles, CA 90089 USA. accurately model the correlation between the applied vector
J. Monteiro and S. Devadas are with the Department of Electrical Engineer- pairs, but assumes that the state probabilities are all uniform.
ing and Computer Science, Massachusetts Institute of Technology, Cambridge, Extensions of this method can produce accurate estimates for
MA 02139 USA.
B. Lin is with IMEC, Belgium, France. acyclic sequential circuits such as pipelines, but not for more
IEEE Log Number 9413459. general cyclic circuits [SI.
1063-8210/95$04.00 0 1995 IEEE
TSUI et al.: POWER ESTIMATION METHODS FOR SEQUENTIAL LOGIC CIRCUITS 40.5

Section 111, we describe an exact switching activity estimation

method for sequential circuits. In Section lV, we first provide
U
4 c
the basis for the approximation schemes we have developed
b and formulate the problem of estimating switching activity
a Combinational Logic
as that of solving a nonlinear system of equations. We de-
4
h - - scribe a scheme based on the notion of a k-unrolled network
A
that can be used to improve the accuracy of estimation in
Section V. We describe a different method to improve the
accuracy based on the notion of a m-expanded network in
Section VI. In Section VI1 we describe methods to solve the
nonlinear system of equations, namely, the Picard-Peano and
the Newton-Raphson methods. In Section VIII, we show that
purely combinational logic estimation methods can provide
inaccurate estimates, whereas the developed approximation
methods produce accurate estimates while being applicable
to large circuits.

11. PRELIMINARIES

A. A Power Dissipation Model

Under a simplified model of the energy dissipation in CMOS
circuits, the energy dissipation of a CMOS circuit is directly
related to the switching activity.
In particular the three simplifying assumptions are:
The only capacitance is at the output node of a CMOS
gate (this capacitance includes the sourcedrain capaci-
tance of the gate itself and the input capacitances of the
fanout gates).
lfl Current is flowing either from Voo to the output capacitor
Fig. 2. Example state transition graph. or from the output capacitor to ground (that is, there is
no short-circuit current).
Any change in a logic-gate output voltage is a change
In this paper, we present results obtained by using the from V,, to ground or vice-versa (that is, there are no
Chapman-Kolmogorov equations for discrete-time Markov stable intermediate voltage levels).
Chains [12] to compute the exact state probabilities of the These assumptions are reasonably justified for well-
machine. The Chapman-Kolmogorov method requires the designed CMOS gates [ 5 ] and when combined, imply that
solution of a linear system of equations of size 2 N , where N the energy dissipated by a CMOS logic gate each time its
is the number of flip-flops in the machine. Thus, this method output changes is roughly equal to the change in energy
is limited to circuits with relatively small number of flip-flops, stored in the output capacitance seen by the gate. If the gate
since it requires the explicit consideration of each state in the is part of a synchronous digital system controlled by a global
circuit. clock, it follows that the average power dissipated by the gate
We next describe an approximate method for switching is given by:
activity estimation in sequential circuits. The basic computa-
tion step is the solution of a nonlinear system of equations
which is derived directly from the logic realization of the
next state logic of the machine under consideration. Increasing
the number of variables or the number of equations in the where Pavsdenotes the average power, Cload is the load
system results in increased accuracy. For a wide variety of capacitance, v , d is the supply voltage, Tcycis the global
examples, we show that the approximation scheme is within clock period, and E(transitions) is the expected value of the
1-3% of the exact method, but is orders of magnitude faster for number of gate output transitions per global clock cycle [9],
large circuits. Previous sequential switching activity estimation or equivalently the average number of gate output transitions
methods can have significantly greater inaccuracies. per clock cycle. All of the parameters in (1) can be deter-
The rest of this paper is organized as follows. In Section mined from technology or circuit layout information except
I1 we briefly review the physical model for power estimation E(transitions), which depends on the logic function being
and summarize the combinational estimation method of [4]. In performed and the statistical properties of the primary inputs.
406 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 3, NO. 3, SEPTEMBER 1995

Symbolic
Simulation
Equations

Fig. 3. Taking correlation into account.

Equation (1) is used by the power estimation techniques simulation method takes into account the correlation due
such as [4], [9] to relate switching activity to power dissipa- to reconvergence of input signals and accurately measures
tion. switching activity.
The same computation can be performed more efficiently,
although not exactly, using probabilistic simulation techniques
B. Combinational Circuits
such as [lo] and [13] or Monte-Carlo simulation [ 2 ] . In the
Average power can be estimated for combinational circuits remainder of this paper, whenever we need to perform the
by computing the average switching activity at every gate in above computation, we will refer to the symbolic simula-
the circuit. tion equations (which provide the exact solution). It should
It is assumed that we are given transition probabilities at however be made clear that any other solution technique
each of the primary inputs to the circuit. That is, for every (probabilistic simulation, Monte-Carlo simulation, etc.) can be
primary input the probability of the primary input staying at used instead.
0 (0 + 0), staying at 1(1 + l),making a 0 + 1transition and
making a 1 + 0 transition are given. Given these probabilities,
111. RIE EXACTMETHOD
the average switching activity at each gate in the circuit can
be calculated.
A symbolic simulation method that performs this compu- A. Modeling Correlation
tation was given in [4]. Under the chosen gate delay model, To model the correlation between the two vectors in a
the method first constructs a Boolean function representing the randomly applied vector pair, we have to augment the com-
logical value at any gate output at each time point 2 t based on binational estimation method described in Section 11-B. This
the primary input variables IO applied at time 0 and I t applied augmentation is summarized in Fig. 3.
at time t. For instance, one may compute the functions fi (t+1) In Fig. 3, we have a block corresponding to the symbolic
+
and f i ( t 2 ) for a particular gate gi. The Boolean conditions simulation equations for the combinational logic of the general
at the inputs that correspond to a 0 + 1 transition on gi sequential circuit shown in Fig. 1. The symbolic simulation
+ +
between times t 1 and t 2 are represented by the function equations have two sets of inputs, namely ( I 0 , l t ) for the
+ +
f i ( t 1) . f i ( t 2 ) . The probability of a 0 + 1 transition primary inputs and ( P S ,N S ) for the present state lines.
+ +
occurring between time t 1 and t 2 given the transition However, given IO and P S , N S is uniquely determined by
probabilities at the primary inputs is the probability of the the functionality of the combinational logic. This is modeled
+ +
Boolean function fi(t 1). f i ( t 2 ) evaluating to a 1. (This by prepending the next state logic to the symbolic simulation
probability can be evaluated exactly using Binary Decision equations.
Diagrams 111 or approximately using Monte Carlo simulation.) The configuration of Fig. 3 implies that the gate output
For each gate, probabilities of transitions occurring at any switching activity can be determined given the vector pair
time point can be evaluated efficiently, and these probabilities (IO,I t ) for the primary inputs, but only PS for the state lines.
are summed over all the time points to obtain the average Therefore, to compute gate output transition probabilities, we
switching activity (at each gate). require the transition probabilities for the primary input lines,
Under the zero delay, unit delay, or a general delay model and the static probabilities for the present state lines. This
(where delays are obtained from library cells), the symbolic configuration was originally proposed in [4].
TSUI et al.: POWER ESTIMATION METHODS FOR SEQUENTIAL LOGIC CIRCUITS 407

B. State Probability Computation C. Power Estimation Given Exact State Probabilities

The static probabilities for the present state lines marked We now describe a power estimation method that uti-
PS in Fig. 3 are spatially correlated. We therefore require lizes the exact state probabilities obtained using the Chap-
knowledge of present state probabilities as opposed to present man-Kolmogorov method. As described in Section 11-B, the
state line ( P S ) probabilities in order to exactly calculate symbolic equations express the exact switching conditions for
the switching activity in the sequential machine. The state each gate in the circuit under the unit or general delay models.
probabilities are dependent on the connectivity of the State Prepending the next state logic block as illustrated in Fig. 3
Transition Graph (STG) of the circuit. accounts for the correlation between the present and next
For each state s;, 1 5 i 5 K in the STG, we associate a states. Finally, computing the exact state probabilities models
variable prob(si) corresponding to the steady-state probability the steady-state behavior of the circuit.
of the machine being in state si at t = ca. For each edge As described in Section 11-B,power estimation of a given
e in the STG, we have e.Current signifying the state that combinational logic circuit can be carried out by creating a set
the edge fans out from, e . N e z t signifying the state that the of symbolic functions such that summing the signal probabil-
edge fans out to, and e . I n p u t signifying the input combination ities of the functions corresponds to the average switching
corresponding to the edge. Given static probabilities for the activity in the original combinational circuit. Some of the
primary inputs to the machine, we can compute prob(Input), inputs to the created symbolic functions are the present state
the probability of the combination I n p u t occurring.' We can lines of the circuit and the others are primary input lines. Each
compute prob(e.Input) using: binary combination of the present state lines is a state in the
circuit and we have a number corresponding to the state prob-
prob(e.Input) = prob(e.Current) x prob(1nput)
ability for each state after solving the Chapman-Kolmogorov
For each state s; we can write an equation: equations.
prob(si) = c
V e such t h a t e.Next = s x
prob( e . l n p u t )
The signal probability calculation procedure has to appro-
priately weight these combinations according to the given
probabilities. Suppose n is a disjoint cover of the function
Given K states, we obtain K equations out of which any one f, i.e.,
equation can be derived from the remaining K - 1 equations.
We have a final equation:
K
f= v
m E Disjoint-Cover(n)
Cm (2)

prob(s;) = 1.
i=l where the Cm's are cubes of the disjoint cover. Each C, is
This linear set of K equations can be solved to obtain the a function of the present state lines and primary inputs. We
different prob( s;) 's. partition the inputs to C, into two groups: the symbolic state
This system of equations is known as the Chap- support SS, which includes all states si that have set the
man-Kolmogorov equations for a discrete-time appropriate state bits, and the primary input support I , which
discrete-transition Markov process. Indeed, if the Markov includes the P I inputs of C,. Hence C, = SSmI,. The
process satisfies the conditions that it has a finite number of signal probability of n is thus given by:
states, its essential states form a single-chain and it contains
no periodic-states, then the above system of equations will
have a unique solution [12].
prob(n) = c
m E Disjoint-Cover(n)
prob(Cm). (3)

For example, for the State Transition Graph of Fig. 2 we

will obtain the following equations assuming a probability of Since the primary inputs are independent of the state that the
0.5 for the primary input being a 1. machine is currently in and states of the FSM are distinct, we
prob(R) = 0.5 x prob(A) can write
p r o b ( A ) = 0.5 x p r o b ( R )
+ 0.5 x prob(B)
+ 0.5 x prob(C)
prob(B) = 0.5 x prob(R)
+ 0.5 x prob(A). From (3) and (4), we have:
The final equation is:
prob(R) + prob(A) + prob(B) + prob(C) = 1. prob(n) = c
m E Disjoint-Cover(n)
prob(lm)
s,E ss,
prob(si).

Solving this linear system of equations results in the state (5)

As an example, consider the following disjoint cover of a
probabilities, prob(R) = k,
prob(A) = prob(B) = i, i, function whose signal probability is to be computed.
and prob(C) = $.
Static probabilities can be computed from specified transition probabilities. f = zl A p s l V zl A p s l A ps2.
408 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION(VLSI) SYSTEMS, VOL. 3, NO. 3, SEPTEMBER 1995

Assume that the probability of i l being a 1 is 0.5, and state state machine controllers, datapaths2as well as pipelines. First,
probabilities are prob(00) = $, prob(0l) = prob(l0) = i, the power dissipation of the circuit was calculated using the
and prob(l1) = 2.
(The first bit corresponds to p s l and the exact state probabilities as described in Section 111-C. Next,
second to ps2.) The probability of the first cube is given the exact state probabilities, the line probabilities were
determined as described in the previous paragraph. Using
prob(i1 A p s i ) = p r o b ( i l ) x [prob(lO) f p r o b ( l l ) ] the topology of Fig. 3 and the computed present state line
probabilities for the P S lines, approximate power dissipations
=0.5 x (2 + 2) were calculated for each circuit. The average err03 in the
-1
- 4' power dissipation measures obtained using the line probabil-
ity approximation over all the circuits was only 2.8%. The
Similarly the probability of the second cube is: maximum error for any one example was 7.3%. Assuming
uniform line probabilities of 0.5 as in [4] results in significant
errors of over 40% for some examples.
The above experiment leads us to conclude that if accurate
line probabilities can be determined then using line probabil-
ities rather than state probabilities is a viable altemative. We
only have to determine N numbers for a N flip-flop machine,
Finally we have: one for each present state line, rather than 2 N numbers, one
for each possible state.

A. Computing Present State Line Probabilities

Note that (5) requires explicit enumeration of the states and In our approximation framework we directly determine
is very costly. In [14], a method which employs a partially line probabilities without recourse to State Transition Graph
implicit enumeration of states using OBDDs is described. extraction. The approximationframework is based on solving a
The estimation method still has average-case exponential nonlinear system of equations to compute the state line proba-
complexity-the probability of each state (respectively, groups bilities. This system of equations is given by the combinational
of states) is computed, and the number of states (respectively, logic implementing the next state function of the sequential
such groups) can be exponential in the number of flip-flops circuit.
in the circuit. However, for the circuits that this method Consider the set of functions below corresponding to the
is applicable to, the estimates provided by the method can next state lines.
serve as a basis for comparison among different approximation
schemes.

Iv. BASISOF APPROXIMATION

STRATEGIES
nSN = f N ( i l , i 2 , " . , i M , psi, ps21'", P S N )
Consider a machine with two flip-flops whose states are
We can write:
00, 01, 10, and 11 have state probabilities prob(00) =
i, i,
prob(0l) = prob(l0) = and prob(l1) = We can a. prob(ns1) =prob[f1(i1, 2 2 , . . . , iM, PSl, PS2r"., P N ) ]
calculate the present state line probabilities as shown below, prob(ns2) = p r o b [ f 2 ( i l , i 2 , . . . , i M , psi, pSZr"', PSN)]
where p s l and ps2 are the first and second present state lines. ...
prob(nsN) = p r o b [ f N ( i l , i 2 , ' " j iM, pslr p s 2 1 " . , P S N ) ]
prob(ps1 = 0) =prob(00) +prob(Ol)
-L+L-L where prob(ns;) corresponds to the probability that nsi is a 1,
- 6 3 - 2
andprob[f;(il, 2 2 , ' " , i ~p s i, , pS2, ..., p s N ) ] corresponds
prob(ps1 = 1) =prob(lO) f p r o b ( l 1 ) to the probability that f ; ( i l , i 2 , . . . , Z M , p s l , p s 2 , . . . , p s ~ )
-L+1-1 is a 1, which is of course dependent on the prob(psj) and the
- 4 4 - 2
prob(ps2 = 0) =prob(00) prob(l0) + prob( i k ) .
--l+l-L We are interested in the steady state probabilities of the
- 6 4 - 1 2 present and next state lines implying that:
prob(ps2 = 1) =prob(Ol) + p r o b ( l l )
- L + 1 - L prob(ps;) = prob(nsi) = p ; 15 i 5 N.
- 3 4 - 1 2 .
A similar relationship was used in the Chapman-Kolmogorov
Note that because psl and psp are correlated, prob(ps1 = (cf. Section 111).
0) x prob(ps2 = 0) = &
is not equal to prob(00) = 6. We were restricted to 8-bit datapaths since the state probability computa-
We carried out the following experiment on 52 sequential tion requires explicitly enumerating the states of the machine.
circuit benchmark examples for which the exact state proba- 3This error is caused by ignoring the correlation between the present state
bilities could be calculated. These benchmarks included finite lines.
TSUI er al.: POWER ESTIMATION METHODS FOR SEQUENTIAL LOGIC CIRCUITS 409

The set of equations given the values of prob(ik) becomes: 11

I

(a)
(li*dprowiLilyf-)

where the gi's are nonlinear functions of the p i ' s . We will

denote the above equations as Y(P)= 0 or as P = G ( P ) .
In general the Boolean function f; can be written as a list
10- ...... IPS"'

k = a userdelined limil
k
NSk-'
d

of minterms over the i k and psj and the corresponding gi

(b)
function can be easily derived. For example, given
Fig. 4. k-unrolling of the next state logic.

and prob(i1) = 0.5, we have k-unrolled nclwork ougutc

I:..........................
., ............ I I
c

We can solve the equation set Y( P ) = 0 or find a fixed point ................................... I

Use signal probabilities
of P = G ( P )to obtain the present state line probabilities. We calculatedby (a)
signal probabilityfeedback
describe the use of the Picard-Peano method to obtain a fixed
point of P = G ( P ) , and the use of the Newton-Raphson
method to solve Y ( P ) = 0 in Section VII. The uniqueness I
or the existence of the solution is not guaranteed for an
arbitrary system of nonlinear equations. However, since in our
application we have a correspondence between the nonlinear
system of equations and the State Transition Graph of the
sequential circuit, there will exist at least one solution to the
nonlinear system. Further, convergence is guaranteed under
mild assumptions for our application.
t
-
...............................................

/
k-unrolled network %
symbolic
simulption
EqU&lU Transition
probabilities

(b)
Fig. 5. Calculation of signal and transition probabilities by network un-
B. Inaccuracy in Formulation rolling.

The above formulation does not capture the correlation be-

tween the state line probabilities. Let us consider the example The above example is small (4 states) and contrived, and
State Transition Graph of Fig. 2. The equations for the next significanterrors may be obtained for such examples. The state
state logic are: line probabilities obtained using the approximation method of
this section are on average close to the exact line probabilities,
and they typically result in switching activity estimates that
are close to the exact method for most real-life examples (cf.
Section VIII). Nevertheless, it is worthwhile to explore ways
to increasing the accuracy. We describe two such mechanisms
Assuming the probability of input i being a 1 is 0.5 we obtain in Section V and Section VI.
the nonlinear equations (after simplification):
v. USING k UNROLLED NETWORKS
IMPROVING ACCURACY
n1 = 0.5 -0 . 5 -
~ 0~ . 5 ~ ~
n~ = P I + 0.5(1 - p1) (1 - p z ) . A. State Line Probability Computation
In the formulation of Section IV, the nonlinear equations
Setting nl = pl and nz = p2 and solving the above equations correspond to a single stage of next state logic. Consider
gives us pl = 0.191 and pz = 0.424. However, if we obtain the unrolled network of Fig. 4(a). The next state logic has
the exact line probabilities using the exact state probabilities been unrolled IC times. As illustrated in Fig. 4(b), we can
as shown in the first paragraph of Section IV, we find that construct a set of nonlinear equations corresponding to this
these approximate line probabilities are in error. Ic-unrolled network, which will partially take into account the
410 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 3 , NO. 3, SEPTEMBER 1995

101 >
IO, m Next State
c Logic
ps2 m ..........
..1

psn NSII
-.... J
A

Fig. 6 . An m-Expanded network with m = 2.

correlation between the state lines, when computing the state method models the correlation between m-tuples of present
line probabilities. state lines. The method is pictorially illustrated in Fig. 6 for
The exact present state line probabilities can be obtained m = 2.
by unrolling the next state logic 0;) times (Fig. 4(a)). This is The number of equations in the case of m = 2 is 3N/2.
however impractical. We thus approximate the signal proba- We have:
bilities by unrolling the next state logic k times where k is a
l ln]s i A nsi+l = fi A
n ~ i , i + ~ [= fi+l
user defined parameter.
The equations corresponding to k = 2 will be: nsi, i+l[l~]= nsi A 7~si+l=fi A
-
fi+l
ns;,;+l[Ol] =-A nsi+1 = fi A fi+l.
ns: =f&, . ' . , ih,p s i , . . . , p s h )
= fl(ii,. ..,
.I,...,
= f 1b1
iz,
iz, . . , nsO,)
fl(Z:,-, iL,Ps:,-.,psg),
We have to solve for prob(nsi, i+l[ll]), prob(nsi,i+l[lO]),
and prob(nsi,i+l [Ol]) [rather than prob(nsi) and prob(ns;+l)
as in the case of m = 1). We use:
. . . , fj&, . . . , ZL, ps:, . . . , psO,)]
... prob(psi A PSi+l) =prob(nsi,i+1[111)
ns:, = f&, . . . , ih, f l ( i 7 , . . . , iL, ps:, . . . , p s g ) , Prob(psi A =prob(nsi,i+1[101)
. . . , fj&, . . . , ZL, ps:, . . . , p s k ) ] . proqpsi A PSi+l) =prob(nsz, i+l[Oll)
The number of equations is the same. The number of primary in the evaluation of the prob(fi)'s.
input variables has increased, but the probabilities for these The signal probability evaluation methods of Section VII-C
variables are known. can be easily augmented to use the above probabilities. In the
Fig. 5(a) shows the method used to calculate signal proba- case of the OBDD-based method placing each psi and psi+l
bility of the intemal nodes of the FSM using the k-unrolled pair adjacent in the chosen ordering allows signal probability
network with signal probability feedback. computation by a linear-time traversal.
The number of equations for m = 3 is 7 N / 3 .When m = N ,
B. Switching Activity Computation the number of equations will become 2 N and the method will
degenerate to the Chapman-Kolmogorov method.
The topology of Fig. 3 was proposed as a means of taking
into account the correlation between the applied input vector The choice of the m-tuples of present and next state lines
pair when computing the transition probabilities. This method is made by grouping next state lines that have the maximal
takes one cycle of correlation into account. amount of shared logic into each m-tuple. Note that the
accuracy of line probability estimation will depend on the
It is possible to take multiple cycles of correlation into
account by prepending the symbolic simulation equations with choice of the m-tuples.
the k-unrolled network. This is illustrated in Fig. 5(b). Instead
of connecting the next state logic network to the symbolic B. Switching Activity Computation
simulation equations, we unroll the next state logic network k To estimate switching activity given m-tuple present state
times and connect the next state lines of the kth stage of the line probabilities, the topology of Fig. 3 is used as before. The
unrolled network, the next state lines of the (IC - 1)th stage, difference is that for m = 2 the prob(psi A psi+l), prob(psi A
and the primary input of the ( k - 1)th stage to the symbolic psi+l) and prob(ps;A psi+l) values are used to calculate the
simulation equations. switching activities.

VI. IMPROVING ACCURACY USING m-EXPANDED NETWORKS VII. SOLVING THE SYSTEM OF EQUATIONS
NONLINEAR
We describe two methods to solve the nonlinear system of
A. State Line Probability Computation
equations obtained using k-unrolled or m-expanded networks.
We describe a different method to improve the accuracy of We will assume that the nonlinear system can be represented
the basic approximation strategy outlined in Section IV.This as P = G(P ) or as Y ( P ) = 0 as described in Section IV.
TSUI et al.: POWER ESTIMATION METHODS FOR SEQUENTIAL LOGIC CIRCUITS 41 1

A. Picard-Peano Method Given Y ( P )= 0 and a column matrix corresponding to an

The Picard-Peano method is used to find a fixed point of initial guess P o , we can write the kth Newton iteration as the
the P = G ( P ) system. This system is reproduced below. linear system solve shown below.

Pl =91(p1, PZ,"', P N ) J ( P k )x P"' = J ( P k )x P k - Y ( P k ) (8)

P z =92(Pl, P Z , " ' , PN)
... where J is the N x N Jacobian matrix of the system of
equations. Each entry in J corresponds to a a y i l a p j evaluated
PN =gN(Pl, PZ,"', P N ) . at P k . The Pk+l correspond to the variables in the linearized
system and after solving the system Pk+' is used as the next
We can start with an initial guess P o , and iteratively
compute P k S 1= G ( P k )until convergence is reached. Con- guess. Convergence is deemed to be achieved if each entry in
vergence is deemed to be achieved if Pk+' - P k is sufficiently
Y ( P is) sufficiently small.
small. The above iteration is known as the Picard-Peano We use the methods of Section VII-C to evaluate:
iteration for finding a fixed-point of a system of nonlinear
equations.
We are only given the Boolean functions
fi(i1, iz,..., i ~ , p s 1p ,a , . . . , psN). There exist
several methods to compute g i ( p 1 , p z , . . . , p ~ ) = for given p j = prob(psj)'s and prob(ik)'s.The Y ( P k )of (8)
prob[fi(il,iz,..., i ~ , p s l , p s z , . . . , p s N ) ] for given can easily be evaluated using the pk values and using (6).
p j = prob(psj)'s and prob(ik)'s. We describe these methods We need to also evaluate J ( P2 ). As mentioned earlier,
in Section VII-C. each entry of J corresponds to ayi/apj evaluated at P k . If
Theorem 7.1: [61 If G is contractive, i.e., lag;/apjl < 1, i # j , then dy;/apj equals - a g i / a p j , and a y ; / a p ; equals
for all i, j , then the Picard-Peano iteration method converges 1 - agi/ap;.
at least linearly to a unique solution P*. In order to perform the evaluation of a g ; / a p j we use the
Theorem 7.2: If each next state line is a nontrivial logic method in the proof of Theorem 7.2.
function of at least two present state lines, then g; is contractive
on the domain (0, 1). agz
- = p r o b ( f z p s , )- prob(f2x).
Proof: Choose any p j . In order to perform the evaluation 8Pj
of a g i / a p j we cofactor f ; with respect to p s j .
We can evaluate prob(fi,,,) and prob(f;=) for a given P k
fi Psj A fipsj V psj A fiE using the methods of Section VII-C.
As an example consider:
f i p s j and f i - are the cofactors of f with respect to p s j , and
are Boolean functions independent of p s j . We can write:

si = P j . PrOb(fipsj) + (1 - P j ) . prob(f;=).
Differentiating with respect to pj gives:

which is exactly what we would have obtained had we

Since we are considering the domain (0, l), which is not differentiated (7) with respect to p l .
inclusive of 0 and 1, and the m i ' s are nontrivial Boolean Theorem 7.3: [ l 11 The Newton iterates:
functions of at least two present state lines for every i, this
partial differential is strictly less than one, because we are
guaranteed that prob( f i p s , ) > 0 and prob( fiK)> 0.
From Theorems 7.1 and 7.2, we can see that the iterated are well-defined and converge to a solution P* of Y ( P ) = 0
signal probability calculation is guaranteed to converge to if the following conditions are satisfied:
a solution, provided some mild assumptions are made with 1) Y is F-differentiable.
respect to the functionality of the next state logic. 2) IIJ(A) - J(B)(I 5 y l ( A - B I), V A , B E D O where
DO is the domain 0 5 p ; 5 1 , V i .
B. Newton-Raphson Method 3 ) There exists P o E DO such that IIJ(Po)-'ll 5 ,f?,7) 2
The Newton-Raphson method can be used to solve a IIJ(Po)-'Y(Po)II and Q = ,Byq5 $.
nonlinear system of equations given an initial guess at the Condition 1 of the theorem is satisfied in our application
solution. The advantage of the Newton-Raphson method is the because the y; functions are continuous and differentiable.
quadratic rate of convergence. However, each iteration is more We need to prove that the parameter y is finite to show that
computationally expensive than the Picard-Peano method. Condition 2 is satisfied.
412 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 3, NO. 3, SEPTEMBER 1995

Theorem 7.4: If Y is given by (6), then y 5 2. TABLE I

COMPAR~SON POWER
OF SEQUENTIAL ESTIMATION
METHODS
Proof: In order to show that:

IIJ(A) - J(B)II I - BIJ,VA, B E Do

is satisfied for y = 2, we will show that the derivative of each

entry of J is less than or equal to 2.
Recall that J is a matrix with each entry corresponding
to ay;/apj. Using the equations provided in the proof of
Theorem 7.2 we can write:

a fj.

Differentiating with respect to pk we have:

Given that the probabilities are between 0 and I, we have:

Condition 3 in Theorem 7.3 is a constraint on the initial

guess for the Newton iteration, and this initial guess can be
picked appropriately, provided y is finite. Essentially, we have
to choose Po such that IIY(Po)II is small.

B. Signal Probability Evaluation Assuming uniform probabilities for the present state line
In the nonlinear equation solver, regardless of whether we probabilities and state probabilities as in [4] can result in
are using the Picard-Peano method or the Newton-Raphson significant inaccuracies in power estimates.
method, we have to repeatedly evaluate the signal probability Computing the present state line probabilities using the
of a Boolean function given input probabilities, i.e., com- technique presented in the previous sections results in 1)
pute prob[fi(il,i 2 , . . . ,i ~ psl,
, p s z , " . , p s ~ ) given
] the accurate switching activity estimates for all intemal nodes
prob(ik)'s and the prob(psj)'s. in the network implementing the sequential machine;
There exist several methods to evaluate signal probability. 2) accurate, robust and computationally efficient power
An exact method corresponds to using Ordered Binary Deci- estimate for the sequential machine.
sion Diagrams (OBDD's) [I]. If an OBDD can be created for In Table I, results are presented for several circuits. In the
fi, then prob(fi) can be evaluated in linear time in the size of
table, combinational corresponds to the purely combinational
the OBDD for fi. OBDD's can be cofactored in linear time, estimation method of [4] and uniform-prob corresponds to
allowing for the efficient evaluation of the Jacobian entries. the sequential estimation method of [4] that assumes uniform
An alternative is to use Monte Carlo simulation. Approxi- state probabilities. The column line-prob corresponds to the
mate signal probabilities can be computed using random logic technique of Section IV and using the Newton-Raphson
simulation on the multilevel network corresponding to f i .
method with a convergence criterion of 0.0001% to solve the
Our experience has been that the signal probabilities quickly
equations. These equations correspond to IC = 0 or m = 1.
converge to the exact results obtained using OBDD's. In order
Finally, state-prob corresponds to the exact state probability
to evaluate a particular Jacobian entry, the appropriate input to
calculation method of Section 111. The zero delay model was
fi has to be set to 0 (I) and random simulation is performed
assumed, however, any other delay model could have been
on the remaining inputs.
used instead.
The first set of circuits corresponds to finite state machine
RESULTS
VIII. EXPERIMENTAL controllers. These circuits typically have the characteristic
In this section we present experimental results that illustrate that the state probabilities are highly nonuniform. Restricting
the following points: oneself to combinational power dissipation (combinational)
Exact and explicit computation of state probabilities is or assuming uniform state probabilities (unifomz-prob) results
possible for controller type circuits. However, it is not in significant errors. However, the line probability method of
viable for data path circuits. Purely combinational logic Section IV produces highly accurate estimates when compared
estimates result in significant inaccuracies. to exact state probability calculation.
TSUI et al.: POWER ESTIMATION METHODS FOR SEQUENTIAL LOGIC CIRCUITS 413

The second set of circuits corresponds to datapath circuits, TABLE II

such as counters and accumulators. The exact state probability ABSOLUTE
ERRORSIN PRESENT STATELINEF’ROBABILITIE~
AVERAGED
OVER A L L PRESENT STATE LINES
evaluation method requires huge amounts of CPU time for
even the medium-sized circuits, and cannot be applied to the Circuit Combinational Uniform Prob. Line Prob.
large circuits. For all the circuits that the exact method is viable Name err err err
for, our line-prob method produces identical estimates. The
uniform-prob method does better for the datapath circuits-in cse 0.427 0.427 0.00788
the case of counters for instance, it can be shown that the dk16 0.0782 0.0782 0.0125
state probabilities are all uniform, and therefore the uniform-
df ile 0.075 0.075 0.047
prob method will produce the right estimates. Of course, this
assumption is not always valid. keyb 0.414 0.414 0.0133
The third set of circuits corresponds to pipelined adders mod12 0 0 0.03
and a pipelined multiplier. For pipelined circuits, exact power
estimation is possible without resort to Chapman-Kolmogorov planet
equation solving . The fourth set corresponds to mixed data-
pathkontrol circuits from the ISCAS-89 benchmark set. Exact
sreg
state probability evaluation is not possible for these circuits.
The CPU times in the table corresponds to seconds (s) or styr 0.3138 0.3138 0.0357
(m) on a SUN SPARC-2. The CPU times correspond to times tbk 0.2614 0.2614 0.026
required for symbolic simulation to estimate combinational
activity plus the time required for the calculation of statenine accum4 0 0 0
probabilities. For all the circuits BDD’s were used to obtain the accum8 0 0 0
line probabilities. However, Monte-Carlo simulation was used
accuml6 0 0 0
for combinatorial activity estimation for the large ISCAS-89
circuits. COUnt4 0 0 0
In Table 11, present state line probability estimates for the count7 1 0 II 0 II 01
benchmark circuits are presented. The error value provided
in each column shows the absolute error (i.e., absolute value count8 0 0 0
of the difference between exact and approximate values) cbp32.4
of the signal probabilities averaged over all present state
lines in the circuit. The exact values were calculated by
the method described in Section 111. (We could not generate
the exact values for circuits in Groups 3 and 4, as the
size of Chapman-Kolmogorov system of equations becomes
too large.) It is evident from these results that the error
averaged over all benchmark circuits is well below 0.05 s1238
(see the line-prob column entries which correspond to the
method described in Section IV). Note that this error is due to
ignoring correlation as exemplified in Section IV-B, and not
due to convergence error of the Newton-Raphson method. The Jacobian and is more expensive than the Picard iteration. The
convergence criterion for line probabilities was set to 0.0001% results obtained by the two methods are identical, since the
to generate these results. convergence criterion used was the same.
We present the switching activity errors for the benchmark To generate the results in Table IV, the convergence cri-
circuits in Table 111. Again, the error value provided in each terion allowed a maximum error of 1% in the line proba-
column represents the absolute error averaged over all internal bilities. In this case, the Picard-Peano method out performs
nodes in the circuit. It can be seen that this error is quite small. the Newton-Raphson method for virtually all the examples.
These two tables demonstrate that the approximate procedure If the convergence criterion is tightened, e.g., to allow for a
provided in Section IV leads to very accurate estimates for maximum error of .01%, the Picard-Peano method requires
both the present state line probabilities and for the switching substantially more iterations than the Newton-Raphson and in
activity values for all circuit lines. several examples, the Newton-Raphson method outperforms
Next, we present results comparing the Picard-Peano and the Picard-Peano method. However, since the error due to
Newton-Raphson methods to solve the nonlinear equations ignoring correlation (cf. Section IV-B) can be more than 1%,
of Section IV. These results are summarized in Table IV. in practice it does not make sense to tighten the convergence
The number of iterations required for the Picard-Peano and criterion beyond a 1% allowed error.
Newton-Raphson methods are given in Table IV under the In some pathological examples, where the conditions of
appropriate columns, as are the CPU times per iteration and Theorem 7.1 are not satisfied, the Picard-Peano method may
the total CPU time. Newton-Raphson typically takes fewer exhibit oscillatory behavior, and will not converge. In these
iterations, but each iteration requires the evaluation of the cases, the strategy we adopt is to use Picard-Peano for several
414 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 3, NO. 3, SEPTEMBER 1995

TABLE III TABLE IV

IN SWITCHING A C T ”
ABSOLUTE ERRORS OF PICARD-F%ANO
COMPARISON AND NEWTON-RAPHSON
AVERAGED OVER ALL CIRCUITLINES
Circuit Picard-Peano Newton-Fbphson
Circuit Combinational Uniform Prob. Line Prob. Name #iter cpu/iter total CPU #iter cpu/iter total CPU

err err err

0.354 0.020 0.010

~~ ~

keyb 0.363 0.067 0.009

mod12 0.387 0.149 0.156
planetll 0.375 1 0.034 1 0.034 I

accum4 0.084 0 0
accum8 0.086 0 0
count7 1 0.2 0.2 1 1 1
accuml6 0.096 0 0 count8 1 0.2 0.2 1 1 1
I1 I I 11 I I I
COUt4 0.169 0 0 cbp32.4 3 0.8 2.4 4 18.5 74
addl6 3 0.3 0.9 3 3 9
count8 0.192 0 0 mult8 2 3.25 6.5 4 9.25 37
I I s953 30 0.04 1.1 4 0.5 2
cbp32.4 I -I
- II - II
I1
-I s 1196 2 1.1 2.2 2 2 4
si23a 2 1.15 2.3 2 2.5 5
mult8

s 1196 they are added together, the overall error may become small
due to error cancelation. Increasing k improves the accuracy of
power estimates for individual nodes (see Table VI), but does
not necessarily improve the accuracy of power estimate for
the circuit due to the unpredictability of the error cancelation
iterations, and if oscillation is detected, the Newton-Raphson during the summing step. The m-expansion-based method
method is applied. The Newton-Raphson method does not behaves more predictably for this set of examples, however,
require the domain to be contractive, however, the initial guess again no guarantees can be made regarding the improvement
has to be “close” to the solution P* in a manner quantified in accuracy (of total power estimates) on increasing m, except
by Theorem 7.3. that when m is set to the number of flip-flops in the machine,
In Table V, we present results that indicate the improvement the method produces the Chapman-Kolmogorov equations,
in accuracy in power estimation when k-unrolled or m- and therefore the exact state probabilities are obtained. The
expanded networks are used. Results are presented for the Newton-Raphson method with a convergence criterion of
finite state machine circuits of Table I for 0 5 IC 5 2 and 0.0001% was used to obtain the line probabilities in Tables
1 5 m _< 4.4 The percentage differences in power from the V and VI.
exact power estimate are given. In general, if k 4 00, the error The CPU times for power estimation are in seconds on
will reduce to 0%, however, increasing k when IC is small is a SUN SPARC-2. These times can be compared with those
not guaranteed to reduce the error in total power estimates listed in Table I under the “Line Prob.” column as those times
(e.g., consider styr). This phenomenon can be explained as correspond to k = 0 and m = 1. Based on these results, we
follows. The total power estimate is obtained by summing conclude that k = 1 and m = 2 provide a good compromise
power consumptions of all nodes in the circuit. The individual between accuracy and run-time.
power estimates may be under- or over-estimated, yet when During the synthesis process, we often want to know the
4The initial error for dk16 and s r e g benchmarks is 0, thus, there is no switching activity of individual nodes instead of a single power
need to improve the accuracy by using larger values of k and m. consumption figure. Table VI presents the percentage error in
TSUI er al.: POWER ESTIMATION METHODS FOR SEQUENTIAL LOGIC CIRCUITS 415

TABLE V can accurately model the correlation between the applied input
OF POWER ESTIMATION
RESULTS BASEDON vector pairs can be used.
IC-UNROLLED
AND 1~-EXPANDEDNETWORKS

Circuit Initial k-Unrolled Error m-Expanded Error REFERENCES

Name Error k=l k=2 m=2 m=4
R. Bryant, “Graph-based algorithms for Boolean function manipulation,”
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R. Burch, F. Najm, P. Yang, and T. Trick.“ McPOWER: A Monte
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A. Chandrakasan, T. Sheng, and R. W. Brodersen, “Low power CMOS
digital design,” in J. Solid State Circuits, pp. 473484, Apr. 1992.
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switching activity in combinational and sequential circuits,” in Proc.
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H. M. Lieberstein, A Course in Numerical Analysis. New York: Harper
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ERRORIN SWITCHING
PERCENTAGE ACTIVITYESTIMATES F. Najm, “Transition density, A stochastic measure of activity in digital
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Equations in Several Variables. Boston, MA: Academic, 1970.
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Tech. Rep. CNEG 93-42, Oct. 1993.

Chi-Ying Tsui received the B.S. degree in electrical

individual node’s switching activity from the exact values as a engineering from the University of Hong Kong, and
the M.S. and Ph.D. degrees in computer engineering
function of k and m, averaged over all the nodes in the circuit. from the University of Southern California in 1989
It is seen that the accuracy of switching activity estimates and 1994, respectively.
consistently increases with the value of k and m. For example, He is an Assistant Professor of Electrical and
Electronic Engineering at the Hong Kong University
the error in switching activity estimates for styr decreases of Science and Technology. He is working on VLSI
from 13% to 6.3% when k increases from 1 to 2 and from 6.6% design and CAD algorithms for high performance
to 6.0% when m increases from 2-4. A similar trend exists low-power microprocessor design. His research in-
terests include power analysis and optimization for
with respect to the maximum error and the root-mean-squared CMOS circuits, and hardwarekoftware codesign for high-performance low-
error criteria. power processors.

Ix. CONCLUSIONS AND ONGOING W O R K

We presented a framework for sequential power estimation
in this paper. In this framework, state probabilities can be Josi Monteiro received the Engineer’s and Mas-
computed using the Chapman-Kolmogorov equations, and ter’s degrees in electrical and computer engineering
present state line probabilities are computed by solving a in 1989 and 1994, respectively, from Instituto Supe-
rior Tkcnico at the Technical Univeristy of Lisbon.
system of nonlinear equations. We have shown that the latter is He is currently working towards the Ph.D. degree
significantly more efficient for medium to large circuits, and at the Massachusetts Institute of Technology in the
does not sacrifice accuracy. area of power estimation and synthesis for low
power of VLSI circuits.
Given the present state line probabilities, the switching
activity and power dissipation of the circuit can be accurately
computed. Any combinational logic estimation method that
416 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 3, NO. 3, SEPTEMBER 1995

Massoud Pedram (M’90-S’9&M’91) received the Alvin M. Despain (S’58-M’65) received the B.S.,
B.S. degree in electrical engineering from the Cal- M.S., and Ph.D. degrees in electrical engineering
ifornia Institute of Technology in 1986, and the from the University of Utah in 1960, 1962, and
M.S. and Ph.D. degrees in electrical engineering and 1966, respectively.
computer sciences from the University of California, He is the Powell Professor of Computer Engi-
Berkeley in 1989 and 1991, respectively. neering at the Univeristy of Southern California
He is an Assistant Professor of Electrical En- (USC), and a Professor in the Computer Science
gineering-Systems at the University of Southern and Electrical Engineering Systems Departments.
California. His research interests span many aspects He has been an Assistant Research Professor at the
of design and synthesis of VLSI circuits, with University of Utah, an Associate Professor at Utah
particular emphasis on layout optimization, logic State University, a Visiting Associate Professor at
synthesis and behavioral optimization, layout-driven synthesis, and design for Stanford University, a Professor at the University of California at Berkeley,
low power. and has been at USC since 1989. He is a pioneer in the study of high-
Dr. Pedram is a recipient of the National Science Foundation’s Research performance computer systems for symbolic calculations. His research group
Initiation Award in 1992 and the Young Investigator Award in 1994. His builds experimental software and hardware systems including compilers,
research has received a number of awards including one ICCD Best Paper custom VLSI processors, and multiprocessor systems. Their goal is to de-
Award and a Distinguished Paper Citation from ICCAD. He has served on termine principles for the design of high-performance computer systems.
the technical program committee of a number of conferences and workshops, Despain’s research interests include computer architecture, multiprocessor and
including the Design Automation Conference. He was the co-founder and multicomputer systems, logic programming, and design automation.
General Chair of the 1994 International Workshop on Low Power Design,
and the General Chair of the 1995 International Symposium on Low Power
Design. He has given several tutorials on low power design at major CAD
conferences and forums including, ICCAD and DAC. He is a member of the
ACM.
Bill Lin received the B.Sc., M.S., and Ph.D. degrees
in electrical engineering and computer sciences
from the University of California, Berkeley, in
1985, 1988, and 1991, respectively.
Since graduating from Berkeley, he has been
working in the VLSI Systems Design Method-
Srinivas Devadas (S’87-M’88) received the B. ologies division of the Inter-University Micro-
Tech degree in electrical engineering from the In- Electronics Center (IMEC) in Leuven, Belgium.
dian Institute of Technology, Madras in 1985, and At IMEC, he is currently heading the System
the M.S. and Ph.D. degrees in electrical engineenng Control and Communications group, which is
from the University of California, Berkeley, in 1986 mainly focusing on system design technology for
and 1988, respectively. embedded hardware-software systems. This group also has a major effort in
Since August 1988, he has been at the Massa- asynchronous design methods and high-speed telecom Am-based network
chusetts Institute of Technology, Cambridge, and is applications. He has been work-package leader in several E.C. sponsored
currently an Associate Professor of Electrical Engi- Esprit projects an Belgian Flemish government sponsored IWT projects.
neenng and Computer Science. He held the Analog Previously, he has worked at the Hewlett Packard Corporation, the Hughes
Devices Career Development Chair of Electncal Aircraft Company, and the Western Digital Corporation. He has authored or
Engineering from 1989 to 1991. His research interests span all aspects of co-authored more than 70 scientific publications in the area of CAD methods
synthesis of VLSI systems. for VLSI design.
Dr. Devadas has received five Best Paper Awards at CAD conferences and Dr. Lin has served on the program committee of several international
journals, including the 1990 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN conferences. In 1987, he received a Best Paper Award at the 24th Design
Best Paper Award. In 1992, he received the NSF Young Investigator Award. Automation Conference, Miami, FL. In 1989 and 1990, respectively, he
He has served on the technical program commttees of several conferences and received a Distinguished Paper Citation at the IFIF’ VLSI conference in
workshops including the International Conference on Computer Design, and Munich, Germany, and at the ICCAD conference in Santa Clara, CA. In
the International Conference on Computer-Aided Design He is a member of 1994, he received a best paper nomination at the ACM Design Automation
the ACM. Conference, San Diego, CA.