PROJECT REPORT (KEC-753)

On

DESIGN AND DEVELOPMENT OF STRONG ARM LATCH

Submitted for partial fulfillment of award of the degree of

Bachelor of Technology

In

Electronics and Communication Engineering

Submitted By

Shivani Chauhan - 1819231100

Sudesh Dubey - 1819231107
Saurav - 1819231098

Under the Guidance of

Mr. Puneet kumar Mishra

Assistant Professor

Deptt. of Electronics and Communication Engineering

G. L. BAJAJ INSTITUTE OF TECHNOLOGY AND MANAGEMENT
Plot no. 2, Knowledge Park III, Gr. Noida
Session: 2021-22 (ODD SEM)

i
 Deptt. of Electronics and Communication Engineering
G. L. BAJAJ INSTITUTE OF TECHNOLOGY AND MANAGEMENT
[Approved by AICTE, Govt. of India & Affiliated to A.K.T.U (Formerly U.P.T.U), Lucknow]

CERTIFICATE

Certified that Shivani Chauhan, Sudesh Dubey and Saurav have carried out
the project work presented in this report entitled DESIGN AND
DEVELOPMENT OF STRONG ARM LATCH for the Subject Project -
I (KEC-753) during the Academic session 2021-22 (ODD SEM). The project
embodies result of the work and studies carried out by Students and the contents
of the report do not form the basis for the award of any other degree to the
candidate or to anybody else.

Mr. Puneet Kumar Mishra (Dr. Piyush Yadav)

(Project Guide) (Project Coordinator)
(Assistant Professor) (Associate Professor)
Deptt.of ECE Deptt.of ECE

(Dr. Satyendra Sharma)

H. O. D., Deptt. of ECE

ii
 INDEX

CHAPTER NO. TITLE PAGE NO.

LIST OF TABLES V

LIST OF FIGURES Vi

ABSTRACT Vi
i

1
1. INTRODUCTION
1.1 Introduction 1

1.2 Types 1

1.2.1 Chain Link Gates 1

1.2.2 Ornamental Gates 4
1.2.3 Accessories 6
1.3 Objective 7
1.4 Advantages of Strong-Arm Latch Comparator 8

2. LITERATURE REVIEW
2.1 History 9
2.1.1 SA-110 9
2.1.2 SA-1100 9
2.1.3 SA-1110 10
2.1.4 SA-1500 11
2.2 Current Developments 11
2.3 Principle of Strong Arm latch Comparator 12
2.4 Benefits to society 12

3. DESIGN SPECIFICATIONS
3.1 List of components 14
3.1.1 NMOS 15
3.1.2 PMOS 17
3.1.3 Clock Pulse 18
3.1.4 Signal Source 20
3.1.5 Voltage Supply 22
3.1.6 Digital Oscilloscope 23
iii
4. OPERATION 26
4.1 Basic Operation 26
4.2 Operational Phases 27
4.2.1 Reset State 27
4.2.2 Sampling Phase 27
4.2.3 Propagation Phase 27
4.3 Working 28
4.4 Limitations 29
4.5 Results 29
4.6 Proposed Design Theory 29

5. Contributional Work Done 33

5.1 Conclusion 33
5.2 Inference 33

6. References 34

iv
 LIST OF TABLES

SNO. TITLE PAGE NO.

1. Types of Strong Arm Latch 1

2. Different Version of Strong Arm Latch 9
3. List of Components 14
4. Specifications of NMOS 16
5. Specifications of PMOS 18
6. Specifications of Clock Pulse 19
7. Specifications of Signals Generator 21
8. Specifications of Voltage Supply 23
9. Specifications of Digital Storage Oscilloscope 25
10. Performance Comparison at 32nm and 90nm technology 32

v
 LIST OF FIGURE

FIGURE NO. TITLE PAGE NO.

Fig 1.1 Strong Arm Latch vii

Fig 1.2 Strong Arm Latch viii

Fig 2.1 SA-110 9

Fig 2.2 SA-1100 10

Fig 2.3 SA-1110 10

Fig 2.4 SA-1500 11

Fig 3.1 NMOS Block Diagram 16

Fig 3.2 Structure of PMOS 28

Fig 3.3 Waveform of Clock Pulse 19

Fig 3.4 Signal Generators 21

Fig 3.5 Voltage Supply 23

Fig 3.6 Digital Storage Oscilloscope 25

Fig 4.1 Strong Arm-Latch Topologies 26

Fig 4.2 Operation Phases of Strong Arm Latch 28

Fig 4.3 Proposed Design of Strong Arm Latch 30

Fig 4.4 Operation of the proposed and conventional 31

latches
Fig 4.5 Energy and Delay Comparison 32

vi
 ABSTRACT

The aim of this thesis is to style and build a unique dynamic comparator that
outperforms the standard StrongARM latch in terms of noise and power efficiency. A
comparator plays a very important role in designing the required high-resolution, high-
speed and low- power analog-to-digital convertor. Among different architectures, CMOS
dynamic latched comparators find wide usage in Analog-to-Digital Converters
(ADCs) due to their high-speed, low power consumption and skill to provide rail-to-rail
outputs. The StrongARM latch is one among the foremost common dynamic
comparators utilized in ADC designs. during this thesis, three novel low-noise low-power
double-tail dynamic latched comparator topologies are proposed and compared to the
traditional StrongARM latch in terms of noise, power consumption and speed. Simulation
results show that the proposed architectures consume 65% to 75% less power than the
StrongARM latch for the identical input- referred noise voltage of 40μV. Additionally,
the speed of proposed floating comparator design is insensitive to input common-mode
variation and outperforms the quality Strong ARM latch for low V cm values. The
StrongARM latch and three proposed novel comparator architectures are fabricated on the
identical die using 180nm process node. The measurement results confirmed the
higher performance of the proposed designs by showing 3.5x less power consumption
than the StrongARM latch with similar input-referred noise voltage. The proposed
floating-capacitor topologies offer a low-power, wide common-mode input range solution
for high-precision comparator design.

vii
viii
 CHAPTER – 1
INTRODUCTION

1.1 Introduction
Strong Arm latches eliminate the necessity for a drop rod and are secure and simple to put
in. These latches are engineered to stay gates in-line with fences. they're especially good
to use once you have different sized gaps between gate panels. For extra security, Strong
Arm latches may be thru-bolted or welded to the gate frame.
a powerful ARM latch comparator (500) includes first and second p-type metal- oxide-
semiconductor, PMOS, cross-coupled transistors (T1, T2); third and fourth n- type metal-
oxide-semiconductor, NMOS, cross-coupled transistors (T3, T4), wherein the
primary PMOS cross-coupled transistor (T1) encompasses a gate electrically coupled to a
gate of the third NMOS cross-coupled transistor (T3) and also the second PMOS cross-
coupled transistor (T2) incorporates a gate electrically coupled to a gate of the fourth
NMOS cross-coupled transistor (T4); and fifth and sixth input transistors (T5, T6). The
fifth input transistor (T5) is electrically connected between the primary PMOS cross-
coupled transistor (T1) and therefore the third NMOS cross-coupled transistor (T3), and
therefore the sixth input transistor (T6) is electrically connected between the second
PMOS cross-coupled transistor (T2) and also the fourth NMOS cross-coupled transistor
(T4).

1.2 Types

Chain Link Gates

Commercial
1 5/8” or 2” Strong Arm Latch for Round Frame

• For Double Drive Gates

• Heavy Duty Steel Latch
• Galvanized or Black Powder Coat Finish
• Fits 1 5/8” or 2” Gate Frame
• Adjusts for 2 1/2” to 6” Gap

1
 Description Part No Weight

1 5/8″ or 2″ Round Frame – Galvanized 4000 9 lbs

1 5/8″ or 2″ Round Frame – Black 4000-B 9 lbs

Residential
1 3/8” Strong Arm Latch for Round Frame

• For Double Drive Gates

• Steel Latch
• Galvanized or Black Powder Coat Finish
• Adjusts for 2” to 4” Gap

Description Part No Weight

1 3/8″ Round Frame – Galvanized 4138 2.9 lbs

1 3/8″ or 2″ Round Frame – Black 4138-B 2.9 lbs

2
 Walk Gate Latch
1 5/8” or 2” Walk Gate Latch for Round Frame

• Heavy Duty Steel Latch

• Galvanized or Black Powder Coat Finish
• Adjusts for 2” to 5” Gap
• Available for 2 1/2”, 3”, 4” or 6 5/8” Round Post

2 1/2” Round Post – Sold individually or 12/box

Description Part No Weight

Galvanized 4250 4.5 lbs

Black 4250-B 4.5 lbs

3” Round Post – Sold individually or 12/box

Description Part No Weight

Galvanized 4300 4.5 lbs

Black 4300-B 4.5 lbs

4″ Round Post – Sold individually or 10/box

Description Part No Weight

Galvanized 4400 4.5 lbs

Black 4400-B 4.5 lbs

3
 6 5/8” Round Post – Sold individually

Description Part No Weight

Galvanized 4658 5 lbs

Black 4658-B 5 lbs

Ornamental Gates

Commercial
2” Strong Arm Latch for Square Frame

• For Double Drive Gates

• Heavy Duty Steel Latch
• Galvanized or Black Powder Coat Finish
• Adapter Available for use on 1 3/4” Square Frame
• Adjusts for 2 1/2” to 3 1/4” Gap

Description Part No Weight

2″ Square Frame – Galvanized 4090 7 lbs

2″ Square Frame – Black 4090-B 7 lbs

4
 Walk Gate Strong Arm Latch
2” Walk Gate Latch for Square Frame

• Heavy Duty Steel Latch

• Galvanized or Black Powder Coat Finish
• Adapter Available to be used on 1 3/4” Square Frame
• Adjusts for 3” to 5” Gap
• Available for 2 1/2”, 3”, 4”, or 6” Square Post

2 1/2” Square Post – Sold individually or 12/box

Description Part No Weight

Galvanized 4290 4 lbs

Black 4290-B 4 lbs

3” Square Post – Sold individually or 12/box

Description Part No Weight

Galvanized 4390 4 lbs

Black 4390-B 4 lbs

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 4″ Square Post – Sold individually or 10/box

Description Part No Weight

Galvanized 4490 4 lbs

Black 4490-B 4 lbs

6 5/8” Square Post – Sold individually

Description Part No Weight

Galvanized 4690 5 lbs

Black 4690-B 5 lbs

Accessories

Adapters
Adapters for 1 3/4” Square Frame (Double Drive Latches Require Two)

Description Part No Weight

Adapter for 1 3/4″ Square Frame 4999 1 lb

6
 Hardware Bags
Replacement Hardware for Strong Arm Latches

Description Part No Weight

Residential DD SA Bag Res DD 0.5 lb

Commercial DD Round SA Bag 0.5 lb

Commercial DD Square SA Bag SQ 0.5 lb

Walk Gate Round SA WG Bag 1 lb

Walk Gate Square SA WG Bag SQ 1 lb

1.3 Objective
The objective behind this project is to propose topology that will deliver superior
performance, improved speed and efficiency and take away the clock feedthrough problem
to the most extent compared to the standard solutions. These are the following objective :

• Designing and implementing Strong ARM Latch comparator.

• An improved Strong ARM latch comparator topology is produced which is fast and
power efficient.
• Executing StrongARM latch in analog-to-digital converters (ADCs) and Flip-
Flops circuits.
• Improvement of this topology by interfacing of sensor in IoT, wearable electronics
and low power applications.
• Algorithm designing for object and human detection from live streaming.
• Implementing latch to supply use in sense amplifier, comparator and in robust latch.
• The proposed design is capable to produce a rail-to-rail output in an exceedingly
shorter time (modified version).

7
 • The proposed cascade cross-coupled dynamic comparator improves the differential
gain of the pre-amplifier and reduces the common-mode voltage which leads to
faster regeneration at small input difference.

1.4 Advantages of Strong Arm Latch Comparator

• The key advantage of this design is reducing the entire internal capacitance within
the circuit without compromising this. this is often achieved by placing the input
transistors within the middle between the cross-coupled transistors. Since the input
transistors are always ON, the necessity for the CT3 and CT4 is eliminated and nodes B
and B` are recharged through the transistors T5 and T6. As a consequence, the speed and
efficiency of the latch are improved, while the realm and also the clock feedthrough
problem are reduced.
• The strong ARM comparator can profit of adiabatic principles by
i) being powered by a sine-wave, the power-clock, instead of the standard DC power
supply, VDD.
ii) using an adiabatic buffer because the output stage, instead of an SR latch.

CHAPTER – 2
LITERATURE REVIEW

8
2.1 History

SA-110
SA-110 was the first microprocessor in the StrongARM family. The first versions,
operating at 100, 160, and 200 MHz, were announced on February 5, 1996. At the
announcement, samples of these versions were made available, and volume production was
scheduled for mid-1996. The 166 and 233 MHz fast versions were announced on
September 12, 1996. [7] Samples of these versions were made at the time of the
announcement, and volume production was scheduled for December 1996. Throughout
1996, the SA-110 was the most widely used microprocessor in portable devices. [8] By the
end of 1996 it was the leading CPU Internet / intranet power and small client systems. [9]
The winner of the first SA-110 design was the Apple MessagePad 2000. [10] It has also
been used in a number of products including the Acorn Computers Risc PC and the Eidos
Optima video editing program. Leading SA-110 designers were Daniel W. Dobberpuhl,
Gregory W. Hoeppner, Liam Madden, and Richard T. Witek.

Fig. 2.1 1920 – SA-110

SA-1100
The SA-1100 came out on the SA-110 developed by the DEC. Announced in 1997, SA-
1100 was targeted at mobile systems such as PDAs and differed from SA-110 by providing
a number of desirable features in those applications. To accommodate these features, the
data repository was reduced to 8 KB.

Additional features include integrated memory, PCMCIA, and colored LCD controls
connected to the dying system bus, as well as five serial I / O channels connected to the
rotating bus connected to the system bus. Memory control supported FPM and EDO

9
DRAM, SRAM, flash, and ROM. PCMCIA control supports two spaces. Memory address
and data bus shared with PCMCIA interface. Glue logic is required. Serial I / O channels
use slave USB interface, SDLC, dual UART, IrDA interface connector, MCP, and synced
serial port.

Fig. 2.2 SA-1100

SA-1110

The he SA-1110 was from the SA-110 developed by Intel. Announced March 31, 1999, it
was introduced as an alternative to SA-1100. [14] In the announcement, samples were
scheduled for June 1999 and volume later that year. Intel stopped using SA-1110 in early
2003. [15] The SA-1110 was available in 133 or 206 MHz versions. It differs from SA-
1100 by incorporating 66 MHz support (133 MHz version only) or 103 MHz (206 MHz
version only) SDRAM.

10
 Fig. 2.3 SA-1110

SA-1500

Fig. 2.4 SA-1500

The SA-1500 was derived from the SA-110 developed by the DEC which was aimed at the
top boxes. [18] [19] It was designed and manufactured at low volumes by DEC but never
included in Intel production. The SA-1500 was available at 200 to 300 MHz. The SA-1500
is equipped with an upgraded SA-110 core, an on-chip coprocessor called Attached Media
Processor (AMP), and an on-chip SDRAM with I / O bus controller. The SDRAM controller
supports the 100 MHz SDRAM, and the I / O controller uses a 32-bit I / O bus that can travel
at high speeds as adiabatically up to 50 MHz to connect to peripherals and a chip. SA-1501
companion.

2.2 Current Developments

In the last few years, the analysis of various comparisons has been made as a powerful
ARM model (ADSA), which uses between 28% and 55% of the strength of traditional solid
ARM (SA), while producing similar features in terms. noise and offset input voltage.
Another comparison established in recent years is the Dynamic Bias Latch-type
Comparator on 65nm CMOS with a 0.4mV input sound of Harijot Singh Bindra, Student
Member, IEEE. This component introduces a simple, low-cost solution for reducing pre-
amplifier power consumption. Therefore, for applications where performance is not
bottlenecks, such as wireless sensor nodes or IoT devices, a flexible bias is an interesting
decision to reduce power consumption. At standard mode voltage, a 0.6V VCM (VDD / 2),
the flexible operating parameter works 2.5 times more efficiently than its predecessor,
making it an ideal building block for such low power applications.
11
2.3 Principle of Strong-Arm Latch Comparator

Update compression analysis is applied to the Strong-Arm latch. Despite the non-linear
durability and variability of these circuits, the same simple circuits have been developed to
accurately reflect offsets, sound and speed. The solid ARM band, first proposed by
Kobayashi et al in 1993, is one of the most widely used stimulant compounds. Due to the
combined challenges arising from circuit inequalities and the performance of time-varying
circuits, it is not yet well understood. It handles a solid ARM latch similar to a line divider
amplifier and thus fails to distinguish between fixed and flexible suspension. The natural
variability of the nature of reflexive comparisons was first noted in audio research literature.
Extends the frame to incorporate dynamic offsets caused by capacitor load imbalances,
however the results are only partially correct due to a lack of theoretical tool to deal with
circuit imbalances.

Refreshing comparisons have different types of configurations. The powerful ARM was
selected for analysis in this study for two reasons. First, it has a soft circuit function with a
large embedded extension, which further compresses the sound and offset. Second, because
of its fragile configuration, it is undoubtedly a major challenge to present.

2.4 Benefits to society

Drones already have a huge impact on people’s lives, the proposed StrongArm latch
controls the dissipation of static power by capturing the current tail source. It also produces
full-scale output fluctuations.

These benefits of StrongArm latch make it ideal for low-power digital circuit applications.
The StrongArm clock is reset throughout the clock cycle.

It provides an easy way to introduce a voltage that will be renewed into a pair of integrated
inverters.
The main problem of power dissipation for conventional comparisons has been mitigated
by the use of StrongArm latch.

12
 CHAPTER – 3
DESIGN SPECIFICATIONS
3.1 List of components
In this project, we will use certain common parts of Strong-Arm latch that meets our
requirments.The list of components used are:-
Table 1: List of components
COMPONENT NAME REFERENCE PICTURE

NMOS

PMOS

CLOCK PULSE

SIGNAL SOURCE

13
VOLTAGE SUPPLY

DIGITAL OSCILLOSCOPE

3.1.1 NMOS
NMOS circuits were much faster than PMOS and CMOS circuits, which had to use very
sluggish p-channel transistors. It was also easier to do NMOS than CMOS, as the latter had
to use p-channel transistors in special n sources on the p-substrate. The biggest drawback
with NMOS (and many other sensible families) is that the current DC has to flow through
a sensible gate even when the output is in stable condition (low in NMOS mode). This
means a constant power outage, i.e. a power outage even when the circuit is unchanged.
The same situation arises with today's high speeds, very dense CMOS circuits
(microprocessors, etc.) also have an important dry current, although this is due to leakage,
not bias. However, older and / or static CMOS circuits used for ASICs, SRAM, etc., usually
use very low static power.
Additionally, as in DTL, TTL, ECL etc., asymmetric input logic standards make NMOS
and PMOS circuits easier to audio than CMOS. This is why CMOS LOGIC has now
replaced many of these models in high-speed digital circuits such as microprocessors
(despite the fact that CMOS was initially slow compared to sensible gates made of bipolar
transistors).

14
 Fig 3.1 NMOS Block Diagram

Table 1: Specifications of NMOS

Operating Voltage 0.120-0.282v

Input Voltage 4.8-6.0v

Material Used Semiconductor (SI or Ge)

Threshold Voltage 0.45v

Signal from Transmiiter 10us

Channel Length 20um

Pin count 3

Software required No Requirement

Size 0.22um

15
3.1.2 PMOS

The p-channel was made using a negative voltage (-25V was normal [18]) in
the third terminal, called a gate. Like other MOSFETs, PMOS transistors have
four modes of operation: cut-off (or subthreshold), triode, saturation
(sometimes called active), and acceleration.
Although PMOS logic is easy to design and produce (MOSFET can be made
to act as an adversary, so the whole circuit can be made with PMOS FET), it
has a few flaws as well. The most unpleasant problem is of direct current (DC)
through the PMOS logic gate where the so-called "pull network" (PUN)
operates, that is, whenever the output is high, leading to the loss of static power.
even when the region is sitting unused.
Also, PMOS circuits are slow to change from top to bottom. While switching
from low to high, the transistors deliver low resistance, and capacitive charging
at output collects very quickly (similar to charging a capacitor using very low
resistance). But the resistance between the outlet and the negative supply rail is
very large, so the transition from top to bottom takes lengthier time (such as
removing a capacitor with high resistance). Using a low value resistor will pace
up the process but also increase the power dispersion.

16
 Fig 3.2 Structure Of PMOS

Table 2: Specifications of PMOS

Input Voltage 5-10v

17
 Threshold Voltage 0.485v

Size 0.594um

Pin 3

Operating Voltage 0.110-0.250v

3.1.3 CLOCK PULSE

The most effective way to get a clock signal to every part of the chip you need, with a very
low skew, metal control grid. In a large microprocessor, the driving power of a clock signal
can be more than 30% of the total power used by each chip. Every building with gates at
the end and all amplifiers in between should be loaded and lowered all cycles. To save
energy, the timing clock closes part of the tree temporarily.
Most digital devices do not require a timer in fixed, unchanging frequencies. As long as the
minimum clock times are acknowledged, the time between clocks can fluctuate greatly
from one edge to the later and back again. Such digital devices work well with a variable
frequency generator, such as Spread-Spectrum Clock Generation, Dynamic Frequency
Scaling etc.
The delay components that make up a common sync system are made up of the following
three sub-systems: memory devices, logical objects, and a clock network and distribution
network.
In CMOS circuits, gate power is charged and dismissed continuously. A capacitor does
not waste energy, but power is wasted on driving transistors. In Reversible

Computing, Inductors can be used to store this energy and reduce energy loss, but it is
usually quite large.

18
 Fig 3.3 : Waveform Of Clock Pulse

Table 3: Specifications of Clock Pulse

Type Analog Wave

Name Square Wave

Time period 50%

Frequency 50Hz

Amplitude 5-10v

3.1.4 SIGNAL SOURCE

Funk Generators are usually a piece of electronic test used to produce different types of
electrical waveform over a wide range of frequencies. Some of the most common types of
waves produced by a work generator are fourteen waves, a square wave, a triangular wave
and a saltooth shape. These waves can be recurring or even one shot

(requiring internal or external trigger source) .The Integrated cycle used to generate
waveforms can also be defined as activity-generating ICs.

19
In addition to producing sine waves, active generators may produce other recurring waves
that include sawtooth waves as well as triangular waves, square waves, and pulses. Another
highlight included in many operating generators is the ability to add DC offset.

Although functional generators cover both audio and RF frequencies, they are generally
not suitable for applications that require low distortion or stable signal frequencies. If those
features are required, other signal generators are more suitable.

Some operating generators can be secured partially from an external signal source (which
may be a reference reference) or other generator generator function.
Functional generators are used in the development, testing and maintenance of electrical
equipment. For example, they can be used as a signal source to check amplifiers or to
launch an error signal in the control loop. The operating generators used primarily to
operate with analog circuits related to pulse generator pulses are mainly used to operate
the digital circuit. A standard operating generator can deliver up to 20 MHz waves. RF
high frequency generators are not the most efficient generators as they usually only
produce clean or modified signals.

A 50% square wave of activity cycle is easily detected by noticing that the capacitor is
being charged or discharged, which is displayed in the current output of the alternating
current. Other activity cycles (in theory from 0% to 100%) can be detected using a
comparator and a saw or triangle signal. Many active generators consist of an indirect
diode cicuit that forms a cicuit that can turn a triangular wave into a precise sine wave by
shortening the corners of the triangular wave by a process similar to attaching to sound
systems.

20
 Fig 3.4 Signal Generators

Table 6: Specifications of Signal Generators

DC Offset <-1 0 V to >+1 0 V (open circuit)

<-5 V to >+5 V (into 50 ohm load)

Frequency Ranges 0.1 Hz to 11 MHz, up/down range

switchable in eight decade step

Main Output Impedance 50 ohm ±10%

Internal Sweep Rate Continuously variable from 0.5 to 50 Hz

21
3.1.5 VOLTAGE SUPPLY

A good power source is a two-wire device that retains a constant voltage drop across all of
its terminals. It is often used as a summary of statistics which makes it easier to analyze
real electronic circuits. If the whole voltage is a good source of electricity can be specified
without any other variable is a circuit, called an autonomous voltage source. On the
contrary, when the voltage across a positive voltage source is determined by a specific
voltage or current in a circuit, it is called a dependent or controlled voltage source. The
scientific model of the amplifier will incorporate power-dependent power sources whose
size is controlled by other related focus factors in the input signal, e.g. In the fault analysis
of the power system, the entire network of sources connected to the transmission lines can
be effectively converted to a positive energy source (AC) with a single block.

Corresponding power sources share current load: If the actual voltage converter is
connected in line with the first, one of them will provide half of the actual power source
that the power supply can deliver. For the rest of the circuit, nothing has changed: These
two combined power sources provide the same voltage, and the same current as the first
one.

The internal resistance of a good power source is zero; able to supply or absorb any current
value. The current through the ideal voltage source is entirely governed by the external
circuit. When connected to an open circuit, there is zero current and thus zero power. When
connected to a load resistance, the current through the source set about infinitely as the load
resistance approaches zero (short circuit). Thus, a good find of electricity can provide
unlimited energy.

There is no actual source of electricity; they all have active internal resistance other than
the egg, and nothing can provide unlimited modernity. However, the internal resistance of
a real power source is successfully demonstrated in a straight circuit analysis by combining
non-egg resistance in the sequence with the appropriate power source.

When two independent power sources are directly connected, they must have exactly the
same voltage; If not, it creates an error in the mind, such as writing down a number.

22
 Fig 3.5 Voltage Supply

Table 5: Specifications of Voltage Supply

Type Alternating Current

Voltage Range Upto 200kv

Frequency 50Hz

3.1.6 DIGITAL OSCILLOSCOPE

Digital strorage Oscilloscope is an oscilloscope that keeps and analyzes digital input
signal rather than using analogue techniques. It is now the most common type of
oscilloscope used because of the improved trigger, storage, display and measurement
features it usually provides.

The input analogue signal is taken from the sample and converted to a digital record of
the size of the signal at the time of each sample. Sample frequency should not be below
Niquist level to avoid naming. These digital values are then converted into an analogue
signal to be displayed on a cathode ary tube (CRT), or converted as needed
23
with a variety of potential outputs --- liquid crystal display, chat recorder plotter or virtual
network connector

A personal computer-based digital oscilloscope depends on a PC for the use of the interface
and display. "Front" circuits, which include input amplifiers and analog converters to
digital, are packaged separately and connect to PC via USB, Ethernet, or other virtual
connectors. In one format, "front" is integrated into a plug-in expansion card that is plugged
into a desktop aircraft. PC-based oscilloscopes may cost less than the same device itself as
they can use memory, display and attached PC keyboard. Displays may be large, and the
acquired data can be easily transferred to a PC-controlled software application such as
distribution sheets. However, the optical connector on the host PC can limit the maximum
amount of data received, and the host PC may produce enough electromagnetic noise to
disrupt the ratings.

Digital oscilloscopes often analyze waveforms and provide numerical values and visual
cues. These values typically include averages, maxima and minima root mean square
(RMS) and frequencies that can be used to capture temporary signal when working in single
sweep mode, without light and speed limit analog storage oscilloscope.

The displayed tracking can be changed after detection; part of the display can be enlarged
to make the details more visible, or a longer trail can be explored on a single display to
identify areas of interest. Many tools allow the saved track to be defined by the user.

24
 Fig 3.6 Digital Storage Oscilloscope

Table 6: Specifications of DSO

Display Resolution 320 Horizontal 240 Vertical Pixels

Display contrast Adjustable

Sensitivity and accuracy 2200 mAh

Output Voltage 2nV;Div-GV;Dv

25
 CHAPTER – 4
4.1 Overall Operation

The change between two input voltages, each evaluated with relation to ground, is
connected into the latch through the NMOS pair M1-M2. The pair is activated by the tail
FET, MCLK, which is supposed to act sort of a switch. The input voltage common-mode
(VIC) must be positioned above the edge voltage of M1, M2 and sets the initial bias
current. This bias current also flows through the cross-coupled inverters, M3-M5 and M4-
M6, that are stacked asynchronous. Differential current produced by M1-M2
“unbalances” the inverter, triggering it to regenerate on this imbalance. Regeneration
forces one FET in each inverter to show OFF, thus choking off a current flow path
through both M1 and M2. Thus M1, M2, and therefore the tail current FET are all forced
into deep triode with VDS = 0 where they not conduct current. The comparator consumes
no static power in its regenerated state. This description is adequate to determine why the
StrongARM latch is popular. a more in-depth analysis is required to know aspects like the
circuit’s innate latency before it regenerates, and the way unbalances within the circuit
elements will cause static and dynamic offsets.

Fig. 4.1 Strong Arm Latch Topologies

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 a. Original Design
b. Proposed Design

4.2 Operational Phases

The circuit’s operation should be divided into three discrete phases, with regeneration
justifiably happening within the last phase. within the first two phases, sampling and
propagation, the circuit magnifies the applied discrepancy voltage on to internal nodes, as
explained.

4.2.1 Reset State

The phases are most evidently discovered when the comparator is released from a well-
described state. The circuit is characterized by four state variables, the voltages on two
grounded capacitors CC and on two load capacitors CL. But it's a time-changing circuit,
and when within the second and third phases the capacitors switch charge, the quantity of
states collapses to 2. Be that because it may, the circuit must be adjusted with all four
states at a predetermined and stuck value so on erase memory of the previous
rejuvenation. A convenient initialization 24 is to precharge all four capacitor voltages
through FET switches to the provision voltage VDD. This initializes the supply and sink
terminals of M3-M6 all to the identical potential.

4.2.2 Sampling Phase

The input voltages Vin1 and Vin2 are applied when the tail current transistor MCLK is
initialized. the typical input voltage sets the bias current (I0) through M1 and M2. This
common-mode current can initially only discharge CC1 and CC2. M3 and M4 will
remain OFF, until the capacitors have discharged by an amount satisfactory to the
brink voltage VtN . this era of your time explains the sampling phase, Ts = CC · VtN I0
(2.16) Over this era the difference within the input voltages vID, which creates a
differential current iID = gm1,2vID, integrates a differential voltage across the capacitors
CC. this is often best seen in a very differential half circuit as shown in Fig (b) VCD,s =
iID · Ts CC (2.17) This differential voltage is the initial condition for the
subsequent phase, propagation.

4.2.3 Propagation Phase

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In propagation phase, M3 and M4 will activate, and by the top of this phase the common
mode (bias) current flowing through them will have discharged both output voltages VO1
and VO2 by |VtP | to show on the cross-coupled PMOS pair M5, M6. During the
propagation phase M1, M2 and M3,M4 are ON. The voltages on capacitors CC and CL
will slope down together, segregated by the continual difference of VGS3(= VGS4).
Thus, Tp = (CL + CC)|VtP | I0.

4.3 Working

The latch consists of 11 transistors: charging transistors (CT1, CT2, CT3, and CT4), cross-
coupled transistors (T1, T2, T3 and T4), input transistors (T5 and T6) and one tail current
transistor (T7). The operation of the latch consists of three phases:

1) Reset

2) Amplification

3) Regeneration

❖ Reset phase starts when the CLK goes Low.

❖ Amplification phase starts when the CLK goes High, turning all CTs OFF and
allowing the capacitors to discharge through T7.

❖ Regeneration phase starts when the voltage at either A or A’ drops to (VDD - Vthp)
turning either T1 or T2 ON, and the other transistor remains OFF due to the
crosscoupled configuration.

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 Fig. 4.2
Operation
Phases of Strong
Arm Latch

4.4

Limitations

One of the limitation during this topology is that the clock feedthrough problem. The clock
feedthrough effect is because of the gate-source (or gate-drain) coupling. This
problem may be reduced by connecting capacitors/transistors at the gate of the charging
transistors, or replacing the charging transistors with transmission gates. By adding
transistor (or capacitor), the whole capacitance within the circuit is increased, and hence,
the speed of the latch is decreased.

4.5 Results

In general, to enhance the performance of the circuit, it's desired to extend this. This can
be achieved by increasing the width of the transistors. However, increasing the
width will increase the overall capacitance within the circuit, hence, the
online performance will remain the identical. In other words, to enhance the performance
of the latch, the whole capacitance within the circuit should be reduced without
decreasing this, or contrariwise.

4.6 Proposed Design Theory

The proposed design consists of 9 transistors. The key gain of this design is lowering the
full internal capacitance within the circuit without negotiating the present. This is
often accomplished by placing the input electronic transistor within the middle between
the cross-coupled transistors.

29
Since the input transistors are always ON, the requirement for the CT3 and CT4 is
excluded and nodes B and B’ are renewed through the transistors T5 and T6. Therefore,
the performance and therefore the power efficiency of the latch are improved, while the
world and also the clock feedthrough problem are reduced.

Fig. 4.3 Proposed Design of Strong-Arm Latch

4.7 Operation of the proposed and conventional latches

The proposed and conventional latches are modeled in the 90nm technology. It shows
the Reset, Amplification and Regeneration phases when Vdiff equals 1mV for both
the proposed and the standard latches.

30
 Fig. 4.4 Operation of the proposed and conventional latches

4.8 Energy and Delay Comparison

(i) 90 nm technology

31
 (ii) 32 nm technology
Fig. 4.5 Energy and Delay Comparison

4.9 Performance Comparison

Table 4.1 Performance Comparison at 32nm and 90 nm technology

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 CHAPTER – 5

5.1 Conclusion

• The proposed architecture improves the speed performance in comparison to the

traditional latch.
• The proposed design is able to provide a rail-to-rail output in a quicker time
(modified version).
• The clock feedthrough problem is decreased in both the Amplification and Reset
phases. it's also noticeable that the Reset introduce the proposed design
takes longer to restore the circuit.
• The proposed cascade cross-coupled dynamic comparator improves the
differential gain of the pre-amplifier and reduces the common-mode voltage
which results in much faster regeneration at small input difference.

5.2 Inference

An improved Strong ARM latch comparator topology is offered within

the proposed design, by putting the input transistors between the cross-coupled
transistors, the total internal capacitance is lowered without negotiating the present.

HSPICE models and estimation of our design in 90nm and 32nm CMOS
technologies, provided by Synopsys, show that the proposed topology can deliver
outstanding performance, better energy efficiency and lower clock feedthrough
compared to the traditional solutions.

33
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