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Implementing Fuzzy Control Systems Using VHDL and Statecharts

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 Implementing Fuzzy Control Systems
Using VHDL and Statecharts

Valentina Salapura, Volker Hamann

{valentina,volker}@vlsivie.tuwien.ac.at

Technische Universität Wien

Treitlstraße 1–182–2
A–1040 Wien
AUSTRIA

Abstract The fuzzifier and defuzzifier parts of the system, which incor-
porate a lot of mathematical computations, are described in
In this paper, we propose an approach for designing fuzzy VHDL as a hand-coded design. We assemble the fuzzy con-
controllers. To reduce design time, we employ two high-level trol system, and synthesize a gate level description for field-
design methods: VHDL and VHDL-based logic synthesis, programmable gate array (FPGA) technology.
and Statecharts with a VHDL backend for graphical design This paper is organized as follows: in section 2 we give
description. A fuzzifier and a defuzzifier parts of a fuzzy con- a brief introduction to fuzzy controllers. Section 3 lists de-
trol system are captured in VHDL, as these parts perform sign choices we have made, and section 4 brings a descrip-
complex arithmetical operations. A rule base of the con- tion of the design flow. Section 5 shows how is a rule base
troller is described in Statecharts, and then is translated into of a fuzzy controller described in Statecharts. A fuzzifier and
VHDL. A complete description of the system is assembled in a defuzzifier of the controller are modeled in VHDL, as pre-
VHDL, and is synthesized using VHDL-based logic synthe- sented in section 6, and section 7 brings the translation of the
sis. The efficiency of the generated hardware is explored for rule base to VHDL. Section 8 outlines the testbench genera-
FPGA technology. tion. The developed model is synthesized and implemented
as sketched in section 9. We draw our conclusions in sec-
tion 10.
1 Introduction
2 Fuzzy controllers
Today, still only a few full custom or semi-custom in-
tegrated fuzzy controllers exist and most of them are as- In this section, we introduce a simple controller for a gas
sembled from standard cells at the gate level. Our design heater system, which serves as an example to the various
approach presented here is a high-level one. The usage steps involved when designing a fuzzy controller. The con-
of high-level modeling methodologies for modeling fuzzy troller is sensitive to two input variables delivered by sen-
controllers reduces development time significantly, making sors: the room temperature and, assuming there is no stable
rapid design of custom fuzzy hardware possible. gas quality, the current gas heating value. The controller’s
VHDL [5] for design capture and VHDL-based logic syn- output influences the valve opening angle for the gas supply
thesis are an efficient method for designing complex hard- via an active element, e.g., a servo motor.
ware. However, for describing regular structures like finite- A membership function gives the degree of membership
state machines, a different approach is more appropriate. For of an input value to every fuzzy set. The input may belong
describing such structures, we employ Statecharts. In addi- to more than one fuzzy set. In the example application, the
tion, a commercial tool based on Statecharts incorporates a sensed room temperature is divided into three overlapping
VHDL generation facility for generating synthesizable code. fuzzy sets called “cool”, “tepid”, and “warm”. A similar
We have employed the Statecharts formalism for capturing classification and membership assignment are made for the
a rule base of a fuzzy control system. Using this high-level gas quality, namely “poor”, “medium” and “high”.
approach, design time is reduced significantly, and different In figure 1, we show the calculation of the output variable
designs of the rule base can be explored in the short time. valve angle when concrete values are assigned to the inputs
temperature (denoted i1 ) and quality (denoted i2 ). The value  a dedicated chip offers the highest execution speed,
i1 is a member of fuzzy sets “cool” and “tepid” with mem-
bership degrees f11 (i1 ) and f12 (i1 ). For the value i2 , only the  design time is short, due to the usage of synthesis and
fuzzy set “medium” is relevant with a membership degree high-level design tools,
f22(i2 ).  low cost of real-estate.
The fuzzified input variables are inputs to the rule base.
The sample controller uses nine rules, displayed in table 1, to For designing a rule base of a controller, we have used a
find an output fuzzy set. Rule 32, for example, is interpreted high-level modeling approach instead of encoding it directly
in full English text as: in VHDL. The reasons for this choice are:
if temperature is tepid and gas quality is  a high-level design approach reduces the design time,
medium then valve angle is half
 global design functionality is evaluated in a short time,
In our example, the rule R21 selects the output fuzzy set
“large” with the membership degree min(f11 (i1 ); f22 (i2 ))  different design choices are quickly explored,
and the rule R32 the output fuzzy set “half” with the mem-
bership degree min(f12 (i1 ); f22 (i2 )).  edit-compile-debug cycle is fastened [4],
The membership degrees delimit the output set defining an
 the design is represented graphically in a natural and un-
area. The solution fuzzy set is composed by combining all
derstandable way,
such areas, and taking the ordinate of the gravitational center
of the area.  translation of a high-level model into VHDL is sup-
memb. ported, so that VHDL-based logic synthesis can be em-
degree ployed.

According to Costa et al. [1], in describing a fuzzy controller

i1 TEPID I1
memb.
COOL WARM in VHDL as hand design, the most time consuming process
degree is writing a synthesizable VHDL description at the register-
transfer level. The usage of high-level design tools reduces
i2
these efforts.
POOR MEDIUM HIGH I2
memb. For high-level modeling, we have selected Statecharts, be-
degree
cause of

o
 existence of tools supporting system modeling in State-
TINY SMALL HALF LARGE HUGE O
charts,
Figure 1. Input and output fuzzy sets.  support for validating Statecharts models,

 support for converting Statecharts models in VHDL,

Rule Temperature Gas quality Valve angle
R11 COOL POOR HUGE  efficiency of Statecharts for hardware modeling.
R21 COOL MEDIUM LARGE
R22 TEPID POOR LARGE
Modeling a rule base of a fuzzy control system in State-
R31 COOL HIGH HALF
R32 TEPID MEDIUM HALF charts is efficient and simple, because of the rule base regu-
R41 TEPID HIGH SMALL larity. The graphical presentation of a rule base is easily un-
R42 WARM POOR SMALL derstandable, and easier to survey and adapt than a VHDL
R51 WARM HIGH TINY
R52 WARM MEDIUM TINY
description. Additionally, the built-in simulator of the front-
end tool supports the quick validation of the actual model.
Table 1. Fuzzy rule base for the gas heater control. Using the Statecharts formalism we were able to explore sev-
eral different rule bases in a short time. Simulating the State-
charts model under a Statecharts simulation environment, we
3 Design choices have fine-tuned the rules, and then picked the best rule base
for hardware implementation.
We have implemented a dedicated fuzzy chip, capable A fuzzifier and a defuzzifier of a fuzzy control system
of performing stand alone operations, rather then to extend perform mathematical operations, such as multiplications
some general purpose processor with fuzzy instructions. Our and divisions. For describing such parts, direct encoding
decision is influenced by several facts: in VHDL at the register-transfer level is more efficient. In
 rules
VHDL, the minimal number of multipliers, adders and di-
class_1 class_2
viders can be instantiated, resulting in a more efficient real-
ization. rule_11 C11 rule_21 C21

We have used field-programmable gate arrays (FPGAs) as rule_12 C12 rule_22 C22
hardware platform, because they are complex enough to be O1 O2

used for rapid prototyping of complex systems, and for the

final implementation of a chip, if only a small number of rule_1k C1k rule_2m C2m
pieces is needed. They offer more flexibility than ASICs, as
when a design is not needed any more, the chip can be repro-
grammed for a new hardware. Figure 2. Statecharts model of a rule base.

huge large
4 Design flow and environment memb_ang(0) = min11; memb_ang(1) = max(min21, min22);

huge O1 large O2
The rule base and the fuzzifier and the defuzzifier are
modeled in parallel and separately in different design en-
half
vironments. For designing the rule base we have used the memb_ang(2) = max (min31, min32);

Statecharts-based SPeeDCHART design tool [2], whereas entry

half O3

for validating the fuzzifier and the defuzzifier, and for inte-
grated system simulation we employ the Synopsys VHDL small tiny
memb_ang(3) = max(min41, min42); memb_ang(4) = max(min51,min52);
system simulator [8].
The Statecharts model is converted to a VHDL code using small O4 tiny O5

the export facility of SPeeDCHART. The VHDL models of

all system parts are integrated, and further system simulation
and debugging are performed under the VHDL environment. Figure 3. Statecharts model of the rule base of the gas
We have used the Synopsys VHDL design analyzer/FPGA heater controller.
compiler [7] for logic synthesis. Additionally, we have
used the XSI Xilinx/Synopsys interface [11] and X-BLOX as
cell generator (XACT 5.1). The target technology is Xilinx hierarchical level. The membership degrees of the result sets
XC4000 FPGAs [10]. are calculated as indicated.

5 A Statechart model of the rule base 6 VHDL models of the fuzzifier and the de-
Each rule of the base has the form: fuzzifier

if p1 andp2 and : : : and p then Cn

While the rule base is described in Statecharts, the fuzzi-
fier and the defuzzifier used in our fuzzy controller have been
where p , 1  i  n denotes the premises of this fuzzy rule,
i described in hand-optimized VHDL.
and C is its conclusion. As soon as all fuzzified inputs are Inputs to the fuzzifier are input variables (8 bit wide), and
available, the rule is applied. outputs are vectors containing membership degrees for all in-
We represent every rule with a substate rule_ij, as put fuzzy sets. To each input fuzzy variable corresponds one
shown in figure 2. The state Cij is entered as soon as all input output vector, whose range depends on the number of fuzzy
variables are available, and if all premises of the rule are sat- sets (number of fuzzy sets multiplied by 8).
isfied. The membership degree of the output fuzzy set is cal- A part of the VHDL description of a fuzzifier is given in
culated in this state, by finding the minimum of the premises’ figure 4. In the architecture body, membership degrees of the
membership degrees. input signal are calculated for each fuzzy set. In an early ver-
Rules with the same conclusion are grouped. If any con- sion, we have added inputs for changing the ranges of fuzzy
clusion of this subset of rules is reached, the transition to the sets. So, we could change the ranges of fuzzy sets without
state Oi is taken. The conclusive membership degree of the having to recompile the source code. Once the ranges of the
class i is calculated as the maximum of all conclusive mem- input sets are determined, these inputs are removed from the
bership degrees of the rules in the group. entity declaration, and are declared as constants.
A part of the Statecharts description of the rule base for the The generated hardware contains several comparators, an
gas heater application is shown as hierarchical decomposi- adder and a multiplier. To handle several input variables, two
tion in figure 3, produced by the SPeeDCHART tool. Five approaches are possible: a) for each input variable, a fuzzi-
statecharts, one for each rule group, activate the output fuzzy fier handling one input variable is instantiated, or b) a sin-
sets. Rules of the same class are described at the next lower gle component is used for fuzzification of all input variables,
 Proc_fuzzifier: PROCESS (in_var)
BEGIN
IF reset = ’1’ THEN
memb_var => (Others <= ’0’);
ELSIF clock’EVENT AND (clock = ’1’) THEN
IF (in_var < tm1m) THEN
tmp :=conv_std_logic_vector(unsigned(unsigned(in_var) - unsigned(start)) * unsigned(delta), 8);
memb_var(7 downto 0) <= tmp;
memb_var(set_nr*8-1 downto 8) <= (Others => ’0’);
ELSIF (in_var < tm2m) THEN
tmp := conv_std_logic_vector(unsigned(unsigned(in_var) - unsigned(tm1m)) * unsigned(delta), 8);
memb_var(7 downto 0) <= conv_std_logic_vector(1 - unsigned(tmp), 8);
memb_var(15 downto 8) <= tmp;
memb_var(set_nr*8-1 downto 16) <= (Others => ’0’);
ELSIF (in_var < tm3m) THEN
...
END PROCESS;

Figure 4. Part of the VHDL description of a fuzzifier for one input variable.

Add_and_divide: PROCESS(clock, reset)

BEGIN
IF reset = ’1’ THEN
nomin_reg <= (Others => ’0’); denomin_reg <= (Others => ’0’);
ELSIF clock’EVENT AND clock = ’1’ THEN
IF (present_step = First) THEN
nomin_reg <= unsigned(nomin_reg) + unsigned(conv_std_logic_vector
(unsigned(memb_var(1*8-1 downto (1-1)*8)) * unsigned(an1m), 16));
denomin_reg <= unsigned(denomin_reg) + unsigned(memb_var(1*8-1 downto (1-1)*8));
ELSIF (present_step = Second) THEN
...
ELSIF (present_step = Divide) THEN
out_var <= nomin_reg / denomin_reg;
END IF; END IF;
END PROCESS;

Figure 5. Part of the VHDL description of a defuzzifier. The division unit is implemented as a function.

multiplexed in time. The decision which approach to use de- mented a 17 by 9 bit division as eight subtractions performed
pends on area and performance constraints. successively.
The defuzzifier is modeled in a similar way. Inputs to the A part of the VHDL description of the defuzzifier is
defuzzifier are vectors, one for each controlling variable. The listed in figure 5. The input is a membership set vec-
range of the vector is determined by the number of the solu- tor (memb_var) and the output is the control variable
tion fuzzy sets – it contains an 8 bit membership degree for (out_var) 8 bit encoded. A finite state machine controls
each output fuzzy set. The defuzzifier determines the gravi- five successive additions and multiplications, and then starts
tational center of the solution fuzzy set, and delivers the re- the dividing unit.
sults as an 8 bit output control signal.
7 A VHDL description of the rule base
In implementing the defuzzifier, we have used the method
proposed by Yager [3]. This approach requires 2N additions, The high-level description of the rule base in Statecharts
N multiplications, and one division, where N is the number is translated to synthesizable VHDL code. The conversion is
of output fuzzy sets of a single output variable. We have re- performed because of the following reasons: having all parts
duced the hardware to two adders, one multiplier, and one of a system in the same language makes the verification of
divider. The adder and the multiplier are multiplexed in time the whole system possible, and logic-level synthesis tools do
to perform 2N additions and N multiplications. not support synthesis from a graphical description.
In our application with one output variable and five fuzzy A part of the code generated from the Statecharts descrip-
sets, we have to perform five additions and multiplications, tion of the rule base is given in figure 6: This code evaluates
before the division can start. The division unit is imple- rule R21 from the rule base. In process Rule_21, the cal-
mented to be fast, at the cost of chip area. We have imple- culation of the minimal membership degrees of the premises
 Rule_21: PROCESS (memb_temp, memb_qual, state_large_1)
BEGIN
CASE state_large_1 IS
WHEN S21b =>
min21<= min(memb_temp(COOL), memb_qual(MEDIUM));
WHEN others => null;
END CASE; END PROCESS;
Out_calc: PROCESS(..., min21, min22, out_large, ...)
BEGIN
CASE out_large IS
WHEN o2 =>
memb_ang(1) <= max( min21, min22 );
WHEN others => null;
END CASE; END PROCESS;

Figure 6. A part of the VHDL description of the rule base.

of rule 21 is performed. Rule R21 together with rule R22 The proposed method has several advantages:
belongs to the rule group with the conclusion “large”. In
process Out_calc, the maximum calculation for this rule  the designer is obliged to spend more thought on the en-
group is performed. vironment of the system, almost as much as in a design
The generated VHDL code is easy to read, and is simi- method based on formal semantics. As he does so in an
lar to hand coded VHDL code. A difference is the usage early design phase, the costs of searching for an optimal
of case statements for encoding rules, instead of an if - solution can be kept small,
then statement, which may be a more natural choice in the
coding process. From the hardware efficiency point of view,  high level design tools encourage the use of Statecharts
both coding styles result in the same hardware realization. models not only for the design itself but also for simu-
Another difference is the partitioning of each rule in distinct lation testbenches,
processes.
 when reaching the FPGA prototype level, it is much
A graphical presentation of a rule base is much easier to
cheaper to test the system prototype by connecting it
understand, as well as to model, than VHDL. The usage of
to another FPGA prototype of the system environment.
a high-level modeling approach reduces the design time sig-
Especially in an industrial environment where expen-
nificantly.
sive machines are controlled by electronic devices, er-
roneous behavior in the integration test stage may have
8 Simulation and testbench creation
disastrous consequences.
Statecharts are not only suitable for designing state-based
reactive systems themselves but can also be used for specify- 9 Synthesis and technology mapping
ing their working environment and thus may serve as a basis
for testbench development. Instead of developing case stud- After design verification, the Synopsys design compiler
ies and/or test vectors, the designer creates a model of the en- [7] is used to perform logic synthesis. The result of synthesis
vironment and steps down the design process in parallel with is a gate-level description of the controller.
the controller itself. Table 2 shows the results of synthesis of the example fuzzy
The testbench as well as the controller are modeled in the controller with two input and one output variables, and a rule
same way. Like for the controller development, Statecharts base consisting of nine rules. The number of fuzzy sets of in-
can be used as a design front-end for the rule base testbench. put variables is three, and for the output variable is five. The
The controller is then simulated directly in Statecharts or – resolution of all variables is 8 bits.
after VHDL generation – in the VHDL environment. The implementation of the fuzzifier instantiates two fuzzi-
There is a significant improvement in design time and fault fication units, one for each input variable. Each unit contains
coverage compared to standard testing methods. Using the three comparators, an adder and a multiplier. The number of
described method, we were able to implement our design comparators depends on the number of input fuzzy sets. If
controller in a couple of days. The most time consuming area constraints are critical, only one fuzzification unit can be
process was the encoding of the fuzzifier and defuzzifier in used, multiplexed in time, for fuzzifying several input vari-
VHDL. Especially when designing the rule base, the interac- ables. In our design, we have used a separate unit for each
tive testing and observation of the external behavior is eased input variable. The realization is scalable to any number of
considerably. variables.
 Synopsys Fuzzifier Rule Base Defuzzifier was captured and verified by simulation using the SPeeD-
Number of gates 1756 1062 2025 CHART design and simulation environment. A simulation
Number of CLBs 136 72 193 under a graphical environment makes it easy to see which
Time delay (ns) 4.75 6.24 4.75 rules are applied. The Statecharts description of the rule base
is translated into VHDL, and integrated with the hand-coded
Table 2. Synthesis results. Number of gates is given VHDL code realizing fuzzification and defuzzification com-
for the LSI 10k library. ponents. Finally, the system model is synthesized to logic
level and mapped to FPGAs.
The most distinctive problem coming up when using the
introduced method is the lack of back-annotation facilities
The defuzzifier calculates one output variable for five
between Statecharts and VHDL. Once the VHDL code has
fuzzy sets. Thus, this implementation performs five multipli-
been generated, there is no way back to the Statecharts level.
cations and additions, multiplexed in time, and one division.
One of the advantages of the proposed method is the sim-
The implementation contains two adders, a multiplier, and a
plicity of constructing and experimentally fine-tuning the
divider. We have implemented a fast divider unit at the cost
rule base. Taking the standard language VHDL as backend
of chip area.
opens all facilities to make use of synthesis tools. Thus, we
A defuzzifier for handling several output variables can be receive all benefits of rapid prototyping and shortening time-
implemented on different ways: a single defuzzifier can be to-market requirements.
multiplexed in time, separate defuzzifiers can be used for
each output variable, or some combination of two. The se- 11 Acknowledgment
lection of the hardware configuration depends on the area and
performance constraints of the particular design. The authors wish to thank to Michael K. Gschwind for his
We have compiled our models targeting two technologies: help with various issues related to VHDL and optimization
Xilinx FPGAs and the LSI 10k ASIC library. For FPGA for FPGAs, and in preparation of this article.
implementation, the measure area efficiency is expressed in
number of CLBs (configurable logic blocks), whereas for References
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