24LC21

1K 2.5V Dual Mode I2C Serial EEPROM

FEATURES PACKAGE TYPES

• Single supply with operation down to 2.5V PDIP
• Completely implements DDC1/DDC2 inter-
face for monitor identification NC 1 8 VCC
• Low power CMOS technology
NC 2 7 VCLK

24LC21
- 1 mA active current typical
- 10 µA standby current typical at 5.5V NC 3 6 SCL
• 2-wire serial interface bus, I2C compatible
• Self-timed write cycle (including auto-erase) VSS 4 5 SDA
• Page-write buffer for up to 8 bytes
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Factory programming (QTP) available SOIC
• 1,000,000 erase/write cycles guaranteed
• Data retention > 200 years NC 1 8 VCC
• 8-pin PDIP and SOIC package
2 7

24LC21
• Available for extended temperature ranges NC VCLK
- Commercial (C): 0˚C to +70˚C 3 5
- Industrial (I): -40˚C to +85˚C NC SCL

4 5
DESCRIPTION VSS SDA

The Microchip Technology Inc. 24LC21 is a 128 x 8 bit

Electrically Erasable PROM. This device is designed for
use in applications requiring storage and serial trans-
mission of configuration and control information. Two BLOCK DIAGRAM
modes of operation have been implemented: Transmit
Only Mode and Bi-Directional Mode. Upon power-up, VCLK
the device will be in the Transmit Only Mode, sending a
serial bit stream of the entire memory array contents, HV GENERATOR

clocked by the VCLK pin. A valid high to low transition

on the SCL pin will cause the device to enter the I/O MEMORY EEPROM
CONTROL CONTROL
Bi-Directional Mode, with byte selectable read/write LOGIC LOGIC XDEC
ARRAY
capability of the memory array. The 24LC21 is available PAGE LATCHES
in a standard 8-pin PDIP and SOIC package in both
commercial and industrial temperature ranges. SDA SCL
YDEC

VCC SENSE AMP

VSS R/W CONTROL

DDC is a trademark of the Video Electronics StandarDs Association.

I2C is a trademark of Philips Corporation.

 1996 Microchip Technology Inc. DS21095F-page 1

This document was created with FrameMaker 4 0 4

24LC21
1.0 ELECTRICAL CHARACTERISTICS TABLE 1-1: PIN FUNCTION TABLE

1.1 Maximum Ratings* Name Function

VCC...................................................................................7.0V
VSS Ground
All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V SDA Serial Address/Data I/O
Storage temperature ..................................... -65˚C to +150˚C SCL Serial Clock (Bi-Directional Mode)
Ambient temp. with power applied ................ -65˚C to +125˚C
VCLK Serial Clock (Transmit-Only Mode)
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins ..................................................≥ 4 kV VCC +2.5V to 5.5V Power Supply
*Notice: Stresses above those listed under “Maximum ratings” NC No Connection
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-2: DC CHARACTERISTICS

VCC = +2.5V to 5.5V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I): Tamb = -40˚C to +85˚C
Parameter Symbol Min Max Units Conditions
SCL and SDA pins:
High level input voltage VIH .7 VCC — V
Low level input voltage VIL — .3 VCC V
Input levels on VCLK pin:
High level input voltage VIH 2.0 .8 V VCC ≥ 2.7V (Note 1)
Low level input voltage VIL — .2 VCC V VCC < 2.7V (Note 1)
Hysteresis of Schmitt trigger inputs VHYS .05 VCC — V (Note 1)
Low level output voltage VOL1 — .4 V IOL = 3 mA, VCC = 2.5V (Note 1)
Low level output voltage VOL2 — .6 V IOL = 6 mA, VCC = 2.5V
Input leakage current ILI -10 10 µA VIN = .1V to VCC
Output leakage current ILO -10 10 µA VOUT = .1V to VCC
Pin capacitance (all inputs/outputs) CIN, COUT — 10 pF VCC = 5.0V (Note1),
Tamb = 25°C, FCLK = 1 MHz
Operating current ICC Write — 3 mA VCC = 5.5V, SCL = 400 kHz
ICC Read — 1 mA
Standby current ICCS — 30 µA VCC = 3.0V, SDA = SCL = VCC
— 100 µA VCC = 5.5V, SDA = SCL = VCC
(Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: VLCK must be grounded.

DS21095F-page 2  1996 Microchip Technology Inc.

 24LC21
TABLE 1-3: AC CHARACTERISTICS

Vcc= 4.5 - 5.5V

Standard Mode
Parameter Symbol Fast Mode Units Remarks
Min Max Min Max
Clock frequency FCLK — 100 — 400 kHz
Clock high time THIGH 4000 — 600 — ns
Clock low time TLOW 4700 — 1300 — ns
SDA and SCL rise time TR — 1000 — 300 ns (Note 1)
SDA and SCL fall time TF — 300 — 300 ns (Note 1)
START condition hold time THD:STA 4000 — 600 — ns After this period the first clock
pulse is generated
START condition setup TSU:STA 4700 — 600 — ns Only relevant for repeated
time START condition
Data input hold time THD:DAT 0 — 0 — ns (Note 2)
Data input setup time TSU:DAT 250 — 100 — ns
STOP condition setup time TSU:STO 4000 — 600 — ns
Output valid from clock TAA — 3500 — 900 ns (Note 2)
Bus free time TBUF 4700 — 1300 — ns Time the bus must be free
before a new transmission
can start
Output fall time from VIH TOF — 250 20 + .1 250 ns (Note 1), CB ≤ 100 pF
min to VIL max CB
Input filter spike suppres- TSP — 50 — 50 ns (Note 3)
sion (SDA and SCL pins)
Write cycle time TWR — 10 — 10 ms Byte or Page mode
Transmit-Only Mode Parameters
Output valid from VCLK TVAA — 2000 — 1000 ns
VCLK high time TVHIGH 4000 — 600 — ns
VCLK low time TVLOW 4700 — 1300 — ns
Mode transition time TVHZ — 500 — 500 ns
Transmit-Only power up TVPU 0 — 0 — ns
time
Endurance — 10M — 10M — cycles 25°C, Vcc = 5.0V, Block Mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

 1996 Microchip Technology Inc. DS21095F-page 3

24LC21
2.0 FUNCTIONAL DESCRIPTION ninth, null bit (see Figure 2-1). The clock source for the
Transmit-Only Mode is provided on the VCLK pin, and
The 24LC21 operates in two modes, the Transmit-Only a data bit is output on the rising edge on this pin. The
Mode and the Bi-Directional Mode. There is a separate eight bits in each byte are transmitted most significant
two wire protocol to support each mode, each having a bit first. Each byte within the memory array will be out-
separate clock input and sharing a common data line put in sequence. When the last byte in the memory
(SDA). The device enters the Transmit-Only Mode upon array is transmitted, the output will wrap around to the
power-up. In this mode, the device transmits data bits first location and continue. The Bi-Directional Mode
on the SDA pin in response to a clock signal on the Clock (SCL) pin must be held high for the device to
VCLK pin. The device will remain in this mode until a remain in the Transmit-Only Mode.
valid high to low transition is placed on the SCL input.
When a valid transition on SCL is recognized, the 2.2 Initialization Procedure
device will switch into the Bi-Directional Mode. The only
way to switch the device back to the Transmit-Only After VCC has stabilized, the device will be in the Trans-
Mode is to remove power from the device. mit-Only Mode. Nine clock cycles on the VCLK pin must
be given to the device for it to perform internal synchro-
2.1 Transmit-Only Mode nization. During this period, the SDA pin will be in a high
impedance state. On the rising edge of the tenth clock
The device will power up in the Transmit-Only Mode. cycle, the device will output the first valid data bit which
This mode supports a unidirectional two wire protocol will be the most significant bit of a byte. The device will
for transmission of the contents of the memory array. power up at an indeterminate byte address. (See
This device requires that it be initialized prior to valid Figure 2-2).
data being sent in the Transmit-Only Mode (see Initial-
ization Procedure, below). In this mode, data is trans-
mitted on the SDA pin in 8 bit bytes, each followed by a

FIGURE 2-1: TRANSMIT ONLY MODE

SCL
TVAA TVAA

SDA NULL BIT

BIT 1 (LSB) BIT 1 (MSB) BIT 7

VCLK
TVHIGH TVLOW

FIGURE 2-2: DEVICE INITIALIZATION

VCC

SCL
TVAA TVAA

SDA HIGH IMPEDANCE FOR 9 CLOCK CYCLES BIT 8 BIT 7

TVPU

VCLK 1 2 8 9 10 11

DS21095F-page 4  1996 Microchip Technology Inc.

 24LC21
3.0 BI-DIRECTIONAL MODE 3.1 Bi-Directional Mode Bus
Characteristics
The 24LC21 can be switched into the Bi-Directional
Mode (see Figure 3-1) by applying a valid high to low The following bus protocol has been defined:
transition on the Bi-Directional Mode Clock (SCL).
When the device has been switched into the Bi-Direc- • Data transfer may be initiated only when the bus is
tional Mode, the VCLK input is disregarded, with the not busy.
exception that a logic high level is required to enable • During data transfer, the data line must remain
write capability. This mode supports a two wire bi-direc- stable whenever the clock line is HIGH. Changes
tional data transmission protocol. In this protocol, a in the data line while the clock line is HIGH will be
device that sends data on the bus is defined to be the interpreted as a START or STOP condition.
transmitter, and a device that receives data from the Accordingly, the following bus conditions have been
bus is defined to be the receiver. The bus must be con- defined (see Figure 3-2).
trolled by a master device that generates the Bi-Direc-
tional Mode Clock (SCL), controls access to the bus 3.1.1 BUS NOT BUSY (A)
and generates the START and STOP conditions, while
the 24LC21 acts as the slave. Both master and slave Both data and clock lines remain HIGH.
can operate as transmitter or receiver, but the master 3.1.2 START DATA TRANSFER (B)
device determines which mode is activated.
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

3.1.3 STOP DATA TRANSFER (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

FIGURE 3-1: MODE TRANSITION

Transmit Only Mode Bi-Directional Mode
SCL

TVHZ

SDA

VCLK

FIGURE 3-2: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

VHYS

SCL
THD:STA
TSU:STA TSU:STO

SDA

START STOP

 1996 Microchip Technology Inc. DS21095F-page 5

24LC21
3.1.4 DATA VALID (D) 3.1.5 ACKNOWLEDGE

The state of the data line represents valid data when, Each receiving device, when addressed, is obliged to
after a START condition, the data line is stable for the generate an acknowledge after the reception of each
duration of the HIGH period of the clock signal. byte. The master device must generate an extra clock
The data on the line must be changed during the LOW pulse which is associated with this acknowledge bit.
period of the clock signal. There is one clock pulse per Note: The 24LC21 does not generate any
bit of data. acknowledge bits if an internal program-
Each data transfer is initiated with a START condition ming cycle is in progress.
and terminated with a STOP condition. The number of The device that acknowledges has to pull down the
the data bytes transferred between the START and SDA line during the acknowledge clock pulse in such a
STOP conditions is determined by the master device way that the SDA line is stable LOW during the HIGH
and is theoretically unlimited, although only the last period of the acknowledge related clock pulse. Of
eight will be stored when doing a write operation. When course, setup and hold times must be taken into
an overwrite does occur it will replace data in a first in account. A master must signal an end of data to the
first out fashion. slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.

FIGURE 3-3: BUS TIMING START/STOP

VHYS

SCL
THD:STA
TSU:STA TSU:STO

SDA

START STOP

FIGURE 3-4: BUS TIMING DATA

TF TR
THIGH
TLOW

SCL
TSU:STA
THD:DAT TSU:DAT TSU:STO
THD:STA
SDA
TSP
IN

TAA TAA TBUF

THD:STA

SDA
OUT

DS21095F-page 6  1996 Microchip Technology Inc.

 24LC21
3.1.6 SLAVE ADDRESS 4.0 WRITE OPERATION
After generating a START condition, the bus master 4.1 Byte Write
transmits the slave address consisting of a 7-bit device
code (1010) for the 24LC21, followed by three don’t Following the start signal from the master, the slave
care bits. address (4 bits), the don’t care bits (3 bits) and the R/W
The eighth bit of slave address determines if the master bit which is a logic low is placed onto the bus by the
device wants to read or write to the 24LC21 (see master transmitter. This indicates to the addressed
Figure 3-5). slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
The 24LC21 monitors the bus for its corresponding ninth clock cycle. Therefore, the next byte transmitted
slave address all the time. It generates an acknowledge by the master is the word address and will be written
bit if the slave address was true and it is not in a pro- into the address pointer of the 24LC21. After receiving
gramming mode. another acknowledge signal from the 24LC21 the mas-
Operation Control Code Chip Select R/W ter device will transmit the data word to be written into
the addressed memory location. The 24LC21 acknowl-
Read 1010 XXX 1 edges again and the master generates a stop condi-
Write 1010 XXX 0 tion. This initiates the internal write cycle, and during
this time the 24LC21 will not generate acknowledge
FIGURE 3-5: CONTROL BYTE signals (see Figure 4-1).
ALLOCATION It is required that VCLK be held at a logic high level in
order to program the device. This applies to byte write
START READ/WRITE and page write operation. Note that VCLK can go low
while the device is in its self-timed program operation
SLAVE ADDRESS
and not affect programming.
R/W A
4.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC21 in the same way as
1 0 1 0 X X X in a byte write. But instead of generating a stop condi-
tion the master transmits up to eight data bytes to the
24LC21 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains con-
stant. If the master should transmit more than eight
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (see Figure 4-2).
It is required that VCLK be held at a logic high level in
order to program the device. This applies to byte write
and page write operation. Note that VCLK can go low
while the device is in its self-timed program operation
and not affect programming.

FIGURE 4-1: BYTE WRITE

S S
T CONTROL WORD T
BUS ACTIVITY A
MASTER BYTE ADDRESS DATA O
R P
T

SDA LINE S P

A A A
BUS ACTIVITY C C C
K K K
VCLK

 1996 Microchip Technology Inc. DS21095F-page 7

24LC21
FIGURE 4-2: PAGE WRITE
S
T S
BUS ACTIVITY A T
MASTER R CONTROL WORD O
T BYTE ADDRESS (n) DATA n DATA n + 1 DATA n + 15 P

SDA LINE S P
A A A A A
BUS ACTIVITY C C C C C
K K K K K

VCLK

5.0 ACKNOWLEDGE POLLING FIGURE 5-1: ACKNOWLEDGE POLLING

FLOW
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus Send
throughput). Once the stop condition for a write com- Write Command
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send- Send Stop
ing a start condition followed by the control byte for a Condition to
write command (R/W = 0). If the device is still busy with Initiate Write Cycle
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or Send Start
write command. See Figure 5-1 for the flow diagram.

Send Control Byte

with R/W = 0

Did Device NO
Acknowledge
(ACK = 0)?
YES

Next
Operation

6.0 WRITE PROTECTION

When using the 24LC21 in the Bi-Directional Mode, the
VCLK pin operates as the write protect control pin. Set-
ting VCLK high allows normal write operations, while
setting VCLK low prevents writing to any location in the
array. Connecting the VCLK pin to VSS would allow the
24LC21 to operate as a serial ROM, although this con-
figuration would prevent using the device in the Trans-
mit-Only Mode.

DS21095F-page 8  1996 Microchip Technology Inc.

 24LC21
7.0 READ OPERATION set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24LC21 will then
Read operations are initiated in the same way as write issue an acknowledge and transmits the eight bit data
operations with the exception that the R/W bit of the word. The master will not acknowledge the transfer but
slave address is set to one. There are three basic types does generate a stop condition and the 24LC21 discon-
of read operations: current address read, random read tinues transmission (Figure 7-2).
and sequential read.
7.3 Sequential Read
7.1 Current Address Read
Sequential reads are initiated in the same way as a ran-
The 24LC21 contains an address counter that main- dom read except that after the 24LC21 transmits the
tains the address of the last word accessed, internally first data byte, the master issues an acknowledge as
incremented by one. Therefore, if the previous access opposed to a stop condition in a random read. This
(either a read or write operation) was to address n, the directs the 24LC21 to transmit the next sequentially
next current address read operation would access data addressed 8 bit word (see Figure 7-3).
from address n + 1. Upon receipt of the slave address
with R/W bit set to one, the 24LC21 issues an acknowl- To provide sequential reads the 24LC21 contains an
edge and transmits the eight bit data word. The master internal address pointer which is incremented by one at
will not acknowledge the transfer but does generate a the completion of each operation. This address pointer
stop condition and the 24LC21 discontinues transmis- allows the entire memory contents to be serially read
sion (Figure 7-1). during one operation.

7.2 Random Read 7.4 Noise Protection

Random read operations allow the master to access The 24LC21 employs a VCC threshold detector circuit
any memory location in a random manner. To perform which disables the internal erase/write logic if the VCC
this type of read operation, first the word address must is below 1.5 volts at nominal conditions.
be set. This is done by sending the word address to the The SCL and SDA inputs have Schmitt trigger and filter
24LC21 as part of a write operation. After the word circuits which suppress noise spikes to assure proper
address is sent, the master generates a start condition device operation even on a noisy bus.
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is

FIGURE 7-1: CURRENT ADDRESS READ

S
BUS ACTIVITY T S
A CONTROL T
MASTER R BYTE DATA n O
T P

SDA LINE
S P

BUS ACTIVITY A N
C O
K
A
C
K

FIGURE 7-2: RANDOM READ

S S
T T S
BUS ACTIVITY A CONTROL WORD A CONTROL T
MASTER R BYTE ADDRESS (n) R BYTE DATA n O
T T P

SDA LINE S S P
A A A N
BUS ACTIVITY C C C O
K K K
A
C
K

 1996 Microchip Technology Inc. DS21095F-page 9

24LC21
FIGURE 7-3: SEQUENTIAL READ

S
T
BUS ACTIVITY CONTROL O
MASTER BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X P

SDA LINE P
A A A A N
BUS ACTIVITY C C C C O
K K K K
A
C
K

8.0 PIN DESCRIPTIONS

8.1 SDA
This pin is used to transfer addresses and data into and
out of the device, when the device is in the Bi-Direc-
tional Mode. In the Transmit-Only Mode, which only
allows data to be read from the device, data is also
transferred on the SDA pin. This pin is an open drain
terminal, therefore the SDA bus requires a pullup resis-
tor to VCC (typical 10KΩ for 100 kHz, 1KΩ for 400 kHz).
For normal data transfer in the Bi-Directional Mode,
SDA is allowed to change only during SCL low.
Changes during SCL high are reserved for indicating
the START and STOP conditions.

8.2 SCL
This pin is the clock input for the Bi-Directional Mode,
and is used to synchronize data transfer to and from the
device. It is also used as the signaling input to switch
the device from the Transmit Only Mode to the Bi-Direc-
tional Mode. It must remain high for the chip to continue
operation in the Transmit Only Mode.

8.3 VCLK
This pin is the clock input for the Transmit Only Mode.
In the Transmit Only Mode, each bit is clocked out on
the rising edge of this signal. In the Bi-Directional
Mode, a high logic level is required on this pin to enable
write capability.

DS21095F-page 10  1996 Microchip Technology Inc.

24LC21
24LC21 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

24LC21 - /P
Package: P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
Temperature Blank = 0˚C to +70˚C
Range: I = -40˚C to +85˚C

Device: 24LC21 Dual Mode I2C Serial EEPROM

24LC21T Dual Mode I2C Serial EEPROM (Tape and Reel)

 1996 Microchip Technology Inc. DS21095F-page 11

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All rights reserved.  1996, Microchip Technology Incorporated, USA. 9/96

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DS21095F-page 12  1996 Microchip Technology Inc.