CMOS Mixed-Signal Circuit Design

Complemented with practical examples and discussions, CMOS Mixed-Signal
Circuit Design, Second Edition is an ideal textbook for graduate students in

mixed-signal circuit design courses. It is also an equally valuable reference for
professionals who want to improve their skills in this area.
R. JACOB (JAKE) BAKER, PHD, is an engineer, educator, and inventor.

He has more than twenty years of engineering experience and holds over
200 granted or pending patents in integrated circuit design. Jake is the
author of several circuit design books. For a detailed biography, please visit:
http://CMOSedu.com/jbakerljbaker.htm.
• IEEE
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a.Malik
S. Nahavandi
Mixed-Signal Circuit Design
M. S. Newman
W. Reeve
Second Edition
Information Services (SIS)
~ Editor
Editor
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rs
Science and Technology R. Jacob Baker

'tate University
Issociales
~ofMacau
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IEEE Press Series on Microelectronic Systems

Stuart K. Tewksbury and Joe E. Brewer, Series Editors
+IEEE
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WILEY
I A JOHN WILEY & SONS, INC., PUBLICATION
I
Brief Contents
Chapter 1 Signals, Filters, and Tools 1
Chapter 2 Sampling and Aliasing 27
Chapter 3 Analog Filters 73
Chapter 4 Digital Filters 119
Chapter 5 Data Converter SNR 163
Chapter 6 Data Converter Design Basics 203
Chapter 7 Noise-Shaping Data Converters 233
Chapter 8 Bandpass Data Converters 285
Chapter 9 A High-Speed Data Converter 301
vi
Contents
Preface xv
Chapter 1 Signals, Filters, and Tools 1

1.1 Sinusoidal Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 The Pendulum Analogy 1
Describing Amplitude in the x-y Plane 3
In-Phase and Quadrature Signals 4
1.1.2 The Complex (z-) Plane 6
1.2 Comb Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2.1 The Digital Comb Filter 11
1.2.2 The Digital Differentiator 14
1.2.3 An Intuitive Discussion of the z-Plane 15
1.2.4 Comb Filters with Multiple Delay Elements 17
1.2.5 The Digital Integrator 19
The Delaying Integrator 20
An Important Note 21
1.3 Representing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3.1 Exponential Fourier Series 22
1.3.2 Fourier Transform 23
Dirac Delta Function (Unit Impulse Response) 23
vii
viii Contents
Chapter 2 Sampling and Aliasing 27

2.1 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.1.1 Impulse Sampling 28
A Note Concerning the AAF and the RCF 30
Time Domain Description of Reconstruction 31
2.1.2 Decimation 33
2.1.3 The Sample-and-Hold (S/H) 35
S/H Spectral Response 35
The Reconstruction Filter (RCF) 39
Circuit Concerns for Implementing the S/H 39
An Example 40
2.1.4 The Track-and-Hold (T/H) 41
2.1.5 Interpolation 43
Zero Padding 44
Hold Register 46
Linear Interpolation 49
2.1.6 K-Path Sampling 50
Switched-Capacitor Circuits 51
Non-Overlapping Clock Generation 53
2.2 Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.2.1 Implementing the S/H 54
Finite Op-Amp Gain-Bandwidth Product 55
Autozeroing 57
Correlated Double Sampling (CDS) 59
Selecting Capacitor Sizes 61
2.2.2 The S/H with Gain 61
Implementing Subtraction in the S/H 63
A Single-Ended to Differential Output S/H 65
2.2.3 The Discrete Analog Integrator (DAI) 66
A Note Concerning Block Diagrams 68
Fully-Differential DAI 69
DAI Noise Performance 70
Chapter 3 Analog Filters 73
3.1 Integrator Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.1.1 Lowpass Filters 73
3.1.2 Active-RC Integrators 75
Contents ix
Effects of Finite Op-Amp Gain Bandwidth Product, fun 78

Active-RC SNR 82
3.1.3 MOSFET-C Integrators 83
Why Use an Active Circuit (an Op-Amp)? 85
3.1.4 gm-C (Transconductor-C) Integrators 86
Common-Mode Feedback Considerations 88
A High-Frequency Transconductor 89
3.1.5 Discrete-Time Integrators 90
Exact Frequency Response of an Ideal Discrete-Time 94
Filter
3.2 Filtering Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.2.1 The Bilinear Transfer Function 95
Active-RC Implementation 97
Transconductor-C Implementation 97
Switched-Capacitor Implementation 98
3.2.2 The Biquadratic Transfer Function 99
Active-RC Implementation 101
Switched-Capacitor Implementation 106
High Q 107
Q Peaking and Instability 112
Transconductor-C Implementation 114
Chapter 4 Digital Filters 119
4.1 SPICE Models for DACs and ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.1.1 The Ideal DAC 119
SPICE Modeling the Ideal DAC 120
4.1.2 The Ideal ADC 121
4.1.3 Number Representation 123
Increasing Word Size (Extending the Sign-Bit) 124
Adding Numbers and Overflow 125
Subtracting Numbers in Two's Complement Format 126
4.2 Sinc-Shaped Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.2.1 The Counter 126
Aliasing 127
The Accumulate-and-Dump 129
4.2.2 Lowpass Sinc Filters 129
Averaging without Decimation: A Review 132
x Contents
Cascading Sinc Filters 132

Finite and Infinite Impulse Response Filters 133
4.2.3 Bandpass and Highpass Sinc Filters 134
Canceling Zeroes to Create Highpass and Bandpass 134
Filters
Frequency Sampling Filters 138
4.2.4 Interpolation using Sinc Filters 139
Additional Control 142
Cascade of Integrators and Combs 142
4.2.5 Decimation using Sinc Filters 143
4.3 Filtering Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
4.3.1 FIR Filters 145
4.3.2 Stability and Overflow 146
Overflow 147
4.3.3 The Bilinear Transfer Function 148
The Canonic Form (or Standard Form) of a Digital 151
Filter
General Canonic Form of a Recursive Filter 154
4.3.4 The Biquadratic Transfer Function 155
Comparing Biquads to Sinc-Shaped Filters 157
A Comment Concerning Multiplications 158
Chapter 5 Data Converter SNR 163
5.1 Quantization Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5.1.1 Viewing the Quantization Noise Spectrum Using 164
Simulations
Bennett's Criteria 165
RMS Quantization Noise Voltage 166
Treating Quantization Noise as a Random Variable 168
5.1.2 Quantization Noise Voltage Spectral Density 169
Calculating Quantization Noise from a SPICE 171
Spectrum
Power Spectral Density 172
5.2 Signal-to-Noise Ratio (SNR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Effective Number of Bits 173
Coherent Sampling 175
Signal-to-Noise Plus Distortion Ratio 176
Spurious Free Dynamic Range 177
Contents xi
Dynamic Range 177

Specifying SNR and SNDR 178
5.2.1 Clock Jitter 178
Using Oversampling to Reduce Sampling Clock Jitter 181
Stability Requirements
A Practical Note 182
5.2.2 A Tool: The Spectral Density 182
The Spectral Density of Deterministic Signals: An 183
Overview
The Spectral Density of Random Signals: An Overview 185
Specifying Phase Noise from Measured Data 189
5.3 Improving SNR using Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
5.3.1 Using Averaging to Improve SNR 192
Ideal Signal-to-Noise Ratio 194
5.3.2 Linearity Requirements 194
5.3.3 Adding a Noise Dither 195
5.3.4 Jitter 198
5.3.5 Anti-Aliasing Filter 198
5.4 Using Feedback to Improve SNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Chapter 6 Data Converter Design Basics 203
The One-Bit ADC and DAC 204
6.1 Passive Noise-Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
6.1.1 Signal-to-Noise Ratio 208
6.1.2 Decimating and Filtering the Modulator's Output 209
SNR Calculation using a Sinc Filter 211
6.1.3 Offset, Matching, and Linearity 212
Resistor Mismatch 213
The Feedback DAC 213
DAC Offset 214
Linearity of the First-Order Modulator 214
Dead Zones 215
6.2 Improving SNR and Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
6.2.1 Second-Order Passive Noise-Shaping 216
6.2.2 Passive Noise-Shaping Using Switched-Capacitors 218
6.2.3 Increasing SNR using K-Paths 220
Revisiting Switched-Capacitor Implementations 224
xii Contents
Effects of the Added Amplifier on Linearity 224

6.2.4 Improving Linearity Using an Active Circuit 225
Second-Order Noise-Shaping 227
Signal-to-Noise Ratio 229
Discussion 230
7.1 First-Order Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
A Digital First-Order NS Demodulator 235
7.1.1 Modulation Noise in First-Order NS Modulators 236
7.1.2 RMS Quantization Noise in a First-Order Modulator 237
7.1.3 Decimating and Filtering the Output of a NS 239
Modulator
7.1.4 Pattern Noise from DC Inputs (Limit Cycle 241
Oscillations)
7.1.5 Integrator and Forward Modulator Gain 243
7.1.6 Comparator Gain, Offset, Noise, and Hysteresis 246
7.1.7 Op-Amp Gain (Integrator Leakage) 247
7.1.8 Op-Amp Settling Time 248
7.1.9 Op-Amp Offset 250
7.1.10 Op-Amp Input-Referred Noise 250
7.1.11 Practical Implementation of the First-Order NS 251
Modulator
7.2 Second-Order Noise-Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
7.2.1 Second-Order Modulator Topology 253
7.2.2 Integrator Gain 257
Implementing Feedback Gains in the DAI 260
Using Two Delaying Integrators to Implement the 263
Second-Order Modulator
7.2.3 Selecting Modulator (Integrator) Gains 264
7.3 Noise-Shaping Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
7.3.1 Higher-Order Modulators 265
M th-Order Modulator Topology 265
7.3.2 Filtering the Output of an M th-Order NS Modulator 266
7.3.3 Implementing Higher-Order, Single-Stage 267
Modulators
7.3.4 Multi-Bit Modulators 269
Simulating a Multibit NS Modulator Using SPICE 269
7.3.5 Error Feedback 271
Contents xiii
Implementation Concerns 274

7.3.6 Cascaded Modulators 275
Second-Order (1-1) Modulators 275
Third-Order (1-1-1) Modulators 277
Third-Order (2-1) Modulators 277
Implementing the Additional Summing Input 279
Chapter 8 Bandpass Data Converters 285
8.1 Continuous-Time Bandpass Noise-Shaping . . . . . . . . . . . . . . . . . . . . 287
8.1.1 Passive-Component Bandpass Modulators 287
8.1.2 Active-Component Bandpass Modulators 289
Signal-to-Noise Ratio 290
8.1.3 Modulators for Conversion at Radio Frequencies 291
8.2 Switched-Capacitor Bandpass Noise-Shaping . . . . . . . . . . . . . . . . . 292
8.2.1 Switched-Capacitor Resonators 292
8.2.2 Second-Order Modulators 294
8.2.3 Fourth-Order Modulators 296
A Common Error 297
A Comment about 1/f Noise 297
8.2.4 Digital I/Q Extraction to Baseband 297
Chapter 9 A High-Speed Data Converter 301
9.1 The Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
9.1.1 Clock Signals 301
Path Settling Time 302
9.1.2 Implementation 303
9.1.3 Filtering 306
Examples 307
Direction 312
9.1.4 Discussion 312
9.1.5 Understanding the Clock Signals 315
9.2 Practical Implemenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
9.2.1 Generating the Clock Signals 316
9.2.2 The Components 318
The Switched-Capacitors 318
The Amplifier 318
The Clocked Comparator 319
9.2.3 The ADC 320
xiv Contents
9.3 Conclusion 322

Index 325
_ _ _ _ _ _ _...tlIi -U--------------_.
Contents
322
325
Preface
Designs that combine analog circuits with digital signal processing, DSP, are called
mixed-signal designs, MSDs. Designs that use both digital and analog circuits but no
DSP, like a 555 timer or a pipeline ADC, are not, by this definition, MSDs. These
mixed-mode or mixed analog/digital circuits aren't as robust as circuits designed using
MSD techniques because they require precise components and often calibrations or
tuning. The use of DSP in a mixed-signal circuit relaxes the requirements placed on the
analog components (important) by overcoming the shortcomings, like low transistor gain
and poor matching, found in nanometer CMOS.
This book provides a tutorial introduction to MSD techniques. The content is
suitable for use in a senior/graduate electrical engineering course or as a reference for a
working engineer doing MSD. The assumed background of the reader is a course in
signals/systems, and courses in digital and analog integrated circuit design in CMOS
technology.
Chapter I covers basic signals, filters, and tools. The reader may be inclined to
skip this material; however, the author would recommend against it unless the reader can:
1) Give an example of an imaginary signal (answer using words and without math or
equations). 2) Explain why imaginary numbers are used. 3) Explain why I/Q signals are
used. 4) Describe the differences between delaying and non-delaying integrators. While
we could keep listing questions, even the most seasoned systems person will likely
benefit from reading and thinking about the material in Ch. 1. Don't skip it! Make an
attempt to understand what is going on in the discussions and not just to understand the
math. Once the reader feels they have mastered this material they should try to provide
physical metaphors to describe a concept or equation (for example, use a cup, water, and
a bucket to describe Eq. [1.56]). Remember that math is easy. Understanding what's going
on is tough.
XVI Preface
Simulation examples are used throughout the book to provide an additional

avenue towards understanding the book's content. In Ch. 1, for example, simulations are
available at CMOSedu.com that aren't present or discussed in the book. An important
part of learning is modifying a simulation, thinking about what should happen and why,
then running the simulation to verify your understanding.
Chapter 2 covers sampling and aliasing. These are key topics because sampling is
required in any MSD system. Further, decimation (down-sampling) and interpolation
(up-sampling) are commonly used in digital signal processing and thus MSD. In addition,
circuits used for sampling are presented. Chapters 3 and 4 cover analog and digital
filtering. The focus is on practical and useful circuits that can be used in MSD. Chapter 5
covers noise and signal-to-noise ratio. The remaining chapters in the book describe the
design of data converters using MSD techniques and the associated trade-offs.
Signals, F
An attempt has been made to present circuits and information with the goal of
answering the reader's questions and provoking thought. Hopefully, this will lead the
reader towards creative solutions to their circuit design problems. For example, the
delta-sigma data converters presented in Ch. 7 use an active integrator. Why? Why can't a
passive integrator be used? Chapter 6 develops data converters using passive elements. Mixed-signal circuit desig
Both the benefits and problems associated with passive topologies are discussed leading processing, and circuit desig
up to answering why an active integrator is used in most delta-sigma data converters. and the mathematical tools.
Finally, one of the main (perceived) limitations of MSD techniques is speed. it to ensure a good foundati
Often, in a MSD, time is traded-off for precision. The results are circuits that are precise, reference for the mathematic
but slow. The pipeline ADC mentioned earlier is an example of a fast circuit that needs to
be precise. Since the pipeline ADC doesn't use MSD techniques, its design can be more 1.1 Sinusoidal Signa
than challenging, especially for a production-worthy design, requiring special layout
Let's take a fundamental 100
attention or extensive calibrations. The last chapter in the book, Ch. 9, presents a
formulas) of representing a
high-speed topology, the K-Delta-1-Sigma topology, that uses MSD techniques that may
function. Naturally occurrin
prove useful in ultimately replacing the pipeline ADC in nanometer CMOS technology
through empirical measure
I nodes. The design procedures used in this topology also provide a good summary of the
r dividing the circumference a
I MSD techniques presented in the book.
I
I Acknowledgments
I
I I would like to thank and acknowledge the reviewers, students, colleagues, and friends The goal of this section is t.
I
I
that have helped to make this book a possibility: Jenn Ambrose, Hemanth Ande, Jeanne understanding of what's goin
I Audino, Kyri Baker, Mahesh Balasubramanian, Amine Bermak, Bertan Bakkaloglu, Joe
I
Brewer, Prashanth Busa, Kris Campbell, Mike Engelhardt, Gilda Garret6n, Shantanu 1.1.1 The Pendulum Ana
I
I Gupta, Bob Hay, Bahar Jalali-Farahani, Kaijun Li, Richard G. Lyons, Pui-In Mak, Consider the (ideal, that is, ](
I Brittany Rotert, Steven Rubin, Vishal Saxena, Stu Tewksbury, Donna Welch, Thad pendulum is moving back ar
I
Welch, and Aruna Vadla.
pendulum leaves Point 1 it s
and finally reaching Point 3.
R. Jacob (Jake) Baker to make this complete journe
period, T. In Fig. 1.1 b we ph
record the position to define
specific time
Positic
This signal, we should all rer
with a frequency.j, of liT.
Preface
e book to provide an additional

.h. 1, for example, simulations are
cussed in the book. An important
lout what should happen and why,
Chapter
1
.g.
are key topics because sampling is
down-sampling) and interpolation
cessing and thus MSD. In addition,
3 and 4 cover analog and digital
flat can be used in MSD. Chapter 5
chapters in the book describe the
Ie associated trade-offs.
Signals, Filters, and Tools
and information with the goal of
ight. Hopefully, this will lead the
.sign problems. For example, the
ictive integrator. Why? Why can't a
converters using passive elements. Mixed-signal circuit design requires a fundamental knowledge of signals, signal
Ie topologies are discussed leading processing, and circuit design. In this chapter we provide an overview of signals, filtering,
st delta-sigma data converters. and the mathematical tools. The chapter may be a review for the reader; however, we use
ons of MSD techniques is speed. it to ensure a good foundation to build on in the coming chapters and to provide a quick
results are circuits that are precise, reference for the mathematical formulas we'll use throughout the book.
ample of a fast circuit that needs to
techniques, its design can be more 1.1 Sinusoidal Signals
( design, requiring special layout
Let's take a fundamental look at the sinewave. While there are many ways (equations and
. in the book, Ch. 9, presents a
formulas) of representing a sinewave, we must remember it is an empirically determined
flat uses MSD techniques that may
function. Naturally occurring signals, shapes, or constants are determined or described
= in nanometer CMOS technology
through empirical measurements or observations. For example, rt is determined by
so provide a good summary of the
dividing the circumference of a circle by its diameter
circumference
rr= (1.1)
diameter
, students, colleagues, and friends The goal of this section is to provide intuitive discussions that will help create a deeper
Ambrose, Hemanth Ande, Jeanne
understanding of what's going on in a circuit or system.
e Bermak, Bertan Bakkaloglu, Joe
-lhardt, Gilda Garreton, Shantanu 1.1.1 The Pendulum Analogy
Richard G. Lyons, Pui-In Mak, Consider the (ideal, that is, lossless) moving pendulum seen in Fig. 1.1a. In this figure the
Tewksbury, Donna Welch, Thad pendulum is moving back and forth between Points I and 3 repeatedly over time. As the
pendulum leaves Point I it starts out slow, gaining maximum speed as it passes Point 2,
and finally reaching Point 3. At Point 3 it stops and reverses direction. The time it takes
R. Jacob (Jake) Baker to make this complete journey back to the starting point, Point I in this discussion, is the
period, T. In Fig. LIb we plot the movement of the pendulum along the arched path. We
record the position to define a function, j(t), that indicates the pendulum's position at a
specific time
Position =j(t) =j(t + nT), where n is an integer ( 1.2)
This signal, we should all recognize, is a sinusoid or sinewave which repeats its position
with a frequency.j, of liT.
2 CMOS Mixed-Signal Circuit Design Chapter 1 Signals, Filters,
limitations when represei

example, what is the ami
pendulum along the arche
let's write, assuming we ar,
Point I. "~ Point 3
Point 2 ~pendulum This function, the sine fun

of this function is the angl.
(a) Ideal (never stops or deviates from
same path) swinging pendulum in motion. corresponds to the functio
The time it takes to swing from Point I Point 3 to a value of + 1, ai
to Point 3 and back to Point I is the period T. of the sine function in ]
Position (along the arc) = jet) measured data (e.g., plottir
Describing Amplitude in th
(
Point 3
Examine the sinewave in I
actual distance the penduh
Point__---2-f------~----_1f_-----'~--.---_+----~ (and Point vi), as a zero ler
t, time
at this point in time). As \
Point 1_
45" ~Oo
(b) Movement of pendulum along the arc in (a) over time. 2
+1
Figure 1.1 Physical interpretation of a sinewave. II
4
Next, consider the circle seen in Fig. 1.2. One complete rotation around this circle
(360 degrees or 2n) is analogous to one complete movement (swing) of our pendulum. 'v
We started plotting the pendulum's position at Point 2 in Fig. 1.1b (Point 2, t = 0, in Fig. 31t
2
1.2). After TI4 we reach Point 3 in Fig. 1.1 b. This corresponds to a 90 degree, or n12,
I 27(
I movement in our circle. After another TI4 seconds we pass back through Point 2. In the y
I circle we've moved 180 degrees. This continues with each swing of the pendulum
I t = TI8
-I- corresponding to a complete revolution around the circle. Note that we do have some
I
I
.1
I
I
t = T14, T + T14, ...
-. Point 3
Length ofO_7C
angle of 45 de;
(c) Point ii
y
-+:'
-I
-.
I
Point 2
I
I
/
-I- t = Tl2, T + Tl2, ... Length of 0 an
t=O, T, 2T, ...
I
I
I angle of 180 d,
I
I
t = 3T14, T + 3TI4, ...
»> Point I (e) Point iv
Figure 1.3 A vector

Figure 1.2 Using a circle to describe the movement of the pendulum in Fig. 1.1. is used tc
Mixed-Signal Circuit Design Chapter I Signals, Filters, and Tools 3
limitations when representing the movement of the pendulum with this circle. For
example, what is the amplitude of the sinewave (what is the relative position of the
pendulum along the arched path)? We'll address these concerns in a moment. For now
let's write, assuming we are using radian angular units,
t3 Position = sin (211' t) = sin(211/o • t) (1.3)
------- Pendulum This function, the sine function, tells us our relative position along the arc (the argument
of this function is the angle which relates to the position on the circle in Fig. 1.2). Point 2
ill
lmo!ion. corresponds to the function having a value of 0 (and times, t = 0, T/2, T, 3T/2, 2T, ... ),
oint 1 Point 3 to a value of + I, and Point 1 corresponds to -1. Finally, remember that the values
he period T. of the sine function in Fig. I.l.b, and Eq. (1.3), are determined empirically from
measured data (e.g., plotting the pendulum's position along the arched path against time).
Describing Amplitude in the x-y Plane
Examine the sinewave in Fig. 1.3a. For the moment we won't concern ourselves with the
actual distance the pendulum swings. In Fig. 1.3b we represent the sinewave, at Point i
(and Point vi), as a zero length vector along the x-axis (the amplitude of the sinewave is 0
t, time
at this point in time). As we move towards Point ii in Fig. 1.3a the length of the vector
4Y ~Oo (a) Portion of the sinewave

. (a) over time. y
2 from Fig. 1.lb.
+1 '.. - -180°
sinewave. 'Ii :111 t= 0
---~--~x
,lete rotation around this circle time
ent (swing) of our pendulum.
ig. l.lb (Point 2, t = 0, in Fig.
~
Length of 0 and angle of 0
:l3. 0 or 211
ponds to a 90 degree, or rrJ2, 2
0
0° or 360° (b) Point i
270
s back through Point 2. In the y y
~ach swing of the pendulum
t= Tl8 t= TI4
. Note that we do have some
-----¥'---"~~x ----+----"~~x
Length of 0.707 and Length of 1 and

angle of 45 degrees angle of 90 degrees
(c) Point ii (d) Point iii
ime y
y
t= Tl2 t = 3TI4
int 2
-----«---~ x ----i----~ X
~ Length of 0 and Length of 1 and

t=O, T, 2T, ... angle of270 degrees
angle of 180 degrees
(e) Point iv (f) Point v
Figure 1.3 A vector swinging around the x-y plane changing both length and angle
is used to represent a sinewave.
the pendulum in Fig. 1.1.
4 CMOS Mixed-Signal Circuit Design Chapter I Signals, Filters, a
---_ - _ . _ - - -
..
increases (here indicating an increase in both the x and y directions), Fig. 1.3c. At T!4 we
are at Point iii in Fig. 1.3a. As seen in Fig. 1.3d the length of the vector is 1 and the angle
The resulting signal, whe
is 90 degrees. Continuing on towards TI2 (Point iv) in Fig. 1.3a the vector is shrinking
once again finally reaching a length of 0 and an angle of 180 degrees, Fig. 1.3e. In Fig. (sinewave) with a length (p
1.3f, Point v, the length is I and the angle is 270 degrees. The key point here is that a in a circle with a frequency
sinewave is represented in the x-y plane by a vector that is changing length and rotating
around in a circle. Knowing this we can simply represent the sinewave by its peak value
and the associated angle between the x-axis and the vector as indicated in Fig. 1.3. For
example, as seen in Fig. 1.3d, the peak value of the sinewave occurs when the angle is 90 where we define the magnit
degrees (TI4) so we could write
sin2n/o ' t ~ lL90° ~x O,y= 1 (104)
knowing the vector representing the sinewave is actually rotating around in the x-y plane (a) Shifti
with time (and a frequency J;, ). Note that we could plot the sinewave more accurately by Fig. 1
adding a third axis, time (the z-axis), and showing the corresponding, corkscrew looking,
3-dimensional plot.
In-Phase and Quadrature Signals
Consider moving the sinusoid in Fig. 1.3a a quarter of a cycle (90 degrees, rrJ2, or a
delay, tdela )" of T14) earlier in time, Fig. lAa. We write, for this time-shifted signal,
. (2n
sm . (360
T· t +2n ') =sm T' ( 1+'4T))' =sm
T' l + 90) =sm. (2n . (2.njo'I+2
r n) (1.5)
As the reader probably already knows, this signal function is called cosinusoidal or
simply a cosine signal and is described using Figure 1.4 Shil
sin (2n/0' t+ ~ I cos (2n/o . t) (1.6) Before going too mu

2) signals? The answer is that
We can say that the cosine signal in Fig. lAa lead~ the sine signal in Fig. l.3a by a phase time by a quarter cycle, ~
shift, 0, of 90 degrees (= TI4 nI2). We could also say that the sine signal lags the cosine respective amplitudes and ir
I signal by a phase shift of -90 degrees. Note that when we talk about phase shift it's we can't shift the sinewave
1
assumed that the frequencies of the two signals are equaL It doesn't make sense to talk unshifted sinewave since we
about the phase shift between two sinusoids at different frequencies. Finally note that the
phase shift is given by
I
tde/av
I 0= 2n . T = 2n/o . tdelay (1.7)
where tdelo/T X 100 % is the percentage the delay is of the period.

I
Figure lAb shows the x-y plane plot for a cosine signal. The peak value of the
I
cosine signal occurs when the angle is 0 degrees so we could write
cos 2n/o . t ~ 1LO° ~ x = I, y = 0 (1.8) Angle
to represent the signal and not show the rotating vector with time. Note that we can say
the cosine signal is in-phase (l) since we are representing it above with a zero degree Figure 1.5 Show
phase shift. We could also say that the sine signal, since it's shifted in time by a quarter
cycle, Eq. (1.4), has a quadrature (Q) phase shift. Note what happens, looking at the Notice that the sigr
vector representations of the sinusoids in Figs. 1.3b-f and lAb, if we create a signal by multiplying them together ar
adding a sine signal to a cosine signal or
)S Mixed-Signal Circuit Design Chapter I Signals, Filters, and Tools 5
lirections), Fig. 1.3c. At TI4 we S IQ(t) cos 21".:/0 . t + sin 211:fo . t (1.9)
of the vector is I and the angle
The resulting signal, when plotted in the x-y plane (Fig. 1.5), results in a vector
1.3a the vector is shrinking
. 180 degrees, Fig. 1.3e. In Fig. (sinewave) with a length (peak amplitude) of Jl2;li or J2
that simply rotates around
s. The key point here is that a in a circle with a frequency of liT (= 10 ). In more general terms, 1.6,
is changing length and rotating
the sinewave by its peak value SIQ(t) = AI' cos 211:fo . t+ AQ' sin2yifo . t = JA; +A~ . cos (21if" . t+tan- 1 Al (1.10)
.or as indicated in Fig. 1.3. For
ave occurs when the angle is 90 where we define the magnitude and phase as
I 2 2
ISIQ(t) I LSIQ(t) = JA I +AQ Ltan- I AI (1.11)
),y= 1 (104)
rotating around in the x-y plane (a) Shifting the sinewave in
1e sinewave more accurately by Fig. 1.3a earlier by Ti4. y
+1
responding, corkscrew looking, t= TI2
'. unit circle
time
\"
_~_.......:;;ii.:a·Ir'~.~ x
a cycle (90 degrees, n12, or a

. this time-shifted signal,
i
~ ii~""
'. . t 0
: sin (2rifo • t+ (1.5)

(b) Vectors representing the
sinewave in (a).
ction is called cosinusoidal or

Figure 1.4 Shifting the sinewave in Fig. L3a earlier in time by T/4.
, . t) (1.6) Before going too much further, we should ask why we would want to add I and Q
signals? The answer is that since the IIQ sinusoids are at the same frequency, shifted in
tle signal in Fig. 1.3a by a phase time by a quarter cycle, we can transmit them with, for example, changes in their
at the sine signal lags the cosine respective amplitudes and increase the information sent for a given bandwidth. Note that
1 we talk about phase shift it's we can't shift the sinewave seen in Fig. 1.3a by 180 degrees, or Tl2, and add it to an
11. It doesn't make sense to talk unshifted sinew ave since we would get no signal at all!
requencies. Finally note that the
y
(1.7)
)eriod.
e signal. The peak value of the
uld write
,y 0 (1.8) Angle is 45°
",ith time. Note that we can say

ng it above with a zero degree Figure 1.5 Showing how an I/Q signal can be represented in the x-y plane.
it's shifted in time by a quarter
e what happens, looking at the Notiee that the signals here are very simple. What happens when we start
d lAb, if we create a signal by mUltiplying them together and shifting them in time (changing the phase shift)? We need
6 CMOS Mixed-Signal Circuit Design Chapter 1 Signals, Filters, !
SIQ(t) AI' cos 2rc/o • t + A Q' sin 2rc/o . t or Euler's formula

,v
y-Iength is A Q I
where the cosine term is a
~ the complex number. Some
Angle is tan- 1 ~~
Further, with a little algebn
Figure 1.6 Again, showing how an I1Q signal can be represented in the x-y plane. The next thing we h
Plotting the real componen
to simplify the math!, To move towards this goal we'll develop the complex, or z-, plane we've always used. To plot
and the frequency-domain representation of signals. the factor ) in the compl,
shouldn't be included when
1.1.2 The Complex (z-) Plane
e, of the complex number, 1
Let's attempt (and fail using the x-y plane) to simplify our mathematical description of the
IQ signal given in Eq. (1.10). Recall the following Taylor series expansions
(1.12) z
6 z'
k
-+ - (U3)
6! 8!
7! + 9! - ... (1.14)
We can now write
cosk+sink k 2 k 3 J(4
l+k----+-+
_ k6 e 8 9
- +k- +k- ( 1.15) Figure 1.7 Th(
2! 3! 4! 5! 61 7! 8! 91 - ...
Comparing Eq. (LIS) to Eq. (1.12) we see that we are close to writing the Taylor's series
for e k • Why is this important? Perhaps the simplest explanation is that if we can represent Example 1.1
sinewaves using exponentiation, then mUltiplying two sinewaves, or shifting a sinewave In the complex plane, pi,
in time, can be performed using simple addition (of exponents). As seen in Fig. 1.8
I
I The question now is how do we modify things to ensure that all terms are added
Le f2 11/Q'/ = 2rc/o • t. The ~
so that Eq. (1.15) matches Eq. (1.l2)? Let's look at the first discrepancy (-1)· ~. The
only way to change the polarity of this term is take the square root of -1 and move it
I
I
inside with k 2 • As the reader may know instead of writing R
for all of these terms we
simplify things and write
}=R (1.16)
Numbers using} (or i) are called imaginary or complex numbers (the reason for using the
name imaginary will be explained in Ex. 1.1). Tmaginary numbers are invaluable for
time-shifting and scaling sinusoidal signals. We now rewrite Eq. (1.12) using) as
e j2n!o-t = cos 2rc/a . t +} . sin
.ks k6 .e
3!+4!+J5T 6!-J"7T+'" (1.17)
Figure
VlOS Mixed-Signal Circuit Design Chapter 1 Signals, Filters, and Tools 7
4/ . cos 2n/o . t + AQ . sin2rifo . t or Euler's formula

elk == cosk+}· sink ( 1.18)
where the cosine term is a real number and the sine term is the imaginary component of
the complex number. Sometimes the following notation is used
---')ox Re{ elk} == cos k and lm{ elk} == sink ( 1.19)

Further, with a little algebraic manipulation we can also write
elk + e-jk. ejk _ e -jk
cosk= 2 ,smk 2} ( 1.20)
I be represented in the x-y plane. The next thing we have to discuss is plotting complex numbers. Examine Fig. 1.7.
Plotting the real component, x, of a complex number, x + }y, follows the same methods
develop the complex, or z-, plane we've always used. To plot the imaginary component, we now use the y-axis. Note that
the factor } in the complex number simply indicates the imaginary component and
shouldn't be included when finding the magnitUde of the number, + y2 or the phase, jx2
8, of the complex number, tan-If.
)tir mathematical description of the
,or series expansions
im,y
+ ... (1.12) z - plane
z=x+}y y
(1.13)
(1.14) x
(1.15) Figure 1.7 The complex plane, plotting the imaginary number
close to writing the Taylor's series

lanation is that if we can represent Example 1.1
sinewaves, or shifting a sinewave In the complex plane, plot the signal e j21t!ot . Comment on the resulting plot.
onents). As seen in Fig. 1.8 the magnitude is le l2 "!o,! = 1 and phase shift is
to ensure that all terms are added Lei21r/ o'/ = 2n/o . t. The signal simply swings around and around in the complex
le first discrepancy (-1) . t. The
le square root of -1 and move it im,y
.ng H for all of these terms we 2
/cos 2 (2n/o . t) + sin (2rifo . t)
' ..r·.~e
______ == tan
-1 sin2rifo . t
,r
2d
= njo' t
(1.16) ~ cos2njo' t
-·---·---I"'-'-ri...·-:----~ Re, x
numbers (the reason for using the
nary numbers are invaluable for
\1
{rite Eq. (1.12) using} as \
el2"!.,, = cos 2n/o . t +} , sin 2n/o . t cos 2rifo . t
(1.17)
Figure 1.8 Plotting Euler's formula in the z-plane.
---------......------------------------------
8 CMOS Mixed-Signal Circuit Design Chapter 1 Signals, Filters, a
plane, on the unit circle, without changing amplitude (both the real and the towards this method of ch,
imaginary components oscillate back and forth between + 1 and -1). One complete Eq. (1.25) as vin(f) or sim
rotation takes lifo, or T seconds. We need to pause a moment and ask "If the discussed in the next sectiOl
magnitude of e j2nfo-t is a constant value of 1 isn't it a DC signal?" (answer: no) Returning to our cor
When a DC signal is represented in the x-y plane it doesn't rotate or change
amplitude like a sinewave does. (Well, since the frequency of a DC signal,/, is 0,
you could say it does rotate around the x-y plane just like a sinewave but since
or, using Euler's formula,
T == 00 (= llf) it never leaves the x-axis). What this, eJ2 rr!o'/, imaginary signal can
be used for is to introduce or represent delay (phase shift).
To understand this last statement in more detail let's write
A . cos 2rr./o . t Re{ A . e l2 "J" , } --1> AL.O (1.21 ) The magnitude response of 1
Suppose we want to delay this signal by td' We can represent a delay at a particular
frequency, 1" using
I':.:1 I J(1 + cos 21
or using
ej2rj~'(-/d) --1> 1L.2rc/o . (-td) --1> 1L.2rr.· -:.;: (1.22)
The delayed cosine signal can be written as

simply
A . cos 2rrf· (t td) == Re{A . e j2nfr • ej2nfHd )} == Re{A . e j2 ,,;fU-IJ)} (1.23)
To simplify the notation we can drop the real indication, Re {}. We could also describe the
delayed cosine signal in terms of angle notation as The phase response is given
AL.0.IL.2rr.'-:';:=A.IAO+2rr..-:.;:J AL.(-2rrfo·td) (1.24)
Again noting that when we use angle notation, the x-y plane, or the complex plane, we Notice at / == 1!(2td) the ph,
need to know the frequency,l" of the input signal since this information isn't present in
(1.29) and
these representations.
1.2 Comb Filters

1
the phase response is
1- A delay can be used to construct a simple, but very useful, filter called a comb filter, Fig.
1.9. Before deriving the equations that characterize this filter let's discuss notation. If our
input signal is a sinusoid we can represent it using
Note that the phase respo
1
1- Vinet) = A cos 2rcf- t (1.25) important for distortion less
response for a comb filter (a
If we were to keep the frequency fixed, / = 1" and vary time, which we've done up to this
be obvious).
point, the output signal of a circuit will simply repeat itself (at the same frequency as the
input signal). What's more useful is varying the input signal's frequency,!, and looking at
1- Example 1.2
the output of the circuit or system (how the amplitude and phase shift vary). To move
Figure 1.11 shows one
vinCi) . e-j2 rftd characteristic impedance
delay ~ (delay) is used for the de
1-1~ v,,,(J)
Vin(f)--3ft-)o.....
with a 50 ohm resistor
resistors don't load the
filter's characteristics (tra
Figure 1.9 A comb filter.

CMOS Mixed-Signal Circuit Design Chapter I Signals, Filters, and Tools 9
---_ _ - - - - - - - - - - - - - - - - - - - - -
..
lmplitude (both the real and the towards this method of characterization let's write the frequency domain description of
Jetween + 1 and -I). One complete Eq. (1.25) as vin(f) or simply v,n' Representing a signal in the frequency domain will be
pause a moment and ask "If the discussed in the next section.
m't it a DC signal?" (answer: no)
Returning to our comb filter in Fig. 1.9 we can write
plane it doesn't rotate or change
! frequency of a DC signal, f, is 0, (1.26)
me just like a sinewave but since
his, e j21t!o'/, imaginary signal can or, using Euler's formula,
.ase shift) .• Real Imaginary
r-.. ~ ~ ..--------.,
tail let's write l+cos2nj-(-ld) + j·sin2rrf·(-ld) ( 1.27)
(L21) The magnitude response of this filter is
can represent a delay at a particular I~:I I J(l +cos2rrf· (-td»2 + (sin2rrf· (-td»)2 b(l +cos2nj- td) ( 1.28)
or using
(1.22)
I+cosx 2COS2~ ( 1.29)
simply
(1.23)
(1.30)
jon, ReO. We could also describe the
The phase response is given by
(1.24) tan-l [ sin2rrf· (-td) ] (1.31)
1 +cos2nj- (-ld)
x-y plane, or the complex plane, we
since this information isn't present in
Notice at 1/(2td) the phase is tan- 1(010), which evaluates to ± 90 degrees. Using Eq,
(1.29) and
sin x 2 sin E. cos E ( 1.32)
2 2
the phase response is
useful, filter called a comb filter, Fig.
this filter let's discuss notation. If our LVVO.UI
In
= n(-td) I for J< l/(2t d) (1.33)
Note that the phase response is linear indicating constant delay through the filter,
if· t ( 1.25) important for distortionless filtering. Figure 1.10 shows the magnitude and frequency
lry time, which we've done up to this response for a comb filter (at this point the reason the filter is called a comb filter should
it itself (at the same frequency as the be obvious).
: signal's frequency,!, and looking at
ude and phase shift vary). To move Example 1.2
Figure 1.11 shows one possible implementation of a comb filter. A 50 Q
characteristic impedance co-ax transmission line with an electrical length of 5 ns
(delay) is used for the delay element (note how the transmission line is terminated
with a 50 ohm resistor and it is assumed that 50 n « 5ill so that the 5ill
resistors don't load the output of the transmission line). Determine the comb
filter's characteristics (transfer function, vojvin ). Verify your answer with SPICE.
ilter.
10 CMOS Mixed-Signal Circuit Design Chapter I Signals, Filters,
L VOU (
Vi"
degrees
2
- 45- -
,.
- 90 - .
_1 l f(Hz) _1 3
1.0V--,--;-:--f-
1
-2td
O.9V
4td 2td td 2td 2t d O.6V
4td O.7V
O.6V
O.5V
Figure 1.10 Magnitude and phase response of the comb filter in Fig. 1.9. O.4V
O.3V .... __
ww -#-- .
O.2V -~~-- .. ---~-
O.lV .. ---- --~~-
In order to perform the addition operation seen in Fig. 1.9 we use the two 5k o.OV-'----+-
100
resistors seen in Fig. 1.11. The current through the top resistor must equal the
50 MHz
current through the bottom resistor or
Figure 1.12 Si
Vinej2n{(-ldl VOIlI VollI - Vin
(1.34)
5k 5k output will have an amI
and thus Vout is the average of the signals on the top and bottom of the resistors output is lagging the inl
Fig. 1.13. Note, in this
(1.35) signal to propagate thro.
filter's behavior follows
The result is our derivation of the comb filter's magnitude response in Eq. (1.30)
is scaled by 2 or
I~:f I = Icos nJ- t I = Icos n 200 ~Hz I

d (1.36) ::::1--/]
I :
O.6V~""---;"
I I -.
The phase response is still given by Eq. (1.31). SPICE simulation results showing O.fV-!.F'
I • I
the filter's frequency response, magnitude and phase, are seen in Fig. 1.12. Note D.2V-+!l
I how the filter eliminates from its output, input signals at frequencies that are o.ovt-·
1-
multiples of 1I2td. This filter can be very useful in communication systems where
it's used to isolate, and prevent crosstalk between, transmission channels.
In order to ensure that we can sketch time-domain signals from frequency
::::1+
I
1-
-n.BV ------;.-
domain plots consider the case when the input has I V peak amplitude and a
frequency of 50 MHz. We can see from these plots, and the equations, that the
-l.ov-l----i--
Ons 4ns
Figure 1.13 Time domain i

I
I
Transmission line 1.2.1 The Digital Comb F

Notice how, when discussin
frequency, 1, and look at th
change the input with time
delayed by td' We represente,
Figure 1.11 Implementation of an analog comb filter. In a digital system WI
a register, Fig. 1.14a. The c(
MOS Mixed-Signal Circuit Dcsign Chapter 1 Signals, Filters, and Tools 11
----------------------------------------------------------
60'
20'
-20'
-60'
1.0V T"""'<:,...--r-.-..,.---~/~;;:_'_'c:..c..:"'--,---__:"....,..~--__,
0.9V
O.8V
0.7Y
O.sv
O.SY
the comb tilter in Fig. 1.9. O.4V
D.3Y
O.2V
D.W
in Fig. 1.9 we use the two 5k O.OV-'---i--4-----i--------¥----i------4
the top resistor must equal the
50 MHz
Figure 1.12 Simulating the operation of the comb tilter in Fig. 1.11.
Voul-Vin
(1.34)
5k output will have an amplitude of 0.707 V and a phase shift of -45 degrees (or the
I and bottom of the resistors output is lagging the input by 2.5 ns). Time domain simulation results are seen in
Fig. 1.13. Note, in this figure, that there is a start-up time, the time it takes the
(1.35) signal to propagate through the transmission line (note the kink at 5 ns), before the
filter's behavior follows the equations we derived .•
agnitude response in Eq. (1.30)
OS1l:200~Hzl (1.36)
'ICE simulation results showing

:lse, are seen in Fig. 1.12. Note
signals at frequencies that are
. communication systems where
:ransmission channels.
lomain signals from frequency
las 1 V peak amplitude and a
ots, and the equations, that the
Figure 1.13 Time domain input and output (50 MHz) for the comb filter seen in Fig. 1.11.
1.2.1 The Digital Comb Filter

Notice how, when discussing the comb filter, it was more useful to vary the input signal
frequency, j, and look at the output (Fig. 1.12) of the circuit rather than attempting to
change the input with time and plot the output. In our comb filter the input signal was
delayed by td' We represented this time delay in the complex plane using eil1tfHd).
la10g comb filter. In a digital system we can implement the delay line seen in Figs. 1.9 and 1.11 with
a register, Fig. 1.14a. The contents of the register change, in Fig. 1.14a, every Ts seconds
12 CMOS Mixed-Signal Circuit Design Chapter I Signals, Filters, i
Time domain Frcquency domain

In--l_+-I
In~Out Vin(f)-t--i;:-}+- Vin(f) = Z-I . Vout(f)
T j,
/s=~ (b) Representing a delay
in the eomplex plane.
Ts
(a) A register that is clocked atls
that delays the input signal byTs •
Figure 1.14 A digital delay.

Figure 1.16
(so this would correspond to ta in Fig. 1.1l). To simplify the notation, since delays are so
common in a digital system that processes signals, we can use
Vau!
z = e j2 T"/T,
r
e j2n'(, or, for a delay, z-I e j2rrf (-T,) =e (1.37)
I Vin
The magnitude and phase I

This representation for a delay, in the frequency domain, is seen in Fig. 1.14b (some
that if we apply a constant
authors use Z-1 to indicate a delay, e j2n(-(-T,), and to differentiate behveen the general
output goes to 2 verifying t
situation where z x +jy). Figure 1.15 shows how Eq. (1.37) is plotted in the z-plane (the
dashed circle). The magnitude of e j2rrfT, is one and its phase shift is 2rcj- T5 or 2rc· i we see in Fig. 1.17.
(plotting eIlrfT, in the z-plane simply plots the unit circle). Note that plotting a delay, Z-I
or e j2nf (-T.• ), also results in a magnitude of one but the phase shift is now -2rc/- Ts. As we
move through the book we will regularly use Eq. (1.37) to evaluate the frequency
response 0/ a discrete-time system, see Fig. 1.21 and the associated discussion, and to
relate the complex number, z to the /requency,.f
t
Js
14 5; t 14
, 'lsi
9lt 14
~t.
1m, Y
Plottinge
J'on£
- f, = cos 2nf + 2nf:
j . sin
1
z x-"-jy /~ I . /
i
1
Figure 1.17 ~fagn
-~-.-~="----+---t:---~ Re, x
Note that if we di\ic
1
/ == /sI2, 3Js12, 5/5 12, 0, j" 21s, 31s, ... can think of it as an averagi
by two). Let's pause and th
output, which is the sum c
3Js14, 7/5 /4, 11/5 14, ...
resolution of the filter's outp
1 all 9-bits and not perform
Figure 1.15 Plotting a delay in the complex plane.
filter" ... or comb filter). Thif
Figure 1.16 shows the digital implementation of the comb filter. We can write (which is simply lowpass til
size should increase!) Noti:
(1.38)
number of input words and (
and thus the transfer function is
Finally, to show ho\\
(1.39) go to zero, consider averag
spaced apart by Ts , Fig. 1.1
or, after reviewing Eqs. (1.27) to (1.33), we get signal frequency and plot the
MOS Mixed-Signal Circuit Design Chapter 1 Signals, Filters, and Tools 13
equency domain
~2}+-Vin(f) = . VOUI(/)
~epresentinga delay
n the complex plane.
_-I
/.. =e Vin~VO"t
:Ia:,
Figure 1.16 A digital comb filter using one delay. Note how the
ify the notation, since delays are so output is the average (sum) of consecutive inputs.
can use
Ivoull I Is/ I
VoUl
Vm
2 . cos 1t- art d L - , -rr . -/ "lor / Is
< (l.40)
e j2 !t{(-·T,) e (L37) Vm /s 2
main, is seen in Fig. 1.14b (some The magnitude and phase response for this digital comb filter is seen in Fig. 1.17. Note
o differentiate between the general that if we apply a constartt (DC, / 0) value of 1 to the input of our digital filter, the
(1.37) is plotted in the z-plane (the output goes to 2 verifying that what we get with Eq, (l.40), at least at DC, matches what
its phase shift is 2rcI T, or 2IT .1: we see in Fig. 1.17,
rcle). Note that plotting a delay, Z·i

phase shift is now -2rcI Ts. As we
I I
V
out
2
2V7~·~
(1.37) to evaluate the frequency

f the associated discussion, and to
tting cos2rrt + j. sin2rrt

DL--L /s 1l /s 31s
)0
/(Hz)
4" 2 2 1l /s
4 2
---)0;; Re, x Figure 1.17 Magnitude and phase response of the comb filter in Fig. 1.16.
~ = 0, Is, 21s, 31s, ... Note that if we divide the output of the digital comb filter in Fig. 1.16 by two we
Cart think of it as an averaging filter (taking two inputs, summing them, and then dividing
by two). Let's pause and think about this for a moment. If the input is S-bits then the
output, which is the sum of two 8-bit words, is a 9-bit word. To avoid lowering the
, 3/,/4, 7fs!4, 11/,/4, ...
resolution of the filter's output (the number of bits in the filter's output word) we can keep
:omplex plane. all 9-bits and not perform the divide by two (but still call the filter an "averaging
filter" ...or comb filter). This is important because we will regularly pcrform averaging
:'the comb filter. We Cart write (which is simply lowpass filtering a signal) to increasc the signal's resolution (so the word
(L3S) size should increase!) Note that our definition of averaging herc is simply adding a
number of input words and outputting the result.
Finally, to show how it's possible for the output of the comb filter in Fig. 1.16 to
t-l go to zero, consider averaging two points of an input signal, at a frequcncy of 1s!2,
z (L39)
spaced apart by T, ,Fig. l.lS. It may be a good exercise, at this point, to vary the input
signal frequency and plot the corresponding outputs to vcrify the results scen in Fig. 1.17,
14 CMOS Mixed-Signal Circuit Design Chapter I Signals, Filters,
These two points average to zero

Vout
Vin
time »
Figure 1.18 Showing how the averaging filter in Fig. 1.16 can have zero output atJsl2.
1.2.2 The Digital Differentiator Figure 1.20 Magnitude a

The digital comb filter seen in Fig. 1.16 could also be called an averaging filter since its
output is the sum of adjacent inputs. The gain of this filter at DC was, as seen in Fig.
1.17, 2. We can also construct a comb filter using a digital differentiator or differencer,
Fig. 1.19. This filter outputs the difference between adjacent input signals.
Figure 1.20 shows the mag

1.19. Notice how, for this c
1.2.3 An Intuitive Discu
It will be very helpful in 0
intuitive feel for the freque
we've discussed in this s,
"'~I
-I V out
¥In--r--~ discrete-time, continuous-a:
the system. To move towar
Figure 1.19 A digital comb filter using a digital differentiator.
averager seen in Fig. 1.16 \~
In the time domain, with an input signal of v,n(t) sampled at discrete times nT" we
can write the output of the digital differentiator filter as
(1.41) It is very useful, for an int
or, in the frequency domain, time system, to plot the po
VOUI(f) = Vin(f) . (1 Z-l) (1.42)

z=x+jy
and so the transfer function of the filter is un:
z-l (1.43)
x Indicates a pole
z
o - Indicates a zero
The magnitude response of the digital differentiator is 6
-.-• X - Indicates six poles at
2
IVoUI!=
Vin ~
12l(1-cos2nLi
is) (1.44) 0 - Indicates two zeroes
or using
Unit
. 2X mag:
I -cosx == 2 sm 2" (1.45)
we get
(1.46)
Q
:08 Mixed-Signal Circuit Design Chapter I Signals, Filters, and Tools 15
J2lr:\cs'
VOlll I v 1
I-V , 1/1
...£I!.!.-(l-
- Z -l)_~

time )
I •••
, ,
Ts , " )
.16 can have zero output at/s l2. 1s)4f,12 j, 3//2 /(Hz)
Figure 1.20 Magnitude and phase response of the digital differentiator (also a comb filter).
:alled an averaging filter since its
filter at DC was, as seen in Fig. The phase response is
~ital difJerentiator or difJerencer,
/ Vout TI: / cO/ f
L - = - - T I : - lOr < <J' (1.47)
;;ent input signals. Vin 2 Is S
Figure 1.20 shows the magnitude and phase responses for the digital differentiator in Fig.
1.19. Notice how, for this comb filter, the gain at DC is O.
1.2.3 An Intuitive Discussion of the z-Plane
It will be very helpful in our discussion of mixed-signal circuits and systems to gain an
intuitive feel for the frequency response of a discrete-time system, like the digital filters
we've discussed in this section (or the switched-capacitor filters in Ch. 3 that are
Vout discrete-time, continuous-amplitude, circuits), by looking at the z-plane representation of
the system. To move toward this goal, consider the transfer function of the simple digital
igital differentiator.
averager seen in 1.16 with a transfer function of
sampled at discrete times n~, we
H(f) = VO!lt(f) =H(z) = 1 +Z-l (l.48)

Vin(f) z
] vin[(n-l)Tsl (1.41) It is very useful, for an intuitive understanding of the frequency response of a discrete
time system, to plot the poles and zeroes of the transfer function in the z-plane, Figure
(1.42)
Im,y
z x
unit circle indicates z = e f2n/ T
,
(1.43)
x-
o-
Indicates a pole
Indicates a zero
l~
6
X Indicates six poles at a location
2 -----ft~----~-------1-----Re.x
)s (1.44) 0 - Indicates two zeroes at a location
! -
Unit circle indicates the~

(1.45) magnitude ofz is unity.
(1.46) Figure 1.21 The z-plane,

16 CMOS Mixed-Signal Circuit Design Chapter 1 Signals, Filter
1.21 also shows how Eq. (lA8) can be displayed on the z-plane. A pole is located at z = 0 angle from the pole alo1
(at the location the denominator goes to zero and the transfer function goes to infinity) 45 0 resulting in an overa
and a zero is located at z = -1 (at the location where the numerator goes to zero).
Note that (1) an
The z-plane is usually used to describe the frequency response of a discrete time periodic with period Is
system, H( I), by assuming the input to the system is a unit magnitude sinusoid with are only concerned with
'0 f
varying frequency,.f. This input, 1 . e'-rtJ" evaluates the output of the system or .(.12 [the Nyquist freqt
magnitude response of}
-
phase
magnitude ~ is a delay of one clock
H(J) == Vout(J) when Vin(J) 1 e j2"Lis ( lA9) greater than or equal to t
in hardware (the output (
We should now see that the unit circle, shown in Fig. 1.21, indicates the relationship
between z and I when specified by Eq. (1A9) (this is important). Therefore, to determine Example 1.3
H( I) from a plot of a transfer function's poles and zeroes in the z-plane, we simply Determine, using the
evaluate H(z) along the unit circle. To show how this transfer function evaluation is of the transfer functi,
performed, consider Eq. (l.48) and the corresponding plot of its pole and zero shown in frequency of 1s14.
Fig. 1.22 along with the magnitude of Eq. (1.48) or Eq. (lAO) plotted against frequency
in Fig. 1.17. At DC (f == 0 and z == 1 . eO = 1LO) point A in Fig. 1.22, the gain of the
circuit is two and is calculated using
distance to zero
IH(J)I (1.50)
distance to pole
The distance from the zero to point A is 2 while the distance between the pole to point A
is 1. Therefore, as shown in Fig. 1.17, the magnitude of H( I) is 2. The phase of the
transfer function is calculated along the positive x-axis using
LH(J) = L of zero - L of pole (1.51)
which, as seen in Fig. 1.17, results in a phase angle of zero. Next consider evaluating H(z)
at 1s14 J ==1s14 and z = 1 . el'i
(
n \
1L90) , point B in Fig. 1.22. The distance from the pole
to point B is 1 while the distance from the zero is fi resulting in a magnitude fi . The Magnitude rep
I
I
Figure
z-plane
-------.L-----
z==x+jy If we label the lengtr
Point B, fsl4,5fs14 ...
I-
I
H(z) == z: J Also at point B, z :::: e
jru2 magnitude of the tram
I Labeling the angles f

I write the phase respon
Point A, DC or 1== 0, Is, 21s ...
1.2.4 Comb Filters witl
Examine the digital filter f
Figure 1.22 The z-plane pole and zero for Eq. (1.48).
S Mixed-Signal Circuit Design Chapter I Signals, Filters, and Tools 17
Jlane. A pole is located at z = 0 angle from the pole along the x-axis to point B is 90°, while the angle from the zero is
Jsfer function goes to infinity) 45° resulting in an overall phase response of -45° (verify with Fig. 1.17).
merator goes to zero).
Note that (1) any digital filter's or discrete-time system's frequency response is
ICY response of a discrete time periodic with period I, (one complete revolution around the unit circle), (2) we normally
unit magnitude sinusoid with are only concerned with evaluating H(z) over the top half of the unit circle (from DC to
put of the system or 1,/2 [the Nyquist frequency, In]), and (3) a pole at the origin has no effect on the
phase
magnitude response of H(z) but does affect the phase response (z-l , a pole at the origin,
Ie .--"----. is a delay of one clock cycle). Finally note that the number of poles in H(z) must be
L
. ei 21tf r ( 1.49) greater than or equal to the number of zeroes if the digital filterlsystem is to be realizable
in hardware (the output ofthe system cannot occur before the system's input).
1.21, indicates the relationship
lrtant). Therefore, to determine Example 1.3
roes in the z-plane, we simply Determine, using the graphical approach just discussed, the magnitude and phase
transfer function evaluation is of the transfer function indicated by the poles and zeroes plotted in Fig. 1.23 at a
t of its pole and zero shown in frequency of 1s14.
lAO) plotted against frequency
. in Fig. 1.22, the gain of the
z-plane z-plane
zero - Evaluated here

( 1.50)
pole
Ice between the pole to point A
f H( I) is 2. The phase of the
ng
L. of pole (1.51 )
'. Next consider evaluating H(z)
.22. The distance from the pole
ulting in a magnitude ti. The Magnitude reponse Phase response
Figure 1.23 The z-plane pole and zero plot for Ex. 1.3.
Point B, fs/4, 51s14 ... If we label the length from a pole (zero) to the evaluation point P (z), then the
Also at point B, z e iJti2 magnitude of the transfer function is given by
""
j _Z_l_
~ ,..; IH(z) I PI 'P2
-1···'··.···.1.
" Labeling the angles for the poles and zeroes as indicated in the figure, we can
I
•
write the phase response as
\ Point A, DC or 0, Is, 21s ...
L.H(z) == 83 -8 2 81
~
1.2.4 Comb Filters with Multiple Delay Elements
i Examine the digital filter seen in Fig. 1.24. The transfer function for this filter is given by
J[ Eq. (l.48). 'I.f"·. ·•.

H(z) =1 Z-K ( 1.52)
l d'
18 CMOS Mixed-Signal Circuit Design
+/)4, etc.). For K = 3 tho

Vin
of their simplicity, comb fi:
towpass, bandpass, and hig
1.2.5 The Digitallntegn
h"xamme the circuit seen i
Clock
I,
I H(z) Vtn~Vout
in the frequency domain
Figure 1.24 A digital comb filter using multiple delay elements.
The magnitude response for this filter is (see Eq. [1.46])

circuit adds the currer
(l.53) that there isn't a delay
non-delaying integrator or (
delay the input signal 0
and the phase response is
(1.54)
Figure 1.25 shows the magnitude responses and pole-zero plots for comb filters with
varying numbers of delay elements, K. For K 4, for example, the zeroes are located at: v,"[n~
I,j, -1, and -j. In other words the transfer function goes to zero at, DC,J/4,f/2, 3j/4,fs, vout[(n L
I )TdT~
clk I
IH(f)1 H(z) == 1 -- Z-K == js
t--Yn-=:-,,)
K 3
H(z) == I _Z-3
2 Figur
1s13 21s13 f, j(Hz) Figure 1.27 shows t1'

,
, IH(f) I
K==4
with its magnitude and pha:
phase responses we can writ,
2 H(z) = l-z-4 Phase sh
, ••• _z_~
H(z)
~--~~~--~~ z 1
f,f4 1,12 3Js!4 f, j(Hz)
, IH(f)1
I
noting e J21t j; I 1 and Le)2
,
, K= 16 used to plotting, Fig. 1.7, for
,
, H(z) l_z- 16
, 2
1/\ 1{1 'AA ~,,' iA:" ,II'
, •••
'/'I
~ To get Eq. (1.57) into the f,
f,f4 f,f2 ~fs/4 f, jCHz)
1s116 using Eq. (1.58) to simplify t
15f,116
Figure 1.25 Frequency response and z-plane plots for various values ofK in a comb filter.
fs +fs14, etc.). For K = 3 the zeroes are located at: I, . " and T'
[f ' Because
- j. 2
of their simplicity, comb filters are very useful in mixed-signal design (and used to design
lowpass, bandpass, and highpass filters that will be discussed in Ch. 4).
1.2.5 The Digital Integrator
Examine the circuit seen in Fig. 1.26. The output of the circuit, in the time domain, is
given by
vin[nTsl + vout[(n
Vin~VOUI Vout[nTsl = l)Tsl ( 1.55)
or, in the frequency domain,
pie delay elements.
H(z) H(f) = Vaat (1.56)
Vm
This circuit adds the current input to the sum of the past inputs, performing integration.
(1.53) Note that there isn't a delay in series with the input signal so this circuit is often called a
non-delaying integrator or accumulator. We'll see in a moment that a delaying integrator
does delay the input signal so it has a transfer function of z-I/( 1 - Z-I).
for 0 </</siK (1.54)

Out Out
~ero plots for comb filters with Vaut(/)
ample, the zeroes are located at: =Vin + Z-I Vow
to zero at, DC,fsI4,f/2, 3//4,fs,
K=3
j,
H(z) l-z-3
H{z) =
1 Vin ) 11 _lz_ll) Valli
Figure 1.26 The non-delaying digital integrator.
Figure 1.27 shows the z-plane representation of the non-delaying integrator along
with its magnitude and phase responses. To determine equations for the magnitude and
K 4 phase responses we can write
H(z) l-z-4 Phase shift
H(z) =z (1.57)
noting I I= 1 and L.e

i2Jt
J; = . This certainly isn't in the form, x + jy, that we are
K= 16
used to plotting, Fig. 1.7, for magnitude and phase responses. Rather it's in the form
H(z) l-z-16
1 ( 1.58)
a+jb
To get Eq. (1.57) into the form x+jy we can multiply it by its complex conjugate or,
using Eq. (1.5 8) to simplify the notation,
ious values ofK in a comb filter.

IH(f)1
z-plane
+---~----~--~.~
Is 3fs!2 f
LH(f)
degrees
A
90-
F
- 90 - -
Figure 1.27 The z-plane representation along with magnitude and phase response
for a non-delaying digital integrator.
The magnitude response it
Ia- jb a .-b
(1.59) Eq. (1,62), The phase resp

a+jb'a-jb a2 + b2 + J a2 + b 2
~~; ~.---'
~
=1 Real, x Imaginary,)
which results, after reviewing Fig. 1.7, in

, While the equatior
( 1.60) digital implementations, \
a+jb analog integrators (DAIs).
We can now write An Important Note
When a digital signal is ge
IH(f) I = -;===========~ ( 1.61)
eonverter) signal aliasing (
J(-I+eos2ntr + (Sin2nir is discussed in detail in th,
use the output of an ADC,
or have to restrict ourselves t
to avoid aliasing. Simulat
IH(f)1 ( 1.62)
1
21sin nt I CMOSedu,com,
Evaluating the phase response directly from the z-plane plot, 1.3 Representing Si
From zero From pole
~ ,~ ~, .. In the past two sections we
fixed frequency and chan!
LH(f) 2nL (nL+ 11) 180 L - 90 (degrees) for 0 < I < Is (1.63)
Is Is 2 Is z-plane, Sees, 1.1.2 and 1,
with varying frequency, Fi~
At DC the phase contribution from the zero is 0°, while the phase contribution from the and non-periodic, that are
pole, at a frequency just above DC, is 90 0 • The result is an overall phase response of function can be represen
I
I -90 0 , At Is 14 the phase contribution from the zero is 90 0 , while the phase contribution frequencies (but all sinusoi
from the pole is 135°, resulting in an overall phase response of -45 0 • signal we are modeling wi
The Delaying Integrator exponential Fourier series r
transform which is used tc
Figure 1.28 shows the delaying integrator. We get this topology by moving the delay from assumed this material is a
the feedback path in Fig, 1.26 to the forward path. The output is related to the input using the material useful for refer
JS Mixed-Signal Circuit Design Chapter I Signals, Filters, and Tools 21
Out Out
Vout(f)
(Vjn + Vout)
/s
()2 /s 3/s 12
~
l
H(z) Vin ~l Vout
I-z-
Figure 1.28 The delaying digital integrator.
( 1.64)
or
lagnimde and phase response H(z) H(f) = Vow = (1.65)
Viti 1 Z-l z-1
The magnitude response is exactly the same as the non-delaying integrator, Fig. 1.27 and
. -b ( 1.59) Eq. (1.62). The phase response is given by
) a 2 + b2
~
Imaginary. ) LH(f) -1t L J!.=-180 L -90forO</<is (\.66)

/s 2 is
While the equations describing the integrators in this section were derived using
1 - tan- IQ ( 1.60) digital implementations, we'll see in the next chapter that they also apply to discrete
'a+jb a
analog integrators (DAIs).
An Important Note
(1.61 ) When a digital signal is generated from an analog signal using an ADC (analog-to-digital
converter) signal aliasing can occur. Signal aliasing comes from the sampling process and
is discussed in detail in the next chapter. The importance here in this section is that if we
use the output of an ADC, clocked at Is , to provide the input signal to a digital filter we
have to restrict ourselves to input frequencies below the Nyquist frequency,f;2, in order
( 1.62) to avoid aliasing. Simulation examples using the filters in this section are available at
CMOSedu.com.
lot, 1.3 Representing Signals

In the past two sections we've talked about representing sinusoids using the x-y plane with
fixed frequency and changing time, Figs. 1.3 and 1.4, and then using the complex, or
es) for 0 < / < is ( 1.63)
z-plane, Sees. 1.1.2 and 1.2.3 with variable time and fixed frequency, Fig. 1.8, and then
with varying frequency, Fig. 1.22. In this section we discuss representing signals, periodic
the phase contribution from the
and non-periodic, that are not single tone (single frequency) sinusoids. Any periodic
is an overall phase response of function can be represented by a sum of sinusoids with varying amplitudes and
)0, while the phase contribution
frequencies (but all sinusoid's frequencies are integer multiples, n, of the original periodic
lse of -45°. signal we are modeling with the sum of sinewaves). In the first section we discuss the
exponential Fourier series representation of a periodic signa\. Next we present the Fourier
transform which is used to represent non-periodic signals in the frequency domain. It's
)ology by moving the delay from assumed this material is a review for the reader. Our presentation is focused on making
ItpUt is related to the input using the material useful for reference later in the book.
22 CMOS Mixed-Signal Circuit Design Chapter I Signals, Filters, c
1.3.1 Exponential Fourier Series 1.3.2 Fourier TransforrT

The exponential Fourier series representation of a periodic function with period T lif)
can be expressed using
00
get) = 2: Cn ' e j21U1fi (1.67)

n=-'Xl
where, as just mentioned, n f represents the integer multiples of the original signal's
frequency f The weighting ofthe sinusoids, cn , is calculated using
t+T
Cn == 1
T
Jg(t)· e- j21U1fi
dt (1.68) Dirac Delta Function (Unit
t
The key thing to note is that we use the Fourier Series to represent signals that are
periodic. Examples include the outputs of the sample-and-hold and track-and-hold
discussed in the next chapter. Using the Fourier Transform to look at the spectrums of
periodic signals can be very challenging for all but the simplest waveforms.
The discrete version (defin{
Dirac delta function is the 1<
As an example of the use of the Fourier Series consider the squarewave seen in
by
Fig. 1.29. The amplitude and period of this waveform are A and Ts respectively. The time
the output pulse is high is Tp. When Tp = T/2 the squarewave has a 50% duty cycle. Using
Eq. (1.68) to calculate the coefficients, with T, = Ills, we get

Some properties of the Dira
Tp
Cn -.L
Ts
JA .
0
e-j21t11f,1 dt = .
-j2rcn
. (e~21tnt;Tp - 1) (1.69)
When n = 0 we can use l'Hospital's rule to get As the amplitude tends tow
equal to 1. Also,
Co 4 (1.70)
2
Using the results from Sec. 1.2.2 we can write
= 2rcn' J2(1- cos 2rcnlsTp)

A few other key properties <
Cn -~ . (1
= 2rcn e-j21tnf,Tp ) (1.71 )
1
For the case when Tp T/2 this simplifies to
. J2(1-cosrcn) (1.72) The Fourier transform ofa (

1- 2rcn
so that the coefficients are zero when n is nonzero and even. When n is odd
(1.73)
1 where the magnitude is ] a
of a sinusoid is determined 1
D D
Ts
)
then, using Eq. (1.74)
Figure 1.29 Representing a squarewave using exponential Fourier Series.

•
[OS Mixed-Signal Circuit Design Chapter I Signals, Filters, and Tools 23
1.3.2 Fourier Transform

lie function with period T (= IIf) The Fourier Transform of a function g(t) is given by
ro
nji
( 1.67)
G(f) = f g(t)·
-00
e-
j2nji
dt (1.74)
while the inverse Fourier Transform is given by

nultiples of the original signal's ro
ated using
get) f G(f)· e
j21tji
dj (1.75)
-,n('dt (1.68)
Dirac Delta Function (Unit Impulse Response)
ies to represent signals that are The Dirac delta function, sometimes called the unit impulse response, is defined as
,Ie-and-hold and track-and-hold oCt to) = 00 when t= to and 0 ift-:/.: to (1.76)
form to look at the spectrums of
mplest waveforms. The discrete version (defined only at discrete time points, that is not continuously) of the
Dirac delta function is the Kronecker delta function, or simply delta function, and is given
consider the squarewave seen in by
'e A and Ts respectively. The time
~ave has a 50% duty cycle. Using oCt nTs) = I when t == nT, and 0 if t -:/.: nTs (1.77)
e get Some properties of the Dirac delta function are that
w
(1.69) fo(t-to)dt (1.78)
As the amplitude tends towards 00 the width of the function moves to 0 keeping the area
equal to 1. Also,
(1.70) OJ
f f(t)· o(t- to)dt == f(to) (1. 79)
A few other key properties are that the Fourier Transform of a constant is
(1.71)
00
f K· . dt = K . o(f) ( 1.80)
os 1tn) (1.72) The Fourier transform of a delay (noting a delay of to is written as e-j2njIO) is
f
00
len. When n is odd e-j2 1t/io . e-j21if1 . dt e-j2~Jto. o(f) (1.81 )

-00
_1£
d
2
(1.73)
where the magnitude is 1 and the phase shift is 21t· J 2rrf· to. The Fourier Transform
of a sinusoid is determined by first writing
Vp' sin(21tflt) = Vp' "'---2}='- - (1.82)
then, using Eq. (1.74)
ponential Fourier Series.

(l.83)
---------......_ - - - - - - - - - - - - - - - - - - - - - - - - - _ ...
and thus Suppose an IQ $:

amplitude of 0.5 '
(1.84) Sketch the resultinl
The magnitude of this equation is Figure 1.7 shows I

number that reside
i. [o(f+./l)-o(/-fJ)] ( 1.85) components are po
imaginary number
and the phase response is
If the output of a s:
phase shift positive
(1.86)
Using the SPICE j
Note that using a single-sided spectrum with positive frequencies only we could rewrite frequency response
the result as (DC), 1/4td' and li2
(1.87) Repeat question 1.

input frequencies o.
Note also that
Plot the magnitudt
Fourier{ Vpcos (2iCfl t)} = i. [0(/+ fl) + 0(/- fl)] (1.88) having the transfer
poles and zeros in
Lastly note that negative frequencies shouldn't confuse us since they simply represent a discussed in Sec. 1
phase shift. For example, response plots whet
sin (2iC(-:f)t) = -sin (2iCft) = sin (2iCft + iC) = sin (2iCft iC) 0.89) For the 3 delayeier
frequencies of O,i,/l
ADDITIONAL READING
Show how to plot
[1] M. Weeks, Digital Signal Processing Using MATLAB and Wavelets, Infinity
phase shift of this co
Science Press, 2007. ISBN 978-0977858200
Determine the z-dm
[2] S. Haykin and M. Moher, An Introduction to Analog and Digital
the frequency respo
Communications, Second Edition, John Wiley and Sons, 2006. ISBN 978
zeroes for this syste
0471432227
[3] R. G. Lyons, Understanding Digital Signal Processing, Second Edition,
Prentice-Hall, 2004. ISBN 978-0131089891 liLt
_1- [4] P. A. Lynn and W. Fuerst, Introductory Digital Signal Processing, Second
Edition, John Wiley and Sons, 1998. ISBN 978-0471976318
[5] L. W. Couch, Modern Communication Systems: Principles and Applications,
Prentice-Hall, 1995. ISBN 978-0023252860
-1
[6] E. P. Cunningham, Digital Filtering: An Introduction, John Wiley and Sons, Fig
1995. ISBN 978-0471124757
Repeat question 1.1
QUESTIONS
forward path of the (
1.1 Suggest an alternate physical example, to the swinging pendulum in Fig. 1.1, of
Determine the expo
sinusoidal motion.
in Fig. 1.29 if it is c(
1.2 Add the z-axis (time) to the representations of the sinewave seen in Figs. 1.3b-f as
1.14 Detennine the expo
discussed following Eq. (1.4).
in Fig. 1.29 for the g
1.3 Suppose an IQ signal is generated using an in-phase component having an

amplitude of 0.5 V and a quadrature component having an amplitude of I V.
U+/I)-8(f-/l)] ( 1.84) Sketch the resulting waveform, the IQ signal, in the time domain.
1.4 Figure 1.7 shows how the magnitude and phase are calculated for an imaginary
number that resides in the first quadrant of the plane (both real and imaginary
-/J)] ( 1.85) components are positive). Show how we calculate the magnitude and phase of an
imaginary number in the other quadrants.
1.5 If the output of a system occurs after the corresponding input to the system, is the
phase shift positive or negative? Why? What does linear phase indicate?
(1.86)
1.6 Using the SPICE files found at CMOSedu.com, verify, in the time-domain, the
~quencies only we could rewrite frequency response information seen in Fig. 1.10 for input frequencies of 1= 0
(DC), 1/4td , and 1I2td .
(1.87) 1.7 Repeat question 1.6 for the digital comb filter (averager) seen in Fig. 1.17 for
input frequencies of DC,j/4, and//2.
1.8 Plot the magnitude and phase frequency responses of a discrete-time system
"+II) + 8(f- 11)] (1.88) having the transfer function (I + z-I . Next, show the location of this system's
poles and zeros in the complex plane and verify, using the intuitive method
1S since they simply represent a discussed in Sec. 1.2.3, the gain and phase of the response match the frequency
response plots when the input signal frequency is O.
ft + n:) = sin (2n:lt n:) (1.89) 1.9 For the 3 delay element comb filter seen in Fig. 1.25, repeat question 1.6 for input
frequencies of 0,1,16, and/;;3.
fATLAB and Wavelets, Infinity 1.1 0 Show how to plot 1/(4+ 3j) in the complex plane. What is the magnitude and
phase shift of this complex number?
'on to Analog and Digital 1.11 Determine the z-domain representation for the circuit seen in Fig. 1.30. Also, plot
and Sons, 2006. ISBN 978 the frequency response, both magnitude and phase, and the location of poles and
zeroes for this system.
Processing, Second Edition,

Out
tal Signal Processing, Second
~7l976318
:: Principles and Applications,
fuction, John Wiley and Sons, Figure 1.30 Circuit used in question 1.11.
1.12 Repeat question 1.11, and sketch the resulting circuit, if a delay is added to the
forward path of the circuit seen in Fig. 1.30.
inging pendulum in Fig. 1.1, of
1.13 Determine the exponential Fourier series representation for the squarewave seen
in Fig. 1.29 if it is centered around ground.
sinewave seen in Figs. 1.3b-f as
1.14 Determine the exponential Fourier series representation for the squarewave seen
"*
in Fig. 1.29 for the general case where Tp T,/2.
LI5 What is the Fourier transform of the signal seen in Fig. 1.29?
1.16 What is the area under the Dirac delta function bordered by the x-axis? Why?
1.17 Show how to take the Fourier transform of sin (2rrJo +0) and cos(2rrJo+~). Plot
the magnitude and phase responses of the transforms.
The block diagram for on

analog signals is seen in
(analog) signals. The inpu
filter (AAF) that limits the
2.1) when the signal is sar
zero-order hold, ZOH), cire
." converter (ADC) where it
digital word is then passec
manipulated (e.g. lowpass j
output of the DSP block is
the digital words back im
changing amplitude but it i
oftbe DAC is fed to a reCOl
removes the spectral con ten
-I
I Note that analog ci
and RCF must be complete
precise analog circuits.
-,
V Ana
-, Pvt
t Anti-aliasing filter
-I
~AA;1 Ism
I
• Sample an
Figure 2.1 Signals r<

MOS Mixed-Signal Circuit Design
in Fig. 1.29')
bordered by the x-axis? Why? Chapter
2
l (2nfo + 8) and cos (2n:/o + $). Plot
anTIs.
Sampling and Aliasing
The block diagram for one example of a mixed-signal circuit design used to process
analog signals is seen in Fig. 2.1. The system's input and output are continuous-time
(analog) signals. The input signal is applied to an analog filter, called an anti-aliasing
filter (AAF) that limits the input spectral content to avoid aliasing (discussed in Section
2.1) when the signal is sampled and held using the sample-and-hold, SIH (also called a
zero-order hold, ZOH), circuit. The output of the SIH is connected to the analog-to-digital
converter (ADC) where it is converted to a digital word that changes with time. The
digital word is then passed through a digital signal processing (DSP) block where it is
manipulated (e.g. lowpass filtered using a digital filter like the one seen in Fig. 1.16). The
output of the DSP block is connected to a digital-to-analog converter (DAC) that changes t
the digital words back into an analog voltage. At this point the signal does have a
changing amplitude but it is still discrete in time (jagged as seen in Fig. 2.1). The output
of the DAC is fed to a reconstruction filter (RCF) to smooth it out. We'll see that this step
removes the spectral content above the Nyquist frequency,/" or/)2.
Note that analog circuits are an important component of this system. The AAF
and RCF must be completely analog in design. Further, the ADC and DAC may contain
precise analog circuits.
Sample and hold Smoothing or

reconstruction filter
Figure 2.1 Signals resulting from AID and DfA conversion in a mixed-signal system.
28 CMOS Mixed-Signal Circuit Design . Chapter 2 Sampling and AI
2.1 Sampling
V'L
In this section we discuss how sampling a signal changes its spectrum. Impulse sampling, Volts f.
decimation, the samplc-and-hold (S/H), the track-and-hold (T/H), interpolation, and
K-path sampling methods are discussed.
2.1.1 Impulse Sampling
Consider the sampling block diagram shown in Fig. 2.2. Let's assume that we apply a fm f
sinewave input, x(t), to this sampling gate of the form, Vpsin (2rrJin . t) (for the moment, a (a) Input spectrum
single frequency input). The output of the sampling gate (a.k.a. sampler),){t), is the
product of the input and a sampling unit impulse signal (Dirac delta function), 8(t nTs)
or
00
Figure 2.3 One-side
yet) L Vpsin(2rrfin' t)· 8(t- nTs) (2.1)
sampler is connected to an
Noting that the frequency of the input is 1;n while the sampling frequency is Is(-= lITs), . fn [the Nyquist frequency]),
the spectrum of the input signal is seen in Fig. 2.3a. Note that the Fourier series so that only /In remains (thi!
representation of the series of sampling impulses above is
Example 2.1
f 8(t
n~-oo
nTs) == f
.Ts n=--co
ej2rcn'IIT, == f
Ts n=--<:o
eI21tnkl (2.2) A sampling gate is strol
MHz Us 100 MHz an,
If we take the Fourier transform of the input signal after sampling (we take the Fourier the resulting output freq
transform of Eq. [2.1)), that is, we look at the spectrum on the output of the sampler, we sampler. Also, sketch th,
get
The resulting frequency
output of the sampler thr
results in an output sine'
situation, that is, to avoic
or, knowing the Fourier transform of ej2rr./ol is 8(/- fo)
and reconstructing, we I
00
sampler are less than lsi
Y(f) = 2jTs . k,,!-}8(f /In - lif,) 8(f + Jin kIs)] (2.4) we see that this is the pUl
both the AAF and RCF (
The sampled spectrum is repeated, at intervals of Is, as seen in Fig. 2.3b (the one-sided
a cutoff frequency equa
spectrum is shown, which is what we will use throughout the book). Note that if an ideal
Figure 2.5 shows the tim
lowpass filter (LPF) is applied to the output spectrum of the sampler (the output of the
I
I
:').I~
v h x(t) == Vpsin (2rrJin . t)
1
rVt v~
I. , , ~ In >~ Sampler ou~u: Aliased signal 40 60
~ t I yet) = x(t) . 8(t- nTs)
50
f,• -_t.:.2
Sampling impulses:
Figure 2.4 Spe.
8(t- nTs)
It should be clear [TOT
Figure 2.2 Impulse sampling a signa\. in a reproduction of the sam
signal's spectrum should hav
v1ixed-Si~'11al Circuit Design Chapter 2 Sampling and Aliasing 29
IY(f)1 (2is-fm)
Volts
,pectrum. Impulse sampling, In is \2fs
d (T/H), interpolation, and
Ts
et's assume that we apply a /

(2rc/;n . t) (for the moment, a (a) Input spectrum
(2is +lin)
(a.k.a. sampler), y(t) , is the
(b) Output spectrum after sampling
IC delta function), b(t nTs)
Figure 2.3 One-sided spectrum of a sinewave (a) before and (b) after sampling.
(2.1)
sampler is connected to an ideal LPF) with a bandwidth greater than /;n (and lower than
ling frequency is is( = liT,), In [the Nyquist frequency]), then the higher-order frequency components can be removed
fote that the Fourier series so that only /;n remains (this is our smoothing or reconstruction filter shown in Fig. 2.1).
00 Example 2.1
L eJ21tn/s1 (2.2) A sampling gate is strobed with an impulse train running at a frequency of 100
n=-CO
MHz (is = 100 MHz and the time in between the impulses, Ts, is 10 ns). Sketch
mpling (we take the Fourier the resulting output frequency spectrum if a 60 MHz sinewave is applied to the
he output of the sampler, we sampler. Also, sketch the time domain input and output of the sampler.
The resulting frequency spectrum is shown in Fig. 2.4. Notice how connecting the
:Uin-k/s)/] . e -J2rtft . dt (2.3) output of the sampler through an LPF, with an ideal abrupt cutoff frequency of In,
results in an output sinew ave with a frequency of 40 MHz. In order to avoid this
situation, that is, to avoid ending up with the wrong, or alias, signal after sampling
and reconstructing, we need to ensure that the signal frequencies applied to the
sampler are less than I sl2 (the Nyquist frequency, again, In). Reviewing Fig. 2.1,
J + /;n -kis)] (2.4)
we see that this is the purpose of the antialiasing filter (AAF). Notice how, ideally,
both the AAF and RCF (reconstruction filter) in Fig. 2.1 are both ideal LPFs with
1 in Fig. 2.3b (the one-sided
a cutoff frequency equal to half the sample frequency (the Nyquist frequency).
!book). Note that if an ideal
Figure 2.5 shows the time domain sketch of the sampler's output. •
e sampler (the output of the
lit Aliased signal 40 60 140 160

I
240 ' MHz f
)0
50 100 150 200 250

:(1). 8(t - nTs) t 1..:. t 2j~
In 2 JS
Figure 2.4 Spectrum of a 60 MHz sinew ave sampled at 100 MHz.
It should be clear from the preceding discussion that: (1) sampling a signal results
al. in a reproduction of the sampled signal's spectrum at DC,/s, 2/s, 3/s, etc., (2) the input
signal's spectrum should have no significant spectral content above J" in order to avoid
30 CMOS Mixed-Signal Circuit Design Chapter 2 Sampling and Ali.
The ideal magnitud!

Alias 40 MHz sinewave below the Nyquist frequenc
Sampler outputs
phase response, shown in Fi
~ \~ In other words, the filters r
. signalS.
Time Domain Description 0)
In this section we show why

.with linear phase response, i
in Fig. 2.7 is a 20 MHz sim
the original input 20 MHz
functions). After reconstruct
sinewave (it should be an ex
100 ns when the output of our satr
. time-domain response of the
Figure 2.5 Time domain input and output for Ex. 2.1.
aliasing, (3) to avoid aliasing both filtering the input signal using an AAF and increasing Sampler input, 20 MHz
the sampling frequency should be used, and (4) to reproduce the sampled signal from the
output of the sampler (which is nonzero only during the sampling impulse times) a ,J
lowpass RCF should be used.
Note that our discussion illustrates the operation of a sampling gate driven with ,,
impulse signals. As shown in Fig. 2.1, a practical system would have other building
blocks. We would rarely, if ever, sample a signal and then reconstruct it without
processing it first.
A Note Concerning the AAF and the RCF
Before going any further, we should discuss the ideal characteristics of the AAF and the
RCF. The ideal characteristics of these filters are shown in Fig. 2.6. Note that both of 10 ns 30 r
these filters must be analog by design. The ideal cutoff frequency for the filters can be no
greater than In (assuming the sampling rate on the input of the system is the same as the Figure 2.7 1m]
sampling rate on the system's output) and the filters should ideally have linear phase. Let's
discuss these two ideal characteristics.
The transfer function
domain impulse response (w
/= = I for AAF LH(jro) the transfer function of the s)
~
n=fs!2 large amplitude, very short t
IH(jro) I Ills for RCF
A o ; ) output in the time domain. T
!
r----, ~ f
: slope ;-2TCl o
IrnPUlse-L
input to
RCF t
In =fs!2 f o
(a) (b)
Figure 2.6 (a) Ideal magnitude and (b) phase responses for the AAF and RCF.
Figure 2.81
[OS Mixed-Signal Circuit Design Chapter 2 Sampling and Aliasing 31
------~---------------------------------------------------
The ideal magnitude response, shown in Fig. 2.6a, passes all spectral content
Alias 40 IV1Hz sinewave below the Nyquist frequency while removing all signals above this frequency. The ideal
phase response, shown in Fig. 2.6b, provides a constant delay, to' to all signals below I..
\
In other words, the filters remove all unwanted signals while not distorting the wanted
signals.
Time Domain Description olReconstroction
In this section we show why the filter shown in Fig. 2.6, an ideal brick walliowpass filter
with linear phase response, is the ideal RCF on the output of our impulse sampler. Shown
in Fig. 2.7 is a 20 MHz sinewave sampled at 100 MHz. Suppose we want to reconstruct
the original input 20 MHz sinew ave from the sampler output (the weighted impulse
functions). After reconstruction, the output of the RCF should be a single-tone, 20 MHz
sinewave (it should be an exact replica of the sampler input). To determine what happens
75 ns lOOns when the output of our sampler is applied to the ideal RCF, we need to determine the
time-domain response of the RCF when its input signal is an impUlse.
put for Ex. 2. L
nal using an AAF and increasing

duce the sampled signal from the
the sampling impulse times) a
J
Sampler input, 20 MHz
/SrunPI"outP~
1 of a sampling gate driven with

,tem would have other building
md then reconstruct it without
laracteristics of the AAF and the

11 in Fig. 2.6. Note that both of
10 ns
'equency for the filters can be no
of the system is the same as the Figure 2.7 Impulse sampling, at 100 MHz, a sinewave at 20 MHz .
.d ideally have linear phase. Let's
The transfer function of a system is the Fourier transform of the system's time
domain impulse response (what we are trying to find here). In other words, to determine
ic.o) the transfer function of the system, we apply an impulse to the input of the system (a very
In =/,/2 large amplitude, very short time duration pulse, Fig. 2.8). We then look at the system's
~
-~~--f output in the time domain. Taking the Fourier transform of this output gives the system's
~
: slope = -21tto
Impulse
input to
ReF -
1 ti~e_ --tIlls
tL
Ideal ReF ~
10
~+-.~.
1
1
.
tIme
o 1----- t=O
(b)
In f
ses for the AAF and ReF.

Figure 2.8 Time domain impulse response of the ideal ReF.
32 CMOS Mixed-Signal Circuit Design Chapter 2 Sampling and Ali
transfer function. Therefore (in the reverse order), to determine the time-domain impulse
response of the ideal RCF, given the transfer function, we take the inverse Fourier
transform of the transfer function. The ideal RCF's transfer function (Fig. 2.6) can be
defined by
IH(j)1 Ills for If I <fn else IH(j)1 = 0 (2.5)
The time-domain impulse response is then given, remembering 2fn , by
In
h(t) f 1. ej21ljl . df = "'----~-
-:(.,is
sin2nfn . t
Sinc( nis . t) (2.6)
nis' t
where
Figure 2.10
smx == Sinc(x) (2.7)
x
An Important Note
The time-domain impulse response of our ideal RCF is shown in Fig. 2.9. Notice that our
impulse is applied to the system's input at t 0 and that the output actually anticipates, or It is important to note that 01
starts, before the application of the input! This indicates that the filter can't be built in a amplitude (unlike an analog
practical analog circuit. Before we discuss the implications of this severe limitation (an and amplitude). The amplitu
ideal reconstruction filter can't actually be built because its impulse response is infinite in amplitude input to the samI
time), examine Fig. 2.10. Figure 2.10 shows the individual impulse response outputs of used to describe systems usi]
an ideal RCF with the impulse train of 2.7 as the input. The output of the RCF is the words, whether we are disc
weighted sum of the individual responses. While this figure is "busy," the basic concept waveforms with amplitudes
of reconstruction can be seen. represent the discrete-time s
for continuous-time systems.
sin nis . t ,
= Sinc(nfs . t)
nifs . t 2.1.2 Decimation
IHU)I
,., In the last section we focu
1-
I concepts to digital signals. v
is fromis to a lower rate off)K
2,4, 8, 16, etc.). This reduct
and is illustrated with the b
x[nTsl
In
,
I Input word rate
, Figure 2.9 (a) Ideal RCF frequency response and (b) impulse response (time).
I Figun
1
What can we do to ease the requirements on the RCF? One answer is to increase is
so it's much larger than the maximum sampled frequency. This solution is the basis for
oversampled data converters or noise-shaping data converters (studied in detail later in I Quantize: to limit the possib
the book). This solution also eases the requirements placed on the AAF. Another idea for time, for example, means that tl
as the sampling impulse times f
easing the design of the RCF is to increase the sample rate of the digital data coming out
during certain discrete time inl
of the DSP block in Fig. 2.1. This technique is called intelpoiation.
discussed in the next section).
- a
~~;"
, ?:'k""
fen;
MOS Mixed-Signal Circuit Design ~+,~'"
", Chapter 2 Sampling and Aliasing 33
letermine the time-domain impulse

tion, we take the inverse Fourier
:ransfer function (Fig. 2.6) can be j
i
else IH(f)1 = 0
mbering 2/n = Is , by
(2.5)
j
e-j-2n!n"(
Tt I,' t
Sinc( Tt/• . t) (2.6) ~==~~~~~~~~~~~~~~~~~~~==~~~-->
time
Figure 2.10 Reconstructing the 20 MHz sinewave of Fig. 2.7.

'lc(x) (2.7)
An Important Note
:; shown in Fig. 2.9. Notice that our
it the output actually anticipates, or It is important to note that our impulse sampler quantizes I the input signal in time but not
tes that the filter can't be built in a amplitude (unlike an analog-to-digital converter which quantizes the input in both time
ations of this severe limitation (an and amplitude). The amplitude out of the ideal impulse sampler is exactly the same as the
,e its impulse response is infinite in amplitude input to the sampler at the sampling impulse times. The z-transform can be
lidual impulse response outputs of used to describe systems using both quantization in time as well as in amplitude. In other
input. The output of the RCF is the words, whether we are discussing digital words, in a binary format, or sampled-analog
figure is "busy," the basic concept waveforms with amplitudes of volts, amps, or coulombs, we can use the z-transform to
represent the discrete-time systems that process the signals. Laplace-transforms are used
for continuous-time systems.
sin Ttls . t
Sinc(n/s . t)
n/s • t 2.1.2 Decimation
In the last section we focused on sampling analog signals. We can apply the same
~3.9dB concepts to digital signals. When a digital signal is "down sampled" its sample rate goes
fromis to a lower rate ofislK where K is generally, but not necessarily, a power of2 (e.g.,
2, 4, 8, 16, etc.). This reduction in the effective sampling frequency is termed decimation
and is illustrated with the block diagram shown in Fig. 2.11. The term decimation (or
Decimate (reduce sample rate)

x[nTd I y(Ki· Ts]
I ~K
~I.n:.:..-_-++--_ _ Out
- I'> / );
(b) -I3.5dB
Input word rate, Is Output word rate,f,IK
I (b) impulse response (time).

Figure 2.11 Block diagram of a decimation block.
RCF? One answer is to increase is
ncy. This solution is the basis for
nverters (studied in detail later in I Quantize: to limit the possible values of a quantity to a discrete set of values. Quantizing in
tced on the AAF. Another idea for

time, for example, means that the output amplitude is only defined at certain discrete times (such
rate of the digital data coming out as the sampling impulse times for the ideal impulse sampler) or that the amplitude is unchanging
during certain discrete time intervals (such as seen in the output of the ideal sample-and-hold
terpolation.
J
discussed in the next section).
34 CMOS Mixed-Signal Circuit Design Chapter 2 Sampling and P
decimate) can be confusing since, among other uses, the dictionary definition "to select 2.1.3 The Sample-and.
by lot and kill one in every ten." The origin of the word comes from a method of
.Understanding the opera
punishing military troops by selecting one in every ten for execution. Our much more
understanding the concep'
kind-hearted definition will mean that we are passing the input word through a lowpass
most mixed-signal syster
digital filter and then down-sampling the result (discarding samples). This procedure is
, sampler so that the samI
effectively passing the digital data through an anti aliasing filter and then resampling the
times. Having tl
result at a lower rate, Fig. 2.12. Note that the sampling gate is simply a register so it is
1n't""."-t,,,,t for proper ADI
trivial to implement decimation.
see, is that it will il
Sampling gate :
Out y[Ki· Ts]
f..----'-I-_+_-
Output word rate,/sIK
Input Clock divider,!, .;- K Output clock

JlJ1JUl
~
~
,~
•• elk
••• Figur,
Figure 2.12 Components of a decimation block.

Consider the application a
To illustrate the aliasing concerns when using decimation, and K 8, examine ,2.14. To make the discussi,
Fig. 2.13. The input spectrum of the digital data, in (a), repeats every f,. The digital input return-to-zero (RZ) as sho
data in (a) is first passed through a digital lowpass filter that is used as an anti-aliasing simpler figure and i\lustrat
filter, Fig. 2.13b. The input and output of the digital filter is clocked atf, in both (a) and the operation of the SIR in
(b). In (c) we re-time the input signal at the slower rate. Decimation is used to lower
power (because of the reduced clock frequency), simplify circuitry (e.g., serial multipliers y(t) L'"
n=-OO
-1- can be used), and to lower the amount of data storage required (fewer words to store).
As depicted in this equatio
Note that to use decimation the wanted input spectral content can't extend beyond /s12K.
sampled value vin(nTs) fo
Assuming K = 8 using convolution, see Fig.
_1- A :/s116 /,/2 /s
yet)
(a) ••• @/s
signal spectrum
S
I aftcr AAF: f /
-1
(b) ••• @/s
1
1
f
-1-
(c) ••• @j;./8
/clk .fs/8 fsl2 j, f

Desired sig;al spectrumS; /s/16
Figure 2.13 Example spectrums when decimation is employed. Figure 2.15

~,~'~,'~ >
~~:~.;
VIOS Mixed-Signal Circuit Design 1iC' Chapter 2 Sampling and Aliasing 35
f~i?<
~"\"r!k
;: dictionary definition is, "to select 2.1.3 The Sample-and-Hold (S/H)

e word comes from a method of
Understanding the operation of the impulse sampler in Sec. 2.1.1 is important in
~n for execution. Our much more
understanding the concepts of aliasing and reconstruction. However, as seen in Fig. 2.1,
the input word through a lowpass
most mixed-signal systems employ a sample-and-hold (SiH) rather than an impulse
:rding samples). This procedure is
sampler so that the sampled waveform is available at times other than the sampling
;ing filter and then resampling the
impulse times. Having the samples "held" in between the sampling impulse times is
Ig gate is simply a register so it is
important for proper ADC operation. The disadvantage of using the S/H, as we shall
shortly see, is that it will introduce distortion into our signaL
Vin
h j;n / ' \ ~ in, A

~Cn____
pIing gate .)
Out y[Ki· T,] I V V time
-- D QI-I- - f ' L - ) ) - -
i'~J I Output word rate,f,1 K ~l 4> Sample and
~y(t)
hold (SIR)
Output clock
~ clock
l'igure 2.14 Sampling and holding an input sinewave.
Sill Spectral Response

nation block.
Consider the application of a sinewave, at a frequency In' to thc ideal S/H shown in Fig.
~ decimation, and K 8, examine 2.14. To make the discussion as general as possible, assume that the output ofthe SIR can
), repeats every!,. The digital input return-to-zero (RZ) as shown in Fig. 2.15 (which shows coarse time quantization for a
Iter that is used as an anti-aliasing simpler figure and illustration of the concept ofRZ). Notc that as T approaches 1~ we get
ilter is clocked at!, in both (a) and the operation of the S/H in Fig. 2.14. The output of the ideal SIR is given by
rate. Decimation is used to lower
ify circuitry (e.g., serial multipliers
y(t) L'" [Vpsin (2rrf,n . nTs) . [u(t nTs) u(t - nTs - T)]] (2.S)
n=~(1)
:e required (fewer words to store).

ontent can't extend beyond j,'/2K. As depicted in this equation the input is sampled at the instants nT and then held at the
sampled value v;n(nTs) for a pulse length of T. We can represent the resulting signal
r Assuming K 8 using convolution, see Fig. 2.l6a, as
J'
y(t) II<
al spectrum ••• @Is
)
m after AAF : f
__---'-O~,----' . ~.~.-.-@~). Is
1ator output : f
time
CO •••
f
@fs/S
).
> S/H out
:imation is employed. Figure 2.15 Sample-and-hold output with return to zero format.
-------------~ .. -~ .. ~.--.<--
vm(nTs) I co
IX; r""·----~--··
== ( - 2: Vin(f- kfs)
yet) 2: [Vp sin(21tfin·t)·o(t-nT,)]®[u(t)-<u(t 1)] Ts k=-oo
(2.9)
or
Weighting from S/H, IH(f
Y(f) == (V in (f) ®P(f»' H(f) (2.10)
T· ISine(n· T ·f)1
where, see Eq. (2.4),
Vp 00
vm(f) ® P(f):= 2jTs . k~'" [o(f - fin - kfs) - o(f + fin - kfs)] (2.11)
We can determine the spectrum of the sampling pulse h(t) seen in Fig. 2.16a, IH(f)I, by
taking its Fourier transform
T,
H(f) f [u(t) - u(t - T)]e-: f 2n: f f • dt (2.12)
o
which is evaluated as
phase shift
T· Sine(n I T)
rre(luCJncy response by Sine
(2.13) the output of the ideal SIR
The magnitude of Eq. (2.13), !H(f)I, is plotted in Fig. 2.16b. The phase response input signal is attenuated b
corresponds to a shift in time of TI2. Since mentioned above, adds dist
S/H's frequency response usi
I Y(f) (Vin(f) ® P(f» . H(f) (2.14)
1
h(t) IH(f) I Sample-and-hold with T === T

I-
I u(t) u(t T)
~ Desired
(a)
,
~time
0 T Ts
f
o
1-
1 ± 3
T T T
Figure 2.16 (a) Sampling pulse and (b) its spectrum.

Figm
S Mixed-Signal Circuit Design Chapter 2 Sampling and Aliasing 37
I(t) - u(t - T)]

Y(1) = (.lTs fk~-cfj
vin (1- kj~)) .T· Sinc( re I T) . e-jICjT
00 T
h(r)
'T .
2:; s
L [0(1 -
k;-oo
fin -/ifs) - 0(1 + lin - k/s)] . T· Sincere I T) . ej21thj
i Q9 [u(t)-u(t- T)] (2.9)

(2.15)
I or
[deat impulse sampler response
Weighting from SIB, IH(j):
oc
f) (2.10)
Iru")1 = T·ISine(re. T 2Ts . k~OO [8(1 - lin lfs) 8(1 + lin lfs (2.16)
As T ~ 0 the output spectrum of the sample-and-hold approaches the ideal impulse

) - 0(1 + lin /ifs)] (2.11 ) sampler's spectrum seen in See. 2.1.1. Note that using an RZ format (making T < Ts) can
reduce the amount of attenuation (and thus distortion) introduced by the S/H. IH(1)I, as
I seen in Fig. 2.16a, IH(1)I, by seen in Fig. 2.16, doesn't roll off as fast. However, the cost for this is a reduction in the
sampled signal power (ultimately we get no signal power out of the S/H as T ~ 0).
Generally, redueing signal-to-noise ratio, SNR, by returning the S/H's output to ground
21t/1. dt (2.12) (RZ), to improve distortion performance, is not a good idea. Reducing SNR to improve
distortion can be useful in some situations, e.g., digital data transmission, where good
SNR isn't as much of a problem as distortion.
sse shift magnitude For most circuit designs, T= Ts so that, as Eq. (2.16) and Fig. 2.17 show, the
~ r·~--~------'
sample-and-hold operation weights the amplitude of the ideal impulse sampler's
-j~/T . T. Sine(re I T)
frequency response by Sine ; ( or Sine ~1. Note that at the sampling frequency (fs=l/Ts)
(2.13) the output of the ideal S/H goes to zero. Also note that at the Nyquist frequeney, J", the
g. 2.16b. The phase response input signal is attenuated by 0.64 or 3.9 dB. This "droop" in the S/H's response, as
mentioned above, adds distortion to the input signal. Let's illustrate the effects of the
S/H's frequency response using an example.
f) (2.14)
Sample-and-hold with T = Ts
Desired spectrum
(b)
l~ =/s12
~I~~
0.13

f
2 1
T T
10.211 =-13.5dB
; spectrum.
Figure 2.17 The frequency response ofa S/H.
38 CMOS Mixed-Signal Circuit Design Chapter 2 Sampling and A
Example 2.2
Using an ideal SPICE model for the S/H show, and discuss, the spectrum resulting Ultimately the (processed)
from sampling a 3 MHz sinewave at 100 Msamples/s. an RCF to recover the inp
The results of passing a 0.5 V (peak) sinewave centered at 0.5 V (-9 dB using 2.19. The response peaks
RMS voltages) through the ideal S/H are shown in the SPICE simulation results introduced by the S/H Sim
seen in Fig. 2.18. Note that SPICE uses a one-sided spectrum so, for example, we the requirements placed 0
must multiply Eq. (2.16) by nvo to ensure proper signal levels. The attenuation the sampling, of having the br
97 MHz image sees is the peaking type response
signal power). Note that in
7 droop introduced by th.
Attenuation Sinc( 1\'06 ) = 0.031 -30.2 dB
The amplitude of the 97 MHz image is -9 dB below the attenuation resulting from
using a S/H or -39.7 dB. At the Nyquist frequency of 50 MHz, an input signal is
attenuated by -3.9 dB as seen in Fig. 2.17.
Note that the S/H cannot be used as an AAF since any aliasing that occurred
using the impulse sampler still occurs using the S/H. For example, sampling a 60
MHz sinewave at 100 MHz still results in a 40 MHz alias signal in the base
spectrum (the spectrum from DC to In), as shown in Fig. 2.3. Now, however, the
signal is attenuated by the SiH (the attenuation is -2.4 dB at 40 MHz when
sampling at 100 Msamples/s.) In other words, the S/H can be thought of as an
ideal impulse sampler followed by a Sinc response filter.
Figure 2.19 I(
An important thing to note is that repetitively sampling and holding a signal
results in only one S/H attenuation hit (assuming the timing is such that a Circuit Concerns for Imp/e
sampling operation is not occurring when the previous SIH stage's output is
changing). This means that topologies that use several SiH operations on an input Figure 2_20 shows a sing]
signal, such as a pipeline ADC, only attenuate the signal by Sinc(ref ifs) once. This switches are closed while t
is important to understand .• the bottom plate (left side c
CH , while the right side 0
.,, . op-amp through the $1 swi1
13 11) the op-amp operat,
short that the capacitor do
1 capacitor) is always at gn
,1
197 MHz
-45dB
I:
1 -5J1dB
'1
-63dB
-72dB n-::=::::-::j:-:.,",",-~ --.
-81 dB fJL_ _-:-_ _~--'-"~-:-::.r'+:----;----;-.::::o.._~""I"""'-i
: : , : : : I
• I~
-90dB
-99dB
OMHz
----- - - - - -
30MHz
-r---------. -~ -----------r- ----------j- -------- ---( ---- -- ---t-----j
I ,
60MHz 90MHz
I
120MHz
I
150MHz
I
160t.lHz
Bottom plate
/ ~
Figure 2.18 Output of a S/H after sampling a 3 MHz sinewave at 100 MHz. Fi
10S Mixed-Signal Circuit Design Chapter 2 Sampling and Aliasing 39
The Reconstruction Filter (RCF)

iiscuss, the spectrum resulting Ultimately the (processed) output of the SIH (assuming T = Ts) should be passed through
s. an RCF to recover the input signal. The spectral shape of the ideal RCF is seen in Fig.
ntered at 0.5 V (-9 dB using 2.19. The response peaks at the Nyquist frequency to compensate for the attenuation
the SPICE simulation results introduced by the SIH Sinc response, Fig. 2.17. Note how using the RZ format modifies
spectrum so, for example, we the requirements placed on the reconstruction filter to the point, when using impulse
;nallevels. The attenuation the sampling, of having the brick wall RCF seen in Fig. 2.6. Therefore there is no need for
the peaking type response seen below (but using an RZ format reduces the SIH output
signal power). Note that in many situations a digital filter may be used to compensate for
31 =-30.2 dB the droop introduced by the SIB process.
, the attenuation resulting from

of 50 MHz, an input signal is
OdB
nee any aliasing that occurred \1 ~_- 3.9 dB (1.56)
1. For example, sampling a 60

MHz alias signal in the base
n Fig. 2.3. Now, however, the
-+----'----~
is -2.4 dB at 40 MHz when j~ f
SIH can be thought of as an
ilter.
Figure 2.19 Ideal reconstruction filter frequency response for a S/H.
;;ampling and holding a signal
19 the timing is such that a Circuit Concerns for Implementing the SIH
revious SIH stage's output is
ral S/H operations on an input Figure 2.20 shows a single-ended SIH implementation. At the time to , the ~I and ~2
ignal by Sinc(rtflj.;) once. This switches are closed while the ~3 switches are open. At this time the input signal charges
the bottom plate (left side or, here, the plate closest to the substrate) of the hold capacitor,
CH , while the right side of the capacitor is held at ground by the feedback around the
op-amp through the ~I switch. At tl the ~I switch opens and for a very short time (set by
13 - t I) the op-amp operates open loop (no feedback). It's assumed that this time is so
short that the capacitor doesn't charge or discharge. As the top plate (right side of the
capacitor) is always at ground at t[ , the charge injection and capacitive feedthrough
MHz
to tI t2 t3
~l
~
~2
~3
vow
~3
\11Hz sinewave at 100 ~Hz. Figure 2.20 Single-ended S/H operation.

resulting from the 4>1 switch turning off is independent of the input signal. When the 4>2
switch turns off its charge will, ideally, be injected into the low-impedance input, vin ,
since the impedance looking into the right of the 4>2 switch is large. This leaves the
voltage across the hold capacitor unaffected. The sequence of turning off the switch to the
right of CH (the top plate) followed by turning off the switch connecting v in to CH (the
bottom plate) is often called bottom plate sampling.
Bottom plate sampling is illustrated in its simplest form in Fig. 2.21. In this figure Note droop
the switch connected to the bottom plate of the capacitor, the 4>] switch, is turned off first.
When this happens the charge is injected into the eircuit independent of the input signal
(each side of the switch is at ground). When the <1>2 switch turns off, its charge can be
injected into the low-impedance node, the input v", , or into the series combination of Cll
and the off <1>1 switch. Again, the charge takes the lowest impedance path to ground and
thus most of the charge injection resulting from the 4>2 switch turning off flows through ReF res
v in ' leaving the voltage across the hold capacitor unaffeeted. The name "bottom plate
sampling" can be confusing. Reviewing Fig. 2.20, we see that the (physical) top plate of
the hold capacitor is connected to the <1>: switch while, in Fig. 2.21, the (schematic
representation) bottom plate of the hold capacitor is connected to the 4>1 switch.
Figure 2.22 Ex
,I. Turns off last
'l'2~
It:~lCH
:!' the lowest
impedance
sampling circui
employing both analog- a
The TlH is implemented u
When the gate of the MO
path to <1>J directly drive the capacit
ground.
7
I ~
Turns off first R..r: ''':',~rv
CH,
assuming that the produc
Rch . is much smaller 1
-1- Figure 2.21 Bottom plate sampling.
An Example
_I
Before leaving this section let's give an example of the speetrums associated with (ideal)
I sampling and reconstruction using a S/H, Figs. 2.1 and 2.22. In Fig. 2.22a we represent an
input signal as a continuous spectrum that is not bandlimited (that is, the speetrum is
completely occupied). In a real spectrum the spectral components don't have a constant
-I-
amplitude (e.g. noise at high frequencies may be considerably smaller than desired
I content at low frequencies) but here, to simplify things, we assume a constant amplitude.
The first step in our example is to pass the input signal through an ideal AAF to
limit the spectral content to the Nyquist frequency, //2, Fig. 2.22b. At this point the
spectrum hasn't been sampled so it doesn't repeat at multiples off;. The output of the AAF
is then passed through the S/H. In Fig. 2.22c we show the Sinc weighting from the
sample-and-hold process but we don't show the effects of sampling. Note the droop in the
response at frequencies approaching//2. In (d) the output of the S/H is seen. Note how
the cntire spectrum is occupied. Finally (e) shows the output after passing the S/H's
output through an ideal RCF, Fig. 2.19. Note that the spectrum is no longer periodic.
Mixed-Signal Circuit Design Chapter 2 Sampling and Aliasing 41
he input signal. When the $2

e low-impedance input, Vi" '
ch is large. This leaves the (a)
f turning off the switch to the
tch connecting Von to CH (the
(b) +1____________________ ~____s_p_e_ct_ru_m__a_fi_e_r_id_e_al_A_AF
___:_ ____._._.__~)
rrn in Fig. 2.21. In this figure
~ $1 switch, is turned off first.
dependent of the input signal (c)
--------____-=
A Note droop ______
~~_:
: Spectrum showing weighting : f
from SIH but not showing effects of sampling
J---------_ . _---------- _ >- ••• )
I turns off, its charge can be
f
~
the series combination of CH
npedance path to ground and
lch turning off flows through
Spectrum
(d) -t-!_ _ _ _ _ _---+_ _
ReF response
__ after
t
_ideal
_S/H •••
_'--_ _
f
)
ed. The name "bottom plate ~

lat the (physical) top plate of Spectrum after ideal ReF,
(e) same as (b) •••
in Fig. 2.21, the (schematic >
~d to the $1 switch. fsl2
f
Is
Figure 2.22 Example spectrums when ideal, AAF, S/H, and ReF are used.
ist
2.1.4 The Track-and-Hold (T/H)
Another sampling circuit that is useful in mixed-signal circuits, especially those
employing both analog- and digital-signal processing, is the track-and-hold, Fig. 2.23.
The T/H is implemented using a sampling gate, here a MOSFET, and a storage capacitor.
When the gate of the MOSFET is driven high it turns on and allows the input signal to
directly drive the capacitor (the T/H's output). In the following discussion, we are
assuming that the product of the MOSFET's on resistance and the hold capacitor,
--- Turns off first Rch . CH, is much smaller than the period ofthe input signal.
Track Track
~
:trums associated with (idcal) Sinewave in Vinet) !
. In Fig. 2.22a we represent an
I 0J:ut
yet)
~""Uit~~
o •
tited (that is, the spectrum is
:lonents don't have a constant
derably smaller than desired
Issume a constant amplitude.
time
gnal through an ideal AAF to :.e
2.22b. At this point the T
:S ofIs. The output of the AAF :( T! >
the Sinc weighting trom the Track
Impling. Note the droop in the
of the S/H is seen. Note how
utput afier passing the S/H's Figure 2.23 Track-and-hold output.
1m is no longer periodic.
To determine how the TIH affects a sampled signal let's first notice that the hold total T/H output spec
portion of the output is exactly thc samc as the SIH with RZ format seen in Fig. 2.15, Eq. Eqs. (2.15) and (2.22) or
(2.15). Knowing this we can focus on the track portion of the output and then sum the
responses to get the overall TIH response. For the track portion of the ideal T/H we can Y rlH(f) = Ts . Sinc( rt I T
write, sce Eq. (2.8),
Ts T cr:
r h,ul -Ts' L
l
k=
YI(t)=n~oc Vp sin(2rt/in· t )· [u(t-nTs-T}-u(t-nTs Ts
1/2j, then we
(f1-'I Sine [
n~ro O(t- nTs)l L
=k~-ro
00
Vp sin(2rt/i1l' t) . {hl(t)@ (2.17) 2
Knowing
00 00
L 8(t nTs) has a Fourier transform of!s L o(f- kis) (2.18)

n=-oo k=-XJ
we can write
(2.19)
Reviewing Eqs. (2.12) and (2.13) we can write
. (Ts T). Sinc(rr; I (T, T) (2.20)

and so, since!, = 1ITs'
epn~selltatlon as
00 T T '"
HI(f)-j, ~ 8(f-kfs)=~·.~ . Sinc(rr;· kj,' (T, T»· 8(f- kf,)
iYT!H(f)1
k~-oo s k-··~ro
(2.21 )
The track portion ofthe T/H's output spectrum for an input signal, vmC!), is conversion then'
yH.~U'."'Hwe don't want tht
fl(f) = Vin(f)@l TSTs T. k~m . Sine(rt· kf, . (T, - T). 8(f- kf,,) j the track portion,
(discussed in Sec. 5.2.1).
2.1.5 Interpolation
,'
One of the main assumpti!
For the single-tone input sinusoid used in Eq. (2.17) discussions, is that an RCF
YIU) = and a cutoff frequency c
',- Vp(Ts T) ~ ( .
challenging analog filter de
2T
'.),
. Smc(rt . kfs . (Ts
£...,
k=···",
T). [8(f-.fin kfs) - 8(f+fin - kfs)] . ) we can increase is while k
words, by increasing!, the (
, or (2.23) wanted frequency of interes
-, Ideal impulse sampler response
Weighting from ht(t)
Decreasing the cloc
cover increasing the cia
Ifl(f)1 L
k=-oo
en
-T)·Sinc(rt·kj,·(Ts T»· 2;, .[8(f-fin-kfs)-8(f+fin
V
interpolation can be used
introductory section, we foc
goes from is to a high!
(2.24) nec:es!;ari a power of 2. In
)S Mixed-Signal Circuit Design Chapter 2 Sampling and Aliasing 43
lal let's first notice that the hold The total T/R output spectrum, YTIH(/), for a general input signal VinCI), is the sum of
RZ format seen in Fig. 2.15, Eq. Eqs. (2.15) and (2.22) or
of the output and then sum the T 00
YT!H(f) = Ts ·Sinc(n IT)· e- ·2rr.f-; . k~OO vm(f-kfs) +

j
portion of the ideal TiH we can
Ts-T. f (2.25)
Ts k=-oo
:1- nTs Ts
IfT= TsJ2 = 112/s then we can write this equation as
00 ({ 1 f 1\
L'" o(t-nTs)l (2.17)
YT!H(f) = L
k=-oo
I -. SincllI· -) . e
\. 2 2 Is
"=-oc J
We know from Fig. 2.17 that a sinewave at nearly J;, will see an attenuation of 0.64 (-3.9
00
dB) when using a SIR with T = Ts. Using the T /H with T = T,/2 the attenuation the
Is L 8(f-kfs) (2.18) sinewave sees at nearlyJ;, (f ~ /,/2) where k = 0 (the frequencies from DC to 1/2) is
k=-oo
IY TlJ{(f) I = ! ISinc(~) . + 1 . eO I (2.27)
or
(2.19)
(2.28)
We know we can't directly add the polar representation of these numbers so let's rewrite
reI(Ts T) (2.20)
this equation, noting 0.9 cos (-~) = 0.636 and 0.9 sin (-~) = -0.636, using the Cartesian
representation as
IYl'lJ{(f) I = ~ 10.636 + j(-0.636) + I + jOI = 0.877 ~ -1.1 dB (2.29)

(2.21) Note that if we are sampling an analog waveform for Nyquist-rate, analog
It signal, vin(f), is to-digital conversion then we have to use a S/H (or the hold portion of the T/H). In this
situation we don't want the input to our quantizer (ADC) to vary, as it does in the T/H
:Ts - T) . o(f- kfs) J during the track portion, since this will cause an error called aperture uncertainty
(discussed in Sec. 5.2.1).
Ts - T). V;n(f- kfs») (2.22) 2.1.5 Interpolation
One of the main assumptions when reconstructing the output signals, in the preceding
discussions, is that an RCF is available with a brickwall like shape (Figs. 2.9 and 2.19)
and a cutoff frequency of 1/2 (the Nyquist frequency). This, however, is a very
challenging analog filter design problem. To make the design of the RCF less challenging
- o(f+fin - kls)] . we can increase f, while keeping the desired spectrum limited in bandwidth. In other
words, by increasin8.f, the effective Nyquist frequency becomes larger than the maximum
(2.23) wanted frequency of interest. This is called oversampling.
[deal impulse sampleI' response Decreasing the clock frequency (decimation) was covered in Sec. 2.l.2. Here we
cover increasing the clock frequency (call interpolation). Both decimation and
interpolation can be used in discrete-time analog signal processing. Here, in this
introductory seetion, we foeus on digital signals. When a digital signal is "up sampled" its
rate goes from J, to a higher rate of K -/s. As with decimation, K is generally, but not
(2.24) necessarily, a power of2. Interpolation is represented as seen in Fig. 2.24.
44 CMOS Mixed-Signal Circuit Design Chapter 2 Sampling and
Interpolate (increase sample rate)

x[nTs] [ . Kr'l
Yl'
i
I
In
_In_---.,f-;I>11'__---11 Out I )
Input sample rate, ~[ nTs]

K ;' )
L~ _ _~
Input word rate,is Output word rate, K is
Figure 2.24 Block diagram of an interpolation block.
There are three basic interpolation schemes (ways of increasing the sampling, or
clocking, frequency): zero padding, using a hold register, and linear interpolation, Fig.
2.25. Figure 2.25a shows an example input to an interpolator. In (b)-(d) we show
interpolation with K 4.
Zero Padding Figure 2.26 A ze
The benefit of using zero padding, Figs. 2.25b and 2.26, is that the desired spectrum
remains unchanged. We'll discuss this more in a moment. The drawback of zero padding the word size and shift ea
is that the amplitude of the output signal drops by K. If our input is a constant value of 1 power of 2). For the pre~
and we insert 3 zeroes (K 4) then our output has an average value of 0.25 (average of 1,
two places reSUlting in t.
0, 0, 0). This is normally not a problem for a digital signal since we can simply increase original input). In the foil
x[nTs] .' the input or output wor
padding.
~ • (a) input signal
•
• •
I
• i Returning to Fig.
bas the assumed spectrUl
+-_-'-_-'-_--'-_.-L~_---,-
I
TI]
Y[/.. K
2
!
•
_
I
___,--'---,~--'----+) n ..L.
.~
"counter and AND gate aI
zero padded waveform Sf
Nyquist frequency has me
" (b) zero padding
I
I !...12 4
T,]
Y[I'. K
T•••,••• I...i.......r...t•••,•••I...
>1' Kt
' Ts
(a)
;. New Nygu
jS ?
1
t (c) hold register
(b)~
tiTr ~m""IIIIIIII ttTt,,,,1m~,
I
1
tllli
y[i'~]
.ll.llil •
. Kt
(c)
~C~~
~1"~'
1
; I
(d)
I
.1'T . ['::"''"
• ~ll." Ts
Figure 2.25 Types of interpolation. Figure 2.27 Exarr

lOS Mixed-Signal Circuit Design Chapter 2 Sampling and Aliasing 45
Jle rate)
y[i· In (a)
Out ---f/~)-----i~ I ...
/ )
Input sample rate,x[nT,] ..§ '
clk! (c) or (d)
o ;:s I------,f--_ y[ i .
Output word rate, K I, Is o e:>CJ
OU)
Sel .-----~KIs
terpolation block.
ys of increasing the sampling, or

ter, and linear interpolation, Fig.
nterpolator. In (b)-Cd) we show Kis
Figure 2.26 A zero-padding interpolation block, see spectrums in Fig. 2.27 .

.26, is that the desired spectrum
It. The drawback of zero padding
the word size and shift each nonzero sample towards the MSB by log2K (assuming K is a
our input is a constant value of 1
power of 2). For the present example we would shift the constant value of I to the left
erage value of 0.25 (average of 1,
two places resulting in 4. When we average the 4 samples (4, 0, 0, 0) we get 1 (our
~nal since we can simply increase
original input). In the following, and in Fig. 2.26, we won't explicitly show the shifting in
the input or output words to compensate for the signal reduction when using zero
(a) input signal padding.
_-L,__IL-_~") n ...L
Returning to Fig. 2.26, we see that our input signal changes every Ts seconds and
has the assumed spectrum seen in Fig. 2.27a (marked (a) in Fig. 2.26). A log2K size
, Ts counter and AND gate are used to select the input signal one of K times so we get the
zero padded waveform seen in Fig. 2.25b (spectrum shown in Fig. 2.27b). Note that the
Nyquist frequency has moved from 1/2 to Kj;/2. The problem is that the images are still
(b) zero padding
• K=4
•••••• I.~i, (a) •••
I, New ~uist frequen~y f
(c) hold register
(b) •••
it""HU ") i, T
s
(c)
removal filter'
f
(d) linear interpolation

•
IT,!!I I .
..LL-'-'-1-Lc....._ _~) I,
Kt
-1'
Cd) •••
s
K·fs/2 K·1s 2K·1s f
ation. Figure 2.27 Example spectrums when zero padding interpolation is employed.
present in the wavefonn and thus need to be removed. This is the point of using the image . Ifwe multiply the top an,
removal filter seen in Fig. 2.26. Figure 2.27c shows the spectrum after increasing the
sample rate and passing the signal through an ideal image removal filter. Also seen in this
figure is the response of the RCF. It now starts rolling off at is 12 and can extend up to
Kf, - f,/2. Note that the RCF's response seen in Fig. 2.27a must cut off abruptly at is 12.
Finally, Fig. 2.27d shows the spectrums when a non-ideal digital image removal filter is
used. The figure shows the nonzero spectral content remaining in the spectrum after
filtering.
Hold Register
Figure 2.28 shows the block diagram of interpolation using an input hold register (which
may simply be the input of a digital filter). The benefit of this topology is simplicity. We
simply clock the input word K times faster into a register to increase the clocking
frequency as seen in Fig. 2.25c. Note how the wavefonn seen in Fig. 2.25c looks similar
to the output of the S/H discussed earlier in the chapter (so we should be expecting some
sort of Sinc response effect on our input signal as seen in Eq. [2.16]).In order to quantify
we label the interpolato
this last comment we can write the output of the hold register in tenns of its input using
T ] K·(n+ 1)-1 1 T ] r
r
Yu i·..2. = L -·x i·..2. =x[nTs]
_ K i~Kn K ~ K
(2.30)
noting, K· n :::; i ~ K . (n + 1) I , or
K -yu(nTs} == x[Kn· ~ J+X[(Kn+ l)~ J+X[(Kn+2)~ J+ ... +X[[K' (n+ 1) 1]~ J

(2.31 )
Writing the z-domain representation (using the input clock as the reference for the delays,
or, z e j2v.f T,) of this equation gives
Yu(z)· zn . K == [l + Z11K + z21K + ... + z(K-l}/K} . zn . X(z) (2.32) This equation is plotted i
I attenuation approaches 13
I or, where the zn represents a shift in time of nT"
,
Yu(z) ==.1. [1 + zllK + + ... + z(K-l)IK] (2.33)
X(z) K
I
,-
UpsampJed output
Digital Desired s~c1!Ji!JJl__!
~Yu [.I- KTs] filter
,- In
-----.~--~DQ~+-~----~
Input word rate,x[nTs ] elk
@is
Figure 2.29 Freql
It's also of interest

Figure 2.28 An interpolation block using a hold register, see spectrums in Fig. 2.32. frequencies of inte
ixed-Signal Circuit Design Chapter 2 Sampling and Aliasing 47
ile point of using the image Ifwe multiply the top and bottom of this equation by I we get
ctrum after increasing the
)val filter. Also seen in this H (z) = Yu(z) (2.34)
u X(z)
ls 12 and can extend up to
ust cut off abruptly atls 12. or
ital image removal filter is
ling in the spectrum after (2.35)
Knowing 11 1(1 cosx)-jsinxl = =J2(1-cosx) and

2
I-cosx 2 8in ",2 we
I input hold register (which
topology is simplicity. We
: to increase the clocking 1
in Fig. 2.25c looks similar (2.36)
K
: should be expecting some
[2.16]).In order to quantify
n terms of its input using Ifwe label the interpolator's output frequency Is,new K·1s then
1 sin (rc. Sine(rc Kf 1

fs.n~)
(2.30) IHu(f)1 =-. (2.37)
K .
sm Sine ( rcf,~J
This equation is sketched in Fig. 2.29. This isn't exactly a Sine response, Fig. 2.17, but a
+ x[ (K . (n + I) 1] ~ ] similar-shaped response. We'll find that this equation also comes up when discussing Sine
response digital filters so let's spend a moment characterizing it. The ratio of the main
(2.31 ) lobe to the first sidelobe can be determined by evaluating the response at 1.51s,new1K or
:he referenee for the delays,
Main lobe
IFirst sidelobe
I K .
. sm
(urc'
K)
\ (2.38)
(2.32) This equation is plotted in Fig. 2.30 for varying K. Note how the maximum amount of
attenuation approaches 13.5 dB (the same as the Sinc response seen in Fig. 2.17).
(2.33) IHu(f) I
Desired sl"""~"""-_
I) y(i. f Is,new K·1s

K K K
is,ne w
2K
Figure 2.29 Frequency response interpolated data sees using a hold register.
It's also of intcrest to determine how much droop the filter will introduce into the
~ spectrums in 2.32. signal frequencies of interest at the Nyquist frequency. Figure 2,31 shows the droop
(attenuation) at the maximum desirable input frequency of j,/2 or j"npw/(2K). We can

calculate the amount of droop, again using Eq, (2.37) when ls,new/(2K), as XU).-: D"ired """
Droop == .
K,sln UK
(1t) (2.39) (a)"DC
YU</)~ Is
This equation is plotted in Fig. 2.31. Note that as K gets large the amount of droop
approaches 3.9 dB (= 0.64) or the same as the Sinc response seen in Fig. 2.17.
(b)~
RCf (;
dB
\- ~
..
(C) • . . . .
Main lobe I
4 13.5 dB
.
'(d)
~.. '
JIII\~
IFirst sidelobe
I:!.
-tlill-i-I 1 !~
f,/2
Kfsl:
Figure 2.32 Example

'
346 8 10 K
Interpolation
Figure 2.30 Attenuation versus K.
Figure 2.32 shows some example spectrums when K = 4 and using an input hold
register for interpolation. In (a) we see a representative input spectrum that repeats every r
is. In (b) the input is upsampled to a clocking ratc of K -j,. The effects of the input • u vi
holding register's Sinc response are seen. At this point we have distorted our desired
K· n ~ i < K· (/1 +
information with the drooping response seen in Fig. 2.31. In (c) the signal's spectrum,
after passing through an ideal image removal filter to remove the undesired frequency Writing this equation in th
components, is seen (see also Fig. 2.28). The RCF can have a slow roll-off ultimately
passing negligible content at frequencies above K·1s - I s l2 where the image around the
-I-
I
new clocking frequency, K·j" exists. Finally, in (d) we show what the spectrums may
look like with a non-ideal image removal filter. The design of the RCF depends on the
allowed amount of unwanted spectral content that can be tolerated in the final output
_1- spectrum. which is the same as Eq. (:
interpolation to introduce
IHu(f) I Droop, dB
. T,]
:::t ·
[
I~Dmop
YI'K
t
-1-
I
~-.-----:- --.--.--.~
!s,new/2K
or
!
-3.8 -1
-4,0 t--t--t-+-+
3 4 6
+-+-1
8
-+--+I~
10 K
11,
Interpolator 11
f,/2
J<'igure 2,31 Droop at edge of signal bandwidth. F

; Mixed-Signal Circuit Design Chapter 2 Sampling and Aliasing 49
f 1,/2 or ls,new/(2K) , We can K=4

1"" Is,ne"/(2K1, as
(2,39)
f
ts large the amount of droop (b)
: seen in Fig, 2.17.
.
After (ideal) image removal filter
f
(c) •••
13.5 dB f
(d)
...
fsl2 f
Kf, 2K·1s
Figure 2.32 Example spectrums when interpolation using a hold register is employed.
Linear Interpolation
The final interpolation scheme we'll look at is linear interpolation, adding samples in
between the interpolator's inputs that linearly change with time, Figs, 2.25 and 2.33. We
1( = 4 and using an input hold can describe linear interpolation mathematically using
ut spectrum that repeats every '
Yu [C 1+
\).Ts]_ [ .. Ts] x[(n+l)Tsl x[n·Ts]
K - Yu 1 K + K (2.40)
.j;. The effects of the input
ife have distorted our desired
. In (c) the signal's spectrum, where K·n:5,i<K·(n+l). Note that when i K·n, Yu[i.1-]=x[nT,]=yu[nTs].
Gove the undesired frequency Writing this equation in the z-domain we get
ave a slow roll-off ultimately
Yu(z). zn+llK z". [ Yu(z) + X(z) . ~- X(z) ] (2.41 )
: where the image around the
how what the spectrums may
Yu(z) \
n of the ReF depends on the (2.42)
: tolerated in the final output
X(z) = K' 1
which is the same as Eq. (2.34). After reviewing Fig. 2.25 we might have expected linear
interpolation to introduce less distortion into the input signal than an interpolator made
Interpolator adds these digital words

• / (adds K 1 samples)
••
i
i • • ••
6 8 10 Interpolator inputs
l-,==~~==~~====~~==~~~~~~l
+"
.K
' - Ts
K, n :5, i:5, K· (n + \) - \
dwidth. Figure 2.33 Using linear interpolation.
using a hold register. However, the fact that the output of an interpolator made using a
hold register sees abrupt changes or steps over time (indicating higher spectral content)
Let's show how to apply K
results in the equivalence in both interpolator's spectral responses. Note that this type of
analog signal processing).
interpolator is more commonly found in analog signal processing using discrete-time
switch is closed when a no
analog circuits.
. high at the same time) sign
2.1.6 K-Path Sampling on the capacitor is
In the last section discussing interpolation (upsampling our signal or increasing the clock
rate) the input clock rate was Is and the output clock rate was Kis. If we define z in terms
and when the q,2 switch ope
of the input clock, z e j21t .{, then a delay on the output of the interpolator is written as
= e-
j2rtf
r: and a delay on the input of the interpolator is written as . If, on the Q2 vout[nTs]' (el
other hand, we define z in terms of the output clock, z then a delay on the output
is written while a delay on the input of the interpolator is written as . In simpler
terms, a delay on the input lasts T, seconds while a delay on the output lasts T)K seconds.
In analog signal processing we can get the same type of behavior, an increase in the
output clock frequency (or upsampling the input signal) by using more than one path.
In order to understand this last statement, consider the parallel paths of S/Hs seen
in Fig. 2.34. Each S/H is clocked on an opposite phase of an input clock. The resistors are If we input a DC voltage
used to sum the outputs of the S/Hs. If the input clock is Is, then the output signal will magnitude of Eq, (2.47) is
change every T/2 seconds or at a rate of 21s Hz. By using two-paths we effectively realize simple RC circuit (as seen i
an interpolation rate, K, of 2. In other words, we can think of the two-path S/H topology
as a single path topology clocked at 21s Hz. For K paths we can write, again,
/s,new K (2.43)
and, knowing the ten
cycle (which is negligible f.
Sample and
x(t)Jn---..-~
hold (S/H)
I
1
clock@/s phaseJ
1 Sample and
hold (StH)
'---___t...rL-=-='--_...J phase2
'1-
x(t) -"In!.L-_ _ _ _~ Sample and
I 1---»--y(t)@2J,
hold (S/H)
clock@2/s
'Figure 2.34 Using two StH paths. Fig

\1ixed-Signal Circuit Design Chapter 2 Sampling and Aliasing 51
m interpolator made using a Switched-Capacitor Circuits

ting higher spectral content)
onses, Note that this type of Let's show how to apply Kpath design to switched-capacitor circuits (commonly used for
)cessing using discrete-time analog signal processing). Examine the switched-capacitor circuit seen in Fig. 2.35. A
switch is closed when a non-overlapping clock (meaning that the clock signals are never
high at the same time) signal is high. When the 4>1 switch opens at (n 1/2)Ts the charge
on the capacitor is
ignal or increasing the clock (2.44)
s Kfs. If we define z in terms
and when the 4>2 switch opens at nT, the charge on the capacitor is
the interpolator is written as
is written as . If: on the Q2 vout[nTs]' (C[+ CF) = vin[(n lI2)Ts] , Ct+vout[(n-l)Ts]' C F (2.45)
f
if, then a delay on the output Writing this equation in the z-domain we get
is written as z-K. In simpler
(2.46)
he output lasts Ts I K seconds.
behavior, an increase in the or
iing more than one path. VOUI(Z)
(2.47)
e parallel paths of S/Hs seen Vln(;;;) == Ct+C F CF'Z-I
input clock. The resistors are
If we input a DC voltage, f = 0 or z I, then the output is equal to the input (the
;, then the output signal will
magnitude of Eq. (2.47) is one). This circuit behaves, for input frequencies «fs like a
)-paths we effectively realize
simple RC circuit (as seen in Fig. 2.35). To prove this let's write
)1' the two-path S/H topology
m write, again, z ej2n.f1t~ "" 1 +}2rcZ 1+ is for f«/S (2.48)
(2.43)
and, knowing the ;;;-112 term in the numerator is simply a phase shift of one-half clock
cycle (which is negligible for input frequencies «D,
(2.49)
~I)@f, or
Yl (t) + Y2(t)
2
Equivalent for input frequencies
1 ,
'0)0 time
-y(t)@2/s
i
rS~l
R,,- f,C, ~ CF
VO"t(t)
(n (n+ 1I2)Ts
Figure 2.35 Switched-capacitor lowpass filter.

52 CMOS Mixed-Signal Circuit Design Chapter 2 Sampling and A
Figure 2.37 shows K-path

(2.50) topology. Note that at tl"
including path matching ar
where we've defined

_ Ts
- C/ (2.51 )
We can also write the exact frequency response, Eq. (2.47), of this switched-capacitor
circuit
(2.52)
(~~ + I - cos 2rr.flf,) + j(-sin 2rr.f/fs)
or
(2.53)
Note that for f «fs the cosine terms is approximately one and the sine term is (b) Equivalent Cil
approximately 2rr.flf, so this equation simplifies to Eq. (2.50).
Next let's examine the two-path version of Fig. 2.35 shown in Fig. 2.36. The Figure
effect of using two paths is to double the output sampling rate, fs.new = 2fs. Using Eq.
(2.47) we can write
Overlapping Clock GI2
(2.54) Figure 2.38 shows a circl
signals. A shift register is I
At the new sampling rate we can write figure is used to detect ifm
'Z-l
flip-flops. The amount of I
'1- H2-path(Z) = C C C -2 (2.55) through the two inverters C(
/+ F F'Z
or, in generic terms of K, replace Z in the transfer function of the single-path topology
with zK to get the transfer function in the K-path topology,
.1
(2.56)
'1
elk
Shift register
Figure 2.36 Switched-capacitor 2-path lowpass filter. Figure 2.38 G

lOS Mixed-Signal Circuit Design Chapter 2 Sampling and Aliasing 53
Figure 2.37 shows K-paths and the equivalent single path topology, a time interleaved
(2.50) topology. Note that at this point there are several important topics we can discuss
including path matching and the effects of clock jitter (more later).
(2.51) ~~~.----------:~
~~--------~---
~3 : n _ _ _ _- - ' _ _
2.47), of this switched-capacitor L
~4 nL______T-__
••
(2.52) •
.....j( -sin 2:rf is)
Non-overlapping docks
(2.53)
I
z :~
ately one and the sine tenn is ej21tjl(Kj,)
(b) Equivalent circuit Ts/K
2.50).
g. 2.35 shown in Fig. 2.36. The Figure 2.37 A K-patb topology and its equivalent circuit. -I
)ling rate, /s,new = 2is. Using Eq.
/.
(2.54)
Non-Overlapping Clock Generation
Figure 2.38 shows a circuit useful for generating four-phase, non-overlapping, clock
signals. A shift register is preset so that only one bit is high. The logic block seen in the
I
figure is used to detect ifmore than one output is high. Note the clear and set inputs of the
flip-flops. The amount of non-overlap, or dead time, between pulses is set by the delay
(2.55) through the two inverters connected to the outputs of the NAND gates.
~tion of the single-path topology

y,
(2.56)
elk
Shift register
O\vpass filter. Figure 2.38 Generating a four-phase non-overlapping clock signal.

2.2 Circuits Example 2.3

In this section we discuss the implementation of the S/H and discrete analog integrators Simulate the operation
(DAIs). The focus is on developing equations and block diagrams for the circuits that will 1 pF and f. = 100 tv
be useful as building blocks in the coming chapters. It's assumed, in this section, that the matching ofthe two cal
reader is familiar with the bottom-plate sampling technique seen in Fig. 2.20 and the The simulation results
associated discussion. shown. Note the non-c
2.2.1 Implementing the 5tH where the falling edge
they go low at the sa
A fully-differential mixed-signal S/H based on the topology seen in Fig. 2.20 is seen changing to very large
below in Fig. 2.39. The sample portion of the SIB occurs when the~! and ~2 switches are operates open-loop witl
closed and the ~3 switches are open. When the ~3 switches are closed the ~! and ~2
switches open and the value of the input signal at this instance is "held" until the next
In part (b) we sho\~
outputs are set to the co
time the ~3 switches are closed.
configuration (which n
We can determine the relationship between the input of the S/B and its output by op-amp to VCM when 4J!
writing the charge stored on C, when the ~! and ~2 switches are closed (the ~3 switches are When 4J3 goes high, the
open) as outputs connected throl
capacitances.
(2.57)
Introducing a 1000A
where Vas is the offset voltage of the op-amp. When the op-amp is in the follower
values of CF from 1 pF
configuration, the ~! switches are closed, and the input/output voltages of the op-amp go
2.40. Also. an unrealis
to VeM ± Vas (assuming infinite op-amp gain). When the <P3 switches close we can write
SlH's operation.•
(2.58) Finite Op-Amp Gain-Band'>
Since charge must be conserved, vow = v m• The input is sampled on the falling edge of ~!' The previous derivations a:
was driven to precisely V 0
Op-amp open-loop gain is .
. open-loop gain of an op-am
,
~2 In nanometer CMOS the I
Vin+~ giving a gain-bandwidth pn
,,
The SIB is an exarr
Vin- ··~--.L""-C-L- Vont···
classic feedback equation
to t1 ~2
$3
t2 tJ
,
~1
~2
n Since, during the hold open
Can write, for DC,
1
~3
I ?~-
Indicates plate closest to the substrate As the op-amp's open-loop i
that the closed-loop gain w
Figure 2.39 Fully-differential SlH differential topology.
;; Mixed-Signal Circuit Design Chapter 2 Sampling and Aliasing 55
Example 2.3
md discrete analog integrators Simulate the operation of the S/H building block seen in Fig. 2.39 assuming Cp
grams for the circuits that will 1 pF and j; 100 MHz. Show that the sampled signal isn't affected by the
mmed, in this section, that the matching of the two capacitors in the S/H or by an op-amp offset.
lue seen in 2.20 and the The simulation results are shown in Fig. 2.40. In part (a) the clock signals are
shown. Note the non-overlap time. Unlike the clock signals shown in Fig. 2.39
where the falling edge of ~2 is delayed from ~I' the simulation sets the signals so
they go low at the same time. This was to avoid the outputs of the op-amp
)gy seen in Fig. 2.20 is seen changing to very large values for the small amount of time the ideal op-amp
'hen the ~; and ~c switches are operates open-loop with an input signal applied.
hes are closed the ~I and ~2
;tance is "held" until the next In part (b) we show the op-amp outputs. Note how, when ~I goes high, both
outputs are set to the common-mode voltage by forcing the op-amp into a follower
configuration (which may lead us to use switches to short the terminals of the
Itof the SHand its output by op-amp to VeM when ~I is high if offset isn't important, more on this in a moment).
are closed (the ~3 switches are When ~3 goes high, the circuit behaves as an S/H. Part (c) of the figure shows the
outputs connected through ~3 switches, as seen in Fig. 2.39, driving 10 pF load
(2.57) capaci tances.
t Vos)
Ie op-amp is in the follower Introducing a 100% mismatch in the two capacitors by changing one of the
values of Cp from 1 pF to 2 pF doesn't affect the simulation results seen in Fig.
put voltages of the op-amp go
2.40. Also, an unrealistically large op-amp offset of 100 mV doesn't affect the
switches close we can wTite
S/H's operation.•
± Vos) (2.58)
Finite Op-Amp Gain-Bandwidth Product
led on the falling edge of ~I' The previous derivations assumed the op-amp had infinite gain so the one op-amp input
was driven to precisely VCM + Vos while the other op-amp input was held at V CM - Vos.
Op-amp open-loop gain is an important parameter when designing a Sill. Let's write the
open-loop gain of an op-amp, assuming a dominant pole, as
AOLDC V oul+ - V oul
AOl.(f) . f Vin+ - Vin
(2.59)
1 +J'
hay
In nanometer CMOS the DC gain, AOLDC' may be 500 while the j;dB may be 100 kHz
giving a gain-bandwidth product, or unity-gain frequency, of 50 MHz.
The S/H is an example of a feedback system that can be characterized using the
classic feedback equation
AOL
ACL = 1 + AA (2.60)
I-' OL
Since, during the hold operation, all of output signal is fed back to the input P 1 and we
can write, for DC,
AOLDC
ACL (2.61 )
I +AOLDc
the substrate
As the op-amp's open-loop gain becomes veri large the SIB's gain moves towards I. Note
that the closed-loop gain will always be less than the desired value. If, in a mixed-signal
:ial topology.
56 CMOS Mixed-Signal Circuit Chapter 2 Sampling an
circuit, VDD is I-V and a SIH with a resolution better than 1 mV is required, then the or AOLDC > 1,000. We
open-loop gain of the op-amp can be estimated using
VDD Resolution ..!...1_--",0-,-".0,-",0..!...1 < A OLDC
(2.62)
VDD 1 1 + AOLDC We can estirr
frequency /."') Aowc f"d
4.0V
(noting that this assUI
response is first-order)
3.5V
l.OV
~1
2.5V
2.0V
1.5V
1.0V
O.5V
~J
O.OV
(a)
This first-order system
~O,5V
Ons 4ns 8ns 1608 20ns 24ns Clock signals
For a given resolution'
If the settling time mu

2.40 durin~
The minimum gain-bar

(b)
Op-amp outputs
If the VDD in a mixed
and the sampling frequ,
than 210 MHz. If the
240mV op-amp is 210kHz. 0
180mV these minimums.
120rnV
A utozeroing
60rnY
OrnV A single-ended versior

·60rnY referred noise, Vi;lOiseU
·120mY offset voltage. We'n re
·180mY We've already shown it
(c)
·240mV removes the offset v(
Inputs and outputs
+
Ons
'-'-4---~-+--~~~-r----~--~ unity-follower configu
lOOns lOOns 300ns 3500s
switches close the \'011
Eq. (2.57) we can write
Figure 2.40 SPICE simulations of the operation of the SIR in Fig. 2.39
_
Chapter 2 Sampling and Aliasing
.. _-------------------------
57
n 1 m V is required, then the or AOLDC > 1, 000. We can write this equation in a more useful form as
AOLDC> VDD. (2.63)

_< A OLDC ResolutIon
(2.62)
1 + AOLDc We can estimate the required op-amp gain-bandwidth product (unity-gain
frequency ~m) A ow cf3dB' for a SIH by substituting Eq. (2.59) into Eq. (2.60) with ~ = I
(noting that this assumes the op-amp doesn't experience slew-rate limitations and its
response is first-order)
ACL = --'==- (2.64)

1 +j.
or
ACL '" - - - ' - - - : : : (2.65)

I +j . --"--
~3
(a)
This first-order system has a time-domain response given by
Clock signals VallI == VinCI e-I.21t f,m) (2.66)
For a given resolution we can write
m]
Resolution (2.67)
""r""" ~ If the settling time must be faster than half of the sampling clock period Ts (=11fs ), as
~. J seen in Fig. 2.40 during ~3' then we can write
!,Ij~,I
Ts
t settling < 2is 2
(2.68)
The minimum gain-bandwidth product of an op-amp used in a SIH is determined using

(b) -is . In (Resolution)
Op-amp outputs f,un == AOLDC' f JdB > rc (2.69)
---t--~ ..
; 420ns 4100s If the VDD in a mixed-signal system is I-V, the desired resolution of the SIH is 1 mV,
and the sampling frequency is 100 "NlHz then the unity-gain frequency,fun' must be greater
than 210 MHz. If the required DC gain, from Eq. (2.63), is 1,000, then the hdB of the
op-amp is 210kHz. Of course, the actual DC gain and fun should be much higher than
these minimums.
Autozeroing
A single-ended version of the SIB in Fig. 2.39 is seen in Fig. 2.41 including the input
referred noise, Vi~oise(f), power spectral density (PSD with units of V2/Hz) and op-amp
offset voltage. We'll represent the input-referred noise in the time-domain using Vinoise(t).
We've already shown in Ex. 2.3, Eqs. (2.57), and (2.58) that this topology "autozeroes" or
(c)
removes the offset voltage. When the ~I switches are closed the op-amp is in the
Inputs and outputs
~---r----l unity-follower configuration and its inputs move to VC,~f + Vos + Vino/se(t). When the ~J
switches close the voltage on the inputs of the op-amp is VCl..f + Vos + Vino/se(t J)' lJ sing
Eq. (2.57) we can write, assuming tl "" lJ,
fthe SIH in Fig. 2.39
(2.70)
58 CMOS Mixed-Signal Circuit Design Chapter 2 Sampling and J.
to tI t2 h Noise Transfer Function

I 2 ·1 sin IT2
I
Iassuming
~
Vonoise
~I
:=
V mOlse
clock signals h.
~2
~3 a near 50% duty cycle.
Vou!
~3
I
Fig
Figure 2.41 SiH with input-referred offset and noise shown.
In the preceding di
At a time T/2 later, thc ~3 switches open and the ~I switches close again to sample the noise spectrum. However,
input signal and the noise. Writing the charge on CF between t3 and t] +T)2 and weighting the output 1
(2.71 ) Having said this, howev(
band limited to the Nyquis
Qualitatively, we can see that if the noise is moving slowly (e.g., Flicker noise) it is DC tof)2 range (the desin
removed from the output signaL However, fast moving noise isn't subtractcd out during
the autozero process. Ultimately the bandwidth of the circuit (say switch resistances and
capacitors) and op-amp finite bandwidth limit the frequency content of the noise.
(a)
To get a quantitative idea for how the autozero process affects noise in the S/H's
output signal we can write
vout(t) = Vin(t3) + Vinoise(t) - Vinoise(h) for t3 :s; t:S; t3 + Ts l2 (2.72) (b)
Focusing on the noise and taking the Fourier Transform of each side of this equation
gives
.,- Vonoise(f) := Vinoise(f) . (e /2rr!(t-lj) - 1) (2.73)
I
1
Note that when t is close to t3 the output has little noise. The worst case situation is right Desire
I before the ~3 switches open at a time t3 +TJ2 (the ~3 switches are on for T)2 seconds). If
.1_
we look at this worst-case situation only, then Figure 2.4:
(2.74) Correlated Double SampZir

I Correlated Double SampliI
·c which is the transfer function of a differentiator, Sec. 1.2.2. Note how it would be followed by a S/H. The Sir
straightforward to extend this derivation to any arbitrary time that the ~3 switches are on. noise/offset are sampled «
Borrowing the results seen in Eq. (1.46) we get a noise transfer function, NTF, of output signal (the correlati
I offset.
I NTF (2.75)
As an example of (
This equation is plotted in Fig. 2.42 along with the response of the SIH. Note that at DC along with a SiH input and
(where the op-amp's offset voltage is located) the output of the S/H is noise free. As and the input-referred nois
alluded to earlier, autozeroing works well for reducing the effects of Flicker noise (a low offset and noise are alway,
frequency noise that is common in CMOS integrated circuits). input.) While we can see no
OS Mixed-Signal Circuit Desib'1l Chapter 2 Sampling and Aliasing 59
_.-_._---------------------
to 1i t1 13 NOise. Transfer Function i-"...

! I = 2 ·Isin 1l I
Ts I
~l
:l Vono;se
Vlnolse 2
assuming clock signals have I
~2
a near 50% duty cycle.
~~.~ Sample-and-hold with T = Ts
~3
I )
Figure 2.42 The noise transfer function ofa SIH.

and noise shown.
In the preceding discussion we didn't include the effects of sampling on the output
litches close again to sample the
noise spectrum. However, at this point, replicating the noise spectrum at multiples off,
leen 13 and t3 +TJ2 and weighting the output noise by the S/H response should be straightforward, Fig. 2.43.
Vas vinOlse(t» (2.71) Having said this, however, note that if our op-amp's input-referred noise PSD isn't
bandlimited to the Nyquist frequency, //2, as it is in Fig. 2.43 then noise will alias into
slowly (e.g., Flicker noise) it is DC to//2 range (the desired range).
noise isn't subtracted out during
ircuit (say switch resistances and
ncy content of the noise.
process affects noise in the S/H's (a) Bandlimited op-amp input-referred noise spectrum
f
3) for t3 :s; 1 :s; t3 -'- Tsl2 (2.72) . After autozero process
m of each side of this equation
(.'3 (e j27tf(t-t,l - 1) (2.73)

The worst case situation is right Desired spectrum
tches are on for T,/2 seconds). If
Figure 2.43 Example spectrums when 51H in Fig. 2.39 is used.
11 (2.74) Correlated Double Sampling (CDS)

Correlated Double Sampling (CDS) is a name used for describing the autozero process
. 1.2.2. Note how it would be
followed by a SIR The S/H in Fig. 2.39 thus employs CDS. Both the input signal and the
time that the ~3 switches are on.
noise/offset are sampled (double sample). Then the offset/noise is subtracted from the
msfer function, NTF, of
output signal (the correlation) to give an output signal with less noise and ideally no
offset.
(2.75)
As an example of CDS, Fig. 2.44 shows an input-referred noise signal and offset
Illse of the SIR Note that at DC along with a S/H input and output. The op-amp's input referred offset is about -220 mV
ut of the S/H is noise free. As and the input-referred noise has a peak-to-peak variation of about 80 mY. (Remember
.e effects of Flicker noise (a low offset and noise are always measured on the output of a circuit and referred back to its
lits). input.) While we can see noise in the S/H's output it is clear that it has been reduced.
60 CMOS Mixed-Signal Circuit Design I"'\..."~t,'r 2 Sampling and
So why would,
.~.~_ •.__
which is a signi
since the inputs of
driven to a known
VeM) that ensuring good
Note that in a two-stage
diff-amp together so th<
voltage of the (
as is our next topi
Noise and offset. 'ol",.,t,,,,,O' Capacitor Size
Figure 2.44 Showing how CDS reduces noise and offset in the SfH in Fig. 2.39.
Figure 2.45 shows a S/H that doesn't employ CDS. This topology is used to help
ensure the CMFB circuits and biasing in the op-amp are more tolerant to offsets. When
the 4>1 switches are on, the inputs of the op-amp are shorted to the common-mode voltage, Table 2.1 (
VeM' and the outputs are shorted together. Note that the op-amp settling time isn't a factor
in the design during this hold portion of the S/H process. At this point in time we can
write
(2.76)
When the 4>3 switches turn on, the op-amp moves into the follower configuration and the
op-amp inputs move to VCM± Vas. During this time we can write, see Eq. (2.58),
(2.77)
Since charge must be conserved
V oul = V in ± Vas (2.78)
2.46 shows a S/H

I
1
Ql
'"p
4>2 CF and when the 4>3 switches

Vin:+:/ __-ir----<t--1
I
I
I
1
Figure 2.45 Fully-differential S/H differential topology without using CDS. ~~.-------""--~.--.~----~-------..
CF • (Vin VCM ± Vas)

S Mixed-Signal Cireuit Design Chapter 2 Sampling and Aliasing 61
So why would we use this configuration? Neither the offset or noise would be
reduced which is a significant disadvantage over the topology in Fig. 2.39. The answer is
that since the inputs of the op-amp are driven to a known voltage (VCM) and the outputs
are driven to a known voltage via the op-amp's common-mode feedback circuit (again
VCM) that ensuring good biasing and stable CMFB loops in the op-amp is easier to attain.
Note that in a two-stage op-amp design we would also short the outputs of the first-stage
diff-amp together so the inputs of output buffer are forced to a known value (the ideal
output voltage of the diff-amp). Design of fully-differential op-amps is discussed In
detail, as is our next topic, in the book CMOS Circuit Design, Layout, and Simulation.
MV~. Noise and offset. Selecting Capacitor Sizes
~~d
L8~s O.9ps 1.0ps
The selection of the capacitor sizes in the SiR is based on thermal noise considerations,
kTIC (kay tee over cee), and settling time. Small capacitors result in lower power circuits
and faster settling times but, at the same time, increase the thermal noise floor. For a
:et in the SIR in Fig. 2.39. detailed discussion of kTIC noise, as well as other circuit noise topics, see CMOS Circuit
Design Layout, and Simulation. Table 2.1 shows the relationship between various
. This topology is used to help
capacitor sizes and corresponding thermal noise for quick reference.
more tolerant to offsets. When
1 to the common-mode voltage, Table 2.1 Capacitor size and corresponding kTiC noise at 300 OK.
-amp settling time isn't a factor
!
'. At this point in time we can Capacitor I JkTIC, IlV JkTlC, mV
size, pF RMS peak-to-peak
i
(2.76) 0.01 I 640 3.84

follower configuration and the 0.1 i 200 1.2
11 write, see Eq. (2.58), 1 64 0.384
Vas) (2.77) 10 I 20 0.12
ILIOO
1
i
6.4 0.038
(2.78)
2.2.2 The 5tH with Gain
Figure 2.46 shows a SiR with gain. Following the derivations from the last section we
can write
'l ~, fC L
T
and when the ~J
Q~~ =: CI' (Vin
switches tum on
VCM± Vas )+ . (Vin VCM± Vas) (2.79)
A Qr
Vout+
J
= c/, (VCM VCM Vas) (2.80)
Vout-
~CL and
~3
Q~: =CF'(VoUi Vcw =Vas) (2.81 )
Knowing charge must be conserved
Qp = '(VOIII VCM Vas)

QF~I
19y without using CDS. ,-----.. ~-----" ,--~- .. -~~- .. --~ ,---~- .. -~
CF'(Vin-VC~f±VOS) -'eCI (Vin-VC\1±Vos)- CI,(VCM VCM±VOS) (2.82)

600mVr
500mVl··· .. ·
4oomVT· .. · ..
30omv-'",'~
2oomvJ ..
100mVr-f· ..
v
OmV --.--
·IOOmV ...... ·
·200mV~ .. · .. -
I .
~300mV ..... -
I .
·400mV- .. ··":
.50omv) ....... :
-600mv-I----i
Ons 501
Figure 2.48
Figure 2.46 A S/H with gain.
or We'll see later, when cove

subtraction in the S/H. Co
V oul (1 + ~J 'Vin- ~;. VCM (2.83) plates of the C1 capacitors
2.49). Doing this results in
For a fully-differential topology the last tenn is common to both the inverting and
non-inverting inputs ofthe S/H so we can write
or, after reviewing Egs. (2.
(2.84)
A block diagram for the S/H in Fig. 2,46 is shown in Fig. 2,47. Note that this op-amp
topology employs CDS. Also note, though we didn't derive it in the last section (because
it ends up being negligible in most circuits), the residual offset after autozeroing is
VosIAoLDC. An op-amp DC gain of 1,000 and an op-amp offset of 50 mV results in a 50 Vout = Vouf+
j..lV residual offset when employing CDS.
1 v," ---J, S!~ ~. --~> V OU1

_1
1 +_C_,
CF
I
"1
Figure 2.47 Block diagram for the SIH of Fig. 2.46.
"1
Example 2.4
Simulate the operation of the data converter S/H building block shown in Fig. (Partial
2,46. Assume C1 = CF = 1 pF and Is 100 MHz.
The simulation results are shown in Fig. 2,48. The gain, as we would expect, is 2.
It may be useful at this point to simulate this circuit with an offset or noise like we
did in Ex. 2.3 .• Figur
; Mixed-Signal Circuit Design Chapter 2 Sampling and Aliasing 63
$3
i
TCL
~
l Vout+
V OUl
I~CL
- I
Figure 2.48 Simulating the SIR seen in Fig. 2.46 with a gain of2.
Implementing Subtraction in the SIH

We'll see later, when covering Nyquist-rate data converters, that it is useful to implement
subtraction in the SiR. Consider what would happen if instead of connecting the bottom
- . VCM (2.83) plates of the C1 capacitors in Fig. 2.46 to VCM we connect them to VCl+ and VCl_ (see Fig.
CF
2.49). Doing this results in
lon to both the inverting and
Qt 3
= CI' (VCI+ VCM± Vos) (2.85)
~)
or, after reviewing Eqs. (2.82) - (2.63)
. (Vin+-Vin-) (2.84)
( CI)
Vou!+ ~ 1+ C • Vjn+ - C • VCI+ (2.86)
g. 2.47. Note that this op-amp F F
e it in the last section (because The differential output voltage is then given by
ual off'let after auto zeroing is
offset of SO mV results in a SO Voul = Vuu/+ Vout = (1 + (2.87)
If Fig. 2.46.
iIding block shown in Fig.
1, as we would expect, is 2.
th an offset or noise like we
Figure 2.49 implementing subtraction in the S/H.
Rearranging the block diagram seen in Fig. 2.49 results in the topology seen in Fig. 2.50.
::!~~
.... 2.rl
D.W . . /
O.OY ...... ; ..
Vow
:::~~~lIt:::::::"
3V
-O.4V
-tl· I··· .: .
... , ..
-o.SY ....... ;..
-n.SY ....... ; ..
-O.7Y ....... , ..
-O.BV ......-: ..
-O.9Y ....... j ..
Figure 2.50 Block diagram of Fig. 2.49 with bottom plates ofC/ tied toVC/.
·1.0Y+----+--
Oos 50ns
Example 2.5
Simulate the operation of the SIH shown in Fig. 2.51 i(t; 100 MHz, CF = C1 = I
Single-Ended fo Differem
pF, VCl+ = 1.5VCM> and VC1 _ is O.5VCM (VCM= 500 mY). Comment on the resulting
output.
Many input signals are sing
is desirable in the first sta.
. change it into a fully-dif
differential converter will 1::
distortion (important). In 0
seen in Fig. 2.53. Agai
the $1 switches are on)
Vin+ Q;~ total = C]

VCl+ Vout+
VCI- Vout-
Vin
noting that the charge on th.

capacitors. The charge on tr
1-
Figure 2.51 S/H used in Ex. 2.5.
,-1
The simulation results are shown in Fig. 2.52. We only show the situation when
we would want to subtract Vc ",/2 from the differential input signal. The inputs are
fully-differential, swinging around the common-mode voltage of 500 mV with an
l
amplitude of 100 mV (so they swing between 600 mV and 400 mY). The largest
$2
Vin+ .. ~- - - .
differential voltage is 600 mV ~ 400 mV or +200 mV while the smallest
, differential signal is 400 mV 600 m V or ~ 200 m V (so the differential signal
1-
swings around ground with an amplitude of 200 mY). Reviewing the block
diagram in Fig. 2.50 with the values in this problem shows that the circuit takes
this input signal, sample-and-holds it, subtract VCM!2 (250 mY) then multiplies it
by 2. We've scaled the output in Fig. 2.52 to show that this sequence of events is I
L
indeed what is happening. Note that if we were to switch VCl_ and VCI_ we would
add VCM!2 to the input signal. • Figure 2.5
S Mixed-Signal Circuit Design Chapter 2 Sampling and Aliasing 65
he topology seen in Fig. 2.50.

V/VootpJNfvoutmJ
1 plates ofC] tied toVCI.

Ons 50ns lOOns 15005 lOnns 25005 :mOns 350ns 4000s 4500s 500ns
Figure 2.52 Simulation results for Ex. 2.5.

I, 100 MHz, CF = C[
A Single-Ended to Differential Output SIH
Comment on the resulting
Many input signals are single-ended, meaning the (one) input signal swings around VCM• It
is desirable in the first stage of the mixed-signal circuit to SIH the signal and then to
change it into a fully-differential signal for further processing. A good single-to
/
differential converter will hold the op-amp's input common-mode voltage at VCM for low
distortion (important). In order to meet this goal consider the modified, from Fig. 2.46,
SIH seen in Fig. 2.53. Again, we can write, (noting the CF capacitors are uncharged when
the ~I switches are on)
Qi,~.tolal=CI+·(Vin VCMtVOS)+Cf~·(VCM VCMtVOS) (2.88)
--,---Vvut+
When the ~l switches turn on the charge on these two input capacitors is
--I-'---Vout~
J: CL
J
Q1 =2C/.(v2n VCMtVOS)
noting that the charge on the C[ capacitors (half ofEq. [2.89]) redistributes through the
(2.89)
capacitors. The charge on the feedback capacitors is then

Q~J 2CF'(Vo!lI-VC~ftVOS) (2.90)
5.
ly show the situation when

input signaL The inputs are
voltage of 500 mV with an
, and 400 mV). The largest ~2
V in+ ~-----r----I Cf+
o mV while the smallest Vout+
, (so the differential signal VCM ~. ./ ;~3
•
C~
_1--_.._---1 +
:1
---...>---- VOUI~
1V). Reviewing the block ~2 I
;hows that the circuit takes
~I
250 m V) then multiplies it <----'----"'"
t this sequence of events is
tch VC[+ and VCl_ we would
Figure 2.53 S/H for single-ended to differential conversion.
Equating the redistributed charge through C F and C1

~l
C 1+· (Vin+ VCM ± Vos) CF • (VOllf+ - VCM ± Vos) + C 1+· (v;+ - VC\f± Vas)
(2.91 )
or
Vin+
CF'(VOUf+- os == C1+'2
VCM± V) (2.92)
Assuming C1+ = C1_ and taking the difference in the SIR outputs gives
(2.93)
Note that this topology doesn't employ correlated double sampling (CDS). Also note that
if we model the op-amp's offset with a single voltage source in series with the
n-l
non-inverting input of the op-amp then one of the inputs will go to VCM + Vos 12 while the n -1/2
other input will go to VCM - Vosl2 (we've just indicated the inputs of the op-amp are at a
potential of V CM ± Vos). Rence the factor of two in Eq. (2.93). In other words, if we
Figure 2.54 S
re-write all of the equations in this chapter by replacing Vas with Vas 12 then the factor of
two in Eq. (2.93) will go away. Simulations at CMOSedu.com are invaluable to
To begin, let's assu
understanding the operation of the circuits in this chapter. For example, see the
~] switch. When the ~I
simulation for Fig. 2.53.
shut off), the char
2.2.3 The Discrete Analog Integrator (DAI)
The final sampling circuit we'll discuss in this chapter is an analog building block that we
will find useful in implementing our data converters using feedback. The discrete analog and the output of the integI
integrator, DAI, is shown in Fig. 2.54. The two clocks signals, ~J and ~2' form ;,.,;;",?:c",;;stored on C 1 becomes
nonoverlapping clock signals. The common mode voltage, VCM ' falls halfway between
the mixed-signal system's high- and low-reference voltages (generally VDD and ground).
Note that the parasitic capacitance to ground associated with the bottom-plate of C1 is remembering that the Op-a!
charged back and forth between v] and v2 but doesn't affect the amount of charge in these charges, Q2 - QI ,
transferred to the feedback capacitor, Cr For this reason this DAr is often called a a~ou,tput voltage change. 1
parasitic-insensitive integrator. (vQut[nTsJ vout[(n

Table 2.2 shows the various relationships between the possible inputs and outputs writing this equation in t
for the DAI of Fig. 2.54. Let's derive the input/output relationships for the most general
situations where both v] and v2 are the inputs.
,
-,
Table 2.2 Discrete analog integrator (DAI) input/output relationships.
The transfer function of the
Input
VI = input and V2 == VCM
Similarly, if we connect th,
shift in time by Ts!2) \
[OS Mixed-Signal Circuit Design Chapter 2 Sampling and Aliasing 67
(2.91)
Vout
VI
..-, Vin4
~'+'2
(2.92)
V2------------------~
outputs gives VCM

-1kBottom
plate
[I 2 Fos] (2.93) (the plate closest
to the substrate)
! sampling (CDS). Also note that
)
rage source in series with the t
n-l n
\vill go to VC\{ + Vas /2 while the
n-1/2
the inputs of the op-amp are at a
q. (2.93). In other words, if we
Figure 2.54 Schematic diagram of a discrete analog integrator (DAl).
Vas with Vas/2 then the factor of
\10Sedu.com are invaluable to
chapter. For example, see the To begin, let's assume the output of the DAr is connected to the op-amp through
the ~I switch. When the ~I switches are closed (~l is high) at n 1 (the instance when the
switches shut off), the charge stored on C, is
(2.94)
an analog building block that we
ng feedback. The discrete analog and the output of the integrator is vout[(n -l)Ts]. When the ~2 switches turn on the charge
locks signals, ~I and ~2' form stored on C1 becomes
ige, VCM ' falls halfway between (2.95)
ges (generally VDD and ground).
d with the bottom-plate of C, is remembering that the op-amp holds its noninverting input terminal at VCM' The difference
l't affect the amount of charge in these charges, Q2 Ql, is transferred to the op-amp's feedback capacitor resulting in
ison this DAI is often called a an output voltage change. This change can be written as
(vouf[nTs]-vOI/([(n-l)TsDCF== C,(vl[(n l)Ts] v2[(n 1I2)]Ts) (2.96)
TI the possible inputs and outputs
or writing this equation in the z-domain results in
elationships for the most general
VoutCz)(l-zl)== ~~(VI(Z)'Z-I V2(Z)' (2.97)
ut/output relationships.
The transfer function of the DAr with the output connected to the ~I switches is then
IOutput connected to ~2 VOl/f(Z) == (2.98)
Similarly, if we connect the output through the ~2 switches (the edges we label n in Fig.
2.54 shift in time by Ts12) we can write
QJ = C/(VCM vl[(n 1I2)Ts]) (2.99)
Q2 CICVCM - v 2[nTs]) (2.100)
and
(2.101) capacitors as indicated in

analog and is interfaced t{
The transfer function of the DAI with the output connected to the <\12 switches is then ADe) and DACs (v2(z] is
_C1.VJ(z), -V2(Z)
VOlll ()
z - C. 1 __ -I (2.102) It should be clea
'r ~
combinations of discrete
Note that ifv2(z) V CM , this equation can be written as other possibilities. In part
each plate so there is no
H(z) = VOl/feZ) • ~ (2.103) function of this DAI is
vJ(z) CF l-z-J
which has a frequency response, IH(!)I, shown in Fig. 1.27. Note that the factor C1ICF
simply scales the amplitude response. If this factor is unity then the magnitude response,
as shown in Fig. 1.27, is 0.5 at 1s12. The Z-1I2 term in the numerator simply modifies the each input signal ~
phase response of the DAI (delaying the output by T sl2 or -180 degrees) and has no .... ~,."'r,h <\11 controlled switl
effect on the magnitude response. Note that at this point we could discuss the frequency are used. If the integrator
responses of the transfer functions given in Table 2.2. However, we would see that the have asymmetric parasitic
discussions and results given in Ch.l for the digital integrator would apply to the DAT tunctl()ll is
with little, or no, modifications.
Example 2.6
Determine the transfer function of the DAI of Fig. 2.54 without the switches on noting the input signals ca
the output of the op-amp. discussed further in the ne)
Reviewing Fig. 2.54 we see that charge is transferred to the feedback capacitor DAI
only when the <\12 switches are closed. Therefore, the output only changes states
during the time interval when the <\12 switches are closed. The transfer function of
the DAI, when no switches are used on the output of the op-amp, is given by Eq.
(2.102). Using the <\11 switches simply adds a half clock cycle delay, Z·112 , to the
integrator's transfer function (instead of the output changing with the rising edge
of <\12' the output changes one-half cycle later on the rising edge of <\11)' •
A Note Concerning Block Diagrams
As we draw block diagrams describing our modulator topologies in this chapter and the
next we often show a circuit like the one shown in Fig. 2.55. The summation, gain, and
integrating blocks are implemented with a single switched-capacitor DAI having the
,, transfer function given by Eq. (2.102). The gain, G, of the DAI is set by the ratio of
,,
,
Di_screte analog integrator
Figure 2.55 Block diagram of a DAI.

(2.101) capacitors as indicated in the figure. It's important to realize that this circuit is entirely
analog and is interfaced to, in general, both ADCs (vout[z] is connected to the input of an
) the CP2 switches is then ADC) and DACs (v2 [z] is eonneeted to the output of a DAC).
(2.102) It should be clear from both Fig. 2.S4 and Table 2.2 that many different
combinations of discrete analog building bloeks are possible. Figure 2.S6 shows two
other possibilities. In part (a) the capacitors used have the same parasitic capacitance on
each plate so there is no benefit to using a parasitic insensitive topology. The transfer
(2.1 03) function of this DAI is
7. Note that the factor C1ICF VOU1(Z) = C· -J . (V2(Z)- VI (z)) (2.1 04)
F l-z
then the magnitude response,
umerator simply modifies the noting each input signal sees the same delay, i.e., Z-I when the outputs are connected
)r -180 degrees) and has no through CPI controlled switches and delay when no switches or CP2 controlled switches
3 could discuss the frequency are used. If the integrator inputs must see the same delay and the capacitors available
Never, we would see that the have asymmetric parasitic capacitance, the topology of Fig. 2.S6b can be used. Its transfer
'ator would apply to the DAI function is
. (Cll . VI(Z)+ Cn . V2(Z)) (2.1OS)

Cp CF
:J. without the switches on noting the input signals can be scaled independently (a useful feature in filter design and
discussed further in the next chapter).
to the feedback capacitor Fully-Differential DAJ
utput only changes states While we've derived the equations governing the operation of the DAI using a single
I. The transfer function of ended topology, in most practical cireuits we'll use fully-differential implementations.
e op-amp, is given by Eq. The same equations apply to both configurations. Figure 2.S7 shows the schematie for the
: cycle delay, Z-112 , to the fully-differential DAI. Note how we keep the bottom plates of the capacitors away from
Iging with the rising edge the op-amp's inputs.
g edge of cp,).•
(a)
.logies in this chapter and the
5S. The summation, gain, and
!d-capacitor DAI having the
Ie DAr is set by the ratio of
C1 VI(Z)' Z-I12 V2(Z)

Z) CF' l-z- 1
\1. Figure 2.56 Other fonns of DAIs.

READING
V2+ CF R. J. Baker, CMOS
Vl+--/
~1
:CI
I ;J Edition, Wiley-IEEE.
C. C. Enz and G. (
T Op-Amp Imperfectio
-t
/"
VCM ; Stabilization," Proc(
~ ::r Vou/ November 1996.
VI_--~
'CI 1. W. Couch, Mod,
~
Prentice-Hall, 1995. I
CF
V2
C 1 . v I (z) . z1I2 - V2(Z)
VOUI(Z)
l-z- 1
Qualitatively, using f
CF
an alias of the sample
Figure 2.57 Fully-differential discrete-analog integrator (OAI) implementation. Re-sketch Figs. 2.12
logic to implement th
DAI Noise Performance
Explain why retumin
Figure 2.58 shows the DAI with kTIC noise sources shown (see Table 2.1). The mean a signal. What is the \
squared input- referred noise is given by
Sketch the input and
(2.106) the DC component oj
4 MHz with a peak
in series with both VI and v1 . A total of 2kTICI is sampled onto C1 during each clock cycle. MHz.
If the input signal can swing from VDD to ground (peak value of the input is VDDI2
while the RMS value of this input is VDD!(2.fi ) ), then we can estimate the SNR using
f \ In Sample and
VDD/~2.fi ) hold (S/H)
SNR = 20 log -;::::===- (2.107)
This equation is useful for determining the capacitor values used in a DAI.
~1
Repeat Ex. 2.2 with a

Re-sketch Fig. 2.22 jJ
content).
Suppose we are intefl
interpolation what i
interpolation what is
Sampled onto C1 when ~l switches close.
interpolator's output c
Sampled onto C1 when ~2 switches close Verify, with simulatic

Determine the transft
Figure 2.58 Noise performance of the OAI.
paths of the switched
ADDITIONAL READING
[l] R. 1. Baker, OvIOS: Circuit Design, Layout, and Simulation, Revised Second
Edition, Wiley-IEEE, 2008. ISBN 978-0470229415
[2] c. C. Enz and G. C. Temes, "Circuit Techniques for Reducing the Effects of
·---Vaul+ Op-Amp Imperfections: Autozeroing, Correlatcd Double Sampling, and Chopper
+ Stabilization," Proceedings of the IEEE, Vol. 84, No. 11, pp. 1584-1614,
/ " ' ' ' + - - - Volll- November 1996.
[3] L W. Couch, Modern Communication Systems: Principles and Applications,
QUESTIONS
:z) 2.1 Qualitatively, using figures, show how impulse sampling a sinewave can result in
an alias of the sampled sinewave at a different frequency.
. (DA1) implementation. 2.2 Re-sketch 2.12 and 2.13 when decimating by 5. hint: use a counter and some
logic to implement the divide by 5 clock divider.
2.3 Explain why returning the output of the S/H reduces the distortion introduced into
m (see Table 2.1). The mean a signal. What is the cost for the reduced distortion in a practical circuit?
2.4 Sketch the input and output spectmm for the following block diagram. Assume
(2.106) the DC component of the input is 0.5 V while the AC component is a sinewave at
4 MHz with a peak amplitude of 100 m V. Assume the clock frequency is 100
lto C[ during each clock cycle. MHz.
value of the input is VDDI2
: can estimate the SNR using
In Sample and Sample and Sample and Out
hold (SIB) hold (SIB) hold (SIH)
107)
clock
used in a DAI.
Figure 2.59 Figure used in Question 2.2.
2.5 Repeat Ex. 2.2 with an input sinewave at 30 MHz.

2.6 Re-sketch Fig. 2.22 if the input signal is a sinewave at 10 MHz (no other spectral
content).
2.7 Suppose we are interpolating, with K = 8, digital data with!, = 100 MHz. Prior to
interpolation what is the frequency range of the desired spectmm? After
interpolation what is the frequency range of the desired spectmm? What is the
interpolator's output clock rate?
when $2 switches close 2.8 Verify, with simulations, that the topologies seen in Fig. 2.34 are equivalent.
2.9 Determine the transfer function, and verify with simulations, the behavior of 4
.e DAl.
paths of the switched-capacitor topology seen in Fig. 2.36.
2.1 0 In your own words discuss why the ~2 switches are shut off after the ~, switches in
the S/H seen in Fig. 2.39.
2.11 Sketch the op-amp's open loop response, both magnitude and phase, specified by
Eq. (2.59).
2.12 What is the voltage across CH in Fig. 2.41 in terms of the input-referred offset and
noise? Verify your answer with simulations commenting on the deviation of the
frequency behavior of the input-referred noise to the frequency response of the
voltage across the capacitor.
2.13 Provide a quantitative description of how capacitor mismatch will affect the
operation of the StH seen in Fig. 2.46. Verify your descriptions with simulations.
nalog F
2.14 Is it possible to design a SIH with a gain of 0.57 How can this be done or why
can't it be done? Use simulations to verify your answer.
2.15 For the first entry (v, input, v 2 = VCM) in Table 2.2 derive the frequency response,
magnitude and phase, of the DAr. Use simulations at a few frequencies to verify
your derivations. the last chapter we disc[
(RCFs) are an imr
2.16 Repeat Question 2.15 for the second entry. pertonm signal processing
2.17 Repeat Question 2.15 for the third entry. RCFs are still require
wider bandwidths)
2.18 Does the DAr use CDS? Why or why not? Use simulations to support your sWltclled-caLpa1c\t()r) counte
answers. cannot be fabricate.
,"~~}"'''l<'L' y true if passive n
±20%. By using activ.
elements, we can e
order filters while IT
I'
I I In this chapter Wt
I integrators (CArs or acti'
I
.......
capacitor (gm-C) integrator:
I practical analog filters f(
I'
I
fully-differential inputs ant
the active filter remains co
. signal using fully-differen
outputs. Single-ended tope
such as Sallen-Key, and
, inversion such as Tow-Th.
I
and Schaumann [2].
I,
3.1 Integrator Buildi

,
, 3.1.1 Lowpass Filters
III order to methodically
lowpass filter shown in Fig
\10S Mixed-Signal Circuit Design
are shut off after the ~l switches in

Chapter
magnitude and phase, specified by
IDS of the input-referred offset and

Iffimenting on the deviation of the
to the frequency response of the
3
Lpacitor mismatch will affect the
lUr descriptions with simulations .
Analog Filters
.5? How can this be done or why
answer.
2.2 derive the frequency response,
ions at a few frequencies to verify
In the last chapter we discussed that analog anti-aliasing filters (AAFs) and reconstruction
filters (RCFs) are an important component of a mixed-signal system. While we can
perform signal processing and filtering in the digital domain, as seen in Fig. 2.1, AAFs
and RCFs are still required in our system. Analog continuous-time filters can be faster
(have wider bandwidths) and take up less area than their analog discrete-time (e.g.,
Use simulations to support your switched-capacitor) counterparts. However, unlike discrete-time filters, continuous- time
filters cannot be fabricated with precise transfer functions and must be tuned. This is
especially true if passive resistors and capacitors are used. Each one can have a variation
of ± 20%. By using active CMOS integrators in the filter implementations instead of
passive elements, we can electrically tune the filters. Also, we can more easily implement
higher order filters while minimizing the effects of loading.
In this chapter we discuss analog filters made using continuous-time analog
integrators (CArs or active-RC integrators), MOSFET-C integrators, trans conductor
capacitor (gm -C) integrators, and discrete-time analog integrators (DAIs). Our focus is on
practical analog filters for mixed-signal AAFs and RCFs. These filters may have
fully-differential inputs and outputs so the common-mode voltage of the op-amp used in
the active filter remains constant (important for noise and distortion). Further, inverting a
signal using fully-differential topologies is trivial since we simply swap the filter's
outputs. Single-ended topologies where the op-amp's common mode voltage can vary,
such as Sail en-Key, and topologies that require separate amplifiers to generate an
inversion such as Tow-Thomas biquad, are covered in the excellent books by Franco [1]
and Schaumann [2].
3.1 Integrator Building Blocks

3.1.1 Lowpass Filters
In order to methodically develop our understanding of CMOS filters, consider the
lowpass filter shown in Fig. 3.1. The transfer function of this filter is
V oul (J) = _--"'-_ (3.1)
Vin(J) 1 +j(f)RC
74 CMOS Mixed-Signal Circuit Design Chapter 3 Analog Filter!
3.1.2 Active-RC Inte,

f3dB ~ 2rrRC
A continuous-time, full)
'goes by other names, in
o dB -+----'---<i----~~ f (Hz)
.the resistors are replace.
Vour(J) I integrators. The gain of'
IVin(J)
/ vour(J) ,
1m .c..-- I
V in(J) 0 i--"""-~
- 45 - - - - - - ~ - - - -, -
90 - - - -: - - - - : - - - "'"-- - -
s plane I O.113dB' lOf3dB

Vin+-
s cr +jro
Vin--
Figure 3.1 First-order lowpass filter.
where ro 2n -f andfis the frequency of the input (and thus the output). Next, consider
the block diagram in Fig. 3.2. This figure shows an integrator and a summing block. The
output of the block diagram can be determined by solving Figu
(3.2) Reviewing Fig. .

or needed integration but
feedback path, the entire
(3.3) the integrator-based im
Vin(J) l+sIG op-amp must be able to
where for a sinewave input s :; jro. Comparing this equation to Eq. (3.1), we see that if we because the RC is used
I set the integrator's gain, G, using several practical and us(
, work an example before
G :; where f3dB :; G (3.4)
RC 2n
we can use an integrator to implement a lowpass first-order filter (the filter has a single
pole).
I
1
1 Vin+
Out
f---~-........-~-- voU/(J)
Vin-
, Integrator
1
Figure 3.2 Block diagram of an integrator-based lowpass filter.

Figure 3.4
; Mixed-Signal Circuit Design Chapter 3 Analog Filters 75
3.1.2 Active·RC Integrators

j ~ 2rcRC
A continuous-time, fully-differential, analog integrator (CAl) is seen in Fig. 3.3. The CAl
_ _- - - - - - ) 0 . f (Hz) goes by other names, including the Miller integrator, the active-RC integrator, and when
the resistors are replaced with MOSFETs operating in the triode region, the MOSFET-C
integrators. The gain of the CAl can be written as
G
r-'---,
Vout = V Oul+ -V oUl- I

(3.5)
ViII Vin+ - Vin = S· RC
IOf3dB
Vin+----.j
Vin-----v' 1'---<1'---1+ VOU/~

ter. R
Switched so gain is
lUS the output). Next, consider positive
ttor and a summing block. The
Figure 3.3 A continuous-time analog integrator (CAl).
(3.2)
Reviewing Fig. 3.2, we see that the CAl of Fig. 3.3 alone will implement the
needed integration but not the summing (difference) block. By adding an additional
feedback path, the entire block diagram of Fig. 3.2 can be implemented. Figure 3.4 shows
(3.3) the integrator-based implementation of the circuits in Figs. 3.1 and 3.2 (noting the
op-amp must be able to drive a resistive load). This filter is called an active-RC filter
1 to Eq. (3.1), we see that if we because the RC is used with an active element (the op-amp). At this point there are
several practical and useful modifications that we can make to this filter. However, let's
work an example before moving on.
Q (3.4)
2rc
er filter (the filter has a single
Vout
?"'-_.-- VOUl+
VOUl+ Active-RC filter.
LSed lowpass filter.

Figure 3.4 Implementation of a first-order lowpass filter using a CAL
Example 3.1
Simulate the operation of the filter in Fig. 3.4 from DC to 100 MHz if R 10k
and C = 10 pF. Show both the magnitude and phase responses of the filter.
It's important to notiee (fe
Assume the op-amp is ideal.
the voltages are first chanl
on the inputs of the op-am
From Fig. 3.1 we know the 3 dB frequency of the filter is 1.59 MHz. The
simulation results are shown in Fig. 3.5. The magnitude and phase response
follow, as expected, the responses for the simple RC filter shown in Fig. 3.1. •
the block diagram iJ
that at DC where s
diagram with the forward
from classic feedback thee
3.6, R/Rr Of course, all
capacitor is an open result:
» (
I
r
I
I
Figure 3.5 Magnitude and phase responses for the first-order filter in Fig. 35.4
ifR= 10k and C IOpF.
.- What would happen if we switched what we define as Vout+ and Vout- in the filter
described in Ex. 3.1 without changing any other connections? Perhaps it is trivial, but the
Vin+
answer is that the output will be inverted. We can modity the block diagram of Fig. 3.2 by
simply mUltiplying the output by -1, as seen in Fig. 3.6. The phase shift in Fig. 3.5 would
. shift up or down by 180 degrees. It would vary from 180 to 90 degrees, or from -180 to
-270 (because +180 degrees is the same as -180 degrees) instead of from 0 to -90
degrees. If we allow the resistors used in the filter to have different values, as seen in Fig.
3.6, we can add a feedback gain to our block diagram. Assuming the outputs are labeled
so that we don't have an inversion in the output of the filter (i.e., they are labeled as seen
in Fig. 3.4), we can write
d-Signal Circuit Design Chapter 3 Analog Filters 77
Vin You! = (3.6)

R, RF 1/sC
DO MHz if R = 10k
lonses of the filter. It's important to notice (for later use) that in order to subtract the output from the input,
the voltages are first changed to currents and then summed (or more correctly subtracted)
on the inputs ofthe op-amp. This equation can be rewritten as
is 1.59 MHz. The
md phase response You, RJ
wn in Fig. 3.1. • -= (3.7)
Yin l+sR F C
Using the block diagram in Fig. 3.6, we can write
_Vo_ut = --=-"-..,.- and hdB (3.8)

Yin 1+ 21t
Equating coefficients in these equations results in

RJ
O2 -R and 0, (3.9)
F
Note that at DC where s ~ 0, the block diagram in Fig. 3.6 becomes the classic feedback
diagram with the forward gain approaching infinity and a feedback factor of O2, Then
from classic feedback theory, the closed-loop gain becomes 1/02 or, for the filter in Fig.
3.6, R/R r Of course, analyzing this circuit (using loop equations) at DC when the
capacitor is an open results in the same gain.
Integrator
Switeh for inversion

see Fig. 3.4
. filter in Fig. 35.4 c

_1_
R/ RIC
,"1+and V OU1- in the filter Vin+
R/
rhaps it is trivial, but the
R/ RF
:k diagram of Fig. 3.2 by Vin~
,e shift in Fig. 3.5 would 0102
iegrees, or from -180 to
f 3dB=~
stead of from 0 to -90
nt values, as seen in Fig.
g the outputs are labeled
they are labeled as seen
Figure 3.6 Integrator-based first-order filter.
78 CMOS Mixed-Signal Circuit Design Chapter 3 Analog Filters
Example 3.2
or, with A OLe!) Wunfs
ModifY the filter in Ex. 3.1 so that the low-frequency gain is 20 dB.
Using Eq. (3.7) or Eq. (3.8), we leave C = 10 pF and RF = 10k. To get the gain of
10, we make R[= lk. The simulation results are shown in Fig. 3.7 .•
This equation is very re,
can be in a filter. For the
the i term in Eq. (3.14
VOUl(j) I
I v;n(j)
Example 3.3
Suppose a first-order
Figure 3.7 A first-order filter with gain, see Ex. 3.2. where Wun 10IRFC
how the magnitude aI
Effects ofFinite Op-Amp Gain Bandwidth ProductJ"" op-amp,!,,".
In the previous two examples we assumed a near-ideal op-amp. The open-loop gain of the The op-amp's unity g;
op-amp can be written, assuming a dominant-pole compensated op-amp, by the filter. This means
equal to the desired b,
Vaul
Ao[.(j) v+ -v. = (3.10) circuit is fun 11 0, wl
1I2rr.R F C. The magnit
I where v+ and V. are the voltages on the noninverting and inverting op-amp input
I ' terminals, respectively. Note that we are using hdB in both Figs. 3.6 and Eq. (3.10) to
1
indicate the 3 dB frequency of a frequency response. While the symbol is the same the
...
I
actual values vary from circuit to circuit. When a practical op-amp is operating at which shows the filter
frequencies above a few kHz, we can approximate the open-loop response (knowing the
imaginary part of the denominator is much larger than the real part) as The point of the
I minimize the effects of tb
1-' A (j)_AOWC·/3dB _fun 2rr.fun Wun (3.11) be used. In the remaini
I OL - jf - j S s
approximated as
I where!,," is the frequency where the op-amp's open loop gain is unity (0 dB). Rewriting
1
. Eq. (3.6) to include the op-amp's finite gain bandwidth product (that is,!,,") and assuming,
...
without the loss of generality, that the op-amp is operating with a single-ended output (v+
tied to VCM [AC ground]), results in The poles of this transfer·
.
Vin V-+Vaul v-+SC'(Vaul-V_) 0 (3.12)
RJ RF
After some algebraic manipulation with v. -V au/fA OLC!), we get
noting that if Wun ~ 00, th
VaUI = -----_-.::'-----;----:: (3.13) Fig. 3.1).
Vin
1+
Desired response
xed-Signal Circuit Design Chapter 3 Analog Filters 79
or, with AOL(f) = O)"nls

20dB.
(3.14)
lOk. To get the gain of
g. 3.7.•
Vin
+ s· [ CR F + "L (I + ~;) ] + 1
This equation is very revealing and shows just how significant a limitation the op-amp
can be in a filter. For the moment, to simplify things, let's assume 0)2 « O)unlCRF so that
. the S2 term in Eq. (3.14) is negligible. We can then write the magnitude and phase
responses as
I I
vo.ut
Vm
(3.15)
Example 3.3
Suppose a first-order filter is designed based on the topology seen in Fig. 3.6,
~x. 3.2. where O)"n = 10IR F C and RFIR/ 10. Assuming 0)2« O)unICRF, comment on
how the magnitude and phase responses of the filter will be affected by the finite
op-amp,fun'
The open-loop gain of the The op-amp's unity gain frequency is only 10 times larger than the bandwidth of
op-amp, by the filter. This means the op-amp's closed-loop bandwidth (with a gain of 10) is
equal to the desired bandwidth of the filter. The bandwidth of a gain of lOop-amp
(3.10) circuit is / un I10, which here is equal to the ideal filter 3 dB frequency of
1I2rr.R F C. The magnitude of the filter's response can be approximated as
I inverting op-amp input RF
igs. 3.6 and Eq. (3.1 0) to

Ie symbol is the same the
I I= b + [0).R;2CR
Vout
Vm F]
2
and L V;ut = -tan- 1 [0). 2CR F ]
In
lop-amp is operating at
which shows the filter's 3 dB frequency is off by a factor of2.•
,op response (knowing the
,art) as The point of the preceding example is, in general lowpass filter design, to
fun _ O)un minimize the effects of the op-amp's finite fun a low value of closed-loop DC gain should
- S (3.11 ) be used. In the remaining discussion let's assume RdRJ = I, so Eq. (3.14) can be
approximated as
is unity (0 dB). Rewriting
(that is, j~n) and assuming, (3.16)
1 a single-ended output (v+
The poles of this transfer function are located at

(3.12) ± J(CR F )2 -4 CRF
CR F.y (Olm
Spl,p2 (3.17)
set
noting that if O)"n --'t 00, then Spl 00, and Sp2 = -lICRF (the ideal position of the pole, see
(3.13) Fig. 3.1).
To get some idea of the required op-amp fun «(flun 2rr/ul1), let's assume that we
want the pole to vary no more than 1% from the ideal location due to finite op-amp
bandwidth
it
v_ _
This can be rewritten as

(3.18)
,,]I -l
1.01 (3.19) l(
If we let x = CO un . CR F , then we need to solve

x-Jx2-4x =2.02 (3.20) Figure 3.8 SPICE mod~
knowing x is positive and much larger than one (co un » lICR F ). Solving Eq. (3.20) for x,
results in x = 100. This means the op-amp's unity gain frequency must be 100 times larger transitions to 40 dB/de
than the filter's hdB in order for the variation of this frequency (the pole) to deviate less closed-loop pole com
than 1% from the ideal. If we can withstand a 10% decrease in the filter's cutoff looking only at the IT:
frequency, then /"n need only be 10 times larger than the filter's hdB' Clearly, from Eq. rolls off faster) in a 10
(3.14), the first-order filter's frequency response is actually second-order when the highpass filter, for exa
op-amp's gain bandwidth product fun is a factor. Therefore, the shapes of the magnitude filter's 3 dB frequency
and phase responses will deviate from the ideal first-order shapes seen in Fig. 3.1. We can we are doing here is ~
draw two very practical conclusions. First, even if it were possible to fabricate precise than the filter's affecl
resistor and capacitor values, the limitations of the op-amp's finite bandwidth may still response starts to fall ,
require the use of tuning when filtering with active-RC integrator-based filters. Tuning fun' of 10 MHz. Also
would consist of adding or removing resistors and capacitors to adjust the precise filter op-amp's (closed-loop)
cutoff frequency (adding/removing the elements using either fuses or, if possible, fun' results in the fi nal J:
MOSFET switches). Second, the op-amp's f.m should be at least 10 times larger than the
I i cutoff frequency (hdB) of the filter (again assuming a closed-loop DC gain of unity, Le.,
I RF /R J = 1). This is a general "rule-of-thumb." Precision filters (well-defined magnitude
. and phase responses) would require wider bandwidth op-amps. Consider the following
I example.
~: 1' ' 'i'

I ~
Example 3.4 -lOdS --- •.:.
Repeat Ex. 3.1 if an op-amp is used with a DC gain of 10,000 and an /"n of 10 ·15dB ..• _+
-20dB .. _..,
MHz.
-25dB -... -~.
Because the op-amp's AOLDC is 10,000 and fun = 10 MHz, the op-amp's open loop -30dSJ-.·-:-·
hdB is 1 kHz (see Eq. [3.11]). We can use the circuit shown in Fig. 3.8 in our J
SPICE simulation to model an op-amp with finite fun' The RC in Fig. 3.8 is
selected to give an op-amp open loop hdB of 1 kHz.
:::::8
::::::
-----r
-45dB
-5UdS -.-._;-
. The 3-dB frequency of the filter described in Ex. 3.1 is, under ideal conditions, -55dB .
I 1.59 MHz. Because our op-amp's unity gain frequency is only 10 MHz, we would 10KHz
expect, from Eq. (3.16), the op-amp to affect the frequency response of the filter.
Fil:,'Ure 3.9 shows the simulation results using the op-amp model of Fig. 3.8. Figure 3.9 Magnit
Comparing Fig. 3~9 to Fig. 3.5, we see differences in both the magnitude and ifR=j(
phase responses of the filters. The magnitude response of Fig. 3.9 initially rolls off frequer
at 20 dB/decade below the ideal 1.59 MHz. Around 10 MHz the response
l-Signal Circuit Design
I, let's assume that we

Chapter 3 Analog Filters
~ _ _ _ _ Vo+
81
-
. due to finite op-amp
(3.18) !
op-amp outputs
(3.20)
Figure 3.8 SPICE modeling of a differential input/output op-amp with finite bandwidth.
olving Eq. (3.20) for x,
lUst be 100 times larger transitions to 40 dB/decade. Clearly this faster roll-off is the result of the op-amp's HAl
Ie pole) to deviate less closed-loop pole coming into play. The limiting behavior of the op-amp, when
e in the filter's cutoff 'dt
looking only at the magnitude response, may be welcome (the filter's response
hdB" Clearly, from Eq. rolls off faster) in a lowpass filter. However, it is not welcome in other filters (a tar
econd-order when the highpass filter, for example). Figure 3.10 shows what happens if we decrease the
lapes of the magnitude filter's 3 dB frequency to 159 kHz by increasing the resistors used to lOOk. What
;een in Fig. 3.1. We can we are doing here is showing how making the op-amp's bandwidth much larger J-c
ble to fabricate precise than the filter's affects the frequency response of the circuit. The magnitude th'
:te bandwidth may still response starts to fall off at -40 dB/decade at the op-amp's unity gain frequency,
)r-based filters. Tuning 1: of 10 MHz. Also seen in Fig. 3.1 0 is the phase response of the filter. The
adjust the precise filter ~;-amp's (closed-loop) phase response, which starts rolling off one decade below
fuses or, if possible, fun' results in the final phase shift of the filter approaching -180 degrees.•
o times larger than the
) DC gain of unity, i.e.,
,veil-defined magnitude
-20 dB/decade
Consider the following
o· -40 dB/decade
00 and anJ,m of 10
op-amp's open loop I I

Vow
V in
LI I
Vout
V;n
m
,e
1 in Fig. 3.8 in our
n
RC in Fig. 3.8 is
h
ler ideal conditions,
10 MHz, we would
sponse of the filter.
model of Fig. 3.8. Figure 3.9 Magnitude and phase responses for the fir~t-order filter in ~ig. 3:4 ,t
the magnitude and if R= 10k and C= 10 pF using an op-amp With a 10 MHz umty-gam n
3.9 initially rolls off frequency. 1<
MHz the response
v
I
82 CMOS Mixed-Signal Circuit Design Chapter 3 Analog FilteJ
Figure 3.11
-20 dB/decade
-40 dB/decade The size of the integrat
converters or modulate
Figure 3.10 Increasing the resistance to lOOk and replotting Fig. 35.9. stored in the capacitor u
In order to model the effects of op-amp finite bandwidth on an active-RC filter's

frequency response, we can add a pole to the ideal transfer function. Assuming unity gain
in the passband (see Eq. [3.3]) results in Equation (3.23) can the1
Undesired
~.--'"----.
Vout(j) _I_ SNR"" 10· logE

---"" (3.21 )
Vin(j) l+slG I +jL
fun
This equation can also t
This result could have been used in the previous example to predict how the op-amp Practically, DRs appro£
affects the filter's behavior. If the filter has gain (> 1) in the passband, see Eq. (3.8), we good polysilicon resisto
can modifY this equation to read diffused or implanted n
Undesired
~--"---,
assuming 500 MHz!.m 0
(3.22) 3.1.3 MOSFET-C Inte

Let's now look at a vari
For a higher order filter we would multiply the desired frequency response by the MOSFETs. Figure 3.12
'.J
I I undesired term's (the op-amp's) response for each op-amp used in the circuit. Clearly, this as resistors they must re
I..J triode operation. Becau
I . limits the order of the filter (limits the number of op-amps used in a circuit; a first-order
filter uses one op-amp, a second-order filter uses two op-amps, etc.). This is especially governed directly by tl
I '
I, true if the filter has a passband approaching the h" of the op-amps used. However, the linearity
I' possibility that the MO
I~ Active-RC SNR response because of the
I;
Consider the single-ended active-RC filter shown in Fig. 3.11. Let's assume an ideal large input signals, the
•
I' with DRs ofaround onl)
I ' op-amp with a maximum RMS output voltage of VDDI(2/2). The RMS input-referred
I noise of the filter, assuming thermal noise dominates over the bandwidth of interest, is the active-RC filters.
I
I. simply j kTIC . The filter's SNR can then be written as We might be qu
I: only 40 dB. Clearly this
I
VDDI(2/2) VDD 2 /8 of resolution or less (36
SNR = 20 . log jkTIC = 10 . log kTIC (3.23) big benefit of this filter
active-RC filter required
in parallel or series wit
-Signal Circuit Design Chapter 3 Analog Filters 83
c
+2:: "--"'1
Vout
/I.
VDD ___ _
+-20'
:r
itj
-40'
-60'
-80'
; -100'
V~_-----J+
R
VCM
1 .
I
VDD
VDDi2- --
; -120'
j -140'
i -160'
~ -180' Figure 3.11 Estimating maximum possible SNR of an active-RC filter.
: -200'
OMHz
The size of the integrating capacitor fundamentally sets the SNR in integrator-based data
converters or modulators. But consider the following: the maximum electrical energy
Ig Fig. 35.9. stored in the capacitor used in an integrator is
on an active-RC filter's Maximum electrical energy !c. (V~D) 2 (3.24)

n. Assuming unity gain
Equation (3.23) can then be rewritten as
\2
!C( VDD) .
2
SNR 10 .10 VDD /8 == 10 . Iocr 2 2 == 10 .10 Electrical energy (3.25)
(3.21) g kTIC e kT g Thennal energy
This equation can also be used to estimate the fundamental dynamic range, DR, of a filter.
redict how the op-amp Practically, DRs approaching 90 dB (IS bits) can be attained using active-RC filters with
band, see Eq. (3.8), we good polysilicon resistors (to avoid the large nonlinear voltage coefficient associated with
diffused or implanted resistors) and linear capacitors. Bandwidths approaching 50 MHz,
assuming 500 MHz!.. op-amps are used, can be attained (at, of course, lower DRs).
(3.22) 3.1.3 MOSFET-C Integrators

Let's now look at a variation of the active-RC filter where the resistors are replaced with
lency response by the MOSFETs. Figure 3.12 shows a MOSFET-C filter. In order for the MOSFETs to behave
the circuit. Clearly, this as resistors they must remain in the triode region. Using long length devices helps ensure
n a circuit; a first-order triode operation. Because the MOSFETs are operating as resistors, their speed is not
etc.). This is especially governed directly by their gate-source voltage (overdrive voltage) or channel length.
used. However, the linearity of the MOSFET resistors is still very important, as is the
possibility that the MOSFETs will introduce a parasitic pole into the filter's frequency
response because of the distributed resistance/capacitance of the channel (Fig. 3.12). For
Let's assume an ideal large input signals, the active MOSFET resistors become nonlinear, resulting in filters
'he RMS input-referred with DRs ofaround only 40 dB. The bandwidth of the MOSFET-C filters parallels that of
andwidth of interest, is the active-RC filters.
We might be questioning the usefulness of the MOSFET-C filter with a DR of
only 40 dB. Clearly this filter will only find use in data conversion systems using six bits
2/8 of resolution or less (36 dB DR) or in systems that process continuous-time signals. The
(3.23)
C big benefit of this filter over the active-RC filter is its ability to be tuned. Tuning the
active-RC filter required adding or removing, via switches or fuses, resistors or capacitors
in parallel or series with the existing resistors and capacitors. Tuning the MOSFET-C
84 CMOS Mixed-Signal Circuit Design Chapter 3 Analog Filte
Vtul1e
MOSFET-C filter
Vin+
Vin+----'
Vin-
Knowing Vin+ = -Vin

current through MI as
One over the slope of

this line is the MOSFETs
resistance The result is that the ne
changing drain-source
implementation of a firs
~.~--.-~-~-.-~ )
Drain-source voltage Inverted channel Parasitic
resistance channel
capacitance
Figure 3.12 A first-order MOSFET -C filter.

[
filter shown in Fig. 3.12 can be accomplished by adjusting ~une' If we assume
long-channel behavior, we can write the resistance of the MOSFETs in terms of VIII"e Vin+
(assuming the input common-mode voltage of the op-amp is 0) as
Rn= / (3.26)
KP \' lv,"", - V ~l
[
mN -
The current through MI in Fig. 3.12 is
Ii";;
Vin+
= Vin+ . KP . L • lune -
W(U V THN - Vin+
) (3.27)
Figure 3.14 Firs
Some improvement in the linearity of the MOSFET resistors, say 10 dB (resulting in a
I DR of 50 dB), can be achieved by utilizing the fully-balanced signals available in the Why Use an Active Circu
I circuit. Consider replacing MI in Fig. 3.12 with the pair of MOSFETs, MIA and MlB,
I,
shown in Fig. 3.13. The resulting current is now Before going any furth
performance using a sim]
Vin+ Vin- KP W[ (V (3.28)
-R +-R = . -L Vin+' lune+ use these elements with
nlA niB
question comes when we
the output of the filter (Wl
»:ed-Signal Circuit Design Chapter 3 Analog Filters 85
MOSFET-C filter
- VouJ.·~
V OUl+
Vin------....l
MIB
Figure 3.13 Linearizing MOSFET resistors.
G
Knowing Vin+ = -Vin and letting V tune V tune+ - V rune -, we can write the equivalent
current through MIas
Vin+ . KP· LW . Vwne (3.29)
~~\
The result is that the nonlinear behavior of the MOSFET's channel resistance due to the
changing drain-source voltage cancels to a first order. Figure 3.14 shows the
implementation of a first-order MOSFET -C filter using linearized MOSFETs.
\
I channel Parasitic
ce channel
capacitance
r.
ing Vrune ' If we assume

)SFETs in terms of VlUne
IS
(3.26)
:J
Vin+) (3.27)
Figure 3.14 First-order MOSFET -C filter using linearized MOSFET resistors.
say 10 dB (resulting in a
j signals available in the
Why Use an Active Circuit (an Op-Amp)?
)SFETs, MIA and MIB,
Before going any further, let's realize that we can get the exact same frequency
performance using a simple resistor/capacitor or MOSFET/capacitor as we get when we
(3.28) use these elements with an op-amp. So, "Why use the op-amp?" The answer to this
question comes when we realize that when a capacitive or resistive load is connected to
the output of the filter (without an active element), the frequency behavior changes. Using
86 CMOS Mixed-Signal Circuit Design Chapter 3 Analog Filten
the op-amp allows us to drive an arbitrary (within reason) capacitive or resistive load. Before discuss in,
Using an active element will also allow us to cascade first-order sections to implement of gm-C filters; namely,
higher order filters. precision application, tl
associated with the amp
3.1.4 gm-C (Transconductor-C) Integrators
be held at a precise valli!
The operational-transconductance amplifiers, aTA, is an amplifier that has only two is not too useful if use,
high-impedance nodes: the amplifier's input and its output. Figure 3.15 shows a schematic resolution is less than t
symbol, transfer curves, and a possible implementation for an OTA (based on a continuous-time signal p
fully-differential diff-amp). Transconductor-C, or g",-C, filters use a circuit, a
We can relate th(
transconductor, that provides a linear voltage-current transfer curve. Our aTA in Fig.
circuit in Fig. 3.15a usinl
3.15 does behave like a transconductor over a portion of the input voltage range but
becomes nonlinear for large input voltage differences, Vin+ - Vin-. By increasing the
lengths of the NMOS diff-pairs used in the aTA, we can increase the linear
common-mode range of the aTA, making it appear as though it were a transconductor. Comparing this result to
The fundamental problems with increasing the lengths of the diff-pair MOSFETs are the
increase in the OTA's input capacitance (affecting the location of the filter's poles and
zeroes) and, perhaps more fundamentally, the inherent reduction in the MOSFET's/r-
The big benefit of the gn
by adjusting the transcon
The circuit of Fig
Fig. 3.3. However, as set
Vin+
first-order filter. In order
Vin ( consider the transconduc
Vin+ - Vin transconductor is gm(Vin,
the second transconductc
(a) Schematic symbol of an OT A
3.l6b, the outputs of th
or transconductor. (b) Transfer curves for an OTA. trans conductor subtract.
we can write
VDD
T-=r~
I '
...;
I;
! '1 ~s;io.ut+ Voul+
I:
I:
I ,
Vin+ r------~ t-- Vin-
,-,
I!
L--+---'~-<I-~
I'
I'
I
I'
~I-'
: I (c) One possible implementation
: I of an OTA.
!I
.I
Figure 3.15 Showing an implementation of an OTA and transfer curves.

Figure 3.]6
d-Signal Circuit Design Chapter 3 Analog Filters 87
.citive or resistive load. Before discussing these issues in more detail, let's look at an important limitation
r sections to implement of gm-C filters; namely, the fact that the transconductor's input voltage must vary. In any
precision application, the input voltage must remain constant because of the roll-off
associated with the amplifier's CMRR (unless, of course, the common-mode voltage can
be held at a precise value). This limits the DR ojgm -C filters to around 50 dB. Again, this
ifier that has only two is not too useful if used as an antialiasing or reconstruction filter unless the system's
3.15 shows a schematic resolution is less than eight bits (48 dB SNR). The gm-C filter finds extensive use in
an OT A (based on a continuous-time signal processing.
ters use a circuit, a
We can relate the input voltage difference to the output voltage difference for the
urve. Our OTA in Fig.
circuit in Fig. 3.15a using
input voltage range but
v in-. By increasing the (3.30)
Vout+ VOIII == j(f)C
an increase the linear
: were a trans conductor. Comparing this result to Eq. (3.5), we can use the same design techniques if we require
f-pair MOSFETs are the
of the filter's poles and G _1_ == gm or j3dB =Q (3.31)
n the MOSFET'sjr RC C 211:
The big benefit of the gm-C filter over the active-RC filter is the ability to tune the filter
by adjusting the transconductor's gm'
+ iout-
The circuit of Fig. 3.15a implements an integrator, as does the active-RC circuit of
Fig. 3.3. However, as seen in Fig. 3.2, we also need to implement a summing block in a
first-order filter. In order to move toward the goal of implementing the summing block,
consider the transconductor circuit shown in Fig. 3.16a. The output current of a single
Vin+ -Vin transconductor is gm(Vin+-Vin-). We can sum this current with the output current from
the second transconductor to implement the summing block in Fig. 3.2. As seen in Fig.
3.16b, the outputs of the two OT As are combined, so the output currents from each
;urves for an OT A. transconductor subtract. Assuming each transconductor has the same transconductance,
we can write
(3.32)
Vin
Switched for subtraction
Vjn+ r---\--1'--:>"-<p---- vDut

ssible implementation c
TA. Vl n :,.'-----,/.--e-_+_-- V out+
(b)
ransfer curves.
Figure 3.16 Implementing a first-order filter using transconductors.
or
V out+ - V out-
(3.33)
Vin+ V;n 1 +J<roC . ...L
g",
If the transconductors have different gms, we can design a filter with a DC gain (see
Problem 3.10), which can be characterized using Eq. (3.8).
Example 3.5
Repeat Ex. 3.1 using a gm-C filter with agm of 100 IlAN.
To simulate a transconductor using SPICE, a voltage-controlled current source
can be used as seen in Fig. 3.17. In order to set the output common-mode voltage
to VCM in the simulation, we add the large resistors (whose values can be changed
to simulate the finite, nonideal, output resistance of the OTA) connected to VCM" If
we didn't use these resistors, after reviewing Fig. 3.16, it would result in an F
unknown common-mode voltage on the second transconductor input.
loops. Figure 3.19 shows
components to provide th
r---*------""-Vou/+
Vin+ vinp
V in- --:-.---\....''J
vmm
'WE ________ '--_---..",.---Vou/
SP~ , which is the same result af
G 1 voutm voutp vinp vinm lOOu
~ VCM
Notice how SPICE defines positive current flow as current
flowing from the + terminal to the- terminal
Figure 3.17 Modeling an ideal transconductor in SPICE using a voltage-controlled

current source.
• 1..:
I .
In order to have the same time constant, and thus pole location, as in Ex. 3.1,
,:
I '
let's set the capacitor value, in the schematic of Fig. 3.16 to 10 pF. The value of
the transconuctance, lIgm , is 10k. The simulation results are shown in Fig. 3.18. Figure 3.19 Sl
",-,, As we would expect, the shape follows, exactly, that of the active-RC filter in Fig. th
,,
'
'
3.5. Also, although not shown, the phase response matches as welL.
A High-Frequency Transc
Common-Mode Feedback Considerations
, A transconductor, Fig. 3.:
In most OTAs the load capacitance is used for compensation. These capacitances common-mode range of
compensate both the normal, forward, differential signal path as well as the CMFB path. increased as we discussec
Reviewing Fig. 3.15, we see that the capacitance in part (a) indeed does provide a load for location of the parasitic p<
differential signals. However, any signal that is common to both outputs (a circuit, that other than the
common-mode signal) doesn't cause a displacement current to flow through the capacitor. of nodes: the input and th{
Because both sides of the capacitor change at the same rate for common-mode signals, sum with the load capacita
the change in voltage across the capacitor is zero. This can result in unstable CMFB
~ed-Signal Circuit Design Chapter 3 Analog Filters 89
(3.33)
ter with a DC gain (see
:rolled current source

ommon-mode voltage
ralues can be changed
.) connected to VeM' If
It would result in an Figure 3.18 Simulation results for Ex. 35.5.
or input.
loops. Figure 3.19 shows how we would break the capacitor in Fig. 3.15 up into two
components to provide the same loading for differential and common-mode signals. We
can write
Vout+ . . -Vout
l/jm2C = loul+ == loul- l/jm2C (3.34)
ioul+ == gm(Vin+ - Vin-) i oul- (3.35)

t 100u
Voul+ - V oul- _ gm
Vin+ - Vin- - jmC (3.36)
L-_----..--- Voul-
which is the same result as Eq. (3.30).
VeM
[lg a voltage-controlled
:)cation, as in Ex. 3.1,

) 10 pF. The value of
e shown in Fig. 3.18. Figure 3.19 Showing how we break the capacitor up to provide a load for
.ctive-RC filter in Fig. the CMFB circuit.
swell. •
A High-Frequency Transconductor
A trans conductor, Fig. 3.20, can be implemented using inverters. To increase the input
:ion. These capacitances common-mode range of the transconductor, the lengths of INVI and INV2 can be
; well as the CMFB path. increased as we discussed for the diff-amp seen in Fig. 3.15. This, again, lowers the
~d does provide a load for
location of the parasitic poles introduced into the transconductor's response. Note, in this
m to both outputs (a
circuit, that other than the power supplies and the tuning voltage, there are only two sets
ow through the capacitor. of nodes: the input and the output nodes. This allows the transconductor's capacitances to
,r common-mode signals,
Sum with the load capacitances and be tuned out.
'esult in unstable CMFB
90 CMOS Mixed-Signal Circuit Design Chapter 3 Analog FiltE
Vtune In
I Vine/) ---,)0-)
Inverter power supply ~ ~
.
Vin+--{50
INVl [ ~
~l~ I
V aUf-
Vin-
Figure 3.20 High-frequency transconductor.

Figure 3.2
3.1.5 Discrete-Time Integrators
Let's consider using a discrete-analog integrator, DAI, discussed in the last chapter to
implement a first-order filter. The output of a DAI with two delaying inputs is Example 3.6
Sketch the implemc
VOUI(Z) C1
(3.37) with characteristics
V)(Z)-V2(Z) CF I z-)
Ifwe apply the filter's input to the noninverting input of the DAI and feed the output back The schematic of
to the subtracting input, see Fig. 3.21, we get clocking frequency
pF, the size of the i
(3.38) 10k, I pF. The 3 dI
Vin(Z) VOUI(Z) Because of the tim(
we can write, see Eqs. (1.62) and (1.66) analysis for the SPI'
filter at 1.59 MHz
I== C· I n DOl f,
2 Isin ny;
C1 1 dL
Iv In
Vout
-v oul F
1.1 an
Voul
. -v out ==
v In -nf,-s -"2 or < < s (3.39) peak-to-peak). The'
The sampling frequency (the frequency the discrete-time filter is clocked at) is is ' while
the filter's input frequency is labeled.! If we require I «Is (say at least sixteen times less
so sin nis "" nis),then we can rewrite Eq. (3.39) as
(3.40)
where
1
G z;--R and iJdB 2n (3.41 )
F sc
placing the gain of the integrator in the same form as Eqs. (3.4). The variable Rsc is a
switched capaeitor resistor
R Ts (3.42)
sc == C1 Is == C1
The equivalent block diagrams for first-order filters using CAIs and using the DAIs
(again assuming! «is) are compared in Fig. 3.2l. Figure 3.22 A switct
Ked-Signal Circuit Design Chapter 3 Analog Filters 91
r []
In Out (!)
Vine!) ) )to ) ) Vout
Integrator
i
(a) C] .J,
G CF S
V OU (- I
"
In Out
Vine!) Vou/(f)
Vout+
Integrator
(b)
,r.
Figure 3.21 Block diagram of an integrator-based lowpass filter.

(a) Continuous-time and (b) the discrete-time equivalent.
sed in the last chapter to
'lying inputs is Example 3.6
Sketch the implementation of a DAI-based (switched-capacitor), first-order filter
- (3.37) with characteristics like the one in Ex. 3.1. Use SPICE to simulate the design.
1
I and feed the output back The schematic of the filter is shown in Fig. 3.22. Here we are assuming the
clocking frequency of the filter is 100 MHz. If the feedback capacitance, CF' is 10
pF, the size of the input capacitor, C/. is then, from Eq. (3042) and knowing Rsc is
(3.38) 10k, 1 pF. The 3 dB frequency of the filter is, once again,1I2n:RscCF 1.59 MHz.
Because of the time-domain (clock) component of the filter, we can't use an AC
analysis for the SPICE simulation. Let's apply a 1 V peak-to-peak sinewave to the
filter at 1.59 MHz and verifY the output of the filter is 3 dB down (0.707 V
: for 0 <I<.Is (3.39) peak-to-peak). The results are seen in Fig. 3.23.
n ~ Indicates plate
is clocked at) is J, , while 10V closest to the
I at least sixteen times less
,-----1 substrate
··--VoUI
(3040)
'----------i+
r G .Is 100 MHz

3dB = 2n: (3 AI)
104). The variable Rsc is a
)
(3.42) 1
:Als and using the DAIs

Figure 3.22 A switched capacitor, first-order filter similar to the one described in Ex. 3.1.
92 CMOS Mixed-Signal Circuit Design Chapter 3 Analog Filt(
The impiementatic
Filter inp_u_t~:,..,,:~_v"..:t--; _ Filter output

O.1V t -
O.6VJ- ----i--- --
The DC gain, as SI
filter's 3 dB freque
:'::JJ ' .. ,
o.zv - ---+---- -;-- Note that the DAI 1
0.1'1 -- --+-.----: ---
0.0'1 ---i- --i:..;:,..L-i----i---r-'-L--i--i------i---'Lj---.
o.o~s O.2~s O.4~s O.6~s O.8~s 1.0~s l.~~s 1.6~s 1.8PS~~s
-
1.2ps
Figure 3.23 Output of the switched-capacitor circuit in Fig. 3.22.
Let's comment on the exact transfer function of the DAI in Fig. 3.22. We see
in Fig. 3.22 that the output is indeed fed back to the input through a ~l controlled
switch. The result is that the output, through the feedback loop, sees one clock
cycle delay, Z·l. The output is assumed settled on the falling edge of ~2 during
each clock cycle. Because of this, the input, which is settled on the falling edge of
~l' sees only a half clock cycle delay, Z·I!2. This means that the DAI in Fig. 3.22
really has a transfer function of
(3.43)
If we think of the input signal arriving a half-clock cycle earlier, then the only
difference in the transfer function here, when compared to the continuous-time
equivalent and assuming!« is, is a small phase difference. We can delay the
input signal a full clock cycle by adding a q,l controlled switch on the output of the
Figure 3.2!
filter. However, because this switch may be part of the next filter section, we don't
discuss this option further.
The big benefit
Example 3.7
and zeroes are determir

Sketch the switched-capacitor implementation of the discrete-time lowpass (first
is often a precise frequ

order) filter shown in Fig. 3_24.
clocking frequency ca
(changing the filter's ch
the 90 dB range have b(
In
Vin(f) --~--{ + I-~----I .9J. Out
s I---:--"-~--- Vout(j) In the previous 1
with the potential alias
input of the filter. An ~
must be used to remo
noise-shaping modulate
the sampling frequency
relaxed AAF design. In!
Figure 3.24 General implementation ofa lowpass first-order filter. the switched input capa
switched-capacitor filtel
:d-Signal Circuit Design Chapter 3 Analog Filters 93
The implementation is seen in Fig. 3.25. The coefficients are

Cn
Filter output G 1 == C ·Is and G2 == -C -is' G (3.44)
F F 1 Cll
The DC gain, as seen in Eq. (3.8) is set by the ratio of Cn to C n (l/G 2 ), and the
filter's 3 dB frequency is
: . • • • .J
G1G2 (3.45)
/3dB=-
FZ] 21t
Note that the DAI used in this filter has a transfer function of
[J
Ips 2.0ps
. [Cll . vm(z) . Z1I2 ~~. Vout(z)] (3.46)
I Fig. 3.22. •
in Fig. 3.22. We see
'Ough a 4J 1 controlled ~l 4J2
oop, sees one clock
g edge of 4J2 during
.n the falling edge of
VCM---,-\ .
C
I \~-<!'~_l---l
. VCM
Vin----t--~ II T_ ''----t-_-+----j
--VOUl
he DAI in Fig. 3.22
(3.43)
artier, then the only

the continuous-time
e. We can delay the
. on the output of the
Iter section, we don't Figure 3.25 Implementation of the block diagram shown in Fig. 5.24.
The big benefit of switched-capacitor-based filters is the fact that the filters' poles
-time lowpass (first- and zeroes are determined by a ratio of capacitors and an external clock frequency (which
is often a precise frequency set by a crystal oscillator). No tuning is needed. Varying the
clocking frequency can precisely set the filter's characteristics for adaptive filtering
(changing the filter's characteristics on the fly). Switched-capacitor filters with SNDRs in
the 90 dB range have been attained at audio frequencies.
Out
~ vou,(J) In the previous two examples we used ideal op-amps and didn't concern ourselves
with the potential aliasing resulting from the analog sample-and-hold operation on the
input of the filter. An analog antialiasing filter, AAF, (that is, not a discrete-time filter)
Vout(f)
- - - == --"--::- must be used to remove the potential aliased signal prior to sampling. As with the
Vin(J) noise-shaping modulator-based data converters we'll study later in the book, the fact that
the sampling frequency, J" is much larger than the input frequencies of interest allows a
relaxed AAF design. Indeed, the resistance of the MOSFET switches used combined with
·order filter. the switched input capacitance (CI ) form a lowpass filter. This filtering may serve as the
switched-capacitor filter's AAF in many designs.
An Important Note Figure 3.27 show

filter. Remembering that
If we pause for a moment and think about the filters we have covered in this chapter we
period off. or one comple
come to the realization that all require precise analog components. High-speed,
response to the filters in tl
wide-bandwidth op-amps and/or components with precise matching or absolute values
write, from Eq. (3.41),
are needed. We might argue that this would be a reason to focus our discussion on digital
filtering (filters using only multipliers, delays, and adders) instead of filters using analog
components. However, digital filters can't alone filter an analog waveform without first
running the signal through an ADC. Further, traditional digital filters that use We can write the magnitu
general-purpose multipliers at reasonable speeds can be very large (take up a significant
layout area). They can be so large in fact as to not be practical in a general purpose
filtering application. Special-purpose chips have been fabricated specifically for digital
filtering (called digital signal processors, DSPs).
3.28 shows the r.
The noise-shaping topologies that use oversampling, discussed later in the book, attenuation of the filter Q(
can reduce the requirements placed on the analog components in the circuit. Isn't it 0.0526 or - 25.6 dB.
logical then to attempt to combine noise-shaping with purely digital filtering for the
design of analog interfaces? The answer is obviously, "yes"; however, as mentioned
above, we have some caveats. While the resulting interface will place lower demands on
the precision of the analog circuitry, we'll need to develop digital filters that don't rely on
complex multipliers. The multiplications we do use should be simple, perhaps requiring
an additional adder, or trivial (shift) mUltiplication. Also we'll need to use the digital
filters to not only filter the input signal but to filter out the modulation noise present in
the output of the NS modulator. Again these topics are discussed in much greater detail
later in the book.
Exact Frequency Response ofan Ideal Discrete-Time Filter
Figure 3.26 shows an equivalent diagram for Figs. 3.21a and 3.21 b. We have replaced the
ratio of capacitors, C[ICp , with the variable A in the figure. To determine the transfer
function we can write
Figure 3.27 The L
discr.
vou,(/) =A· [Vin(/) vOIII(f))' I -I (3.47)
-z
or 3.2 Filtering Topoll
In this section we present
(3.48) on continuous-time analo
z-(l-A)
3.2.1 The Bilinear Tral
Consider the block diagr
Integrator relate the filter's output to
VoutU)
...
I,
Out
I:
I
Figure 3.26 Digital block diagram of an integrator-based discrete-time lowpass filter. This filter's transfer fum
functions. Using this to
,ed-Signal Circuit Design Chapter 3 Analog Filters 95
Figure 3.27 shows the z-plane plot and magnitude response for this first-order
filter. Remembering that all discrete-time filters have a periodic frequency response (a
overed in this chapter we
period off, or one complete revolution around the unit circle), we can compare this filter's
omponents. High-speed,
response to the filters in the previous examples. To do so, let's assume fs 100 MHz and
:ching or absolute values
write, from Eq. (3.41),
: our discussion on digital
:ad of filters using analog
g waveform without first
f3dB ~' = 1.59 MHz "" 0.1 . Ig~ MHz that is, A= 0,1 (3.49)
digital filters that use We can write the magnitude response of Eq. (3.48), with z = cos 2nfl/S + j sin 2njifs , as
rge (take up a significant
cal in a general purpose A
(3.50)
~d specifically for digital J(cos2njlj~ -1 +A)2 +sin2 2rrfifs
Figure 3.28 shows the responses of the first-order discrete-time filter. The maximum
,cussed later in the book, attenuation of the filter occurs at f,12 or 50 MHz here and is, from Fig. 3.27 with A 0.1,
Its in the circuit. Isn't it 0.0526 or - 25.6 dB.
J digital filtering for the
; however, as mentioned H(z) A

I place lower demands on z-(l-A) z-plane
11 filters that don't rely on
simple, perhaps requiring IHU)I
.1 need to use the digital
>dulation noise present in
ed in much greater detail
~ •••
2-A I )
31s12 f
,lb. We have replaced the
[0 determine the transfer
Figure 3.27 The z-plane representation and magnitude response of a first-order

discrete-time filter.
(3.47)
3.2 Filtering Topologies

In this section we present some basic filter building blocks using integrators. Our focus is
(3.48) on continuous-time analog implementations ofthese filters.
A)
3.2.1 The Bilinear Transfer Function
:"
pator
~ ~,
VOUI(f)
Consider the block diagram of the general first-order filter shown in Fig. 3.29. We can
relate the filter's output to its input using
Voutif) (3.51 )
r
: Out
,
s
VOuf(f)
I +1.iG;"
---= (3,52)
I+ G,sG
2
:ete-time lowpass filter. This filter's transfer function is termed "bilinear" because it is the ratio of two linear
functions. Using this topology we can implement lowpass, allpass (used for phase
while the filter's zero is I(
The filter's gain at DC, in
Active-RC Implementatio
The active-RC impleme
Again, as mentioned earl
repeatability from one p
fsl2 on-ehip, with fuses (or s'
the summation is impler
3dB currents are summed a
OdB
common-mode voltage,
-3dB
switehed-eapacitor imp Ie
-6OB
-!ldB We won't discuss
dB VB log of -12dB function. It should be ob'
frequency -15dB linearized MOSFETs (set
-lUdB
-21dB
-2~dB
-27dB
-lOdB
10KHz 100KHz lMHz 10MHz 100MHz
fsl2 3fs12
Figure 3.28 The magnitude response of the discrete-time first-order filter

of Fig. 3.26 with an A of 0.1.
shifting), and highpass filters (keeping in mind that the highpass filter will ultimately
Vjn - - - _ . _ - -......... 1
change into a bandpass filter response because of the op-amp's or transconduetor's high
frequency rolloff). The location of the filter's pole is given by
(3.53)
In Out
Vjn({) --+--+--1 i-----clo>--+--+--- Vout({)
Figure 3.30 1m
Transconductor-C Implef
- Figure 3.31 shows tht
transconductor stages. A
Figure 3.29 Implementation of a bilinear transfer function using an integrator. currents. Summing the cu
~d-Signal Circuit Design Chapter 3 Analog Filters 97
while the filter's zero is located at

-:J1 Continuous-time
? f i l t e r response !ldB.zero = 2rcG (3.54)
3
"'-=9 The filter's gain at DC, in all cases, is

-~,
(3.55)
Active-RC Implementation
The active-RC implementation of the bilinear transfer function is seen in Fig. 3.30.
Again, as mentioned earlier, the resulting active-RC transfer function suffers from poor
repeatability from one process run to the next. The RC time constants must be tuned,
on-chip, with fuses (or switches) and adding/removing resistors or capacitors. Note how
rs the summation is implemented by changing the input/output voltages to currents. The
o· currents are summed at the inputs of the op-amp (which remain, ideally, at the
-10'
common-mode voltage, VCM)' This is important to note in both the active-RC and
-140'
switched-capacitor implementations.
-210'
-280' We won't discuss the implementation of the MOSFET -C-based bilinear transfer
-350' function. It should be obvious that replacing the resistors in Fig. 3.30 with MOSFETs or
-420' linearized MOSFETs (see Figs. 3_12-3.14) provides a MOSFET-C implementation.
-490'
-560'
RF
CI
3fs12
first -order filter

RI
Vin+
~,----- V Olll
lSS filter will ultimately +

or transconductor's high V in- VVv"--__--1+ ·-Vout+
RI
G j =_1_
RICF
(3.53) I
CI G2 =:: RI
RF
G3 RICI
Figure 3.30 Implementation of an active-RC bilinear transfer function filter.
Transconductor-C Implementation
Figure 3.31 shows the implementation of the bilinear transfer function using
transconductor stages. Again, as with the active-RC filter, signals are summed using
using an integrator. currents. Summing the currents at the output nodes results in
98 CMOS Mixed-Signal Circuit Design Chapter 3 Analog Filter:
V.,,+ Vout+ _ Voul+ 0

gml ( Vin+ V m ) - gm2 ( Vout+ - Vout ) + l/s2C l/s2Cz (3.56)
l
where we know Vout+ = -Vout- and Vin+ = -Vin-. It will be helpful to write
~ (3.57)
I/s2C) IIsC) I/sC)
Using this expression, we can write Eq. (3.56) as
(VO!lf+ Vout-)' (s(C) + C 2)+ gm2) = (Vin+ Vin-)' (gml +sCJ) (3.58)
or finally
Vaut+ - V out-
Vin+ - Vin
(3.59)
It's important to note that when looking at this equation, the location of the pole and zero
can be adjusted by changing each transconductor's gm independently. The ability to adjust
one variable in a filter's transfer function and only change the position of a single pole or
zero is called orthogonal tuning.
Figure 3.3
G 1 = gmd(C) + C z ) 3.2.2 The Biquadrati'

G gm2
z gml
As we briefly indicated
Vin+ ]---\,_---<i>---- V out- cascading first-order se
C)
G3 =
gm) first-order filters are res
Vin~
than filters with comple
lowpass filters having j
attenuation of 6 dB at
. Using a second-order fi
MHz so that the attenua
Figure 3.31 Impiemention ofa bilinear filter using transconductors. -40 dB/decade). Furthe
using Butterworth, Chel:
Switched-Capacitor implementation The biquadratic,

quadratic equations) is g
The switched-capacitor, SC, implementation of the bilinear filter is seen in Fig. 3.32. This
filter is directly derived from the active-RC filter of Fig. 3.30. From Eq. (3.42) we can
write
1 1
R1=-C
{' andRF=-C
{' (3.60) where 2rt/o = roo. The c(
1) 'JS 12 'JS
and so
and G3 (3.61)
C11 or
Note how, in this discrete-time filter, the passband gain is C I3 IC F when the filter is
designed for a highpass response (and the filter no longer behaves like a discrete-time
filter). The gain at DC in all situations is Cn/Cn.
ed-Signal Circuit Design Chapter 3 Analog Filters 99
V ou /+ =0 (3.56)
lis2C 2 ~l
o write
(3.57)
(3.58)
~:::-i'--..o-- VOUI
Mr '
/'""~---Voul+
(3.59) C
:tion of the pole and zero

ntly. The ability to adjust
v;n-L- '"-' " --1---<10--
C121
Isition of a single pole or U
!'
Figure 3.32 lmplemention of a bilinear filter using switched capacitors.
Gl gmd(C 1 + C2 ) 3.2.2 The Biquadratic Transfer Function

2
G2= gmi As we briefly indicated in the last section, higher order filters can be implemented by
)out- cascading first-order sections. However, because the pole and zero locations in these
G 3 -.fL
- gml first-order filters are restricted to real values, the performance of these cascades is poorer
Jout+ than filters with complex pole and zero locations. For example, cascading two identical
lowpass filters having hdB frequencies of 1.59 MHz would result in a filter that has an
attenuation of 6 dB at 1.59 MHz and a 40 dB/decade roll off at higher frequencies.
Using a second-order filter, we can design a filter to have a sharper transition at 1.59
MHz so that the attenuation is less than 6 dB at 1.59 MHz (however, the roll off remains
lsconductors. -40 dB/decade). Further, we can use these sections to implement higher order filters
using Butterworth, Chebyshev, Elliptic (Cauer), or Bessel responses.
The biquadratic, or "biquad" for short, filter transfer function (a ratio of two
quadratic equations) is given by
is seen in Fig. 3.32. This
From Eq. (3.42) we can Voul
(3.62)
Vin
S
2
+ (2nfo 1
Q)s+(2;ifo) 2
(3.60) where 2rt/o coo. The complex-conjugate poles are located at
(3.63)
(3.61 )
ell or
'13/CF when the filter is
aves like a discrete-time rt/o,
PhP2 == - ±). 2rt/o .11 -
1(1\12 (3.64)
Q V ,2Q/
In order to move toward the goal of implementing a biquad, consider the block Active-RC Irnplernentati
diagram in Fig. 3.33. This block diagram is essentially the cascade of two first-order
Figure 3.34 shows the
blocks (as seen in Fig. 3.29) except that instead of feeding the output of the second stage
associated design equati
back to its input, we feed it back to the input of the first stage. We can determine the
If, for example, a low
transfer function of this filter by writing
simplified.
Voul' (3.65)
or
Voull (s + ~' G2 ) = Vin (I +S~3)GI _ Voui GlSG S (3.66)
Further, we can relate voWI to the output using
(3.67)
Using Eq. (3.66) with Eq. (3.67) gives
V out
(
i Vin •
\
(1 +SG3)G 1
G G -
S+ I 2
Vout
S+
GIGS ) (1
G G
1 2
.
G )G4
+s 6 S (3.68) Vin- --r---vVV'-
I Rn
or , 11---
II GIG4G5(l+SG6)) _ '1/(I+SG3)G,(l+SG6)G4) Cll
VOUII +
"SZ+sG1Gz
- Vm
\
2
s +SGIG 2
(3.69)
Finally, the transfer function of the biquad is given by

Voul = s2G IG 3 G4 G 6 +S(GI G3 G4 + GIG 4 G6)+ G1 G 4 (3.70)
Vin S2 +S(G l G2 + G 1 G4G SG6 ) + G 1G4 G 5
Equating terms in Eqs. (3.62) and (3.70) gives
1 :
(I,
r"j a2 G 1 G3G4G6 (3.71)
ii',
il
)--j a1 = G, G3 G 4 + G 1 G4G6 (3.72) a2 = CCn Cn
CF2
Fl
II
aO=G 1G4 (3.73)
211./0 211./0 1
Q= G , G2 +G , G4 G S G6 (3.74) =--=-
Q Q RFlC
(21t/d G, G 4 G S (3.75)
Figure 3.34 fm!
Vou!1
Figure 3.35 sho\\'

"
transfer function for a se
, (C), and resistor (R). T
I lowpass biquad filter. HI
I DC gain of the biquad fi
Q, is greater than 11 fi
Butterworth or maximall
Figure 3.33 Implementation of a biquadratic transfer function using two integrators.
ixed-Signal Circuit Design Chapter 3 Analog Filters 101
Jiquad. consider the block Active-RC Implementation

cascade of two first-order
Figure 3.34 shows the active-RC implementation of the biquad filter along with the
output of the second stage
associated design equations. It should be noted that this is the general design schematic.
ge. We can determine the
If, for example, a lowpass filter needs to be implemented, the filter can be greatly
simplified.
I G (3.65)
!Vourl)"S
I .
--lou[-S
GIGS (3.66)
Cn Cl2
(3.67)
Voutl Rl2
Vout+
+ +
(3.68) ('------.----1 + ('------.----1 + Vout-
Rn V ou tl+
Cl2 Cn
(3.69)
~4G6)+GIG4
(3.70)
GI G4 GS
(3.71 )
C Cl2 1
(3.72) a 2 =n- - - ao=--~--
R n C Fl R l2 C n
CFICn
(3.73)
(00
-=--=---+
2n[0 1 Cl2
(3.74)
Q Q RFICFl CFlRnCn
(3.75)
Figure 3.34 Implementation ofthe active-RC biquadratic transfer function filter.
I--+-_V_o:..::ut(f) Figure 3.35 shows the frequency response, pole-zero locations in the s-plane, and
transfer function for a second-order lowpass circuit made using an inductor (L), capacitor
(C), and resistor (R). This LRC circuit has the same frequency response shape as a
lowpass biquad filter. However, the DC gain of the LRC circuit must be unity while the
DC gain of the biquad filter can be set to ao/(2n[0)2 . Note that if the pole quality factor,
Q, is greater than 1I.j2 the response will show peaking. Setting Q to 0.707 results in the
Butterworth or maximally flat response.
1 using two integrators.
inductor and capacito

(variations in the resis
/0 = - 2 . - indicates the poles are
2rc!iC
system with right-half
3.37. •
Q=*ff
Vout(J) I
Imjro
IVin(j)
OdB~--~~~4---~ Q 0.2--::f8iiijr-r-:::::f:
COo zeroes at infinity
----;---"'r-----+ Re,cr
Q 0.5
s plane
s cr +jco :
/rnax =/0' t-
I I
2Q2
Figure 3.37 The effect

Figure 3.35 Second-order lowpass filter.
Example 3.9
Example 3.8 Simulate the design
Design an LRC circuit with a Q of 0.707 and a cutoff frequency (10) of 1.59 MHz. similar to Fig. 3.36.
From Fig. 3.35 we have two equations we need to solve Using the basic top'
Cn = Cn 0 and then
/0 = 1.59 }';{Hz -+ LC = lOx 10- 15 and Q
2rc!iC
We can set C 100 pF, then L = 100 IlH, and R 1.4l4k (definitely not practical
values if the circuit is going to be purely integrated). The response of the resulting which we shall use tc
LRC circuit is shown in Fig. 3.36. Note how the cutoff frequency is set by the filter is given by
IdS 40'
~ . OdS 20' 3 dB down atio

I -7dB o· Knowing a 2 01 0,
•
~
-l~dB
-21 dB
-20'
-40'
- 40 dB/decade here. The simulation n
t
it
-2adB
-35dB
O'
-80'
Notice that at DC,
integrator, vourl+ and VO"l]. ,
":, :
~
-42dS
-49dB
-100'
-120'
section. As the frequency
'J -56dB '140' Figure 3.39 sho\\

i, ·63dB second-order lowpass res]
:, ·lOdS
:.
'J
·77dB -200'
values of the inductor a
bandpass response is; hiE
10KHz 100KHz lMH> 10MHz 100MHz
eventually rolls off at -20
Figure 3.36 Second-order magnitude response for the circuit described in Ex. 3.8. as an open (resulting in a
inductor can be thought of
xed-Signal Circuit Design Chapter 3 Analog Filters lO3
inductor and capacitor, while the Q of the circuit is set by all three elements
(variations in the resistance having the largest effect on the circuit's Q). Higher Q
10 indicates the poles are moving toward the imaginary axis (keeping in mind that a
2rr.JLC
system with right-half plane poles is unstable [oscillates]) and more peaking, Fig.
11[ 3.37. •
Q
R~C
Q M-+-'-++i-i"+---i--i--i-~ii--- Q 5
max
+--:---:--:+:+~~~~ ~~~=i=i~#T--Q = 1
)1 + 4~2
f (Hz) Q 0.707
Q = 0.5
I
x=/o' i1
V
Figure 3.37 The effect ofQ on the frequency response of a second-order lowpass filter.
r.
Example 3.9
Simulate the design of an active-RC filter that has frequency characteristics
ncy (10) of 1.59 MHz. similar to Fig. 3.36.
Using the basic topology of Fig. 3.34, we see that for a lowpass filter,
C lI = C n 0 and therefore G3 = G6 0. Further
L
I
10 = 1.59 MHz = 2rr. C R C' R
'Fl n Fl Fl
:lefinitely not practical
,ponse of the resulting which we shall use to set Rn = RFl = lOk and C Fl CFl lO pF. The Q of the
'equency is set by the filter is given by
Q= 2rt/o . RFI C F1 -+ RFI = 7.07 kO.
dB downat/o
Knowing a 2 = a l = 0, the gain at DC is ao/(2rr/o)2 or RFl/RIl (lIG s), which is I
- 40 dB!decade here. The simulation results are shown in Fig. 3.38 .•
Notice that at DC, when used in the lowpass configuration, the outputs of the first
integrator, v outl + and vouil_ , must be equal. If not, the difference is integrated by the second
section. As the frequency increases, so does the difference in these voltages.
Figure 3.39 shows the second-order bandpass response. Again, as with the
second-order lowpass response, the center frequency (resonant frequency) is set by the
values of the inductor and capacitor. The Q of the filter indicates how narrow the
bandpass response is; higher Q indicates a narrower response. Note how the response
eventually rolls off at -20 dB/decade. At low frequencies the capacitor can be thought of
leseribed in Ex. 3.8. as an open (resulting in a first-order RL circuit response), while at high frequencies the
inductor can be thought of as an open (resulting in a first-order RC circuit response).
n
OdB 20' OdB
-7dB o· -fidB ---,
-14dB -20' -12dB :::j:

-21dB -40' -lOdB' ,
-ZOdB -60' -24dB
-35dB -80' -JOdB
-42dB -100' -JfidB
-49dB -120' -42dB ---~-
-SodB -140' -48dB
-ti3dB
-7UdB
-77dB
-160'
-180'
-200'
:::::14
-G6dB '
1KHz 10KHz 100KHz It.tHz 10t.tHz 100MHz 1KHz
Figure 3.38 Magnitude and phase responses for the active-RC filter of Ex. 3.9. Figure 3.40 Bal
Example 3.11
I Repeat Ex. 3.10 if the
Vow sliC
-=
Vin S2 +s...L + Figure 3.41 shows th,
RC
20k with the inductor
OdS-,
: -
fo/Q -9dB-+---<
o dB -+-____'~o(.......")-'_ _ _-----+ -18dBT---'

-27dS~ .... -
I ;
3 dB -
~~~~u1>
Im,iro
One zero at infinity
and one at the origin
--'---'m----';loo- Re,cr
·12dB ....;.
.!£Q. -81dB ....:.
s plane
X2Q 20 dB/decade -90dS - ,~.
s = cr +jro
/0 ·99dB~
1KHz
Figure 3.39 Second-order bandpass filter. Figure 3.41 B
Example 3.12
Example 3.10 Use an active-RC filt{
Repeat Ex. 3.8 for the bandpass LRC circuit. Let's begin by writing
Again, we can set C = 100 pF and L = 100 /IF. Solving for Q using the equation in Vow
Fig. 3.39 results in Vin
Q=R/¥ =0.707 RJ~~~~ ~R=707 Looking at this equati

Cn = 0 and Ril 00, F
The simulation results are seen in Fig, 3.40.•
:ed-Signal Circuit Design Chapter 3 Analog Filters 105
C filter of Ex. 3.9. Figure 3.40 Bandpass response of a second-order circuit with a Q of 0.707.
Example 3.11
Repeat Ex. 3.10 if the Q is increased to 20.
fo
2rcJLC Figure 3.41 shows the simulation results. To attain a Q of20, we use a resistor of
20k with the inductor and capacitor values remaining unchanged.•
Q=Rff
J
~
~---c»> f (Hz)
- 20 dB/decade
Figure 3.41 Bandpass response of a second-order circuit with a Q of20.
Example 3.12
Use an active-RC filter to implement a filter with the response shown in Fig. 3.41.
Let's begin by writing the filter's transfer function
, using the equation in Vout
Vin
Looking at this equation, Eq. (3.62), and Fig. 3.34 we see that a2 = ao = 0 and so
Cn. 0 and RlI 00, Further then
C ll
al = - - ' -
RnCFlCn
'-- _1-J
Jio -
271: CFIRnCnRn
1 == 1.59 MHz
Technically, the filter is
filter.
2n{o 271: . 1.59 MHz

Q 20
The passband gain (the maximum gain) occurs atfo and is calculated by replacing
s in the transfer function above with j2n{o . It is given by
alQ
Apassband =:: 271:fo
If, again, we set CFl = Cn = 10 pF and Rn = Rn = 10k, we get anfo of 1.59 MHz.
Further then, with a Q of 20, we can set RFJ to 200k. Finally, setting the passband
gain to unity results in
2n{o Cn
al = - - = ~ Cll 0.5pF
Q R 12 C F1 C n
While these values do result in a biquad with the shape seen in Fig. 3.41, the
values are not practical. Redoing the calculations while trying to minimize the
component spread gives another possible solution: RI2 = lOOk, CFl 20p, RFI
lOOk, Cn = 5p, ClI = 5p, and Rn = lk. The simulation results are seen in
3.42.•
120'
100'
80'
60'
Figure 3."
40'
20' The biquad in F
0' understand the topology,
,20'
more than two bilinear
·40'
switched capacitance, C
·60'
feedback resistance, R n ,
-liD'
. filter implementation, ge
-100'
1KHz 10KHz 100KHz 1MHz 10MHz 100MHz
Figure 3.42 Outputs ofthe biquad of Ex. 35.12 using active-RC elements. We have a major concel
Fig. 3.34 or 3.43 with a
Switched-Capacitor Implementation within a factor of 4 of e:
The switched-capacitor implementation of the biquad circuit is shown in Fig. 3.43. Note magnitude different (100
G6 0,
how this circuit is a simple translation of the active-RC circuit of Fig. 3.34. Again, if the
filter designed using this section has a lowpass or bandpass response, it can be simplified.
For example, from Figs. 3.35 and 3.39 (the implementation of lowpass and bandpass and 271:10
filters), we see that a2 is zero. This indicates that G6 can be set to zero (removing Cn in
Figs. 3.34 or 3.43). The resulting second-order filter response can be written as This equation shows tha
Vout =:: als+aO SGIG3G4+GIG4 of RFI results in a smalle
(3.76) input of the first op-amp
Vin s2+e~o)s+(271:1o)
-Signal Circuit Design Chapter 3 Analog Filters 107
Technically, the filter is no longer biquadratic, so we will refer to it as a second-order

;;0; 1.59 MHz
F2 filter.
4>1
llated by replacing
--:I Cn !
v~ '~~~-4-
anfo of 1.59 MHz.

~ttingthe passband Voul+
Vout-
~n in Fig. 3.41, the

g to minimize the
., CF1 = 20p, RFI
ts are seen in Fig.
Cn
20' ·is Gs Cf12 ·is
00'
80'
60'
Figure 3.43 Implementing a biquad filter using switched capacitors.
40'
23' The biquad in Fig. 3.43 can look confusing until we start to dissect it. If we
3' understand the topology of Fig. 3.32, we see that the switched-capacitor biquad is nothing
23'
more than two bilinear filters connected in cascade. The only difference is that the
43'
switched capacitance, Cm' is fed back to the input of the first op-amp to simulate the
liO'
feedback resistance, Rn , in Fig. 3.34. This circuit, for the general lowpass or bandpass
80'
filter implementation, gets much simpler when the unused components are removed.
00'
HighQ
RC elements. We have a major concern alluded to in Ex. 3.12 when using either of the topologies of
Fig. 3.34 or 3.43 with a large Q. As we saw in this example the capacitor values were
within a factor of 4 of each other (20p and 5p) but the resistors used were two orders of
)wn in Fig. 3.43. Note magnitude different (lOOk and 1k). This large difference can be traced to, again assuming
Fig. 3.34. Again, if the G6 0,
;e, it can be simplified.
lowpass and bandpass (3.77)
zero (removing Cn in
e written as This equation shows that RFI has the largest direct dependence on Q. Using a large value
of RFI results in a smaller feedback signal (a smaller amount of current is fed back to the
(3.76) input of the first op-amp). In other words G2 in Fig. 3.33 is small.
108 CMOS Mixed-Signal Circuit Design Chapter 3 Analog Filte
In order to minimize the amount of signal, V QutP fed back and summed with the
input signal, while at the same time forcing the components to have similar values,
consider the modified, from Fig. 3.33, biquad block diagram shown in Fig. 3.44. All we
and
have done here is added a separate signal path in parallel with the G2 path. Instead of
subtracting, though, we are now adding the signal to the input summing block. Equation
(3.70) can be rewritten, assuming G6 is zero (a bandpass or lowpass response), as
Voul s(G 1 G3G4) + Gl G 4 In an attempt to mi
(3.78)
Vin s2+SGl(G2-G2Q)+GIG4GS 4p, CF2 to 20p, CF1
simulation results a:
or, equating the coefficient of s in the denominator of this equation with the coefficient of
s in the denominator ofEq. (3.62), results in
(3.79)
The implementation of the "high-Q" biquad is seen in Fig. 3.45 (with G6 included). The
CII
additional gain from the figure is
Rn I
G 2Q=--Q-
RFi Q-1
(3.80) i -Rll
v ..
In-t-L-;\N'
Rewriting Eq. (3.79) results in
2n/o G1G2
(3.81 )
Q Q
Let's use this result in the following example.
In VourV> L._ _ _ __
Figure 3.45 Impleme

The bold
Example 3.14
Repeat Ex. 3.13 usin
is clocked at 100 Ml
Figure 3.44 Implementation of a "high-Q" biquadratic transfer function.
To implement the fil
capacitors. Howevel
Example 3.13 ratios of capacitors. '
Repeat Ex. 3.12 using the high-Q circuit of Fig. 3.45. values in Fig. 3.46. I
The passband gain is I so we know that all resistors by 10. T
OJ
resistors can be calct
~ G1G2
Gl= Q = GjG3G4 =G 1(G2 G 2Q)==Q
or 2n/o 10 x 10 6 = GI G2 == lIRFI C F1 . We also know that

:ed-Signal Circuit Design Chapter 3 Analog Filters 109
~k and summed with the

to have similar values,
own in Fig. 3A4. All we
and
1 the G~ path. Instead of
umming block. Equation
:ISS response), as
(3.78) In an attempt to minimize component spread let's set RFI to 5k, Rfl. to 20k, CII to
Gs 4p, to 20p, CF ] = 20p, Rn = l.25k, and finally RFIQ = 5.25k (roughly). The
on with the coefficient of simulation results and schematic are shown in Fig. 3A6.•
(3.79) RFI
RF2
; (with G6 included). The
CIl
(3.80)
Vin+ j :£ ~c--_-++-
Vout+
V(}ut
(3.81 )
I
~=G2'
Voutif)
Q Q
RFI _
Q 1
Figure 3.45 Implementation of the "high-Q" active-RC biquadratic transfer function filter.
The bold lines indicate the added components.
Example 3.14
Repeat Ex. 3.13 using a switched-capacitor implementation. Assume that the filter
is clocked at 100 MHz.
msfer function.
To implement the filter, we need to replace the resistors in Fig. 3.46 with switched
capacitors. However, we notice in the gain equations that the resistors are all
ratios of capacitors. This means we can reduce the size of the filter by scaling the
values in Fig. 3.46. In order to do this let's divide all capacitors by 10 and multiply
all resistors by 10. Therefore, we can write C'l OAp, CFI 2p, and Cn = 2p. The
resistors can be calculated using
G 1G2
Q RFI = 50k-). C m =. O.2p
C/2l'1s
52.5k -). C121Q =. 0.190p

..
------------~--.- .. --------
Figure 3.47 sho,,",

implement the high-(
5k
Also note how the ciJ
~ 1.25k
and Cn)'
5.25k
20p 4>1 4>
(O.16p) ,
O.2p O.I9p ,
~--+H-- Voul+
~/..L I /
Vin- --1 -_-i
r'
(O.8p): T T
vin+~O~P! ••.
5k
I.25k
VeM
-1
ffiI--::::
~
',1'
./""
I!,·,.
- Vin- O.4p'
9da-..,.....,..,.....,.,.."---,-,-.~~~~L--,-,-~.,--:-:-,..,..,.,,CT 120' (O.8p): !
1-
100'
CQT"
80'
SO·
O.2p O.~
40'
(O.16p)
20'
o'
'20' Figure 3.47 Switc
.+.l-j.:.,,:i1- -.40'
-no'
,..;.; ~.~~:~I- ·80' Again, as in Ex.
·100' transient analysis, we
we get the correct Ot
signal to the filter at
However, as seen i1
Figure 3.46 Bandpass filter discussed in Ex. 3.13. simulations it's easy t
outputs oscillate at fo (
as the Q of the bandpl
1 plane. If, for some re<
R12 -C-- == 200k -+ Cm == 0.05p (!)
!l21s become an oscillator (
the filter we approxin
Rn == C I" == 12.5k -+ Cm == O.Sp
122 'Js «t:
-s
cos 2,g
j,
'" I and sir
Looking at the value of Cm , we see it may be too smaIL Let's change its scale
factor from 10 to 4. This means
R12 == C I" -= SOk -+ Cm -= 0.125p which clearly will no

112 •J S
We have to scale Cn as well (so that G4 remains constant). Now Cn = 5 pF. frequency J,. As we di
in excess of the sampJ
the combination of th.
[xed-Signal Circuit Design Chapter 3 Analog Filters III
Figure 3.47 shows the implementation of the filter. Note how easy it was to
implement the high-Q circuitry. All we did was add two capacitors to the circuit.
Also note how the circuit is simplified after removing the unused components (Rn
and Cl2 ).
~l
2p
(O.16p)
Figure 3.47 Switched-capacitor implementation of a high-Q filter; see Ex. 35.14.
Again, as in Ex. 3.6, because this circuit can only be simulated using a
transient analysis, we will input a sinewave at a known frequency and verify that
we get the correct output. Looking at Fig. 3.46, we see that if we apply a I V
signal to the filter at 1.59 MHz we should get a 1 V signal out at 1.59 MHz.
However, as seen in Fig. 3.48, the filter is unstable and oscillates. Using
3.13. simulations it's easy to show that even if we ground the inputs of the filter, the
outputs oscillate atfo(1.59 MHz). To understand why, remember in Fig. 3.39 that
as the Q of the bandpass filter is increased, the poles move closer to the right-half
plane. If, for some reason, the poles move into the right-half plane, the filter will
become an oscillator (unstable). It's important to remember that when we designed
the filter we approximated our discrete-time variable z as 1 + = It (when f
cos "" 1and sin ~; "" ~J). We could be more exact and write
Let's change its scale
2nf . 2nf
z "" cos-+ jsm- (3.82)
j, Is
which clearly will not follow 1 + ~:for frequencies f approaching the sampling
..row Cn = 5 pF. frequency J;. As we discussed in Ch. 2, sampled signals will have spectral content
in excess of the sampling frequency. Practically, the spectral content is limited by
the combination of the switches "on" resistance and the capacitors in the circuit.
112 CMOS Mixed-Signal Circuit Design Chapter 3 Analog Filtel
gain-bandwidth produc
ideal integrator gain of
Output
Input-_..:.:c:.:~
Using this result, we (

[3.64]) as
or, looking at a single tt
Figure 3.48 Output of the filter in Fig. 3.47 showing instability.
As f gets larger, the cosine term will decrease from one, causing the real portion to
get smaller. A decrease in the real component, as seen in the complex plane in This subtraction results
Fig. 3.39, causes the pole to move closer to the right-half plane (causing the Q to of the circuit; Fig. 3.50
increase). (3.85) to estimate the sl
Practically, the maximum Q we can design for (but not attain) is in the r
neighborhood of 5. If we redesign the biquad of Fig. 3.47 to have a Q of 5, we see
that all we need to change is CII (from O.4p to O.8p) and CI21Q (from O.19p to
O.16p). The simulation results are seen in Fig. 3.49. In this figure, we adjusted the
input frequency until we reached a 3 dB point (the filter's center frequency was
1.59 MHz, as expected). This occurred at 1.52 MHz and 1.66 MHz. The Q of the
circuit is not 5, but is, from Fig. 3.39, 1.59/(1.66 - 1.52) or 11.36.•
So, for the filter Q to re
0.8V
n.sv Let's use this result in tl

0.4V
O.2V
Input
o.ov
Output
-,uv
·1.llV
Figure 3.49 Output ofthe filter in Fig. 3.47 after lowering the Q to maintain stability.
Q Peaking and Instability

While it would appear the active-RC circuit is the best choice for high-Q filter Figure 3.50 Showir
implementations, we must remember that the discussion neglected the effects of the finite
I-Signal Circuit Design Chapter 3 Analog Filters 113
gain-bandwidth product U;m) of the op-amps. We can model these effects by replacing the
ideal integrator gain of lis with
l~ 1 (3.83)
s s ( 1+_'_1\
2tt/un I
Using this result, we can rewrite the pole locations of Eq. (3.62) (see Eqs. [3.63] and
[3.64]) as
(3.84)
• 5.0~s or, looking at a single term,

Unwanted
~
tability.
(2nf)2
s(
l+_S_
) +Pl=S+Pl (3.85)
g the real portion to 2n/un 2nJ,.m
! complex plane in This subtraction results in a shift in the pole toward the right-half plane, increasing the Q
e (causing the Q to of the circuit; Fig. 3.50. Reviewing Eq. (3.64), we can subtract the unwanted term in Eq.
(3.85) to estimate the shift in the Q or
)t attain) is in the 2
n/o (2nf) • • l( 1 2/0)
- - - - orat f= 10 we can wnten/o - - - (3.86)
ve a Q of 5, we see Q 2n/un Q fun
'I2lQ (from 0.19p to
lTe, we adjusted the The shifted Q is then
nter frequency was 1 2/0
MHz. The Q of the = -Q J,.- ~ QShifl (3.87)
Qshijt lin
36.•
So, for the filter Q to remain finite, we require
« I (3.88)
fun
Let's use this result in the following example.
f. .... Output 1m,

Poles move towards right-half plane
due to finite op-amp gain-bandwidth.
The result is an increase in the filter's Q.
s 2.01ls 'l
-------~--~~*_---------~~
splane
Re
a maintain stability.
~ ~ X I ~ Ideal distance is ~
:>ice for high-Q filter Figure 3.50 Showing Q peaking resulting from the op-amp finite gain bandwidth product.
the effects of the finite
Example 3.15
Resimulate the filter in Ex. 3.13 using op-amps that have anfu" of 100 MHz.
The center frequency,lo, of this filter is 1.59 MHz and the Q is 20. Using Eqs.
(3.87) and (3.88), we can estimate the increase in Q due to op-amp finite
gain-bandwidth product as
Q2fo
0.636 ---? Qshift 55
fun
Practically, this is too high of a Q (the poles are too close to the right-half plane),
and the filter will be unstable (noise in the circuit, or simulation noise in the
simulation, will push the poles into the right-half plane). Figure 3.51 shows the
simulation results (see also Ex. 3.4). The inputs to the filter are grounded. The
unstable oscillation frequency is close to the ideal,lo, but is shifted by a small
amount. •
Figure 3.5
Figure 3.51 Showing how the filter of Ex. 3.13 becomes unstable due to
finite op-amp bandwidth.
Transconductor-C Implementation
Let's redraw the bilinear filter in Fig. 3.31 as seen in Fig. 3.52. We redraw it like this to
show how the feedback gain, G2, is implemented. In the block diagram of the biquad filter
ShO\\<l1 in Fig. 3.43, we used a similar scheme to implement the feedback gain, Gs- Figure
3.53 shows the implementation of a biquad filter using transconductors where we have Figure 3.53 •
drawn it so that the trans conductors appear to be connected in series. This topology can
be redrawn so that it looks similar to Fig. 3.52 (showing a direct correspondence between
it and Fig. 3.43). Note that we could have drawn the schematic without the crossing wires
if we switched the output polarity of two of the transconductors (that is, put the minus S. Franco, Design
output on the top of the output instead of the plus output). Third Edition, Mc(
R. Schaumann am
University Press, 2
P. R. Gray, D. A.
Circuits, Wiley-IEl
ed-Signal Circuit Design Chapter 3 Analog Filters 115
~n of 100 MHz.
Q is 20. Using Eqs.
ue to op-amp finite Vin+ 1-+-----_-----_--- VOIit+
Vjn~ !-.--._--t-r-------+_--v out_
the right-half plane),

mlation noise in the
igure 3.51 shows the
G1 gmd(C l +C2 )
~r are grounded. The
is shifted by a small G 2 == gm2
gmt
G3 .f.L
gml
Figure 3.52 Redrawing the bilinear tIlter shown in Fig. 3.31.
Ips
mstable due to
We redraw it like this to

19ram of the biquad filter
'eedback gain, Gs' Figure
nductors where we have Figure 3.53 Implementing a biquadratic filter using transconductors.
~eries. This topology can
correspondence between
ADDlTIONAL READlNG
rithout the crossing wires
's (that is, put the minus [1] S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits,
Third Edition, McGraw-Hill, 2003. ISBN 978-0071207034
[2] R. Schaumann and M. E. Van Valkenburg, Design of Analog Filters, Oxford
University Press, 2001. ISBN 978-0195118773
[3] P. R. Gray, D. A. Hodges, and R. W. Brodersen (eds.), Analog MOS Integrated
Circuits, Wiley-IEEE, 1980. ISBN 0-471-08964-8
_ "_____I
r4] P. R. Gray, B. A. Wooley, and R. W. Brodersen (eds.), Analog MOS Integrated Derive the transf
Circuits Il, Wiley-IEEE, 1989. ISBN 0-87942-246-7
[5] P. A. Lynn, An Introduction to the Analysis and Processing of Signals,
Hemisphere Publishing Corporation, 1989. ISBN 0-89116-981-4 Vinl+ ----"'\
[6] Y. P. Tsividis and J. O. Voorman (eds.), Integrated Continuous-Time Filters:

Principles, Design, and Applications, Wiley-IEEE, 1993. ISBN 0-7803-0425-X
[7] B. Nauta, Analog CMOS Filters for Very High Frequencies, Kluwer Academic
Publishers, 1993. ISBN 0-7923-9272-8
QUESTIONS
3.1 Resketch Fig. 3.2 for the following circuit.
Fi
Show the derivat

Show the details
Is it possible to
independently? I
generate Fig. 3.31
Figure 3.54 First-order lowpass filter using an inductor and a resistor. What happens to
than 0.5? (Hint:
3.2 Show that Eq. (3.6) is still valid if the circuit's inputs and outputs are referenced to the In.., equation i
the common-mode voltage, VCM' (The op-amp inputs should also be at VCM') Compare the siz{
3.3 Sketch the implementation of a first-order 10wpass filter using a CAl with a 3 dB using an active el
frequency of 10 MHz and a DC gain of 6 dB. Simulate your design to verify it Show, using the!
works as expected. and thus the spec
3.4 Plot, in the complex plane, the ideal pole location and the actual pole locations stabilize high-Q s
due to finite op-amp unity gain frequency for the filter described in Ex. 3.4. Redesign and sirr
3.5 Plot Eq. (2.59) of the last chapter using SPICE and the op-amp model shown in of 5, while tryin
Fig. 3.8. possible modific~
3.45) to reduce th
3.6 Suppose an antialiasing filter was required for a l2-bit data converter. Further
assume the filter is to be implemented using an active-RC topology. If VDD 1.0 Show how to del
V, estimate the minimum value of the integration capacitor that should be used, seen in Fig. 3.53.
assuming the filter's noise performance is dominated by thermal noise. Is it wise, Repeat Ex. 35.9 u
for 12-bit system performance, to design the filter so that its SNR is equal to the
SNR of the data converter? How would a "hiE
35.12 using the tn
3.7 Repeat question 3.6 if the op-amp used in the filter has a linear output swing of
80% of the power supply voltage. Show, using biqu
be implemented.
3.8 Derive the transfer function for the filter shown in Fig. 3.16 if the transconductors
have different gros. Sketch the block diagram, similar to the one seen in Fig. 3.6,
for the filter.
<ed-Signal Circuit Design Chapter 3 Analog Filters 117
, Analog lvIOS Integrated 3.9 Derive the transfer function for the following first-order transconductor filter.
Processing of Signals,
6-981-4
Continuous-Time Filters:
· ISBN 0-7803-0425-X f - - + - - - - V OUl+
c
mcies, Kluwer Academic I---+_---Voul-
Figure 3.55 A first-order filter with two inputs.
3.10 Show the derivation details that result in Eqs. (3.44) and (3.46).
3.11 Show the details of how the gains, G, are derived in Fig. 3.30.
3.12 Is it possible to tune the gain, Q, and cutoff frequency of the lowpass biquad
independently? If so, how? Give examples using the simulation netlist used to
generate Fig. 3.38.
· and a resistor. What happens to the poles in the biquadratic equation, Eq. (3.62), if the Q is less
than 0.5? (Hint: The filter behaves like the cascade of two first-order filters.) Is
I outputs are referenced to thef.nax equation in Fig. 3.35 valid?
uld also be at VCM') Compare the size of the elements used in Exs. 3.8 and 3.9. Is there a benefit to
· using a CAl with a 3 dB using an active element for monolithic implementation?
e your design to verify it Show, using the simulations from Ex. 3.14, that increasing the switch resistance,
and thus the spectral content present in a switched capacitor circuit, can help to
the actual pole locations stabilize high-Q switched-capacitor bandpass filters.
~scribed in Ex. 3.4. Redesign and simulate the operation of the filter discussed in Ex. 3.14, with a Q
, op-amp model shown in of 5, while trying to minimize the difference between Cll and Cn . Suggest a
possible modification to the filter topology (similar to how we add G ZQ in Fig.
3.45) to reduce this component spread.
it data converter. Further
.C topology. If VDD = 1.0 Show how to derive the transfer function of the transconductor-C biquad filter
citor that should be used, seen in Fig. 3.53. Can this filter be orthogonally tuned? If so, how?
, thermal noise. Is it wise, Repeat Ex. 35.9 using the transconductor-based biquad.
at its SNR is equal to the
How would a "high-Q" biquad be implemented using trans conductors? Repeat Ex.
35.12 using the transconductor-based biquad.
> a linear output swing of
Show, using biquad sections, how the lowpass ladder filter seen in Fig. 3.56 can
be implemented.
U 6 ifthe trans conductors
Ithe one seen in Fig. 3.6,
Figure 3.56 Implementing a ladder filter using biquads, see problem 3.20.
Digital F
In this chapter we stu

mixed-signal circuit d(
integrator and, to a less
chapter the reader may'
4.1 SPICE Model!

order to verify, using
~chapter, we start out
. converters (DACs) and
DACs and ADCs that
digital word based on aJ
4.1.1 The Ideal DAe
Consider the ideal trans
figure that we have dn
that VREF+ > VREF-. Wh
becomes VREF-. When
analog voltage defined
(LSB). If the DAC has,
if, for example, VREF+ =

distance between adjace
ideal DAC we are ass
VREF+ 1 LSB. We co
V REF_ + 1 LSB up to VR
1 LSB smaller than the
For the DAC develop'
V REF = 0 V. Selection
ICed-Signal Circuit Design
Chapter
-_.----VOUI
4
lee problem 3.20.
Digital Filters
In this chapter we study the implementation of digital filters specifically useful for
mixed-signal circuit design. As in the last chapter, our filters will be based on the
integrator and, to a lesser extent, the differentiator. Prior to studying the material in this
chapter the reader may want to review Sec. 1.2.
4.1 SPICE Models for DACs and ADCs

In order to veritY, using SPICE simulations, the theory for digital filters discussed in this
chapter, we start out by developing simulation models for ideal digital-to-analog
converters (DACs) and analog-to-digital converters (ADCs). Our goal is to generate ideal
DACs and ADCs that we can place in a mixed-signal simulation to either generate a
digital word based on an analog input or look at the spectrum of a digital signaL
4.1.1 The Ideal DAC
Consider the ideal transfer characteristics of a 3-bit DAC shown in Fig. 4.1. Notice in this
figure that we have drawn two reference voltages, VREF+ and V REF-, and are assuming
that V REF+ > VREF-. When a digital input of 000 is applied to the DAC, the output voltage
becomes V REF-. When the input code is increased to 001, the output of the DAC (an
analog voltage defined at discrete amplitude levels) increases by one least significant bit
(LSB). If the DAC has an input code with a number of bits, N, then we can define an LSB
as
1 LSB = .:.....!-"""-'--:-~c..=- = VLSB for N? 2 (4.1 )
If, for example, VREF+ 1.25 V and V REF- 0.25 V and N = 3, then our LSB, the vertical
distance between adjacent points in Fig. 4.1, is 0.125 V. Note that in our discussion of an
ideal DAC we are assuming that the output of the DAC ranges from VREF- up to
V REF+ - 1 LSB. We could just as easily have assumed that the output ranged from
V REF- + I LSB up to V REF+. The important thing to notice is that the DAC output range is
1 LSB smaller than the difference between the positive and negative reference voltages.
For the DAC developed in this chapter, we will assume VREF+ = VDD = 1.0 V and
VREF- 0 V. Selection of the power supply rails, which are noise free in a SPICE
VREF+ VREF
We can implement this
VRE~ 8/8 1 source). For a 3-bit, idee
like
1 ~~ 7/8
VREF+ -
• >Nonlinear depend€
6/8 • Bout Vout 0 V=«v(v
5/8 • J_-" I LSB

-
4/8
Example 4.1
3/8
Write the nonlinear dt
2/8
• The statement follow,
VRE~ 0
118
.'
"
I I
Bout Vout 0 V=«v(v
+(v(B11l)*2048)+v(
+v(B7L)* 128+v(B6l
000 001 010 011 100 101 IJO III +v(B2L)*4+v(B1 Lt:!
remembering that a II.

remainder of the line
doesn't indicate additi
The next thing WI
want to use our ideal DJ
1 - - - - - - VOUT well defined. We need 1
power-supply voltage VD
bO----1 amplitude is greater than
switch implementation u
dependent source from re,
VDD
Figure 4.1 An idea13-bit DAC
simulation, allow the maximum output range for the DAC (assuming the reference
voltages are indeed the maximum and minimum voltages in the system, i.e., no charge
pumps or external, larger, power supply voltages). Ifwe need more resolution when using
our ideal DAC, we will simply increase the number of bits, N, used and thus decrease the
value of the DAC's LSB.
SPICE Modeling the Ideal DAC
We can write the output of the ideal DAC in terms of the reference voltages and digital Figure 4.2 '
input codes b" (which are logic "0" or "I "), and assuming that an input code of all zeroes
results in an output voltage of VREF-, as 4.1.2 The Ideal ADC
bl"l-l bN-2 b bo)
VOUT (VREF+ - V REF-)· ( Y + 22 + ... + 21"1-1 + 2N + V REF-
l
(4.2) The characteristics of our
is shifted to the left. Ifwe
or intersection of the analog
DAC transfer curve of
ixed-Signal Circuit Design Chapter 4 Digital Filters 121
TJ"
rOUT = (VREF+ V ) 21
REF-' (b N-I 2 N- 1 + b N-2 2 N- 2 + ... + b l ' ~')1 + b)
0 + V REF- (4.3)
N '
We can implement this equation, in SPICE, using a nonlinear dependent source (a B

source). For a 3-bit, ideal DAC, the statement that implements this equation may look
like
*Nonlinear dependent source, B, for generating the 3-bit DAC output
Boul Voul 0 V=( (v(vrefp )-v(vrefm »/B)*(v(B2L)*4+v(B1 L)*2+v(BOL))+v(vrefm)
The terms BXL correspond to logic signals that have a value of I V or 0 V.

LSB
Example 4.1
Write the nonlinear dependent SPICE source statement for an ideal 12-bit DAC.
The statement follows:
Bout Voul 0 V=«v(vrefp)-v(vrefm»/4096)*
+(v(B11 L)*204B)+v(B1 OL)*1 024+v(B9L)*512+v(BBL)*256+
Digital +v(B7L)*12B+v(B6L)*64+v(85L)*32+v(B4L)*16+v(B3L)*B+
Iput code, b 2 b I b o +v(B2L)*4+v(B 1L}*2+v(BOL) )+v(vrefm)
remembering that a "+" in the first column of a line indicates that the text on the
remainder of the line behaves as if it were typed at the end of the previous line. It
doesn't indicate addition .•
The next thing we need to concern ourselves with is the digital logic levels. We
want to use our ideal DAC with real circuits where the logic voltage levels may not be
!'OUT well defined. We need to determine and use a switehing-point voltage based on the
power-supply voltage VDD. We will assume the input logic code is a valid logic "1 II if its
amplitude is greater than VDDI2 and a logic "0" if its amplitude is less than VDDI2. The
switch implementation used to generate the logic signals (l V and 0 V) used in our
dependent source from real signals is shown in Fig. 4.2.
VDD IV BX is the logic input with

a, possibly, poorly defined
1;OOMEG amplitude.
(assuming the reference
he system, i.e., no charge blP CI.'" wh", B" > 1<], _)
-----:::;:.;..:..
~ lOOMEG
(
lore resolution when using Close4. \V~en BX; < triQ
Ised and thus decrease the

~ v
renee voltages and digital Figure 4.2 Generating logic levels using voltage-controlled switches.
input code of all zeroes
III
4.1.2 The Ideal ADC

(4.2) The characteristics of our ideal ADC are shown in Fig. 4.3. Notice that the transfer curve
is shifted to the left. If we were to flip the curve on its side and mark, with black dots, the
intersection of the analog input voltage with the ADC transfer curve, we would have the
DAC transfer curve of Fig. 4.1. Again, 1 LSB is given by Eq. (4.1). Notice how
122 CMOS Mixed-Signal Circuit Design Chapter 4 Digital Filters
converting a (normalized) input voltage of 0.1 V will result in an output code of 000 If the input signal j
which is the same output code resulting from converting 0 V. Unlike the ideal DAC, the input signal is mult
ideal ADC quantizes its input with the practical result of adding noise to the input signal.
This output is usee
This noise is called quantization noise.
repeated. This cont
The reference vol1
Digital calculating the midpoint b
output code, b2 b 1 bo I LSB
~
the VeM is referenced to 0 '
111 VCM
110
We also want to level-shit
101 want to shift the transfer (
this we use the following
100
output voltage of the ideal
011 • Level shift by VREF
BPIP PIPIN 0 V=V(C
010
001
000 1/2
~O 1/8 2/8 3/8 4/8 5/8 6/8 7/8~8/8
Analog input voltage ""
V REF- We are level-shifting the:
VREF+ -1 LSB
model as flexible as possi'
0.5 V and VREF = 0.25
simplified.
4.1.3 Number Represe
Suppose we have an ideal
and a V REF- of ground.
minimum output of the [
LSB or 0.9961 V. An inpl
1----- bo the common-mode volta)
corresponding digital cod
offset format. The output
format. A more useful fc
1
Figure 4.3 An ideal 3-bit ADC. complement format, Fig. L
The implementation of the ideal ADC consists of an ideal S/H followed by

passing the output ofthe S/H (the held signal) through an algorithm to generate the output Illlllll (0.9961 V)
bits. The algorithm we use is based on a pipeline ADC and follows: (255)
1000 0000 (0.5 V)
1. The input signal is sampled and held. (128)
2. This held signal is input to a comparator that compares the input value to a 0000 0000 (0 V) ~ -
reference voltage. (0)
3. If the input signal is greater than the reference voltage, the output bit is set to a
Figure 4
high, and the reference signal is subtracted from the input. The difference is
multiplied by two and passed to the output of the stage.
in an output code of 000 4. If the input signal is less than the reference voltage, the output bit is set low. The
Unlike the ideal DAC, the input signal is multiplied by two and passed to the output of the stage.
Ig noise to the input signal.
5. This output is used as the input to the next stage and steps 2, 3, and 4 above are
repeated. This continues for N stages (where N is the number of bits in the ADC).
The reference voltage, or common mode voltage VCM ' can be determined by
calculating the midpoint between VREF+ and V REF- followed by subtracting so that
the VCM is referenced to 0 V. This can be written as
VCM VREF+ + V REF V VREF+ + V REF V
2 -t CA10 = 2 - REF- = (4.4)
We also want to level-shift the input signal so that it is referenced to 0 V. In addition, we

want to shift the transfer curves to the left by 112 LSB as seen in Fig. 4.3. In order to do
this we use the following SPICE statement (for an 8-bit ADC where V(OUTSH) is the
output voltage of the ideal SIH [the input to the pipeline algorithm above])
• Level shift by VREFM and 112LSB
BPIP PIPIN 0 V=V(OUTSH)-V(VREFM)+«V(VREFP)-V(VREFM»12 A 9)
The last term in this statement is 112 LSB, which is given by

~ V IN V REF
112 LSB= ~""-'---"''''-- assuming V REF+ > V REF ~ 0 (4.5)
18 V REF+
" We are level-shifting the input and common-mode voltage because we want to make the
,+-1 LSB
model as flexible as possible. For example, we want the ADC model to function if VREF~
= 0.5 V and V REF = 0.25 V. Note that if V REF 0 and V REF+ = VDD, the model can be
simplified.
4.1.3 Number Representation
Suppose we have an ideal ADC and DAC each with a resolution of 8-bits, a V REF+ = 1 V
and a V REF of ground. Using Eq. (4.1) the data converter's LSB is 3.906 mY. The
minimum output of the DAC, Fig. 4.1, is ground and the maximum output is VDD 1
LSB or 0.9961 V. An input sinewave swinging from ground to VDD and centered around
bo the common-mode voltage, VCM ' of 500 mV is seen in Fig. 4.4. Also seen are the
corresponding digital codes and voltages. This number format is referred to as binary
offset format. The output of our ideal ADC and the input of our ideal DAC are in this
format. A more useful format, for adding and subtracting digital numbers, is the two's
complement format, Fig. 4.5. We get this format by complementing the MSB of a word in
an ideal SIH followed by

:ithm to generate the output 1111 1111 (0.9961 V)
.ows: (255)
1000 0000 (0.5 V) ---f-----'r-~
(128) time
Jares the input value to a 0000 0000 (0 V) - -

(0)
e, the output bit is set to a

Figure 4.4 Representing a sinusoid in binary offset format.
e input. The difference is
Example 4.2
0111 1111 (0.9961 V)
Show how to conv
(+127)
complement number
time
0000 0000 (0.5 V) --f---~---f------>,;------'--ld~'-r':;':'::"--~ A I-bit binary offse

1111 1111 (0.496IV/T noise-shaping ADC;
(-1)
represent 0 as -I an<
1000 0000 (0 V) 7 VCM 128· VLSB
(-128)
Figure 4.5 Representing a sinusoid in two's complement format.

For 4-bit representa:
use these results fr
binary offset (and thus to go back-and-forth between two's complement and binary offset
converters.•
we simply complement the MSB). Note, in Fig. 4.5, that -] is represented using 1111
1111, -2 is represented using 1111 1110, etc. Also note that the MSB corresponds to the A comparator is
word's sign-bit. An MSB of 0 indicates a positive value (or the common-mode voltage, number used in this exa
VCM> 0000 0000) while an MSB of 1 indicates a negative value (a code or voltage below for determining the LSB
VCM)'
Increasing Word Size (Extending the Sign-Bit)
Adding Numbers and 01
Often as we design digital filters we'll need to increase the word size to increase the
Figure 4.7 shows how 1:1
resolution of the signal or to avoid register overflow. Figure 4.6 shows how we would
do, when adding two di
increase the binary offset representation of the output of a 3-bit ADC to 8-bits while
(see the allowable over
changing the format to two's complement representation. The MSB of the ADC's output
allows the final output \
is extended and inverted. Notice what would happen if our ADC's input signal were VCM'
the inputs. Note that II
The ADC's output is then 100. This is changed into 0000 0000. The common-mode
integrator seen in Fig. 1.
signal, as seen in Fig. 4.5, can be thought of as a reference, or zero, level. Since we'll be
harmful overflow. For ~
using two's complement numbers throughout the rest of the book the reader should spend
overflow (unless the int(
some time reviewing, and ensuring they understand, Figs. 4.4, 4.5, and 4.6.
is easy to detect since
(positive or negative). If
ADC Output After extension MSB must be 0 (1) . If
000 (0) 1111 1100 (-4) the two inputs are positi'
001 (I) 11111101(-3)
010 (2) Ill! 1110 (-2) Adding two's complel
011 (3) 11111111 (-1)
A (3-bits) 4-bits
-----I
;l Ideal
3-bit ADC
100 (4)
101 (5)
110 (6)
0000 0000 (O)
0000 0001 (1 )
000000 10 (2)
B (3-bits) 4-bits
~
felk I 111 (7) 0000 DOll (3) Extend the sign-bit
Two's complement word IIO(
,
ADC Output
is binary offset with sign extension + 110(
1 100(
Figure 4.6 Showing how to change the output of an ADC to two's complement and Overtl(
how to extend the sign bit.
Figure 4.~
xed-Signal Circuit Design Chapter 4 Digital Filters 125
Example 4.2
Show how to convert a I-bit binary offset number into 2-bit and 4-bit two's
complement numbers.
J~m_
_ VCM"" 0.5 ..... time)
VC.H-VLSB
A I-bit binary offset number has values of 0 or I (common for the output of a
noise-shaping ADC). To change this into a 2-bit two's complement number we'll
represent 0 as -I and I as +I or
dU
VCM 128· VLSB

O~II(-I)
1~01(+1)
.ent format.
For 4-bit representations we can write 0 ~ 1111 (-I) and I ~ 0001 1) . We'll
plement and binary offset use these results frequently when discussing noise-shaping (delta-sigma) data
converters.•
s represented using III I
~ MSB corresponds to the A comparator is an example of an ADC (or quantizer) that will generate the I-bit
e common-mode voltage, number used in this example. Reviewing Eq. (4.1) we see that this equation doesn't work
(a code or voltage below for determining the LSB of a I-bit ADC. We can modify Eq. (4.1) for this situation
1 LSB VREF+ - VREF "" VLSB for N 1 (4.6)
Adding Numbers and Overflow
Nord size to increase the
Figure 4.7 shows how two's complement numbers are added. Note that the first thing we
L6 shows how we would
do, when adding two digital signals, is to extend our sign bit to avoid harmful overflow
-bit ADC to 8-bits while
(see the allowable overflow examples in the figure). This increases the word size and
v1.SB of the ADC's output
allows the final output word size to always be large enough to accommodate the sum of
C's input signal were VeM'
the inputs. Note that this is important. In filters employing feedback, like the digital
1000. The common-mode
integrator seen in Fig. 1.26, we may increase the word size even more to avoid, or delay,
zero, level. Since we'll be
harmful overflow. For an integrator a DC input will always, after some time, result in
k the reader should spend
overflow (unless the integrator's input is always zeroes). Also note that harmful overflow
.5, and 4.6.
is easy to detect since it will only occur when the two inputs are the same polarity
(positive or negative). If the MSB of the two input words is a 0 (I) then the output word's
Qillp.u.t After extensjon MSB must be 0 (l) . If it's a I (0) then we know overflow occurred. In simpler terms, if
1(0) 11111100(-4) the two inputs are positive (negative) then the output must be positive (negative).
(1) 1111 1101 (-3)
1(2) 1111 1110 (-2) Adding two's complement numbers A Out (A+B)
(3) 11111111 (-1) 0011 (+3) 0011 0110 (+6)
A (3-bits) 1-----"...... ( 4-bits)
1(4) 00000000 (0) ---'---3I>---l 1100(-4) 1100 (-4) 1000 (-8) OF!
(5) 00000001 (1) 1111(-1) 0001 (+ 1) 0000 (0) OF!
B (3-bits) ,
1(6) 00000010 (2) -'--i--)-----' 0011 (+3) Illl (-1) 0110 (+2)
(7) 00000011 (3) 0001 (1) 1100 (-4) 1101 (-3)
Extend the sign-bit
nent word 1100 1111

lsion + 1100 +0001
VOOO (-8) ~1 0000 (0)
wo's complement and
Overflow (OF!), toss into the bit bucket (ignore).
Figure 4.7 Showing how two's complement numbers are added.

Subtracting Numbers in Two's Complement Format

Figure 4.8 shows how two's complement numbers are subtracted. Here we are subtracting
the input B from the input A. In order to do this we complement B (run the N-bit word I-bitinpuL x[nTs
through N inverters). We then tie the carry input of the adder high. Shown in Fig. 4.8 are Input c1ocL=:-:=-_
several examples of subtraction. Note, again, how we extended the sign bit to ensure no j,.....nsLrL
harmful overflow occurs.
Subtracting two's complement numbers Reset every K c\(
A (3-bits) Figu
--'--:-~---I
B (3-bits)
-:...,~.-~~~
Extend the sign-bit
, Invert the word we are subtracting
A B B+ 1 Out {A-B) The transfer function for tr

0011 (+3) 1100(-4) 0100 (+4) 0111 (+7)
1100(-4) 1100 (-4) 0100 (+4) 0000 (0) OF!
1111(-1) 0001 (+1) 1111 (-1) 1110 (-2) OF!
0011 (+3) 1111 (-1) 0001 (+1) 0100 (+4) We'll see this equation fn
0010 (+2) 0001 (+1) 1111(-1) 0001 (-1) employs decimation, see ~
output word rate. More (
Figure 4.8 Showing how two's complement numbers are subtracted. magnitude of the frequenc:
4.2 Sine-Shaped Digital Filters

Perhaps the most useful digital filters that we'll encounter when doing mixed-signal
circuit design have Sine-shaped responses. Let's start this section by discussing one ofthe
simplest of these filters.
4.2.1 The Counter
Figure 4.9 shows how a counter can be used as a digital filter with a I-bit input. If we
assume the clock frequency is Is (= I IT,) and the counter is read out and reset every KTs
seconds then a constant input of Os (-1 in two's complement, see Fig. 6.3» will result in a Figure 4.10 shows the frec
counter output of 0 (-K) at the end of the time interval KTs seconds. A constant input of for large K and small frequ
logic I s results in a counter output of K. An input of alternating I s and Os (the input is a
50% duty cycle squarewave with a frequency ofls 12) results in an output of KI2 (0 for
two's complement numbers). The output of the counter is related to its inputs using
K-H Figures 2.30 and 2.31 in C
y[Ki· Tsl = L x[n· TsJ (4.7) from a Sinc response filter
n=K(i-l )
characterize all of the Sine
This equation simply indicates that we are taking K inputs, adding them together, and the
result is the output of the filter (so we can think of this filter, like any lowpass filter, as
an averaging filter). Rewriting Eq. (4.7) in the z-domain, Note, again, if we input a I
K-J 4.1 0). If our input is 101'
U(_) Y(z) Lz-n=l+z-1 + ... +Zl-K (4.8)
11'L. X(z) output is K12. However, I(
=0
input of 101010 is a squar
d. Here we are subtracting

Counter
ent B (run the N-bit word I-bitinp x[nTs) , - _ - , y[Ki· Ts]
igh. Shown in 4.8 are Input clo"":"--:=-=_ _ _--i h Y - K-bits
1 the sign bit to ensure no j,...fl.IUL Output
fslK
Reset every K clock cycles so counter can count from 0 to K.
:Figure 4.9 Using the counter as a digital filter.
-I
subtracting 1
~·(I+z-1
H(z) + ... (4.9)
l-z- 1
t (A-B) The transfer function for the counter is then
1 (+7)
K
)0 (0) OF! H(z) = I-z- (4.10)
0(-2) OF! 1 -z -I
)0 (+4)
We'll see this equation frequently so let's spend some time on it. Note that the counter
II (-1)
employs decimation, see Sec. 2.1.2, since the input word rate is K times faster than the
output word rate. More on this in a moment (since aliasing will be a concern). The
are subtracted.
magnitude of the frequency response ofEq. (4.10) is given by
. (K 'X)i\,
sm 1t
IH(j) I (4.11 )
when doing mixed-signal
n by discussing one of the
Sine( 1t¥)
. with a I-bit input. If we IH(j)I=K. (4.12)
ld out and reset every KT, Sine ( 1tf;)
e Fig. 6.3)) will result in a
Figure 4.10 shows the frequency response of the counter (see, also, Fig. 2.29). Note that
:onds. A constant input of for large K and small frequencies this equation can be approximated using
g 1s and Os (the input is a
.n an output of K12 (0 for (4.13)
i to its inputs using
Figures 2.30 and 2.31 in Ch. 2 relate the amount of attenuation and droop we can expect
(4.7) from a Sinc response filter for various values of K. Again, these equations can be used to
characterize all of the Sinc filters in this section.
ing them together, and the
ike any lowpass filter, as
Note, again, if we input a DC value of constant 1s then the counter's output is K (see Fig.
4.10). If our input is 101010 ... or 11001100... or 111000111000 etc. then the counter
-2+ ..• + Z 1-K (4.8) output is K/2. However, looking at the filter response seen in 4.10 and knowing an
input of 10 10 lOis a squarewave with a frequency of f)2, we would expect the counter's
128 CMOS Mixed-Signal Circuit Design Chapter 4 Digital Filter
Using a counter
/H(f)/
A Sinc(Kn . f,) the significant amount
/H(f)/ didn't discuss problem
K
sinin· L) counter's uses, howevel
" Is
See Fig. 2.30 as some sensing appli(
shrunk down to limit th
(review Fig. 4.10) .
•••
K~ K K K
The counter's input wa
2K Counter's output word rate can be used, Fig. 4.12,
K clock cycles (note
Figure 4.10 Frequency response of a Sine-shaped digital filter. accumulator, seen in Fi
hold register and the su
output to be zero (and it is if we think in terms of two's complement numbers). However, filtering behavior of th'
let's look at the operation in terms of binary offset numbers.
maximum input word's
Let's assume K is 8 and the counter is clocked at a frequency of 100 MHz. The summation of K, N-bit,
I-bit word rate coming into the counter is at 100 MHz while the counter is read out every wide (rounding up
12.5 MHz (decimation by 8). Figure 4.11a shows the frequency response of the counter accumulate-and-dump f
and the first-harmonic of the input of 1010101... or a squarewave at 50 MHz. We only
concern ourselves with the first harmonic of the squarewave to keep the figures from
getting too cluttered. A sinewave at 50 MHz, see Eqs. (1.85), having a peak-to-peak
amplitude of I, or a peak amplitude of 0.5, is represented at ± 50 MHz with dirac-delta
functions having amplitudes of 0.25. Figure 4.11 b shows the input signal spectrum after Input, N-bits
resampling at the output rate of 12.5 MHz (note the aliasing of the sampled signal at DC).
In (c) we see that after including the counter's Sine-shape response all of the tones
disappear except for the aliased tone at DC (and tones at 100 MHz, 200 MHz, etc.) The
output of the counter, which is read out as the counter is reset every KTs seconds, (that is Input clockJlJ
we don't look at the output of the counter while it's changing) is a constant value of 4 (that Is
never changes) even though the input is a 50 MHz squarewave.
Reset every K cl
Counter's frequency response
8 Input, 10101...,50 MHz

(a) Counter's response 4.2.2 Lowpass Sine I
and input signal. Input signal
37- 5 Reviewing Eq. (4.10) or
0.25/ filter without the decin::
I,MHz 4.13 shows how cascad
seen in this figure are se
K. Note how, to get the I
(b) Sampled input spectrum 0.5 intuitively make sense
highpass Sinc-response
I,MHz on the unit circle. Noti,
4
(c) Counter's output spectrum. signal (where the droop
Tones at 100, 200, etc. MHz
not shown.
·~/,MHz
Figure 4.11 Showing how decimating using a counter results in aliasing.

Using a counter as a digital filter, as we've just seen, has limited uses because of
the significant amount of aliasing that occurs with the inherent decimation. Note that we
:lU)1 didn't discuss problems that occur when the input signal contains noise. One of the
counter's uses, however, is in applications where the desired signal is constant (DC) such
as some sensing applications. By using really large values of K the bandwidth can be
shrunk down to limit the effects of noise while at the same time amplifying signals at DC
(review Fig. 4.l0).
f
, .. The Accumulate-and-Dump
The counter's input was a I-bit word. For N-bit input words the accumulate-and-dump
can be used, Fig. 4.12, in place of a counter. The input signal is summed in a register for
K clock cycles (note that this is the non-delaying integrator, also known as an
.igital filter. accumulator, seen in Fig. 1.26). At the end of this time the sum is clocked into an output
hold register and the summing register is reset (the integrator is reset). The equations and
ment numbers). However,
filtering behavior of the accumulate-and-dump are exactly the same as the counter. The
maximum input word's value is 2N - I (all N bits high). In order to accommodate the
quency of 100 MHz. The summation of K, N-bit, input words the register size used must be at least N + log2K bits
e counter is read out every wide (rounding up to the nearest integer). The frequency response of the
:y response of the counter accumulate-and-dump filter or the counter at DC is K.
rave at 50 MHz. We only
to keep the figures from
i), having a peak-to-peak : Accumulator or
. non-delaying
50 MHz with dirac-delta : integrator
I1put signal spectrum after Input, N-bits x[nTs]: + }--~--t-~--l
:he sampled signal at DC).
response all of the tones
\IlHz, 200 MHz, etc.) The
:very KTs seconds, (that is Input clockJ1Sl.fL· Dump sum into
this register.
a constant value of 4 (that Is .
r-L:...:..:..: lsiK
Res-et-e-v-e-ry-K-=-=c=lo=c=k=-c....:y=c=le=s=.~.>-------!.!-~4 . -.-~
Figure 4.12 The accumulate and dump.

101...,50 MHz
4.2.2 Lowpass Sine Filters
Input signal
Reviewing Eq. (4.10) one may wonder if we could implement this lowpass Sinc-response
)25/ filter without the decimation inherent in a counter or an accumulate-and-dump. Figure
£;. f,MHz 4.13 shows how cascading a comb filter with an integrator implements Eq. (4.10). Also
60 seen in this figure are several z-plane plots and frequency responses for varying values of
K. Note how, to get the lowpass response, we simply cancel the zero at DC (if this doesn't
. 0.5 intuitively make sense review Sec. ] .2.3). We'll show that to implement bandpass or
highpass Sinc-response filters all we do is cancel a zero using a pole at some other point
Lf,MHZ
on the unit circle. Notice in Fig. 4.13 that we've defined the bandwidth of the desired
signal (where the droop is -3.9 dB, see Figs. 2.31 or 4.10) using
~f,MHz B= (4.14)
2K
:ults in aliasing.
Change into two's com

and extend sign ~~
Integrator, Fig. 1.26
Y(z) ~8-bit
ADC
~
8 .
Comb filter, Fig. 1.25
IH(f)1
I z-plane
i, Is K=2 H(z) = 1 900mV
'C?v:
I-z
810mV
••• nOmV
» fin (Hz) 6]OmV
~
5~OmV
4 • ,,
450m'l
, K=4 360mV
L087~~~ •••
270mV
) 180mV
Bfsl4 fsl2 3.!s14 : 90mV
OmV
C
Figure 4.15 Inpul

K 8
H(z)
•••
) Example 4.4
Determine, and ske'
B
Is withK= 8.
The transfer functiOl
Figure 4.13 Lowpass Sine-response filters with varying values ofK.
h
Example 4.3 The time domain reI

Assuming an 8-bit input word sketch the implementation of the Sine-shaped filter
y
I _Z-8
l-Z-l Note that the output

(4.7). The time-dar
What is the output word size? Using SPICE verify that the filter's frequency shown in Fig. 4.16. 1
response is given by Eq. (4.13) with K = 8. Assume]; == 100 MHz.
The output of the filter is the sum of K, N-bit, words so the filter's output word
size must grow to
Output word size == N + log2K (4.15)
For this example where K = 8 and the input word size is 8-bits the final output
word must grow to II-bits. The filter is sketched in Fig. 4.14.
Figure 4.15 shows the filter's input and output when the input frequency is
6.25 MHz (==f,l2K). As seen in Figs. 4.10 and 2.31 the filter's attenuation is -3.9
dB or 0.638. The phase shift is 78.75 degrees (see Eqs. [1.54] and [1.63]).• Figur,
ed-Signal Circuit Design Chapter 4 Digital Filters 131
Change into two's complement . . Change back to

and extend sign bit b L Extend the SSfn-bIt by 2 == log2 K 1~binary offset format.
~
Integrator
Figure 4.14 Digital filter sketeh for Ex. 4.3.

z-plane
810mV
720mV
:::::1/::.
1-- H(z) = 1- ,-'
36omVr:::
270mV- .......... ..
180mvi- ............ :
90mV4... .
omv+ i I i I
Oos 1000' 200ns 300m; .400ns 500ns
1--- H(z) = 1
Figure 4.15 Input and output of the filter in Fig. 4.14 at a frequeney of6.25 MHz.
Example 4.4
Determine, and sketch, the time-domain impulse response of an averaging filter
withK= 8.
The transfer function of the filter is given by Eq. (4.1 0) or
g values of K.
H(z) = 1 I+Z~1+z-2+ + + z·5
l-z
The time domain relationship between the input and the output is then
the Sinc-shaped filter
y[nTsJ x[nTsJ+x[(n I)TsJ+x[(n-2)TsJ+ ... +x[(n-7)TsJ
Note that the output is simply a sum of the inputs over time, KTs' as seen in Eq.
(4.7). The time-domain impulse response of the first-order averaging filter is
the filter's frequency shown in Fig. 4.16. Note the rectangular shape .•
MHz.
le filter's output word x[ nTsl
1• Impulse input
(4.15) -++-+-1-11-+1""'IH-I-+-I-11-+1""'IH-I-+-I-II-~) time, niTs
o
8-bits the final output y[nTsJ
~.
:he input frequency is

~r's attenuation is -3.9
1 !TTTTTTT• •o::u;
o 1 2 3 4 5 6 7 8 9 10 II
)0 time, niTs
54] and [1.63]) .• Figure 4.16 Impulse response of a K = 8 averaging filter.

132 CMOS Mixed-Signal Circuit Design Chapter 4 Digital Filt
Averaging without Decimation: A Review

The counter and the accumulate-and-dump discussed in Sec. 4.2.1 performed averaging
and decimation in one stage. In other words, for example with K 4, it summed four
input samples, as shown in the sequence below, and passed the result to the output:
B = 0.5(f,IK
First output Second output
~---'-----~, ~,-------~,
x(l) + x(2) + x(3) + x(4) + x(5) + x(6) + x(7) + x(8) + x(9) + ... (4.16)
where the output clocking frequency is, as seen in Fig. 4.9, J.JK. For the lowpass
Sinc-response (averaging) filters discussed in this section
Finst output
Figure 4.17
x(l) + x(2) + x(3) + x(4) + x(5) +x(6) + x(7) + x(8) + x(9) + ...
Second output
I ,
Example 4.5
x(l)+ x(2) +x(3) +x(4) + x(5) + x(6)+x(7)+x(8)+ x(9) + ...
Repeat Ex. 4.4 if!
Third output
The transfer funct
x(l)+x(2)+ x(3)+x(4)+ x(5)+x(6) + x(7) +x(8) + x(9)+ ...
~---~---~
Fourth output
x(1)+x(2)+x(3) + x(4) + x(5)+x(6)+x(7)+x(8)+ x(9)+ ...

H(z) [LL
-z
I
The time domain J
(4.17)
y[nTd =x[nT,] +
where the outputs of the averaging filter occur at the same rate as the inputs, J,. The
z-domain representation of the Sine filter in Fig. 4.13 is the same as the counter or the The impulse resp(
accumulate-and-dump's transfer function the triangular shaI
lasts twice as long
y(nTs) x[nTs]+x[(n-1)Ts]+x[(n-2)Ts]+ ... ~Y(z) X(z)(l+ +z-2+ ... + z 1-K)
(4.18)
or, again, a filter response given by Eq. (4.10)
Cascading Sine Filters
The transfer function of a cascade of L of these Sine-response filters can be written as
1
H(z) = [ 1 =:-1-KJL (4.19)
KL. rSinc(KnfJ ]L Figure 4,]

IHU)I (4.20)
_ Sinc( nf) Finite and Infinite 1m!
The attenuation through a cascade of L Sinc lowpass filters, see Eqs. (2.38) and (2.39) is At this point a short n
in Fig. 1.24 (or Fig..
!=K
I Mainlobe
First sidelobe
L .sin L (1.5n)""L.13dBforK>8
" K
(4.21)
impulse response (FU
the comb filter causes
while the droop at !s/2K, see Fig. 4.17, is is applied and a -I }
Droop = [K. sin (2~) TL ""L· (-3.9) dB for K':2. 8 words, the impulse r,
(4.22) differentiator are also,
their inputs (the outpu'
ted-Signal Cifcuit Design Chapter 4 Digital Filters 133
IH(f) I
L ·3.9 dB
.2.1 performed averaging
:1 K = 4, it summed four
~.~~ -"
esult to the output:
B = 0.5(1s1K) L· 13 dB
+x(9)+ ... (4.16)

" f,IK. For the lowpass , fslK 2(fslK) 3(j,1K) f
is/(2K)
Figure 4.17 General frequency response ofa lowpass Sine (averaging) filter.
+ x(9) + ...
Example 4.5
~)+ x(9) + ...
Repeat Ex. 4.4 ifanL = 2 averaging filter is used.
The transfer function of the filter is
s)+ x(9) + ...
H(z) [ I - z-8
l-z-I
J2 = 1 + 2z- 1 + + 4z-3 + 5z-4 + ... + 3Z-1 2 + 2Z- 13
8) + x(9) + ...
The time domain relationship is
(4.17)
y[nTsl x[nTs]+2x[(n 1)Tsl+3x[(n-2)Tsl+ ... +2x[(n-13)Ts]+x[(n 14)TsJ
rate as the inputs,],. The
arne as the counter or the The impulse response of the L 2 lowpass Sinc filter is shown in Fig. 4.18. Note
the triangular shape of the curve and how the impulse response of the L == 2 filter
lasts twice as long as the L = 1 filter's response in Fig. 4.16 .•
(4.18)
y[nTs l
8
iIters can be written as
(4.19) ..l-f-t-+--+-+-f-t-+--+-+-f-t--'--'-.-.t~ time, nITs

o 1 2 3 4 5 6 7 8 9 101112 13 14 15 16
(4.20) Figure 4.18 Impulse response of an L = 2 averaging filter with K = 8.
Finite and Infinite Impulse Response Filters

: Eqs. (2.38) and (2.39) is At this point a short note concerning digital fiIter names is in order. The comb filter seen
in Fig. 1.24 (or Fig. 4.14), or the differentiator in Fig. 1.19, is an example of a finite
13 dB for K~ 8 (4.21) impulse response (FIR) digital filter. Applying a unit amplitude impulse to the input of
the comb filter causes the output of the comb filter to go to a 1 at the moment the impulse
is applied and a -1 KTs seconds later. The output is zero at all other times. In other
words, the impulse response of the filter has a finite duration. The comb filter and
3 for K ~ 8 (4.22)
differentiator are also called non-recursive filters since their outputs are only a function of
their inputs (the output isn't fed back and used in the filter).
134 CMOS Mixed-Signal Circuit Design Chapter 4 Digital Filtel
The integrator (also sometimes called an accumulator) shown in Figs. 1.26, 1.28,
and 4.14 is an example of an infinite impulse response (IIR) digital filter. Applying a unit
amplitude impulse to the input of the digital integrator, with zeroes the remaining times,
In --I-
causes the output of the integrator to increase to one and remain at one indefinitely. In
other words, the output response of the integrator is of infinite duration. The integrator is
also called a recursive filter since its current output value is a function of previous output
values. Any digital filter with a denominator is a recursive filter. Figl
While the averaging filters seen in Figs. 4.13 and 4.14 use an integrator (IIR
section) and a comb filter (FIR section), overall, as seen in the previous two examples, it The time-domain repre
exhibits FIR behavior. Further, since the averaging filter's output is only a function of its
y[nTs] =
inputs, as seen in Eq. (4.17), it is a non-recursive filter.
4.2.3 Bandpass and Highpass Sine Filters . It's desirable to determ
So far we've focused on lowpass filters. There are many situations, especially in value that results in a 1
communication systems, where we may want to filter or perform data conversion on a bandpass filter with tri'
range of frequencies that doesn't extend from DC to B (= j,/2K). Bandpass ADCs and delays and additions s'
DACs, for example, are popular in communication systems. In this section, we introduce investigate is /s/4. At
bandpass and highpass sine-shaped filters. comb filter transfer fun
Canceling Zeroes to Create Highpass and Bandpass Filters

In Fig. 4.13 we saw that we can generate a lowpass filter by canceling the zero at DC in a
The magnitude and z-pl
comb filter. We can generate a highpass, or differencing, filter by canceling a comb filter
zero at is 12 , as seen in the example shown in Fig. 4.19 with K 8. The same equations,
Eqs. (4.21) and (4.22), can be used to describe the behavior of this filter where, in the
highpass response, the main lobe has shifted to j,/2. Also, when looking at Fig. 4.19,
remember that the frequency response of a digital filter is periodic with period Is.
l-z- 8 ", Z8 -I
8 1 +z-l z7(z+ 1)
j,/4 J
•••
t
fsl2
Figure 4.21 A ban,
is 14 Is f
3j,/8 We can determ
procedure used to deten
Figure 4.19 A highpass filter implementation using a comb filter.
We can generate a bandpass filter by canceling the zeroes at j,/4 and 3/s 14, or
some other frequencies, using a digital resonator. The general topology of the bandpass
digital filter is shown in Fig. 4.20. Keeping in mind that the digital resonator is used to
cancel the zeroes ofthe comb filter, we can write At the center of the pas~
first side lobe, on eithe
response and is calculat.
(4.23)
(ed-Signal Circuit Design Chapter 4 Digital Filters 135
hown in Figs. 1.26, 1.28,

ital filter. Applying a unit Comb filter
roes the remaining times,
In Out
lin at one indefinitely. In
iuration. The integrator is
mction of previous output
Figure 4.20 Implementing a sine-shaped bandpass filter.
l4 use an integrator (IIR
previous two examples, it The time-domain representation of this equation is
lIt is only a function of its
y[nTsl = cos2 l21tZJ .y[(n l)Tsl - y[(n 2)Tsl + x[nTsl (4.24)
It's desirable to determine at which frequencies the cosine term is an integer, zero, or a
situations, especially in value that results in a trivial multiplication, that is, a shift so that we can implement the
Jrm data conversion on a bandpass filter with trivial multiplications. In other words, we want a filter that uses only
uq. Bandpass ADCs and delays and additions so that its implementation is simple. The first frequency we will
this section, we introduce investigate is /s/4. At this frequency the cosine term is zero and the digital-resonator/
comb filter transfer function (the bandpass transfer function in Fig. 4.20) reduces to
1 -K
H(z) := -=L (4.25)
1 +z-2
lceling the zero at DC in a
The magnitude and z-plane response of this filter, for K 8, is shown in Fig. 4.21.
by canceling a comb filter
8. The same equations,
Jf this filter where, in the
,hen looking at Fig. 4.19, Z8 - I
lic with period is. I + z-2 Z6(Z2 + 1)
'\
DC
f
Figure 4.21 A bandpass filter implementation using a comb filter and digital resonator.
We can determine the magnitude response of Eq. (4.25) following the same
procedure used to determine Eq. (2.38). The result, for the f,/4 resonator, is
l eomb filter.
~roes at 1,/4 and 3f,14, or (4.26)

I topology of the bandpass
iigital resonator is used to
At the center of the passband, that is f,/4, IHU)I = K/2. The ratio of the main lobe to the
first side lobe, on either side, is plotted in Fig. 4.22 along with the lowpass Sinc filter
response and is calculated using
Main lobe I K . 31t (4.27)
(4.23) IFirst side lobe = '2 .sm K
dB Low pass resp?nse

The implementation is
13t
I Main lobe I T
First sidelobe 9-1
11 T
.,
Bandpass response when I:: /,/6 orl,./3
x[nTs]
+
7
st
1
Ii;;,dP~' .ttenn.tion whenf = /,/4
Example 4.7
Fig!
Assuming an 8-bit If
3 I I ~ I ) bandpass filter
3 4 6 8 \0 12 16 K
Figure 4.22 Lowpass and bandpass filter attenuation versus number of comb filer zeroes, K.
V.rhat is the output v
The cosine term in Eq. (4.24) can be set to ±l when 1= Is 16 or 1s13 resulting in a response is given by E
bandpass filter. It should be clear that with the appropriate choice of sampling frequency,
number of zeroes K used in the comb filter, and value of the cosine term, many different The sketch of the fil
combinations of simple bandpass filters can be implemented using these techniques. Again, the word size ~
There are, however, only a few resonators that can be implemented using binary numbers. is 8, the word grows:
The resonators' coefficients must be such that the poles perfectly lie on the unit circle and filter and 2-bits in tht
cancel the comb filter's zeroes on the unit circle. when the input is 25 .r-.
verify that Eq. (4.26)
The ratio of the main lobe to the first sidelobe for 1= 1s16 or /,/3 IS given, 12.5 MHz the filter's
assuming K = 12,24, ... , by frequency response). ,
is
Main lobe I K sin U;)
(~~)sin (~- i;)
sin
IFirst side lobe - ----si-n-=----:: 1.15Ksin (4.28)
IH(f)1
which is approximately l3.5 dB for K = 24,36,48 ... and 10.15 dB for K = 12, 4.22.
In order to increase the amount of attenuation between the main lobe and the first
where, since we norm
side lobe in a bandpass filter implementation, we can cascade filter sections (as we did in
equals the output), th
the lowpass filter implementations discussed earlier). For example, cascading five 1s14 we'll see that we can .
bandpass filters with K == 8 will result in an attenuation of 57 dB. Also, note that by
they don't contribute tl
changing the sampling, or filter clock frequency J.. , we can easily change the bandpass
filter's center frequency. A change in the clock frequency, and its selection, can easily be
implemented using a counter and some control logic.
Example 4.6
Sketch the block level circuit diagram for an 1s14 digital resonator.
From Eq. (4.24) the time domain representation of the 1,/4 resonator can be
written as
I
ed-Signal Circuit Design Chapter 4 Digital Filters 137
y[nTsJ = x[nTsJ - y[(n 2)T,J

The implementation is shown in Fig. 4.23 .•
dB
x[nTsl -+--+--1 I----+---~-.--- y[nTs l

I
H(z)
1 +Z-2
~'hen 1 =ls 6 or j~:3 1,/4 resonator
Figure 4.23 Implementation ofa digital resonator.
Example 4.7
Assuming an 8-bit input word, sketch the implementation of the Sinc-shaped
I )0 bandpass filter
K L£:
1 +z-2
er of comb filer zeroes, K.
What is the output word size? Using SPICE verify that the filter's frequency
fs/6 or 1s13 resulting in a response is given by Eq, (4.26) with K = 8. Assume j~ = 100 MHz.
:e of sampling frequency,
sine term, many different The sketch of the filter is seen in Fig. 4.24 (note the similarity to Fig. 4.14).
using these techniques. Again, the word size grows by log2K from the input to the output Here, where K
ted using binary numbers. is 8, the word grows 3-bits, to an output word size of II-bits, (I-bit in the comb
{ lie on the unit circle and filter and 2-bits in the resonator). Figure 4.25 shows the output of the resonator
when the input is 25 MHz (= J,J4). It can be useful to vary the input frequency and
verify that Eq. (4.26) is correct. For example, if we change the input frequency to
1=I s l6 orls13 is given, 12.5 MHz the filter's output is zero (this is the first adjacent zero point in the
frequency response). When the input frequency is 15 MHz, the output of the filter
is
I1t)sin(lL
!K \3 2K
(4.28) 3n) sin (Knf,) sin (8n&)
IH(f) I 0.5881
= -
0.588 = 1 -) 0.25 (scaled by 4)
IB for K 12, Fig. 4.22. cos (2nl1~o)
1
= cos (2n:f,)
he main lobe and the first
where, since we normalize the filter's output so that passband gain is I (the input
Iter sections (as we did in
equals the output), the output of the filter is 0.25 the input. In the next chapter
nple, cascading five 1s14
we'll see that we can throwaway some of the lower bits in the output word since
7 dB. Also, note that by
they don't contribute to an increase in the SNR.•
.sily change the bandpass
ts selection, can easily be Change into two's complement , , Change back to
and extend sign bit b . 1. Extend the SIgn-bit by 2 = \og2 K 1 binary offset format
~ ~ JC"
)nator.
Resonator
(.,J4 resonator can be
Figure 4.24 Digital filter sketch for Ex, 4,7.
summation of the frequenl

variable width. Note that (
.the final result. This is t,
outputs.
4.2.4 Interpolation usir
We saw back in Sec. 2.1.5
of the digital data. This"
placed on the reconstructi,
Fig. 2.28. Before we disc
"Why can't we use an inpu
Examine the block
anti-aliasing filter (AAF)
Figure 4.25 Input and output of the filter in Ex. 4.7 at Is 14.
ADC is a sample-and-h,
attenuation at the Nyquist
Frequency Sampling Filters
Fig. 2.29 and the associat
Consider the topology of a comb filter and resonators shown in Fig. 4.26. We are feeding provide an additional Sine
the output of the comb filter through the resonators (with different center frequencies) and Ex. 2.2) repetitively samp
then using the combined sum of the resulting bandpass filter responses (the Sinc shapes) Since the input signal in I
to build a bandpass filter. This is exactly the same as reconstructing a waveform in the isn't affected by another Si
time domain using an ideal RCF, as discussed in Ch. 2, except now we are using the
Digital resonators
Comb filter
In Out
Figure 4.2'
Note that because,

experienced the associatel
discussions in this sectiOl
designs that do use zeroes
Sinc responses a Sinc-response filter then
does introduce a Sinc-res]
when performing interpoia
The next question i
The answer to this come:
Sidclobes not shown
important component of an
Figure 4.26 A frequency sampling filter.

summation of the frequency domain Sinc responses to generate a bandpass filter with a
variable width. Note that every other digital resonator is subtracted rather than added to
the final result. This is to account for the phase reversal between adjacent resonator
outputs.
4.2.4 Interpolation using Sine Filters
We saw back in Sec. 2.1.5 that an interpolator is a circuit that increases the clocking rate
of the digital data. This was useful for, among other things, reducing the requirements
placed on the reconstruction filter. The simplest interpolator was the input hold register,
Fig. 2.28. Before we discuss interpolation using Sine filters let's answer the question
"Why can't we use an input hold register for interpolation here?"
1-10n5
Examine the block diagram in Fig. 4.27. The ADC is clocked at a rate ofls so the
anti-aliasing filter (AAF) limits the ADC's input spectrum to /,/2. On the input of the
1.7at/s 4.
ADC is a sample-and-hold (SIR) with a Sinc-shaped spectral response (-3.9 dB
attenuation at the Nyquist frequency of 1s12, see Fig. 2.17). We might expect, based on
Fig. 2.29 and the associated discussion, that the hold register seen in Fig. 4.27 would
IFig. 4.26. We are feeding provide an additional Sinc-shaped response in the signal path. Rowever, remember (see
ent center frequencies) and Ex. 2.2) repetitively sampling and holding a signal results in only one SIR attenuation.
esponses (the Sinc shapes) Since the input signal in Fig. 4.27 sees this response when it passes through the SIR it
ructing a waveform in the isn't affected by another Sine-shaped response as it passes through the hold register.
ept now we are using the
=/s,ne w
1-+-'10-- Out
Figure 4.27 Interpolation using a hold register (see Sec. 2.1.5).
Note that because of this assumption that the data has passed through a SIR and
experienced the associated Sinc-shaped filtering, we won't use zeroes padding in the
discussions in this section. It should be straightforward to extend the discussions to
designs that do use zeroes padding. Also note that if the digital data hasn't passed through
ler response a Sinc-response filter then passing it through a hold register, as discussed in Sec. 2.1.5,
does introduce a Sinc-response (which, as we'll fmd out now, may often be desirable
when performing interpolation).
The next question is "Why would we want the signal to see additional filtering?"
Sidelobes not shown
The answer to this comes from reviewing Fig. 2.26. The image removal filter is an
important component of an interpolator. We can implement this filter using
1 z_
H(z}= __ -K JL (4.29)
[ l-z-l
140 CMOS Mixed-Signal Circuit Design Chapter 4 Digital Filtet
The benefit, for an interpolator, comes from realizing that if we clock the comb filter with The attenuation thr'
a slower clock, fJK, then one clock delay is KTs so we can simplify the comb sections
using Sine!
IH(/) I ==
I-z-K -* 1 (4.30) Sine
Figure 4.28 shows an interpolator implemented using a cascade of Sinc Filters. The
attenuation through the interpolator is given, see Eq. (2.37), by or, for L = 1,
attenuation betweel
Sinc(K1tf'~"") L
2.30. For LIthe
IH(/) I == (4.31) dB.
Sinc(1tf,~J Figure 4.29 she
the interpolator'!
Larger attenuation can be achieved by cascading more stages, L. Again, the word size
points. For L = 2 v.
grows by I-bit through each comb filter and by log2K - 1 through each integrator. Also
a more "rounded" c
note that if we were to use zeroes padding instead of the inherent hold register present in It can be instructiv
the topology (see discussion on previous page) a selector, see Fig. 2.26, would be added the resulting outpu
in between the comb filters and integrators to introduce K - 1 zeroes. drops as the input
•
In I :ot"'or (it:'" T d
ret')I . Out S60mV,
880mV
800ml'
Input word rate, Is Output word rate,KIs == Is.new 120mI"
640ml'
560ml'·
L sections L sections 4BOml'
~
/
~
~mm
... ~
~~'~.~
" /=:
/ ,,~~~~
...
_ _ _ _ _ _
r=Ll.out
)~
"
~/
400ml'
320ml'
240mV,
160mV
Clocked atfs Clocked at Kfs = is",,,,,,, 80mI"
0.1
Figure 4.28 Interpolating using Sine filters for image removaL

960mV
B80ml',
Example 4.8 BOOmV,
Using an 8-bit word, an input clock rate of 12.5 MHz, an input frequency of 1.1 nOmV·
MHz, and K = 8 determine the output word size, magnitude, and output clock rate 640mV,
5GOmV,
for interpolators with L = 1 and 2. Also determine the attenuation between the
480ml',
passband and the first sidelobe, see Fig. 2.29. Verify your results with SPICE,
400ml',
The Nyquist frequency is 6.25 MHz (the spectral content on the input of the ADC 320mV,
240mI"
should be < 6.25 MHz to avoid aliasing). The output clock rate is 100 MHz. For
HOmV
the case when L = 1 the word grows I-bit through the comb filter and 2-bits
80mV
through the integrators so the output word size is II-bits. When L = 2 the output 0,
word size is I4·bits. We'll see in the next chapter that the signal-to-noise ratio sets
the number of bits we keep on the output of the filter or in between adjacent Figure 4
stages.
'ted-Signal Circuit Design Chapter 4 Digital Filters 141
clock the comb filter with The attenuation through the filter is
mplify the comb sections L L
. (
Smc\Krc1;.new)
J I Sinc( 8rc;o~)
. (
sm \. 8rc]OO
II )
L
IH(f)1 = "" =(O.988)L

(4.30) Sinirc L ) II I
S'me ( niOO; 8nU
100
\ /S.Hew
:ade of Sine Filters. The
or, for L = 1, - 0.107 dB and for L = 2, 0.214 dB. We can estimate the
attenuation between the passband and first sidelobe using information seen in Fig.
2.30. For L = 1 the attenuation is roughly 13 dB and for L = 2 the attenuation is 26
(4.31 ) dB.
Figure 4.29 shows the simulation results. Looking closely we see that for L
the interpolator's output is simply a linear change between adjacent output
, L. Again, the word size
points. For L 2 we see additional phase shift (more delay through the filter) and
lugh each integrator. Also
a more "rounded" behavior indicating a better representation of the original signaL
mt hold register present in It can be instructive to vary the input frequency in these simulations and look at
Fig. 2.26, would be added the resulting output signals (especially showing how the output signal amplitude
~roes.
drops as the input signal moves closer to the Nyquist frequency of 6.25 MHz) .
•
V{vout_interpolated]
Out
~
ut word rate, Kis
tions L=l
~
.~ut
.~
--.~
Kis
0.2115 0.411S 0.611' 0.8115 1.01ls 1.211s 1.4110
~e removal. V!vout_no_lnterpotadonl
960mV,---=+=::.::.:::;..:::=::.c..,.--.---,--.--_--,
880mV
aOOmV
input frequency of 1.1 720mV
:, and output clock rate 640mV
tenuation between the 560mV .•.

L=2
4BOmV
:sults with SPICE.
400mV
1 the input of the ADC 320mV
: rate is 100 MHz. For 240mV-·
160mV
comb filter and 2-bits
80mV+---t---i---"r---i---r---i---r--'
When L = 2 the output O.Olls O.2~s 0.411s 0.611s 0.8ps 1.0\10 1.2115 lAps
gnal-to-noise ratio sets
,r in between adjacent Figure 4.29 Interpolation using one- and two-stage Sine filters.
Additional Control 4.2.5 Decimation using

In order to have an additional parameter for adjusting the image removal filter As seen in Fig. 2.12, resarr
characteristics, Eqs. (4.29) and (4.31), consider adding delay to our comb filter sections as passing the data through
seen in Fig. 4.30. section we discuss using a
4.1 O. The output word ral
limited to DC to f)2K (as!
L sections L sections Notice that, in the j
filter or differentiator befO!
overflow problems in the 1.
might try putting the integ
Clocked atis signals, or by using very
overflow problems altogetl
Figure 4.30 General interpolation using Sinc filters. (4.29)
Using this topology we can describe the filter's characteristics using
H(z:
H(z) -= l-z
_KM]L
[ (4.32)
I Z-I
and
r f \, L
SinclKM· n;;:;;:) or we can implement deci
IH(f)1 -= (4.33) the associated discussion).
Sinc( 1t f,:J that we are assuming thf
implementation of the deci
Figure 4.31 plots this equation. Note that the Nyquist frequency J/2) remains faetors of delay are implerr
unchanged since it's set by the sampling in the ADC. By using the factor M we can .an averager, 1 + , with a
achieve a narrower bandwidth but at the cost of more droop at the Nyquist frequency. The some authors, a CIC filtel
word size, in this filter, still grows by I-bit in every comb section and by log2K - 1bits in there aren't any integrators
the integrator sections. when using this decimatOl
increasing the order of the
iH(f)i
Sinc(Mn . f)
\H(f)1 =. j'
smc(n· K-jJ In
Desired spe:illJb!lI!._ Input word ralt
f h,ne'1' = K .Is
o M lvl
£
2M
Figure 4.31 Frequency response image removal tilter using a Sine interpolator, Fig. 4.30.
Cascade ojIntegrators and Combs

A quick note before leaving this section. The filters we presented are often labeled CIC
filters since they are formed by cascading integrators and comb filters. We'll continue to Figure'
avoid using this tenn for reasons that will become clear in the next section.
vfixed-Signal Circuit Design Chapter 4 Digital Filters 143
4.2.5 Decimation using Sinc Filters

the image removal filter As seen in Fig. 2.12, resampling digital data at a lower frequency (decimation) consists of
to our comb filter sections as passing the data through a digital anti-aliasing filter followed by resampling. In this
section we discuss using a Sinc filter, (4.10) and (4.12), with a response seen in Fig.
4.1 O. The output word rate of the decimator is I/K and the input desired spectrum is
limited to DC tofsl2K (as seen in Fig. 4.10).
ections
Notice that, in the filters we've covered so far in this chapter, we've put the comb
filter or differentiator before the integrators or resonators. This was to eliminate unwanted
••• overflow problems in the latter (which are recursive filters). After reviewing Fig. 4.28 we
might try putting the integrators before the comb filters. While this may work for small
t Kfs = Is.new signals, or by using very wide registers in the integrators, it would be better to avoid
overflow problems altogether. In order to move towards this goal lets write Eq. (4.8) and
r
lC filters.
(4.29)
teristics using
H(z) ~z-n
= [K-l =[I+z-1+ + ... +z !-K]L
(4.32)
=[(1 + . (1 + z-2) ..... (1 + )Y
(1 + . (1 + z-2)L ..... (1 + )L (4.34)
or we can implement decimation using only non-recursive averagers (see Fig. 1.16 and
(4.33) the associated discussion). The word size increases by I-bit through each averager. Note
that we are assuming the decimation is a factor of 2 here. Figure 4.32 shows the
implementation of the decimator. The registers are used to re-sample the data. The higher
frequency 1/2) remains factors of delay are implemented by clocking the registers with the slower clock (clocking
using the factor M we can an averager, I +z-I, with a clock of IsIK implements 1 + z-K). This topology is called, by
Lt the Nyquist frequency. The some authors, a CIC filter (see comment at the bottom of previous page) even though
ction and by I bits in there aren't any integrators present in the topology. Figure 4.33 shows example spectrums
when using this decimator. Note that the sidelobes alias into the desired spectrum. By
increasing the order of the filter L, we can reduce the effects of aliasing.
Sine ( Mn . f) Decimate (reduce word rate)

IH(f)1 = '
Input wo-:-r-a-te-,-f,+:-iI')......--I1 ~ K 1 - - o-u+/t-pu-il~ w-o-r-~-~:te,.fsI
... K
f f"new K ·Is
;inc interpolator, Fig. 4.30.

...~ (1 +Z. -1)L H ?
~
out
.&
K
,en ted are often labeled CIC
mb filters. We'll continue to Figure 4.32 Decimation using Sinc anti-aliasing filters.
: next section.
/,/16 Assuming K = 8 4.3 Filtering Topol

/./2
••• @ (' The Sinc filters discussl
(a) Input signal spectrum :7 J'
-·--------''''''''''----------------'»f circuit design, especiall

complicated multiplicat
characteristics and there
(b) Spectrum after AAF
. response. In this section
on the integrator. Most c
after resampling the last chapter covering
(c) ••• @/sIK
f 4.3.1 FIR Filters
\' h~=h~ hn h Towards understanding t
topology seen in Fig. 4.3:
Notice how the sidelobes alias into the desired spectrum
Figure 4.33 Spectrums when decimating and a Sinc anti-aliasing filter used.
If, for example, we set al
(4.9) and (4.10),
Example 4.8
Using an 8-bit word, an input clock rate of 100 MHz, an input frequency of 1.1
MHz, and K == 8 determine the output word size, magnitude, and output clock rate
for Sinc-decimators with L 1 and 2. Verify your results with SPICE. or, again, a Sinc-shaped
earlier, Figure 1.24, this t
The transfer function of the anti-aliasing filter inherent in the decimator is given
by Eq. (4.34) with K 8 and L 1 or 2. The output word rate is 12.5 MHz. The
simulation results are seen in Fig. 4.34. Note that the decimated output with L 1
looks essentially the same as the output with L = 2 (except for more delay when L In~_-
2). This (the shape of the outputs being more or less the same) wasn't the case
for the interpolator outputs seen in Fig. 4.29. For the interpolator, where aliasing
isn't a concern, increasing L results in a reduction in the aliased signals present on
the output of the interpolator. Increasing L allows the interpolator output to move
closer to the original input (in the extreme, L ~ ct:), and we get the original analog
waveform). By increasing the order, L, in the decimation filter we reduce the
aliased signals present in our desired spectrum, Fig. 4.34 .•
V(vout_no_decimation)
As another examp
shifting the word left two
bit increases the word s
hardware). Figure 4.36 sl
first-order RC circuits stc
simply reveals the filter's
heuristic approach can be
The benefits of us
recursive so no feedback
drawback is that they, fc
recursive structures we'll
Structures are subject to il
Figure 4.34 Decimating by 8, an example. overflow. Let's discuss the
AssumingK 8 4.3 Filtering Topologies

• spectrum @j, The Sinc filters discussed in the last section are very useful for general mixed-signal
circuit design, especially when interpolating or decimating, since they don't employ
complicated multiplications. Unfortunately, they also don't have sharp filtering
• Spectrum after AAF characteristics and there isn't a lot of flexibility when selecting the filter's frequency
\ >/ response. In this section we'll present some additional filtering topologies mostly based
on the integrator. Most of these topologies are directly related to topologies discussed in
r output after resampling the last chapter covering analog filters.
~ ... ~fjK 4.3.1 FIR Filters
Towards understanding the reason for this approach, consider the non-recursive FIR filter
topology seen in Fig. 4.35. The transfer function of the filter is
H(z)=Ao+A (4.35)
lliasing filter used.
If, for example, we set all of the filter's coefficients to 1 then we can write, as seen in Eqs.
(4.9) and (4.10),
l-z-4
input frequency of 1.1 H(z) (4.36)
l-z-I
e, and output clock rate
ith SPICE. or, again, a Sinc-shaped lowpass comb filter. When compared to the comb filters used
earlier, Figure 1.24, this topology has more adders.
the decimator is given
. rate is 12.5 MHz. The
nated output with L = 1
for more delay when L In~_.---I
~ same) wasn't the case

-polator, where aliasing
lased signals present on
-polator output to move
: get the original analog Out
,n filter we reduce the
I
Figure 4.35 A four-stage FIR filter.
ation)
As another example consider setting all of the coefficients to 0.25. This is done by
shifting the word left two bits or by extending the sign-bit by two bits. Extending the sign
bit increases the word size and ensures we don't lose resolution (but results in more
hardware). Figure 4.36 shows the resulting filter's step response. Note the similarity to a
first-order RC circuits step response. Also note that the impulse response for this filter
simply reveals the filter's coefficients (here all 0.25). Based on a desired step response a
heuristic approach can be used to design the filter.
The benefits of using FIR filters are that they are inherently stable (they are non
recursive so no feedback is used) and they can have linear phase (constant delay). The
drawback is that they, for a given number of delays, aren't as good at filtering as the
2.4ps recursive structures we'll talk about in the rest of this section. Unfortunately, recursive
structures are subject to instability. In addition, topologies using integrators are subject to
,e. overflow. Let's discuss these two issues before going any further.
x[nTs]
z-a
Ao =AI
A2 A3 =: 0.25
II.... !!!!!!!!
o
Step input
> time, niTs
y[nTs]
/t.. Output
11o •••• 'TT!!!!!

I 2 3 4 5 6 7 8 9 1011
) time,nlTs
Figure 4.36 Step response of a 4-stage FIR filter "With all coefficients set to 0.25.
4.3.2 Stability and Overflow

A weighted integrating filter is seen in Fig. 4.37. The output of the circuit is fed back to
Figure 4.
the input after it is multiplied by a. The output of the circuit in the time-domain may be
written as
y[nTs]=:x[(n-I)Ts]+a·y[(n l)Ts] (4.37)
Recall that when we use
or
the input/output word si
y[nTs] x[(n 1)Ts] + a· x[(n 2)Ts] + a 2 • x[(n 3)Ts] + a 3 • x[(n 4)Ts] + ... , (4.38) increased by I-bit for
which will obviously blow up if a> I. determining the register
. fed back and summed at
required can be challeng
output to wrap around (
X(z) Y(z)
vice-versa). In Fig. 4.~
Y(z) = [aY(z)+X(z)]z-1 saturates. This keeps tl
y(nTs) = a .y[(n 1)Ts] + x[(n 1)Ts] nonlinearities in the filte
U( ) = Y(z) instability. The question
Jl!Z X(z)
look at the carry out bit 1
a normal occurrence wh,
Figure 4.37 A weighted integrating filter. if the input sign bits an
positive then the output
The z-domain representation ofEq. (4.37) is . numbers. Figure 4.40 she
1
H(z) =: z-a (4.39)
Figure 4.38 shows the z-plane and magnitude plots for this equation. If a > 1 then H(z)
becomes unstable. So for a stable system we must require our poles to reside within the
unit circle. (There are no restrictions on the location of zeroes.) This sounds simple
enough; however, notice that we have, in most of the previously discussed digital filters,
placed poles right on the unit circle. If there is rounding in our digital numbers, we could
be faced with an unstable digital filter. This would be a very common occurrence in a
1000
digital filter implemented using software, if care was not taken to avoid rounding errors.
Since we use integer numbers in our hardware implementations, instability shouldn't be a (a) Integrator ove
problem unless we start to try to round numbers to decrease hardware complexity
(performing divisions or multiplications) without being careful. Figure 4.39
H(z) = = _I_ z-plane

input I az- I z-a
:,nITs
IH(f)1
tput a .~ ..
:,nITs _ ____
I
_ ___ L____
•••
_ ____ _
,
l+a . )
:fficients set to 0.25. 1s12 Is 3!s12 f
,f the circuit is fed back to

Figure 4.38 The z-plane representation and magnitude response
n the time-domain may be for a weighted integrating filter.
Overflow
I)Ts] (4.37)
Recall that when we used integrators with comb filters earlier in the chapter we increased
the input/output word size of the integrators by log2K 1 while the comb filter outputs
:[(n-4)Ts ]+ ... , (4.38) increased by I-bit for an overall increase of log 2 K. We calculated these values by
determining the register size required to sum K words. In a recursive filter the output is
fed back and summed at various points in the filter, so determining the exact register size
required can be challenging. Figure 4.39a shows how an integrator overflows causing the
output to wrap around (go from the most positive value to the most negative value or
vice-versa). In Fig. 4.39b we show the more desirable situation where the output
z) = [aY(z)+X(z)]z-l saturates. This keeps the filter from becoming unstable; however, it will introduce
nonlinearities in the filter's response. Nonlinearity at some extreme is usually better than
'z) = Y(z) = --='--_ instability. The question is, "How do we determine overflow?" We know that we can't
, X(z) I-a·
look at the carry out bit because, as we saw in Figs. 4.7 and 4.8, the adder overflowing is
a normal occurrence when adding two's complement numbers. What we do know is that
r. if the input sign bits are both 0 then the output sign bit must be 0 (if both inputs are
positive then the output must be positive). The same can be said for adding negative
numbers. Figure 4.40 shows how we can modify an integrator to avoid overflow.
(4.39) Olill
quation. If a> I then H(z)
r poles to reside within the
roes.) This sounds simple time time
OOOOO-!L---------~
sly discussed digital filters,
r digital numbers, we could
y common occurrence in a
n to avoid rounding errors.
1000 - t--- lOOO-t-
lS, instability shouldn't be a (a) Integrator overflow (b) Clamping the output when
ease hardware complexity overflow occurs.
Figure 4.39 Integrator overflow and clamping the integrator's output.

Note that in order for 0

lower than the filter's d
pole and zero are locatec
GJD « J and G3D » 1.
I--I-~-..- Y(z)
X(z) - __--i-~ Let's attempt to s
we see that the feedback
can be used to further a·
amplitude of the signal
operation, and we can pn
functionality, set G2 to 1.
blocks, as seen in Fig. 4.·
Figure 4.40 Modifying the integrator to avoid overflow. of the transfer function, I
4.3.3 The Bilinear Transfer Function

The bilinear transfer function and its implementation using an integrator and . Before attempting to sir
differentiator were presented back in Sec. 3.2.1. Figure 4.41 shows the digital show that, indeed, Eq. (4
implementation of the bilinear filter seen in Fig. 3.29. It's important, at this point, to see remember that
how the continuous-time implementation in Fig. 3.29 is directly implemented in Fig.
4.41. In particular we note that
(4.40)
where s = jro = j2rr./. Re\'
and so
_~-'- = _1_ . _1_+_1_''",-,-,-,--,-"",, (4.41 )

G2 1 +j . --'--
The location of the pole is given by

which is clearly the same
(4.42)
Example 4.9
while the location of the zero is at
Sketch, and determin
following RC circuit.
/3dB.zero (4.43)
In 10k
-
Integmtor
- . - - .
Vin
I;
If
-
Out
. Vout(f)
Differentiater
Figure 4.41 Digital implementation of the bilinear transfer function.

ixed-Signal Circuit Design . Chapter 4 Digital Filters 149
Note that in order for our filter to be useful the frequencies of interest must be much
lower than the filter's clocking frequency, 1,. In other words, the frequencies where the
pole and zero are located must be much less than 1,. This means, assuming G2 1, that
GlD« 1 and G)D» I.
Let's attempt to simplify this tilter. If we look at the transfer function, Eq. (4.41),
we see that the feedback gain, G z, simply scales the amplitude of the transfer function and
can be used to further adjust the location of the filter's pole. Because we can scale the
amplitude of the signal either before or after the filter, and independent of the filter's
operation, and we can precisely set the pole of the filter using G iD , we ean, without loss of
functionality, set G2 to 1. We can then rearrange the summing, delaying, and multiplying
blocks, as seen in Fig. 4.43. Using these results we can write the z-domain representation
overflow. of the transfer function, Eq. (4.41), as
VOltt(z) G lD (1 +G 3D ) Z-G3D/(l +GJD)
(4.44)
Vin(Z) == z-(l GlD)' z
using an integrator and Before attempting to simplify the filter implementation seen in Fig. 4.43 further, let's
4.41 shows the digital show that, indeed, Eq. (4.44) is equivalent to Eq. (4.41) whenl«f,. It will be helpful to
}ortant, at this point, to see remember that
'ecUy implemented in Fig.
::::: 1 - §.. if 1 «Is or z "" 1 + §.. "" _1-s "" if "" 0 (4.45)
h h 1 h J?
(4.40)
where s == jm == j2rrf. Rewriting Eq. (4.44) in the s-domain results in
Vout(f)
Vjn(f)
= Gl~( 1+ G3D)
1 + f, 1 + GlD
·ll (1 -7J's
) G3D/(l + G3D)J (4.46)
(4.41)
1+
(4.47)
1+
which is clearly the same as Eq. (4.41) when G2 = 1.

(4.42)
Example 4.9
Sketch, and determine the transfer function for, the digital filter equivalent of the
(4.43) following RC circuit. Assume the digital filter is clocked at 100 MHz.
10k
Integrator
VOllt(f) 1 1 +jro· lOOns
Out Vin(f) =2" l+jm·50ns
; Vout(f)
Figure 4.42 A simple first-order RC circuit.

ransfer function.
Comparing the tram

In
G3D = l'
fs
Out then we can use an
seen in Fig. 4.44. 1
the multiplication b
as desired at DC, w
0.1, and the output (
Out ~
LE
t:
Out
Out
H(z)
The Canonic Form (or

Studying Fig. 4.44, we
We see in this figure
(which, of course, is a r
is seen in Fig. 4.45. In
change because, now, t
write the output as
Vout(z)
Vin(Z) =
GlD
z-(1 G ID )
which is clearly the sa

Figure 4:43 Simplif}1ng the digital implementation of the bilinear filter. output is one clock cyt
response of the filter an
~ed-Signal Circuit Design Chapter 4 Digital Filters 151
Comparing the transfer function in Fig. 4,42 to Eq. (4,47), we see that if
= 100 ns -+ G 3D 10 and f = 50 ns -+ GlD = 0.2

is Gw ' s
Out then we can use any of the filters in Fig. 4.43. The sketch of the digital filter is
z-ll---+-_---'l>-
seen in Fig. 4.44. The multiplication of the transfer function by 112 is nulled by
the mUltiplication by GlDG3D 2), To verify that the filter in Fig. 4.44 functions
as desired at DC, we see that the output of the first stage is 0.5 when the input is
0.1, and the output of the second stage is 0.05 (with a 0,5 on its input).•
~t
g-l
t::J 0,8
----"'--- . (1 . 10/11)
l-GID
Figure 4.44 Digital filter from Ex. 4.9.
The Canonic Form (or Standard Form) ofa Digital Filter

Studying Fig. 4.44, we might wonder if we can further reduce the size of the digital filter.
We see in this figure that it may be possible to eliminate the second delay element
(which, of course, is a register) and use only a single delay. The result of this modification
is seen in Fig. 4.45. Intuitively we would think that the phase response of the filter will
change because, now, there is less delay in series with input of the second adder. We can
write the output as
V011f(Z)
--:
Vin(Z)
G lD G 3D II + G3D
G3D
.
1 Z-l
1
(1- GlD) 1
(4.48)
or
VOI"(Z)
--:
G ID (1 + G·3D ) . _z_G-,3:o:D....;/C,-1_+_G_3: .:; D, -) C4.49)
VinCZ) z-(l-GlD)
which is clearly the same response as derived in Fig. 4.43 or Eq. (4.44) except that the
le bilinear filter, output is one clock cycle, z, earlier. This reduced delay has no effect on the magnitude
response of the filter and little effect, assumingf«f" on the phase response of the filter.
152 CMOS Mixed-Signal Circuit Design Chapter 4 Digital FilteJ
Out Vout(Z)
f-"+---
Example 4.10
Using the canonic f
Comparing Eq. (4.~
2rrj3d8.p(
1
ADc=
Figure 4.45 Canonic form of a first-order digital filter. 2
The general form ofthis first-order canonic (or standard form) filter is seen in Fig.
4.46. The filter is termed canonic because the minimum number of delays are used. One and thus Bl == -0.9.
delay is used for each pole. Remember that in order for a digital filter to be realizable in implement the mult
hardware there must be fewer or an equal number of zeroes than poles in a filter's transfer
function. Let's do a quicl
apply 0.1 to the inp
4.42, the output of
Change to addition and negate B I input to the filter is
~~ AJ==I-G lD
According to Fig.
integrator is 1I[ 1
then be 0.5 - 0.45 0
Bo == GlD(l + G3D)
Bl =-GlDG3D
-I z+!!J.
H(z) = Bo+!i~=Bo' ~
I AlZ-I Z-Al
Figure 4.46 General canonic form of a first-order digital filter,
We can, again, derive the transfer function for the first-order bilinear digital filter.
This time, however, let's use the variables in Fig. 4.46. Again, assuming!« Is, and using
Eq. (4.45) results in
Figure 4.4
1+
H(f) = Bo +BI , _ _--"_ (4.50)
I-Al Example 4.11
Sketch the digital fi
where last chapter that has
the filter is clocked c
/,(l-A d (4,51)
/3d8,pole =: 2rr The filter's continu01
and
Using Eqs. (4.50) to

lxed-Signal Circuit Design Chapter 4 Digital Filters 153
and the gain at DC is
ADC (4.53)
Example 4.10
Using the canonic form of the first-order digital filter, repeat Ex. 4.9.
Comparing Eq. (4.50) with the transfer function in Fig. 4.42, we can write
I
2rcj3dB,pole == 50 ns
ADC=l=~..:.-;;;;;....!.. Bo+Bl
1-0.8 ~Bo+Bl 0.1
al filter. 2 I-AI
form) filter is seen in Fig.

2rcj3dB,zero 100 ns =Is· (I + ~~) 100YIHZ(~~) ~ Bo
er of delays are used. One
and thus B 1 -0.9. The filter's sketch is seen in Fig. 4.47, We will discuss how to
al filter to be realizable in
implement the multipliers later.
n poles in a filter's transfer
Let's do a quick check to see if the filter functions as desired at DC. If we
apply 0.1 to the input of the filter then, according to the transfer function in Fig.
4.42, the output of the filter should be 0.05 or one-half the input. Because the
ddition and negate B 1
input to the filter is a DC signal, both sides of the delay will have the same value.
/ According to 4.38, this value will be 0.5 (the output of the weighted
integrator is 1/[ I 0.8] times the input signal, here 0.1, at DC). The output will
then be 0.5 0.45 or 0.05 (as we would expect), •
~ + !!J.
.. B
Bo'--O
Z-Al
igital filter.
::>rder bilinear digital filter.
lssumingj «.t.:, and using.
Figure 4.47 Canonic form ()fthe first-order digital filter in Ex. 4.10.
(4.50)
Example 4.11
Sketch the digital filter implementation of the lowpass filter in Ex. 3.1 from the
last chapter that has a DC gain of 1 and a 3 dB frequency of 1.59 YIHz. Assume
the filter is clocked at 100 MHz.
(4.51)
The filter's continuous-time frequency response is given by
H(j) = ----"--
I +j.
(4.52)
Using Eqs. (4.50) to (4.53), we begin by calculating AI
154 CMOS Mixed-Signal Circuit Design Chapter 4 Digital Filt
f3dB,pole 1,59 MHz 100MHz(I_A1)-?A 1 09

2n . B
and then
Bo+BI Bo+B)
ADC = - - = 1 = - - -? Bo +B) 0.1
. I-AI I 0,9
Let's put the zero at infinity so it doesn't affect the transfer function
f 3dB,zero = 00 fs l( 1 Bo
2n +!!J..) ~ BoO and B I = 0,1
A sketch of the filter is seen in Fig. 4.48 .•
Figure 4.48 First-order digital filter in Ex, 4.1 L

Number of poles n ~ r.
General Canonic Form ofa Recursive Filter
Before leaving this section, let's show in Fig. 4.49 the general form of an nih-order canonic
digital filter (where n indicates the number of poles in the transfer function), The
z-domain transfer function of the filter is given by
4.3.4 The BiquadrCl
m m
LBjz-i L B1Zn-1 The digital biquad fil
H(z) = --,-i=O-'--n_ _ i~O
(4,54) 4.50. The transfer fun.
n
I LA;[i zn - L Ajzn-j
1=1 ;=1
Ifwe want to write the frequency domain transfer function, we write, again assumingf«
Is and using Eq, (4.45),
(4.55)
or In
~
(4,56)
While we can design higher-order digital filters using the topology of Fig. 4.49, we will
restrict our analysis to first- and second-order filters where hand calculations are
relatively easy to perform. Note that we can increase the attenuation of a filter by using Fi
several of these sections in cascade,
(ed-Signal Circuit Design Chapter 4 Digital Filters 155
= 0.1
mction ••
B1 =0.1
•
.t
•••
LII.
Number of poles n?: number of zeroes.
,nn of an n'h -order canonic Figure 4.49 General canonic fonn of a digital filter.
e transfer function). The
4.3.4 The Biquadratic Transfer Function

The digital biquad filter based on the canonic fonn seen in Fig. 4.49 is shown in Fig.
(4.54) 4.50. The transfer function of this filter is
Bo + B IZ-I + B2Z-2 + BIZ+B2
~~~
BOZ2
H(z) (4.57)
l-A1z- 1 -A 2z-2 z2 -A Iz-A2
.vrite, again assuming!«
(4.55)
(4.56)
t) n-i
logy of Fig. 4.49, we will

re hand calculations are
uation of a filter by using
Figure 4.50 The digital biquad filter (see Fig. 4.49).
156 CMOS Mixed-Signal Circuit Design Chapter 4 Digital Filter:
In order to translate this transfer function into the frequency domain, we use Eq. (4.45) lSdB
and assume our frequencies of interest are much less than the sampling frequency 10dB
odB
OdB
-!idB
·lOdB
(4.58) -15dB
·20dB
-25dB
-30dB
After some algebraic manipulation we can put this equation in the form seen in Eq. (3.62)
~=
Bo . S2 + ';;(2Bo + BI)' S +f.l(Bo + BI + B2)
j. ~m
~:::j1
-SOdB
s2+!s(2-AI)·s+f?(l-A I A2) -55dB
-60dB-+
where 10K
(4.60) Fi
01 .fs(2Bo +Bd (4.61)
00 =f}(Bo+Bl +B 2 ) (4.62) Comparing Biquads to ,
. Consider the frequency
21rlo = fs(2 - A J) (4.63)
Q . This filter uses a clockiI
and finally,
(4.64) Note the significant dr

doesn't have this droop
Example 4.12 compensate for a Sinc-:
Repeat Ex. 3.8 using the digital biquad clocked at 100 MHz. (4.59) • (4.64) we can s'
In this example a lowpass filter is designed withfo 1.59 MHz and Q 0.707. 1.75, Al -0.78125
Reviewing Fig. 3.35, we see that for a lowpass filter O 2 and a l are zero. This complexity or performa
means, in Eq. (4.59), Bo and BI are zero. Further, biquad filters are seen iI
0.707 ~ Al
6
Q 2n· 1.59 x 10 = 1.859
100x 106(2-Ad
The block diagram of th
and
2rr ,\2
1o OdB"
l-AI-A2= ( Ts) ~A2=-0.869
I
J\
·20dB-i .
and finally, because the gain at DC is 1,
I
B2 l-A I -A2=O.OI
Note that if a scaling in the amplitude is allowable, we can remove this
mUltiplication or approximate it with shifts in the digital word.
The simulation results are seen in Fig. 4.51. In order to implement this
simulation in SPICE, we used transmission lines for the delay elements and
:::1
voltage- controlled voltage sources for both the multiplications and the adders. 'loodBl
This method allows us to simulate the filter's frequency response. Note that the
frequency response is periodic with the filter's clocking frequency.•
I?igure 4.52 I
omain, we use (4.45)

mpling frequency
-Bz
(4.58)
he form seen in (3.62)
(4.59)
(4.60)
Figure 4.51 Simulating the digital filter in Ex. 4.12
(4.61 )
(4.62) Comparing Biquads to Sine-Shaped Filters
Consider the frequency response of the Sine-shaped lowpass filter shown in 4.52.
(4.63)
This filter uses a clocking frequency of 100 MHz and a K of 16 or
3
IH(z) I = 1 -1 1 (4.65)
l-z
(4.64)
Note the significant droop in the filter's response. It's desirable to design a filter that
doesn't have this droop or, even more desirable, contains a small amount of peaking to
compensate for a Sinc-shaped attenuation from a SIH, decimation filter, etc. Using
(4.59) - (4.64) we can set, for a digital biquad equivalent of this filter, B2 0.03 Al
I MHz and Q 0.707. 1.75, A2 = -0.78125 (there are several other solutions, depending on the desired
and a I are zero. This complexity or performance of the filter). The simulation results comparing the Sinc and
biquad filters are seen in Fig. 4.53. The transfer function of the biquad filter is
H(z) =: ----"'-'-=--"='-- (4.66)
The block diagram of the filter is seen in Fig. 4.54.
Od!!-,.-_ _~_ _ _-,--_VfY,-.-=•.:!..q--,----~--_n

J.869
-lOd!!
··· .
',--,---------------,.
..
-~Od!!
we can remove this

-SOd!!
Ird.
ier to implement this -BOrlB
Ie delay elements and
ations and the adders. -IOOdB
20MHz 40MHz 60MHz 8DMHz 100MHz
esponse. Note that the
luency.•
Figure 4.52 Frequency response of a third-order Sinc filter with K = 16.
158 CMOS Mixed-Signal Circuit Design Chapter 4 Digital Filte
20dB~----'-"-==~-,-----~- IOdS·
OdB OdB'
·20dB ..
·IOdB·
·40dB
-2DdB·
·60dB
.;::::r:: : : . . ;." ·30dB·

·40dB
~~\r• • ·..l!•• .• •••! • • .• • ·t·.• •

-50dB
-GOdS
·lOdB
·.1'··•.••••••••• ·8UdB
·SOdS
-24OdB·l i i i 1---- -100dB
20MH. 40MH. 60MHz 80MHz IOOMHz 5001
Figure 4.53 Comparing a third-order Jowpass Sinc filter to a third-order biquad. Figure 4
In Out
In
\AdjUst as needed
Figure 4.54 The digital biquad filter described by Eq. (4.66).

to nonnalize
output word size.
4 Fi:
Example 4.13
Redesign the filter in Fig. 4.54 so that the response has a small amount of peaking ADDITIONAL REAl
at 3.125 MHz. Compare, with simulations, the biquad's response to the Sinc [I] M. Weeks, Di!
filter's response seen in Fig. 4.52. Science Press, :2
Reviewing Eq. (4.63), we see that to increase the Q we need to increase A j • [2] T. B. Welch,
Keeping in mind that we want to have simple multiplications relying heavily on Processing ji'O/
shifts, let's try increasing Aj to 1.78125 and A z to 0.8125. The simulation results 978-084937382
are seen in Fig. 4.55. In this figure we compare the modified filter response to the
response of the Sinc filter. Note that we have a couple of dB peaking in the [3] S. Haykin ar
cascaded biquad filter's output. _ Communication
0471432227
A Comment Concerning Multiplications
[4] R. G. Lyons,
While discussing the implementation of digital multipliers is outside the scope of this Prentice-Hall,2 1
book a comment is in order about simple mUltiplier implementations. While, in some
filtering applications, simple shifts can prove very useful, we can implement more useful [5] P. A. Lynn an
multipliers using adders. Figure 4.56 shows one possible implementation using a single Edition, John W
adder along with the associated multiplication factors. We could implement the [6] L. W. Couch,
coefficients in Ex. 4.13 using a similar scheme. For example, Aj = 1.78125 2 - 0.25 + Prentice-Hall, I'
0.03125 and A2 = 0.8125 I - 0.25 + 0.0625 (both requiring two adders). Other creative
ways can be used to implement multipliers. For example, a multiplication of 0.5625 by [7] E. P. Cunningh
cascading two simple mUltipliers with multiplication factors 0.875. 1995. ISBN 978
~ 100MHz
a third-order biquad.
Figure 4.55 Designing a biquad filter with peaking, see Ex. 4.13.
~out B= Multiply by
I o
0.5 0.5
"AdjUst as needed
0.25 0.75
to nonnalize
output word size. 0.125 0.875
0.0625 0.9375
0.03125 0.96875
. Eq. (4.66).
Figure 4.56 A simple multiplier using a single adder.
naIl amount of peaking ADDITIONAL READING

response to the Sinc
[1] M. Weeks, Digital Signal Processing Using MATLAB and Wavelets, Infinity
Science Press, 2007. ISBN 978-0977858200
e need to increase A I' [2] T. B. Welch, C. H. G. Wright, M. G. Morrow, Real-Time Digital Signal
ions relying heavily on
Processing from Matlab to C with the TMS320C6x DSK, CRC, 2006. ISBN
The simulation results
978-0849373824
~d filter response to the
of dB peaking in the [3] S. Haykin and M. Moher, An Introduction to Analog and Digital
Communications, Second Edition, John Wiley and Sons, 2006. ISBN 978
0471432227
[4] R. G. Lyons, Understanding Digital Signal Processing, Second Edition,
: outside the scope of this
lentations. While, in some
:an implement more useful [5] P. A. Lynn and W. Fuerst, Introductory Digital Signal Processing, Second
lementation using a single Edition, John Wiley and Sons, 1998. ISBN 978-0471976318
We could implement the [6] L. W. Couch, Modern Communication Systems: Principles and Applications,
AI = 1.78125 = 2 0.25 + Prentice-Hall, 1995. ISBN 978-0023252860
wo adders). Other creative
:mltiplication of 0.5625 by [7] E. P. Cunningham, Digital Filtering: An Introduction, John Wiley and Sons,
~75. 1995. ISBN 978-0471124757
QUESTIONS Qualitatively eXJ:

increased by pass
4.1 If V REF+ 1.0 V and VIII::F_ = 0 regenerate Fig. 4.1 using SPICE. (Design a 3-bit Ex. 4.8, verify tha
ideal DAC model in SPICE.) The y-axis will be voltages in decimal form.
In Fig. 4.32, whic
4.2 If, again, V REF+ = 1.0 V and VII£F_ = 0, sketch Fig. 4.1 for a I-bit DAC. Note that
the digital input code will either be a 0 or a I and the analog voltage out of the For the FIR filtel
DAC will be either 0 or 1.0 V. Using Eq. (4.1) what is the voltage value of I filter's frequency!
LSB? How does this compare to the value of I LSB we get from the sketch? Is
For the filter seen
Eq. (4.1) valid for a I-bit DAC? Why? The I-bit DAC will be a ubiquitous
filter will be stab
component in our noise-shaping modulators later in the book (see Fig. 7.15).
the filter's poles a
4.3 Why do the transfer curves of Fig. 4.3 show a shift of 1/2 LSB to the left? How do
we implement this shift in SPICE?
4.4 Use SPICE to implement 4-bit ADC and DAC. If the converters are clocked at x
100 MHz (and the outputs of the ADC are connected to the inputs of the DAC),
apply an input sinewave (to the ADC) that has an amplitude of 500 m V peak
centered around 500 m V DC with a frequency of 5 MHz. Again, use VREF+ 1.0 V
and VRI::F_ O. Show the DAC's analog output.
4.5 Using SPICE generate the spectrums of the input and output signals in question
4.4.
4.6 Suppose we think of the I-bit input, 0 or I, in Fig. 4.9 as +1 or -1 (two's Repeat Ex. 4.9 fo
complement numbers). What is the output of the digital filter when the input is
always O? Is the magnitude response seen in Fig. 4.10 correct? Why?
4.7 Suppose the I-bit input signal seen in Fig. 4.9 is an alternating sequence of
1010 I 0 ... In terms of two's complement numbers, what is the output of the digital Repeat Question
filter (what is the output of the counter)? What is the frequency of the input
signal? Is the frequency response seen in Fig. 4.10 correct? Repeat Ex. 4.12 i
4.8 Repeat Ex. 4.3 for a filter with a transfer function of Show that the f
multiplier.
Also, plot the location of the filter's poles and zeroes in the z-plane.
4.9 Repeat question 4.3 for a filter with a transfer function of
4.10 Repeat Ex. 4.5 if L is increased to 3.

4.11 Sketch the impulse response of the filter seen in Fig. 4.19.
4.22 Show that if the'
4.12 What are the transfer functions of the bandpass filters, indicated in Fig. 4.22, with circuit of Fig. 4.
center frequencies off/6 andf)3? Sketch the frequency responses and the location aren't directly po
of their poles and zeroes in the z-plane. multiply-by-O.93
4.13 Simulate, using an ideal 8-bit ADC on the input, and an ideal DAC on the output
(calculate the size of the DAC), the operation of the digital resonator seen in Fig.
4.23.
ixed-Signai Circuit Design Chapter 4 Digital Filters 161
4.14 Qualitatively explain why the desired spectrum of an input signal can't be
[lg SPICE. (Design a 3-bit increased by passing data through an interpolator. Using the simulations given in
s in decimal form. Ex. 4.8, verify that this is indeed the case.
for a I-bit DAC. Note that 4.15 In Fig. 4.32, which blocks serve as the AM and which serve as the S/H?
~ analog voltage out of the 4.16 For the FIR filter seen in Fig. 4.35 with all coefficients set to 0.25, sketch the
: is the voltage value of I filter's frequency response.
we get from the sketch? Is
)AC will be a ubiquitous 4.17 For the filter seen in Fig. 4.57 determine the range of values for a and b where the
book (see Fig. 7.15). filter will be stable. What is the filter's transfer function? Sketch the location of
the filter's poles and zeroes.
12 LSB to the left? How do
: converters are clocked at X(z)

to the inputs of the DAC),
mplitude of 500 mV peak
:z. Again, use VR£F+ 1.0 V
output signals in question Figure 4.57 A weighted integrating filter.
~. 4.9 as + I or -I (two's 4.18 Repeat Ex. 4.9 for a filter with a transfer function of
tal filter when the input is
orrect? Why? V 0111
I +j.
== _ _--'-"':.:.=_
in alternating sequence of
t is the output of the digital 4.19 Repeat Question 4.18 using the canonic form of the first-order digital filter.
:he frequency of the input
~ct? 4.20 Repeat Ex. 4.12 if the Q is increased to 1.
4.21 Show that the filter shown in Fig. 4.58 can be implemented using a single
multiplier.
the z-piane.
of
Figure 4.58 Filter used for question 4.21.

19.
4.22 Show that if the values of A and B are restricted to 1,0.5,0.25,0.125, etc. that the
indicated in Fig. 4.22, with circuit of Fig. 4.59 can be used to implement multiplication by coefficients that
{ responses and the location aren't directly powers of two. How would a multiply by 0.75 be implemented? a
multiply-by-0.9375? a multiply-by-0.5625?
in ideal DAC on the output
igital resonator seen in Fig.
In ----...-~40--~~)_____ Out
Figure 4.59 A simple multiplier where A and B simply shift the data.
Data Con'
After studying Chs. 1-4 w
sampling, decimation, and
.the basics of filtering. In tI
Quantization noise is the ef
(aka quantizer), a comparat
that reduces the word size
focus on is the shape of
spectrum of an input analo~
5.1 Quantization No
Examine the clocked comp:
we'll use a VDD of I V and
the comparator, the non-in'
at VCM' the output goes to
between the input and outp
analog signal, the input, t(
. added noise to our input sil
process, from a block diag
model is shown in Fig. 5.:
VDD
T
In, analog . 1~.

500mV _
i
~
~!c1
I
Is
Figure 5.1
ixed-Signal Circuit Design
Out Chapter
lly shift the data.

5
Data Converter SNR
After studying Chs. 1-4 we should understand the sampling process, including analog
sampling, decimation, and interpolation, the operation of the ideal ADC and DAC, and
the basics of filtering. In this chapter we turn our attention towards quantization noise.
Quantization noise is the effective noise added to a signal after it passes through an ADC
(aka quantizer), a comparator (a I-bit ADC or quantizer)), or, for digital signals, a circuit
that reduces the word size (removes the LSBs of the word). One of the key things we'll
focus on is the shape of the quantization noise spectrum and how it's added to the
spectrum of an input analog or digital signal.
5.1 Quantization Noise

Examine the clocked comparator seen in Fig. 5.1. In this ehapter, like the rest of the book,
we'll use a VDD of 1 V and a common-mode voltage, VCM ' of 500 mY. When the input to
the comparator, the non-inverting input, is 600 mV then, since the inverting input is held
at VCM' the output goes to I V on the rising edge of the clock signal. The difference
between the input and output of the comparator is 400 mY. Note that we've gone from an
analog signal, the input, to a digital signal, the output. However, while doing this we
added noise to our input signal. It's useful to think of this analog-to-digital (quantization)
process, from a block diagram point of view, as simply adding noise to our signal. This
model is shown in 5.2. Notice that we've assumed that the noise we added to our
VDD 1.0 In Added noise
In,analog ~ 600mV
800mV
IV
IV
+400mV
+200 mV
i Out, digital
500mv~
200mV OV -200 mV
I~ clock 450mV OV -450mV
950mV IV +50mV
Is
Figure 5.1 How a comparator adds noise to an input signal.

164 CMOS Mixed-Signal Circuit Design Chapter 5 Data Converter ~
Analog
vin_ _ _ _-I
Digital
i
I
Anal~ital
'm T
V Qe(f) (added noise)
360mV ...... .
210mV ...... .
Figure 5.2 Modeling ADC quantization noise.
180mVT· ....
90mvL
input signal has a spectrum of VQe( f). Determining the shape and range of this noise OmV.
Ons S{
spectrum is one of the goals of this chapter. Finally, while a good portion of our studies
will focus on the quantization noise introduced during the analog-to-digital process we
can also apply the same results when truncating a digital word's size, Fig. 5.3. Figure 5.5 Se
. ADC input and the DAC (

VQe(Z) (added noise) Fig. 5.6. The inherent nois
is approximately -80 dB
N-Fbits output (the signal + quant
Nbits " ) ;
I
) I fez)
Nbits Out fez) Out desirable to determine wh
!
Drop lower F bits. N-Fbits ADC quantizes the signal
Quantizer don't introduce quantizatic
Udal
Figure 5.3 Quantizing a digital word and modeling the added noise.
-, OdS-!- i'''"'
'20d!!~'i""
5.1.1 Viewing the Quantization Noise Spectrum Using Simulations ' 30dB t ....
Consider the simple connection of an ideal 8-bit ADC to an ideal 8-bit DAC seen in Fig. -40d!!~' ... .
SA. If we apply a 7 MHz sinewave to the ADC with an amplitude of 004 V and an offset ~Ud!!~'
of 0.5 V (so the sinewave swings from 100 mV to 900 mY]) and clock the ADC at 100 -60dSJ -'"
MHz we get the signals seen in Fig. 5.5. Note that the output of the DAC looks very -10dS
similar to the output of an ideal SIR (see Fig. 2.14). Now, however, the amplitude of the -OOd!!..,
DAC output signal is quantized, that is, within 1 LSB (= 1.0/256 or 3.906 mY, see Eq.
-SOd!!
[4.1], for the present simulation) of the ADC input. This quantization is not obvious after lMHz
looking at Fig. 5.5 (the time domain response). However, looking at the spectrums of the
Figure 5.6 ADC inpu1
VDD = 1.0 VDD l.0
Analog I Digital --~ Analog
Bennett's Criteria
8
Vjn
Is I lrt'
:8-b:OC I
I
I
lldelli
8-bItDAC
Vout
In order to characterize tf
following assumptions (B
.~
l. The input (to t
Figure 5.4 Passing a signal through an ADC and then through a DAC.
VREF- so that no satura'
operating range of the A
spikes to the output spect
.fixed-Signal Circuit Design Chapter 5 Data Converter SNR 165
-{r~r\
V Qe(f) (added noise)
oise.
ape and range of this noise

good portion of our studies
analog-to-digital process we
1'5 size, Fig. 5.3.
Iclk =Is = 100 MHz
Figure 5.5 Seven MHz ADC input and the corresponding DAC output.
ADC input and the DAC output reveals the difference in the noise floor between the two,
VQeCz) (added noise) Fig. 5.6. The inherent noise floor in the simulation that is associated with the input signal
is approximately -80 dB (0.1 mY, RMS.) The noise floor associated with the DAC's
output (the signal + quantization noise) is approximately -70 dB (0.316 mY, RMS). It is
Y(z) Out
desirable to determine what sets this value and its spectral content. Again, note that the
N-Fbits ADC quantizes the signal which results in the quantization noise (an ideal S/H and DAC
::luantizer don't introduce quantization noise).
; the added noise.
n9 Simulations
ideal 8-bit DAC seen in Fig; fu.\1S
)litude of 0.4 V and an offset'
]) and clock the ADC at 100
ltput of the DAC looks very
.owever, the amplitude of the
.01256 or 3.906 mY, see Eq.
mtization is not obvious after -90d~M+H-z--4-1-TI.!-Ht - - 81 MHz 121 MHz 161MHz
oking at the spectrums of the Is
Figure 5.6 ADC input and output spectrums for Fig. 5.4 with signals seen in Fig. 5.5.
1.0
Bennett's Criteria
In order to characterize the spectral characteristics of the quantization noise let's make the
following assumptions (Bennett's criteria) concerning the signal we are converting:
1. The input (to the ADC) signal's amplitude variation falls between VREF+ and
en through a DAC. VREF- so that no saturation of the digital output code occurs. Exceeding the normal
operating range of the ADC affects the quantization noise spectrum by adding spurs or
spikes to the output spectrum.
166 CMOS Mixed-Signal Circuit Design Chapter 5 Data Converter S:
2. The ADC's LSB is much smaller than the input signal amplitude. When this
80mV
isn't the case, the output of the ADC can appear squarewave-like (when converted back 60mV
40mV
into an analog waveform) and result in a spectrum, once again, that contains spikes or 20mV
spurs. We'll see later in the book that adding or subtracting a fed-back signal (from the OmV
-20mV
output based on the expected or past quantization noise) to the input modifies this ·40mV
.fiOmV
requirement.
3. The input signal is busy (not DC or a low frequency input). We define busy, for
the moment, as meaning that no two consecutive outputs of the ADC have the same
digital code. For the ideal ADC in Fig. 5.4 1 LSB 3.906 mV and Ts 10 ns so that the
input must change at least 3.906 mV every 10 ns. We'll see that adding a high-frequency
dither or pseudorandom noise signal to the input, which can be filtered out later (either
using a digital filter or when we pass the output through the reconstruction filter), can
:::::6
o.o~. 0.11
make the requirement on the input of being busy practical in an actual circuit. We use
these assumptions (Bennett'S criteria) in the following discussion unless otherwise
indicated.
:::::r··
--..--
-40dB
·48dB
..... .
.... --
An Important Note
-56dB .... ..
It's important to note that simply sampling an input waveform, using a SIH, does not
result in quantization noise. The amplitude into the ideal SIH, at the sampling instant, is
exactly the same as the amplitude out of the ideal S/H. In order to understand why this is :::::[1:
·BBdBL. ·.
important, consider the test setup shown in Fig. 5.7. If we apply a 3 MHz sinewave -96dB ------
centered around the common-mode voltage with a 400 mV amplitude we get the outputs -104dB --- .. -
seen in Fig. 5.8. Clearly there is a difference between the SiR's input and its output. -112dB .. - ....
However, this difference has nothing to do with noise, an unwanted signal, since passing -120dB
IMHz
the output of the SIH, VanIsh' through the ideal reconstruction filter of Fig. 2.19 results in an
exact replica of the SIH input Vi" .
Figure 5.8 Time-domain d
A section of the inpl

5.IOa. It's important to und
--~) Vout
and DAC shown in this figu
that rises too quickly will d
slightly above 482 mY, in t
The ADC output code can l
for the present simulation) (
Figure 5.7 Taking the difference between the SIR input and output. this figure it appears as tho
RMS Quantization Noise Voltage

If we were to set up a test configuration similar to that shown in Fig. 5.7 (see Fig. 5.9), Slow
vj~R_a_m~-j IdE
where the input to the ADC is subtracted from the DAC output, the resulting output
A[
waveform would have little to do, in every case, with the quantization noise. This is true
when the input to the ADC contains a broad frequency spectrum extending from DC to
the Nyquist frequency,J,; = 1/2. However, if we apply a slow linear ramp to this test setup
(to limit the input frequency spectrum) we can (1) see the reSUlting quantization noise
over a wide frequency spectrum and (2) observe the transfer curve, in the time domain.
Note that this input violates Bennett's criteria (which, as we'll see, means the noise power Figure 5.9 Taking t
spectral density is flat from DC to the Nyquist frequency).
ixed-Signal Circuit Design Chapter 5 Data Converter SNR 167
~nal amplitude. When this

like (when converted back
Difference between
lin, that contains spikes or S/H input and
fed-back signal (from the output in Fig. 5.7 .
.0 the input modifies this
input). We define busy, for

f the ADC have the same S/H input and
, and Ts IOns so that the ...... output in Fig. 5.7.
at adding a high-frequency
be filtered out later (either
: reconstruction filter), can
I an actual circuit. We use
,cussion unless otherwise
Difference spectrum
rm, using a S/H, does not

, at the sampling instant, is
:r to understand why this is
apply a 3 MHz sinewave
aplirude we get the outputs
S/H's input and its output.
ranted signal, since passing
31MHz 61MHz 91MHz 121MHz 151MHz 181MHz
ter of Fig. 2.19 results in an
Figure 5.8 Time-domain difference between S/H input and output along with the spectrum.
A section of the input and output, using the test setup of Fig. 5.9, is shown in Fig.
5.lOa. It's important to understand the input/output relationship between the ideal ADC
and DAC shown in this figure. (Note that clocking the ADC too slow or putting in a ramp
that rises too quickly will distort this waveform.) As an example, when the ADC input is
slightly above 482 mY, in this figure, the ADC output code (input to the DAC) changes.
The ADC output code can be calculated as 482 mVIl LSB ( 1 LSB 11256 = 3.906 mV
for the present simulation) or changing from 123 to 124. Looking at the transfer curves in
nput and output.
this figure it appears as though the output changes when the ADC code is 123 or 480.4
a in Fig. 5.7 (see

lutput, the resulting output }----~Voutd
ntization noise. This is true
rum extending from DC to
inear ramp to this test setup
esulting quantization noise
curve, in the time domain.
see, means the noise power Figure 5.9 Taking the difference between an ADC input and the DAC output.
168 CMOS Mixed-Signal Circuit Design Chapter 5 Data Converter
VISB
Figure 5.11 Probal

assum
Figure 5.10 Difference between an ADC input and DAC output.

so that, once again, the Rlv
mVIl LSB. This, as seen in Fig. 5.lOb and discussed below, results in centering the
quantization error around the input. This is the reason we shifted the ADC transfer curves
by 1/2 LSB when we developed our ideal ADC model.
The difference output, between the two signals of Fig. 5.IOa, is shown in Fig. Again, if our LSB voltage
5.IOb. Some points to note about this sawtooth waveform are that I) its average value is (RMS). If we look at Fig.
zero, 2) the waveform contains an abrupt transition (and so we expect a wideband output the entire spectrum (white
spectrum similar to that which occurs after sampling a waveform), and 3) its peak-to-peak less than -80 dB. Note th~
amplitude is I LSB. Like a sinewave, which also has zero average value, we can not because of the samplil
characterize this quantization error waveform by looking at its root-mean-square (RMS) experience aliasing). Qual'
value. This value can be calculated using during the analog-to-digitc
the quantization error spec
I
V Qe.RMS = V~ 1
T
(0.5 LSB
transitions in the DAC 01
between the changes hav
longer time or using a mul
This value is the RMS quantization noise voltage for a specific data converter. Note that quantization errors are fun
the value of the period for this sawtooth waveform, T , doesn't appear in the evaluated than what is seen in Fig. 5.
result of this equation. Also note that the sampling frequency, Is ' isn't present in this
5.1.2 Quantization Noi~
equation. For our present discussion where I LSB is 3.906 mY, VQe.RNI.S = 1.13 mV or -59
dB (RI\1S). If the quantization noise .
determine the noise power
Treating Quantization Noise as a Random Variable
noise voltage spectral dens
If Bennett's criteria hold, then the quantization noise voltage can be thought of as a
random variable falling in the range of ±0.5 LSB, as seen in Fig. 5.11. The probability
that the quantization error is -0.2 LSB is the same as the probability that the error is 0.4
LSB. In other words, there is no reason why the quantization error should have one value
more often than another value. where the factor of 2 aceo
Notice that we assumed a .
The quantization error noise power is the variance of the probability density of the quantization noise:
function. The RMS quantization error voltage is the square root of the quantization noise Solving this equation yield
power. The variance of the probability density function (the quantization noise power,
PQJ is given, knowing the average of the quantization error, Qe, is zero, by
'
Mixed-Signal Circuit Design Chapter 5 Data Converter SNR 169
1I2LSB
Probability density function, p
E
," .. ,....... ~l LSB =
!.:'::::i'::':: 3.906 mY
f
-II2LSB
p' dQe= 1
;::::::.,::--::: ADC input

1 LSB = VLSB
':::::::::::::::. DAC output
( J I ) Qe
-112 LSB 112 LSB
Figure 5.11 Probability density function for the quantization error in an ADC
assuming Bennett's criteria hold.
!l2LSB V2
md DAC output.
PQe= f
-!l2LSB
p·(Qe)2·dQe= LSB
12
(5.2)
so that, once again, the RMS quantization noise voltage is

low, results in centering the
[ted the ADC transfer curves VLSB
V Qe,RMS = JT2 (5.3)
Fig. 5. lOa, is shown in Fig. Again, if our LSB voltage is 3.096 mY, then, once again, VQe,RMS = 1.13 mV or -59 dB
re that I) its average value is (RMS). If we look at Fig. 5.6, we see that the RMS noise voltage varies essentially over
we expect a wideband output the entire spectrum (white noise) and has a value ranging from around -70 dB down to
'orm), and 3) its peak-to-peak: less than -80 dB. Note that although the entire spectrum contains quantization noise it is
~ero average value, we can not because of the sampling process used in the ADC (and so quantization noise doesn't
its root-me an-square (RMS) experience aliasing). Quantization noise is added to the signal after the sampling process
during the analog-to-digital conversion process. In order to qualitatively understand why
the quantization error spectrum is white, in Fig. 5.6, we remember that there are abrupt
~dt = I LSB = VLSB (5.1) transitions in the DAC output, and if the quantization error is truly random, the times
JT2 JT2 between the changes have varying periods. We might speculate that by simulating a
longer time or using a multiple frequency input so as to "exercise" the ADC, the resulting
ific data converter. Note that quantization errors are further randomized and the resulting error spectrum will be flatter
esn't appear in the evaluated than what is seen in Fig. 5.6.
:Dcy, is ' isn't present in this
o.V, VQe,RMS = 1.13 mV or -59 5.1.2 Quantization Noise Voltage Spectral Density
If the quantization noise voltage spectrum is truly flat (Bennett's criteria hold) we can
determine the noise power spectral density of VQe.RMS, V8e(f) with units of V 21Hz, or the
noise voltage spectral density, VQe(f) with units of VI/Hz by solving
:age can be thought of as a
in Fig. 5.11. The probability V2 /,12
'obability that the error is 004 t~B = 2

o
f V8e(f)· df (SA)
1 error should have one value -
where the factor of 2 accounts for the power in the negative frequencies of the spectrum.
Notice that we assumed a spectrum from DC to the Nyquist frequencY,isI2. Assuming all
e of the probability density
of the quantization noise falls below the Nyquist frequency is the worse-case situation.
root of the quantization noise
Solving this equation yields
1e quantization noise power,
Qe, is zero, by V e(f) = VLSB = VREF+ - VREF (5.5)
Q J12!s J
2N 12!s
-,;'-.
. ,:'
170 CMOS Mixed-Signal Circuit Design Chapter 5 Data Converter SJ
with units of VI jii;. Note that the quantization noise spectral density is inversely sampling frequencies. F
proportional to the sampling frequency. Figure 5.2 shows how we can model the ADC as we assume Bennett's cril
a summation of the input signal and the quantization noise. In order to see the
After looking at Eq. 5.5 we might think that by simply increasing the sampling remove tones (input sigJ
frequency we can reduce the amount of quantization noise an ADC introduces into an in Fig. 5,13 the way
analog input signal. While increasing the sampling frequency spreads the quantization (remembering simply s
noise spectral density out over a wider range of frequencies (see Fig. 5.12) with a DAC's output. Using i<
corresponding reduction in amplitude, the sampling frequency doesn't affect the total zero. In most systems \\
RMS quantization noise voltage. However, bandlimiting the spectrum using a filter mixed-signal system. Tl
reduces the amount of quantization noise introduced into an input signal (this is system is linear (consl
important and the reason mixed-signal design is so powerful). In the simplest case a spectrum of the outpu
lowpass filter is used on the output of the ADC to reduce the amount of quantization wanted signal and its ali
noise introduced into the signal. We can write the amount of noise introduced into an
input signal over a range of frequencies using
IH
J
V~e.RMS = 2 V~e(f) . dl where IL <IH'S/s12 (5.6)
z,omV~
1.6mV
IL 1.2mV
Again, the factor of 2 is used to account for the contributions to VQ€,I1MS in the negative
frequency spectrum. Let's show that the sampling frequency doesn't affect the :::::
. L
quantization noise, assuming Bennett's criteria are valid. O.OmV
-O.4mV~-"-'
-o.8mv+ ...
All quantization noise is assumed to
-1,2mv+--- ...
fall in the frequency spectrum of
VLSB interest (the worst case situation).
-1, 6mV t-.. _- ~.
~2,OmV+---·~··T
J12/s +----::~/----,I Dos SOn
J" =/s12 I
Vin II
Figure 5.12 Quantization noise spectral density. i j, ] . j
Example 5.1 I
Using the SPICE simulation that was used to generate Fig. 5.IOb with sampling
frequencies of 100 and 200 MHz calculate and simulate the amount of
quantization noise introduced into the input signal.
Doubling the sampling frequency has little effect on the output quantization noise.
Our calculated value was 1.13 mV using Eqs. (5.1) and (5.3) while the simulated
Figure 5.13 Dt
values are 1.127 mV for both 100 and 200 MHz sampling frequencies .•
Example 5.2 Calculating Quantization]

Suppose a 7 MHz sinewave with a peak amplitude of 400 mV is applied to the The spectrum of a signa
topology seen in Fig. 5.9. Calculate and compare to simulations the amount of Transform (FFT). We car
quantization noise introduced into the sinewave when sampling frequencies of individual components usb
100 and 200 MHz are used.
Again, the RMS value of the quantization noise added to the input signal is 1.13
mY. The simulated values are 1.12 mV and 1.15 mV for 100 and 200 MHz
Aixed-Signal Circuit Design Chapter 5 Data Converter SNR 171
Jectral density is inversely sampling frequencies. Figure 5.13 shows the simulation results. Again, note that
" we can model the ADC as we assume Bennett's criteria are valid (input busy, large compared to an LSB, etc.)
In order to see the quantization noise introduced by the ADC we have to
ply increasing the sampling remove tones (input signal and its aliases) from the DAC's output signal. As seen
an ADC introduces into an in 5.13 the way we do this is by subtracting the S/H input signal
cy spreads the quantization (remembering simply sampling a waveform doesn't introduce noise) from the
:ies (see Fig. 5.12) with a DAC's output. Using ideal components the delay through the system is nearly
ncy doesn't affect the total zero. In most systems we have to adjust the delay to match the delay through the
he spectrum using a filter mixed-signal system. This only works if the phase shift through the mixed-signal
J an input signal (this is system is linear (constant delay). A more useful technique is to look at the
full. In the simplest case a spectrum of the output signal and remove, using for example Matlab™, the
the amount of quantization wanted signal and its aliases .•
of noise introduced into an
2.0mV,~~_~_ _ _ _ _V(vq=,=,el_~""""""T"""""''''~_ _~
'f 5.f,J2 (5.6)
l.SI11V
ns to VQe.RMS in the negative

quency doesn't affect the
iltization noise is assumed to

Ie frequency spectrum of
(the worst case situation).
-2.0mV I ,
Dos 50ns 1DOns 150n5 200ns 250ns JOOns 350n5 40008 450ns 50005
)
;12 f
~VQe(t)
Ideal Ideal
lsity.
ADC DAC
L - _ _I I VQe(f)
I
ig. 5.1 Ob with sampling

mulate the amount of SIH
utput quantization noise.

5.3) while the simulated
frequencies.• Figure 5.13 Deternlining quantization noise in a mixed-signal system.
Calculating Quantization Noise from a SPICE Spectrum

DO m V is applied to the The spectrum of a signal in a SPICE simulation is generated using a Fast-Fourier
rlUlations the amount of Transform (FFT). We can estimate the RMS value of this spectrum by summing the
;amp ling frequencies of individual components using
, the input signal is 1.13 (5.7)

for 100 and 200 MHz
172 CMOS Mixed-Signal Circuit Design Chapter 5 Data Converter S
where M is the number of points used in the FFT andhes is the resolution of the FFT (the 5.2 Signal~to-Noise I
distance between adjacent points). Note that here we are assuming that VFFr(f) is an RMS
value. If it's a peak value then the right-side of Eq. (5.7) should be divided by .fi . In the last section we devel
as a noisy circuit block wht
Figure 5.14 shows a portion of the quantization noise spectrum for the signal seen the input signal. Logically,
in Fig. 5.l3. We can estimate the RMS noise from this spectrum assuming, as seen in Fig. the mixed-signal system in
5.12, that the noise is bandlimited. While we can look at the specifics of the FFT in the
simulation to exact numbers, let's simply count the number of points seen in the plot If we apply a sine
(Fig. 5.14) and see how close we get to the exact answer of 1.13 mY. First note that -74 Vp l!2) to an ADC input,
dB is 200 !lV RMS and, as seen in Fig. 5.14, we are assuming a constant spectrum (white ADC input signal is VLSBI'i
noise). Looking at the plot there are roughly 32 points from DC to 50 MHz so
VQe.RMS = J32· (0.2 mV)2 = 1.13 mV

is an exact match. Note, again, that since we are assuming all of the noise falls between If we remember that
DC and the Nyquist frequency, our estimated value (-74 dB) for the quantization noise is
a little above the actual value we see in this range.
and we assume that the
maximize the SNR), that i~
.60dElI~_ _ _ _ _ _ _ ....:VM=e,,-I_ _ _ _-,--_ _-,
V~~;~~S .7.dOL...... then Eq. (5.10) can be rew
-74dB~
. -SOdB
(see Fig. 5.12)
Effective Number ofBits
9.dB
Equation (5.13) relates tho;
the input signal is a sine
·100dB+-----i----i------' ---il---~·
OMHz 20MHz 40M!lz 60MHz SNR, in most cases, will ~
When the SNR is measure
Figure 5.14 Spectrum of the quantization noise seen in Fig. 5.13.
Power ~pectral Density where the measured SNR

The variable V~e(f) in Eq. (5.6) is a power spectral density (PSD) with units of V2/Hz.
To convert our SPICE plot above (RMS amplitudes) to a power spectral density we use Example 5.3
Determine the effecti'
---,-~c::.....:. with units of V2/Hz and a measured VQe,RM
(5.8)
If we assume that th,
and change the y-axis from 20 . logy to 10 . logy. Note that we can then use Eq. (5.6) to mY, then the measure
calculate VQe,RMS (without the factor of two since SPICE uses one-sided spectrums). To
generate a SPICE plot similar to what is seen in Fig. 5.12 we use
V Qe(f) = VFFT(f) with units of VI !if; (5.9) The effective numbe

calculate VQe.RMS we e
Again the quantization noise in the simulation would extend beyond //2, unlike the analyzer or take the F
assumed shape seen in Fig. 5.12. in either case, similar
:he resolution of the FFT (the 5.2 Signal-to-Noise Ratio (SNR)

lming that Vm(f) is an RMS
Ild be divided by ,/2 . In the last section we developed the idea of treating an analog-to-digital converter (ADC)
as a noisy circuit block where the output of the ADC is the sum of quantization noise and
~ spectmm for the signal seen the input signal. Logically, the next step in our development of concepts is to characterize
rum assuming, as seen in Fig. the mixed-signal system in terms of the signal-to-noise ratio (SNR).
Ie specifics of the FFT in the
ber of points seen in the plot If we apply a sinewave with an amplitude of Vp (and thus an RMS value of
'1.13 mY. First note that -74 Vp / ,/2) to an ADC input, then, knowing the RMS quantization noise added to a busy
Ig a constant spectmm (white ADC input signal is VLsBI l12 (see Eqs. [5.1] and [5.3]), the resulting SNR is
)C to 50 MHz so
(5.10)
1.13 mV
all of the noise falls between If we remember that

) for the quantization noise is
VLSB = 1 LSB (5.11)
and we assume that the largest possible amplitude sinewave is the ADC input (to
maximize the SNR), that is,
(5.12)
then (5.10) can be rewritten as
SNRjdeal = 20 . log -"'--- 6.02N + 1.76 (in dB) (5.13)
Effective Number ofBits

Equation (5.13) relates the number of bits used in a data converter to the ideal SNR when
the input signal is a sinewave that ranges from VR£F+ to VREF~' In reality the measured
SNR, in most cases, will be different from the ideal value calculated using this equation.
When the SNR is measured, we relate it to the effective number of bits using
,een in Fig. 5.13. 1.76
N eif == ---"''':''::-:::-'-''--'- (5.14)
6.02
where the measured SNR (SNR meas ) is specified in dB.
y (PSD) with units of V2IHz.
.ver spectral density we use Example 5.3
Determine the effective number of bits for an ADC with, = 1.0, VREF- == 0
(5.8) and a measured VQe,RMS of2 mY.
If we assume that the input peak amplitude, Vp , is 0.5· (VREF+ V REF-) or 500
. we can then use Eq. (5.6) to mY, then the measured SNR is given by
ses one-sided spectmms). To
: use 0.5/ ,/2
SNRmeas = 2 mV = 177 45 dB
of (5.9) The effective number of bits, NelJ , is, from Eq. (5.14), 7.18 bits. Note that to
calculate VQe,RMS we either take the output of the DAC and feed it into a spectmm
tend beyond /,/2, unlike the analyzer or take the FFT of the digital output data of an ADC so that we get a plot,
in either case, similar to what is seen in Fig. 5.14 .•
174 CMOS Mixed-Signal Circuit Design Chapter 5 Data Converter S1'
Coherent Sampling
Example 5.4
Using thc ideal 8-bit ADC and DAC shown in Fig. 5.4 with a sampling frequency It's important to understand
of 100 MHz show, using SPICE, that applying a full-scale sinewave at 24 MHz to SNR that is different from tl
this configuration will cause the resulting SNR to approach the ideal value given input frequency is 10 MHz
by Eq. (5.10). coherent. The sampled poin
quantization error can then t
Let's begin by calculating SNR,deaJ' From Eq. (5.11), SNR ideaJ is roughly 50 dB, as
the data converters have 8-bit resolution. Coherent sampling (
namely spectral leakage. II
The time-domain input and output of the circuit and the corresponding DAC
consider the sinewave wit
output spectrum, are shown in Fig. 5.15. The input to the ADC in Fig. 5.4 is a 24
performed on a time-domai
MHz sinewave with a peak amplitude of 0.5 V centered on a DC voltage of 0.5 V
simplest window is the reet
(the peak-to-peak voltage of the input wavefonn is VDD or 1 V). The V Qe.RMS
is finite and set by the simu
measured with SPICE, in a separate simulation using a SIH to remove the input
the infinite duration sinewf
signal and aliased signals from the DAC's output spectrum, is 1.4 mV. The
Fig. 5.16b to obtain the wa
simulated SNR is then (0.5/.j2)/l.4 mV or 253 (48 dB), which is close to the means the resulting wave
value, 50 dB, calculated at the beginning of the example.• response (an impulse) and
wavefonn) in the frequenc
1.0V response being an impulse j
0.9\1 Fig. 5.16e. Note that th~ F
0.8V "leaks" into the frequencies
of the peak value of the Si
24 MHz input minimize these sidelobes,
ADC input
0.4V
0.]\1
0.2\1
O.W
DAC output
o.ov
(a)
_IV\; ,+,
(e)
(e) Frequency Sf
Figure 5.15 Signals from Ex. 5.4, simulating Fig. 5.4 with a 24 MHz sinewave input.
Figure 5.16 Showing h
riixed-Signal Circuit Design Chapter 5 Data Converter SNR 175
Coherent Sampling
th a sampling frequency It's important to understand that poor selection of the input frequency can result in an
sinewave at 24 MHz to SNR that is different from the ideal value calculated using Eq. (5.13). For example, if our
ch the ideal value given input frequency is 10 MHz while the clock frequency is 100 MHz then the sampling is
coherent. The sampled points repeat with every cycle of the input signal. The amount of
deal is roughly 50 dB, as quantization error can then be, repeatedly, near ± 112 LSB or much larger than VLss I!l2 .
Coherent sampling can be useful to minimize the undesired effects of the FFT,
the corresponding DAC namely spectral leakage. In order to understand what is meant by "spectral leakage,"
ADC in Fig. 5.4 is a 24 consider the sinewave with infinite duration shown in Fig. 5.16a. When an FFT is
n a DC voltage of 0.5 V performed on a time-domain waveform, the first step is to "window" the waveform. The
simplest window is the rectangular window. In a simulation the duration of the sinewave
o or 1 V). The V Qe.RMS
I/H to remove the input is finite and set by the simulation time or transient stop time, T"op' We can think of taking
;trum, is 1.4 mV. The the infinite duration sinewave of (a) and multiplying it by the rectangular waveform of
Fig. 5.16b to obtain the waveform used in the simulation, Fig. 5.l6c. This multiplication
), which is close to the
I
means the resulting waveform is the convolution of the original sinewave spectral
response (an impulse) and the frequency domain transform of the squarewave (a Sinc
waveform) in the frequency domain. The result is that instead of the sinewave spectral
response being an impulse function, as seen in Fig. 5.16d, it is a weighted Sinc waveform,
Fig. 5.16e. Note that the FFT spectral response of the sinewave in (e) is spread out or
"leaks" into the frequencies around the actual or continuous time response. The large ratio
of the peak value of the Sinc pulse to its first sidelobe is usually undesirable. Rather, to
!='I=--+-- 24 MHz input minimize these sidelobes, other windowing functions are used. One commonly used
ADC input
DAC output
Ts/op
900s 1DOns
(a) (b)
V Ts/op f
(c) (d) Frequency spectrum of (a)
Log amplitude
11 Ts/op
A
/ ~f f
Linear amplitude
f;n 11 Ts/op
(e) Frequency spectrum of (c) (t), Von Hann (Hanning) window
.24 MHz sinewave input.
Figure 5.16 Showing how spectral leakage in an FFT affects the spectrum of a waveform.
window is the von Hann (a.k.a. Hanning or Cosine) window represented, without the
sidelobes, in Fig. 5.16f. The response is shown on both linear and log amplitude scales
and the width of the window is 21T,ropat its base.
Selecting an input sinewave frequency, I.. ' such that Is If. is a whole number
creates a condition where an integral number of input sinewave cycles fit perfectly into
the simulation or measurement time (so the windowing function isn't important). This
results in an output spectrum that contains isolated tones (no spectral leakage). Coherent
sampling may be used to reduce the effects of spectral leakage when determining the
SNR by ensuring1.. «fs (to randomize the quantization noise).
Signal-to-Noise Plus Distortion Ratio
In a practical data converter the output spectrum contains not only quantization noise but
distortion resulting from nonlinearities and mismatch in the data converter circuitry.
Figure 5.17
When we calculate the RMS quantization noise voltage using Eq. (5.7) and nonideal
components, we are actually calculating the noise plus the distortion in the spectrum.
Measuring SNDR 1
Until this point we have only used ideal components, so that distortion in the output
DAC, or loading digital da
spectrums was absent. We can rewrite Eq. (5.7) to indicate that when it is used with a
output of an ADC. Trying
measured spectrum, both noise and distortion are included in the result as
oscilloscope, is usually a \
IM- 1 comparable to the dynami
VQe-l-D,RMS = IL V;"FT(k ./RES) (5.\5) utilize narrow band filteri]
~ 1.=0
circuit and can have dyna
The signal-lo-noise plus distortion ratio is then given by spectrum. Also note that tl
SNDR = 20 log :p! j2

Qe+D.RMS
(5.16)
and distortion.)
Spurious Free Dynamic Rc
The effective number of bits, from Eq. (5.14), can then be calculated using Another specification of it:
term relates the peak sign~
N - SNDR 1.76 (5.17)
ejJ- 6.02 largest spike in the outpu
using
Example 5.5 SFI:
Suppose that the test setup shown in Fig. 5.9 is used with an input sinewave
having a frequency of 7 MHz, a peak amplitude of 0.5 V, and centered around 0.5 For the spectrum shown in
V (so that, once again, the sinewave swings from 0 V to 1 V.) Using SPICE V (-9 dB RMS), while the
simulation, determine the SNDR if there is a gain error in the ideal ADC in Fig, of this data converter is th(
5.9 (it's no longer ideal) so that each stage in the pipeline algorithm used to
Dynamic Range
implement the ideal SPICE ADC has a gain of 2.1 instead of the ideal 2.0.
The dynamic range of a d~
The resulting DAC output spectrum is shown in Fig. 5.17. The RMS noise plus
as the ratio of the largest
distortion voltage, VQe-+D,RMS, is 22.58 mY, using SPICE and remembering to
smallest output signal ch,
remove, with the SiH, the desired terms at DC and 7 MHz as well as the undesired dynamic range (DR) can b
images at 93 MHz, 107 MHz, and 193 MHz. The SNDR is then
0.51j2 DR 2010!
SNDR = 20 log 22.58 m V 0;; 24 dB
The effective number of bits is 3.7. In other words, a 5% gain error in the ADC
amplifiers results in an effective resolution of less than half of the ideal value of If a 1,000 to 1 dynamic n
8-bits.• bits is needed.
OS Mixed-Signal Circuit Design Chapter 5 Data Converter SNR 177
iindow represented, without the

linear and log amplitude scales
h that Is /f,n is a whole number

inewave cycles fit perfectly into
~ function isn't important). This
, (no spectral leakage). Coherent
l leakage when determining the
loise).
, not only quantization noise but

in the data converter circuitry.
;e using Eq. (5.7) and nonideal Figure 5.17 Output spectrum with ADC gain error (see Ex. 5.5).
the distortion in the spectrum.
so that distortion in the output Measuring SNDR requires a spectrum analyzer, when looking at the output of a
~ate that when it is used with a DAC, or loading digital data into a program that can perform an FFT when looking at the
i in the result as output of an ADC. Trying to measure SNDR using a time domain instrument, such as an
oscilloscope, is usually a waste of time because the dynamic range of the instrument is
comparable to the dynamic range of the data converter under test. Spectrum analyzers
'ES) (5.15)
utilize narrow band filtering on their input to reduce the inherent noise measured in a
circuit and can have dynamic ranges in excess of 120 dB over a very wide frequency
spectrum. Also note that the SNDR is sometimes abbreviated as SINAD (signal-to-noise
and distortion.)
(5.16)
Spurious Free Dynamic Range
calculated using Another specification of interest is the data converter's spurious free dynamic range. This
term relates thc peak signal in the output spectrum (the input sinewave or carrier) to the
(5.17) largest spike in the output spectrum up to the Nyquist frequency. This can be written
SFDR(dBc) = input carrier(dB) - unwanted tone(dB) (5.18)

;ed with an input sinewave
; V, and centered around 0.5 For the spectrum shown in Fig. 5.17, the input sinewave (carrier) has an amplitude of 0.5
I V to I V.) Using SPICE V (-9 dB RMS), while the largest unwanted tone has an amplitude of -46 dB. The SFDR
'or in the ideal ADC in of this data converter is then 37 dBc.
pipeline algorithm used to
:ead of the ideal 2.0.
. 5.17. The RMS noise plus The dynamic range of a data converter can be specified in several ways. One definition is
;PICE and remembering to as the ratio of the largest output signal change (e.g., [VREF+ -I LSB] VREF-) over the
1Hz as well as the undesired smallest output signal change (I LSB). Remembering 1 LSB = (VREF+ VREF_)/2 N the
)R is then dynamic range (DR) can be written as
N
VREF-)l2 -VREF-=2010g2 N 6.02N
24 dB VREF_)l2 N
l5% gain error in the ADC (5.19)

m half of the ideal value of If a 1,000 to 1 dynamic range (60 dB) is required, then a data converter with at least 10
bits is needed.
--
Another way to specifY DR is as the ratio of the RMS full-scale input sinusoid resolution will be less th:
amplitude, Vpl fi , to the input sinusoid amplitude (RMS) that results in an SNDR of 0 section we relate the sar
dB. (The RMS amplitude of the input signal is equal to the RMS quantization noise plus effective number of bits.
distortion, VQe+N,RMS, when the SNDR is 0 dB.) This is nothing more than saying that the around the ideal value.
SNDR can be used to specify DR, Figure 5.19 show!
sinewave frequency is rut
Example 5.6
point (when the sinewave
Determine the DR for the ideal ADC in Ex. 5.4 using Eq. (5.19). Compare the
input signal. We assume t
result to the SNDR calculated in Ex. 5.5.
ifthe sampling clock freg
Using Eq, (5.19), the DR is 48.16 dB (the ideal value). The SNDR calculated in is 50 ps I1T s ), then tt
Ex. 5.5 was 24 dB. Clearly, the SNDR is a better indication of DR than is the (where parts per million [1
value obtained using Eq. (5.19) .•
Specifying SNR and SNDR
The SNR and the SNDR are usually specified as a function of input sinewave amplitude
at a fixed frequency, Fig. 5.18. The x-axis in Fig. 5.18 is normalized so that an input
sinewave with a peak-to-peak amplitude of VREF+ VREF- corresponds to 0 dB. We might
be wondering how we differentiate between SNR and SNDR as both, up to this point,
have been calculated in the same way (Eqs. [5.71 and [5.15]). We continue to calculate
SNDR using a data converter output spectrum, remembering to zero out the desired tones
and images, and Eq. (5.15) as was done in Ex. 5.5. When we calculate the SNR, we
follow the same procedure except that now we also zero out any spikes or ~purs (spurious
responses) in the spectrum that are "sticking up" above the noise floor in the spectrum.
These spikes come from imperfections in the data converter and result in distortion in the
output waveform. Note in Fig. 5.18 how the SNR and the SNDR coincide until the input
signal amplitude gets reasonably large (so the distortion tones increase in amplitude
above the quantization noise).
ill
"0
.€'" Figure ~
B 60
if;
'6
'" 40
::l The slew rate of tt

-a
signal transitions high), is f
"
20
Vl
'0
<=
.9
.;
~ -80 -60 -40 -20 0
ti5 We can relate the uncerta
Normalized input signal amplitude (dB)
sampled voltage, 11Ti" usinE
Figure 5.18 Specfying SNR and SNDR for a data converter.
5.2.1 Clock Jitter If we require the uncertaint

We might assume that by using the ideal data converters in a system with "real world" -VREF_)l2 N +! and we reme
input and clock signals· we would get a resolution (number of bits) limited by the peak-to-peak c10ckjitter Cal
resolution of ideal data converters used. However, if the clock signal used isn't ideal, the
S full-scale input sinusoid resolution will be less than ideal because of a problem known as aperture jitter. In this
~t results in an SNDR of 0 section we relate the sampling clock's jitter to the data converters SNR and thus the
v1.S quantization noise plus effective number of bits. Clock jitter is the variation in the period of the doek signal
'I more than saying that the around the ideal value.
Figure 5.19 shows the basic problem. In this figure we have assumed the input
sinewave frequency is running at the Nyquist frequency/" (= Is 12 ) so that the sampling
point (when the sinewave crosses zero in this figure) is seeing the fastest transition in the
1- (5.19). Compare the
input signal. We assume the peak amount of jitter in the clock signal is 6.Ts • For example,
if the sampling dock frequency is 100 MHz (T, IOns) and the peak-to-peak clock jitter
le SNDR calculated in is 50 ps 6.Ts ), then the specification of the sampling clock stability is 5,000 ppm
tion of DR than is the (where parts per million [ppm] = 10-6 and 6.Ts (stability, ppm)· (l(fs)).
6.Ts peak-to-peak jitter

'input sinewave amplitude
)rmalized so that an input
esponds to 0 dB. We might
· as both, up to this point,
· We continue to calculate
) zero out the desired tones
oNe calculate the SNR, we
ly spikes or spurs (spurious
oise floor in the spectrum.
ld result in distortion in the
)R coincide until the input Ideal
nes increase in amplitude sampling point
~
Aperture
uncertainty/jitter
SNDR Figure 5.19 Data converter input signal and clock jitter.
The slew rate of the signal in Fig. 5.19, at the sampling point (when the clock
signal transitions high), is given by
~I
(5.20)
We can relate the uncertainty in the sampling instant, 6.Ts ' to the uncertainty in the
sampled voltage, 6.V" using
l. converter.
6.Vs .,
-T = TCj,Vp, or 6.Vs (5.21)
6. s
Ifwe require the uncertainty in the sampled voltage, 6.Vs' to be at most 0.5 LSB == (
1 system with "real world" -VREF_)!2N+land we remember Vp = (VREF+ VREF-)!2, then our maximum allowable
er of bits) limited by the peak-to-peak clock jitter can be determined for a particular data converter using
· signal used isn't ideal, the
180 CMOS Mixed-Signal Circuit Design Chapter 5 Data Conver
<~. (a resolution Joss;;:' 0.5

11 Ts,- N ,I' (5.22)
2 TYs
or in tenus of the sampling clock stability
where'!;n is, once agair
StabT
llty,ppm I1TS .JS
I'
T, = _I_
= I1Ts 11:.2 N (5.23)
bits lost due to the excI
loss in resolution is O.
Table 5.1 relates the stability requirements placed on a sampling clock for a data
(5.25) or (5.26). The id
converter resolution, N, if less than 0.5 LSBs aperture error or sampling voltage
system is clock jitter, c.
uncertainty is required of the data converter.
Table 5.1 Maximumjitter, "'T" for 0.5 LSB sampling uncertainty.
Example 5.S
For an ideal 8-bit
converter with 100
assuming the ADC'>
We can write the ,
peak-to-peak jitter a
or
Example 5.7 N
Suppose a phase-locked loop (PLL) is used to generate a clock signal for a data The effective numbe
converter. If the resolution of the data converter is 10 bits and the frequency of the
sampling clock coming from the PLL is 900 MHz, then specify the maximum Using Oversampling to J
jitter allowed in the output of the PLL. Assume that the maximum sampling error Suppose we limit the m.
allowed is 0.5 LSB and that the data converter is sampling a sinewave with a sampling frequency is re
frequency of 100 MHz.
Because the sinewave being sampled has a frequency below the Nyquist value,
Eq. (5.22) cannot be used directly. Instead, after reviewing the derivation of this
ill other words, we are f
equation, we can rewrite it in tenus of any input signal frequencY''!;n' as
(we are oversampling 1
1 1 (5.24) frequency ([). where K
I1Ts S N
2
'-
11:
. f,II!
2
signa\. Notice that Eq. (
noting that when'!;n 12, Eq. (5.24) reduces to Eq. (5.22), Using Eq. (5.24) frequency and data cony,
with the numbers in this problem results in a peak-to-peak jitter of 1.56 ps! The or the sampling frequenc
reader familiar with PLL design will recognize that this is a very challenging For a given maxi
requirement when designing a PLL (that is, to design a PLL with an output stability of the oscillator'
frequency of 900 MHz and an output jitter less than 1.56 ps) .•
St,
We're now in a position to answer how, given the peak-to-peak clock jitter, the
SNR ofa data converter is degraded from the ideal value (given in Eq. [5.13]) when the Ifwe were sampling at 1
input sampling clock isn't ideal. Rewriting Eq. (5.24) and assuming sampling clock would be
MHz, with lOps jitter w
1
I1Ts ;;:. N . 2 I' (5.25) increase the sampling cle
2 11: 'Jin
atleast 10,000 ppm (thq
xed-Signal Circuit Design Chapter 5 Data Converter SNR 181
(a resolution loss;?: 0.5 LSB), we get

(5.22)
t1Ts =__I_. (5.26)
2 N- NLru, 2n ·Jin
where In is, once again, the frequency of the input sinewave, and NLoss is the number of
(5.23)
bits lost due to the excess jitter. Assuming Eq. (5.25) is valid, then when NLoss is zero, the
loss in resolution is 0.5 LSB and Eq. (5.26) reduces to the equality condition in Eqs.
mpling clock for a data
(5.25) or (5.26). The ideal data converter's SNR, assuming the only non-ideal factor in the
Tor or sampling voltage
system is clock jitter, can be written as
effective bits, N'lf
I ,
: uncertainty. SNR = 6.02' eN - NLoss 0.5) + 1.76 (in dB) (5.27)
Example 5.8
For an ideal 8-bit ADC clocked at 100 MHz, determine the SNR of the data
113.4
converter with 100 ps of peak-to-peak jitter in the input sampling clock, t1Ts ,
assuming the ADC's input is a full-scale sinewave at 25 MHz.
28.3
7.1
We can write the number of bits lost by solving Eq. (5.26) as a
function of
peak-to-peak jitter as
1.77
0.44 NLoss = N + 3.32· log (2n ·Jin . t1Ts) assuming t1Ts ;?: .-LN . 2 +. (5.28)
2 n 'jin
0.11
or
NLoss = 8 + 3.32 ·10g(2rc· 25MEG·IOOps) = 2 bits
dock signal for a data The effective number of bits, NeD' is then 5.5 and the SNR is 34.87 dB. •
ld the frequency of the
specify the maximum Using Oversampling to Reduce Sampling Clock Jitter Stability Requirements
.ximum sampling error Suppose we limit the maximum input frequency coming into an ADC to In , such that the
ng a sinewave with a sampling frequency is related to the maximum ADC input frequency by
ow the Nyquist value, = K·Jin or Jin = 2K (5.29)

2
~ the derivation of this
In other words, we are getting at least 2K samples for every cycle of the input sinewave
lenCy,J;n' as
(we are oversampling the input signal). If we were sampling at twice the Nyquist
(5.24) frequency (is), where K I, then we would get two samples for every cycle of the input
signal. Notice that Eq. (5.24) gives the maximum jitter specification for a given input
;.22). Using Eq. (5.24) frequency and data converter resolution, but it doesn't specify the sampling frequency, is ,
: jitter of 1.56 ps! The or the sampling frequency period, Ts'
is a very challenging
..
L PLL with an output
k-to-peak clock jitter, the

For a given maximum jitter, t1Ts' we can reduce the requirements placed on the
stability of the oscillator by increasing the sampling frequency. This can be written as
Stability(new), ppm = [stability(old), ppm] . K (5.30)
~n in Eq. [5.13]) when the. If we were sampling at I MHz and the stability required was 10 ppm, then the jitter in the
ling sampling clock would be at most 10 ps, peak-to-peak. Increasing the sampling rate to 100
MHz, with lOps jitter would require an oscillator stability of 1,000 ppm. If we were to
(5.25) increase the sampling clock frequency to I GHz, then the stability of the clock would be
at least 10,000 ppm (the period is 1 ns and the jitter is lOps or 1% [10,000 ppmD.
182 CMOS Mixed-Signal Circuit Design Chapter 5 Data Converter SN
characteristics of the data cor

Example 5.9
In Table 5.1 we saw that the 16-bit data converter clocked at 44.1 kHz could have jitter or a random variable
at most 111 ps peak-to-peak jitter to limit the sampling uncertainty to 0.5 LSB. describing the spectrum of a t
We saw that the stability required of the oscillator under these cireumstances was The Spectral Density ofDetel
5 ppm at 44.1 kHz. What would happen to the stability requirements of the
oscillator generating the sampling clock if we increased the sampling cloek Consider the simple sinewav(
frequeney to 128·44.1 kHz 5.645 MHz?
We know that the input bandwidth, prior to increasing the sampling frequeney, is This signal is termed "deterrr
limited to 44.1 kHz/2 or 22.05 kHz (= B, the bandwidth of the input signal). We it is continuous or sampled. \
then assume the maximum input frequency, In , remains at or below 22.05 kHz time Riit), using the autocorl
even after we increase the sampling frequency. We can define the oversampling
factor, in this example, as
6
K 2.822 x 10 = 128
22.05 x 10 3 The average value of Eq. (5.3
The jitter requirement remains III ps whether we use a sampling frequency of
44.1 kHz or 5.645 MHz. However, now that the clock frequeney has increased to
5.645 MHz, the stability required of the oscillator has gone from approximately 5
ppm to 640 ppm.•
or knowing
It's important to note that the oversampling ratio, K, is given by
sinA· :
K =fs/2 B for /;n ~ B (5.31)
B we can write
If we desire less than 0.5 LSBs aperture error, and we are using oversampling, then we
can use Eqs. (5.22) and (5.31) to write vz .sin 2n/;n 1"
1 K 1 When we integrate this rest

l1Ts ~ 2N . rr.fs = 2N . 2rr.B (5.32)
frequency of 4n/;n (remembe
where, once again, B is the bandwidth of the input signal and K is the oversampling ratio. Over a long period of time th
As shown by this equation and in Eq. (5.30), using oversampling reduees the value ofEq. (5.33) as a funct
requirements placed on the stability of the sampling clock. Tfj/2
A Practical Note Rin(t)

. 1
hm -T
J I
To-'oo 0 --Tol2
We need to point out that the effects of clock jitter are possible even if the clock is
The spectrum of the averag
perfectly stable because of the clock's finite transition times (rise and fall times). If the
transform of the autocorrelat
rise time of the clock signal in Fig. 5.19 is finite, say 50 ps, then the same derivations and
function (PSD) and is given 1
discussions concerning jitter in this section can be applied to determine how the SNR of
the data converter is affected. We would assume the aperture window is a function of the
transition times of the sampling clock signaL The slower the transition times, the larger
the sampling uncertainty. In any practical data converter the SNR, and thus the effective
number of bits, will be reduced because of the clock jitter and finite transition times as The power spectral density fi
the input signal frequency increases.
5.2.2 A Tool: The Spectral Density
The observant reader may have noticed, in the last section, that we only discussed the This is simply two impulses
of VZl4 (V2/Hz). The total a
peak-to-peak jitter, l1T" and how it effects the data converter's performance. It is very
useful, in many situations, to also have an idea how the spectrum or spectral
characteristics of the data converter's output change as a function of the random sampling
d at 44.1 kHz could have jitter or a random variable such as noise. In this section we discuss tools useful in
; uncertainty to 0.5 LSB. describing the spectrum of a random signal.
these circumstances was The Spectral Density ojDeterministic Signals: An Overview
lity requirements of the
$ed the sampling clock Consider the simple sinewave signal of the form
Vin(t) -= Vp sin2rgtnt (units, Y) (5.33)
Ie sampling frequency, is This signal is termed "deterministic" because the signal has a well-defined shape whether
of the input signal). We it is continuous or sampled. We can find the average power of this signal, as a function of
s at or below 22.05 kHz time Riit), using the autocorrelation junction (ACF) for continuous signals given by
define the oversampling
R,n(t) == lim
To-w"
i Tol2
J Vin(t)· Vinet + t)· dt (units, y2)

0 -To12
(5.34)
The average value ofEq. (5.33) as a function of time is then

a sampling frequency of Tol2
equency has increased to
ne from approximately 5
Rin(t) lim 1
T04r:t::J
J [V sin2rgtnt]· [V sin2nJin(u t)]dt
p p (5.35)
-Toll
or knowing
; given by
sinA . sin B t[ cos(A - B) cos(A + B)] (5.36)
(5.31 )
we can write
lsing oversampling, then we V2
Vi .sin 2rgtnt· sin 2nJinCt + t) -= f[cos2nJint cos 2rgtn{t + 2t)] (5.37)
(5.32) When we integrate this result, the term cos [2rif,n(t + 2t)] represents a sinusoid with a
frequency of 4rgtn (remembering our integration variable is t) and a phase shift of 2nJint.
K is the oversampling ratio. Over a long period of time this term averages to zero. Therefore, we can write the average
oversampling reduces the value ofEq. (5.33) as a function oftime (the autocorrelation function)
Rin(t) lim
To->m
i Toll
0 -To/2
V2
J 2' cos 2rgtnt . cit -= f .cos 2rgtnt (units, y2) (5.38)
ossible even if the clock is

. (rise and fall times). If the The spectrum of the average value of a function can be found by taking the Fourier
len the same derivations and transform of the autocorrelation function. The result is called the power spectral density
, determine how the SNR of function (PSD) and is given by
window is a function of the
~ transition times, the larger
Pin(f) = 1 Rin(t)· e-i2rrjl . dt (units, y2/Hz or y2 . s) (5.39)
SNR, and thus the effective
nd finite transition times as The power spectral density function of Eq. (5.33) is then, with the help ofEq. (5.38),
~
Piif) ; . [&(f+Jin )+8(f-Jin)] (units, y2/Hz) (5.40)
that we only discussed the This is simply two impUlses in the frequency spectrum located at ± hn with an amplitude
er's performance. It is very of V;/4 (y2/Hz). The total average power of this signal is given by
the spectrum or spectral
184 CMOS Mixed-Signal Circuit Design Chapter 5 Data Converter ~
"" cc
PAVG = JPin(f)' dJ J
2· Pin(f)' dJ (units, V /Q or watts)
o
2
(5.41)
assuming a l-Q (normalized) load, which, for Eq. (5.33), is Vp2 (V2). The PSD is the Fourier tran
The voltage spectral density, with units of VI jHz , is simply the square root of
Eq. (5.39) (that is, the square root of the PSD Jpin(f) D. The root mean square
(R.\1S) voltage of a signal is given by The RMS value of the sam1
through an ideal reconstru
VRMS=JPAVG = 21P in (f).dJ= !21(voltagespectraldensity)2.dJ (5.42) again, Vpl Ii .
The PSD of
o , 0 Vi14 at frequencies of ± Is.·
The RMS value of Eq. (5.33) is simply, as one would expect for a sinewave, Vpl Ii. The Spectral Density ojRa1
Note the similarity between Eq. (5.42) and Eq. (5.7). Let's use our jitter discussi<
of a random signal. We'll d
Example 5.10
random variable that falls b
Determine the ACF, PSD, average power, and RMS value of a signal Vet) made
in the region (just as was a
up of three sine waves with peak amplitudes of V1 ' V2 , and V3 with frequencies of
when calculating the RMS
ft, J;, and J;. assume the jitter has a G
Using Eqs. (5.34) and (5.38), the ACF is practical and realistic situati
R(t) =
V2
T cos 2rrJI t +
V2
-t V2
cos 2rr/2t+ ; cos 2nJ3t (units, V2)
Consider the repres
figure shows the ideal po
represented on the probabi
The PSD (positive frequencies) is determined using Eqs. (5.39) and (5.40)
rising edge of the clock, tr;
P(f)
vf vi
4,o(f-JI)+4·o(j-J2)+4·U( -j3)(umts, V 1Hz)
vi s: J . 2
PDF as shown. We are aSSl
the rising edge of the clock
probability of being in the
The average power, using Eq. (5.41), is
boundary (as shown in traCt
PAVG
vl + vi + vi (units, watts)
2 Trace
Finally, the RMS value of the signal is given by Ideal cI
(units, V) 2~t{
Note that if we added phase shifts to OUf signals the results would be the same; the 3~t(
phase shift doesn't change the signal's average value, so we get the same results
whether sines or cosines are used in our original spectrum .•
4 _ _ _ _-!~al
Next, suppose that the sinewave specified by Eq. (5.33) is sampled at a rate ofls
Vin(nT.,) = Vp sin(2nf;n' nTs) (5.43) 5~ Edge cl
The ACF for a sampled signal can be written as

. 1 N Peak-to-peak jitter, D.T,
Rin(nTs) =hm (2V 1)
N-.oo ,+
2:
k~-N
vin(kTs )' vin(kTs + nT.,) (5.44)
which results in Figure 5.20 Clock

anywl
v1ixed-Signal Circuit Design Chapter 5 Data Converter SNR 185
2
(5.41) Rin(nTs) = fV cos 2n/in . nTs (units, y2) (5.45)
The PSD is the Fourier transform of this equation,

V2 00
is simply the square root of Pin(f) = 4;s k"'foo [8(f-.fin + kfs) + 8(f+/in + kfs)] (5.46)
) D. The root mean square
The RMS value of the sampled sinewave, Eq. (5.43), assuming we have passed the signal
through an ideal reconstruction filter (RCF) with a bandwidth of fs/2, is simply, once
~ctral density)2 . df (5.42) again, Vpl fi . The PSD of the signal, after passing through the RCF, has an amplitude of
Vp4 at frequencies of±/;".
lect for a sinewave, Vpl fi . The Spectral Density ofRandom Signals: An Overview
Let's use our jitter discussion of the last section to illustrate how to look at the spectrum
of a random signal. We'll do this in two parts: (1) we'll begin by assuming the jitter is a
random variable that falls between two limits and has equal probability of lying anywhere
ue of a signal Vet) made
in the region (just as was assumed for the quantization error probability density function
I1d V3 with frequencies of
when calculating the RMS quantization noise voltage in the last chapter), and (2) then
assume the jitter has a Gaussian distribution around some average value (the more
practical and realistic situation) and determine how the output of the ADC is affected.
Consider the representations of clock jitter shown in Fig. 5.20. Trace I in this
figure shows the ideal position of the rising edge of a clock signal. This point is
represented on the probability density function (PDF), p(t) , at time zero. On the next
(5.39) and (5.40)
rising edge of the clock, trace 2, the edge is a little too early and is represented on the
PDF as shown. We are assuming, probably incorrectly for most practical situations, that
f-/J)(units, y2/Hz)
the rising edge of the clock is falling within the peak-to-peak boundaries with the equal
probability of being in the correct position (as shown in trace 1) or at the edge of a
boundary (as shown in trace 4). We also know that the area under the PDF curve in Fig.
(units, watts)
Trace
: Ideal clock edge position p(t)
Probability density function, PDF
(units, Y) 2~tooearlY 5 1 3 4
ts would be the same; the 3~toolate ~ / ~ I

) we get the same results
11.
4_...;_ _-'~ at the boundary
3) is sampled at a rate ofis
o t!.Ts time
(5.43)
5~ Edge close to boundary
2
:< );
Peak-to-peak jitter, t!.Ts
vin(kTs + nTs) (5.44)
Figure 5.20 Clock jitter assuming the edge falls with the same probability
anywhere within the peak-to-peak limits.
186 CMOS Mixed-Signal Circuit Design Chapter 5 Data Converte
5.20 must equal unity, and the average value (also known as the mean or the expected
value and denoted by < y > or y) of a PDF is given by
..
00 RMS JItter = (J '" 6/:iTs
Average value, y, ft. pet) . dt (5.47)

Peak-to-peakjitter", I
Example 5.11
Detennine the average value of the jitter with the PDF shown in Fig. 5.20.
We can use Eq. (5.47) to detennine the average value of any PDF. Applying this
equation to the PDF shown in Fig. 5.20 results in
flT.,!2
Average value, y, == ft. /:iT . dt = 0

-flT,2 s
This somewhat obvious result means that the average position of the clock rising Figure 5.21
edge is the ideal position indicated by trace 1 in Fig. 5.20. Any PDF that is
symmetrical about some center point will have an average equal to the center sampling clock affects a
point. • (5.20), (5.21), and (5.22).
given time, as
The variance of the PDF is defined as the average of the square of the signal's
departure fTOm its average value. For a random signal this can be written as
(x"
f (y_y)2 ·p(y)·dy (5.48)
where 8Ts(t) is a randon
time. (The variable 8Ts(t
and the expected transiti(
where (J is the standard deviation of the PDF (the square root of Eq. [5.48]). For our value of 8Ts(t) is /:iTs, v
purposes, in this book, we can think of variance as the average power of a random probability distribution fi.
(voltage) signal and the standard deviation as the RMS value of the signal (see Eqs.
[5.41] and [5.42]). Example random signals include the time difference between the Rewriting Eq. (5.
actual edge of a clock and the ideal edge location (jitter), the voltage difference between written as
the input of an ADC and the ADC's reconstructed output (quantization noise), and the
random fluctuations of electrons due to thennal motion in a resistor (thennal noise).
Example 5.12 We're interested in the

Detennine the RMS value of the jitter when the jitter has a probability density quantization noise plus
function, PDF, as shown in Fig. 5.20. SNDR. Notice that the Sf
the sampled signal) so '
Using Eq. (5.48) the variance of the jitter PDF is reconstruction filter.) Ais
flTd? Eq. (5.50) simply shifts t
d 1
f
-flT,i2
2
t . /:iT .
s
f=
3jflT/2
3 . /:iT . t -flTi2
s
carrier in an amplitude-m
and thus the RMS jitter is Example 5.13

Repeat Ex. 5.8 assum
(J = ~ RMS jitter, (seconds) In this example the I
~12
frequency, fm' is 25
where /:iTs is the peak-to-peak jitter in the sampling clock rising edge. Note the power in the sampline
similarity to the derivation of VQc.RMS in Sec. 5.1.1 .•
A more useful discussion of jitter can be constructed if we assume the jitter has a
Gaussian PDF, as shown in Fig. 5.21, and attempt to describe how the jitter in the
lixed-Signal Circuit Design Chapter 5 Data Converter SNR 187
; the mean or the expected p(t)

" !J.Ts
RMS J1tter
(5.47)
cr"'6
t
pet) = .expl-LJ
Peak-to-peak jitter'" !J.Ts 2cr 2
Nn in Fig. 5.20.
:my PDF. Applying this
o cr 2cr Time
. dto:=O
ition of the clock rising Figure 5.21 Sarnplingjitter with a Gaussian probability distribution.
5.20. Any PDF that is
1ge equal to the center sampling clock affects an ADC output spectrum with a single-tone input. Using Eqs.
(5.20), (5.21), and (5.22), we can write the sampling error voltage (review Fig. 5.19), at a
given time, as
f the square of the signal's
be written as !J. Vs(t) 0:= oTs(t)· Vp ·2rr.Jin . cos 2rr.Jint (5.49)
where oTs(t) is a random variable indicating the jitter in the sampling clock at a given
dy (5.48)
time. (The variable oTs(t) is the time difference between the actual clock transition time
and the expected transition times that are spaced by Ts [see Fig. 5.20].) The peak-to-peak
oot of Eq. [5.48]). For our value of oTs(t) is !J.Ts, while its average value is zero. Again, we assume that the jitter
,rerage power of a random probability distribution function is Gaussian, as seen in Fig. 5.21.
lue of the signal (see Eqs.
me difference between the Rewriting Eq. (5.49) using a discrete time step nT" the sampling error can be
voltage difference between written as
luantization noise), and the Sampling error amplitude Carrier term
sistor (thermal noise).
, .
!J. Vs(nTs) = oTs{nTs)' Vp ·2rr.Jin· COS 2rr.JinnTs (5.50)
We're interested in the spectrum of this error signal as it will add to our RMS
as a probability density quantization noise plus distortion voltage, effectively lowering the data converter's
SNDR. Notice that the spectrum of Eq. (5.50) will have aliased components (and so will
the sampled signal) so we need to filter out these components above Is 12 (with the
reconstruction filter.) Also note that multiplying the sampling error by the cosine term in
Eq. (5.50) simply shifts the error spectrum to a frequency 1;•. The cosine terms act like a
.) = __
(!J.T )2 ,
s _ (seconds")
carrier in an amplitude-modulated signal. This is illustrated in Fig. 5.22.
12 12
Example 5.13
Repeat Ex. 5.8 assuming the clock jitter has a Gaussian PDF.
seconds)
In this example the peak amplitude of the input signal, Vp ' is 0.5 V, the input
frequency, 1;., is 25 MHz, and the peak-to-peak jitter is 100 ps. The average
;k rising edge. Note the power in the sampling error amplitude spectrum is
2
= cr 2 • .....
-,--,,---:-=-....,;.... = (\. !J.Ts
6
\) 2 • (Vp . 2rr.Jin)
2 (5.51)
if we assume the jitter has a . PAVGJiller
;cribe how the jitter in the

r
r
188 CMOS Mixed-Signal Circuit Design Chapter 5 Data Converter Sl
Sampling error amplitude spectrum Data converter output spectral content resulting from jitter
~4) l.--~ o f o f
)
o
Figure 5.22 Modulating sampling error with an input sinewave frequency. Figure 5.23 Sampling an
or Specifying Phase Noise fro",
1006Ps]2 . (0.5 . 2n '225 MHz)2 It's important to note that \'\

PAVGJilter [ 0.858 X 10-6 V 2
(that is, have odd order ha
generally, more appropriat{
while the RMS voltage associated with this error is 0.926 mY. The quantization
However, because the term~
noise associated with this 8-bit data converter is variation in the period of .
VREF+ - VREF specification from measured
1.3 mV
2NjIT. Consider the repres(
The RMS noise voltage due to clock jitter and quantization effects is then given density) shown in Fig. 5.24.
by voltage (or power) with unit
power of the fundamental (c
JO.858 2 + 1.3 2 mV = 1.56 mV power in a bandwidth at son
We can calculate the SNR using
r::;
SNR=20.1 0.5/,,2 47.1 dB
og 1.56 mV Phase noise, dBc/Hz
giving an effective number of bits, from Eq. (514), equal to 7.53. Note that this is
a significant improvement over what was calculated in Ex. 5.8, where the jitter where the first term is the ne
variation was always the peak-to-peak value .•
The PSD of the sampling error amplitude, described by Eq. (5.50), can be
determined with the help ofEq. (5.4l)
2 oCJ
Cf
2 -'..-(V-,,-P_'2-::-n..::.. if,:. . .,;11):-
•- 2 2
o
JPjitter(f) . d/ (5.52)
If the spectrum of the phase noise due to jitter is narrow, as seen in Fig. 5.22, then the
spectral density of the sampling error, Pjit/.,.(/), is concentrated around the frequency of
the input sinusoid. However, if we assume the phase noise spectrum is white and evenly
distributed throughout the base spectrum (so that we integrate Eq. [5.52] from DC to//2), o
we can write
2
Cf2 (Vp' 2rrjin)
Pjiller(f) = /s . 2 (5.53)
Fi~
The power spectral density of the sampling error voltage, assuming even distribution of
the noise throughout the base spectrum, is shown in Fig. 5.23.
ixed-Signal Circuit Design Chapter 5 Data Converter S:t-<R 189
content resulting from jitter
)
f o
lewave frequency. Figure 5.23 Sampling amplitude error PSD assuming sampling error spectrum is white.
Specifying Phase Noise from Measured Data
858 x 10-6 y2
It's important to note that we have been discussing clock signals that are square waves
(that is, have odd order harmonics) and so discussing jitter (a time-domain term) is,
generally, more appropriate than discussing phase noise (a frequency domain term).
mY. The quantization
However, because the terms are both widely used to indicate the same, basic, effect (a
variation in the period of a periodic waveform), we will briefly discuss phase noise
Y specification from measured oscillator data.
Consider the representation of a measured oscillator spectrum (power spectral
III effects is then given density) shown in Fig. 5.24. In general, oscillator noise is specified in terms of the carrier
voltage (or power) with units of dBc (decibels with respect to the carrier). The ratio of the
power of the fundamental (called the carrier or sampling clock) at is is taken to the noise
power in a bandwidth at some offset from the fundamental
IO.log(V Z)
r , 10· log (V2IHz)
B
Phase noise, dBc/Hz 10 . log r11 Posc(f) . df ] - 10· log P(ls ) (5.54)
) 7.53. Note that this is LrLJ
5.8, where the jitter

1<:. where the first term is the noise power at an offset fromis.
:d by Eq. (5.50), can
1/
,een in Fig. 5.22, then the

d around the frequency of
:ctrum is white and evenly
~q. [5.52] from DC toisI2), o ls f
fLI
(5.53) fm
Figure 5.24 Measured oscillator spectrum.

Iming even distribution of
5.3 Improving SNR using Averaging or, generalizing this to K-f:
Examine the two-path combination of ADCs and DACs shown in Fig. 5.25. The top ADC
and DAC are the path we had back in Fig. 5.4 clocked at 100 MHz. The bottom path is a
mirror image of the top except that its clock signal is inverted. The two resistors are used Further note that if we w(;
to sum (or more correctly average) the outputs of the DACs into a single output. This filter out part of the quanti
configuration effectively samples the input at 200 MHz (200 Msamples/s [2 .];]). this section to improve SN
Example 5.14
Repeat Ex. 5.1 but use
An,log ~~ 8 Ideal Analog seen in Fig. 5.25.
v in_~ Ideal I
:l
1
"["0 MH, AD~

I
8-bit DAC As discussed in Ex. 5
f, ,'-bit L I =Vouta +2 Voutb input signal is 1.13 n
~~ Id~l
Voal
Digital
results in adding, using
@2f,
8 Ideal I I
8-bit DAC Voutb

~itADC I
to the input signal. Fi
noise added to the inp\
Figure 5.25 Using two paths to average the quantization noise. O.787mV.•
Figure 5.26 shows the quantization noise PSD spectrums when the single path z.omV-r-
ADC/DAC is clocked atfs and then at 2fs. Notice how the quantization noise is spread out 1.5mVj······
over a wider frequency range when a higher sampling frequency is used. As seen in Ex.
5.1 the sampling frequency doesn't affect the RMS value of quantization noise. The area
of the spectrums in Fig. 5.26 is equal to VZsB/12 (negative frequencies are not shown) for
both sampling frequencies.
1. vIsB
@2f, 2 12];
ViSB
12]; +---------------------, ~ J
f Figure 5.27 Sh
Figure 5.26 Quantization noise power spectral density for two sampling frequencies. An Important Note
For averaging to effective]:;
Now if we were to compare the quantization noise added to an input signal using be linear to the final outpu1
a single path clocked at 21s to a system using two paths clocked at fs we would find that Fig. 5.28. In the ideal sitm
the two path system added less noise. In order to understand why, notice that when we that falls exactly in betwee
take two random uncorrelated variables, the quantization noise added to the input signal converter has a nonlinearit:;
from each path in Fig. 5.25, and average (sum the power from each) them we get is much different from t1:
o 2 contains a missing code (aT
VQe,RMSl + V Qe,RMS2 times of 1-LSB results in t
vQe,RMS.2-path
2
2
(5.55)
converter is nonmonotonic
Signal Circuit Design Chapter 5 Data Converter SNR 191
or, generalizing this to K-paths
g. 5.25. The top ADC 1 VLSB

V Qe,RMS = JK' [l2 (5.56)
The bottom path is a
two resistors are used
Further note that if we were to add a lowpass filter to the output of our DAC, we could
a single output. This
filter out part of the quantization noise and further decrease V Qe,RMS' We use these ideas in
les/s [2 ·Is D. this section to improve SNR; however, let's do an example before going any farther.
Example 5.14
Repeat Ex. 5.1 but use, to increase the sampling frequency, the two path topology
Analog seen in Fig. 5.25.
As discussed in Ex. 5.1, the RMS value of the quantization noise added to the
VOlil = VoutQ +2 Volilb input signal is 1.13 mY. Using two paths to increase the sampling frequency
results in adding, using Eq. (5.56),
@2/s
VQe,RMS= ~. 3.9},mV =0.797mV
v2 12
to the input signal. Figure 5.27 shows the simulation results (the quantization
noise added to the input signal when two paths are used). The simulated VQe,RMS is
. nOise. 0.787 mV .•
when the single path 2.0mV'-,-----,----,-------:------,-----'~"'--__,_-_,___-_,___-,____,

on noise is spread out 1.5mV
. used. As seen in Ex. 1.OmV
~ation noise. The area
O.5mV
ies are not shown) for O.OmV
-O.5mV
-1.0mV
2
LSB
-1.5mV ,,
, , ,, ,
.., , ,
,,
, ,
............ '. --- _._ ..... -. - -- -- _. - ...... ---- - -- -- --'- -... " .'- .. --- -
2/s
-2.0mV ~.-
,
,
,, .
,
,
,
,
,,
'-.
,
,
,,
-.~
•
,
. , ,
,
_.'-
I
I
,,
,
,
,
,
,
,
-2.5mV ······-r······-f-----··r-····
I , ,
-r-----·~-····--:-------f-------~---·· -~-"-----
, •
-3.0mV+--i-'--'i------i-'--'-i-. --+--+---j-'--i--'--1-----I
o.o~s O.2~s O.4~s O.6~s O.8~s 1.0~s 1.2~s 1.4~s 1.6~s 1.8~s 2.0~s
/ Figure 5.27 Simulated quantization noise using two-paths, see Ex. 5.14.
,ling frequencies. An Important Note

For averaging to effectively reduce the RMS quantization noise, the ADC and DAC must
) an input signal using be linear to the final output resolution. In order to understand this in more detail examine
Is we would find that Fig. 5.28. In the ideal situation, two adjacent codes are averaged to give an output code
, notice that when we that falls exactly in between the outputs of the data converter. In the case where the data
led to the input signal converter has a nonlinearity, the averaged point doesn't necessarily provide an output that
,them we get is much different from the data converter outputs themselves. If the data converter
contains a missing code (an input difference between two inputs at consecutive sampling
(5.55) times of l-LSB results in the same output), then the averaging does nothing. If the data
converter is nonmonotonic (an increase in the data converter's input doesn't result in an
-,." -
on the bandwidth of the ~

Input signal Input signal increased the sampling r
density seen in Fig. 5.26
Ideal code level limit our desired input si
input sinewave at 1s12 w
~AVeraged
Example 5.15
For the topology se
~points From this spectrum
Averaged
- Points input signal. Compa!
To begin let's write (
• Indicates output of the data converter
Ideal situation Nonlinearity in transfer characteristics

so the PSD of the qu
Figure 5.28 How ADC or DAC linearity affects averaging.
increase in its output) then the averaged value is meaningless. Finally, note that an input
DC value (a digital code that isn't changing for the DAC, or an analog voltage that isn't This PSD is plotted
changing for the ADC) or a value that isn't "busy" (not changing by at least I LSB in
between sampling instances) will not benefit from averaging.
5.3.1 Using Averaging to Improve SNR
2
VLS,
The averaging topology shown in Fig. 5.25 is not practical in most situations (one notable
exception is the parallel combination of noise-shaping converters discussed later in the 3.1
book). The silicon area required to implement the extra ADC and DAC generally costs
more than is gained by the reduction in quantization noise. Figure 5.29 shows how we can
add a digital averaging filter (in this figure averaging two ADC's outputs, or K = 2) to the
output of the ADC to reduce quantization noise. By lowpass filtering the quantization
Figure 5.30 QuaT
noise PSD seen in Fig. 5.26, we reduce the amount of noise added to our signal.
Unfortunately, this lowpass filtering also limits the range of allowable (wanted) signal To determine th,
frequencies. Notice that both the ADC and digital averaging filter are clocked at a rate of
Is. The averaging filter seen in Fig. 5.29 is described using Figs. 1.16 and 1.17.
We might, at this point, assume that we can use a low-resolution ADC, say 6-bits,
with a significant amount of averaging (K » 2, see the lowpass Sine-shaped filters seen or
in Ch. 4) to attain large resolutions (again the ADC must be linear). Assuming the input
to the ADC is busy and we place restrictions on the bandwidth of the signals coming into
the ADC then we can increase the resolution by averaging. We have to place restrictions
It would appear that
V;n-,
~ Ideal
ADC
'------'
~-+/-~~r-+/-
Lowpass filter
Digital
after we review the
the gain of the filte
Knowing this we ca
Figure 5.29 Using a digital averaging filter to reduce quantization noise.

on the bandwidth of the signal coming into the ADC because, unlike Fig. 5.25, we haven't
nput signal increased the sampling rate of the signals. Therefore, the amplitude of the power spectral
density seen in Fig. 5.26 remains unchanged. For an averaging of two, we would have to
Ideal code level limit our desired input signal bandwidth to is 14, Fig. 1.17. If this wasn't the case, then an
input sinewave at is 12 would average to zero.
Actual code level Example 5.15

For the topology seen in Fig. 5.29, sketch the output quantization noise PSD.
From this spectrum determine the RMS value of the quantization noise added to
Averaged
- - - - Points input signal. Compare this value to the one obtained using Eq. (5.56).
To begin let's write (see Eq. [lAO])
msfer characteristics
I + Z-l = 2 ·1 cos ni 1
so the PSD of the quantization noise can be written as

averaging.
V~e(f)= ~~h .4·lcos2nil forO~f~4
. Finally, note that an input
an analog voltage that isn't This PSD is plotted in Fig. 5.30.
aging by at least 1 LSB in
nost situations (one notable

:rters discussed later in the
=: and DAC generally costs )
:ure 5.29 shows how we can f
fn=!sI2
C's outputs, or K = 2) to the
is filtering the quantization
Figure 5.30 Quantization noise power spectral density after averaging two samples.
loise added to our signal.
o allowable (wanted) signal
To determine the RMS quantization noise (see Eq. [1.29])
ilter are clocked at a rate of
s. 1.16 and 1.17.
·resolution ADC, say 6-bits,
v2 (
VJe,RMS = 2 J I~h' 2
1,12
I+ cos [f])
2nls . df
ass Sinc-shaped filters seen
or
linear). Assuming the input .
h of the signals coming into 2 2 [ ]/=1,12 2 2
V2 = V LSB + V LSB sin2nL = V LSB "* l. V LSB
1e have to place restrictions Qe,RMS 6 6n fs 1=0
6 K 12
It would appear that our RMS quantization noise has actually increased! However,
Digital after we review the transfer characteristics of our filter seen in Fig. 1.17 we see
the gain of the filter at low frequencies (where our desired signal resides) is two.
--+ Knowing this we can write the SNR as
~r
2V lJi V lJi
SNR = 20 log P j6 = 20 log P [i4
VLsBI 6 VLsBI 24
luantization noise.
. ..- .........
or, once again,

ADC output 1
VQe,RMS =-I- .-
VLSB
- (5.57) -r
JKffi
•
Ideal Signal-lo-Noise Ratio
Reviewing the derivation ofEq. (5.13) and using Eq. (5.57) we can write the ideal SNR
for a data converter employing a digital (averaging or Sine-shaped) lowpass filter as
1 LSB
E -0~
t
Averag
ADC output 2
SNRideal = 6.02N + 1.76 + 10 10gK (5.58) Averaging two points (id
where N is the number of bits (the resolution) of the data converter whose output is being (a)
averaged. Using no averaging, that is K = I, results in this equation simplifying to Eq.
(5.13). Averaging two samples causes the SNR,deal to increase by 3 dB or the effective
resolution of the data converter to increase by 0.5 bits. The increase in resolution due to
averaging can be written as
1010gK
Increased resolution,}lhnc (5.59) black dot) is shifted dow]
6.02
offset from its ideal posi
Figure 5.31 shows how averaging the output of a data converter changes the effective we could use any numbf
resolution of the data converter. Again, note that the increase in resolution is based on the better than the desired fir
following assumptions: a busy input signal, the input signal is bandlimited, and the data
converter is linear to the final resolution (data converter resolution, N, + improvement in The number of
resolution, NIne> coming out of the averaging circuit. improvement in resolutio
(the number of bits comi)
Improvement in resolution,NIne
(bits added)
SNRideal =- 6.02(N + NIne) + 1.76 The ADC output should:

the changes will be diffe
soot achieve an increase in th

(its actual levels must be
3.33!
1.67
where no averaging (Nine
o -+-.--+---f---+I·----~> This is a sign(fzcant lim
10 100 lk K Number of points averaged ADC. This is especially
and DNL less than ±0.5 I
Figure 5.31 Using averaging to improve data converter resolution. feedback topologies that
allow averaging to more I
5.3.2 Linearity Requirements
5.3.3 Adding a Noise
Examine the cases for averaging ADC outputs shown in Fig. 5.32. In part (a) we show the
ideal situation where the black dots indicate two consecutive outputs spaced by one LSB Our assumption, when (
(time is not shown in this figure). The ADC outputs in part (a) are located on the ideal density of the quantizati.
levels, while the averaged output falls exactly in the middle of these levels (and hence our input is not "busy"). In 0
increased resolution). Part (b) of this figure shows the situation where the ADC outputs the ADC input that has a
are shifted downwards by 0.5 LSBs from their ideal levels. Following this offset, the
averaged point shifts downwards as well. In Palt (c) the top output of the ADC (the top
Ked-Signal Circuit Design Chapter 5 Data Converter SNR 195
(5.57)
ADC output I
.}
•
i:.~Averaged point
~ Ideal level It 0.5 LSB
E
/DJ>.L
1 LSB ~.~ ~ ~ 1 LSB ~tf· ~
1 LSBC
~ Averaged point 0
~can "'Tite the ideal SNR
ed) lowpass filter as
(5.58)
t
ADC output 2
A veraging two points (ideal)
-. Averaging two points (nonideaJ)

DNL of 0.5
(c)
rter whose output is being (a) Averaging two points (nonideal)
uation simplifying to Eq. offset of 0.5
by 3 dB or the effective (b)
Tease in resolution due to
Figure 5.32 Linearity requirements when averaging.
K
(5.59) blaek dot} is shifted downwards by 0.5 LSBs and so the averaged point shows a 0.25 LSB
offset from its ideal position. While we used a single LSB difference to show averaging,
rter changes the effective we could use any number of LSBs to show that the ADC accuracy must be equal to or
resolution is based on the better than the desired final digital filter output accuracy.
bandlimited, and the data
ion, N, + improvement in The number of bits in the ADC (its resolution) N, and the number of bits
improvement in resolution after filtering, N/ne ' are used with the final, total number of bits
(the number of bits eoming out ofthe digital filter) to give
N Final = N + N fnc (5.60)
= 6.02(N+Nfnc ) + 1.76 The ADC output should ideally ehange in increments of the exact LSB voltage. In reality,
the changes will be different from the ideal output levels (as just diseussed). In order to
aehieve an increase in the number of final bits, the output of the ADC must be aceurate
(its aetuallevels must be spaced from the ideal levels) to within
+ V Rli"F+ VREF- 1
± (0.5 LSB) . - N (5.61 )
~ 2NFi"ul+ 1 2 J~
where no averaging (NIne 0 and K = 1) means the ADC is at least 0.5 LSBs accurate.
~ This is a significant limitation when using averaging to increase the resolution of an
mber of points averaged
ADC. This is especially true when a resolution greater than 10 bits is desired with INL
and DNL less than ±0.5 LSBs. In the next seetion, and in the next chapter, we will look at
er resolution. feedbaek topologies that may relax the accuracy requirements plaeed on the ADC and
allow averaging to more effeetively remove quantization noise.
5.3.3 Adding a Noise Dither
.2. In part (a) we show the
ltputs spaced by one LSB Our assumption, when diseussing the benefits of averaging or calculating the spectral
.) are located on the ideal density of the quantization noise, falls apart for DC or slow-moving signals (the ADC
lese levels (and hence our input is not "busy"). In order to help with this problem consider adding a noise signal to
1 where the ADC outputs the ADC input that has a frequency content that falls within the range
Following this offset, the
ltput of the ADC (the top is < f
2K~ 2
(5.62)
so that it can be filtered out with the averaging filter (see Fig, 4.10). This noise is often amplitude be greater th:
called dither (a state of indecision or agitation) because it helps to randomize the spectral allowable range of input
content of the quantization noise, making it white. from dithering since the,
Fignre 5.33 shows the basic idea. In part (a) a DC signal is applied to the ADC Before we discus
that falls halfWay between two ADC transition codes spaced apart by 1 LSB. The output (a Gaussian PDF) for thl
code of the ADC remains unchanged with time. In part (b) a noise signal is added to the and DC input shown in I
DC input which has two benefits: (I) the quantization noise (the difference between the long time, we get the av
input signal and the reconstructed ADC output code) changes with time, and (2) the would also mean that we
output of the ADC has some variation which makes it "possible to determine the DC average enough ADC ou
voltage after averaging, generally a good idea to
Finally, it's important th
dither signal must averag
ADC Output code N offset (the known DC ofj
in the data convcrter's (ae
co
til DC Input signal
....J
ADC Output code N-l
RMS dither cr 0.5

(a)
Figure 5.33 (a) DC input signal and (b) DC input signal with dither added.
We can add the noise signal to our desired input signal with a circuit similar to
that shown in Fig. 5.34. Simple resistors add and reduce the noise signal applied to the
ADC input. The noise signal source is, most easily, derived from some sort of
asynchronous logic circuit and has a peak amplitude (before reduction) of VDD I V in
this book). In this figure note that we have indicated that the dither signal amplitude
Figure 5.35 Input to
should be approximately 0.5 LSB RMS (remembering the signal is, ideally, random and
band limited as specified by Eq. [5.62]). This number, 0.5 LSB RMS, is subjective, and no
exact rules as to its selection can be given othcr than the desirc that the peak-to-peak An example of ar
Thc outputs of the rows
and fight against each ot
Input with dither Input with dither
~
Input
,.~ Y I:"l ADC
Input 50
-~-r~----L ADC
I I
~~
r Dlth;l
It,ooo
Approximately 0.5 LSB RMS dither
--~
Dither
I nois;' I 0 toiY generating
I s.'ource i Id!git~l
-- l:lrcUit
Block diagram
Circuit implementation
Figure 5.34 Adding dither to an ADC input signal.

Figure:
1ixed-Signal Circuit Design Chapter 5 Data Converter SNR 197
~. 4.10). This noise is often amplitude be greater than I LSB. One disadvantage of adding the dither is that the
)s to randomize the spectral allowable range of input signals shrinks. A DC signal at VDD - 1 LSB will not benefit
from dithering since the ADC will be at its full-scale output.
gnal is applied to the ADC Before we discuss the implementation of a dither source, consider one possibility
apart by I LSB. The output (a Gaussian PDF) for the desired probability density function (PDF) of the dither signal
noise signal is added to the and DC input shown in Fig. 5.35 (the input to the ADC). [fwe average this signal over a
(the difference between the long time, we get the average or DC input signal since the dither averages to zero. This
ges with time, and (2) the would also mean that we can have some dither spectral content below f/2K as long as we
sible to determine the DC average enough ADC output samples to make its contribution to the SNDR small. It is
generally a good idea to use Eq. (5.62) as a gnide for allowable dither spectral content.
Finally, it's important that any dither signal we generate has a symmetrical PDF (the
dither signal must average to VDDI2 before amplitude reduction). If not, an unknown DC
offset (the known DC offset is the VDD/2 attenuated by the resistive divider in Fig. 5.34)
I~
in the data converter's (actually the filter's) output will result.
p(t)
time
)0 RMS dither = (J = 0.5 LSB
pCt) ~ .exp [
a,,2n:
with dither added.

Amplitude variation
,\lith time
tal with a circuit similar to Volts
noise signal applied to the
rived from some sort of
DC in, V in
:duction) of VDD I V in
he dither signal amplitude
~al is, ideally, random and
Figure 5.35 Input to the ADC, dither and DC, with a Gaussian probability distribution.
RMS, is subjective, and no
esire that the peak-to-peak An example of an implementation of a dither noise source is shown in Fig. 5.36.
The outputs of the rows of inverters, which are tied together, will occur asynchronously
and fight against each other causing the amplitude of the dither signal to occupy levels
Input with dither
Dither
out
5,000
Dither
Ot IV generating
digital
circuit
Circuit implementation
;igna1.
}'igure 5.36 One possible implementation of a dither circuit.
other than the nonnal logic levels of VDD and ground for significant amounts of time.
IH(f) I
The dither signal can be made more random by adding more rows of inverters. The A
challenge to this design is setting the number of inverters used in each row so that the
spectral content falls within the desired range (which may require a large number of
inverters) and keeping the output of the dither circuit uncorrelated with the sampling
clock. Other techniques for generating random noise, such as using linear serial feedback
registers, can be found in most books covering communication systems.
5.3.4 Jitter
/n =/s
We can apply the averaging discussion just developed directly to the jitter discussion
(a)
presented earlier in the chapter and answer the question, "How does averaging effect the
sampling amplitude error power (resulting fromjitter) in a data conversion system?" Ifwe
Figure 5.37 (a) AAF requiI
assume that the jitter has a Gaussian PDF, then the average power in the sampling error
r
amplitude, from Ex. 5.13, is
significance of this will be
P AVG,jiller '" [ cr· tz . 2TC/in (5.63)

our averaging filter's resp'
course, the penalty for the
for a fixed sampling freque
where cr is the standard deviation of the jitter (see Fig. 5.2 J). It may be helpful to rewrite
Eq. (5.57) in tenns of the quantization error power as 5.4 Using Feedback
2 1 visB By averaging the outputs
PQe,AVG = (VQe.RMS) = K'12 (5.64)
effective data converter re
doubling in (octave increas
and apply the same derivation to Eq. (5.63) to give
0.5-bit increase in effectiv
1 [vp
requires averaging 4,096
P AVGJiller = K' cr· ,fi ·2rif;n
J2 (5.65) sampling clock frequency,.
1n this section we I
This equation shows that the sampling error amplitude power, PAVG,jiller' introduced into
converters (ADCs and DJ
the data converter's output spectrum decreases with averaging. Averaging two samples
(lower the amount of avera
causes the sampling error amplitude power to decrease by 3 dB. This effectively reduces
certain bandwidth). A to
the jitter requirements placed on the sampling clock. While this may not appear to be very
analog-to-digital conversi
significant at first glance, consider what happens if, for example, 256 samples are
conversion). The complete
averaged (K 256). The sampling error power decreases by 24 dB, making clock jitter,
ADC) would be made up
when using a reasonably stable oscillator, almost not an issue. Also note that a doubling
digital-to-analog interface
in the jitter's standard deviation, cr, results in a 6 dB increase in sampling error amplitude
interpolating filter and a
power.
modulator will contain a Ie
5.3.5 Anti-Aliasing Filter with the decimating filter,
The use of averaging will also lead to relaxed requirements of the anti-aliasing filter The basic lopolog
(AAF). Figure 5.37a shows the requirements placed on the AAF without averaging. As Depending on the cireuit
we saw in Ch. 2, ideally, the transition from the 3 dB frequency to the "stop frequency" or separated into two categon
Nyquist frequency should be infinitely sharp (the filter should abruptly change from a
Predictive modulat
gain of unity to a gain of zero [something small]). When using averaging, Fig. 5.37b, we
to feed back an analog si
have to limit our desired input signal bandwidth to B. The rolloff of the filter in part (b)
output of the summer to
of the figure can be much more gradual and in many cases a simple, single pole, RC filter
possibly, the quantization
is all that's needed for an AAF. Also, our averaging filter will attenuate the ADC output
output the change in the j
spectrum, as seen in Fig. 1.17, and help to remove input signal power above f/2K. The
being delta-sigma-modula
lixed-Signal Circuit Design Chapter 5 Data Converter SNR 199
gnificant amounts of time.

)re rows of inverters. The IH(f) I IH(f) I
ed in each row so that the
B =fsI(2K)
require a large number of ,/
rrelated with the sampling
using linear serial feedback
systems.
In =fsl2 f In =fsl2 f
;tly to the jitter discussion
N does averaging effect the
(a) (b)
L conversion system?" Ifwe
,ower in the sampling error Figure 5.37 (a) AAF requirements without averaging, and (b) AAF requirements with averaging.
significance of this will be easier to see as the number of points averaged increases and
our averaging filter's response gets sharper with more attenuation (see Fig. 4.10). Of
(5.63) course, the penalty for the relaxed requirements of the AAF is reduced signal bandwidth
for a fixed sampling frequency.
It may be helpful to rewrite
5.4 Using Feedback to Improve SNR
(5.64) By averaging the outputs of an ADC, or interpolating between inputs of a DAC, the
effective data converter resolution can be increased. As specified by Eq. (5.58), every
doubling in (octave increase in) K (where K is the number of points averaged) results in a
0.5-bit increase in effective resolution. An effective ADC resolution increase of 6-bits
requires averaging 4,096 samples. If a 1 MHz signal bandwidth is of interest, our
(5.65)
sampling clock frequencY,h, will have to be 8.192 GHz!
:r, introduced into

PAVG./iller'
In this section we briefly introduce the idea that feedback can be used with data
19. Averaging two samples converters (ADCs and DACs) to improve overall data conversion system performance
.B. This effectively reduces (lower the amount of averaging or oversampling needed to attain a given resolution over a
s may not appear to be very certain bandwidth). A topology of this nature is called a modulator or coder (for
:xample, 256 samples are analog-to-digital conversion) or a demodulator or decoder (for digital-to-analog
24 dB, making clock jitter, conversion). The complete analog-to-digital interface (a circuit block that functions as an
. Also note that a doubling ADC) would be made up of a modulator and a lowpass (decimating) filter, while the
n sampling error amplitude digital-to-analog interface (a circuit block that functions as a DAC) would consist of an
interpolating filter and a demodulator. This can be confusing since, for example, a
modulator will contain a low-resolution ADC in a feedback configuration which, together
with the decimating filter, behaves like a high-resolution ADC.
s of the anti-aliasing filter The basic topology of a feedback modulator or coder is shown in Fig. 5.38.
~AF without averaging. As Depending on the circuit blocks used for A( I) and B( I) feedback modulators can be
y to the "stop frequency" or separated into two categories: predictive modulators and noise-shaping modulators.
Id abruptly change from a
g averaging, Fig. 5.37b, we Predictive modulators (a.k.a. predictive coders), such as delta-modulation, attempt
lloff of the filter in part (b) to feed back an analog signal with the same value as the input signal. This drives the
mple, single pole, RC filter .. output of the summer to zero, reducing the required input range of the ADC and,
I attenuate the ADC output possibly, the quantization error introduced by the ADC. Predictive modulators effectively
lal power above 1/2K. The output the change in the input signal over time. Noise-shaping modulators, an example
being delta-sigma-modulation, also known as sigma-delta-modulation, on the other hand,
------------
.J
Vout(f) Out
(to digital
filtering.)
In Vin(f)
Figure 5.38 Block diagram of a feedback modulator.
feed back, and output, the average value of the input signal. This signal can be filtered
(averaged) to reduce the accuracy required of the analog circuit components. Fi~
Noise-shaping modulators effectively output the average of the input signal over time. In
a noise-shaping data converter the averaging and decimating filter, as discussed earlier, is
connected to the output of the modulator. Because of the averaging used in noise-shaping In a noise-shapir
modulators, the analog components, in the forward path of Fig. 5.38, require less signal bandwidth so that
accuracy. However, the DAC's output, in the feedback path (which is subtracted from the on the other hand, will f
input), doesn't experience the averaging so, once again, the DAC must be linear to the signal spectrum passe:
final desired resolution of the data converter. DAC linearity concerns have led to the use quantization noise spect
of a single-bit DAC (an inverter), in many noise-shaping data converter applications. The filter or analog compon
one-bit DAC is inherently linear. (Two output points determine a line!) Because of the DAC in the feedback pa
relaxed requirements placed on the analog circuit components, we will concentrate the an integrator, the quant
next chapters, in detail, on noise-shaping topologies for both ADCs and DACs. Notice removed with the avera
that both predictive and noise-shaping modulators utilize oversampling. modulator does not redt
pushes the noise to frequ
In order to understand these statements in more detail, let's use the additive
quantization noise model for the ADC developed in this chapter, Fig. 5.2. Figure 5.39 ADDITIONAL READ]
shows Fig. 5.38 redrawn using this model where the quantization noise is represented in [1] R. J. van de Plas
the frequency domain by VQeCf). We can relate the inputs (the wanted input signal and Converters, SpriI
the unwanted quantization noise) to the output of the feedback modulator by
Signal transfer function, STF(f)
[2] Engineering Sta
Noise transfer function, NTF(f)
~ Devices), Newne
A(f)
(5.66) [3] M. Gustavsson,
I + A (f) . B(f) 1 +A(f)· B(f)
Communications
In a predictive modulator the feedback filter, B( f), has a large gain so that, ideally, the
[4] S. R. Norswortl
fed back signal equals the input signal. If A(f) = 1 (a wire), then both the STF (signal
Converters: The
transfer function) and the NTF (noise transfer function) have a value of, approximately,
978-0780310452
IIB( f). Recovering the input signal requires passing the output of the predictive
modulator through an analog filter with a transfer function of precisely B(f) (noting that [5] J. C. Candy and t
B[f] is a digital filter in the modulator of Fig. 5.39). The required precision of the analog Wiley-IEEE Pres
filter (the matching between the filter in the modulator and the filter in the demodulator)
[6] S. K. TewksbUl
limits the attainable resolution when using predictive modulators. Notice that both the
Noise-Shaping (
input signal and the quantization noise experience the same spectral shaping (spectral
CAS-25, pp. 436
discrimination is absent in a predictive modulator). Also note that the name "predictive"
comes from the modulator attempting to predict the input signal in order to drive the [7] W. R. Bennett, ,
output of the summer to zero. If the prediction is perfect, the signal that is fed back Vol. 27, pp. 446
exactly matches the input signal.
: Mixed-Signal Circuit Design Chapter 5 Data Converter SNR 201
Voul(f) Out
(to digital
filtering.)
Vout(f) Out
Analog
modulator.
al. This signal can be filtered

analog circuit components. Figure 5.39 Block diagram of a feedback modulator .
. the input signal over time. In
g filter, as discussed earlier, is
eraging used in noise-shaping In a noise-shaping modulator the gain of the forward path, A( f), is large in the
h of Fig. 5.38, require less signal bandwidth so that the STF is approximately unity (assuming B[f] I). The NTF,
(which is subtracted from the on the other hand, will approach zero, ideally, in the bandwidth of interest. Note that the
,e DAC must be linear to the signal spectrum passes through the modulator essentially unchanged, while the
{ concerns have led to the use quantization noise spectrum is shaped (and thus the name noise-shaping). No precision
.ta converter applications. The filter or analog components are required, as discussed earlier, except, perhaps, for the
rmine a line!) Because of the DAC in the feedback path of the modulator. We'll see in the next chapter that if A( /) is
lents, we will concentrate the an integrator, the quantization noise is pushed to higher frequencies so that it can be
'oth ADCs and DACs. Notice removed with the averaging filter. This is a very important concept, as a noise-shaping
ersampling. modulator does not reduce the quantization noise to attain higher resolutions, but rather
pushes the noise to frequencies outside of the signal bandwidth of interest.
detail, let's use the additive
~hapter, Fig. 5.2. Figure 5.39 ADDITIONAL READING
ization noise is represented in [1] R. 1. van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog
(the wanted input signal and Converters, Springer, 2007. ISBN 978-1402075001
ck modulator by
lerion, NTF(f)
[2] Engineering Staff Analog Devices Inc., Data Conversion Handbook (Analog
Devices), Newnes, 2005. ISBN 978-0750678414
,VQe(f) (5.66) . [3] M. Gustavsson, J. J. Wikner, and N. Tan, CMOS Data Converters for
·B(/)
Communications, Springer, 2000. ISBN 978-079237780 I
large gain so that, ideally, the
~e), then both the STF (signal [4] S. R. Norsworthy, R. Schreier, and G. C. Temes (eds.), Delta-Sigma Data
ve a value of, approximately, Converters: Theory, Design. and Simulation, Wiley-IEEE Press, 1997. ISBN
the output of the predictive 978-0780310452
of precisely B(f) (noting that [5] J. C. Candy and G. C. Temes (eds.), Oversampling Delta-Sigma Data Converters,
quired precision of the analog' Wiley-IEEE Press, 1992. ISBN 978-0879422851
the filter in the demodulator)
lulators. Notice that both the [6] S. K. Tewksbury and R. W. Hallock, Oversampled, Linear Predictive and
ne spectral shaping (spectral Noise-Shaping Coders of Order N>I, IEEE Trans. Circuits and Sys., Vol.
He that the name "predictive" CAS-25, pp. 436-447, July 1978.
t signal in order to drive the [7] W. R. Bennett, "Spectra of Quantized Signals," Bell System Technical Journal,
t, the signal that is fed back Vol. 27, pp. 446-472, July 1948.
""j
QUESTIONS
5.1 Develop an expression for the effective number of bits in terms of the measured
signal-to-noise ratio if the input sinewave has a peak amplitude of SO% of (VREF+
VREFJ·
5.2 When using Eq. (S.14) what is the assumed ADC input signal? Put your answer in
terms of the ADC reference voltages.
5.3 Describe, in your own words, the difference between specifying SNR and SNDR.
5.4 Using SPICE simulations with an ideal ADC and DAC, show how coherent
sampling can result in an RMS value of quantization noise larger than what is Data Con
specified by Eq. (S.3). Comment on the shape of the quantization noise's
spectrum.
5.5 Suppose a perfectly stable clock is available (AT., is zero in Eq. [S.2l D. Would we
still have a finite aperture window if the clock has a finite rise time? Describe why
or why not?
Mixed-signal design is pc
5.6 How do the number of bits lost because of aperture jitter change with the with analog circuit design.
frequency of an ADC input sinewave? If the ADC input is a DC signal, is aperture precision of the analog eire
jitter a concern? Why? is "Analog Design without
5.7 Why must Bennett's criteria be valid for the averaging filter in Fig. S.29 to reduce In the past five ch,
the quantization noise in the digital output signal? Give an example input signal mixed-signal circuits. For
where averaging will not reduce quantization noise. converter (ADC) using mi:
5.8 Assuming Eq. (S.S7) is valid, rederive Eq. (S.13) including the effects of through an anti-aliasing 1
averaging K ADC output samples. Is Eq. (S.13) or the equation derived here valid shaping modulator, as dis
name for an ADC with 1 tc
for a slow or DC input signal? Comment on why or why not.
feedback loop to get a ru
5.9 If Bennett's criteria are valid, does averaging ADC outputs (or DAC inputs) put output is extracted using
any restrictions on the bandwidth of the input signal? Why? Give an example. decimated. In simple wor
representation of the analo
5.10 How accurate does an 8-bit ADC have to be in order to use a digital filter to
various DC input signals.
average 16 output samples for a final output resolution of lO-bits (see Eq. (S.59])?
Assume the ideal LSB of the 8-bit converter is 10 mY. Your answer should be Note that this type
given in both m V and % of the full-scale. sampling frequency, f" mt
also see that these types 0
5.11 Show the detailed derivation ofEq. (S.66).
on the topology used, dell
5.12 Summarize, and compare, the advantages and disadvantages of predictive and greater detail later).
noise-shaping data converters.
Analog input Ikl\F ~

!......--J
Clock input
Figure
fixed-Signal Circuit Design
s in terms of the measured Chapter

nplitude of 50% of (VREF+ -
; signal? Put your answer in

6
Jecifying SNR and SNDR.
DAC, show how coherent
ilnoise larger than what is
If the quantization noise's
Data Converter Design Basics
TO in Eq. [5.21)). Would we
lite rise time? Describe why
Mixed-signal design is powerful because it combines digital-signal processing (DSP)

me jitter change with the with analog circuit design. Using DSP, as we'll show in this chapter, reduces the required
LIt is a DC signal, is aperture precision of the analog circuits. Perhaps a different, yet appropriate, name for this chapter
is "Analog Design without using Analog Components!"
; filter in Fig. 5.29 to reduce· In the past five chapters, we covered topics we'll frequently use in the design of
ive an example input signal mixed-signal circuits. For example, Fig. 6.1 shows how we'll design an analog-to-digital
converter (ADC) using mixed-signal circuit design techniques. Our analog input is passed
) including the effects of through an anti-aliasing filter (AAF) to a noise-shaping (NS) modulator. The noise
equation derived here valid shaping modulator, as discussed in Sec. 5.4, uses a low-resolution quantizer (a fancy
hy not. name for an ADC with 1 to a few bits resolution, like the comparator seen in Fig. 5.1) in a
feedback loop to get a running average of the analog input signal. The desired digital
,utputs (or DAC inputs) put· output is extracted using a moving average filter, the lowpass filters in Sec. 4.2, and
Why? Give an example. decimated. In simple words, the modulator's digital output signal is averaged to get a
ler to use a digital filter to representation of the analog input signaL Figure 6.2 shows example modulator outputs for
\ of lO-bits (see Eq. [5.59))? various DC input signals.
).V. Your answer should be Note that this type of data converter is often called an oversampled ADC since the
sampling frequency,fs, must be much larger than the input frequencies of interest. We'll
also see that these types of data converters are called noise-shaping ADCs or, depending
on the topology used, delta-sigma (or sigma-delta) ADCs (these names are discussed in
[vantages of predictive and greater detail later).
I-bit
Analog input I~
-----J AM
L-..J
H ~NS d~l ~
NS modulator r
.
Digital
Filter
l Digital Output
f.!........_. _'r=~
Clock input "Decimation filter
Figure 6.1 An ADC using a NS modulator and digital filter.

204 CMOS Mixed-Signal Circuit Design Chapter 6 Data Conver
A VREF+ VI
!
1.0
Average = I~O 0.25
0
1.0
[ 0
nJ1JlJL Average = = 0.5 VREF- 0
::i 1.0 A one-bit DAC
0 (31)·(10)
.... (Repeats every 32) Average
2
ro
oi 32
;; Figure 6.3 Thh
ot UUU~ U~ ~~u_U~n _~U_ ~ _U

-0 (7)-(1.0)
0 10 Average
::E ~- 8
6.1 Passive Nois
1.0 . --
~ ~ .. Average = 180
~
.~ ....
~
~ ~
Figure 6.4 shows a sd
~I
. . ..
..
Average =0 V Fig. 5.38, we see that t

) write the output of the:
8 16 24 32 40
Figure 6.2 Modulator outputs and their corresponding DC averages.

noting that we are aSSl
The One-Bit ADC and DAC block is
In this chapter we'll use, exclusively, a one-bit ADC and DAC. To understand why, let's
review Fig. 5.28 and 5.32. In all cases, unless the spacing of the codes is perfect in these
data converters, averaging the codes will result in non-linearity. However, by using an so,
ADC or DAC with only two output codes in our NS modulator we are guaranteed
linearity (two points determine a line!). If one of the reference voltages in the ADC or
DAC is offset from its ideal value then we'll get a gain error but no nonlinearity error. and therefore
In Chs. 4 and 5 we treated the clocked comparator as a I-bit quantizer (ADC) with
an LSB given by
I LSB VREF+ VREF- = VLSE (6.1) This is nearly the tran!
this response as integr
as an added noise source, Fig. 5.2. The PSD of the added noise, see Eq. (5.5), is moment. Using Eq. (5.
2
VQe(f) == 12/
vISE (6.2)
s
In this chapter we'll set VREF+ = VDD I V and VREF- == 0 V so that VDDI2 or 500
mV. We can think of the output of the comparator (the output of the NS modulator) as a Notice that the AAF i
binary offset number with a value of 1 or O. After a simple conversion to two's
function appears to be
complement numbers, the output can be changed to +1 (01) or -I (II). Since our input average the modulator
signals are referenced, or swing around, VCM it's useful to think in terms of two's zone issues for a passi
complement numbers. For example, in Fig. 6.2, if we apply 500 mV to the input of our to get a better represen
NS modulator we get 1010101... (second sketch) or an average of 500 mV (= VCM). Since
all signals are referenced to VCM it may be more useful to say that we aren't applying a
signal (meaning just the common-mode voltage is present at the input) and thus we get a
Next, let's write
sequence of + 1, -J , + I, -1, etc. that averages to zero (Vcu)' Figure 6.3 shows how we
think about this in more detail. If we pass a signal through an inverter we are multiplying
it by -1 when we think in terms of two's complement numbers.
ixed-SignaJ Circuit Design Chapter 6 Data Converter Design Basics 205
Binary offset Two's complement

,.-'-.. ,.-'-..
VREF+ VDD - - - - - ~ 01 or+ 1

Two's complement
Average = 14° = 0.25 ,.-'-..
······-······OOorO
fill Average = 12° = 0.5

VREF- 0 ----- 0
Binary offset
,.-'-..
~
Two's complement
,.-'-..
II or-I
Average '= (31)·(1.0)
A one-bit DAC
~ 32
Figure 6.3 Thinking about the inverter in terms of the common-mode voltage.
Averaoe = (7)·(1.0)
e 8
6.1 Passive Noise-Shaping
Averaoe =.!Jl.
'" 8 Figure 6.4 shows a schematic and block diagram of a passive NS modulator. Reviewing
Average =0 V 5.38, we see that this is a modulator topology with 8U) = I. To calculate AU) let's
I > write the output of the summing block (the resistors), or the input to the A(f) block, as
40
Vi" - Vint -Voul - Vinl '
R + R =I~ (6.3)
: DC averages.
noting that we are assuming all voltages are referenced to VCM' The output of the A(f)
block is
:. To understand why, let's (6.4)

le codes is perfect in these
ty. However, by using an so,
ulator we are guaranteed
e voltages in the ADC or Vin - Vout Vtnl' UmCR + 2) (6.5)
no nonlinearity error. and therefore
-bit quantizer (A DC) with
A(f) (6.6)
2 +jroRC
(6.1) This is nearly the transfer function of an RC circuit, see Eq, (3.1). We can also think of
this response as integrating for frequencies above 1I21tRC. We'll come back to this in a
see Eq. (5.5), is
moment. Using Eq. (5.66) we can write
(6.2) STF(f)
,
I 2
VoutU) = 3 . RC 'Vin(f) + . 3 +Jm
. RC .VQe(f) (6.7)
) that VDDI2 or 500 +Jm
of the NS modulator) as a
Notice that the AAF is built-in to this topology via the STF. At DC the noise transfer
rlple conversion to two's
function appears to be 2/3. However, we know that at DC, as seen in Fig. 6.2, we can
r -1 (11). Since our input
average the modulator's outputs and recover, exactly, the analog input signal (see dead
think in terms of two's
zone issues for a passive modulator on page 215). This means that VQe(O) ~ O. Let's try
)0 m V to the input of our
to get a better representation for the output of the modulator. In order to begin notice that
of 500 m V (== VCM)' Since
that we aren't applying a (6.8)
e input) and thus we get a
Next, let's write
:;'igure 6.3 shows how we
Iverter we are mUltiplying (Vin-Vint + -VOUl-Villl). + V (f) (6.9)
\ R R jmC Qe Vout
Vin - Vim
Digital
Analog >-----.r--- Vout
DAC Is
-Vaul
F
(a) Circuit implementation of a passive NS modulator
Example 6.1
VQeCf) Simulate the operatior
10 pF, and the c10cl
simulation results and
Vin l---,--VOUI
Figure 6.6 shows the
circuit. Notice that as
stays low more often.
or a logic 1, more oft
~_-_V;;.;.OU,,-I--1- 1 code into an N-bit we
used to get our origina
(b) Block diagram model of a passive NS modulator. The STF starts tc

continue to operate at
We'll see that for prot:
Figure 6.4 A passive-integrator NS modulator. Here we are using an
changes with time for
term adds distortion aJ
and
small because of the I
Vio Voul - 2Vinl + VQe ·jwRC == jwRC· VoUl (6.10) small since the feedl
What's of concern is t1
Vin - 2V;nl + VQe )wRC == Voul • (1 +jwRC) (6.11 )
so finally
STF(f) NTF(f) l.W-,--
r---"-----.
1.nv~
jwRC V -2· Viol
Vow = 1 + jwRC 'Vin + 1 + jwRC . Qe + (6.12) OgVr~"
1 +jwRC
~~
Extf'd noisc/distortion :·~i·:::I~::·

O.6V-··· .. .
The key things to note are: I) that if we can keep ViOl from varying we eliminate this extra o.svl. i .. .
distortion term (this is why we use an active integrator in later chapters), 2) the signal
o·~t·t·
:~ll
sees a lowpass response (so we have, as already mentioned, a built-in AAF that limits
input spectral content), and 3) the noise is shaped towards the higher frequencies (the
noise is high passed filtered). If our quantization noise is flat, as seen in Fig. 5.12, then
high-pass filtering the noise gives the PSD seen in Fig. 6.5. Quantization noise that has
o.ovl .....
-n.w+--
n.o~.
been shaped in this way is called modulation noise. Note that the faster we clock the
comparator (the larger I) the less variation we'll get in Vim' Also note, again, that the
(digital) output of the modulator is the average of the (analog) input signal. Figure 6.6 Simulat
vExed-Signal Circuit Design Chapter 6 Data Converter Design Basics 207
In =fsl2 I
Figure 6.5 Modulation noise spectral density.
fS modulator
Example 6.1
f) Simulate the operation of the NS modulator seen in Fig. 6.4 when R is 10k, C is
10 pF, and the clocking frequency is 100 MHz. Comment on the resulting
simulation results and the operation/limitations ofthe circuit.
Figure 6.6 shows the input (a sinewave at 500 kHz) and (digital) output of the
circuit. Notice that as the input signal moves towards ground the output signal
stays low more often. As the input signal moves towards VDD the output is high,
or a logic I, more often. While we can use a digital filter to change this one-bit
code into an N-bit word (and we will!) let's show that a simple RC filter can be
used to get our original signal back from the digital data, Fig. 6.7.
::>dulator. The STF starts to roll-off at 1I2nRC or 1.59 MHz. While the circuit will
continue to operate at higher frequencies the SNR of the data converter will suffer.
We'll see that for proper operation the comparator's gain becomes very important.
L1lator.
Here we are using an ideal comparator. Finally, it's interesting to look at how Vint
changes with time for various inputs. Remember, as seen in Eq. (6.12), that this
term adds distortion and noise to our input signal. At high-frequencies this term is
small because of the pole at 1/2nRC and at low frequencies the contributions are
iroRC,vout (6.1 0) small since the feedback loop responds faster than the input signal changes.
What's of concern is the moderate frequencies and how the SNR is degraded .•
1+jroRC) (6.11)
-2· Vim
!e + 1 +jroRC
(6.12)
Extra noise/distortion
rying we eliminate this extra

later chapters), 2) the signal
I, a built-in AAF that limits
the higher frequencies (the
1t, as seen in Fig. 5.12, then
Quantization noise that has
that the faster we clock the
,. Also note, again, that the
) input signal. Figure 6.6 Simulating the operation of the passive NS modulator seen in Fig. 6.4.
208 CMOS Mixed-Signal Circuit Design Chapter 6 Data Converter I
We spent a great ,
decimation. Let's use these
modulator. Let's set the bar
noting that we assumed,

response. We can reduce t
through additional lowpas~
with peaking to account
substitution gives
Figure 6.7 Using an RC circuit to filter the digital output in Fig. 6.6.
The value of RC must be rr
clock, T" to keep v int from
6.1.1 Signal-to-Noise Ratio
Eqs. (5.10) to (5.13) we get
Let's calculate the SNR for the first-order noise-shaping modulator seen in Fig. 6.4 and
characterized by Eq. (6.12). In the following we'll ignore the extra noise/distortion SNRidea/ 20·log
resulting from variations in Vim' Further note that the pole associated with both the STF v
and NTF won't affect the SNR since it's common to both. We know the output of the
modulator is passed through a lowpass filter with a bandwidth B to remove the
modulation noise, Fig. 6.8. The smaller B the lower the noise in the final digital output If we set RC 4.4(1; = 4.47
word and the larger the SNR. Again, the trade-off with using smaller lowpass filter
bandwidth is that the frequency range of the allowable input signals shrinks. Let's SNRideal = 21
calculate the RMS noise in the filter's output using
B 2 B For K 4 this equation i~
V;Oise,RMS = 2 f INTF(f)l21 V Qe(f)12 . df = 2· ~~~ f
. (2nj- RC)2 . df (6.13) beyond 4 we get an increa:
o 1s 0 dB
or
2 ViSB 2 B3
Vnoise.RMS = 2· 12fs . (2nRC) . 3 (6.14)
again noting that using a smaller digitallowpass filter bandwidth, B, reduces the noise. Figure 6.9 compares the fil
Eq. (5.58). It's important
oversampling feedback mo·
be busy).
6.1.2 Decimating and Fi
It's important to note that I
was passed through a perf
output through a Sine aver<
the higher frequency noise·
want to answer two questi(
should be used in the digit:
Figure 6.8 Filtering out modulation noise to calculate SNR. we use only this filter (no:
NS modulator be affected?
xed-Signal Circuit Design Chapter 6 Data Converter Design Basics
We spent a great deal of time in Ch. 4 using Sinc-shaped lowpass filters for
decimation. Let's use these filters here for filtering and decimating the output of the NS
modulator. Let's set the bandwidth of the filter, see Fig. 4.17, to
B j, (6.15)
2K
noting that we assumed, when deriving Eq. (6.14), a brickwall-shaped lowpass filter
response. We can reduce the noise further, after decimation, by passing the digital data
through additional lowpass filtering (perhaps using the biquad filters discussed in Ch. 4
with peaking to account for the droop introduced with the Sinc filter). Making the
substitution gives
1.4ps
V;oise,RMS = 12 (6.16)
Jut in Fig. 6.6.
The value of RC must be much longer (at least five times) than the period ofthe sampling
clock, Ts, to keep Vim from varying too much. Following the procedures used to derive
Eqs. (5.10) to (5.13) we get
llator seen in Fig. 6.4 and
the extra noise/distortion SNRideal = 20 . log 6.02N + 1.76 20 --::::::~ + 20 logK3/2
Dciated with both the STF Vnoise.RMS
Te know the output of the
dwidth B to remove the (6.17)
in the final digital output Ifwe set RC 4.4if, 4.4T, then we can write
ing smaller lowpass filter
put signals shrinks. Let's Vp / ,fi
SNRideal = 20 . log . 6.02N + 1.76 - 18.06 + 30 10gK (6.18)
Vnoise,RMS
2
For K = 4 this equation is the same as Eq. (5.13). However, for every doubling of K
Y·RC) ·df (6.13) beyond 4 we get an increase in resolution, Nine' of 1.5 bits or an increase in SNRideai of 9
dB
18.06
(6.19)
(6.14)
SNRideal 6.02(N + Nine) + 1.76 (6.20)
:h, B, reduces the noise. Fignre 6.9 compares the first-order NS modulator to simple oversampling, Fig. 5.31 and
Eq. (5.58). It's important to note that Bennett's criteria need not be valid using the
oversampling feedback modulator discussed in this section (e.g. the input doesn't have to
be busy).
Filter removes 6.1.2 Decimating and Filtering the Modulator's Output
_ _ this noise.
It's important to note that Eq. (6.17) was derived assuming the output of the modulator
was passed through a perfect lowpass filter with a bandwidth of B, fl2K. Passing the
) output through a Sinc averaging filter, see Fig. 4.14, will result in a poorer SNR because
'2 f the higher frequency noise components will not be entirely filtered out. In this section we
want to answer two questions: (1) what order, L (sec Eq. [4.19]), of Sine lowpass filter
should be used in the digital filter on the output of the NS modulator, and (2) assuming
late SNR.
we use only this filter (no additional filtering), how will the ideal SNR of the first-order
NS modulator be affected?
210 CMOS Mixed-Signal Circuit Design Chapter 6 Data Convel
the SNR (= 25.78 d

Improvement in resolution,Nlnc through each of th
(bits added) First-order noise shaping using a passive
~ modulator and neglecting the throw the LSB of 1
noise/distortion term in Eq, (6,12), of the filter is wh
5.00 filter's output (the
J 6 or I 0000. Whe
3.33 The output can swi
, Simple oversampling
1000 (8). By remo'
\.67 0000 (0) around 1
VREF+ (here fi'DD) tl
o - - I -____ -+---I--+----~.~
10 100 Ik K Number of points averaged Figure 6.11 she

500 kHz. Looking
Figure 6.9 Comparing first-{)fder noise-shaping to simple oversampling (Fig. 5,29), we should only se
looking at Fig. 6.1
We begin to answer the first question by noting that the increase in the number of We've, up to this r
bits, Nine' was specified by Eq. (6.19). If our NS modulator uses a I-bit ADC, then the In the next section
final, after the digital filter, resolution of the resulting data converter is Nine + 1 bits. (An offsets effect the pc
NS modulator using a 5-bit ADC [often called a multibit NS modulator] would ideally
have an output resolution of Nine + 5 bits.) Further, we saw in Ex. 4.3 and Fig. 4.14 that 960mV-r
the word size increased by 10gzK bits in each Sinc filter stage, For a cascade of L filters
we can require :::::j
120mv1
30 10gK - 18.06 640mvl
L . Iog2K~ 6.02 (6.21 )
56omV1
480mV-i
For K:S: 256 we only need one lowpass Sinc filter or L = 1.
400rnv~
Example 6.2
Sketch the implementation of a K 16 decimating filter for the NS modulator :::::-"1
16UmV
discussed in Ex. 6.1. Simulate the operation of the resulting ADC (modulator and BOrnV
filter). Estimate the SNR, number of final bits, and Nyquist frequency. 0.01
The decimating filter's transfer function is Figure 6.11 S

(6.22) SNR Calculation using
and seen in Fig. 6.10 (see Sec. 4.2.5). The filter's output clock rate is 100 MHzl16 Let's now consider he
or 6.25 MHz so the Nyquist frequency is half of this or 3.125 MHz. The increase effects the SNR of the I
in the number of bits is 3, using Eq. (6.19), so the final output word size, based on SNRidcal was calculat(
band limited to B. Fil
modulation noise) in a
shape of the averaging
dividing by K, see Eq.
range of1)2 (see Fig. :
We can calcula
order modulator and ar
Figure 6.10 Lowpass and decimating filter used in Ex. 6.2,

fixed-Signal Circuit Design Chapter 6 Data Converter Design Basics 211
the SNR (= 25.78 dB), is 4-bits. Our filter causes the word size to increase by I-bit
;e shaping using a passive through each of the 4 stages so that our final output word size is 5-bits. We can
ltor and neglecting the throw the LSB of this word out; however, notice that the largest word we get out
listortion term in Eq. (6.12). of the filter is when the filter's input remains a 1 at all times. In this case the
filter's output (the output of the ADC made using the NS modulator and filter) is
16 or 1 0000. When the filter's input is a 0 at all times our filter's output is 0 0000.
The output can swing from I 0000 to 0 0000 around the common-mode code of 0
rsampling
1000 (8). By removing the MSB we can make the output swing from 1111 (15) to
0000 (0) around 1000 (8). However if the NS modulator's input moves close to
VREF+ (here VDD) then the output of the filter can overflow.
-'»
~umber of points averaged Figure 6.11 shows the simulation results. The input frequency, as in Ex. 6.1, is
500 kHz. Looking at the frequency response of our filter, Eq. (4.20) and Fig. 4.17,
,rsarnpling (Fig. 5.29). we should only see a minor amount of attenuation through the filter. However,
looking at Fig. 6.11 we see more than a minor amount of output signal reduction.
le increase in the number of We've, up to this point, ignored the extra distortion/noise term seen in Fig. 6.12.
uses a I-bit ADC, then the In the next section we'll discuss this term in more detail and how matching and
mverter is Nine + 1 bits. (An offsets effect the performance of the modulator.•
S modulator] would ideally
1 Ex. 4.3 and 4.14 that 960mV..,--,..-"=---....,--'-'?--,---,--~=:!....,.---,
e. For a cascade of L filters 880mV

800mV ..
120mV
(6.21 ) MOmV
560mV
480mV
400mV
320mV
240mV
r for the NS modulator
160mV
Ig ADC (modulator and
t frequency.
80mV i I I-~--t--r----i--i---i---+----l
0.0115 0.7115 1.4115 2.1115 2.0ps 3.5115 4.2115 4.9ps 5.611' 6.3115
Figure 6.11 Simulating the ADC (modulator and filter) discussed in Ex. 6.2.
(6.22)
SNR Calculation using a Sine Filter
lock rate is 100 MHz/I 6 Let's now consider how filtering with a Sinc filter instead of the ideal lowpass filter
.125 MHz. The increase effects the SNR of the modulator/filter implementation of a data converter. Remember the
tput word size, based on SNRideal was calculated in Eq. (6.18) assuming the modulation noise was strictly
bandlimited to B. Figure 6.12 shows the PSD of the NTF2(f) and IVQe (f)12 (the
modulation noise) in a first-order passive NS modulator. Also shown in this figure is the
shape of the averaging filter's magnitude response squared that is normalized to unity by
dividing by K, see Eq. (4.20). Here we are showing the shape of a filter with K = 16 and a
range ofJJ2 (see Fig. 5.12).
We can calculate the RMS quantization noise resulting from a cascade of a first
order modulator and an averaging filter, L I, using
/,/2
in Ex. 6.2. V~e.RMS 2 JINTF(f)12 . IvQe(f)12 . IH(f)12 . df

o
(6.23)
V Ri
'~
\ V2
IVQe(f) I2 • INTF(f) I2 = l~f. (2nj- RC)2 .
Figure 6.;
+=T-~---~--~--~:··--~==~-=~--~~f
~~ ~n
Resistor Mismatch
B = {~ , Ideal maximum input frequency
In order to detennine the ef
Figure 6.12 Showing modulation noise and filter response. neglecting the effects of the
or
Rr (Vin vinr)-Ri'
(6.24)
RrVin Vint·(Ri+J
For the frequency range of interestf«fs so sinx "" x and we get

You! = 1 +jeo
2
VQe.RMS = 2·
2
VLSB
12~
2
. (21s . RC) . K 2 ' I
I ·(,/2 . 2 ( f )
Sill Kn1s . df (6.25) The effect of mismatchec
distortion). Note that the <
Let's let 6 = n . f, so precision operation.
-,
-" The Feedback DAC
,
r-·~---..
2 The feedback DAC is th

fsin K6· d6
o
2
(6.26) operation. Consider the w,
shapes of the DAC's outp
and
fl rd"'M~
2
VQe,RMS = u'
viSB (
2nR
C)2
. 2n2K3 (6.27)
Comparing this result to what we got in Eq. (6.16) we see that using the Sinc lowpass
filter is nearly ideal for removing modulation noise. The more important concern, when
using the Sine lowpass filter, is the droop that the desired signal undergoes. Ideal shape Sh:
(ideal area is all(
6.1.3 Offset, Matching, and Linearity shaded)
Examine the passive NS-modulator with offsets and mismatched resistors seen in Fig. (a)
6.l3. In this section we want to discuss how non-ideal behavior affects the performance
of the modulator. To begin, notice that a comparator offset has the effect of causing the
average value of vint to be VCM ± Vas and thus the offset passes directly to the output of
the modulator. This means that if we apply the common-mode voltage to the input the Figure 6.14 C
average of the output voltage is VCM ± Vas.
(ixed-Signal Circuit Design Chapter 6 Data Converter Design Basics 213
Ri
0---~------~------------~+
F(f)i: == .., , (2rif' RC/

l.lf,
Figure 6.13 Passive modulator with mismatch and offsets,
. »f
1s2
Resistor Mismatch
In order to determine the effects of resistor mismatch we can re-write Eqs. (6.9) to (6.12),
:r response, neglecting the effects ofthe offset voltage, as
~ _ _:..!.2!.. + -VOURI Vim) .. lC + VQe(f) Vout (6.28)

f Jro
Rj' (Vin Vim) - Ri . (VOUI + Vinl) + jroRiRr C, VQe =jroRiRj" C· Vout (6.29)
(6.24)
Rj" Vin - Vmt . (R, + Rf) + VQe -jroRjRr C· VQe = (jroR,Rj" C + R i )· VOlll (6.30)
et jroCRj -Vim'
Vout = 1 +jroCR . Vjn + 1 +jroCRf ' V Qe + 1 +jroCRj (6.31 )
J
(6.25)
The effect of mismatched resistors is a gain error (but no non-linearity, and thus,
distortion). Note that the absolute value of the capacitor isn't critical or important for
precision operation,
The Feedback DAC
The feedback DAC is the most critical component in the modulator for precision
(6.26) operation, Consider the waveforms seen in Fig. 6.14. In this figure we show the ideal
shapes of the DAC's output (remember our DAC here is a simple inverter so we get
'3
(6.27) ,
hat using the Sinc lowpass

e important concern, when (c) Wider, ideal, pulse shape
tl undergoes. Ideal shape Shape with under
(ideal area is and overshoot
shaded)
ched resistors seen in Fig: (a) (b)
ior affects the performance (d) Increasing pulse width (going
is the effect of causing the ' slower) to minimize nonideal pulse
es directly to the output of characteristics,
:i.e voltage to the input the
Figure 6.14 Comparator output pulse shapes, input to the integrator.
214 CMOS Mixed-Signal Circuit Design Chapter 6 Data Convert!
perfect linearity, Fig. 6.15). As seen in the figure, the shape of the pulse affects the
amount of charge, or current, we send back to the capacitor. In part (a) we see the ideal
pulse shape and the ideal area under the pulse (the shaded area). In part (b) we see how
1.0Vf
O.9V •...•
n.BV •••.•
the finite rise time and fall time can affect the actual area under the curve and thus the
output of the integrator. In order to minimize these unwanted effects we can use wider n.N]'.. '"
D.6V ,"'"
pulses as shown in parts (c) and (d), which means we run the modulator at a slower
D.SV
clocking frequency. Increasing the width of the pulses minimizes the percentage of the
O.4V
area affected by the transition times. Note that the feedback signal directly subtracts from
O.JV
the input signal so that any noise or unwanted variation in the fed back signal, such as an
D.N
amplitude variation, can be considered as adding noise to the input (and thus degrading
D.1V
the modulator's SNR). This is important. In the coming chapters we will use switched
D.W
capacitor circuits that simply have to fully-discharge in order to make the shape of the D~.
feedback pulse less important.
Figure 6.16
Ideal
/ MSB of the filter's outp
:> 1.0 through the selector to tb
,;:f
£I-
::I
\ Nonideal the selector to clamp the
0 Dead Zones
0 Besides the nonlinearity
0 0.5 1.0 Comparator input, V
the output doesn't move,
is seen when the input si
Figure 6.15 Ideal and nonideal transfer curves for a l-bit DAC. zones are the result of
DACOjJ,et 0000100001. etc.}. The
relatively wide range of i
Notice, in Fig. 6.15, that if our DAC's reference voltages are offset from their ideal values this question examine th!
of VREF+ and V REF- that, like mismatched resistors, all we get is a gain error (no the output of the modulal
non-linearity). Possibly the most important concern when using a single-bit inverter suppose the input voltag
topology DAC is the on-resistance of the transistors used to drive the feedback resistors. time, it's possible for the
The drive strength of the MOSFETs should be so high that little voltage is dropped across the fed back current [-\
them (so the output of the DAC swings between V REF+ and V REF-). This (limited DAC using an active integrator
drive) is, again, another reason we'll soon start to focus on switched-capacitor
implementations of NS modulators. 6.2 Improving SNR
Linearity of the First-Order Modulator
In this section we discw
We've ignored the effects of the extra noise/distortion term seen in Eq. (6.12) because it's We'll start out by discussi
a nonlinear error highly dependent on the input signal's characteristics (and thus hard to modulator. This topolog
quantify). Let's use simulations to look at the linearity of the first-order NS modulator and discussed in the last sectit
digital filter seen in Fig. 6.1 0 (with a DAC connected to the output of the digital filter to avoid dead zones), and Ie
show the digital data as an analog wavefonn). Figure 6.16 shows the input/output of Fig. we'll discuss using switcb
6.10 with a slow ramp applied to the modulator's input. Note that when the input ramp benefit of switched-capac
voltage is close to the power supply rails the digital output becomes nonlinear (too high remove the effects of
when the input is close to ground and to low when the input is close to VDD). Also seen non-overlapping clock g(
in this figure, as mentioned in Ex. 6.2, is the digital filter overflowing. In order to avoid discuss putting NS modu
this situation we can use a selector, like the one seen in Fig. 4.40, with the Set input lowering the final output
connected to the MSB of the filter (remember we do a mUltiply by 2 by removing the section by showing how a
filter's MSB to scale the filter's output to full scale as discussed in Ex. 6.2). When the and noise by removing th.
1ixed-Signal Circuit Design Chapter 6 Data Converter Design Basics 215
:>e of the pulse affects the

In part (a) we see the ideal
ea). In part (b) we see how
Overflow
lder the curve and thus the
d effects we can use wider
the modulator at a slower
nizes the percentage of the
gnal directly subtracts from
fed back signal, such as an
: input (and thus degrading
lters we will use switched
r to make the shape of the
Figure 6.16 Simulating the linearity of the first-order NS modulator.
MSB of the filter's output is a 0 we simply pass the multiplied-by-2 output of the filter
through the selector to the final output. When the MSB of the filter's output is a I, we use
the selector to clamp the final output to 1111 and thus avoid overflow.
Dead Zones
)
Besides the nonlinearity seen in Fig. 6.16, notice that for some ranges of input voltages
Comparator input, V
the output doesn't move or, rather, the output is dead. A simple example of a dead output
is seen when the input signal is close to the common-mode voltage, 500 mY. These dead
a I-bit DAC.
zones are the result of a repeating modulator output code (e.g., 010 10 I, 110110,
0000100001, etc.). The question is why does the modulator output code repeat for a
relatively wide range of input voltages (e.g. 460 m V < Vi" < 540 mV)? In order to answer
ffset from their ideal values this question examine the modulator seen in 6.13. With an input voltage of 500 mV
re get is a gain error (no the output of the modulator is 101010... so that the average of the output is 500 mV. Now
using a single-bit inverter suppose the input voltage is increased to 510 mY. Because the voltage Vim varies with
[rive the feedback resistors. time, it's possible for the average current supplied from the input, [v m -V;nt(t)]IR; to equal
Ie voltage is dropped across the fed back current [-vout-Vint(t)]IR/ when the modulator's output is 1010101... By
VREF-). This (limited DAC using an active integrator, Sec. 6.2.4, we can hold Vin/ constant and eliminate dead zones.
:us on switched-capacitor
6.2 Improving SNR and Linearity
In this section we discuss techniques for improving signal-to-noise ratio and linearity.
,!llin Eq. (6.12) because it's We'll start out by discussing the second-order passive (uses two capacitors) noise-shaping
lcteristics (and thus hard to modulator. This topology is considerably more useful than the first-order topology
rst-order NS modulator and discussed in the last section because it has better linearity, randomizes the output code (to
ltitput of the digital filter to avoid dead zones), and lower modulation noise in the signal bandwidth of interest. Then
lWS the input/output of Fig. we'll discuss using switched-capacitors instead of resistors in the feedback paths. The big
~ that when the input ramp benefit of switched-capacitor circuits over continuous-time circuits is that, Fig. 6.14, we
~comes nonlinear (too higb remove the effects of non-ideal pulse shapes. The drawback is the need for a
s close to VDD). Also seen non-overlapping clock generator (which consumes power and layout area). Next we'll
:rflowing. In order to avoid discuss putting NS modulators in parallel. This is useful for increasing SNR while not
g. 4.40, with the Sel input lowering the final output clocking frequency (at all or as much). Finally, we'll end the
iply by 2 by removing the . section by showing how an active circuit, e.g. an op-amp, can be used to improve linearity
ised in Ex. 6.2). When the and noise by removing the extra term seen, for example, in (6.12).
216 CMOS Mixed-Signal Cireuit Design Chapter 6 Data Converte
6.2.1 Second-Order Passive Noise-Shaping and

After examining the first-order modulator seen in Fig. 6.4 we might wonder if we can get
better perfonnance by double filtering the input signal and removing the comparator's
connection to VCM' Figure 6.17 shows the resulting circuit. In this circuit we have two Finally, we can write
feedback paths. We've connected the largest amount of feedback to the inverting input of
the comparator to ensure ncgative, overall, feedback. Note that, because the output is fed
back to both integrating nodes v) and v2' the circuit will act to drive these nodes to the
same value and thus attempt to keep them equal to each other.
noting the quantization m

second-order passive noi~
SNRideal =
The modest increase in S

better linearity and reduc
extra noise/distortion tern
Figure 6.1 7 Second-order passive modulator.

Note that this topology 2
To attempt to describe the operation of the circuit let's write drawback of this is that tr
(Vin - Vj Vo,,1 VI
~1. -
VDD to ground. Figure
l R ---+-="--~
R R ) jmC - VI (6.32) simulation seen in Fig.
linearity and extent of dea,
and
( ---.<-
Vl-V2
R ' R
I
Vat/I-V2) ·--=v,
jmC·
(6.33)
:::lu.. ;.
8V U
If the quantization noise added to VI and v2 is VQel and VQe2 then + V Qel = Vo"ll and
V2 + VQe2 = V out2. We can then write
VJ
n.1V
O. 1·· ..
"'.,u~.'
(
n.GV 'U"'+'
Vin - 3Vl +V2 +jmRC· V Qe1 == voutl(jmRC-I) (6.34) n.sv ....... j..
0.4'1 ....... ~U
VI 2V2 +jmRC· VQe2 = v ou l2(jmRC -1) (6.35)
O'JV~""'i
Adding these two equations gives O.2V .........
O.lV·.. ,"
Vin - 2vI - V2 +jmRC. (V Qel + V Qe2) = (vaul] + vat/a)' (jmRC - I) (6.36) o.nv .
o~s s~s
As a quick check to ensure that this equation is correct, notice that if we pass the output
signal through a 100vpass filter with a bandwidth approaching 0, 0) - ) 0 and we use a large Figure 6.18 Repeating thi
RC then for a DC input, Vin "" Vj "" V2 and Vin - 2Vl - V2 -2V out (so Vau! "" Vi")' Next,
adding the random signal powers together (see, for example, Eq. [5.55] and the associated
Example 6.3
discussion) gives Repeat the simulation
2 modulator seen in Fig. I
2 (2
(mRC) . "VQel + VQe2
2) =(mRC )2 . 2VQe (6.37)
The simulation results
resembles the input am]
'(ed-Signal Circuit Design Chapter 6 Data Converter Design Basics 217
and
ight wonder if we can get
:moving the comparator's
this circuit we have two Finally, we can write
k to the inverting input of
because the output is fed 2 (roRc)2
V . '=
1 + (roRC)2 2 (6.39)
I drive these nodes to the oul,nOlse
2 1 ·v·
2
(6.40)
VOut,signal
1+ (roRC)2 In
noting the quantization noise power is cut in half. Equation (6.18) can be rewritten for the
second-order passive noise-shaping topology as
Vlj2
P
SNRideal 20'10g =6.02N+1.76 15.13+3010gK (6.41)
VnOlse,RMS
The modest increase in SNR, however, is not the big benefit of this topology. Rather the
better linearity and reduction in dead zones are the major benefits of the topology. The
extra noise/distortion term can be written as
2vI + V2
(6.42)
or. 1 + (roRC)2
Note that this topology attempts to drive VI and V 2 to the same value, that is Vi.' The
rite drawback of this is that the comparator must operate with an input range extending from
1 VDD to ground. Figure 6.18 shows the simulation results where we repeated the
VI (6.32) simulation seen in Fig. 6.16 but used the second-order modulator. Clearly both the
DC
linearity and extent of dead-zones are much better using the second-order modulator.
(6.33) .
:hen VI + VQel
UroRC -1) (6.34):

C-l) (6.35) ,
2)' UroRC-l)
5~s 1 O~s 15"s 2n~s 25~s 3n~s 35"s 40"s 45~s 50\ls
that if we pass the output
ro ~ 0 and we use a large Figure 6.18 Repeating the simulation seen in 6.16 but with a second-order modulation.
Voul (so V oul "" Vin). Next,
[5.55] and the associated

Example 6.3
Repeat the simulation seen m Fig. 6.11 and Ex. 6.2 using the second-order
modulator seen in Fig. 6.17.
(6.37)
The simulation results are seen in Fig. 6.19. The output amplitude more closely
resembles the input amplitude .•
VI
1.0V
O.9Y
O.8Y .......
O.7V •.
,, 'i
O.6V
n.sv
O.4V -
O.3V
O.ZY
O· 1V T
o.ov
o.o~s
Figure 6.19 Repeating the simulation seen in Fig. 6.11 but with a second-order modulation. Figure 6.21 Regene
6.2.2 Passive Noise-Shaping Using Switched-Capacitors The operation of this topol,

(6.31). The signal gain can
Figure 6.20 shows the first-order modulator seen in Fig. 6.4 implemented using switched
capacitor (SC) resistors, Fig. 2.35 (the resistors in Fig. 6.4 are replaced with SC resistors).
Figure 6.21 shows the simulation results similar to Fig. 6.7 but using this new
implementation. Again the benefit of this implementation over the continuous-time If C isn't exactly equal to
implementation seen in Fig. 6.4a is that the shape of pulse coming out of the feedback elim'inate this gain error, a
DAC, here an inverter, isn't important as long as the capacitors fully charge and sharing the feedback and i
discharge. of this circuit are found at
To characterize the operation of this topology let's write, again see Fig. 2.35, see that the input signal, in
together using C,m' The inl
Rsc =
1 (6.43) the polarity of the outpu1
I,C connected the input and fe(
the plate with the largest
bottom plate of C" and iH
plate, from the substrate, S
Digital passes through to C,./, Wh,
Since the bottom-plate par
charge from this parasitic i:
n-l n
n 112
Figure 6.22 Sv,;itche,
Figure 6.20 First-order passive modulator using switched-capacitors. gam err(
~ed-Signal Circuit Design Chapter 6 Data Converter Design Basics 219
second-order modulation. :Figure 6.21 Regenerating Fig. 6.7 using a passive switched-capacitor modulator.
rs The operation of this topology can be described by simply substituting Eq. (6.43) into Eq.
(6.31). The signal gain can then be written as
lemented using switched
placed with SC resistors). Rj == C;
(6.44)
5.7 but using this new R,
,ver the continuous-time
If C, isn't exactly equal to Cj then the input signal undergoes a gain error. In order to
ning out of the feedback
eliminate this gain error, and to simplify the implementation of the modulator, consider
lcitors fully charge and
sharing the feedback and input capacitors, Fig. 6.22. Simulations showing the operation
of this circuit are found at CMOSedu.com. Reviewing the derivations in Sec. 2.2.3, we
again see Fig. 2.35, see that the input signal, in Fig. 6.22, is subtracted from the fed back signal and summed
together using Clm • The inputs of the comparator are swapped, from Fig. 6.20, to ensure
the polarity of the output signal matches the input signal's polarity. Notice that we
connected the input and fed back signal's to the bottom plate of C/. Remember that this is
the plate with the largest parasitic capacitance. When the ~I switches are closed, the
bottom plate of C and its parasitic, are charged to VI•• Noise coupled into this bottom
"
plate, from the substrate, sees the low-impedance input so that ideally none of the noise
Digital
passes through to Ctnt" When the <1>2 switches close the bottom plate of C/ charges to vow!"
>----t>--- Vout Since the bottom-plate parasitic charges back and forth between Vi. and VO" ' , none of the
charge from this parasitic is transferred to C,.,.
~l
>----tr--- Vout
VCM
Figure 6.22 Switched-capacitor implemenation of the passive modulator without

led-capacitors. gain error.
220 CMOS Mixed-Signal Circuit Design Chapter 6 Data Convertel
6.2.3 Increasing SNR using K·Paths What about USinl

Figure 6.23 shows a 2·
By increasing the sampling rate,J;, we can spread the quantization noise out over a wider
benefits to this topology
frequency range, Figs. 5.12 and 5.26. Thus, for a fixed digital averaging filter bandwidth
K-paths of modulators, 2
(see Fig. 6.1), the amount of noise in a digital output signal can be reduced. As discussed
3) the comparator's are t
earlier in Secs. 2.1.6 and 5.3 we can increase the effective sampling frequency by using
operation can occur over
K-paths (putting K modulators in parallel). Since we've used the same variable, K, for
topology is the mismatc
both the number of points averaged in the digital filter on the output of a modulator, Sec.
digital outputs of the mo
4.2, and the number of paths used, Sec. 2.1.6, let's, in this section, use variables with
and 10). This addition, W
differentiating subscripts to describe the operation of a modulator implemented with
K-paths and oversampling H(z) 1 +Z-1 1
Kavg '" number of samples averaged in the digital filter (6.45)
and
or an average of two filtt'
Kpa•h = number of paths used in the modulator (6.46) from 0000 to 1000 (whic
The digital filter connected to the output of the modulator can then be described using and 6.18 when the input (
the overflow problem, 0
1 - z-K",g JL discussed earlier, is to us'
H(z) -= [ I _z-1 (6.47)
000 to 111.
By using K-paths our sampling frequency changes fromJ; to Kpalh Is so that the PSD of
the quantization noise, Fig. 5.26, gets spread out over a wider frequency range
2 (J ViSB (6 48)
VQe ) = 12 . K .r
path J.Y
.
For the noise-shaping topologies we would replace K (for example, see Eq. [6.18]) with
Kavg' Kpalh while the bandwidth of our desired signal spectrum ranges from DC to B
when decimation is used where
B= (6.49)
2Kavg
The next question that we need to answer is "Is it practical to implement parallel
paths of noise-shaping modulators or Nyquist-rate data converters?" Clearly there will be
an increase in layout area using this approach. Is the increase in SNR worth the increase
in chip size, power draw, or complexity? Well, let's not spend any time on Nyquist-rate
converters (e.g., flash or pipeline) in a K-path configuration (called a time-interleaved
converter) since the input signal would have to meet Bennett's criteria (pages 165-166,
Figure 6.23 Two-patr
consider problems with a DC input). Reviewing Fig. 2.37 we see that using a SC
modulator like the one seen in Fig. 6.22 may be a possibility. However, notice that we Note that each pa
need to multiply up the clock frequency from!, to KJ; then pass the resulting signal at a different voltage, del
through the non-overlapping clock generator seen in Fig. 2.38. Further, the SC
modulators would have to settle (fully charge/discharge their capacitors) within TjK
seconds (an even bigger concern if the modulator uses an active element like an op-amp). so combining the input n
If this is possible why not simply use a single path clocked at the higher rate, KJ; (or feedback paths into K-r
better yet two paths clocked at KJI2 like the topology seen in Fig. 2.36)? We get the same mismatch, requires som,
performance as the K-paths but with a much simpler implementation. Since we have to we've added an amplif
direct, and process, the input signal to the various paths, again Fig. 2.37, at a high-rate comparator's offset is ref
limits the use of K-paths in SC circuits (more on this in a moment and in Ch. 9). G = 100, for example, th
(ed-Signal Circuit Design Chapter 6 Data Converter Design Basics 221
What about using the modulator seen in Fig. 6.4 in a K-path implementation?
:m noise out over a wider Figure 6.23 shows a 2-path, or time-interleaved, implementation. There are several
veraging filter bandwidth benefits to this topology including: 1) the input can be continuously connected to the
be reduced. As discussed K-paths of modulators, 2) no active device (e.g. an op-amp) with settling time issues, and
pIing frequency by using 3) the comparator's are triggered on the rising edge of a clock signal (so the feedback
he same variable, K, for operation can occur over the entire clock period, Ts for each path). The drawback of this
[tput of a modulator, Sec. topology is the mismatched gains through each path. Notice that we've combined the
ction, use variables with digital outputs of the modulator into a two-bit word (so the possible outputs are 00, 01,
llator implemented with and 10). This addition, we should recognize, is a filter with a transfer function
I-
H(z) = I +Z-l Z-Kpath
"'--=---
I _z-l
where /s,new = Kpafh ',Is, =e _j2n,_f_
/s,treW
:ligital filter (6.45)

(6.50)
Itor or an average of two filter. Ifwe were to use 8-paths we would get a 4-bit output ranging
(6.46)
from 0000 to 1000 (which may result in the same overflow problems we saw in Figs. 6.16
m be described using and 6.18 when the input of the topology is near or VDD, here). A simple solution to
the overflow problem, other than using a selector to keep overflow from occurring as
(6.47) discussed earlier, is to use only 7-paths (instead of 8) so the final output code ranges from
000 to Ill.
llh -Is so that the PSD of
quency range
Output
VOUll (2-bits)
(6.48) >---1"'=::"';
@2/s
pie, see Eq. [6.18]) with Carry
n ranges from DC to B
(6.49)
~al to implement parallei voual

's?" Clearly there will be
SNR worth the increase
my time on Nyquist-rate
;alled a time-interleaved
criteria (pages 165-166,
Ie see that using a SC Figure 6.23 Two-path, time-interleaved, passive modulator with mismatch and offsets.
:-!owever, notice that we Note that each path, in Fig. 6.23, will attempt to hold the input of each comparator
)ass the resulting signal at a different voltage, dependent on the offset voltage of the comparator,
2.38. Further, the SC
capacitors) within TjK (6.51 )
~lement like an op-amp). so combining the input resistors and capacitors into a single path and the comparators and
the higher rate, Kj~ (or feedback paths into K-paths, to simplify the circuit and to reduce the effects of path
2.36)? We get the same mismatch, requires some thought. Consider the 4-path topology seen in Fig. 6.24. Here
:ation. Since we have to we've added an amplifier, with a gain of G, in series with the input path. Each
Fig. 2.37, at a high-rate comparator's offset is referred back to the integrating capacitor by dividing by this gain. If
•and in Ch. 9). G = 100, for example, the differing offsets will have little effect on the circuit's operation.
Reduces the effects of varYing comparator offsets.
v:l~.
Path filter
T';C -.~---~
H(z) '" 1-z

4 1.IIVIT
0.9V ....
O.BV •• i'"
4R~ r~
1-z- 1 0.7'1 ..... .
L____~ . 4>1 0.6V .... ..

~_ ______~--'
O.SY ......
0.4V .... ..
+ 0.3V ..... .
0.2V .... ..
0.1V .... ..
o.ov+-
o.ops
Figure 6.25 Sim
Analog i K-path
In l modulator
Note that decimation

is not used here or
in Fig. 6.25, while it
is used in Figs. 6.26
and 6.27. Figure 6.26
Kpath = 4, only two clock phases shown. using decimation of 4 we

output by the path filter if
Figure 6.24 Four-path passive modulator. No longer time-interleaved since the integrator the path filter in Fig. 6.
is common to all feedback paths (we'll call this the K-Delta-I-Sigma topology)
Nyquist-rate ADC (a droc
Another design concern, when using this topology, is the delay around each feedback can use this topology to irr
path. If there is excessive phase shift through the forward or feedback paths, the
modulator will be unstable. Using an open-loop (no feedback) amplifier, like a diff-amp, 1.1IV:::;::s;::
will ensure minimum delay (again noting the gain, and thus frequency response, of this o,9v~'1~"'1
amplifier aren't important as long as the gain is high enough to eliminate the offset effects
of the comparators and the delay through the amplifier is comparable to TsIKpath). Using
0.8''1"+l
0.7'1-·
an op-amp, in a feedback configuration, can ultimately limit the maximum speed of this O.6V J ··
topology. Figure 6.25 shows the output of the modulator in Fig. 6.24 with the same input 0.5v 4..·
signals and values used to generate Figs. 6.7 and 6.21. In Fig. 6.25 we've displayed the ;
0·4'11 ....
digital output word in analog form. Notice that the RC filtered output of this circuit is I
O,3V-t~~· ..
much smoother (contains less noise) than the outputs seen in Fig. 6.7 and 6.21. The extra 0.2v l..... .
smoothing from the inherent filtering when adding the outputs of the modulators together,
(see filter transfer function in Fig. 6.24), helps to reduce the noise in the signal. Because
of this inherent filtering it's easy to perform decimation directly on the output of the
o.ov -l
O.1V ..... ..
o.o~s
modulator. Figure 6.26 shows adding a register to re-time the output of the modulator
(decimate) back down to /,. Also seen in this figure is the digital filter seen in Fig. 6.1 that Figure 6.27 Regen
is used to remove the modulation noise. Regenerating the simulation results in Fig. 6.25
V(out) V!dou~
Path filter 1.0V-.--""",nrri
. .
, , , , ,
4 ) O.9V <-.----------,----------,----------,---------- . . - -
, , , , ,,
H(z) = I-z-I O.BV
,,
,
,,
,,
,
,,
,
,
,
,,
,
I
,
--.----------,----------,--------.-,----------..,-
,,
,
,,
. -
I-z ,o· , , ,
, _______ ,, __________ •, __________ ,, _________ _
O.7V
O.6V
O.5V
O.4V ..........•.........
O.3V ..........•.........
O.2V
O.1V
o.oV'+---i---j-.LLLLLlU.tw'-WlllJ.lilljLlULJb...-T---'''''-"..1UfiWllllJlJW.Df'-".J.IJ
o.o~s O.2~s O.4~s O.6~s O.B~s 1.0~s 1.2~s 1.4~s
~
, 3-bits out Figure 6.25 Simulating the operation of the 4-path modulator in Fig. 6.24.
,
@41s
bits:
· , I _ Z-Kpa1h log2 K path + 1
K- b ItS, I _ Z-Ka"g ]L
1 - Z-I I---b-cif-ts---I [ 1-z- 1 j,'
1
H(z)=~
I-z
-4
· . 4.32 !
Figure K a",
)
I-*---'----"-~-----l-c-Kpath I Final output clock rate:
Note that decimation
is not used here or
: +
,
Kpath
1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Decimator:l ____________________
Kavg Decimator:
I
+ ,
in Fig. 6.25, while it Path filter Averaging filter

is used in Figs. 6.26
and 6.27. Figure 6.26 Performing decimation on the output of the modulator.
:s shown. using decimation of 4 we get the results seen in Fig. 6.27. The rate of the digital word
output by the path filter is fs (just as it is when using a Nyquist-rate converter). Further,
led since the integrator
Delta-I-Sigma topology). the path filter in Fig. 6.26 has the same frequency response as the SIR used in a
Nyquist-rate ADC (a droop of -3.9 dB atfsl2, Fig. 2.17). Thus, with some thought, we
ly around each feedback can use this topology to implement high-speed Nyquist-rate ADCs.
or feedback paths, the
mplifier, like a diff-amp, l.OV-,--""-n-nrrVcm!v,;;,in,,.).",,-----,r-,_V-,-!o_ut.,..)- - c ._ _-,,~!c:cdO=-=ut,,-)_ : - - '
:quency response, of this O.9V .. . •.......• ; ..........•.•••...•.. ;.......... ; ..•......• ~ .... .
liminate the offset effects , , , , ,
-,----------,----------,-.--------,----------.,----
O.BV .. , , , , ,
, , , ,
Irab1e to Tsl Kpath). Using O.7V ..........•..•.
• ,,
______ 4 __________ •
,, ,, ,,
_ _ _ _ _ _ _ _ _ _ • _ _ _ _ _ _ _ _ _ _ .. _ _ _ _
,,, ,,, ,
,,
,
,,
: maximum speed of this O.6V ..........•....
,
--------_.- ... -.--.--------_
,
.. --------------
, ,
6.24 with the same input ,

,
.. ... .
O.5V ..........•..•• - --.----------.----------.----
,
6.25 we've displayed the ..
O.4V •••.......•.........••....
·· ·· ..
.- --.----------.----------.----
..
I output of this circuit is
O_3V ------------------- .• --.
___ •
·, ___ •
..,,
______ • __________ 4 ____ _
.
~. 6.7 and 6.21. The extra._ · ,
O.2V
: the modulators together,
O.W
ise in the signal. Because .
O.OV+-----r---r-
tly on the output of the O.O~s O.2~s O.4~s O.6~s O.8~s 1.0~s 1.2~s 1.4~s
output of the modulator

filter seen in Fig. 6.1 that Figure 6.27 Regenerating the signals seen in Fig. 6.25 with a decimation of 4.
lation results in Fig. 6.25
224 CMOS Mixed-Signal Circuit Design Chapter 6 Data Convert
Revisiting Switched-Capacitor Implementations

At the beginning of the section, we dismissed the option of using switched-capacitor
noise-shaping topologies in a K-path configuration, Fig. 2.3 7, because the capacitors
would have to charge or discharge within T,IK seconds (comparator delay < To IK is a
and finally
challenge). We said that if this were possible why not use two paths, clocked on opposite
phases of a clock (Fig. 2.36), but at the higher clock frequency of K·Is? In the next
chapter we'll show that a first-order noise-shaping delta-sigma modulator implemented
using switched-capacitors has an input/output relationship given, see Eq. (7.2), by Voul = -
STF(f) NTF(f)
,--A--" ~.---..
vout(z) == Z-l 'Vin(Z) + (I _Z-I) .VQe(z) (6.52)

It would appear that by
The signal-trans fer-function (STF) is simply one clock cycle delay, Z-l while the effect of the input signa
quantization noise is differentiated, Fig. 1.20. In other words the noise-transfer-function useful for Nyquist-rate
(NTF) is that of a differentiator, (1 - z-I). Note the similarity to the differentiation, jroRC, from the output of the
the quantization noise sees at low frequencies, 1 » jroRC, in the continuous-time passive the modulator's output.
NS modulator, Eq. (6.12). If we put K of these switched-capacitor topologies described hold Vi., fixed so that it ,
by the above equation in parallel, Fig. 2.37, we can write the corresponding output of the an active element discus
topology, see Eq. (2.56), as
Before getting tc
STF(fl NTF(f)
~ r----"----. the next chapter, that WI
Vout(z) Z-K'V;n(z)+(I-z-K).VQe(z) (6.53) with the added amplifl
feedback system) equal
Note that the data is changing, on the output of this topology, at a rate of K Is = !,.new, so
get an effective decrease
that z = ej2rcfljs.n,~. While the quantization noise PSD, as indicated in Eq. (6.48), will be
spread out over a wider frequency range the fact that our NTF has the shape of a comb 6.2.4 Improving Line,
filter, Fig. 1.25, instead of differentiation limits the use of SC modulators in K-path ADCs
Figure 6.28a shows the
using clock signals like those seen in Fig. 2.37 for high-speed conversion.
input to the comparator,
One may wonder why the STF is Z-K or such a long delay? Looking at the timing
of the clock signals in Fig. 2.37 we see that each path is only activated every To seconds.
If z == ej2rcfljs.new or z = e j2rcfl(K/.) then to represent a single path delay of T, seconds we have
to use Z-K. In this scenario, Fig. 2.37 where H(z) represents the transfer function of a In (b) we've replaced thl
modulator, each of the modulators is independent, that is, not sharing the integrating can write
capacitor (integrator) as we did in the topology seen in Fig. 6.24. With some thought we
can implement a practical K-path ADC using SC circuits sharing a common integrator,
Fig. 6.24, with clock signals. also seen in Fig. 6.24. having a width of Ts and leading
If the amplifier's gain, G.
edge spacing ofT/K seconds so that the effective samplingfrequency is K Is (Ch. 9).
Effects ofthe Added Amplifier on Linearity
We added the amplifier with a gain, G, in Fig. 6.24 in order to reduce the effects of
comparator offset and make combining K-paths of quantizers sharing a common
integrating capacitor a practical analog-to-digital converter topology. We haven't analyzed
how this added amplifier can affect the linearity and performance of the topology. Let's
do that here. Rewriting Eqs. (6.8) to (6.12) with this gain included we get
VQe(f) + G· Vint(f) = Vout(f) (6.54) (a)
(6.55)
Figure 6.28 ReI'
lixed-Signal Circuit Design Chapter 6 Data Converter Design Basics 225
Vin - Volil 2Vil11 + VQe -jO)R~ =jO)R~ . VOUI (6.56)

,f using switched-capacitor
37, because the capacitors Vin 2Vint + VQe -jO)R~ = Voul' (1 +j(J)Rg) (6.57)
nparator delay < Ts IK is a
paths, clocked on opposite and finally
ency of K·Is? In the next NTF(/l
STF(f)
na modulator implemented j(J)R£
m, see Eq. (7.2), by -2· Vim
VOU! = . G
c ·VQe + (6.58)
I +J(J)R c 1 +j(J)R~
\. ... -~~
Extra noise/distortion
(6.52)
It would appear that by using a very large gain, G, we can eliminate the lowpass filtering
ycle delay, ;:--1 while the effect of the input signal (and thus pass very wideband signals to the modulator'S output,
the noise-transfer-function useful for Nyquist-rate analog-to-digital conversion) and remove the modulation noise
) the differentiation, jwRC, from the output of the modulator. The extra noise/distortion term, however, remains in
he continuous-time passive the modulator's output. Again, the only way to get rid of the noise/distortion term is to
acitor topologies described hold V inl fixed so that it doesn't vary. This can be accomplished using relatively large 1. or
;orresponding output of the an active element discussed next.
Before getting too excited about removing the modulation noise we'll find out, in
the next chapter, that we can think of the comparator as also having a gain, Gc ' in series
(6.53) with the added amplifier that varies keeping the forward gain of the modulator (a
feedback system) equal to unity. In other words, if we increase the amplifier gain G we
at a rate of K·1s = fs,new, so
:ated in Eq. (6.48), will be get an effective decrease in the comparator's gain Gc'
F has the shape of a comb 6.2.4 Improving Linearity Using an Active Circuit
'lodulators in K-path ADCs
~onversion.
Figure 6.28a shows the integrating topology we've used in our passive modulator. The
input to the comparator, Vinl , in this circuit can be written as
~lay? Looking at the timing
. 1
activated every T, seconds. lin' j(J)C (6.59)
Iclay of Ts seconds we have
; the transfer function of a In (b) we've replaced the passive integrator (the capacitor) with an active integrator. We
Jot sharing the integrating can write
.24. With some thought we · Vin( Vc
- G . Vim an d lin = Jij(J)C (6.60)
'ring a common integrator,
a width of T, and leading
quency is K·1s (Ch. 9). If the amplifier's gain, G, is big we can write
. 1
Vc "" -lin' j(f)C (6.61)
er to reduce the effects of
~
tizers sharing a common i in Comparator c .c omparator
Jlogy. We haven't analyzed
ance of the topology. Let's
led we get
~f :t? .
~
Vim"
I _~
Vc·
~
>-
(f) (6.54) (a) (b)
(6.55)
.Figure 6.28 Replacing the passive integrator (a) with an active integrator (b).
where we've switched the inputs of the comparator to account for the inversion.
Remember our goal is to keep v;nl constant so that we reduce the noise/distortion term in,
for example, Eq. (6.58). We can then write
Vi"'''''.fro C . G (6.62)
As G -; <X) we get Vi"1 - ; O. Figure 6.29 shows the implementation of a first-order

continuous-time noise-shaping modulator using an active integrator. The same equations
derived earlier, Eqs. (6.12), (6.19), and (6.20), apply to this configuration.
V,'. R
~"----------~~--~----~i'~------ Comparator
Analog C VCM-f + Digital
!\I'~__~v_·in_I _1_ Vouf
Figure 6.31
VCM i+ Second-Order Noise-Sha

~()p-amp
Is Figure 6.32 shows a sec
topology seen in Fig. 6.
don't include VCM in the f
DAC
Figure 6.29 An active-integrator NS modulator.
Example 6.4
Repeat Ex. 6.1 using the modulator seen in Fig. 6.29.
Treating the comparator ;
The simulation results are seen in Fig. 6.30. In the simulation we can show that Vim
doesn't vary (the point of adding the op-amp to the modulator). In order to show
the better performance in linearity/distortion let's pass the I-bit digital output we can write
through an average of 16 filter, see Ex. 6.2, and regenerate the results seen in Fig.
6.16 (see Fig. 6.31). Clearly, the active topology in Fig. 6.29 shows better linearity
than the passive topology seen in Fig. 6.4 .•
O.3V+....... :
lIJ---.;-1----.;-1----1-1----,1·
0.011" 0.2po 0.411. 0.6116 0.8110
-----i-
LOllS
Figure (
Figure 6.30 Repeating Ex. 6.1 for the first-order active NS modulator.
fixed-Signal Circuit Design Chapter 6 Data Converter Design Basics 227
ccount for the inversion.

he noise/distortion tenn in,
(6.62)
:mentation of a first-order
grator. The same equations
lfiguration.
Comparator
Digital
Vaul Figure 6.31 Linearity of the active NS modulator, compare to Fig. 6.16.
Second-Order Noise-Shaping
Is Figure 6.32 shows a second-order active noise-shaping modulator based on the passive
topology seen in Fig. 6.17. Knowing that all voltages are referenced to VC.<,f (so that we
don't include VCM in the following derivations to keep the equations simpler) we can write
VI _(Vin-Voal) ._1_ (6.63)
ator. R jruC
_(VI + VOUI) . _1_ (6.64)
R jruC
Treating the comparator as adding noise to v2' Fig. 6.4,
ion we can show that VIRt
(6.65)
llator). In order to show
the I-bit digital output we can write
e the results seen in Fig.
29 shows better linearity (6.66)
Vout
R R
I
Is
-Vout Vaal
Figure 6.32 Second-order noise-shaping modulator, version I.

ve NS modulator.
and finally
R R C
STF
NTF
v~~
h~
2
UroRC)
V out = -----=-----
2
'V rn + 2 • V Qe (6.67)
UroRC) + jroRC + 1 UroRC) + jroRC + I
The STF has a second-order response, Sec. 3.2.2. Poor selection of the resistor and
capacitor will cause instability. Note that for low frequencies the NTF increases as the R~V~
square of frequency so we expect better SNR, for a given bandwidth B (see Eq. [6.15]),
using this topology. Let's try to make this topology more robust by using only a single
feedback path, Fig. 6.33. The transfer relationship for this modified topology is then
NTF
STF ~
,.....-----A--- 2 Figure 6.
Voul ::;:; 1 'Vi" + UroRC) ,VQe (6.68)
UroRC)2 + 1 (jroRC)2 + 1 this equation reduces to, f,
Reviewing Fig. 3.35, the poles fall on the y-axis and so the topology is unstable. ofl/2,
R R
1'--+----11 VI
T NIl'
Unstable!! ! Signal-to-Noise Ratio
C ;
Following the procedure fi
R~
B

Vc
+
>-___-V"-2--; +
Vout
V;oise,RMS J
2 IN1
o
Vow Again with B :=!si2K we fl
Figure 6.33 Second-order noise-shaping modulator with a single feedback path (bad).
V l.fi
Consider the single-feedback path modulator seen in Fig. 6.34. We've added a SNRideal 20 .log---!.P~-
Vnoise,Rk
resistor in series with the feedback capacitor in the first integrator. We can now write
Setting RC = 2.69/fs (notil
Vi =_(Vin~vour) 'C~C+R) (6.69) integrators, discussed in ill
V2 -(~) 'jroC == (Vin -Vout) 'jro~C' Cro~C+ I) (6.70)
STP NTF
~-~ , ~--~
2
jroRC + 1 . (jroRC) V
Voul = 'V m + 2 . Qe (6.71)
(jroRC)2 +jroRC + I (jroRC) + jroRC + I For every doubling in K
The benefits of this topology, other than the better SNR and only a single feedback loop, increase in SNRideal' To es
are that we can select RC so that the STF is closer to one over a wider bandwidth and (6.21 ),
there is smaller delay between the input and output of the modulator (which is of critical
importance in a K-path topology). Setting, for example,
RC 2Ts 2!fs (6.72) For 16 5, K '£ 1024 we can
(6.67)
;tion of the resistor and

the NTF increases as the
width B (see Eq. [6.15]),
st by using only a single
led topology is then
Figure 6.34 Second-order noise-shaping modulator, version II.

(6.68)
this equation reduces to, for frequencies of interest much less than the Nyquist frequency
of1,12,
ogy is unstable.
(6.73)
Unstable!! ! Signal-la-Noise Ratio
Following the procedure for calculating SNR seen in Sec. 6.1.1
B B
+ VOUI
V;oise,RMS 2 f INTFU)l2IVQeU)12 ·df=2· 12F . f(21t/-RC)4 .df
o :Is 0
(6.74)
V;Oise,RMS = 2 . . (2rcRC)4 . (6.75)

fs 12ls 5
Again with B =f s l2K we get
feedback path (bad).

2
Vn<)lse,
, R"S == 12 • (2'TrRC)4
. .~ (6.76)
m, 80. K5
V I fi (21tRC -/,)2
iig. 6.34. We've added a SNRideal 20 . log V p == 6.02N + 1.76 20 log !80 + 20 logK5/2 (6.77)
,r. We can now write noise,RMS 80
Setting RC 2.69/fs (noting that we might have to increase the RC to avoid saturating the
(6.69) integrators, discussed in more detail in the next chapter)
SNRideai 6.02N+ 1.76-30.10+5010gK (6.78)
(6.70)
30.10
(6.79)
SNRideal:::: 6.02(N + Nine) + 1.76 (6.80)

(6.71)
For every doubling in K above K = 4 we get 2.5 bits increase in resolution or 15 dB
y a single feedback loop, increase in SNRideQI' To estimate the order, L, of the decimating filter let's write, see Eq.
r a wider bandwidth and (6.21),
lator (which is of critical
(6.81)
(6.72) For 16 :s; K:S; 1024 we can use a second-order filter, L 2.

ADDITIONAL READIN(
Example 6.5
Simulate the operation of the second-order NS modulator in Fig. 6.34 clocked at [1] J. C. Candy and G.
100 MHz, with RC = 20 ns, and decimated with a filter having a transfer function IEEE Press, 1992. I:
[11 ~:-~16r [2] S. K. Tewksbuty

Noise-Shaping Cae
CAS-25, pp. 436-4L
Estimate the bandwidth, B, of the output signal, the increase in the number of bits,
;¥mc' and SlVR,deor [3] H. Inose, Y. Yasuc
IEEE, Vol. 5I,pp. J
The simulation results are seen in Fig. 6.35. The final output clock frequency is
6.25 MHz and the bandwidth of the desired signal, B, is 3.125 MHz. Using Eq. QUESTIONS
(6.79) we estimate the increase in the number of bits as 5. Using Eq. (6.80) the
6.1 Suggest a topology
ideal SNR is 37.88 dB. Note that the number of bits coming out of the filter is 9
back signals are cu
bits, the input I-bit word size increases 8-bits. We can throw the lower 5-bits out
topology have the e
or throw the MSB out to divide by 2 and throw the lower 4-bits out Gust not
Simulate the operat
continue to pass them along in the system since they are simply noise) .•
6.2 Simulate the opera~
960mV I
V(vin] Vlout] VI"utt] quantizer (ADC). l
anOmV kHz (as used to gen
800mV
6.3 Using Eqs. (6.14)
720mV
modulators using a
640mV
560mV 6.4 Repeat Ex. 6.2 if (

4aOmV
Estimate the freque
400mV
the input signal. Ve
320mV
240mV 6.S Suppose the compa

160mV 50 mV input-refer
OOmV
o.o~s
,
O.7ps lAps 2.1ps 2.0ps 3.5ps 4.2p. 4.9ps 5.6ps 6.3ps
conversion from an.
6.6 Figure 6.36 shows
Figure 6.35 Simulation results for Ex. 6.5.
techniques. Assumi
Discussion circuit in the invert
0.5 V, a 10k resisto
The second-order active NS modulator is the workhorse for analog-to-digital converters feedback resistor of
using noise-shaping. The increase in resolution of 2.5 bits for evety doubling in K is a closed loop gain
significant. This topology can also be used in a K-path configuration, Fig. 6.24, replacing and a peak-to-pea~
the capacitor and amplifier (see simulation examples at CMOSedu.com). The challenge is operates. Note that
keeping the forward delay through the modulator small (so the modulator remains stable). results in more idea
This dictates using simple op-amp topologies that are vety fast with moderate gains, e.g.,
self-biased diff-amps. Finally. for high-speed we focused on using K-path topologies. The
drawback of this approach is the need for several clock phases whose rising edges are
spaced by T/K. A delay-locked loop (DLL) can be used for generating these clocks and is
straightforward to design. The benefits of the K-path approach are that the matching of lO(
the resistors undergoes averaging via the K feedback paths, the pulse rising/falling edges
are made less important since relatively wide pulses are used in each feedback path, and non-invertin
there is an inherent filtering when we combine the outputs of the paths together. Clearly
further research in the design of these topologies is warranted; however, we leave this
Figure 6.36 A
work to the refereed literature and continue to focus on the fundamentals.
xed-Signal Circuit Design Chapter 6 Data Converter Design Basics 231
ADDITIONAL READING
n Fig. 6.34 clocked at [1] J. C. Candy and G. C. Ternes (eds.), Oversampling Delta-Sigma Data Converters,
ng a transfer function IEEE Press, 1992. ISBN 0-87942-285-8
[2] S. K. Tewksbury and R. W. Hallock, Oversampled, Linear Predictive and
NOise-Shaping Coders of Order N> I, IEEE Trans. Circuits and Sys., Vol.
CAS-25, pp. 436-447, July 1978.
: in the number of bits,
[3] H. Inose, Y. Yasuda, A Unity Bit Coding Method by Negative Feedback, Proc.
IEEE, Vol. 51, pp. 1524-1535, November 1963
put clock frequency is
;.125 MHz. Using Eq. QUESTIONS
. Using Eq. (6.80) the
6.1 Suggest a topology for a passive-integrator NS modulator where the input and fed
Ig out of the filter is 9
w the lower 5-bits out back signals are currents. Derive a transfer function for your design. Does your
er 4-bits out (just not topology have the extra noise/distortion term seen in Eq. (6.12)? Why or why not?
.ply noise) .• Simulate the operation of your design .
6.2 Simulate the operation of the NS modulator seen in Fig. 6.4a but using a 4-bit
quantizer (ADC). Use a 100 MHz clock frequency and an input sinewave at 500
kHz (as used to generate Fig. 6.7).
6.3 Using Eqs. (6.14) and (6.17) compare the noise performance of passive NS
modulators using a I-bit quantizer to those using a 4-bit quantizer.
6.4 Repeat Ex. 6.2 if C is changed to I pF and a 1 GHz clock frequency is used.
Estimate the frequency where the output of the digital filter is -3 dB (0.707) from
the input signal. Verify your answer with simulations.
6.5 Suppose the comparator used in the NS modulator and filter used in Ex. 6.2 has a
50 mV input-referred offset voltage. How will this offset voltage affect the
6.3JlS
conversion from analog to digital? Verify your answer with SPICE simulations.
6.6 Figure 6.36 shows the implementation of an op-amp using mixed-signal design
5.
techniques. Assuming the comparator is powered with a 1 V supply, simulate the
circuit in the inverting op-amp confignration with the non-inverting input held at
0.5 V, a 10k resistor connected from the inverting input to the input source, and a
:lalog-to-digital converters feedback resistor of lOOk from the op-amp's output back to the inverting input (for
)r every doubling in K is a closed loop gain of -10). Set the input source to have a DC offset of 500 mV,
~ation, Fig. 6.24, replacing and a peak-to-peak amplitude of 20 mV at 500 kHz. Explain how the circuit
:du.com). The challenge is operates. Note that using an active integrator, instead of the passive integrator
:nodulator remains stable). results in more ideal behavior (less variation on the op-amp's inputs).
with moderate gains, e.g.,
.ng K-path topologies. The
es whose rising edges are
inverting input
erating these clocks and is
100 pF I Op-amp's
1 are that the matching of
output
: pulse rising/falling edges
n each feedback path, and non-inverting input
1 GHz
:he paths together. Clearly
j; however, we leave this
Figure 6.36 An op-amp implemented using mixed-signal techniques .
.amentals.
6.7 In your own words explain why dead zones in the second-order passive modulator
seen in Fig. 6.17 are less of a problem than the first-order modulator seen in Fig.
6.4a.
6.8 Verify, using simulations, that the modulator seen in Fig. 6.20 suffers from
capacitor mismatch while the one in Fig. 6.22 does not.
6.9 What is a time-interleaved data converter? Why is a time-interleaved converter
different from the converter seen in Fig. 6.24?
6.10 Show the details of how to derive the transfer function of the path filter seen in
Fig. 6.24. Noise-S
6.11 Repeat question 6.7 if an active integrator, Fig. 6.28, is used in place of the
passive integrator.
6.12 Repeat Ex. 6.5 if K is changed from 16 to 8.
In this chapter we co
We start out discus:
topologies including SI
7.1 First-Order ~
The block diagram of

we showed, but in the
the input, vin(z), and th
where, as in the last (

noise's transfer functio
Delt,
In VinCZ)
t +
Analog --"'"
L
Figurl
Consider what
2.2.3) as shown in the i
1.ixed-Signal Circuit Design
Ind-order passive modulator

·rder modulator seen in Fig.
Chapter
in Fig. 6.20 suffers from
. time-interleaved converter
7
on of the path filter seen in
Noise-Shaping Data Converters
In this chapter we continue our discussion of first-order noise-shaping data converters.

We start out discussing first-order topologies and then move on to higher-order
topologies including second-order noise-shaping and cascaded modulators.
7.1 First-Order Noise Shaping

The block diagram of a NS feedback modulator is shown in Fig. 7.1. At the end of Ch. 5
we showed, but in the s domain, that the output of the modulator, voulz), can be related to
the input, vin(z), and the ADC's quantization noise, VQe(z), by
NTF(z)
r---'--,
A(z) 1
Vout(z) = 1 + A(z) 'Vin(Z) + 1+ A(z) .VQe(z) (7.1)
where, as in the last chapter, STF(z) is the signal's transfer function and NTF(z) is the
noise's transfer function.
Delta Sigma
In Vin(Z) Vaut(z) Out
! +
Integrator
Digital
Analog~
DAC
Figure 7.1 Block diagram of a noise-shaping (NS) modulator.
Consider what happens if A(z) is an integrator (implemented using a DAI, Sec.

2.2.3) as shown in the figure. Equation 7.1 becomes
voul(z)=Z-lVin(z)+(1 Z-l),VQe(Z) (7.2)
234 CMOS Mixed-Signal Circuit Design Chapter 7 Noise-Shaping D:
This equation is important! It shows that the input signal simply passes through the After careful review we sho
modulator with a delay while the quantization noise is differentiated (see Fig. 1.20 for the to the NS modulator represe
magnitude response of a digital differentiator with a transfer function 1 - Z-I). We can
We can use the SPII
think of the noise differentiation as pushing the quantization noise to higher frequencies.
the NS modulator of Fig. 7.
We'll come back to how NS affects the quantization noise spectral density, VQe( f), in a
a 500 kHz sinewave centen
moment. But first let's attempt to understand what's happening here.
input and output of the mod
In Fig. 7.1 the summer takes the difference (Delta) between the input signal and
the fed back signaL The integrator accumulates or sums (Sigma) this difference and feeds
the result back, via the ADC and DAC, to the summer. This forces the output of the
modulator to track the average of the input. Sometimes the fed back signal will have a
value greater than the input signal, while at other times the fed back signal will be less
than the input signal. The average signal fed back, however, should ideally be the same as
the input signal. Note that this type of NS modulator is often called a Delta-Sigma or
Sigma-Delta modulator. Also, at this point, we should see the need for the averaging
filters discussed earlier.
A circuit implementation of a first-order NS modulator is shown in Fig. 7.2. For
the moment we use a single-bit ADC and DAC (both implemented using the clocked
comparator) for gain linearity reasons (discussed in more detail later). The analog voltage
coming out of the integrator is compared to the common-mode voltage (this is our I-bit
ADC) using the comparator. For the I-bit DAC a logic-O has an analog voltage of 0 V, Figure 7.3 Sir
while a logic-I has an analog voltage of VDD I V here) so that the comparator's output
can be used directly (fed back to the DAI).
A Digital First-Order NS D(
So far our noise-shaping d
<PI
<PI ,<P2 I i~ Figure 7.4 shows a first-c
conversion. While the disc
VCM--~ I ~ ~ I reconstruction filters is giv
vd
-Voul
first-order NS demodulator.
PI""
1
~ v,.
""
: -l +
>----*------1'
Clod"d
+
00""'''''0'
:1
Digital inp~; I ~
j,
Figure 7.2 Circuit implementation of a first-order NS modulator. Clock input
The comparator is clocked on the rising edge of <PI resulting in a T, delay (Z-l) in Figure 7.
series with the fed back signal and a delay of Tj2 (z-112) in series with the input signaL
To understand this statement, remember that the nonoverlapping clock dead time (the Figure 7.5a shows a
time both <P 1 and <P2 are low) is short and, practically, the falling edge of <P2 occurs at the DAC. Figure 7.5b shows thl
same instance as the rising edge of <PI (and so we could also use (!)2 to clock the circuit and the circuit of Fi~
comparator). This results in a transfer function, see Table 2.2, to the input of the (see Fig. 1.28), and the qw
comparator (which can also be thought of as the ADC output since the fed back signal quantization by selecting (m
and modulator output are the same signal) of 011111 in two's complemeJ
-I current discussion, are VDD
Desired ADC input/output -zI _I (Vin - voua (7.3) implement a DAC using n
-z
later, is the preferred methm
ixed-Signal Circuit Design Chapter 7 Noise-Shaping Data Converters 235
imply passes through the After eareful review we should see that the eireuit implementation of Fig. 7.2 corresponds
iated (see Fig. 1.20 for the to the NS modulator represented by the block diagram shown in Fig. 7.1.
function l-z-l). We can
We can use the SPICE models developed earlier to demonstrate the operation of
oise to higher frequencies.
the NS modulator of Fig. 7.2. Assuming our sampling frequeney is 100 MHz, the input is
:ctral density, VQe( f), in a
a 500 kHz sinewave centered around Vel,! 0.5 V) with a peak amplitude of 0.5 V. The
Jere.
input and output of the modulator are shown in Fig. 7.3.
tween the input signal and
:) this difference and feeds
s forces the output of the
~d back signal will have a
~d back signal will be less
ould ideally be the same as
n ealled a Delta-Sigma or
he need for the averaging
r is shown in Fig. 7.2. For

:mented using the cloeked
I later). The analog voltage
:e voltage (this is our I-bit
an analog voltage of 0 V;
Figure 7.3 Simulating the operation of the modulator in Fig. 7.2.
bat the comparator's output
A Digital First-Order NS Demodulator
So far our noise-shaping discussion has centered around analog-to-digital conversion.
Figure 7.4 shows a first-order NS demodulator-based topology for digital-to-analog
conversion. While the discussion concerning selection of the digital interpolating and
reconstruction filters is given in Ch. 4, we are interested here in the topology of the
first-order NS demodulator for use in a DAC.
:locked comparator
Digital inpu!
---'if--I
'L Digital
Filter
. r It
'-lS modulator. Clock input \ Interpolation filter
liting in a Ts delay (Z-l ) Figure 7.4 DAC using a NS modulator and digital filter.
~ries with the input signal.
ping clock dead time (the Figure 7.5a shows a block diagram of a first-order NS demodulator for use in a
19 edge of <1>2 occurs at the DAC. Figure 7.5b shows the practical implementation. The only differences between this
also use i!i2 to clock the circuit and the circuit of Fig. 7.1 is that the DAI is replaced with an all-digital integrator
2.2, to the input of the (see Fig. 1.28), and the quantizer (comparator) is replaced with a circuit that performs
. since the fed back signal quantization by selecting (using the MSB of the accumulator output word) digital VREF+ (=
011111 in two's complement) or VREF- 100000 in two's complement) which, for our
current discussion, are VDD and ground. Note that this topology isn't the preferred way to
(7.3) implement a DAC using noise-shaping. Using the error-feedback topology, discussed
later, is the preferred method.
236 CMOS Mixed-Signal Circuit Design Chapter 7 Noise-Shaping.
VQe(Z) where N is the number 0

Using a single-bit ADC.
Quantizer VLSB = 1 V. This again 81
In Vin(Z) Out pushing it to higher frequ
! + Analog write the PSD of the NTF
Accumulator
Digital --""
(a) Figure 7.6 shows the PS

Is = 100 MHz. Note that
Quantizer noise. The modulation noi
Accumulator
modulator. The modulatic
In MSB Out reviewing Fig. 7.6 we s~
:Olllll... However, after passing tl
: 100000 ... frequency noise resulting
VQe.RMS' By restricting the
quantization noise in our
(b) digital filter on the output
input signal. Notice that
Figure 7.5 Block diagram of (a) a NS demodulator and, (b) a more detailed quantizer with an LSB tha
implementation for use in a DAC.
feedback that adds or subt
input.
7.1.1 Modulation Noise in First·Order NS Modulators
Here we present a more detailed discussion of the quantization noise spectrum for a
first-order NS modulator. To begin, let's write Eq. (7.1) in the time domain, V2/Hz J.
6nv
J.lnVE...•.•.
3.0nV ....... ..
vour[nTs] == Vin[(n-l)Ts] +vQe[nT,] vQe[(n-l)Ts]

::::~~-":::::::
(7.4)
which shows the output is a function of the first difference (order) of the quantization
· ·.·
2.1nV ....... .
1.8nV ....... .
noise vQe[nTs] - vQ.[(n - I)TJ Intuitively note that the smaller we make Ts (the faster we
1.5nV ....... .
sample since Ts = 1/f,), the closer our digital output vouJnTs] approaches the analog input
l.znv
E
vin[nTJ 0.9nV ...... ..
0.60V ...... ..
N ext, using Eq. (7.1), let's write the product of the noise transfer function and
0.3nV ..... .
vQe[z] (the modulation noise) of the first-order NS modulator in the frequency domain as O.OnV
OM.
NTF(z)VQe{Z):= (l-z-l)VQe(Z) --+ NTF(f)VQe(f) = (I_e--' f,).
i2rt
~
oJ 12js
Figure 7.1
(7.5)
where we have used, see Fig. 5.12, 7.1.2 RMS Quantizatioi
VQe(f)= ~ (units, V/JHz I forOSjSfs/2 (7.6) The RMS quantization no
..J 121s J using
B
and, once again (see Eq. [4.1] or, for the I-bit ADC [comparator], Eq. [6.1]),
V~e.RMS = 2 JINTF.
(7.7) o
Remembering that the rna;
frequency,;; , and the over
where N is the number of bits used in the low-resolution ADC/DAC in the modulator.
Using a single-bit ADCIDAC in a NS modulator, N = I, results in this book in
Quantizer
VLSB = I V. This again shows that we are not reducing the quantization noise, but are
Out pushing it to higher frequencies so that it can be filtered out. Using Eq. (l.46), we can
Analog write the PSD of the NTF as
INTF(f)12 . I VQe(f) I2 . 4 sm i
. 2 7t
(7.8)
121s is
Figure 7.6 shows the PSD of the first-order NS modulation noise for VLSB 1 V and
Is 100 MHz. Note that we are discussing modulation noise instead of quantization
noise. The modulation noise is the quantization noise after being differentiated by the NS
Quantizer
modulator. The modulation noise is the unwanted signal added to the input signal. After
MSB Out reviewing Fig. 7.6 we see that the magnitude of the modulation noise is significant.
However, after passing this signal through a lowpass filter, we can remove the higher
frequency noise resulting in a lower value of data converter RMS quantization noise,
VQe.RMS' By restricting the bandwidth of the modulation noise we can drive the RMS
quantization noise in our signal to zero. Of course, by lowering the bandwidth of the
digital filter on the output of the modulator we also limit the possible bandwidth, B, of the
input signal. Notice that we have violated Bennett's criteria, Sec. 5.1.1, by utilizing a
(b) a more detailed quantizer with an LSB that is comparable to the input signaL Now, however, we are using
feedback that adds or subtracts a signal from the input and ultimately affects the quantizer
input.
ition noise spectrum for a

:ime domain,
(7.4) ,
(order) of the quantizatiOIi
~ we make Ts (the faster we
lpproaches the analog input
10ise transfer function and

1 the frequency domain as
20.... 401.4. 60.... 80.... 100....
VLSB
-e .- in =92 = 50 MHz /, Hz, X 10 6
J
12is
(7.5) Figure 7.6 Modulation noise for a first-order NS modulator.
7.1.2 RMS Quantization Noise in a First..()rder Modulator

The RMS quantization noise present in a bandwidth, B, can be calculated, see Eq. (6.13),
using
::>r], Eq. [6.1]),
(7.9)
Remembering that the maximum bandwidth of our input signal is related to the sampling
frequency,!, , and the oversampling ratio, K, by
238 CMOS Mixed-Signal Circuit Design Chapter 7 Noise-Shaping Dal
B (7.10) (7.14) we can solve for tl

2K uses a I-bit quantizer) 38
and, for small values of x, (ADC) resolution, using
Note that the ADC is m
sinx ""X (7.11 ) shown in Fig. 7.4.•
then 7.1.3 Decimating and Fill
7 _ VLSB • ...1L. It's important to note that E(
~ Qe,RMS - [fi !3 K3i2 (7.12)
was passed through a perfe(
This equation should be compared to Eq. (5.56). Further, we can describe the ideal data through a Sinc averaging fi
converter SNR using first-order NS, see Eqs. (5,10) - (5.13) as because the higher frequenc
section we want to answer
SNRideal =:
Vp
20 . log -V-
/J2 6.02N + 1.76 20 log ~ + 20 logK3/2 (in dB) (7.13)
averaging filter should be us'
Qe,RMS ",3 (2) assuming we use only th
the first-order NS modulator
or
We begin to answer 1
SNRideai 6.02N + 1.76 5.17 + 30 10gK (in dB) (7.14) bits, Nmc' as
This equation should be compared to Eq. (5.58) where we saw every doubling in the
oversampling ratio, K, results in a 0.5-bit increase in resolution (called simple
oversampling). Here we see that every doubling in the oversampling ratio results in 1.5
If our NS modulator uses a I
bits increase in the resolution (or a 9 dB increase in SNR;deaJ A first-order NS
the resulting data converter
modulator's performance is compared to simple oversampling in Fig. 7.7 (see also Sec.
called a multibit NS modula
6.1.1 and Fig. 6.9).
Further, we saw in Sec. 4.2.:
Improvement in resolution,Nine that we can require
(Bits added) 30 5.17
Nine == ----''''::----
6.02
16.6
SNRideal 6.02(N+Ninc) + 1.76
Solving this equation results
13.3
First-order NS
10.0 where M is the order of the
the averaging filter, or,
6.66
3.33 ~ Simple oversampling

O-+--t"'--+---I---!---!------» In the next section we discu~
10 100 lk 10k K ,Oversampling ratio we use a Sinc averaging filte
Figure 7.7 Comparing simple oversampling to first-order noise-shaping. Example 7,2
Comment on the implerr
Example 7.1 described in Ex. 7.1. As
Determine the ideal signal-to-noise ratio and the maximum signal bandwidth or 6.25 MHz.
allowed, B, for the first-order NS modulator of Fig. 7.1 if 16 of its output samples The transfer function of 1
are averaged (K 16).
Because the sampling frequency, Is ' is 100 MHz, we can use Eq. (7.10) to
determine the maximum input signal bandwidth, B, is 3.125 MHz. Using Eq.
(7.14) we can solve for the SNRidea' as (knowing that the NS modulator of Fig. 7.1
(7.10)
uses a I-bit quantizer) 38.73 dB. This corresponds to an equivalent data converter
(ADC) resolution, using Eq. (5.13), of 6.14 bits (number of bits added is 5.14).
Note that the ADC is made with the components, modulator, and digital filter,
(7.11 ) shown in Fig. 7.4 .•
7.1.3 Decimating and Filtering the Output of a NS Modulator
(7.12) It's important to note that Eq. (7.14) was derived assuming the output of the modulator
was passed through a perfect lowpass filter with a bandwidth of B. Passing the output
n describe the ideal data through a Sinc averaging filter, see Figs. 4.10 and 4.13, will result in a poorer SNR
because the higher frequency noise components will not be entirely filtered out. In this
section we want to answer two questions: (1) what order, L (see Eq. [4.19]), of Sinc
averaging filter should be used in the digital filter on the output of the NS modulator, and
K 312 (in dB)
(2) assuming we use only this filter (no additional filtering), how will the ideal SNR of
the first-order NS modulator be affected.
We begin to answer to the first question by writing the increase in the number of
(in dB) (7.14) bits, Ninc' as
law every doubling in th~ N =3010gK-5.17
resolution (called simple inC 6.02
(7.15)
mpling ratio results in 1.5
If our NS modulator uses a I-bit ADC, then the final, after the digital filter, resolution of
\jRldeal)' A first-order NS
the resulting data converter is ~nc + 1 bits. (An NS modulator using a 5-bit ADC [often
; in Fig. 7.7 (see also Sec.
called a multibit NS modulator] would ideally have an output resolution of Nine + 5 bits.)
Further, we saw in Sec. 4.2.5 that the word size increased by log2K bits in each stage so
that we can require
3010gK-5.17
.I K> 3010gK 5.17
6.02 L og2 - 6.02 (7.16)
'deal
Solving this equation results in L being greater than or equal to 2. In general, we ean write
NS L= l+M (7.17)
where M is the order of the modulator. For a first-order modulator we use two stages in
the averaging filter, or,
Ie oversampling 1I
H(z) = [ _-=-.L. -KJ2 (7.18)
K l-z- 1
In the next section we discuss second-order NS modulators (M= 2). For these modulators
ersampling ratio we use a Sinc averaging filter with L = 3.
:r noise-shaping.
Example 7.2
Comment on the implementation of the digital decimation filter for the modulator
described in Ex. 7.1. Assume the final output clocking frequency is 100 MHzll6
mm signal bandwidth or 6.25 MHz.
6 of its output samples
The transfer function of the digital filter is
can use Eq. (7.10) to 1

H(z)= _z_ -16J2
[ 1 -z·l
.125 MHz. Using Eq.
240 CMOS Mixed-Signal Circuit Design Chapter 7 Noise-Shaping [
The block diagram of the filter is seen in Fig. 4.32 using 4 stages and L = 2. The and finally,
increase in resolution through each (I +z-I)2stage is 2 bits (see Fig. 6.10 for the
filter when L = I). The resolution calculated in Ex. 7.1 was 6.14 bits, which we
round up to 7-bits. Because the output of the digital filter is 9-bits (8-bits through
the four stages plus the I-bit coming out of the modulator), we drop the lower two This equation should be cc
bits (divide by 4) to get our final 7-bit resolution .• filter was ideal with a band
Next let's examine how filtering with a Sinc filter affects the SNR of the data NS modulator and a secone
converter. Remember the SNRideal was calculated in Eq. (7.14) assuming the modulation
noise was strictly bandlimited to B. Figure 7.8 shows the PSD of the NTF2 (f)·1 VQe(f)12
(the modulation noise) of the first order NS modulator. Also shown in this figure is the Comparing this to SNRjdeal I
shape of the averaging filter's magnitude response squared, Eq. (4.20). Here we are results in only a 2.16 dE
showing the shape of a filter with L 2 (set by Eq. [7.17] for a first-order modulator) and remember that using a Sin
K = 16. We limit our range to /, 12. SNR will be lower than wi
order modulators using Si:
4
valid the deviation from Sf.
sin (
Krr.L
/
)
7.1.4 Pattern Noise frol
111(f)12 = l. f,
[ K . ( f) ] In the ideal Nyquist-rate A

"" ,(. words the output code doe!
Fig. 7.3 (the average of the
to a digital filter the outp\:
ripple on the output of the:
of the ripple and the ampl
shows an example of this
(the common-mode voltag,
fslK output is a square wave of
B, Ideal maximum input frequency at half the clocking frequer
outside our base spectrum
Figure 7.8 Showing modulation noise and filter response. a significant way, affect th
function that falls at half
We can calculate the R..\1S quantization noise on the output of the Sinc filter in a resulting in a constant filte
cascade of a first-order modulator and an averaging filter using (see Sec. 6.1.2) get the digital filter outpu
f,l2
V~e,RMS = 2 f INTF(f)l2·1 VQe(f) 1 2
• 111(f)12 • d/ (7.19) 600mV..,.-
,
o
f sinsin2((KnL)
4 550mV .....
V~,RMS == 12/ 8
f,l2
/' (7.20)
\
8 • K4 ' 0 nt) .d/

~.m'
\
Ifwe let S nt, then this equation can be written as
450mV
,
, 400mV'';-
V2Qe,RMS Ssin (KS) de

4
(7.21)
Dos 1
2
o sin S Figure 7.9 Showi
, stages and L = 2. The and finally,

s (see Fig. 6.10 for the
VLSB
as 6.14 bits, which we (7.22)
.s 9-bits (8-bits through JT2
we drop the lower two This equation should be compared to Eq. (7.12), which was derived assuming the digital
filter was ideal with a bandwidth of B. The SNR resulting from using a first-order (M = I)
fects the SNR of the data NS modulator and a second-order (L = 2) Sinc averaging filter is
) assuming the modulation SNR sinc = 6.02N + 1.76 - 3.01 + 30 10gK (in dB) (7.23)
of the NTF 2 (f).1 VQe(f)12
shown in this figure is the Comparing this to SNRideal given in Eq. (7.14), we see that using a Sinc filter for averaging
Eq. (4.20). Here we are results in only a 2.16 dB difference (increase) in SNR over the ideal filter. If we
l first-order modulator) and remember that using a Sine filter results in a droop in the desired signal, Fig. 2.31, the
SNR will be lower than what is predicted by Eq. (7.23). (Note that an analysis of higher
order modulators using Sinc averaging filters would show that as long as Eq. [7.17] is
valid the deviation from SNR idea/ is negligible.)
7.1.4 Pattern Noise from DC Inputs (Limit Cycle Oscillations)
In the ideal Nyquist-rate ADC, a DC input signal results in a single output code. In other
words the output code doesn't vary. In a NS-based ADC the output code varies as seen in
Fig. 7.3 (the average of the output is equal to the input signal). When this code is applied
to a digital filter the output of the filter shows a ripple or variation. Unfortunately, this
ripple on the output of the filter can cause noise in the spectrum of interest. The frequency
of the ripple and the amplitude of the ripple depend on the DC input value. Figure 7.9
shows an example of this ripple. The input signal for the modulator in Fig. 7.2 is 0.5 V
(the common-mode Voltage) while the modulator is clocked at 100 MHz. The modulator's
output is a square wave of alternating ones and zeroes. The first harmonic of this signal is
at half the clocking frequency or, in this example, 50 MHz. Since the ripple frequency lies
outside our base spectrum (which, from Ex. 7.2, is from DC to 3.125 MHz) it will not, in
response. a significant way, affect the SNR. (The digital filter will likely have a zero in its transfer
function that falls at half the clocking frequency eliminating the ripple altogether and
utput of the Sinc filter in a resulting in a constant filter output value.) If we increase the input signal to 510 mV we
(see Sec. 6.1.2) get the digital filter output ripple seen in Fig. 7.10. A component of the ripple is at a
rJ(f)l2· df 600mV,----,--,----,.--,----.:..c:;:.::L---,--~___:_-__,____,
550mV ....... ~ ...... .
4oomvl...~+_-t--+-+--i___;_-_T_-,___;_-....J
Ons 10nsJO~sZOns 40n5 SOns 60ns 70ns 80ns 90ns
KS) de
's Figure 7.9 Showing how filtering the output of a modulator results in ripple.
242 CMOS Mixed-Signal Circuit Design Chapter 7 Noise-Shaping Dat
S~OmV-,---_ _ _ _ _ _---,------,-V!::[o:::utf),,------,---_ _ _,----_ _---,

7.1.5 Integrator and Fol"VII
S20mV
SOOmV : :·::::::::::t.~~~.~s. ::j:::::::·:::::

,,, ,,
,
---------------.--
---------------.---------------
So far we haven't discussed f
are using near-ideal compollt
580mV ,
---------~---------------,------------
, to the finite op-amp output s'
, '
5S0mV and output signals shown in 1
5~OmV
520mV
. . fit!IIII!!!I!!/ •. ·mmlj·. I ··:
..:..·..:
swing of the op-amp is beyOl
op-amp were to replace th(
~m~mjJ~l:it ....
500mV voltages less than VDD (= 1
op-amp saturation is not ne(
~80mV
~SOmV
..... . i desirable to understand how
~~OmV modulator. Note also, in Fi!
On. 200ns 400n6 600ns 800ns
change when it passes thrOUj
fed back signal, the comparat
Figure 7.10 Showing a lower frequency ripple in the modulator's output
frequency that is roughly 1/500 ns or 2 MHz, which is well within our base spectrum. The
resulting tone will lower the SFDR and the SNR of the data converter. The question now
:::l..·..·..
l.ZV ....... ".
becomes, "How do we minimize the possibility of unwanted tones appearing in the data l.OV
converter's output spectrum?" Looking at the digital output ofthe modulator we see that it 0.8V
would be better to spread or flatten the repeating data out so that we don't get repeating O.SV
tones (as discussed in the dead zone discussion in Sec. 6.1.3). Although we may still have OAV
a tone, or repeating sequence, at a frequency in the base spectrum, the amplitude of the 0,2V .
tone will be well below the VQe,RMS of the data converter (and so it won't affect the SFDR O.OV'+'---+
·0.2V ......... ..
of the data converter). In order to accomplish this spread or randomization we can add a
-o,~V
noise dither source (see Sec. 5.3.3) to our basic NS modulator, as seen in Fig. 7.11. By
-O,SV,-I---t
applying the dither to the input of the comparator (quantizer) the dither will be o.o~. 0.2~.
noise-shaped like the quantization noise (the spectral content of the dither, Eq. [5.62], is
less important).
Figure 7.12 01
Dither Consider the linearizl

Source VCM
The gain of the integrator, se
~l
~l
,
Ip
VCM\
~~~lP-f-- We have also drawn the COil

VoUI
VCM
>------1+ gain of the comparator is uni
+ modulator's forward gain as
Figure 7.11 Adding a dither source to a first-order NS modulator. We can rewrite Eq. (7.2) usi:
Z
Vaut(z) = - -
Finally, note that unwanted tones are usually not a problem if the input signal is l+z
busy and random (not DC as discussed in this section). Later in the chapter, we discuss
If GF approaches zero (the
second-order modulators that utilize two integrators. The second integration helps to
then the output of the mode
spread the repeating sequences out over a longer period of time so that, hopefully,
noise. (This is bad.) Since
negligible unwanted tone energy is present in the base spectrum.
difficult to filter the modula
7.1.5 Integrator and Forward Modulator Gain

So far we haven't discussed the shape or amplitude of the integrator's output. Because we
are using near-ideal components in our simulations, we haven't seen any limitations due
to the fmite op-amp output swing. Figure 7.12 shows the integrator's output for the input
and output signals shown in Fig. 7.3 (using the modulator of Fig. 7.2). Clearly the output
swing of the op-amp is beyond the power supply rails. If the transistor-level model of the
op-amp were to replace the ideal op-amp, the integrator's output would saturate at
voltages less than VDD (= 1.0 V here) or greater than ground. While in some situations
op-amp saturation is not necessarily bad (the gain of the integrator goes to zero), it is
desirable to understand how decreasing fonvard loop gain affects the performance of the
modulator. Note also, in Fig. 7.12, that the output of the integrator makes the largest
change when it passes through the comparator reference voltage, VCM = 0.5 V, since the
fed back signal, the comparator output (a full-scale signal), is input to the integrator.
lodulator's output.
hin our base spectrum. Th~

)nverter. The question now
tones appearing in the data'
:he modulator we see that it
that we don't get repeating Power supply
Although we may still have range.
:trum, the amplitude of
50 it won't affect the SFDR
mdomization we can add a
)r, as seen in Fig. 7.1 L By
ltizer) the dither will be
of the dither, Eq. [5.62],
Figure 7.12 Output swing limitations in the op-amp (integrator).
VCM Consider the linearized model of our first-order NS modulator shown in Fig. 7.13.
The gain of the integrator, see Eq. (2.103) or Fig. 2.55, is given by
~l
GI= (7.24)
CF
We have also drawn the comparator with a gain. Up until this point we have assumed the
+ gain of the comparator is unity. We'll comment on this more in a moment. Let's define the
modulator's forward gain as
(7.25)
\IS modulator. We can rewrite Eq. (7.2) using this gain as
VOli/(Z) --=--=---1-) . VQe(Z) (7.26)

)blem if the input signal is
. in the chapter, we discuss
If GF approaches zero (the integrator saturates while the comparator gain stays finite),
econd integration helps to'
)f time so that, hopefully, . then the output of the modulator is the sum of the integrated input and the quantization
noise. (This is bad.) Since the quantization noise is not spectrally shaped it will be
n.
difficult to filter the modulator's output to recover the input signal. If the forward gain is
244 CMOS Mixed-Signal Circuit Design Chapter 7 Noise-Shaping [
In .x(z) Y(z) Out VCM--'\

l"'
"\T~
Figure 7.13 Block diagram of a NS modulator showing forward gains.

~ "" 0: 100MI
greater than two, then, as seen in Fig. 4.38 and the associated discussion, the poles of the
YUUmV
transfer function reside outside the unit circle and the modulator will be unstable. We can
810mV
restrict the values of the forward gain to
720mV
(7.27) fj)nmV
5~OmV
Ideally, however, the gain is one. il50mV
360tuV
Example 7.3 270mV
Show, using SPICE simulations and the modulator of Fig. 7.2, that an integrator lS0mV
gain of 0.4 will result in an op-amp output range well within the power supply 90mV .......
range. OmV
O.Ops 0"
Figure 7.14a shows a schematic of the modulator with G1 0.4. Figure 7.14b
shows the output of the integrator (the output of the op-amp) in the modulator of
part (a) with the input sinew ave shown in Fig. 7.3. The output swing is limited to Figure 7.14 (a) First
roughly 80% of the supply range. For general design it is desirable to set our the outp
integrator gain to 0.4. This ensures our integrator doesn't saturate unless the input
to the modulator goes outside the supply voltage range. (precise integrator gain i~
followed by an ADC.
It's interesting to note that in both modulators, Fig. 7.2 and Fig. 7.14a, the
forward gain is unity. This is a result of the effective gain of the comparator Before leaving this
changing forcing the forward gain, controlled by the fed back signal, to unity. shaping modulator that use:
What this means is that our modulator functions as expected with a signal gain of is the input signal to the AI
one (Eq. [7.2] is valid) whether G1 is 1 or 0.4. Next we discuss how this change in range of ADC output code~
comparator gain occurs.• allowable range of modulal
Figure 7.15 shows the transfer curves for the comparator. The x-axis, the
comparator input, is the output of the integrator in our modulator. Shrinking the
integrator's output swing while holding the output swing of the comparator at the supply 1.0
rails (1 V) results in an increase in effective comparator gain. This gain variation, with the >
integrator output swing, helps to set the forward gain of the modulator to precisely I. We ~
:;
can write this using equations as 0
Integrator gain, G I Comparator gain, G c 0
'-'''~' ,
0
Integrator output Comparator(modulator) output Modulator output
(7.28)
Modulator input Integrator output Modulator input
If the modulator is functioning properly, then the average value of the modulator output Figure 7.15
will be equal to the modulator input and thus GF = I. It's interesting to note that this result
xed-Signal Circuit Design Chapter 7 Noise-Shaping Data Converters 245
:;>iz) 4>1
ADC Ip
VeM
I
Y(z) Out
Vaut
>--+----,------1 +
Clocked comparator
(a)
: forward gains,
liscussion, the poles of the ,

r will be unstable. We can
7,2, that an integrator

.thin the power supply
I/ "" 0.4. Figure 7 .l4b

Ip) in the modulator of (b)
put swing is limited to Figure 7.14 (a) First-order NS modulator with an integrator gain of 0.4, and (b)
is desirable to set our the output of the op-amp.
lturate unless the input
(precise integrator gain isn't important) will apply to any integrator that is directly
followed by an ADC.
'.2 and Fig. 7.14a, the
ain of the comparator Before leaving this section, let's point out a couple of problems with a noise
back signal, to unity. shaping modulator that uses a multibit ADC, Fig. 7,16. Since the output of the integrator
:d with a signal gain of is the input signal to the ADC, the limited integrator output swing will directly effect the
uss how this change in range of ADC output codes. Limiting the range of ADC output codes will then limit the
allowable range of modulator inputs unless scaling is used (shifting the output codes or
1parator. The x-axis,
modulator. Shrinking
~ comparator at the supply
:> 1.0
his gain variation, with the
)dulator to precisely 1. We Gain is the slope ofthese lines.
o +=-~----'--+-----1- :>
ulator output o 0.5 1.0 Comparator input, V
Input signal
lulator input
Ie of the modulator output Figure 7.15 Comparator gain as a function of input voltage.
;ting to note that this result
246 CMOS Mixed-Signal Circuit Design Chapter 7 Noise-Shaping I
In order to deterr
Digital requirements of the compa
output code comparator changes states.
111 Change in integrat<
110
For the modulator of Fig.
101 hysteresis is much less tha
100 Dashed lines indicate ADC gain enough so that the compar
then the modulator will 1
011 designs can be used while
010 7.1.7 Op-Amp Gain (In1
001 Now that we've discusse,
OOO~>~--------------------~
open-loop gain of the op·
o lI8 2/8 3/8 4/8 5/8 6/8 7/8 8/8 gain, some of the charge st
Analog input voltage (integrator output) the feedback capacitor, C
leakage. The charge on the
Figure 7.16 A 3-bit ADC. the feedback capacitance.
We can write the (
sizing of capacitors in the DAI). Next, notice in Fig. 7.16 that the variation in the gain of
The output voltage of tl
the ADC, with input signal, is more limited than the gains attainable with the simple
common-mode voltage Vc
comparator seen in Fig. 7.15. Limiting the range of ADC gains can result in modulator
v~ is the op-amp's inver
forward gains that are not exactly unity. This is especially true at high input frequencies
(2.102), we can rewrite Eq
where the gain of the integrator is low. However, if the integrator gain is high, the
effective gain of the ADC is not important. The point here is that using a multibit ADC
will increase the open-loop gain requirements of the op-amp used in the integrator.
7.1.6 Comparator Gain, Offset, Noise, and HystereSiS or, rewrite Eq. (2.102) to il
It's of interest to determine how the performance of the comparator influences the
operation of the modulator. Both the comparator's offset and input-referred noise, Fig.
7.17a, can be referred back to the modulator's input, Fig. 7.17b. By doing so we can
determine how they effectively change the input signal seen by the modulator. As seen in Using this result in Eq. (7
Fig. 7.17, the high gain of the integrator, A( f), reduces the effect of the comparator's gain of the modulator, GF ,
noise and offset on the input signal. For example, if the gain of the integrator at DC is
1,000 and the offset voltage of the comparator is 50 m V, then the input-referred offset is
only 50 !-lV.
Comparator's input-referred . The gain error term

noise and offset, V n,comp (f) Input-referred nOIse and offset, Vn ,comp(f)/A(f)
In~~~fi\ /ut
~mparator
Integrator Integrator
Comparator
is ideally zero so that Eq.
gain, ClICn reduces the g
Note also that the denom
(a) (b)
term results in a data COl
Figure 7.17 (a) Referring the comparator offset and noise to (b) the input ofthe modulator. voltage that is a function
error] and frequency), but
fixed-Signal Circuit Design Chapter 7 Noise-Shaping Data Converters 247
In order to determine the minimum gain and maximum allowable hysteresis

requirements of the comparator, let's review Fig. 7.14. We see that when the output of the
comparator changes states, the output of the integrator changes by at least
Change in integrator output G/·(VDD VC,I1)=~~' VREF+;VREF (7.29)
For the modulator of Fig. 7.14 this equation can be evaluated as 0.2 V. As long as the
hysteresis is much less than this value and the gain of the comparator (110.2 or 5) is large
ed lines indicate ADC gain enough so that the comparator can make a full output transition with this input difference,
then the modulator will function properly. Very simple, low-performance comparator
designs can be used while not affecting the modulator's performance.
7.1.7 Op-Amp Gain (Integrator Leakage)
Now that we've discussed the gain of the comparator, let's determine how high the
~
open-loop gain of the op-amp must be for proper integrator action. With low op-amp
:/8 gain, some of the charge stored on the integrator's input capacitor, C1 , is not transferred to
It) the feedback capacitor, C F • This loss of charge is sometimes referred to as integrator
leakage. The charge on the input capacitance effectively leaks off when it is transferred to
the feedback capacitance.
We can write the open-loop, frequency-dependent gain of the op-amp as Aoi f).
t the variation in the gain of
The output voltage of the op-amp is then Vout=AOL(f)(v+-v_), where v+ is our
attainable with the simple
common-mode voltage VCM (the noninverting terminal of the op-amp), see Fig. 2.54, and
ains can result in modulator
v_ is the op-amp's inverting input terminal. Following the procedure to derive Eq.
ue at high input frequencies
(2.1 02), we can rewrite Eq. (2.100) with finite op-amp gain as
integrator gain is high, the
'i that using a multibit ADC
lsed in the integrator.
Q2 C/ (vCM- vout[nTs1 [T])
AOL(f) -V2 n s
(7.30)
or, rewrite Eq. (2.1 02) to include the effects of finite op-amp gain to get
comparator influences th~ Cl . VI (z) . V2(Z)
(7.31 )
ld input-referred noise, Fig. CF (I C, I
+Cr.AOLU)
)
-z
-I
7.17b. By doing so we can
,y the modulator. As seen iIi Using this result in Eq. (7.1) and, as discussed in the last section, assuming the forward
e effect of the comparator's gain of the modulator, GF , is one gives
n of the integrator at DC IS
n the input-referred offset is (7.32)
The gain error term

,ffset, Vn,comp(f)!A(f)
._1_
~
f.gain (7.33)
...
CF AoL(f)
~-~~or is ideally zero so that Eq. (7.32) reduces to Eq. (7.2). Note that reducing the integrators
Integrator gain, CllCn reduces the gain error while increasing the gain required of the comparator.
Note also that the denominator term is common in both the signal and the noise. This
(b)
term results in a data converter gain error (it behaves as if it were an op-amp offset
,) the input of the modulator. voltage that is a function of the integrator's output amplitude [which results in the gain
error] and frequency), but it will not affect the modulator's SNR. In order to determine the
248 CMOS Mixed-Signal Circuit Design Chapter 7 Noise-Shaping Data
increase in the modulator's output noise (the change in the shape of the modulation noise) where, for the DAI (see Fig. 7,
we need to look at the noise transfer function including the effects of the gain error
(7.34)
or, in the frequency domain, The feedback factor is 0.714
must settle in a time, t « T)~
(7.35) this percentage using Eqs. (7.3
~
Following the same procedure used to arrive at Eq. (7.12) and assuming constant op-amp Vaul/inal
gain, AoL(f), from DC to B, results in
The output will only reach 67(
2 ViSB [ ,,2 1 (Is 13 + 2 f, ] the op-amp used has a unity g,
VQe,RMS 2· 121s . 4(1 +egain)f; . 3" \2KJ Egain ' 2K (7.36)
noting that if egain 0, this equation reduces to Eq. (7.12).

If we assume the contribution to the noise from the error term squared, e;ain, is
small, which is valid for op-amp gain
AoL(f) > K (the oversampling ratio) (7.37)
r
over the frequency range of DC to B, then we can rewrite Eq. (7.13), to include the effects T
of finite op-amp gain, as v
SNR gerr =6.02N + 1.76 - 20 log fi + 20 logK312 10 log(l + egain) (7.38) FigUl
The largest degradation in the SNR, resulting from integrator leakage, can be estimated as In deriving Eq. (7.42)
0.5 dB if K:?: 8 (egain '" 1/8 neglecting GJ ). The minimum gain· bandwidth product of the (7.39) to determine the settli
op-amp is estimated as incomplete settling will resull
Op-amp unity gain frequencY'!un = K· B =Is 12 (7.39) output changes it will changt
the transfer function of our D,
assuming the op-amp is rolling off at 20 dB/decade at B (a dominant pole compensated
op-amp). Otherwise, the minimum gain of the op-amp can be estimated simply as the
overs amp ling ratio, K.
In order to illustrate typical op-amp requirements, let's consider the modulator of
Full, or complete, settling rec
Fig. 7.14 with K = 16 and B = 3.125 MHz (see Ex. 7.1). The fun of the op-amp is
larger than the sampling freq
estimated, using Eq. (7.39), as 50 MHz. If the open-loop response of the op-amp starts to
the required bandwidth of th
roll off at 10kHz, then the DC gain of the op-amp must be at least 5,000. However, we
error, resulting from incomp
could also use an op-amp with a DC gain of 100 (remembering low integrator gain
because the integrator is dire(
increases the undesirable effects [noise and offset] of the comparator on the performance
of the modulator topologies,
ofthe modulator) that rolls off at 500 kHz.
settling time becomes more
7.1.8 Op-Amp Settling Time integrator output must settle
linearized block diagram of
Equation (7.39) can be used, for the moment, to provide an estimate for the settling time
modulator is then evaluated t<
requirements of the op-amp in a first-order modulator. Assuming the settling time is
linear, and not slew-rate limited, we can write the change in the op-amp's output It's important to real
assuming a dominant pole compensated op-amp as slew-rate limitations. If slewi
_1_ not be a constant and will
Vaul == Vaulfinal(] (7.40) (whether a comparator follow
2rrfu . ~
e of the modulation noise) where, for the DAI (see Fig. 7.18), the feedback factor is
:ts of the gain error
~= CF (7.41 )
(7.34) CF+CI
The feedback factor is 0.714 in the modulator of Fig. 7.14. The output of the DAI, vaUl'
must settle in a time, t « Ts 12), to some percentage of an ideal value, VaUl/inG'. Solving for
this percentage using Eqs. (7.39), (7.40), and (7.41) and assuming Ts l2 = t results in
(7.42)
The output will only reach 67% of its ideal final value in the modulator of Fig. 7.14 when
2 is ]
Egain · 2K
the op-amp used has a unity gain frequency of/, 12.
Tor term squared, E~ain' is
Ltio)
V out
'g (1 + Egain) Figure 7.18 The feedback factor in the DAI.
:akage, can be estimated a In deriving Eq. (7.42), we used an op-amp unity gain frequency specified by Eq.
1· bandwidth product of th '
(7.39) to determine the settling response of the integrator. If the settling is linear then
incomplete settling will result in a constant DAI gain error (0.67 above). Every time the
=f,12 output changes it will change by some constant percentage of its ideal value. Rewriting
the transfer function of our DAI to include this constant gain error results in
ominant pole cOlnpem;atc:d Settling gain error, G s
)e estimated simply as CI '1 _~A.(f, jI")' VI (z) . z-1/2 - V2(z)
Z = -C . ( - e
Vout () P uni') . 1-1 (7.43)
F -z
consider the modulator
Full, or complete, settling requires that the op-amp's unity gain frequency, fun , be much
The f.," of the op-amp
larger than the sampling frequency, /, (in other words we can't use Eq. [7.39] to specify
mse of the op-amp starts
the required bandwidth of the op-amp if settling time is important). The constant gain
t least 5,000. However,
error, resulting from incomplete settling, can be tolerated in the first-order modulator
oering low integrator
because the integrator is directly followed by a comparator, as discussed earlier. In some
parator on the pel~tolm2lllcle
of the modulator topologies, though, the integrator is not followed by a comparator so
settling time becomes more important. In order to determine to what percentage the
integrator output must settle in these topologies, a gain term, say Gs ' is added to the
linearized block diagram of the modulator (integrator). The transfer function of the
:timate for the settling time
modulator is then evaluated to determine the allowable values of Gs for the application.
uming the settling time is
;e in the op-amp's output It's important to realize that we are assuming the op-amp doesn't experience
slew-rate limitations. If slewing is present, then the added gain term, in Eq. (7.43), will
1
not be a constant and will introduce distortion into the modulator's output spectrum
2nj;, . ~
(whether a comparator follows the integrator or not).
250 CMOS Mixed-Signal Circuit Design Chapter 7 Noise-Shaping 1
7.1.9 Op-Amp Offset Finally, as used in

from quantization noise, ji
The operation of the DAI is subject to the op-amp's offset. It can be shown that this offset
will effectively add (or subtract) from the common-mode voltage, VeAl' and thus
effectively shift the input signals upwards or downwards. The resulting modulator output
will then show an offset equal to the op-amp's offset. In order to circumvent this problem, and
offset storage can be used in the integrator.
7.1.10 Op-Amp Input-Referred Noise
Here we discuss how the DAl's unwanted noise contributions affect the SNR of the where Vp is, again, the peal
modulator, assuming we know the DAl's input-referred noise PSD V;,DAl!). Figure 7.19
shows the modulator's input-referred noise source, Vn,ckt(!), in series with the input
signa\. This noise source, with units of VI JHz ,
includes both the integrator's and the 7.1.11 Practical Implen
comparator's contributions. However, as discussed earlier, the noise contributions from
the comparator are usually negligible because of the high-gain of the integrator. Switched-capacitor circui1
charge injection. To reduc
Modulator's input-referred noise, Vn,ckt(f) =: JV;,DAI(f) + V;,comp(f)IA 2(f) could be stated that if r
fully-differential topologi!
In
\ .
~
first-order, the voltage cha
In addition fully-differenti:
substrate-coupled noise rej
Comparator
Integrator Figure 7.20 shows
The inputs are now differ,
Figure 7.19 The modulator's input-referred noise contributions from both the output of the integrator,
comparator and the integrator. transfer function as the sinl
Because the modulator's input-referred noise adds directly to the input signal, we
can use the derivations developed earlier in the chapter. As specified in Eq. (7.2), the
modulator's input, and thus its input-referred noise, pass through the modulator with a
delay of Z-l, If we assume the modulator's input-referred noise is white and bandlimited to
Is 12 such that
Vn,ckt(f) =: Ji for! <fs!2 (7.44)
then passing the output ofthe modulator through an ideallowpass filter with a bandwidth
Vl--
of B ( = fs/[2K] ) results in
(7.45)
Noting that not passing the output of the modulator through a lowpass filter results in an Figure 7.20 Fully-d
RMS output noise of Vn , we see that the averaging filter (the lowpass filter) reduces the
It's important to un
noise by the root of K. We could also think of the filtering as reducing the PSD of the
assume VCM 0.5 V and
modulator's input-referred noise by K. Remembering the jitter discussion from Ch. 5, we
Assuming the input is balm
see a direct parallel in the derivations of how averaging affects the RMS value of a
random signal (noise or jitter). maximum input voltage is
hand, is Vlm;n 0 I -I
range of the single-ended D
Finally, as used in Ex. 5.13, we can estimate the finite SNR of a data converter
from quantization noise, jitter, and circuit noise using
m be shown that this offset
e voltage, VCM' and thus vn.RMS I 2
" V Qe,RMS +
2
Vjiller,RMS +
2
Vckt,RMS (7.46)
resulting modulator output
:0 circumvent this problem, and
SNR 20 . log Vpl Ii (7.47)

Vn,RMS
)ns affect the SNR of the where Vp is, again, the peak amplitude of an input sinewave and
.
~SD V;DA[(f). Figure 7.19.
, in series with the input Vjitter,RMS JPAVGJitter (see Eq. [5.51]) (7.48)
lth the integrator's and the' 7.1.11 Practical Implementation ofthe First-Order NS Modulator
e noise contributions from
ofthe integrator. Switched-capacitor circuits suffer from the problems of capacitive feedthrough and
charge injection. To reduce these effects, fully-differential circuit topologies are used. It
could be stated that if reasonable size capacitors and dynamic range are required,
fully-differential topologies are a necessity simply because they subtract out, to a
first-order, the voltage changes on the switched-capacitors resulting from these problems.
~ut In addition fully-differential topologies are used because they improve power supply and
substrate-coupled noise rejection and improve distortion (even-order harmonics cancel).
rator
Figure 7.20 shows the fully-differential implementation of the DAI of Fig. 2.54.
The inputs are now differential, that is, now VI VI+ - VI_ and V2 V2+ V2-, as is the
ons from both the output of the integrator, Voul = Vout~ - Voul-. The fully-differential DAI has the same
transfer function as the single-ended DAI assuming the input signals are differential.
ctly to the input signal,

specified in Eq. (7.2),
)Ugh the modulator with
is white and bandlimited
~+----Vout+
/2
~+---- V OU /
lass filter with a
C] V I (z) . Z-112 - V2 (z)

CF . l-z- 1
lowpass filter results in Figure 7.20 Fully-differential discrete-analog integrator (DAl) implementation.
lowpass filter) reduces
IS reducing the PSD of
It's important to understand the signal levels in the fully-differential DAI. Let's
discussion from Ch. 5, assume VCM 0.5 V and the input voltages can range in amplitude from 0 to 1 V.
fects the RMS value of Assuming the input is balanced correctly ifvl+ = 0.85 V, then VI_ must equal 0.15 V. The
maximum input voltage is v tmax= I 0 = 1 V. The minimum input signal, on the other
hand, is V tmin 0 - I = -1 V. The range of inputs, or outputs, is then 2 V or twice the
range of the single-ended DAI.
252 CMOS Mixed-Signal Circuit Design Chapter 7 Noise-Shaping Data
Figure 7.21 shows the implementation of a first-order NS modulation utilizing a 7.2 Second-Order Nois
fully-differential DAI. Let's simulate the operation of this modulator with the input
If we review Eq. (7.2), we mi
signals and capacitor sizes used in Fig. 7.14 (1. 100 MHz, C1 = 0.4 pF, and CF = I pF,.t:.
VQe(Z) , can result in an impTO'
= 500 kHz, and a 0.5 V peak input sinewave [the input sinewave, Vin+ Vin-, has a peak bandwidth B. The second-orde
amplitude of I VD.
quantization noise
v
Voul
The modulation noise may then
Ii
Figure 7.23 shows a compariso

NS modulators. Notice that the
Figure 7.21 Fully-differential implementation of a first-order NS modulator.
Figure 7.22 shows the simulation results for the outputs of the modulator of Fig.
7.21 after being passed through two RC filters with time constants of 100 ns. Passing a
single modulator output to the decimating filter would result in an output that is half the
input signal amplitude, which can be compensated for at the output of the filter by a
shift-left operation (multiply by two). Note that the input common-mode voltage of the
op-amp remains at 0.5 V. This is important as the design of the op-amp becomes more Figure 7.23 Comparing f
challenging if the common-mode voltage is not constant. The finite op-amp
common-mode rejection ratio (CMRR) can introduce distortion into the output of the Following the procedure usee
modulator. bandwidth B results in
1.OV,---:----,-:..>-=--:---.,---,--,----,~.::.:!.;-__:-__,
O.9V
with an increase in the SNR of
D.8V
D.N
s
O.6V Every doubling in the oversam
O.5V bits increase in resolution'
0.411 oversampling, first-order NS, ;
O.3V discussed earlier, the oversamp
O.2V
7.2.1 Second...()rder Modul.
D.1V
O.OV --i-i--+--+--i---r--tj---r----j
Consider the block diagram of
0.0115 0.2115 0.4115 0.61/5 1.6115 transfer function of this modula
Figure 7.22 Outputs of the fully-differential first-order modulator after RC filtering.

. NS modulation utilizing a 7.2 Second-Order Noise-Shaping

modulator with the input
If we review Eq. (7.2), we might wonder if further filtering of the quantization noise,
[ = 0.4 pF, and C = I pF,fin
F
VQe(Z) , can result in an improvement in the data converter's SNR over an input signal
'fave, Vin+ Vin-, has a peak
bandwidth B. The second-order modulator's output shows a double differentiation of the
quantization noise
Vollt(Z) =Z-IVin(Z) + (1 - z-J)2 VQe(Z) (7.49)
The modulation noise may then be written, see Eq. (7.8), as
~1 2
INTF(f)i2 . IVQe(f) I2 = ~~f. .16sin 4 nZ (7.50)
Figure 7.23 shows a comparison between the modulation noise of first- and second-order
NS modulators. Notice that the modulation noise is "flatter" in the bandwidth of interest.
1.0n"',.--,----,="--,--,---,---"'="-~__,
O.9:,.v .......... --~ "".,'
•.••v·Seeond-order moduiatio~ no·ise..l
order NS modulator.
I.UinV
fJ.<CnV'i·"··"'·"···;·""";···
0.1nll'+···,,;··..,,·,·····,
uts of the modulator of
0.2nll'+·" +."...;
(lstants of 100 ns. Passing D.1MV ,..... ;....+.. ~""
in an output that is half the ....v+--F::=....;,....-;;O;=c.:..;--f--+--+-;..---+--i
he output of the filter by
.....
tmmon-mode voltage of First-order modulation noise
: the op-amp becomes more Figure 7.23 Comparing first- and second-order NS modulator's modulation noise.
stant. The finite
Following the procedure used earlier to calculate the RMS quantization noise m a
bandwidth B results in
(7.51 )
with an increase in the SNR of

SNRideal = 6.02N + 1.76 - 12.9 + 50 logK (7.52)
Every doubling in the oversampling ratio results in an increase in SNR of 15 dB or 2.5
bits increase in resolution! Figure 7.24 shows a comparison between simple
oversampling, first-order NS, and second-order NS-based data converters. Note that, as
'::::::r:::"'! discussed earlier, the oversampling ratio is generally greater than or equal to eight.
*
""""~J""
7.2.1 Second-Order Modulator Topology
. - ..... - ~~
----t-'
Consider the block diagram of a NS modulator shown in Fig. 7.25 (see Fig. 5.39). The
liS 1.0\1s 2.0110 transfer function of this modulator may be written as
!ulator after RC filtering. A(z) 1
1 + A(z)B(z) . Vin(Z) + 1 + A (z)B(z) . VQe(z) (7.53)
Improvement in resolution, Nine

(Bits added) / Second-order noise-shaping, M '= 2
In Vin(Z)
16.6
13.3
10.0
6.66
3.33 o
o -+·-f<iL--+--+1--+1--+1..- --i")o
10 100 lk 10k K ,Oversampling ratio
Figure 7.24 Comparing improvement in modulator resolution.
+ \--4----1 A(z)
B(z)
Figure 7.25 Block diagram ofa feedback modulator.
Comparing this equation to Eq. (7.49), we can solve for the forward and fed-back circuit
blocks, A(z) and B(z), by equating coefficients Figure'

A(z)
STF(z) == I + A (z)B(z) (7.54) modulator output. We cal
resulting in the implement:
and
The second-order (
NTF(z) = I +A(~)B(Z) = (1 )2 (7.55) implement a NS DAC (se(
directly to implementation
The results are section, is the op-amp's 0
This is more of a concen
A(z) (7.56) integrator isn't connected d
Figure 7.27a show~
and Fig. 7.51 c without changir
B(z):= 2 -Z-I (7.57) the gain, I/G1 , through tt
integrator. Notice that in F
The second-order modulator can be implemented using the topology shown in Fig. 7.26a.
comparator's gain (not sho
The output of B(z) is the sum of the modulator output and the differentiated, (l-z- 1),
we can arbitrarily changf
lixed-Signal Circuit Design Chapter 7 Noise-Shaping Data Converters 255
VQe(Z)
Comparator
lise-shaping, M 2 A(z)
~----~ r-----~
I vou/(z) Out
ing,M
B(z) :
(a)
[= 0
~ Vout(z) Out
versampling ratio 1 -z -1
or resolution.
Vout(Z) Out
In v;n(Z)
odulator.
(c)
forward and fed-back
Figure 7.26 Block diagrams of second-order modulators.
modulator output. We can redraw the block diagram in (a), as shown in Fig. 7.26b,
resulting in the implementation of a second-order NS modulator shown in Fig. 7.26c.
The second-order (de) modulator topology of Fig. 7.26c can be used directly to
implement a NS DAC (see Figs. 7.4 and 7.5). However, this topology doesn't lend itself
directly to implementation using the DAL The major concern, as discussed in the last
section, is the op-amp's output going to the power-supply rails (integrator saturation).
This is more of a concern in the second-order modulator since the output of the first
integrator isn't connected directly to a comparator.
Figure 7.27a shows how we can add an integrator gain to the block diagram of
Fig. 7.51c without changing the system's transfer function. Figure 7.27b shows pushing
the gain, 1/G1 , through the second summer so that it is directly preceding the second
integrator. Notice that in Fig. 7.27b this (the second integrator's gain) is in series with the
lpology shown in Fig. 7.26a comparator's gain (not shown; see Fig. 7.15 and the associated discussion). This means
the differentiated, (1 - Z-l) we can arbitrarily change the second integrator's gain because the comparator gain
256 CMOS Mixed-Signal Circuit Design Chapter 7 Noise-Shaping D
VQAz)
Comparator VCM
I
l~,
~2 ~l
I voU/(z)Out . C '
1 -Z-I
~ I ~.'V"qCM+
f~~
(a)
Can be selected arbitrarly because

of comparator gain (not shown). VQe(z) Figure 7.28 1m!
\ 7.2.2 Integrator Gain

As we showed in Eq. (7.21
order modulator will also l
need to discuss how to sele
noise and offsets were r
discussions, then we couic
imperfections in the swit(
practical modulator, integr
lead to modulator instabilit
_1_ Figure 7.29 shows
l-z- 1 integrator gains are set to
range. If we replace the id
the integrator outputs wi
saturation can be thought
Integrator saturation can b
(c) small integrator gain, and u
Figure 7.27 Block diagrams of second-order modulator introducing integrator gains.

1.2Y
1.W
changes to force the loop gain to unity. Figure 7.27c shows the resulting configuration
where the second integrator has the a gain of G2 and the first integrator has a gain of G1•
Also notice that we have added a delay in series with the input signal. This delay was
added to show how using a DAl results in an added delay in series with the input signal
: :~
O.TV
O,6Y
N.···:::J
O.SV
(see Fig. 2.55 and the associated discussion). The delay doesn't affect the magnitude of O.4V :. ,.' "
modulator's transfer function but rather indicates the input signal arrives half a clock O.3Y , ..... ;,
O.2V ---- .. ,
cycle later. O.lV4 •• -----;
Figure 7.28 shows the DAr implementation of the second-order modulator of Fig. o.ova·
"j.:
.JJ.W , ....
7.27c. Note how the output of the modulator is fed back and immediately passes through .JJ.2V
C,Ops O,2~
the first integrator and is applied to the second integrator (no delay as seen in Fig. 7.27c).
This is a result of switching the phases of the clock signals in the first integrator. We
should also see how the input signal sees an added half-clock cycle delay. Note that at Figure 7.29 Sho'
this point it should be straightforward to sketch the circuit implementation of the the i
fully-differential, second-order modulator (see Fig. 7.21).
VCM
l~:
~2 4>. I Vout
-I
..,..'
~ VCM
f
':~: +
'\; Vin
cause
vn). V Qe(Z) Figure 7.28 Implementation of the second-order modulator of Fig. 7.27c.
7.2.2 Integrator Gain

,-I As we showed in Eq. (7.28) for the first-order modulator, the forward gain of a second
order modulator will also be unity when the modulator is functioning properly. We now
need to discuss how to select the integrator gains to avoid hamaful integrator saturation. If
noise and offsets were not a concern, as shown in Fig. 7.17 and the associated
discussions, then we could make our integrator gains very small (ultimately limited by
imperfections in the switches such as clock feedthrough and charge injection). In a
practical modulator, integrator saturation (the integrator's gain going to zero) can also
lead to modulator instability, as shown in Eq. (7.27), and the associated discussion.
Figure 7.29 shows the integrator outputs for the modulator of Fig. 7.28 if both
.-1
integrator gains are set to OA. Notice that both outputs go outside the supply voltage
range. If we replace the ideal op-amps in the simulation with transistor-based op-amps,
the integrator outputs will saturate at some voltage within the supply range. This
saturation can be thought of as noise and ultimately limits the data converter's SNR.
Integrator saturation can be avoided by limiting the input signal range, designing with
small integrator gain, and using op-amps that have a wide output swing.
[}troducing integrator gains.
the resulting ,",V'.lUI"''''''

integrator has a gain
Iput signal. This delay
series with the input
m't affect the magnitud Supply range
signal arrives half a
immediately passes
delay as seen in Fig.
; in the first integrator.
;k cycle delay. Note that Figure 7.29 Showing integrator outputs in a second-order modulator with
:uit implementation of the integrator gains both set to 0.4.
258 CMOS Mixed-Signal Circuit Design Chapter 7 Noise-Shaping Oat:
For a more quantitative view of how the gains in a second-order NS modulator are added to determine the
affect performance, let's consider a couple of different topologies. Figure 7.30 shows the schematically. Assuming we I
block diagram of the second-order NS modulator topology of Fig. 7.25, with an integrator look at the stability and for
gain coefficient, Gp and a comparator gain, Gc ' added. Deriving the transfer function of voltages.
this linearized model with G F = G I • G c results in
(7.58)
The poles of this transfer function are located at
Zpl,pZ = (1- GF) ± J{l- GF)2 (1- Gp) (7.59)

We know that for the modulator to remain stable the poles must reside within the unit
circle. This means that our values of forward gain are restricted to
(7.60)
Figure'
Again, if the modulator is functioning properly, GF = I (because of the comparator's gain
variation as seen in Fig. 7.15 and the associated discussion). Next, consider the m
shown in Fig, 7.32. In a mOl
using the DAl. The transfer f
Vvut(Z) Out 1 +z
Figure 7.30 Block diagram of a second-order feedback modulator with gains.
We should make some observations at this point. Reviewing Eq. (7.27), we see
that the allowable range of forward gain, in the first-order modulator, is larger than the
allowable range in the second-order modulator. However, as long as the integrators don't
saturate (Gj doesn't approach zero), stability for either modulator is easy to attain. An Figure 7.32 Ger
analysis of the stability of higher-order modulators show that the range of allowable
forward gains decreases with the order of the modulator. For example, a third-order Notice that if G 1 = G~ =
modulator can have a forward gain of at most 1.15. Finally, notice that the input signal to Eq. (7.49). The poles of tt
range is more restricted for the second-order modulator, in order to avoid integrator
saturation, as seen in Fig. 7.29. We'll discuss methods to attain wider input signal range 2 GIG 2 G c G2G3
ZpJ,p2
and more robust stability criteria by adjusting the feedback gains later.
Notice that we are treating our modulator as a linear system even though it isn't When the modulator is func
linear; the comparator gain is a nonlinear variable. The linear approximation is useful in input, viiz) in (7.61), to
order to give an idea of the stability of the modulator under certain operating conditions.
Generally, a DC input is applied to the modulator in the simulation, while lowpass filters
~cond-order NS modulator are added to determine the average eomparator gain, Gc' Figure 7.31 shows this
~ies. Figure 7.30 shows the schematically. Assuming we know GJ (the gain coefficient ofthe integrators), we ean then
lig. 7.25, with an integrator look at the stability and forward gain of the modulator for varying DC input signal
ing the transfer function of voltages.
nust reside within the unit

I to
Vine Voutc
Figure 7.31 Simulating the gain of the comparator.

se of the comparator's gain
Next, consider the more generic block diagram of the second-order NS modulator
shown in Fig. 7.32. In a moment we'll discuss how to implement the feedbaek gain, G3 ,
using the DAr. The transfer function ofthis topology can be written as
vou/(z) = _ _ _G t G 2Gc '

~~~_ _---2.~~_ _~~::':"':"-'-_ _
(7.61)
1+ ·(GIG2Gc+G2G3Gc-2)+
voAz)
}-....-+-....:
Out
Ilodulator with gains.
"iewing Eq. (7.27), we

odulator, is larger than
ong as the integrators
llator is easy to attain. Figure 7.32 Generic block diagram of a second-order NS modulator.
lat the range of allowable,
'or example, a third-order Notice that if G 1 = G z G3 G c = 1 (where G 1 G2G c Gp), then this equation reduees
notice that the input signal to Eq. (7.49). The poles of this equation are loeated at
I order to avoid . '
in wider input signal 2 - GI GzG c G2G3G c ± J(2 - Gl GzG c - G zG3G c)2 -4(1- GZG3G c}
[lS later.
Zpl,p2 = 2 (7.62)
system even though it isn't, When the modulator is funetioning properly we require the (linearized) coefficient of the
approximation is useful in input, vm{z) in Eq. (7.61), to be unity
ertain operating conditions.
lation, while lowpass filters
I(z
G
Zpl )(z Zp2)
1-1 (7.63)
260 CMOS Mixed-Signal Circuit Design Chapter 7 Noise-Shaping
Again, if we set Gl ::: G2 ::: G3 ::: 1 (and Gc = 1), then the poles are located at DC, that is,
Zpl,p2 0 (7.64) Vl(Z) J:ff
Equation (7.62) is useful to estimate the modulator's stability when scaling amplitudes by ~
adjusting the integrator gain coefficients, G G2 , and G3 •
j
,
implementing Feedback Gains in the DAf

Consider the modified DAI shown in Fig. 7.33. Notice that if Cn Cn , this topology
reduces to the DAI shown in Fig. 2.54. Also note that some of the switches can be DA
combined to simplify the circuitry. Assuming that the output is connected. through the <h
switches (or that there are no switches connected to the output of the op-amp, see Eq.
[2.102]) we can write the transfer function of the integrator as
C13 I
- V2(Z)' C . -1- (7.65)
n
The block diagram of this topology is shown in Fig. 7.34a. We want to implement a block
diagram like the one shown in Fig. 7.34b. Because we have already defined
G2 = C n (7.66)
Cn DA
we define our feedback gain, G 3 , as
G3 ::: Cn (7.67)
Cn Gl Cn
Figure 7.36 shows
Cn compared with Fig. 7
power supply range.
VCM: ,
VCM
1
1
SI vow
exceeds the power su
performance in the al
followed by a compar2
Let's attempt to ge
as seen in Fig. 7.31, t
"" 13 l ~ 7.37 shows how we
~1: T ~----V2 source is used to keep

added into the general
the comparator output
Figure 7.33 Adding an additional gain setting to our DAr.
Example 7.4
Sketch the circuit implementation of a second-order NS modulator based on the
topology of Fig. 7.32, where G1 = G2 = G3 0.4. Comment on the stability of the
resulting configuration. Simulate the design and show the integrator output swing.
The block diagram of the modulator is shown in Fig. 7.35. We could dissect Eq.
(7.62) at this point to determine the transient properties of the modulator.
However, before discussing the transient characteristics of the modulator, let's
look at the integrator output swing. Figure 7.35 Impl
tlixed-Signal Circuit Design Chapter 7 Noise-Shaping Data Converters 261
, are located at DC, that is,

(7.64) ,
when scaling amplitudes by
if Cn = CI3 , this topology

me of the switches can be DAr of Fig. 7.33
is connected through the $2 (a)
put of the op-amp, see Eq.
~ - -----------,
1.._1_ I vour(z)
(7.65)
'2 1
want to implement a block
G2 = Cn
! Cn
ready defined
G3 = Cl3
Cn
(b)
Figure 7.34 Block ofaDAL
Figure 7.36 shows the output swing of the integrators. This figure should be
compared with Fig. 7.29. The output of the first integrator now falls within the
power supply range. The output of the second integrator is reduced but still
exceeds the power supply range. This, as discussed earlier, has less impact on
performance in the actual transistor-based modulator because the integrator is
followed by a comparator.
Let's attempt to get an idea for the stability of the modulator by adding LPFs,
as seen in Fig. 7.31, to the simulation (with a DC input) to measure Gc ' Figure
7.37 shows how we will implement the LPFs. The voltage-controlled voltage
source is used to keep from loading the modulator with the RC circuit when it is
added into the general simulation. In our ideal modulator shown in Fig. 7.35 both
the comparator output and integrator outputs are ideal voltage sources, so we don't
) ourDAL
modulator based on the

:ot on the stability of the
integrator output swing.
5. We could dissect Eq.
ties of the modulator.
of the modulator, let's
Figure 7.35 Implementation of a second-order modulator with feedback gain.
420mV
360mV
JOOmV
240mV
180mV
120mV
OmV
·GOmV
-120mV
·IOOmV
Gu.s lu!
Figure 7.38 Aven

ofFi~
Figure 7.36 Integrator output signals in the modulator shown in Fig. 7.35.
Using Two Delaying Integr
need the isolation (and therefore we can add the RC LPF directly into the
simulation). Consider the second-order
implemented using the cin
Figure 7.38 shows the comparator input and output, after lowpass filtering, for phases of the clocks in the
the modulator of Fig. 7.35 when the input signal is 0.1 V (DC). The average too much thought we kno\>;
comparator input voltage is roughly 0.4 V. The resulting comparator gain is then of a feedback system mo'
only 0.25. Using Eq. (7.62) to calculate the location of the poles results in mathematically. The transfc
ZpJp2 = 0.96 ·0.195. These poles are very close to the unit circle. Small shifts
in the DAI gains can result in an unstable modulator. Increasing the input signal
amplitude makes the modulator more stable. Increasing G3 also increases the
modulator's stability. The poles are located at
The simulation that generated Fig. 7.38 can be very useful in understanding
basic second-order modulator's stability criteria. Changing the simulation Zpl,p2
variables and looking at the resulting simulation outputs can be very instructional.
Note that increasing the simulation time in the netlist that generated Fig. 7.38 This equation should be COl
would reveal that the comparator input actually has small amplitude oscillations. the poles must be inside the
Also note that Fig. 7.36 shows the output of the second integrator going outside result in a modulator that h
the power supply rails with variations in the input signaL This is related to the Fig. 7.27. The extra delay'
stability of the modulator being a function of the input voltage. An input signal ratios (since the delay is t
close to VDD, for example, causes the modulator to be less stable than an input bandpass modulators exce
signal close to VCM' • quality, stability, and thus p
Out
~I ~
~ lOOpF RC» l/fs I :;
Figure 7.37 SPICE implementation of a LPF for determining comparator gain.

Figure 7.39 Secor
360mV
300mI'
2AOmV
180mI'
120mV
SOmV
OmV
-SOmV
-120mI'
-180mV'+---i--i--i---i---j--i---+--r---i---i
Ous lila 2uI Jus 4ns 5us 6us 1us Bus Sus 10us
Figure 7.38 Average comparator input and output when using the modulator
of Fig. 7.35 with an input signal of 0.1 V.
hown in Fig. 7.35.
Using Two Delaying Integrators to Implement the Second-Order Modulator

LPF directly into the
Consider the second-order modulator topology shown in Fig. 7.39. This topology can be
implemented using the circuits in either Fig. 7.28 or Fig. 7.35 by simply switching the
;!r lowpass filtering, for phases of the clocks in thc first integrator (by making both integrators delaying). Without
V (DC). The average too much thought we know that adding gratuitous delay to the forward or feedback paths
:omparator gain is then of a feedback system moves the system towards instability, however let's show this
,f the poles results in mathematically. The transfer function of this topology is
mit circle. Small shifts
'easing the input signal G 1 G2G c • Z-2 Vin (Z) + (1 z-1)2 . VQe(Z)
G3 also increases the
Vout(z) = I 2 (7.68)
l+z- ·(G2G3Gc -2)+z- ·(l-G2G3Gc+GtG2Gc)
The poles are located at
(senIi in understanding
nging the simulation 2 - G2G3G c ± J(2 G2G3G c )2 -4(1- G2G3G c + Gl G 2G c )
Zpt,p2 = 2 (7.69)
n be very instructional.
[at generated Fig. 7.38 This equation should be compared to Eq. (7.62). Remembering that for a stable modulator
amplitude oscillations. the poles must be inside the unit circle, we see that using two delaying integrators will not
ntegrator going outside result in a modulator that has as robust stability criteria as the general implementation of
. This is related to the Fig. 7.27. The extra delay won't cause instability in modulators with large oversampling
jltage. An input signal ratios (since the delay is then relatively small); however, for high-speed topologies or
;ss stable than an input bandpass modulators excess forward (or feedback) delay can significantly effect the
quality, stability, and thus performance of the modulator and therefore should be avoided.
VQe(z)
Out
Vout(Z)
RC» Ilfs Out
ing comparator gain.
Figure 7.39 Second-order NS modulator using two delaying integrators (bad).

7.2.3 Selecting Modulator (Integrator) Gains 7.3.1 Higher-Order Mo'

Before leaving this section, let's discuss the general selection of modulator gains. In We can take the theory d,
general, for good stability, the inner loop feedback gain, G3 , should be made as large as section and generalize it j
possible. For general design, set G3 = 1. This simplifies the design of the modulator and M feedback loops).
circuitry and provides good flexibility when selecting the values of G1 and G2 • If G3 1, modulator results in
then Eq. (7.62) may be rewritten to show the location of the poles as
2 ~ G] G 2 G c ~ G 2 G c ± J(2 ~ G 1G 2 G c G 2 G c )2 -4(1- G2G c )

Zpl,p2 = 2 (7.70)
The RMS noise in a band"
Keeping in mind that the reason we are not setting all gains to one is to avoid integrator
saturation, we can look at Eq. (7.70) as a guide to determine how we can reduce G 1 and
G2 • Since G2 is directly followed by the comparator, we can set its gain to 0.4 as discussed
earlier. Practically then, we can reduce the value of G1 to a very small number and still The ideal increase in the S
have a stable modulator. At the same time, using a small G1 avoids integrator saturation.
The practical problem with a small G 1, as discussed earlier, is the increase in the
SNRideal 6.0
input-referred noise. Again trade-offs must be made for given design criteria. Figure 7.40
shows the integrator outputs for the modulator of Fig. 7.39 when G1 = 0.2, G2 0.4, and
G3 1. Note that, when compared to Figs. 7.29 and 7.36, the outputs are very well or
behaved. We don't have the abnormal transitions above the power-supply rails indicating
that the modulator stability is becoming marginal with input signal values close to the
power-supply rails. The increase in resolution,
1.lY.--,.------,"-='-".--__ _ _ _ .---'-'-".--~_..,
LOY
G] 0.2
D.SY G2 0.4
This equation shows that
G3 = 1 increases by M + 0.5 bits.
D.1V -
D.SY Mih_Order Modulator TOF
n.sv
O.4V Reviewing the general N:
O.3Y forward transfer function,
0.2V
NS modulator. The transfe
D.W
O.W
-o.lV+--t---i---r--i----i---i--i---+--j---j
D.Ops O.2ps O.4ps O.6ps 0.8115 1.Ops 1.2115 1.~1i. 1.61'S 1.811S 2.0ps
Using this equation toge'
Figure 7.40 Integrator outputs for a modulator with first integrator gain of 0.2.
function of
7.3 Noise-Shaping Topologies

and a feedback filter trans:
The last section presented the fundamentals of NS data converters. It's important to
understand this fundamental material before proceeding with the topics presented in this
section.
In this section we cover (1) higher-order NS modulators, (2) NS modulators using The block diagram of an r.
multibit ADCs and DACs (multibit modulators), and (3) cascaded modulators shortly, it's impossible (i
(higher-order modulators built with a cascade of first- and/or second-order modulators). using only one delaying in
7.3.1 Higher..()rder Modulators

In of modulator gains. In We can take the theory developed for our first- and second-order modulators in the last
ihould be made as large as section and generalize it for an Mth-order modulator (a modulator having M integrators
~ design of the modulator and M feedback loops). Rewriting Eqs. (7.8) and (7.50) for the general M"'-order
.es of G1 and G2• If G3 == I, modulator results in
Ies as
(7.71)
(7.70)
The RMS noise in a bandwidth, B, can be written, see Eqs. (7.12) and (7.51), as
) one is to avoid integrator
now we can reduce G 1 and VLSB . __ 1_
VQe,RMS 0= [U. hM+ I KV+112 (7.72)
its gain to 004 as discussed "'
ery small number and still
The ideal increase in the SNR can be written as
voids integrator saturation.
er, is the increase in the
design criteria. Figure 7040 SNRideal 6.02N+ L76-2010gl~]
2M+I
+ [20M+ 10] ·logK (7.73)
len G1 0.2, G z 0.4, and
the outputs are very well . or
,wer-supply rails n'JlUl"aLHl~ SNRideal 6.02(N+ N;nc) + 1.76 (7.74)
signal values close to
The increase in resolution, Nine' is given by
-l-li (20M+ 10) .logK-2010gr

6.02 \ 2M+ I
~)'] (7.75)
This equation shows that for every doubling in the oversampling ratio, K, the resolution
increases by M + 0.5 bits.
M1h-Order Modulator Topology
Reviewing the general NS modulator topology of Fig. 7.25, we want to determine the
forward transfer function, A(z), and the feedback transfer function, B(z), for an Mth-order
NS modulator. The transfer function of a general Mth-order modulator is
(7.76)
Using this equation together with Eq. (7.53) results in a forward modulator transfer
ltegrator gain of 0.2. function of
A(z) (7.77)
and a feedback filter transfer function of

nverters. It's important to
I-(l-z-l)",
he topics presented in this B(z) 0= -1 (7.78)
Z
;, (2) NS modulators using The block diagram of an Mth-order NS modulator is shown in Fig. 7 AI. Note, as we'll see
) ) cascaded modulators shortly, it's impossible (in an analog-to-digital converter) to implement this topology
cond-order modulators). using only one delaying integrator.
266 CMOS Mixed-Signal Circuit Design Chapter 7 Noise-Shaping
1\ondelaying integrators Delaying integrator

,----,~ ~ r - - - - , ~
,----,
_1_ _1_ ••• Vout(z) The change in SNR, whe
l-z- 1 I-z-l Out filter with bandwidth, B, j
Increase in
For first-, secondo, and tl

Figure 7.41 Generic block diagram of an Mth-order 1\8 modulator. and 10.39 dB, respectivel
the SNR if we neglect th
7.3.2 Filtering the Output of an M th·Order NS Modulator in the Sine-filters respons
signal content is often Ii
Let's revisit the derivation of Eq. (7.17). This equation states that the number of Sine (reduction in the desired
stages, L, used in cascade, for near optimum removal of the modulation noise, is one using the Sine averaging j
more than the order of the modulator (L = M + I). Rewriting Eq. (7.19)
7.3.3 Implementing Hi
/,12
V~e.RMS 2 f INTF(f)12 . IvQe(f)12 . IH(f) I 2
. dl (7.79) The single-stage, higher·
directly. It is impossible t
o
where the decimation filter's transfer function is given by all but the last integratO!
modulator using two del
2(M+l)
stability criteria of a mod
-1. Krtt
sin ( )
(7.80)
of the topology shown in
[ K sin (rtf,) ] can help the situation by
the point is that impleme:
The mean-squared quantization noise is calculated by evaluating topology will result in ar
that if the modulator'S fO!
IvQ.(f)ll
~ 2(M+l) too long (because of the 1
f 2stnrt .[1-. sin (Krtt)]

,..-A---.
2 f,12 input signal instead of sut
V2 - 2· ViSB
. IJ2M
.dl (7.81)
K sin ( rt£)
Qe,RMS - 121s' 0 [ In order to help .
Is \ /, feeds the input signal fOI
or the forward gain and d
(allowing scaling of amp
the modified NS topolog:
(7.82) and feedback transfer fun,
If we let e = rtf, then we get

A(z) = l)-M ·l
2
VQe,RMS
[2
VZSB
= 121s' K
]2(M+I)
. rt . (7.83)
and
• '7- M
-A(z)B(z) = - +
(1 (
Finally, the RMS quantization noise associated with an Mth-order modulator followed by
an M + I L) Sine averaging filter is
2 JMt-lI2 M
:grator VQe,RMS = {1";:;' [ -K . IT 2 (7.84)
..; 12 m=! m
oI.i-_---.
The change in SNR, when using the Sine averaging filter decimator instead of the ideal
filter with bandwidth, B, is given by looking at the ratio ofEq. (7.72) to Eq. (7.84)
Increase in SNR = -20 log l2 M+ 1I2 • TI 2m2m-I. -'---

m=l
(7.85)
For first-, second-, and third-order modulators, the difference in the SNRs is 2.16, 6.35,
NS modulator. and 10.39 dB, respectively. This shows that using a Sinc averager, theoretically, increases
the SNR if we neglect the decrease in the desired signal amplitude because of the droop
tor in the Sine-filters response, Fig. 4.17. To avoid the droop, as discussed earlier, the desired
signal content is often limited to frequencies well below fJ2K B). When the droop
$ that the number of Sine (reduction in the desired signal amplitude) is taken under consideration, the SNR, when
e modulation noise, is one using the Sine averaging filter, is worse than the ideal filter with bandwidth B.
q. (7.19)
7.3.3 Implementing Higher-Order, Single-Stage Modulators
H(f)12 ·df The single-stage, higher-order modulator of Fig. 7.41 can be difficult to implement
directly. It is impossible to implement a higher-order modulator, when using DAIs, where
all but the last integrator are nondelaying. However, as we saw with the second-order
modulator using two delaying integrators in Fig. 7.32 and Eqs. (7.61) and (7.62), the
stability criteria of a modulator using only delaying integrators is poorer than the criteria
of the topology shown in Fig. 7.41 (where only the last integrator is delaying). While we
(7.80)
can help the situation by staggering delaying and nondelaying integrators in a modulator,
the point is that implementing a higher-order modulator without modifying our basic NS
!lg topology will result in an unstable circuit. Intuitively, we can understand this by noting
that if the modulator's forward gain is too high and the delay through the forward path is
L) ]2(M+Il too long (because of the large number of integrators), the signal fed back may add to the
input signal instead of subtracting from it.
~) ·df In order to help with the stability of a higher-order modulator a topology that
feeds the input signal forward into additional points in the modulator (thereby reducing
the forward gain and delay) and feeds the output signal back as discussed earlier
(allowing scaling of amplitudes) is needed. In order to move towards this goal, consider
l(K1f.L) the modified NS topology for higher- order modulators shown in Fig. 7.42. The forward
~..::-Is-.df and feedback transfer functions can be written as
(7.86)
M
1t·IT2;:1 (7.87)
m=1
and
-A(z)B(z)
rder modulator followed by
(7.88)
268 CMOS Mixed-Signal Circuit Design Chapter 7 Noise-Shaping Dat:
so that the feed forward coef

In over the region of interest (tl
Vin(Z) The NTF is given by
Vaut(z)
Out
or
'--~---I b l 1--------.;=""---+------------' NTF(z)
Figure 7.42 Block diagram of a modified M1h_order NS modulator.

The coefficients, b" are selec
or are positive since the feedbac
the modulator is performed .
(7.89)
using basic digital-signal pr.
Before going any further, let's explain what we are trying to do with the modified, computer program of some
higher-order, NS topology of Fig. 7.42. We know that the NTF(z), for a general specifications. One challeng€
modulator, is of the form (l-z-I)M with a shape seen in Fig. 7.43. At high frequencies harmful integrator saturation.
the modulation noise will get very large. Atfsl4, for example, the magnitude of the noise
7.3.4 Multi-Bit Modulator!
transfer function, INTF(f) I , is (fi) MCsee Fig. 1.20). For the modified NS modulator Throughout this chapter we l
we will try to reduce the modulation noise at higher frequencies by changing the shape of our quantizer in the forward j
the NTF(z). Our modified NTF(z) will be of the form modulators, as discussed eal
Feedback DAC linearity is ill
NTF(z)=LPF(z)·(l Z-I)M=LPF(z).(z z l)M HPF(z) (7.90) from the input signal. Any di
will directly affect the modl
where LPF(z) [HPF(z)] is a lowpass [highpass] filter implemented with the feedback SNR. The benefits of using a
coefficients bx ' The goal is to flatten out the higher frequency modulation noise (keep the SNR (see Eq. 7.73), better st:
noise from getting too large) thereby reducing the NTF( f) at high frequencies and developed in this chapter), fe
keeping the modulator stable. One drawback of using this technique is that the signal no drawbacks of using multibit
longer sees just a delay in its transfer function but rather it sees the lowpass response. The must be a flash converter) an
modified STF will be of the form of the modulator. The ADC
M since they are in the forward,
STF(z) =NTF(z) ·A(z) = LPF(z) . 2: aj' (z-I)H (7.91)
1=1 Simulating a Multibit NS Mo.
Figure 7.44 shows a circuit-l
INTF(f) I using a 4-bit ADC and DA(
An example shape ofa modulator. Most ofthe desig
higher-order NTF.
(1
j LPF(z)· (1- Z-I)M
design of the feedback DAC
(say l2-bits resolution or
correction, methods have be
errors appear as a random val
and not affect the SNR of the
Figure 7.46 shows 0
resistive unit elements, resis
B f VDD and ground while the
Figure 7.43 Showing the change in the NTF in a higher-order modulator.
analog output In other word
xed-Signal Circuit Design Chapter 7 Noise-Shaping Data Converters 269
so that the feed forward coefficients, ax ' can be used to help make the STF(f) constant
over the region of interest (the STF can be made to have an overall lowpass response).
The NTF is given by
I
NTF(z) = 1 +A(z)B(z) (7.92)
or
NTF(z) = M
HPF(z) (7.93)
1-(z-1)-M. L: hi' (z_I)1-1
i=l
NS modulator.
The coefficients, bx ' are selected for a highpass response. Note also that our coefficients
are positive since the feedback paths, as seen in Fig. 7.42, are subtracting. The design of
(7.89) the modulator is performed by determining the feed-forward and feedback coefficients
using basic digital-signal processing filter design (and, to keep the algebra simple, a
19 to do with the modified, computer program of some sort), then to simulate the design to see if it exceeds
le NTF(z), for a general specifications. One challenge, among others, is to meet a given SNR without causing
7.43. At high frequencies harmful integrator saturation.
the magnitude of the noise
7.3.4 Multi-Bit Modulators
Ie modified NS modulator
Throughout this chapter we have assumed N I; that is, we have used a comparator for
s by changing the shape of our quantizer in the forward path of our NS modulator. The main advantage of single-bit
modulators, as discussed earlier, is the inherent linearity of the I-bit feedback DAC.
J Feedback DAC linearity is important because the output of the DAC is directly subtracted
=HPF(z) from the input signal. Any distortion or nonlinearity (or noise) in the output of the DAC
will directly affect the modulator's performance and, ultimately, limit the modulator's
mented with the feedback SNR. The benefits of using a multibit (N > 1) quantizer in a NS modulator are increased
nodulation noise (keep the SNR (see Eq. 7.73), better stability (the modulator behaves closer to the linearized theory
) at high frequencies and developed in this chapter), fewer spectral tones, and simpler digital-decimation filter. The
mique is that the signal no drawbacks of using multibit topologies, are the increase in ADC complexity (the ADC
the lowpass response. The must be a flash converter) and the need for the DAC to be accurate to the final accuracy
of the modulator. The ADC errors, like gain errors in the integrators, are less important
since they are in the forward, high-gain path of the modulator.
Simulating a Multibit NS Modulator Using SPICE
Figure 7.44 shows a circuit-level implementation of a first-order, multibit, NS modulator
using a 4-bit ADC and DAC. Figure 7.45 shows the SPICE simulation outputs of this
An example shape of a modulator. Most of the design effort, when developing multi-bit modulators, goes into the
higher-order NTF.
j design of the feedback DAC. Because it is nearly impossible to design highly accurate
-
LPF(z)· (1 Z-I)M
(say l2-bits resolution or better) DACs without trimming, or some sort of error
correction, methods have been developed that attempt to randomize DAC errors. If the
gain at high frequnencies) errors appear as a random variable, they may appear as white noise in the output spectrum
and not affect the SNR of the data converter.
Figure 7.46 shows one possible implementation of a DAC. This DAC utilizes
resistive unit elements, resistors laid out in a square that connect, on one side, between
VDD and ground while the other side connects to a rotating switch connected to the
'-order modulator. analog output. In other words, in one case we connect VDD to one comer of the resistor
~l ~2 VREF+ == VDD
Jp ~lClk VDD
_\ ~ ~
VallI
I
f\
VCM
T
O.4p
~
In
VREF =: 0
In
Is == 100 MHz '-------' 3·bit DAC inputs
bo
Figure 7.44 Circuit implementation ofa first-order multi-bit NS modulator. bl
b2
cube and ground to the opposite corner (assuming VREF+ = VDD and VREF 0). There
exist two voltage dividers along each of the sides of the resistor square. The output of the
DAC can change from zero, to (l/8)VDD, to (2/8)VDD, ... up to (8/8)VDD. Depending on
~o
Clock
the output of the decoder, one tap from each side is fed to the analog output. Because 1,9
U
there are two sides, the outputs from each side are combined and effectively averaged.
990mV'~-,-------,:..!.:-"""-,.---,---:--........,,----,--=""T---,.---,
900mV
810mV Connected to VDD wh(
720mV .. and connected to groun
tilOmV
450mV Figure 7.46 lmpl~
7.3.5 Error Feedback

The NS topologies we've di
OmV+---~-+---r-4--~~---+-~--'-~ since the signal fed back is
o.Ops O.4ps O.Bps l.Zp. 1.6ps 2.0ps 2.4ps 2.8115 3.2p.s l.6ps 4.0p.
values of the modulator out
Figure 7.45 Output of the multi-bit modulator in Fig. 7.44. However, NS modulators VI
employing quantization," l'
feedback topology shown iI
The purpose of the counter is to vary the connections of VDD and ground around input modulators because el
the outside of the resistive divider to randomize variations in the output voltage due to We can use this topology, 1:
resistor mismatch. In order to understand this in more detail, consider a constant DAC (sometimes also called a me
output voltage of VDDI2. As the counter changes output values, so do the connections to
VDD and ground in the resistor string. In order to keep a constant output voltage of Looking at Fig. 7.4'
VDDI2 the switches in the center of the DAC move accordingly based on the output of and the output of the quant
the counter and the input to the decoder. In this way variations in the resistors, hopefully, from the input after a delay
average out to a constant value. VOU{(z) Vine,
With a little thought the reader can think of other schemes to attempt to Note that the signal transft
randomize the errors that are fed back and subtracted from the input. In all cases it's
one; that is, STF(f) = 1. F
presumed, for these techniques to work correctly, that the DAC errors average to zero or a
which results in
very small value.
1ixed-Signal Circuit Design Chapter 7 Noise-Shaping Data Converters 271
Connected to VDD when counter output is 8

VREF+ VDD and connected to ground when counter output 0
~l' .
I elk I 4-~it lOut
. . vou/
. ADC I
~ 4-bits
VREF 0
)it In
\C r-----,f----'
Analog
i-bit NS modulator. Output
VDD and VREF == 0). There

tor square. The output of the
to (8/8) VDD. Depending on
the analog output. Because Switch
md effectively averaged.
VDDbus
Ground bus
Connected to VDD when counter output is 0
and connected to ground when counter output is 8
Figure 7.46 Implementation of a DAC for use in a multi bit NS modulator.
7.3.5 Error Feedback

The NS topologies we've discussed so far are sometimes called interpolative modulators
since the signal fed back is the average of the input signal interpolated between known
values of the modulator output (the average of the modulator outputs is the input signal).
in Fig. 7.44. However, NS modulators were first introduced (see C. C. Cutler, "Transmission systems
employing quantization," 1960, U.S. Patent No. 2,927,962 [filed 1954]) using the error
1 feedback topology shown in Fig. 7.47. Error feedback topologies are not used in analog
; of VDD and ground around
input modulators because errors in the analog subtraction directly add to the input signaL
in the output voltage due to
We can use this topology, however, in the implementation of a digital input demodulator
ii, consider a constant DAC
(sometimes also called a modulator), as the subtraction is digital.
Jes, so do the connections to
I constant output voltage of Looking at Fig. 7.47 we note that by definition the difference between the input
ingly based on the output of and the output of the quantizer is the quantization noise, VQ.(z). This noise is subtracted
ns in the resistors, hopefully, from the input after a delay (for a first-order modulator) resulting in
(7.94)
her schemes to attempt to
Note that the signal transfer function for an error feedback-based modulator is simply
n the input. In all cases it's
one; that is, STF(f) 1. For a first-order NS modulator we set F( z ) == Z-l (a register),
.C errors average to zero or a .
which results in
272 CMOS Mixed-Signal Circuit Design Chapter 7 Noise-Shaping Dat
Out VOIl'(Z) Out

Nbits
Quantizer
Quantizer
Figure 7.47 Block diagram of an error feedback modulator. Figure 7.49 Show
(7.95)
A second-order modulator with a NTF(f) (I_Z-I)2 would use a feedback filter,
noticing from Eq. (7.94) that NTF(f) = 1 - F(z) , of
F(z) = 1-(1 (7.96)
Implementation of a second-order NS modulator is shown in Fig. 7.48. Note that when
trying to implement higher-order modulators using error feedback we run into the same Figure 7.5(
problem we encountered when using an interpolative modulator, namely. instability
resulting from a NTF that is too large at higher-frequencies. As with interpolative The number of bits u
modulators, we can design the NTF to have a high pass response. the maximum input signal
complement numbers, the we
word's MSB is used to incr
We'll comment more on this
In Vin(Z) VOIlI(Z) Out Figure 7.51 shows th(
if a I-bit output is used, the
filter (RCF). The I-bit DAC
Quantizer
multibit modulator and DAI
modulator order, as well as e
discussed earlier, is that the
since it is in series with the 0
Figure 7.48 Block diagram ofa second-order error feedback modulator. Interpolation fil
Digital input Digital
We've introduced the error feedback topology with the idea that it can be used in a filter
modulator (demodulator) that performs digital-to-analog conversion. We first introduced
a modulator for use in a DAC back in Fig. 7.5. At this point we need to answer the
question, "Why is the NS topology of Fig. 7.47 a better choice for DAC implementation,
in general, then the topologies of Figs. 7.5 and 7.41?" The answer to this comes from the Figure 7.
realization that the quantizer and difference block in Fig. 7.47 can be implemented by
simply removing lower bits from the digital input words. This is illustrated in Fig. 7.49. Let's look at how to
The resulting error feedback modulator will be simpler to implement than the modulators error feedback quantization
based on interpolative topologies. Figure 7.50 shows Fig. 7.47 redrawn to show the we know that
simpler implementation.
Vout(Z) Out
Nbits Out voutCz) Out
N bits N F bits vou/(z)
N-Fbits
~uantizer
Quantizer F
__ b_it_S---t:~'-)-<E----It ) /
r (
, This is implemented USing J

k modulator. Figure 7.49 Showing how the quantizer and difference block are implemented.
(7.95)
·uld use a feedback filter, Nbits Vout(Z) Out
N-Fbits
(7.96) Fbits
1 Fig. 7.48. Note that when
iback we run into the same Figure 7.50 Block diagram of an error feedback modulator.
dulator, namely, instability
:ies. As with interpolative The number of bits used in the modulator, N, is selected to avoid overflow when
se. the maximum input signal and fed-back signal are subtracted. When using two's
complement numbers, the words input to the adder must be the same length. The smaller
word's MSB is used to increase the smaller word's size until the word lengths match.
We'll comment more on this important concern in a moment.
Vout(Z) Out Figure 7.51 shows the block diagram of an NS-based DAC. As we saw in Fig. 7.4,
if a I-bit output is used, the modulator can be connected directly to the reconstruction
tilter (RCF). The I-bit DAC is perfectly linear so distortion concerns are reduced. Using a
Quantizer
multibit modulator and DAC gives a better SNR, for a given oversampling ratio and
modulator order, as well as easing the requirements placed on the RCF. The drawback, as
discussed earlier, is that the DAC must be accurate to the final desired output resolution
since it is in series with the output signal path.
'eedback modulator. Interpolation filter

Digital input Digital
~ idea that it can be used in a NS (de)modulator
filter
version. We first introduced
Jint we need to answer the
~e for DAC implementation, .
lswer to this comes from the Figure 7.51 DAC using a NS modulator and digital filter .
.47 can be implemented by
lis is illustrated in Fig. 7.49. Let's look at how to estimate the quantization noise added to the signal from the
plement than the modulators error feedback quantization process. Assuming we are using two's complement numbers
7.4 7 redrawn to show the we know that
I LSB
Nbits ,.---------A-- 7.3.6 Cascaded Modula
r~
VREF+ - VREF
0111111... == VREF+ (7.97) The NS modulators discus!
2N
loop topologies with the g
and topologies discussed in Sec
this section we discuss cas'
lOOOOOO... "" VREF (7.98)
discussed here are sometiI
For the DAC to function properly we must change the numbers back to binary offset While our focus in this sec
(complement the left-most or most-significant bit) unless the DAC input uses two's to modulators used in DAC
complement format. This is easy to see if the output of the modulator is a single bit
We indicated, in th,
(N-F 1) since an MSB of I == VREF+ and a O::!'-VREF- where VISB == VREF+ VREF-. By
to the input isn't practical il
dropping F bits the voltage weighting of an LSB in the modulator output can be written
analog subtraction, Vo.(z),
as
VQe(z) back to the input, (
(7.99) modulator. The second mO(
VLSB
own unwanted modulation
modulator, we can effectiv(
This result is used in Eq. (7.6) to estimate the quantization noise spectrum in a NS
modulator. The major benefit c
and second-order loops c
Implementation Concerns
addition, as we'll briefly di
We know from our discussions in the last chapter that most digital additions and I-bit ADC and DAC follov
subtractions utilize two's complement numbers because of the simplicity (see Sec. 4.1.3 with low oversampling rati,
and the associated discussion) in implementing the hardware. However, consider the
Second-Order (1-1) Modul,
two's complement N-bit input in Fig. 7.49. If we drop the lower F bits, the resulting
number fed back to F(z) (the quantization noise) is not in two's complement format. A second-order NS modu
modulators (called a I-I
In order to circumvent these types of problems, the topology shown in Fig. 7.52
modulator is given by
can be used. The input to the quantizer/subtractor is changed from two's complement
format into binary offset format. (See Figs. 4.4 and 4.5 for a comparison of the formats.)
Quantization is then performed; the lower bits are dropped from the output and fed back.
while the output of the sec(
The fed-back word (the quantization error) is then changed from a binary offset number
back into a two's complement number. The size of the word fed back is adjusted to match
the size of the modulator's input (knowing that the words used in two's complement
arithmetic must be the same size so that the sign bit is in the same location in each word,
see also Fig. 4.7).
In Nbits Nbits N - Fbits Vout(z)

Two's complement Binary offset Binary offset
MSB
Fbits
/
Binary offset
Adjust the output word size so that it matches the modulator's input word size.
Figure 7.52 Implementation of the quantizer and difference blocks.

Figun
[ixed-Signal Circuit Design Chapter 7 Noise-Shaping Data Converters 275
7.3.6 Cascaded Modulators

(7.97) The NS modulators discussed up to this point, in this chapter, have been single feedback
loop topologies with the general form seen in Fig. 5.38. This includes the higher-order
topologies discussed in Sec. 7.3.1 and the error-feedback topologies of the last section. In
this section we discuss cascaded or multistage NS modulators. The cascaded modulators
(7.98)
discussed here are sometimes called MultistAge noise SHaping or MASH modulators.
Ibers back to binary offset While our focus in this section is on modulators for ADCs, it is easy to extend the theory
he DAC input uses two's to modulators used in DACs.
: modulator is a single bit
We indicated, in the last section, that feeding back the quantization noise, VQe(Z) ,
'e VLSB VREF+ VREF-. By
dator output can be written to the input isn't practical in analog implementations ofNS modulators. The output of the
analog subtraction, VQe(z), would be added directly to the input signal. Instead of feeding
VQ.(z) back to the input, cascaded modulators feed it forward to the input of another
.I (7.99) modulator. The second modulator's output is then a delayed version of VQe(z) as well as its
own unwanted modulation noise. If this output is subtracted from the output of the first
n noise spectrum in a NS modulator, we can effectively reduce the resulting overall quantization noise.
The major benefit of a cascaded topology is stability. Unconditionally stable first
and second-order loops can be cascaded to implement higher-order modulators. In
addition, as we'll briefly discuss, modulators consisting of a first-stage modulator using a
nost digital additions and I-bit ADC and DAC followed by a multibit modulator can provide reasonable resolutions
e simplicity (see Sec. 4.1.3 with low oversampling ratio K.
Lfe. However, consider the
lower F bits, the reSUlting Second-Order (1-1) Modulators
; complement format. A second-order NS modulator can be implemented using a cascade of two first-order
lpology shown in Fig. 7.52 modulators (called a I-I modulator), as seen in Fig. 7.53. The output of the first
ed from two's complement modulator is given by
~omparison of the formats.) Vj(Z) Z-IVin(Z)+(l-z··l)VQel(Z) (7.100)
lm the output and fed back.
,om a binary offset number while the output of the second modulator is
:d back is adjusted to match·· V2(Z) = _Z-l VQe1 (z) + (1- z-l)VQe2(Z) (7.101)
used in two's complement
lame location in each word.
In vm(z)
N - Fbits Vout(z) .
Binary offset
Jits
ary offset
ut word size.
erence blocks.
Figure 7.53 Second-order (1-1) cascaded modulator.
276 CMOS Mixed-Signal Circuit Design Chapter 7 Noise-Shaping Data Cor
The overall modulator output is given by Third-Order (J -1-1) Modulators

Vout(z) =Z-I V1 (Z)+(I-z- 1)V2(Z) By adding a third first-order modu
or third order modulator, Fig. 7.:
= z-2 Vin (z) + Z-1 (1- Z-I)VQel (z) - z-1 (1- Z-I) V Qel (z) + (1 - Z-I)2 V Qe2(Z)
written as
(7.102) V3(Z)
Note that the second modulator is used to subtract the first's quantization noise, VQel(z), while the ideal output of the 1-1-1
from the final output. If all of the components are ideal, the resulting modulator has
second-order noise shaping. In practice, however, the coefficients of VQel(z) in Eq. (7.102) Vout(z) = VI (z) +
will not exactly cancel. When this occurs, VQel(z) is said to leak to the output of the
Again, as we saw in Eq. (7.106),
modulator. Differences in the coefficients are caused by gain errors in the first
output and spoil the overall cascad
modulator's analog integrator when compared to the output of the digital differentiator.
is large enough, we get no benl
Let's attempt to characterize the performance of the 1-1 modulator if the (7.106), that the unwanted term (
integrators have gain coefficients, Gi' other than one, as seen in Fig. 7.13. We can write expect better overall performance
the output of the first modulator's integrator in Fig. 7.53 as order. The unwanted term would f
G -1 G -1
01(Z)= I+(~IF'~I)z-1 'Vin(Z)-I+(~IF'~l)z-I' V Qe1 (z) (7.103)
Using Eq. (7.26) with this equation we can write

In Vin(Z)
(GF-GIl)'Z-1 I-(1-Gn)·z-1 )
VQelout(Z)=Vl(Z)-OI(Z)= 1 • Vin(Z) + ) 1 ·VQel(z) (7.1 04)
1 + (GF - I)z- 1 + (GF - 1 Z-
where, ideally, the output quantization noise of the first modulator, VQelou/Z) ,is VQel(z). If
the modulator is functioning properly, then GF = 1 independent of G1 as discussed earlier.
Equation (7.104) can then be written as
VQelout(Z) = (1- GIl) ·z-I . Vin(Z) + [1-(1- GIl) ·Z-I]. VQel(z) (7.105)
Z-1
Using this equation in Eq. (7.101) while assuming the second modulator uses an 1 -z -I
integrator scaling factor, Gn' and G1'2 is one results in (rewriting Eq. [7.102])
Vout(z) = z-2 Vin (z) + z-I (1 - Z-I)VQel (z) - z-1 (1 - z-I) VQelout(Z) + (1 - z-I)2 VQe2(Z)
Desired output Unwanted term
, ,
= z-2 Vin (z) + (1 - z-I)2 VQe2(Z) + [VQel (z) - Vin(Z)] . z-2(I - Z-I) . (1 - GIl)
(7.106) z
1
While we can set the second modulator's integrator gain coefficient, Gn> to 0.4 to avoid
integrator saturation, as discussed earlier, we must set GIl as close to unity as possible.
Using a unity gain coefficient results in a reduction in the modulator's overall dynamic
range (see Fig. 7.12 and the associated discussion). Note that the input signal appears in Figure 7.54 .
the unwanted term in Eq. (7.106). It should be obvious at this point that we can add
scaling parameters at various points in the modulator to attempt to maximize the
modulator's dynamic range. Also note that the number of bits in the 1-1 modulator's Third-Order (2-1) Modulators
output will be more than one bit (two bits if comparators are used in each first-order A third-order modulator formed
modulator). order modulator is shown in Fig.
vfixed-Signal Circuit Design Chapter 7 Noise-Shaping Data Converters 277
Third-Order (1-1-1) Modulators

By adding a third first-order modulator to our I-I modulator of Fig. 7.53, we get a 1-1-1
2 or third order modulator, Fig. 7.54. The output of the added third modulator can be
Qel(Z) + (l ) VQe2 (z)
written as
(7.102) V3(Z)=-z- I V Qdz)+(l Z-I)VQe3(Z) (7.107)
: quantization noise, V0.1(;), while the ideal output of the 1-1-1 cascade is given by
:he resulting modulator has
ents of VQel (::) in (7.102) vout(z) VI(Z)+ V2(Z) + V3(Z) Z-3Vin(z)+(I-z-I)3VQe3(Z) (7.1 08)
to leak to the output of the
Again, as we saw in Eq. (7.106), noise from the first modulator can leak through to the
y gain errors in the first
. the digital differentiator. output and spoil the overall cascade's SNR. Indeed, if the leakage from the first modulator
is large enough, we get no benefit from adding the third modulator. Notice, in Eq.
the 1-1 modulator if the (7.106), that the unwanted term exhibits first-order differentiation, (l-z- 1 ). We might
1 in Fig. 7.13. We can write expect better overall performance, that is, less leakage if the first modulator is second
order. The unwanted term would then exhibit second-order differentiation .
. _-I
F~ I)Z-1 . VQel(Z) (7.103)
'Il)' Z-1
-1)Z-1 . VQel(Z) (7.104) .
Ilator, VQe1a.,(z) , is Vo.1(Z). If

nt of G1 as discussed earlier.
second modulator uses an

ng Eq. [7.102])
'Qelout(Z) + (1
Unwanted tenn
(7.106)
:fficient, GI2 • to 0.4 to avoid
s close to unity as possible.
modulator's overall dynamic
It the input signal appears in

Figure 7.54 Third-order (1-1-1) cascaded modulator.
this point that we can add
) attempt to maximize the
bits in the I-I modulator's

Third-Order (2-1) Modulators
are used in each first-order
A third-order modulator formed by using a second-order modulator followed by a first
order modulator is shown in Fig. 7.55. The output of the first modulator is given by
(7.1 09)
. _.. __ .. _-------------------------
278 CMOS Mixed-Signal Circuit Design Chapter 7 Noise-Shaping Data (
When this equation is compare(

order differentiated. Also, we
modulators using the 2-1 topol
and can provide output signals·
thus dynamic range) isn't a com
One of the interesting 1
first (second-order) modulato
(first-order) modulator utilizes
topology is dominated by the
provides an enhancement in d:
interesting data converters are (
Implementing the Additional St
Before leaving our introductiOJ
Figure 7.55 Third-order (2-1) cascaded modulator. of the extra summing block m
while the output of the second modulator is shows the topology of the two ,
(7.11 0) One way to implement
The output of the 2-1 modulator is then, ideally,

vout{z) VI(Z)z··1 +(1 z-I)2 v2 (z) z-2 Vin (z)+(l-z-J/ VQdz) (7.1 II)
Let's attempt to characterize the leakage to the output by first determining the
output of the second integrator 01(Z) (the input to the comparator). We'll use the topology
shown in Fig. 7.32, with GJ = 1, to define our gains. The output, 01(Z), is (assuming that
G F G1G2Gc I)
GIGZ·Z·I Vin (Z)-[(G 1G2+G2) G2Z-1]. VQel(Z)
(7.112)
I +Z-I ·(G2G c -l)+Z-z(l-GzG c)
Figure 7.56 Showing im
Again, writing the input to the second modulator as (using Eq. [7.61])
Fig. 7.57. This DAI is a modi:
VQelout(Z)=Vl(Z) 01(Z)
integrator is related to the inpu
(l G 1G2)'Z-l vin (Z)+ Z-I)2+(G]G2+GZ)' el2
1 v OlII(Z)=OI(Z)' CF2' 1
1+Z- '(G2G c -l)
noting that if GI = G2 = Gc I then VQelout(Z) = VQel (z). If we write the output of the If we set en == em = Cn and
cascade as assuming it is clocked with t
half-clock cycle delay in sene'
with o/z) and viz), then we ca
(7.114)
then
Fignre 7.58 shows the impleilll
Desired output
----~,
We could also use the
VOUl(z) = Z-2 Vin (Z) + (1 - Z-I)3 VQe2(Z) + block of Fig. 7.56. This topole
Undesired term circuit and no matching differ
2 1(I_Z-I)2[(1 G 1G 2) . Z-l Vin(Z) + [(1 G2) (G 2Gc - G 2)Z-I]. VQel(Z) ] no longer insensitive to the
(7.115)
1 +Z-I . (G 2G c 1)+z-2(1 G2Gc) capacitor. In the parasitic insE
\I1ixed-Signal Circuit Design Chapter 7 Noise-Shaping Data Converters 279
When this equation is compared to Eq. (7.106), we see that the undesired term is second
order differentiated. Also, we have more control over the integrator gains. Third-order
modulators using the 2-\ topology are much more robust than the I-I-I-based topology
and can provide output signals free of unwanted tones. Again, if integrator saturation (and
thus dynamic range) isn't a concern, then we can set G I G2 = I .
One of the interesting uses of the 2-1 modulator is the configuration where the
first (second-order) modulator utilizes a I-bit ADC and DAC, while the second
(first-order) modulator utilizes a multibit ADC and DAC. The overall linearity of this
topology is dominated by the second-order modulator, while the multibit modulator
provides an enhancement in dynamic range for a given oversampling ratio. These very
interesting data converters are discussed in greater detail in [7].
Implementing the Additional Summing Input
Before leaving our introduction to cascaded converters, let's discuss the implementation
dulator.
of the extra summing block used to generate the quantization noise, VQ.(z). Figure 7.56
shows the topology ofthe two summing blocks and how they can be combined.
(7.110) One way to implement the extra subtracting input and the integrator is shown in
(7.111)
put by first determining the VI (z)
ator). We'll use the topology
,tput, o/z), is (assuming that I--~-- Out to integrator
'---<E---- V2(Z)
~I] 'Z~I VQel(Z)
(7.112)
'hG c )
Figure 7.56 Showing implementation of the dual summing block as a single block.
[. [7.61])
Fig. 7.57. This DAI is a modification of the DAI shown in Fig. 7.33. The output of this
integrator is related to the inputs by
.-1
VQel (z) Cn Z~112 Cn 1 Cpo
(7.1l3) VOlt'(z) OI(Z)' - . - - V2(Z)' - . - - Vl(Z)' -=-. (7.116)
c) Cn l-z~1 Cn l-z~1 Cn 1
, we write the output of the If we set Cn = Cm '" Cn and we realize that the comparator in the second modulator,
assuming it is clocked with the rising edge of <P I (or the falling of <P2), adds a
half-clock cycle delay in series with the v1(z) input and a full clock cycle delay in series
:z) + (I
with 01(Z) and v2(z), then we can write
(7.114)
Vour(Z) [0 I (z) VI(Z)-V2(Z)]' (7.117)
1
Figure 7.58 shows the implementation of a 2-1 modulator.
We could also use the topology shown in Fig. 7.59 to implement the summing
block of 7.56. This topology has the benefit of using a single capacitor for a simpler
circuit and no matching differences between C n and . Unfortunately, the topology is
Z-I] . z-I VQel (Z)]
(7.115) no longer insensitive to the parasitic capacitance on the top plate of the switched
'c) capacitor. In the parasitic insensitive topologies, Fig. 7.57 for example, the top plate of
280
<1>1
VeM
VI(Z) -~.- .............
01(Z)---
VI (z) _ _ _ _ _ _ _ _ _ _ _ _----1
Figure 7.59 1m
res
Figure 7.57 Implementing the dual summing block for a cascaded modulator. ADDITIONAL READl
[I] R. Schreier and
the capacitor is always held at the common-mode voltage, VCAr In the topology of Fig. Wiley-IEEE Pres
7.59 the top plate is charged to yJ(t) when the <1>1 switches are closed and discharged to
VeM when the <1>2 switches are closed. The difference between these voltages combined [2] S. K. Dunlap an
with the value of the unwanted parasitic capacitance to ground on the top plate causes Delta-Sigma Mo
unwanted charge to transfer to the feedback capacitor and a gain error. This by itself isn't Papers, Vol. 51,
too bad. However, the unwanted capacitance can have a large depletion capacitance [3] A. Eshraghi ane
component, resulting in a voltage-dependent capacitance and thus nonlinear gain. ADC Architectu
Nevertheless, in some applications this topology may still prove useful. Theory and Appi
[4] S. R. Norswort
Converters: ThE
978-078031045:
VI (z) R. T. Baird and
[5]
Converters usinl
Systems II: Anal
December 1995
[6] J. C. Candy and

Wiley-IEEE Pre
[7] B. P. Brandt an
12-b 2-MHz AI
12, pp. 1746 - I
QUESTIONS
7.1 Show how to d{
7.2 After re\'iewin~

seen in Fig. 7.2
Figure 7.58 Implementation ofa 2-1 NS modulator. the modulator?
7.3 Using SPICE s
through an RC
help to recove
signal's amplitt
..fixed-Signal Circuit Design Chapter 7 Noise-Shaping Data Converters 281
Vt(Z) - - -
Ot (z)
+
Figure 7.59 Implementing the dual summing block with a single capacitor
results in sensitivity to the top plate parasitic capacitance.
1 cascaded modulator. ADDITIONAL READING

[1] R. Schreier and O. C. Temes, Understanding Delta-Sigma Data Converters,
In the topology of Fig.
Wiley-IEEE Press, 2005. ISBN 978-0471465850
re closed and discharged to
~n these voltages combined [2] S. K. Dunlap and T.S. Fiez, "A Noise-Shaped Switching Power Supply using a
md on the top plate causes Delta-Sigma Modulator," IEEE Transactions on Circuits and Systems 1: Regular
ain error. This by itself isn't Papers, Vol. 51, No.6, pp. 1051 - 1061, June 2004
large depletion capacitance
[3] A. Eshraghi and T.S. Fiez, "A Comparative Analysis of Parallel Delta-Sigma
and thus nonlinear gain.
ADC Architectures," IEEE Transactions on Circuits and Systems 1: Fundamental
re useful.
Theory and Applications, Vol. 51, No.3, pp. 450 458, March 2004
[4] S. R. Norsworthy, R. Schreier, and O. C. Temes (eds.), Delta-Sigma Data
Converters: Theory, Design, and Simulation, Wiley-IEEE Press, 1997. ISBN
978-0780310452
[5] R. T. Baird and T. S. Fiez, "Linearity Enhancement of Multibit ~L AJD and DIA
Converters using Data Weighted Averaging," IEEE Transactions on Circuits and
Systems 11: Analog and Digital Signal Processing, Vol. 42, No. 12, pp. 753 - 762,
December 1995
[6] 1. C. Candy and O. C. Temes (eds.), Oversampling Delta-Sigma Data Converters,
[7] B. P. Brandt and B. A. Wooley, A 50-MHz Multibit Sigma-Delta Modulator for
12-b 2-MHz AJD Conversion," IEEE Journal o/Solid-State Circuits, Vol. 26, No.
12, pp. 1746 1756, December 1991
QUESTIONS
7.1 Show how to derive Eqs. (7.1) and (7.2) from the block diagram seen in Fig. 7.1.
7.2 After reviewing Sec. 2.2.3, would it be possible to replace the delaying integrator
seen in 7.2 with a non-delaying integrator? If so, what is the NTF and STF of
Jduiator. the modulator? Is the modulator stable?
7.3 Using SPICE simulations, show how passing the digital signal seen in Fig. 7.3
through an RC lowpass filter will reduce the modulation noise in the signal and
help to recover the original analog input signal. What happens to the original
signal's amplitude if it's filtered, by the added RC filter, too much?
282
7.4 Show the spectrums (modulator input, digital output, and analog output after
7.25 In your own words, h
filtering) of the signals in question 7.3. Discuss what the spectrums indicate.
the effects of a jittery
7.5 If an extra delay, Z~l, was added to the forward path of the modulator in Fig. 7.2
7.26 Determine the transfe
would the resulting topology be stable? Why or why not?
7.27 Derive Eq. (7.51).
7.6 Show, using timing diagrams, how Eq. (7.3) is correct.
7.28 Sketch the implement
7.7 For the NS modulator shown in Fig. 7.5 used for digital to analog conversion,
7.29 Derive Eq. (7.61)
what component serves as the ADC? What component serves as the DAC?
7.30 Sketch the fully-diffel
7.8 Explain how the quantizer in Fig. 7.5 functions.
7.31 Resimulate the modu
7.9 What are we assuming about an input signal if the modulation noise follows Eq.
stability of the resultil
(7.5)?
7.32 Resimulate the modu
7.10 What is the magnitude ofEq. (7.5) (plot it against frequency)?

stability of the resulti:
7.11 What is the difference between quantization noise and modulation noise?
7.33 Regenerate Fig. 7.40
7.12 Show the steps and assumptions leading to Eq. (7.12).

swing of any op-amp
7.13 Is the statement on page 238 that "every doubling in the oversampling ratio results
7.34 Comment, in your (
in 1.5 bits increase in resolution" really true if K is small? Explain.

converter can be won
7.14 Does noise-shaping work for DC input signals? If so, how?

7.35 Derive Eq. (7.75). M:
7.15 Show the steps leading up to Eq. (7.22).

7.36 Resimulate Fig. 7.44
7.16 What is the difference between a NS ADC and a Nyquist ADC?

7.37 Sketch a possible im]
shown in Fig. 7.48.
7.17 In your own words, describe ripple in the output of a digital filter connected to an
NS modulator.
7.38 What transfer functio
7.18 Does adding a dither signal to the input of a NS modulator help reduce the
peak-to-peak ripple in the digital filter output? Does it help to break up tones in
the filter's output?
7.19 Derive Eq. (7.26).
X(z)
7.20 Repeat Ex. 7.3 if the integrator's gain is set to 0.5.
7.21 Estimate the range of Gc for the quantizer seen in Fig. 7.16. How does this
compare to the range of G, for the I-bit quantizer seen in Fig. 7.15? Name two
F
benefits of the I-bit quantizer over multi-bit quantizers.
7.39 In Fig. 7.54 sketch tl
7.22 Verify that Eq. 7.30 is correct. Use pictures if needed.

the Y:(z) output.
7.23 In your own words, and without equations, describe integrator leakage. How
7.40 Derive the transfer n
would you relate integrator leakage, found in integrators that use an active
derivation). What is
element as seen in the NS modulators found in this chapter, to the passive

concern when not u
integrators used in the NS modulators discussed in the last chapter?

common-mode of T,
7.24 Would large parasitic op-amp input capacitance affect the settling time of a DAI?
circuit's output (relm
Verify your answer using simulations with ideal op-amps (infinite open-loop gain)
good idea, now that
and non-ideal op-amps (open-loop gains around the oversampling ratio, K).
are tied to ground or
plates of the capacitc
, and analog output after 7.25 In your own words, how does oversampling affect input-referred offset/noise and
: spectrums indicate . the effects of a jittery clock on an NS data converter?
. the modulator in Fig. 7.2 7.26 Determine the transfer function of the DAr shown in 7.20 .
.?
7.27 Derive Eq. (7.51).
7.28 Sketch the implementation of the full-differential second-order NS modulator.
;ital to analog conversion,
7.29 Derive Eq. (7.61)
:erves as the DAC?
7.30 Sketch the fully-differential equivalent of Fig. 7.33.
7.31 Resimulate the modulator in Ex. 7.4 if the gains are set to one. Comment on the
dulation noise follows Eq.
stability of the resulting circuit.
7.32 Resimulate the modulator in Ex. 7.4 if the input is only 50 mY. Comment on the
ency)?
stability of the resulting circuit.
flOdulation noise?
7.33 Regenerate Fig. 7.40 by selecting integrator gains so that the maximum output
swing of any op-amp is 800 m V peak-to-peak.
oversampling ratio results 7.34 Comment, in your own words, on why the actual SNR of a NS-based data
I? Explain. converter can be worse than the ideal values calculated in the chapter.
)w? 7.35 Derive Eq. (7.75). Make sure each step of the derivation includes comments.
7.36 Resimulate Fig. 7.44 using two-bit ADC and DAC.
;tADC? 7.37 Sketch a possible implementation of a quantizer for the crror feedback modulator
shown in Fig. 7.48.
gital filter connected to an
7.38 What transfer function does the following block diagram implement?
10dulator help reduce the
help to break up tones in
shift left
X(z) Y(z)
Fig. 7.16. How does this

n in Fig. 7.15? Name two
Figure 7.60 Circuit for question 7.38.
7.39 In Fig. 7.54 sketch the block diagram implementation of the circuit in series with
the Yiz) output.
integrator leakage. How
7.40 Derive the transfer function of the topology seen in Fig. 7.61 (show details of your
[ators that use an active
derivation). What is the input common-mode voltage of the op-amp? Is this a
.s chapter, to the passive
concern when not using a negative supply voltage? If the input signals have a
ast chapter?
common-mode of VDDI2, does this affect the common-mode voltage of the
:he settling time of a DAl? circuit's output (remember that the op-amp is part of an integrator). Would it be a
)s (infinite open-loop gain) good idea, now that the inputs of the op-amp and the top plates of the capacitors
rsampling ratio, K). are tied to ground or the virtual ground of the op-amp, to swap the bottom and top
plates of the capacitors? Why or why not? Use SPICE to support your answers.
284 CMOS Mixed-Signal Cireuit Design
Bandpass
Figure 7.61 Circuit used in question 7.40.
7.41 Repeat question 7.40 for the op-amp circuit seen in Fig. 7.62.
The data converter topologif

<PI <P2 analog-to-digital conversion
. frequency, B. These topolog
V1(Z) ~ chapter we dcvelop the idea
I VOUf(Z) frequencies that doesn't inclu
01(Z) ~ T ~ +
bandpass data converters. Bal
especially wireless commun'
higher frequency and thus cO!
V2(Z)
Before developing tht
Figure 7.62 Circuit used in question 7.41. through 6, why in-phase (J
systems. tn simple terms, II!
without increasing the band,
that use several phase-shifte
employed to further increase
bandwidth. In this chapter, )
(JIQ) sinewaves.
As seen in Fig. 1.6 an
signal. 8.1 shows time
I1Q signal). The phase shift (
lagging the J component by 4
varying the amplitude of eit)
amplitude of the JiQ signal
information we are transmi
quadrature amplitude modul,
In order to recover th
let's first write, see Eq. (1.10:
where fc represents the fre(

information we are transmil
fixed-Signal Circuit Design
Chapter
8
Bandpass Data Converters
.40.
;.7.62.
The data converter topologies we've covered in the last few chapters have performed
analog-to-digital conversion on a range of frequencies extending from DC to some
frequency, B. These topologies are sometimes called lowpass data converters. In this
chapter we develop the idea that we can perform data conversion on a bandwidth of
frequencies that doesn't include DC. The topologies developed in this chapter are called
bandpass data converters. Bandpass data converters are useful in communication circuits,
+ especially wireless communications, where the information is modulated up to some
higher frequency and thus contained in some fixed bandwidth in the frequency spectrum.
Before developing the idea of a bandpass data converter, let's review, on pages 4
41. through 6, why in-phase (1) and quadrature (Q) signals are used in communication
systems. In simple terms, IIQ signals are used because we can send more information
without increasing the bandwidth of the transmission channel. Note that other schemes
that use several phase-shifted sinewaves (e.g., 0, 30, 60, and 90 degrees) may also be
employed to further increase the information transmitted without increasing the channel
bandwidth. In this chapter, however, we focus only on 0 and 90 degree phase-shifted
(IIQ) sinewaves.
As seen in Fig. 1.6 and Eq. (1.11), summing I and Q components results in the I1Q
signal. Figure 8.1 shows time-domain, equal amplitude, I and Q signals and their sum (the
I1Q signal). The phase shift of the I1Q signal leads the Q component by 45 degrees while
lagging the I component by 45 degrees when equal amplitude I and Q signals are used. By
varying the amplitude of either (or both) the I or Q signals we vary the phase shift and
amplitude of the IIQ signal (this variation in amplitude and phase shift represent the
information we are transmitting). Note that this modulation scheme is often called
quadrature amplitude modulation (QAA-1).
In order to recover the information from the I and Q components in the IIQ signal
let's first write, see Eq. (1.10),
SIQ(t) =At· cos2rr.j~ . t+AQ' sin2rr.j~· t (8.1)
where j; represents the frequency of a carrier signal while AI and AQ represent the
information we are transmitting. Both AI and AQ vary with time and thus have some
-~~------~-----------------------------
286 CMOS Mixed-Signal Circuit Design Chapter 8 Bandpass Data ConveJ
8.1 Continuous-Time Be
aOOml"..,-~--~-==':'-----~--=':~'------,----,-'--"-.,------.
I/Q
100mV When we developed the (Iowpa:
.OOmV
SOOml'
used a capacitor to sum (sigma)
400mV .- .. .
300mI' .... . I
signals. The result was an abser
200mI'
Q DC where the impedance of the
100mV
Oml'
modulator let's replaee the cap

-100mI'
Following the same reasoning,
-200mI'
noise at the resonant freque

~400mV
-SOOml'
fo 1I2n!IC .
-60DmV
-700mY
8.1.1 Passive-Component B
On$ Figure 8.2a shows the impleme
modulator using this approach.
Figure 8.1 In-phase (I), quadrature (Q) signals, and IJQ signals. use Fig. 8.2b. We ean write
topologies)
spectral representation, AI(!) and AQ(f). The AI component amplitude modulates the
cosine term while the AQ component amplitude modulates the sine term.
In order to recover the AI and AQ in the receiver we can multiply the received
signal, ideally a sealed version of SIQ(t) , by cosine and sine signals. For Ai' and
SIQ(t). cos2nfc' t (AI' cos2nfc' t+AQ' sin2nfc' t)· cos2nfc' t (8.2)

Knowing
eosA . sin B ~(sin [8 - A] +sin [A + BD (8.3)
cosA . eosB ~(eos [B A] + cos [A + BD (8.4)

we get
AI(f) AQ
S'Q(t) . cos 2nfc . t:= - - + 2 . cos 2n2fc . t + - . sin 2n2fc . t (8.5)
Desired signal Remove by passing through a lowpass filter
(a) Circuit
The AI component can be recovered by passing this signal through a lowpass filter to
remove the higher frequency components. Note that it's assumed the maximum frequency
of interest in AI(f) is less than h.
"\lin - Villt
In order to recover AQ from the received signal we multiply by a sinewave or
S'Q(t)· sin2nfc' t (AI' cos27T.fc· t+AQ' sin2nfc' t)· sin2nfc· t (8.6)
Knowing R
sinA . sinB:= t(eos [B -AJ + cos (A + BD (8.7)

we get
. AQ(f) A
S/Q(t). sm2nfc - t= --2- + 2 . eos2n2fc· t+ 2' . sin2n2fc' t (8.8)
'----,~
Desired signal Remove by passing through a lowpass filler

Figure 8.
We'll use these results later in the chapter in Sec. 8.2.4.
ixed-Signal Circuit Design Chapter 8 Bandpass Data Converters 287
8.1 Continuous-Time Bandpass Noise-Shaping

When we developed the (lowpass) passive noise-shaping modulator back in Sec. 6.1 we
used a capacitor to sum (sigma) the difference (delta) between the input and the fed back
signals. The result was an absence of noise in the modulator's output signal, Fig. 6.5, at
DC where the impedance of the capacitor is infinite. In order to implement a bandpass
modulator let's replace the capacitor in Fig. 6.4 with an LC tank circuit, Fig. 3.39.
Following the same reasoning, the output of our bandpass modulator should have no
noise at the resonant frequency of the tank where its impedance is infmite,
10 1I2nffC.
8.1.1 Passive-Component Bandpass Modulators
Figure 8.2a shows the implementation of a passive-component bandpass noise-shaping
modulator using this approach. To determine the transfer function of this topology let's
j I/Q signals.
use Fig. 8.2b. We can write (following what we did in Sec. 6.1 for the lowpass
topologies)
It amplitude modulates the
,ine term.
(
Vin - Vinl + -VOIII - Vint). sL + V (I) == v (8.9)
R R l+s2LC Qe olll
can multiply the received
:nals. For AI' and
)052rr/c . t (8.2) (8.10)
[A +B]) (8.3)
5[A +B]) (8.4)
sin2n2[c' t (8.5)
lowpass filter
(a) Circuit implementation of a bandpass modulator.
through a lowpass filter to
ed the maximum frequency
VQe(f)
:iply by a sinewave or Vin - Vinl
fc . t)· sin2nJc . t (8.6) r-_._-VOUI
[A + BD (8.7)
sin2n2[c' t (8.8)
(b) B lock diagram
>wpass filter
Figure 8.2 A bandpass passive NS modulator.

288 CMOS Mixed-Signal Circuit Design Chapter 8 Bandpass Data Conve
or
I +s2LC
vOU! = vm . - - : - ' . ' . - - + VQe(f)· - Vin!' - - - - - - ' ' - - - (8.11 )
+s2LC 1 +s~+s2LC 1 +s~+s2LC
and tinally (see Fig. 3.39 and then Eq. [6.12] for the analogy with the lowpass passive
modulator)
(8.12)
Extra noise/distortIon term
The STF shows a bandpass response while the NTF shows a band reject response, Fig.
8.3. Like the lowpass modulator we have the extra noise/distortion term that causes the Figure 8.4 Simulati,
modulator to deviate from the ideal behavior. We know, at this point, that we can drive
V in , to zero by using an active element (amplifier). This is discussed in the next section.
Figure 8.3 Modulation noise spectral density for a bandpass modulator. ·140dB+----i-
20.0MHz 21.4MHz 2
Example 8.1
Figure 8.5 SPI
Simulate the operation of the NS modulator seen in Fig. 8.2 when R is lk, Cis 10
pF, L is 4.06 I-LH, and the clocking frequency is 100 MHz. Comment on the An Important Note
resulting simulation results and the operationllimitations of the circuit.
Notice that the value of the indm
The conversion is centered around, from Fig. 8.3, 25 MHz. What this means is if modulator. If one understands th
our input signal is a sinew ave at 25 MHz we should be able recover an exact replaced with an active circuit, I
replica of this input after removing the modulation noise. If a DC signal is applied of frequencies (the range we w,
to the modulator we should get out no signal (actually the modulator should representation).
output a sequence, like 101010101 that averages to VCM or, for a mixed-signal
system, no signal). 8.1.2 Active-Component Bal
Figure 8.4 shows the simulation results. Note the ripple in the output, after To remove the extra noise/distor
filtering, amplitude. This variation can be removed by more filtering (increasing 6.2.4, an active circuit. Figure
the Q of the simple filter used in the simulation by increasing the resistor) to variation in vim is zero when tht
remove noise. It is useful, when learning, to vary the input frequency in the this topology as
simulation and look at how the output of the modulator changes (keeping in mind
the frequency response, Fig. 3.39, of the LC tank circuit). Finally, Fig. 8.5 shows
the spectrum of the modulator's output when a 25 MHz input tone is applied.
Again, as in the passive noise-shaping lowpass topology, the extra, unwanted,
term in (8.12) limits the SNR. •
\1ixed-Signal Circuit Design Chapter 8 Bandpass Data Converters 289
After filtering modulator output.

2sf:. Notice amplitude variations. This
71 • _ _--'8"--_
(8.11) is a ripple just like we had in the
I + sf:.
8
+s2LC lowpass modulators with a DC
input (and can be removed with
?;y with the lowpass passive more filtering, higher Q).
Modulator output
(8.12)
Input signal
a band reject response, Fig.

;tonion tenn that causes the Figure 8.4 Simulation results for the modulator discussed in Ex. 8.1.
this point, that we can drive
ussed in the next section .
.t the resonant frquency.
>
f
mdpass modulator.
:.2 whenR is lk, Cis 10 Figure 8.5 Spectrum of the modulator's output in Ex. 8.1.
MHz. Comment on the An Important Note
If the circuit.
Notice that the value of the inductor we used in Ex. 8.1 is too big to be integrated with the
'z. What this means is if modulator. If one understands the concepts in this section we see that the LC tank can be
e able recover an exact replaced with an active circuit, like a gm-C filter, that has a high-impedance over a range
If a DC signal is applied of frequencies (the range we want to convert from an analog representation to a digital
'I the modulator should
representation).
lor, for a mixed-signal
8.1.2 Active-Component Bandpass Modulators
}ple in the output, after To remove the extra noise/distortion tenn in Eq. (8.12) we can use, as we did back in Sec.
lore filtering (increasing 6.2.4, an active circuit. Figure 8.6 shows one such implementation. Noting that the
~reasing the resistor) to variation in V inl is zero when the op-amp's gain is infinite we can rewrite Eq. (8.12) for
input frequency in the this topology as
langes (keeping in mind STflf) lvTF(f)
Finally, Fig. 8.5 shows
l input tone is applied. --~-
Vout ,VQe(f) (8.13)
y, the extra, unwanted,
290 CMOS Mixed-Signal Circuit Design Chapter 8 Bandpass Data C
vln-;-_ _ _ _- J
Analog
R
R
~ I :
ADC (comparator)
+ Digital
R~~
Vinl
V out
VCM +
Op-amp j,
I
DAC
-Vout
Figure 8.6 An active-integrator bandpass NS modulator. Figure 8.
Simulations demonstrating the operation of this topology are found at CMOSedu.com. 8.1.3 Modulators for C(
/
Signal-to-Noise Ratio One area, at tlk time of thi

use of bandpass data cor
The output ofthe bandpass modulator can be passed through a bandpass filter, Sec. 4.2.3, communications. Currenf
with a bandwidth 2B to remove the modulation noise, Fig. 8.7. The smaller B, the lower centered around some carr
the noise in the final digital output word and the larger the SNR. Again, the trade-off with is performed using a mt
using smaller filter bandwidth is that the allowable input signal frequency range shIinks. multiplier) with both conti
Let's use the results in Sec. 6.1.1 (or Sec. 7.1.2) to help with our SNR estimate for mixing we can go dire(
here. When we compare Fig. 6.8 (which doesn't show the noise power contributed from its output is digital, and i
the negative components of the frequency spectrum) to Fig. 8.7, we see exactly the same modulator design at high
shape (note that for large Q, as used in Ex. 8.1, this isn't true). Therefore we can use the forward and feedback pat
equations derived earlier for the lowpass modulators to cstimate the SNR in the bandpass topology seen in Fig. 8.2
topologies. Notice that iflo is 25 MHz and B is 100 kHz then the oversampling ratio, K, is required in an RF circuit th
125. Figure 8.9 shows a
Notice that the bandpass modulator seen in Fig. 8.6 has a second-order response, modulator in Fig. 8.2. The
two poles in the NTF, so it's called a second-order bandpass modulator (even though its used to provide gain and i
SNR is similar to a first-order lowpass response). A fourth-order bandpass modulator, receiver is dominated by tl
Fig. 8.8 (again see simulations at CMOSedu.com), has behavior (an SNR) similar to the current, g m Vin (this is the i
second-order noise shaping topology discussed in Secs. 6.2.4 and 7.2. must, on average, equal tt
digital voltage value, can
(which is equal, on avera~
Bandpass filter !VQe!2 'INTFI 2 , V 2 /Hz output goes low). Derivin;
fo response ~
'\ current, iin gmvin. output
show that we don't get an e
Input signal employ K-path sampling, I
B modulator's forward delay.
2K fo fo+B f adequate oversampling ra1
addition, it's used to ensur
fo-B
6.24) when combininl
course we can combine thl:
Figure 8.7 Filtering out modulation noise to calculate SNR. discussed in Sec. 4.2.3, r
implementations of these t(
1ixed-Signal Circuit Design Chapter 8 Bandpass Data Converters 291
L L
R
ADC (comparator) vin----N, --.-_, I \ I \ I
CMf>f,
-vr I
igital
Vout >--+-V:...;2'--i +
VCM +
f, VCM
lOdulalOL Figure 8.8 Fom1:h-order bandpass noise-shaping modulator.
'ound at CYIOSedu.com. 8.1.3 Modulators for Conversion at Radio Frequencies

One area, at the time of this writing, that still has substantial room for development is the
use of bandpass data converters for wireless (narrowband or radio frequency [RF])
a bandpass filter, Sec. 4.2.3, communications. Currently mixing (down converting the transmitted information
.7. The smaller B, the lower centered around some carrier frequency) into an intermediate frequency (or to baseband)
fR. Again, the trade-off with is performed using a multiplier. A multiplier is an analog circuit (e.g., a Gilbert
II frequency range shrinks. multiplier) with both continuous-time inputs and output. By using a bandpass converter
belp with our SNR estimate for mixing we can go directly to digital format (the bandpass converter's input is analog,
)ise power contributed from its output is digital, and it is clocked with a local oscillator). The key to a successful
~.7, we see exactly the same
modulator design at high operating frequencies is minimizing the delay in both the
:). Therefore we can use the forward and feedback paths of the converter (to ensure a stable converter). Thus the
.ate the SNR in the bandpass topology seen in Fig. 8.2 is more likely to be successful at the high conversion rates
the oversampling ratio, K, is required in an RF circuit than the topologies seen in Figs. 8.6 and 8.8.
Figure 8.9 shows a topology built from the concepts used in the simple passive
las a second-order response, modulator in Fig. 8.2. The low-noise amplifier (LNA) isn't part of the modulator and is
, modulator (even though its used to provide gain and isolation for the RF input signal (the noise performance of the
-order bandpass modulator, receiver is dominated by the perfonnance of this first stage). The output of the LNA is a
vior (an SNR) similar to the current, gm Vin (this is the input to the modulator). A portion of the current fed back, I flJ ,
and 7.2. must, on average, equal this input current. The output of the modulator, even though a
digital voltage value, can be thought of as the current fed back, iout, to the resonator
(which is equal, on average, to N ·hB where N is the number of times the comparator
output goes low). Deriving the STF and NTF, similar to (8.12) (but with an input
current, iin =gmVin, output current, io"" and quantization noise current, IQe(f)) would
show that we don't get an extra noise/distortion term. Note that increases in the SNR must
signal employ K-path sampling, Fig. 6.24, rather than topologies that result in an increase in the
modulator's forward delay. The use of K-path sampling is also required to ensure that an
f adequate oversampling ratio can be achieved when the carrier frequency is large. In
addition, it's used to ensure the inherent lowpass filtering we get (the path filter seen in
6.24) when combining the comparator's outputs doesn't affect the desired signal (of
course we can combine the comparator outputs so that they have a bandpass response, as
culate SNR. discussed in Sec. 4.2.3, rather than a lowpass Sine response). We leave the detailed
implementations of these topologies to the refereed literature.
292 CMOS Mixed-Signal Circuit Design Chapter 8 Bandpass Data C(
Must be capable of supplying current.

~I
~ Vbiasn ,
VC_M_~
Antenna VI(Z) ~
L
V2(Z),_ _ _ _ _ _ __
ADC
L -_ _ _ _~~------~+
>---<>---- Digital
LNA is VI (z)
VOUI(Z) = ---
Figure 8.9 Design of a bandpass modulator for data conversion at RF.
Figure 8.10 Im]:

8.2 Switched-Capacitor Bandpass Noise-Shaping
In Sec. 4.2.3 we discussed the idea that we can implement a Sinc-shaped averaging
or an i s l2 resonator (the pc
bandpass filter centered aroundj)4 (oris 16) having a transfer function, Eq. (4.25), of
we'll need to use two delaY5
1 -K any reasonable level of prec
H(z) =~ (8.14)
1 +Z-2
In order to imp1eme
Comparing this equation to the equation for the equivalent lowpass averaging filter, Eq. in parallel (see Eq. [2.56]
(4.10), we see that transforming our lowpass modulator topologies into bandpass switch the phases of the de
modulator topologies with bandpass responses centered atisl4 can be accomplished by resonators in Fig. 8.10 con
word rate is 100 MHz (the
Substituting Z-2 for -Z-I (8.15)
high). Reviewing Eq. (2.56:
The discrete-analog integrator (DAI) discussed in Sec. 2.2.3 is the basic building block
used in lowpass, switched-capacitor, modulator implementations. In order to implement a
bandpass modulator at is 14 we need to replace the DAI used in the lowpass topologies
with an isl4 resonator, an analog implementation of Fig. 4.23, or or our desired.l /4 resonat,
delayed by a full clock cycl
Rep Iace 1
-----I
.h
Wit 1
-----2 (8.16)
l-z- 1 +z see that this delay means
fourth-order modulator) us
or, when we can't avoid a delay in the implementation of the building block, since we also couldn't des
z-I . Z-I non-delaying DAIs.
Replace -----I with -----2 (8.17)
1-z- 1 +z
Example 8.2
8.2.1 Switched-Capacitor Resonators Simulate the operatior
In order to move towards implementing a switched-capacitor is 14 resonator, consider the C1 = CF = 1 pF. Comm
circuit in Fig. 8.10. The top portion of the circuit is simply the DAI discussed in Sec. using a SPICE simu1atil
2.2.3 (Fig. 2.54). The bottom portion provides the positive feedback needed for the The pole of the resonat,
addition (instead of subtraction) of the delayed output. The transfer function of this circuit frequency offs/2). We I
IS
stable its poles must lit
to oscillate (become un:
(8.18)
vfixed-Signal Circuit Design Chapter 8 Bandpass Data Converters 293
VeM
~c
>---'0--- Digital
" - - - - - - - - - - - - - - - - < - 1 r-------.J
I conversion at RF.
Figure S.lO Implementing anls12 resonator for use in a bandpass modulator.

aping
~nt a Sinc-shaped averaging
or an /,/2 resonator (the pole is located atfsI2). In order to implement an 1s14 resonator
: function, Eq. (4.25), of
we'll need to use two delays in the feedback path. Implementing two (analog) delays, with
(8.14) any reasonable level of precision, in the feedback path is challenging.
In order to implement an 1s14 resonator, we'll take two 1s12 resonators, put them
lowpass averaging filter, Eq. in parallel (see Eq. [2.56] in the K-path sampling discussion found in Sec. 2.1.6), and
Ir topologies into bandpass switch the phases of the clocks in each topology. So, for example, if we clock two of the
4 can be accomplished by resonators in Fig. 8.10 connected in parallel (see Fig. 2.37) at 50 MHz then the output
-1
(8.15) word rate is 100 MHz (the output of the topology changes each time either ~I or ~2 goes
high). Reviewing Eq. (2.56) for two paths, Z --7 Z2 , we can then re-write Eq. (8.18) as
3 is the basic building block
ions. In order to implement a (8.19)
ed in the lowpass topologies
3, or or our desiredfs 14 resonator transfer function. Note that in this equation the VI input is
_1_
delayed by a full clock cycle (see Fig. 2.55 to see how this is modeled for the DAI). We'll
+Z-2 see that this delay means that we can't design a two stage bandpass modulator (a
fourth-order modulator) using two non-delaying resonators. This shouldn't be a surprise
building block, since we also couldn't design a second-order lowpass modulator, Fig. 7.27c, with two
non-delaying DAIs.
(8.17)
Example 8.2
Simulate the operation of the resonator in Fig. 8.10, clocked at 50 MHz, if
)r fs 14 resonator, consider the . C 1 = CF = 1 pF. Comment on the stability of the resonator. Verify your comments
ly the DAI discussed in Sec. using a SPICE simulation.
lve feedback needed for the The pole of the resonator is located at z -I, right on the unit circle (located at a
ransfer function of this circuit frequency offs/2). We know, from Sec. 4.3.1, that for a discrete-time circuit to be
stable its poles must lie inside the unit circle. We, therefore, expeet the resonator
to oscillate (become unstable), Fig. 8.11. •
(8.18)
294 CMOS Mixed-Signal Circuit Design Chapter 8 Bandpass Data Conve
20V'--,-_ _--,-:v-'-'(v.::..:ou'-'-I]__ _ _ _-'-'V1v.:c.in:;,:s-"'p]...:.-V"-lv"'-ins::..::m2 ] - - - ,

Output
16V ·······(····t······~······: ···;······T·······;········: or, assuming G 1 G c = 1 (as discl
12V ...•... ; ....... 1"" ......:........ :....... ,....... ;............ .... . ~
BV ....... : ..•.... ; ....... .'.......... . ...... ; ............, .••
(V Input
OV-=-~'Th.J
Note the inversion in the signal
-(V
V2 = VCM signal see Fig. 3.6 and, for a
-1IV ••.••.. : ••••••. ; .•......:.......•••••..•..•.. ; ............••••......•.
, , 1 + z-2 , has the shape seen in F
"
" ,,
·12V ,
..,, , , ,
.." we move away from is 14. Note
- - - - -_. - - - - - - - j. - - . - .'. - - -
,
- -". - - -_ •• - -' - - - -~- - - - - - - - .' - - - - - - - -
·16V
.
"
"
---~
, , ,
Vout(Z) =
VI (Z) . Z-1I2
I
- - - - --, - --- - - j. - - - ---' -- - - - - - - _. - - - - - - '. - -- - - .'. - - - - _.'- - - - - - - - - - --
1 +Z- poles in the NTF is two (a first-<

·2OV
Dns 50ns 1DOns 15Dns 200ns 250ns 300ns 350"s 400n5 450ns 500ns
Figure 8.11 Simulating the operation of the resonator in Fig. 8.10.
Example 8.3
Suggest a modification to the resonator in Fig. 8.10 to eliminate the need for the
gain of -1 block. Verify your circuit modification with SPICE.
Reviewing Fig. 2.56 we see that if we connect the fed back output signal to the
top plate of the 2CF capacitor, Fig. 8.12, then the signal is inverted when it's Figure 8.13 Block
transferred to the output of the resonator. Simulation files for this circuit verifying
correct operation are available at CMOSedu.com. Note that we'll use the topology Example 8.4
seen in Fig. 8.10 since it is more tolerant of charge injection errors on the 2CF Simulate the operation of tJ-:
capacitor than the topology seen in Fig. 8.12 .• modulator's output spectrurr
out of the modulator at a r:
input frequency of 25.1 MH
an ideal digital bandpass fil
<1>1 <1>2 then estimate the final SNR h
,
Vc~,\ Figure 8.14 shows the mod

~--l>----
noise increases as the freq
VI (z) '\~---iT>--C_J_~,' VCM
+ oversampling ratio, K, can t

V2(Z)_ _ _ _+-_____~-'-----.J
OdB..,---_---,_ _-,--_ _,-:-V('-'-VO=uI]
·10dB ----------.---------1-, ---_. --1-------

~
,
.,,, , ,
'
''
-20dB -----T----------,----------,---_·
, , , -
·30dB
Figure 8.12 Implementing a resonator for use in a bandpass modulator.
·40dB
8.2.2 Second-Order Modulators
-50dB ................. ..
Figure 8.13 shows the implementation of a second-order modulator based on the
first-order lowpass topology seen in Fig. 7.1. Remembering, from page 290, that a ·60dS+------1---j---i----'
0.1 104Hz 7.1104Hz 14.1104Hz 21.1Io4Hz 2B
second-order bandpass modulator's SNR is similar to (calculated in the same way as) the
first-order lowpass modulator's SNR we can write Figure 8.14 Spectr
Mixed-Signal Circuit Design Chapter 8 Bandpass Data Converters 295
(8.20)
~Output
or, assuming G 1 = I (as discussed in Sec. 7.1.5),
STF NTF
.--Input (8.21 )
Note the inversion in the signal transfer function. This is trivial to remove; for an analog
signal see Fig. 3.6 and, for a digital signal, see Fig. 6.3. The noise transfer function,
1+ ,has the shape seen in Fig. 8.7. Atfsl4 the modulation noise is zero increasing as
VI (z) . z-1I2 we move away from j~ 14. Note that this topology is second-order because the number of
1 +z-I poles in the NTF is two (a first-order lowpass modulator has one pole in its NTF).
lator in Fig. 8JO.
Vout(Z) Out
~liminate the need for the

PICE.
back output signal to the
;nal is inverted when it's Figure 8.13 Block diagram of a second-order bandpass modulator.
:s for this circuit verifying
.hat we'll use the topology Example 8.4
jection errors on the 2CF Simulate the operation of the second-order modulator seen in Fig. 8.13 (show the
modulator's output spectrum) with a clocking frequency of 50 MHz (data eoming
out of the modulator at a rate of 100 MHz because of the 2-paths used) and an
input frequency of25.1 MHz. If the digital output of the modulator is run through
an ideal digital bandpass filter with a pass frequency range of 25 MHz ± 390 kHz
then estimate the final SNRideol'
Figure 8.14 shows the modulator's output spectrum. Notice how the modulation
noise increases as the frequency moves away from fs 14 (25 MHz here). The
oversampling ratio, K, can be calculated using, once again,
I.?-L-.-.....i---;----:t-- Desired output tone

at25.l MHz.
landpass modulator.
ler modulator based on the

ring, from page 290, that a -60dBr---i----i-----i---'-'+-''----.---·······-r---r'
.lated in the same way as) the O.lMHz
Figure 8.14 Spectrum of the modulator's output discussed in Ex. 8.4.

296 CMOS Mixed-Signal Circuit Design Chapter 8 Bandpass Data Cor
K= .!S (8.22) A Common Error

2B
Back in Fig. 7.39 and the ass
For the present example is 100 MHz and B 390 kHz so K 128. From Eq. forward path of the modul:::
(7.14) the SNR,denl is 66 dB.. delaying resonator, Fig. 8.17
8.2.3 Fourth-Order Modulators stage is made delaying by Sil
circuit. Unfortunately, the ad,
Figure 8.15 shows the block diagram of a fourth-order bandpass modulator formed by four clock cycles of delay.
transforming the lowpass second-order modulator seen in Fig. 7.26c. Again, the bandpass CMOSedu.com, for Fig. 8.1'
topology is now called a fourth-order modulator because the number of poles in the NTF unstable. The output of the m
is four. The transfer function for this, is 14, bandpass modulator (sometimes called a
quadrature modulator) is
STF NTF
(8.23)
Again, as discussed in Sec. 8.1 the fourth-order bandpass modulator's SNR can be
estimated using the same approach that we used for the second-order lowpass modulator
discussed in Sec. 7.2.
Figure 8.17 A fourth-ord
1 A Comment about l(fNoise

I +Z-2
Notice that in the bandpass n
noise doesn't have a signific;
Comparator gain not shown. large frequency). At lower
output removes both the mod
8.2.4 Digital I/Q Extractio
I<igure 8.15 A fourth-order bandpass modulator.
One of the benefits of digiti
Example 8.5
extract the I and Q compone
Repeat Ex. 8.4 using the fourth-order topology seen in Fig. 8.15.
chapter). The multiplication t
recover the original signals :
Figure 8.15 shows the modulator's output spectrum. The oversampling ratio, K, is
Extracting the IIQ componer
again 128 so using Eq. (7.52) the SNRideal is 100 dB. •
mismatch (difference in de
demodulators. Figure 8.19 sh
_i.-~+---!--'i-- Desired output tone from 25 MHz) signal seen in
at 25.1 MHz. the simulation is simply a
simulation example at CMOS
Modulation noise After looking at Fig.
output, a I-bit word, by 1,0,
corresponds to 0 I (+ 1) in
Multiplying these outputs b
Multiplication by + I or -1 n
11 x (-1) 01. A data select{
be used to implement the m
-60~~MHZ 7.1MHz 14.1MHz 2L1MHz 28.1MHz 35.1MHz 4Z.1MHz 49.1MHz
8.19 at CMOSedu.com for on
Figure 8.16 Spectrum of the modulator's output discussed in Ex. 8.5.
fixed-Signal Circuit Design Chapter 8 Bandpass Data Converters 297
(8.22) A Common Error

Back in Fig. 7.39 and the associated text we discussed that adding gratuitous delay to the
so K = 128. From Eq. forward path of the modulator would move it towards instability. Consider using a
delaying resonator, Fig. 8.17, for the first stage of the fourth-order modulator. The first
stage is made delaying by simply switching the phases of the clock signals used in this
circuit. Unfortunately, the added two clock cycle delay in the forward path, for a total of
Ipass modulator formed by four clock cycles of delay, makes the topology unstable. Simulation examples at
7.26c. Again, the bandpass CMOSedu.com, for Fig. 8.17, can be used to help show that this modulator is always
lumber of poles in the NTF unstable. The output of the modulator oscillates atJ,14 regardless of the input signal.
ulator (sometimes called a
STF
(8.23)
is modulator's SXR can be
ld-order lowpass modulator
Figure 8.17 A fourth-order bandpass modulator two delaying resonators (bad).
VOll/(Z) Out A Comment about IljNoise

-2
Notice that in the bandpass modulators we've discussed llj noise isn't a concern. The IIj
noise doesn't have a significant effect on the signal atf!4 (assumingf,i4 is a relatively
lin not shown. large frequeney). At lower frequencies the digital filter eonneeted to the modulator's
output removes both the modulation noise and the Iljnoise.
8.2.4 Digital IIQ Extraction to Baseband
.dator.
One of the benefits of digitizing the signal around f, 14 is the ease with which we can
extract the J and Q components in the transmitted signal (see the first few pages of this
:.8.15.
chapter). The multiplication by the sine and cosine terms, see Eqs (8.2) and (8.6), used to
recover the original signals simplifies to multiplying by either +1, -1, or 0, Fig. 8.l8.
~versampling ratio, K, is
Extracting the JIQ components digitally eliminates the J and Q channel phase response
mismatch (difference in delay through each path) encountered in typical baseband
demodulators. Figure 8.19 shows the simulation results showing how the 100 kHz (offset
sired output tone from 25 MHz) signal seen in Fig. 8.16 is demodulated to baseband. Note that the input in
25.1 MHz. the simulation is simply a 25.1 MHz sinewave, not an JIQ generated signal (see
simulation example at CMOSedu.com using an JIQ signal).
lIodulation noise After looking at Fig. 8.18 we might wonder how we multiply the modulator
output, a I-bit word, by 1, 0, and -1. As seen in 6.3, a 1 coming out of the modulator
°
corresponds to 1 (+ 1) in two's complement while a
MUltiplying these outputs by ° ° corresponds to 11 (-1).
results in an output of 00 (0) in two's complement.
Multiplication by +1 or -1 resultsinOI x(+I) 01,01 x (-1) 11,11 x(+I)=ll,and
°
11 x (-1) = 1. A data selector and a multiplexer with some logic for output selection can
be used to implement the multiplier (see the simulation example used to generate Fig.
8.19 at CMOSedu.com for one example).
cussed in Ex. 8.5.
J
298 CMOS Mixed-Signal Circuit Design Chapter 8 Bandpass Data Con'
[4] A. K. Ong and B. A. '
i""d"
IF Extraction at 20 MI
C is pp. 1920-1934, Decem
4
[5] S. R. Norsworthy, R
I---~ I output Converters: Theory, J
978-0780310452
In
Multipliers Digital filters [6] B.-S. Song, "A 4th-C
Op-Amps," IEEE Soh
I---~ Q output 1995
Is [7] B.-S. Song, "A Fourt
Numbers of Op-Amp,
sin 2rc· ~ . nTs = sin n~ = 0, 1,0, -1... pp. 1309-315, Deceme
[8] D. B. Ribner, "Multist

Figure 8.18 Digital I1Q demodulation. Systems 11: Analog an
June 1994
[9] S.A. Jantzi, W.M. Snt
250rnV
"\~---'-I--I/Q Sigma-Delta Modulatt

200rnV
150rnV
pp. 282 - 291, March I

Q
lOOrnV
[10] J, C. Candy and G. C.

50mV
Wiley-lEEE Press, 19 t
OrnV
-50rnV
1 QUESTIONS
-100rnV
-150rnV
8.1 Show, using SPICE, h

-200rnV
discussed in the begin

-250rnV
------ the resulting I/Q to COl
-300rnV
O~s 4~s 16~s 8.2 Suggest a topology fe

input and fed back sig
Figure 8.19 Showing how I and Q components of a signal can be extracted digitally. Does your topology h
or why not? Simulate
8.3 Show the details of de

ADDITIONAL READING
8.4 Repeat question 8.3 fe
[1] R. Schreier and G. C. Ternes, Understanding Delta-Sigma Data Converters,
Wiley-lEEE Press, 2005. ISBN 978-0471465850 8.5 Derive the transfer fur
[2] A. I. Hussein and W.B. Kuhn, "Bandpass Lf1 Modulator Employing 8.6 Sketch the implement
Undersampling of RF Signals for Wireless Communication," IEEE Transactions but using a multi-bit q
on Circuits and Systems 11: Analog and Digital Signal Processing, Vol. 47, No.7,
8.7 Show the details of he
pp. 614 - 620, July 2000
8.8 Derive the transfer ful
[3] A. Jayaraman, P.F. Chen, G. Hanington, L. Larson, and P. Asbeck, "Linear
High-Efficiency Microwave Power Amplifiers using Bandpass Delta-Sigma 8.9 Using the modulator
Modulators," IEEE Microwave and Guided Wave Letters, Vol. 8, No.3, pp. 121 sinusoid to the modul
123 March 1998 digital data through a
input and output sigm
ixed-Signal Circuit Design Chapter 8 Bandpass Data Converters 299
[4] A. K. Ong and B. A. Wooley, "A Two-Path Bandpass SD Modulator for Digital
0,-1,0...
IF Extraction at 20 MHz," IEEE Journal afSolid-State Circuits, Vol. 32, No. 12,
pp. 1920-1934, December 1997
[5] S. R. Norsworthy, R. Schreier, and G. C. Ternes (eds.), Delta-Sigma Data
I output Converters: Theory, Design, and Simulation, Wiley-IEEE Press, 1997. ISBN
978-0780310452
filters [6] B.-S. Song, itA 4th-Order Bandpass ~z: Modulator with Reduced Number of
Op-Amps," IEEE Solid-State Circuits Conference, pp. 204-205, 367, February
Q output 1995
[7] B.-S. Song, "A Fourth-Order Bandpass Delta-Sigma Modulator with Reduced
Numbers of Op-Amps," IEEE Journal of Solid-State Circuits, Vol. 30, No. 12,
1. 0, 1... pp. 1309-315, December 1995
[8] D. B. Ribner, "Multistage Bandpass Delta Sigma Modulators," IEEE Circuits and
1. Systems II.' Analog and Digital Signal Processing, Vol. 41, No.6, pp. 402 405,
June 1994
[9] S.A. Jantzi, W.M. Snelgrove, and P.F. Ferguson Jr., "A Fourth-Order Bandpass
--'-+--I1Q Sigma-Delta Modulator," IEEE Journal of Solid-State Circu.its, Vol. 28, No.3,
pp. 282 291, March 1993
Q
[10] J. C. Candy and G. C. Ternes (eds.), Oversampling Delta-Sigma Data Converters,
I QUESTIONS
8.1 Show, using SPICE, how to adjust the phase and amplitude of the I and Q signals
discussed in the beginning of the chapter to modulate the amplitude and phase of
the resulting I1Q to construct a constellation diagram for 8-level rectangular QAM.
8.2 Suggest a topology for the bandpass passive-integrator NS modulator where the
input and fed back signals are currents. Derive a transfer function for your design.
n be extracted digitally. Does your topology have the extra noise/distortion term seen in Eq. (8.12)? Why
or why not? Simulate the operation of your design.
8.3 Show the details of deriving the transfer function for the modulator in Fig. 8.6.
8.4 Repeat question 8.3 for the modulator seen in Fig. 8.8.
a-Sigma Data Converters,
8.5 Derive the transfer function for the modulator seen in Fig. 8.9.
~ Modulator Employing 8.6 Sketch the implementation of a modulator, based on the topology seen in Fig. 8.9,
~ation,"IEEE Transactions but using a multi-bit quantizer and feedback DAC.
Processing, Vol. 47, No.7,
8.7 Show the details of how Eq. (8.18) is derived.
8.8 Derive the transfer function of the modulator seen in Fig. 8.12.
1, and P. Asbeck, "Linear
19 Bandpass Delta-Sigma 8.9 Using the modulator topology in Ex. 8.4, show that if we apply a 25 MHz input
~rs, Vol. 8, No.3, pp. 121 - sinusoid to the modulator we can recover this input signal by passing the output
digital data through a bandpass filter with a very small bandwidth (show that the
input and output signal amplitudes are equal).
8.10 Derive the transfer function of the topology seen in Fig. 8.17. VerifY that the
topology is unstable by determining the location of the topology's poles.
8.11 Using a bandpass modulator and digital demodulation (sketch the schematic of
your design) show how to recover a 10 kHz sinewave that is amplitude modulated
with a carrier frequency of I MHz. Use SPICE to verifY the operation of your
design.
A High-Spe
The majority of the data converte

off time for resolution (so the
clocking frequency). In other w.
output word size, N) we've avera
remove the modulation noise. n
reducing the noise-shaping mod
turn our attention towards high-~
covered in Sec. 6.2.3 where K-I
used for the required feedback su
9.1 The Topology

Our high-speed topology, Fig. (
bandpass topology) that sums thf
the K feedback paths. Let's start (
9.1.1 Clock Signals
Examine the clock signals seen
figure can be generated by simpl
need KI2 phases of a clock sigm
falling) edges of these clock sign
The key thing to note is that t17

sampling Fequency. Rather the
frequency, fs.n".... Why is this im
oscillator, for example, made \"
effective, sampling frequency is
then we are oversampling 1000
each path to have enough time t
consideration (path settling tim
paths in the converter, and thus t
n Fig. 8.17. Verify that the

e topology's poles. Chapter
on (sketch the schematic of
: that is amplitude modulated
verify the operation of your
9
A High-Speed Data Converter
The majority of the data converter topologies we've discussed up to this point have traded
off time for resolution (so the signal bandwidth is generally much smaller than the
clocking frequency). In other words, to get higher signal-to-noise ratios, SNRs, (wider
output word size, N) we've averaged (filtered) the output of a noise-shaping modulator to
remove the modulation noise. The averaging (again, filtering) has the undesired effect of
reducing the noise-shaping modulator's allowable signal bandwidth. In this chapter we
tum our attention towards high-speed topologies. Our approach is based on the material
covered in Sec. 6.2.3 where K-paths are used but with switched-capacitor, SC, circuits
used for the required feedback subtraction from the input (delta) and integration (sigma).
9.1 The Topology

Our high-speed topology, Fig. 6.24, consists of a single integrator (or resonator for a
bandpass topology) that sums the difference between the input signal and the signals from
the K feedback paths. Let's start out this section by discussing the clock signals.
9.1.1 Clock Signals
Examine the clock signals seen in Fig. 9.l. Notice that the last four clock signals in this
figure can be generated by simply inverting the first four clock signals (so for K-paths we
need KI2 phases of a clock signal atjJ By sampling an input waveform on the rising (or
falling) edges of these clock signals we get an effective sampling frequency of
fs,new = Kpalh ·Is (9.1)
The key thing to note is that the frequency of the clock signal, Is ' doesn't set the new
sampling frequency. Rather the delay between rising edges sets the effective sampling
frequency, Is,new' Why is this important? If we generate these clock signals using a ring
oscillator, for example, made with inverters having delays of 10 ps then the new, or
effective, sampling frequency is 100 GHz! If our desired signal bandwidth is 100 MHz
then we are oversampling 1000 to 1. The frequency Is is selected to allow the circuits in
each path to have enough time to respond (settle). Using the ring oscillator example, this
consideration (path settling time) tells us how many inverters we need, the number of
paths in the converter, and thus the ring oscillator's oscillation frequency Is.
302 CMOS Mixed-Signal Circuit Design Chapter 9 A High-Speed Data C{
9.1.2 Implementation
Figure 9.4 shows how we woul
single integrator, I-sigma, wit
switched-capacitors, Fig. bu
has to respond very quickly, a
integration capacitor, 4C" is sele
in detail in the last chapter. Also
outputs from each path can be
summed to generate an output Cl
outputs are high). Summing the
function of
H(;
is,new Kpath'ls
as seen in 9.3. Note that this

Figure 9.1 Showing the clock signals used for time-interleaved sampling and the
high-speed topologies discussed in this chapter. sample-and-hold, SIH, Fig. 2. 17,
path outputs let's do some examp
Path Settling Time
Figure 2.37 details the clock signals used in traditional multi-rate signal processing. iH(f)i
These signals should be compared to the clock signals seen in Fig. 9.1. When processing
digital signals that are clocked, for example, on the rising edge of the clock signal, the
signals in Figs. 2.37 and 9.1 are equivalent. In an analog circuit, however, the signals seen
in 9.1 allow the capacitors more time to be charged or discharged. This is illustrated
in Fig. 9.2. We need to be carefUl here. When sampling the input signal we must ensure
that the input signal can charge the sampling capacitors, using either clock signals, in
T/Kpa1h ' If this isn't the case then we effectively filter our input signal reducing its
amplitude (the benefit of this inherent filtering is a built-in anti-aliasing filter, AAF). The
reward for using the wider clock signals is that we can adjust the feedback signal's timing
to help keep the topology stable. It's also critically important for a precision feedback 2Kpalh
signal from the DAC. The fact that the rate the capacitors charge/discharge is highest
right after the switches close can be used to ensure that a single path pushes the summing Figure 9.3 Frequency respo
circuit in the right direction. However. ifthe "push" isn't significant enough (doesn't occur
quickly enough before clocking the next path) the topology will oscillate. The summing Examp]e 9.1
circuit's signal, say the voltage across C in Fig. 6.24, will move around confused because Simulate the operation of the
of the varying, or conflicting, information fed back from each path in the converter (see 100 MHz. Show that an inpu
Sec. 9.1.5 for further discussions). and 2.17, attenuating the inpl
Figure 9.5 shows the simul
centered around 500 m V wi
I I I 9.1
which the data comes out of
nL..-_-InL--_---'nl.-__ Fig. 2.37 every 1.25 ns). Also notice tl
here I V, divided by 8 or 125
Switched-capacitor Figure 9.6 shows the inpl

charging/discharging (the Nyquist rate if we wer(
MHz). We expect the ampli"
Figure 9.2 Charging discharging a switched-capacitor. The simulation shows an ou
•
1ixed-Signal Circuit Design Chapter 9 A High-Speed Data Converter 303
9.1.2 Implementation
Figure 9.4 shows how we would implement a high-speed analog-to-digital topology, a
single integrator, I-sigma. with K feedback paths, K-deltas, (see Fig. 6.24) using
switched-capacitors, Fig. building blocks. The amplifier used in the active integrator
has to respond very quickly, as described in the last chapter. Further note that the
integration capacitor, 4Ci , is selected based on an integrator gain of 0,25, again, discussed
in detail in the last chapter. Also seen in this figure are the clock signals and the way the
5 =~ outputs from each path can be combined together. The outputs of the K paths can be
6 = $2 summed to generate an output code ranging from 0000 (aU outputs are low) to 1000 (all
$3 outputs are high). Summing the outputs together results in Sinc filtering with a transfer
function of
1 _Z-8 .
H(z) "" ~ With Is,new Kpa1h'ls (9.2)
as seen in 9.3. Note that this is exactly the same response that we get when using the
:avcd sampling and the
sample-and-hold, SIB, Fig. 2.17, clocked at/,. While there are other ways to combine the
path outputs let's do some examples.
mlti-rate signal processing. IH(f) I

n Fig. 9.1. When processing /~, Nyquist frequency
dge of the clock signal, the
it, however, the signals seen H(z)
ischarged. This is illustrated
Desired spe~lliIl~
input signal we must ensure
,ing either clock signals, in
Ir input signal reducing its f fs,new = Kpath ·Is
Iti-aliasing filter, AAF). The Kpath Kpa1h
the feedback signal's timing fq;~ew
,nt for a precision feedback 2Kpalh
charge/discharge is highest
[Ie path pushes the summing Figure 9.3 Frequency response of the summing circuit (path filter) seen in Fig. 9.4.
ficant enough (doesn't occur
will oscillate. The summing Example 9.1
ve around confused because Simulate the operation of the data converter seen in Fig. 9.4 if C; 100 tF and/, =
:h path in the converter (see 100 MHz. Show that an input frequency of 50 MHz results in, as seen in Figs. 9.3
and 2.17, attenuating the input by 3.9 dB 0.64).
Figure 9.5 shows the simulation results when the input is a 7 MHz sinusoid
Fig. 9,1 centered around 500 mV with an amplitude of 400 mY. Notice that the rate at
which the data comes out of the summing circuit is 800 MHz (the output changes
Fig. 2.37 every 1.25 ns). Also notice that the change in the output is the reference voltage,
here 1 V, divided by 8 or 125 mY.
Switched-capacitor Figure 9.6 shows the input and output if the frequency is increased to 50 MHz
charging!discharging (the Nyquist rate if we were to decimate down to a clocking frequency of 100
MHz). We expect the amplitude of the output to be 0.64·0.4+0.5 or 756 mY.
capacitor, The simulation shows an output of 750 mY (remember the quantization noise) .
•
304 CMOS Mixed-Signal Circuit Design Chapter 9 A High-Speed Data 0
I-sigma
4JI-l 4J2-1
VCM ~'
i: C ! :
----.~4J1-2~ 4J2-2
.:~~~------~~+---~
-~,
<Pl~
-L:
4J2-~: : : :r i r-1
J:'-+----+ l'~;;:L--j
4J1-3~
L
4J1-3 4J2-3
4J2-3~ I I "" I '
Figure 9.5 Simulating
a 7 MHz ir
4J 1-4 '~;;I~
r-:--:--:l:, r-1
L-.J
i
'" ,....."." :, , .' .,----,

. , r-1 909mV'-r=r::-~-'-';"""
'1'2-4 , , ~' L-----1 L
4J 1-4 4J2-4 Bl0mV
~.
Non-overlapping clocks. 720mV
IT '-+-------r--__+__ s
4J2-1 4JH :§l
IT: Ys
0
Summing circuit.
J'-+-----+-_+__
YI 1On. 20n.
Yz
~ Y6 Y3 Figure 9.6 Again, sim

now with,
J : '-+---------\-_+______'
Y4
4J2-3 4J1-3 Example 9.2

Repeat Ex. 9.1 ifthe output;
"T Figure 9.7a shows that addiJ
li,-+------+---+- to decimate the word rate de

summation circuit or a log;
4J2-4 4Jl-4 summing circuit (not shown
~: Adding the eight outputs together.

circuit are an important prac
so eliminating the skew intn
_.J'''--------' Path filter, 1 - z-8
1
on the input side (Fig, 9.7a),
The simulation results aJ
K-Deltas Comparators, aka quantizers frequency is at the Nyquist
Avoiding decimation (down
Figure 9.4 A topology for high-speed data conversion using mixed-signal techniques.
the K-delta-I-sigma topology. 9.6, and 9.8, and discussed
signal intact.
lixed-Signal Circuit Design Chapter 9 A High-Speed Data Converter 305
:::t.. 1Lf..- . l...·--:r::.. .L....

\I{vinj
o.avil·--d--··'it·--·+----··}··--·+
::: . .:·;--:·::.~~·:·::: ...:·:L:.·--i .=::r::::..
0.5V --.~---- .. C__ .
. ·~----· .. 7
.
.... - -------- ..... +h,.•. ; .....
.
::: ..:...L:::.. :::::.: ~.~
.::::.L· .;::::.:::·::::::.L.\
O.2V ~ -1 ___ :w. ______; --.".~ 1 f ",wf_·_·
O.lV ....... ( .... : . . . . +. . ~ .... ;........;.......; ....... ~.
o.ov , I I I I --i---i--"-i-----i
Ons 30ns SOns 90ns 120ns 150ns 180ns 210ns 2~Ons 270ns 300ns
Figure 9.5 Simulating the operation of the data converter in Fig. 9.4 with
a 7 MHz input signal.
gOOmV'.--~--~;?---.,---;,.,-,---~,---=~-.",.__.-__,
810m\!
~on-overlapping clocks.
360mV
270mV
Summing circuit.
180mV
9UmV
OmV+--~-~-i--i---i---4-~-~-~-~
Ons 20llS 3Dns 4Dns 50ns 60ns 80ns 90n. lOOn.
Figure 9.6 Again, simulating the operation of the data converter in Fig. 9.4 but
now with a 50 MHz input signal.
Example 9.2
Repeat Ex. 9.1 if the output is decimated down to the 100 MHz clock rate.
Figure 9.7a shows that adding a register in series with the K outputs can be used
to decimate the word rate down to Is. A K-bit register can be placed in front of the
summation circuit or a log2 K wide register can be placed on the output of the
summing circuit (not shown in Fig. 9.7). Timing mistakes in this digital part of the
circuit are an important practical concern. The digital signals are moving quickly
the eight outputs together.
so eliminating the skew introduced by the summing circuit, by placing the
'ath filter, 1 - z-8 on the input side (Fig. 9.7a), is the approach we take here.
I
The simulation results are seen in 9.8. Notice that, when the input signal
~ers
frequency is at the Nyquist rate in Fig. 9.8b, that the sampling instances repeat.
Avoiding decimation (down-sampling), as can be seen when comparing Figs. 9.5,
ng mixed-signal techniques,
9.6, and 9.8, and discussed in detail earlier in the book, helps keep the original
signal intact.
J
306 CMOS Mixed-Signal Circuit Design Chapter 9 A High-Speed Dau
From To summing
To summing
circuit.
Ys
(a) Decimating by K. (a) 7 MHz input

Ys
Figure 9.9
(b) Decimating by K!2.
~1-1
Examples
Figure 9.7 Adding a register to decimate the outputs ofthe high-speed modulator. Let's say that we want to de~
outputs 8-bit words at least
mixed-signal circuit techniq
pipeline or flash) replacemer
Let's use the topolo!
Generating the phases of th(
that the reader understands t'
based on kTiC noise, Table:
our topology with eight patl
noise, of 800 iF.
As mentioned at the
(a) 7 MHz input (b) 50 MHz input, note how the sampling
times are repeating. iF capacitors with the input
ns so the switch resistance sl
Figure 9.8 Repeating Ex. 9.1 but with a decimation of 8. What this design COl
In order to move towards reducing the unwanted effects of decimation
rate on the output of the K-p
(aliasing) and timing errors, examine the topology seen in Fig. 9.7b. Here we've seen in Fig. 9.10. Here we 1
split the word up into two paths (though we could also use 4 paths with the cost of Directly on the output of
tighter timing concerns). Summing the words together, we still get the filtering decimate by 8 back down to
specified by Eq. (9.2). However, our decimated word rate is now 21;. Figure 9.9 indicated by Eq. (9.2) this 1<
shows the simulation results using these techniques. The benefits should be centered around 500 mV \\
obvious.• attenuation of our signal fro'
9.1.3 Filtering
Thinking about what we've done in this section we might come to the conclusion that the
topology seen in Fig. 9.4 is nothing more than a flash ADC implemented with The output of the summing
8-comparators. We are only getting, effectively, 3-bits out of the topology (see previous 1000 (8 in decimal). We pa
examples) so why not simply use a 3-bit flash ADC? The simple answer to this is that word size by 3-bits each fOJ
averaging (read filtering) has little, Fig. 5.31, to no (for a DC input) effect on the centered around the comme
resolution of a Nyquist-rate ADC while averaging can be used in a noise-shaping by 2 and center the word (a
topology to increase the resolution, Fig. 7.7. We are repeating material presented earlier more than required. The iS1
in the book so let's just do some examples to provide additional discussions.
Mixed-Signal Circuit Design Chapter 9 A High-Speed Data Converter 307
~ .D
N
~
elk.
T $2-1
To summing
circuit.
u.s JOn,. .cOns SOn$ !jOna 10n5 BDJls 90'''01 1DOllS
(a) 7 MHz input (b) 50 MHz input
Figure 9.9 Repeating Ex. 9.1 but with a decimation of 4.

(b) Decimating by K!2.
$:-1
Examples
e high-speed modulator. Let's say that we want to design an ADC that is clocked with a 100 MHz clock and that
outputs 8-bit words at least at a 100 MWord/s rate. In other words, we want to use
mixed-signal circuit techniques to design the equivalent of a Nyquist-rate ADC (e.g.,
pipeline or flash) replacement (so the signal bandwidth ranges from DC to 50 MHz).
Let's use the topology seen in Fig. 9.4 as the basis for discussing this design.
Generating the phases of the clocks is something we'll discuss later. Further we assume
that the reader understands that selecting the size of the capacitors used in the topology is
based on kTIC noise, Table 2.1, considerations. We'll continue to use 100 fF capacitors in
our topology with eight paths for an effective capacitance, for calculating input-referred
noise, of800 fF.
As mentioned at the beginning of the section, we must be able to charge the 100
input, note how the sampling
: repeating. fF capacitors with the input signal in T)K seconds. For the present example T)K 1.25
ns so the switch resistance should be much less than 12.5 kO (very easy to ensure).
imation of 8.
What this design comes down to is selection of both the appropriate decimation
:d effects of decimation rate on the output of the K-path topology and the digital filter. Examine the block diagram
I in Fig. 9.7b. Here we've
seen in Fig. 9.10. Here we use the 8-path topology seen in Fig. 9.4 clocked at 100 MHz.
se 4 paths with the cost of Directly on the output of the modulator, which changes at a rate of 800 MHz, we
, we still get the filtering decimate by 8 back down to 100 MHz, with the register, and add the outputs together. As
'ate is now 2j~. Figure 9.9 indicated by Eq. (9.2) this lowpass filters the data. If our input is a sinusoid at 6.25 MHz
The benefits should be centered around 500 mY with a peak amplitude of 400 mY, then we can estimate the
attenuation of our signal from this addition (filtering) using
-~""-=0.993 (9.3)
)me to the conclusion that the
Ish ADC implemented with The output of the summing circuit is a 4-bit word that ranges from 0000 (0 in decimal) to
of the topology (see previous 1000 (8 in decimal). We pass the 4-bit output through two Sinc filters which increase the
simple answer to this is that word size by 3-bits each for a total output word size of 10-bits. However, the word is not
r a DC input) effect on the centered around the common-mode voltage so we can shift the word left to do a multiply
be used in a noise-shaping by 2 and center the word (as discussed earlier). This reduces the word size to 9-bits, still
jng material presented earlier more than required. The issue is that we also reduce the signal bandwidth. For our 6.25
mal discussions.
308 CMOS Mixed-Signal Circuit Design Chapter 9 A High-Speed Data Co
Thermometer code ~fs @f, 0000 1000 Multiply output by 2, shift to 8is
\ \ &+-1\0 gHOfrOm IOt09b~~tS'
~@f\ J \
4
In~+\ 4 1-z- 8
7 l-Z=~ 9 Out
I Fig. 9.4 + DQ
elk
Analog '------' Lf I - Z-I I - z . Digital
8fs
.. is 100 MHz
/ D~~imator a~d -path filter

~~:DQ51
ts:::.~'9dB=0'64
~ I
i elk
_ _ __
i -7.8 dB = 0.41 @ 6.25 MHz
50 MHz
l~f
8is 4/s
. ~f Figure 9.12 D,
50 100
6.25'12.5 MHz
Figure 9.1 0 Decimating and filtering the output of the K-path modulator, an
approach that won't work for Nyquist-rate conversion.
810mV
72UmV
MHz input signal, as seen in Fig. 9.10, this means that we attenuate the signal by OA1. 630mV
The total attenuation of our 6.25 MHz input signal is then OA07 so the peak amplitude 540mV
out of the filter is 663 mV (ideally it's 900 mY). Figure 9.11 shows simulation results
verifying our hand calculations. Note the delay through the filter when starting.
Studying Fig. 9.10, we see that the decimation right at the beginning of the digital
filter is limiting our bandwidth. Consider spreading the decimation out through the filter
as seen in Fig. 9.12 (see also Sec. 4.2.5). Here we've put a register on the output of the
summing circuit instead of on its input, Fig. 9.7a. For ideal signals we may not need this OmV·-j-L-.,.----t-
Ups 50ns 1 OOn~
register; however, as mentioned earlier, eliminating skew and timing errors is important
for proper data converter operation. Simulation results are seen in Fig. 9.13. The input
signal undergoes less attenuation but the final resolution is 7-bits instead of 9-bits Figure 9.13 Simul
(indicating that there is less filtering in Fig. 9.12 than 9.10). In order to move towards our
design requirements, an 8-bit converter with a signal bandwidth of 50 MHz that is Figure 9.14 shows our ill
clocked at 100 MHz, our final output clock rate will be increased to 200 MWords!s results, with a 6.25 MHz input, a
(instead of 100 MWords/s as in Figs. 9.10 and 9.12). Fig. 9 A we are still attenuating 01
of the adder is changing at 200
place in the filter. The chain of a\
size by I-bit per stage. The
(0.707)5 :::: 0.177, see Fig. 1.17.
results in an overall attenuation
signal frequency and simulate to '
Figure 9.16 shows yet ane
MHz input should see the -3.9 (
9.10. In addition, as seen in Fig.
the first zero point occurs at
additional, minor, attenuation, Fi
remove the modulation noise in
fiNo, the filter doesn't remove th
Figure 9.11 Simulating Fig. 9.10 with a 6.25 MHz input signal. goals? Further, how do we detem
lixed-Signal Circuit Design Chapter 9 A High-Speed Data Converter 309
tiply output by 2, shift to

:om 10 to 9 bits,
'l ~
1-
~~@f,
Z-1
Out
Digital
@8j,
J \
I~ Fig. 9.4~1--4T--1~tF
t:<.='
~
: ~f
@ 50 Mlh
Multiply
Sls 50 100 output
by 2,
7
/ Out
I dB = 0,41 @6.25 MHz
4j~
~f Figure 9.12 Decimating through the filter, see Sec, 4,2.5,

12,5 .'v1Hz
:-palh modulator. an
onversion.
ttenuate the signal by OAI,

A07 so the peak amplitude
II shows simulation results
ter when starting,
. the beginning of the digital
nation out through the filter
'egister on the output of the
ignals we may not need this
d timing errors is important
,een in 9,13, The input
is 7-bits instead of 9-bits Figure 9.13 Simulating 9.12 with a 6.25 MHz input signal.
[1 order to move towards our
dwidth of 50 MHz that is Figure 9.14 shows our next attempt at filtering and decimation. The simulation
ncreased to 200 MW ords/s results, with a 6.25 MHz input, are seen in Fig. 9.15. By adding together the 8 outputs in
Fig. 9A we are still attenuating our input signal with a Sine response. Note that the output
of the adder is changing at 200 MWords/s. We don't employ decimation at any other
place in the filter. The chain of averaging filters, on the adder's output, increases the word
size by I-bit per stage. The attenuation from this digital filter at 50 MHz is
(0,707)5 0.177, see 1.17. This, combined with the attenuation from the addition,
results in an overall attenuation for a 50 MHz input signal of 0.113 (change the input
signal frequency and simulate to verify).
Figure 9.16 shows yet another filter. This filter doesn't employ decimation so a 50
MHz input should see the -3.9 dB attenuation from adding the 8 outputs together,
9.10, In addition, as seen in Fig. 1.17 (but with frequencies on the x-axis scaled by 8 so
the first zero point occurs at 400 MHz), the averaging stages will provide some
additional, minor, attenuation, Fig. 9.17. The question we need to ask is "Does this filter
DOns ~50ns 500no
remove the modulation noise in addition to increasing the word size?" If the answer is
"No, the filter doesn't remove the modulation noise," then how do we meet our design
[z input signal.
goals? Further, how do we detelmine if the filter removes the modulation noise?
310 CMOS Mixed-Signal Circuit Design Chapter 9 A High-Speed Dat,
Anal~~ Fig. 9.4~
~~
~
8fs
Figure 9.16 Filteri
~
remov
word ~
1.011
.. > 0.911
O.BV
so/is Is 21s'200 0,711
2 0.611
Figure 9.14 Another filter; however, this topology has problems removing 0.511
the modulation noise.
0.411
0.311
0.211
O.W
D.OV
On. SOns
Figure 9.17 Simul

the ll(
:::fKT
0.811-+-(K
On. 1DOns 150n8 200ns 250ns 300n. 350n. 400n. 450n. 500ns
o. 7V4 1""\ ~
Figure 9.15 Simulating Fig. 9.14 with a 6.25 MHz input signal. Note the
the nonlinearity in the output.
-ti ...
0 6v
D,5114--·,\"
+.
In order to move towards answering these questions, notice the nonlinearity in
0.41'1. ....,\.
both Figs. 9.15 and 9.17. We implemented the filter by focusing on only increasing the ~.3V+ ..... A\
,
0.2V~--"'"''
output word size to 8-bits. We didn't concern ourselves with removing the modulation
noise and thus we see noise and nonlinearity in our output signal. Reviewing Sec. 7.1.3, 0.1V4 ..·....;·
we can remove the modulation noise by using the filter seen in Fig. 9.1 0 but without the o.ov-r---i-
Dns 10m
decimation (noting that if L 2 then only the path filter and one Sinc filter are used for a
7-bit output). This also helps us move closer towards the design goals. Figure 9.18 shows
the simulation results when a 50 MHz input is applied to the topology seen in Fig. 9.l0 Figure 9.18 Using th
due to 3·
without decimation. The input signal undergoes 3-Sinc filter responses (0.64)3 0.262.
[ixed-Signal Circuit Design Chapter 9 A High-Speed Data Converter 3 II
8f,
MUltiply
Multiply output
output by 2.
8 8 by 2.
~Out
'_L_.~ . Diigital
8f,
@2!s
Figure 9.16 Filtering without decimation. This filter won't do a good job
removing the modulation noise but it does increase the output
word size to 8-bits .
problems removing
Figure 9.17 Simulating Fig. 9.16 with a 6.25 MHz input signal. Again, note the
the nonlinearity in the output.
Ons 450no 500ns
ut signal. Note the
, notice the nonlinearity in

ISing on only increasing the
h removing the modulation
gnal. Reviewing Sec. 7.1.3,
in Fig. 9.10 but without the
me Sinc filter are used for a
gn goals. Figure 9.18 shows
: topology seen in Fig. 9.10 Figure 9.18 Using the filter seen in Fig. 9.10 without decimation. Attenuation is
due to 3-Sine stages. The input signal frequency is 50 MHz.
esponses (0.64)3 0.262.
312 CMOS Mixed-Signal Circuit Design Chapter 9 A High-Speed Data
Direction
In order to move towards our design goals we can use the filter seen in Fig. 9.12 but with ""1iiW
~l~
an additional averaging, I + z I , stage on the filter'S output. This increases the word size
to 8-bits. The penalty is an extra 3 dB attenuation at 50 MHz (so the total attenuation at
50 MHz is 10.S dB or 0.2S8). The practical issue with this topology, for very high-speed
operation, is avoiding timing errors in the stages clocked at Sis. For a general design, we'll
use the topology seen in 9.10. Timing errors are straightforward to minimize. The
~ H(z)
~3 -'
drawback is the reduction in signal bandwidth. ••
•
An area that should be investigated further is the use of biquad filters for
removing the modulation noise, as discussed in Sec. 4.3.4.
,_I~
9.1.4 Discussion
If the NS modulator seen in Fig. 7.2 is clocked at 100 MHz we get the noise transfer
function, NTF, shape seen in Fig. 9.l9a (out to 800 MHz or Sis). While we are used to
/
H(z) = Vin(Z)'
focusing on the spectral content between DC andls (= 100 MHz here), we know that any
discrete-time system's frequency response repeats with the sampling frequency, Is. The
signal bandwidth, as seen in the figure, is 6.25 MHz, assuming Kavg = S. Note that we are
not showing the frequency response of the digital filter used for removing the modulation
noise (which is where Kavg is used, Eq. [6.47] and Fig. 7.8). Figure 9.19b shows the
assumed spectrum of the quantization noise while Fig. 9.19c shows the single path
clocked at 100 MHz (noting we are not showing the non-overlapping clock signals).
INTF(f) I2
200
: 50 100 200 400 500 600 700 800 MHz (c) Quantization noise for aJ
6.25 (a) NTF ofa noise-shaping topology clocked at 100 MHz, 7.6.
IVQe(f) I2, V 2 /Hz NTFer)
visB i . V;n(Z) i M d It
-'-Iou a or.
H()
Z
Vin(Z)' + (l-Z-l) ,VQe(f)
12fs~ , elk ~ Desired spectrurr
50 100 MHz ~IOOMHz
(b) Quantization noise PSD, Fig. 5.12. (c) Modulator clocked at 100 MHz. 50 100 200
6.25 (d) Moe

Figure 9.19 NTF and quantization noisc spectrums of a first-order NS modulator
clocked at 100 MHz with 8. Figure 9.20 Eight
Next, examine the S-path topology of modulators seen in 9.20 (modified from quantization noise out over a
Fig. 2.37 for this discussion). In (a) of the figure each modulator is clocked at!" the same noise added to our signal in t
as in Fig. 9 .19c, but with time-shifted clock signals. In (b) we show the equivalent circuit, our desired signal bandwi.
see discussion on page 224 for details, noting the equivalent circuit's output changes with improvement in SNR. Note
a frequency of Kporh ·Is. By using an effectively higher clock frequency we spread the SOOMHz.
\fixed-Signal Circuit Design Chapter 9 A High-Speed Data Converter 313
~~~.--------~~
rer seen in Fig. 9.12 but with

This increases the word size ~~ ~~~------~---
z (so the total attenuation at
~ H(z) r;-~ ~3 : n.. . ._ __ ---'-7--_
Jpo!ogy, for very high-speed
~~4_,~~n~----~-
t~. For a genera! design, we'll
:htforward to minimize. The '0 H(z)
••
~~ ••
•
e use of biquad filters for
~.~~)
~8 8 ~l
.:.
Kpath 8
Ca) 8 modulators in parallel
fz v.e get the noise transfer H(z) Vin(Z)·z-l+ (l-z-I). VQe(f)
Ir ~f,). While we are used to
fHz here), we know that any
sampling frequency,!,. The ~lK JL..h--.SLS
ng Kavg 8. Note that we are ~2K~
for removing the modulation ~
.8). Figure 9.l9b shows the TsIKpafh
1.l9c shows the single path (b) Equivalent circuit

rlapping clock signals). H(ZKpd'h) =Vin(Z) . Z-Kpdlh + (1 - Z-Kpalh) . VQe(/)
is "" 100 }'fHz

2 12ls,new 121s . Kpalh
/VQe(f)1 , V21Hz Is,new = 800 kfHz
I
./\D,
-+-
I I I l- I I I )
> 100 200 300 400 500 600 700 800 MHz
500 700 800 MHz (c) Quantization noise for an 8-path topology clocked 100 MHz, compare to Fig. 9.19b.
)cked at 100 MHz, Fig. 7.6.
2
NTF(f)
~
INTF(f) I • 8. i21s
ineZ) . Z-l + (1- z-l) . VQe(f)
L O"i"d 'p,,!rum ??1

. 100 MHz
)cked at 100 MHz.
..k ~ ~ ~-t--I---+I---+I---II----+I-~)o
: 50 100
I I
200
i
300 400 500 600 700 800 MHz
6.25 (d) Modulation noise of 8-path topology above.
rst-order NS modulator
Figure 9.20 Eight moduLators in parallel (a time-interLeaved topology).
n in Fig. 9.20 (modified from quantization noise out over a wider range of frequencies, (c). This reduces the modulation
ator is clocked at!" the same noise added to our signal in the bandwidth from DC to 6.25 MHz as seen in Fig. 9.20d. If
e show the equivalent circuit, our desired signal bandwidth remains at 6.25 MHz then we will 'clearly get an
circuit's output changes with improvement in SNR. Note that the output of the topology is I-bit changing at a rate of
)ck frequency we spread the 800 MHz.
314 CMOS Mixed-Signal Circuit Design Chapter 9 A High-Speed Dat
Suppose we want to use this topology for high-speed data conversion where we 9.1.5 Understanding the
use the fact that our effective output clock frequency is 800 MHz (and so the Nyquist
frequency is 400 MHz)? Is this possible or does it make sense? This is a good point to Notice that in Fig. 7.2 we us
remember the fundamentals. As mentioned on page 201, using noise-shaping does not our high-speed topology sef
result in a reduction in quantization noise. Rather, noise-shaping topologies push the strobe the comparator. For e)
quantization noise to frequencies outside the region of interest. Reviewing Fig. 9.20d we are clocked with <P1-I whill
see that (all of) our quantization noise is still present in the spectrum from DC to 400 captured on C, at the falling
the comparator. Since neal
MHz (see example below). It's impossible to reduce this noise with a digital filter without
effecting the desired signal in this same frequency range. associated with transferring
When the comparator makes
Example 9.3 with minimal delay, so that
Estimate the RMS value of the quantization noise for the 8-path topology clocked path's decision. The result is
at 100 MHz seen in Fig. 9.20d. topology clocked at Kpa'h ·Is
V~e,RMs == I
4/,
INTF(f) I
2
• 8~~~Is . df ==
2
I
4(,
4· sin
2
(f)
11:
V2
1; . 8. ~~Is . df
In a practical imp lei
integrator and comparator
experiences a delay. The re~
this instability. In this exarr
== ViSB .J[I-COS(211:.L)].df == ViSB mV here, and the clock sign
4·12Is 0 Is 12 used for both the input pair
when using ideal componen'
or VQe,RMS == VLSB / Jl2 , no reduction in quantization noise. While this result was the input signal; however, v
derived for the case Kpolh == 8 the reader should see that the result is valid for any
shown, the oscillation is m
value of K po1h ' •
signals to minimize the df
always occurs at a high free
Example 9.4
the output of the modulator
Estimate SNR;deal for the topology seen in Fig. 9.20a.
Another example, bt
The procedure for calculating SNR was given in Sec. 5.2. Since we just calculated
that the average of the outp
the quantization noise, all that's left is to calculate the desired output signal power.
the clock signals applied to
If we apply a sinusoid to the topology with a peak amplitude of Vp , then adding
grows and shrinks. In tr
the output signal powers from each path results in Kpalh . V')I2. We can then write
comparator or through the ~
~.Vp/J2 into account when selectir
SNRideal == 20 . log ~ concern is the increase in
VLSB/" 12 (which can be reduced by ir
or (see Fig. 5.31)
1.0V I ,i I
SNRideal == 6.02N + l.76 + 10 log Kpalh (9.4) o·9Vi-- --~-t
For every doubling in the number of paths we get a 3-dB (0.5 bits) increase in the O.BVi· "r'
SNR. Such a modest increase in SNR is, generally, too insignificant for the
hardware costs so this approach isn't used .•
O.N
O.6V .... r'1"". ·
O.5V-f--r'-"-
The virtues of the topology seen in Fig. 9.4 should be clearer. Using a single O.4V
integrator (I-sigma) with K feedback paths (K-deltas) we can attain conversion O.3V
bandwidths approachingf)2 with reasonable resolutions. Since a single integrator is used,
common information is applied to the input of each quantizer. This allows the O.1V
quantization noise to be pushed to very high frequencies. In other terms, we get fast O.OV+-J--;--
Dns 1Dns
sampling by using K feedback paths while we are able to push the quantization noise to
higher frequencies using a single integrator common to all quantizers.
Figure 9.21 Sl
ixed-Signal Circuit Design Chapter 9 A High-Speed Data Converter 315
data conversion where we 9.1.5 Understanding the Clock Signals

MHz (and so the Nyquist
;e? This is a good point to Notice that in Fig. 7.2 we used q,] to clock both the input switches and the comparator. In
ing noise-shaping does not our high-speed topology seen in Fig. 9.4, however, we used an earlier clock signal to
aping topologies push the strobe the comparator. For example, examining the top path in Fig. 9.4, the input switches
t. Reviewing Fig. 9.20d we are clocked with q, I-I while the comparator is clocked with q,Z-I. The input signal is
spectrum from DC to 400 captured on Ci at the falling edge time of q, I-I. A very short time later, T)Kparlt' we clock
with a digital filter without the comparator. Since near-ideal components are used in our simulations the delay
associated with transferring the charge on Ci to the integrator's output is nearly zero.
When the comparator makes a decision it is immediately fed back to the integrator, again
with minimal delay, so that the next path's decision is directly dependent on the previous
l-path topology clocked path's decision. The result is the topology behaves like a single, first-order, noise-shaping
topology clocked at Kpath Is.
In a practical implementation of the modulator, however, the delay through the
integrator and comparator is finite and so the information fed back to the integrator
experiences a delay. The result is a built-in instability. Figure 9.21 shows an example of
this instability. In this example, the input signal is the DC common-mode voltage, 500
'4/= VZ<;B mV here, and the clock signals are selected so that, as in Fig. 7.2, the same clock signal is
12
used for both the input pair of switches and the comparator (the near-worst case situation
e. While this result was when using ideal components). The average value of the output signal does, indeed, equal
Ie result is valid for any the input signal; however, we have the unwanted oscillation seen in the figure. As we've
ShOW11, the oscillation is minimized (ideally removed) by proper selection of the clock
signals to minimize the delay feeding back the output signals. Since this oscillation
always occurs at a high frequency, a multiple of the clock frequency, the digital filter on
the output of the modulator removes it.
Since we just calculated Another example, but with an AC input signal, is seen in Fig. 9.22. Notice, again,
red output signal power. that the average of the output does equal the input signal. It can be instructive to change
tude of Vp , then adding the clock signals applied to the comparators in the modulator to show how this oscillation
];12. We can then write grows and shrinks. In the practical implementation the finite delay through the
comparator or through the switches charging or discharging the capacitors must be taken
0. into account when selecting the clock phases for the comparators. Another practical
concern is the increase in the output swing of the integrator because of this instability
(which can be reduced by increasing the size of the integrator's feedback capacitor).
(9.4)
:0.5 bits) increase in the
)0 insignificant for the
be clearer. Using a single

we can attain conversion
::: a single integrator is used,
uantizer. This allows the
n other terms, we get fast
;h the quantization noise to
ntizers.
Figure 9.21 Showing built-in instability in the high-speed modulator.
316 CMOS Mixed-Signal Circuit Design Chapter 9 A High-Speed Data (
1.0V-,,--...,.,....-n-~=------,r-T---,-·~-~-····--+--'-=---:-
D.SY
D.7V
O.SV
D.SY
OAV
O.3V
O.ZV
Figure 9.24 Ring oscill:
O.W
O.OV+----+---jL-L-.lj---+-.JL--i--···-r----r----'---'t--'------r--'-----'-'l
Ons JOns 60ns 90ns 120ns 150no 180ns 210ns 240n5 270ns JOOns process. Note that the frequen
inverters in the delay stage. A
Figure 9.22 Showing built-in instability with a sinewave input signal. 200 MHz (lower for a simu
sampled at a rate offs.nev.. or 1.t
then decimated, 9.7a.
9.2 Practical Implementation
:~lffi
In this section we'll discuss the practical implementation of the high-speed topology
proposed in this book. The goal of this section is to provide discussions and provoke
thought that should prove helpful when designing a converter using this topology. The
:~~i~·:::nf:
goal is not to provide definitive solutions for specific applications. This endeavor is left
for discovery by the engineers and researchers doing mixed-signal circuit design.
12V -- •. -,-'-
9.2.1 Generating the Clock Signals lOV .-- ---- :- ••
8V -- .-.--- ---
Generating the 16 clock signals needed for the topology seen in Fig. 9.4 can be 6V ----.-.
challenging. We could use a delay-locked loop (DLL) that takes an input clock signal and
generates the 16 clock signals (but that adds complexity). Here we use a ring oscillator
that runs asynchronously with an external clock signal. Figure 9.23 shows the basic delay
01f?E
-zv i i
stage schematic and icon used in thc oscillator. Figure 9.24 shows the complete ring Dns 30s
oscillator while Fig. 9.25 shows some simulation results in a 500 nm, 5-V, CMOS
Figure 9.25
Figure 9.26 shows hI

clocks can be interfaced usin
running faster than the ext
synchronizer doesn't introdu
processes digital signals. Aft
ring oscillator is a practical
Ring oscillators are certainl
notice that by combining the
jitter by Kpo1h' see, for examp
clock signal. Slow variation:
no affect on the data convert
simply vary the sampling
differences in the internal
decimating, should be tal
Figure 9.23 Delay stage used in the ring oscillator, schematic and icon. metastability concerns, e.g.,
goes high resulting in a glitcl
Mixed-Signal Circuit Desif:,'11 Chapter 9 A High-Speed Data Converter 317
Figure 9.24 oscillator, schematic and icon, for use with the data converter.
process. Note that the frequency of the oscillator can be adjusted by adding or removing
inverters in the delay stage. Also notice that the simulated oscillation frequency is around
\ ave input 200 MHz (lower for a simulation with layout parasitics). The analog input signal is
sampled at a rate ofIs.new or 1.6 GHz. The 8 path outputs are added together, Fig. 9.4, and
then decimated, Fig. 9.7a.
of the high-speed topology

de diseussions and provoke
ter using this topology. The
ations. This endeavor is left
ignal circuit design.
f seen in Fig. 9.4 can be

ces an input clock signal and
[ere we use a ring oscillator
e 9.23 shows the basie delay
~4 shows the complete ring
in a 500 nm, 5-V, CMOS
Figure 9.25 Simulating the oscillator in a 500 nm process.
Figure 9.26 shows how the external (synchronous) and internal (asynchronous)
clocks can be interfaced using a synchronizer. We are assuming that the internal clock is
running faster than the external clock (so the output is decimated). Note that the
synchronizer doesn't introduce aperture jitter as discussed in Sec. 5.2.1 since it only
proeesses digital signals. After reviewing this section, however, we might wonder if the
ring oscillator is a practical choice for providing the clock signals to the data converter.
Ring oscillators are certainly not as stable as crystal-controlled oscillators. However,
notice that by combining the Kpalh outputs together we reduce the variance of the aperture
jitter by K,""lh' see, for example, Eq. (5.30). Further filtering reduces the effects of a jittery
clock signal. Slow variations in VDD, ground, or temperature will also have essentially
no affect on the data converter's performance (via the ring oscillator) since these changes
simply vary the sampling rate (the internal clock frequency). Note that for large
differences in the internal and external cloek frequencies aliasing concerns, when
decimating, should be taken into consideration in the synchronizer (as should
:hematic and icon. metastability concerns, e.g., the external clock (not) going low just after the internal clock
goes high resulting in a glitch on the output of the AND in Fig. 9.26).
1, Chapter 9 A High-Speed Data
Synchronizer
In Digital
Analog Filter ~.DQ Out
T
External clock
Internal clock,
clocked with ring oscillator, Fig. 9.24. External clock (not)
Internal clock
Irm=:
Figure 9.26 Synchronizing the external and internal clock signals.
Ou(rn
9.2.2 The Components

The Switched-Capacitors
Figure 9.27 shows the schematic and the icon for the switched-capacitors used in the FigUJ
modulator. The concerns, when selecting the widths of the MOSFETs, as discussed on
pages 302 and 307, are that the capacitors can be charged/discharged within T/Kpafh ' The
effective resistances of each MOSFET in Fig. 9.27 is 500 n. Since two MOSFETs are in
parallel with switches on each side of the 100 fF capacitor, the time constant is 50 ps.
:
Finally, the size of the capacitors used in this circuit, as discussed on page 307, is set by
thermal noise considerations.
2.55V
i
m
2.53\1 ....... ~ ....... ~
2.51\1 .... · .. j·..··.. ·i

2.49\1 ...... +.--.. ~
2.47\1 ...... +------~
2.45V ' •
nnr; ?n~ 1Jir:
Figure 9.29 Simulating
The Clocked Comparator

The schematic and icon of th
Figure 9.27 Schematic and icon of the switched-capacitors used in the modulator. The input clock signal is sha
comparator is reduced and tl
The Amplflier decision can be made). The l
No DC current flows in the
Figure 9.28 shows the schematic and icon for a self-biased amplifier. This topology was signal changes states. The }.
picked because it's simple and fast. Further, for the comparator discussed next, the changes states (only) on the
outputs are complementary and generated from NMOS devices (which interface nicely NAND gates are buffered u
with the comparator's inputs). Simulation results are seen in Fig. 9.29. The non-inverting these outputs don't fully char
amplifier input is held at 2.5 V while the inverting input is pulsed from 2.45 to 2.55 V these gates droops or bounc
(100 mV change). The output changes from roughly 2.8 to 0.8 (2 V change) so the gain is nonlinearity. Finally, the inpl
20 (which should be larger than Kpafh or 8 here). Both outputs of the amplifier are loaded, of the NMOS device but n01
in the simulation, with 400fF capacitors. Our concern, Sec. 7.1.8, is that we don't see Note, as discussed already, t
slewing in the response. The amplifier sizes picked here are larger than required for our through the comparator (and,
final design (so power is wasted).
Synchronizer
Out Inpf~tP
i
External clock
Inffl~tm
External clock (not)

:rnal clock
nal clock signals.
tehed-capacitors used in the Figure .9.28 Self-biased amplifier and icon.

MOSFETs, as discussed on
ischarged within T/K path ' The
. Since two MOSFETs are in
~, the time constant is 50 ps.
:ussed on page 307, is set by Amplifier outputs
Amplifier inputs
Figure 9.29 Simulating the operation ofthe amplifier in Fig. 9.28 with 400 if loads.
The Clocked Comparator

The schematic and icon of the clocked comparator used in the design is seen in Fig. 9.30.
rs used in the modulator. The input clock signal is sharpened and buffered up so that the input capacitance of the
comparator is reduced and the edges in the comparator are fast (so that a good, reliable,
decision can be made). The basic latch is formed with cross-coupled inverters (as usual).
No DC current flows in the comparator. Current is pulled from VDD when the clock
amplifier. This topology was
signal changes states. The NAND gates are used to ensure that the comparator output
nparator discussed next, the
changes states (only) on the rising edge of the input clock signal. The outputs of the
vices (which interface nicely
NAND gates are buffered up to ensure that they can drive the switched-capacitors. If
Fig. 9.29. The non-inverting
these outputs don't fully charge the switched-capacitors or the VDD/ground connected to
; pulsed from 2.45 to 2.55 V
these gates droops or bounces, the feedback signal will be affected causing noise and
.8 (2 V change) so the gain is
nonlinearity. Finally, the inputs to the comparator should be above the threshold voltage
ts of the amplifier are loaded,
of the NMOS device but not so large that the input devices are pushed into deep triode.
:c. 7.1.8, is that we don't see
Note, as discussed already, that we need to be careful to ensure minimal forward delay
e larger than required for our
through the comparator (and, of course, the integrator).

·_-_...... _ - -

1
Chapter 9 A High-Speed Data {
elk
Inp~ t.c""",
InN _ . bar
Figure 9.30 Clocked comparator and icon.
Figul
synchronize the output data to

at the rate of the ring oscilh
frequency of (roughly) 200 M
9.34 shows the simulation re:
signal is 10 MHz (same as Fi:
input conversion rates are comparar
input 500 nm CMOS process (even 1
Figure 9.31 Simulating the operation of the comparator in Fig. 9.30.
9.2.3 The ADC

Figure 9.32 shows the schematic of the high-speed ADC (minus the digital filter) we
designed in this section using a 500 nm CMOS process with a VDD of 5 V. The resistors
are used (for SPICE simulations) to provide a simple method of summing the digital
outputs for ease of viewing. While they are useful for speeding up the simulation, they are
not useful for looking at the performance of the converter. The finite transition times,
glitches, etc. in the digital data limit their usefulness when viewing analog data. Figure On. 30no 60
9.33 shows the results of simulating the ADC with a 10 MHz input signal.
At this point, in order to characterize the behavior of the ADC, we need to add the Figure 9.33 Simulat
digital filter to the modulator's output. Ideally the K-delta-I-sigma topology seen in Fig.
9.4 behaves like a single, first-order, noise-shaping modulator clocked atrs,new Figure 9.35 shows a
• Kpath or 1.6 GHz here) with a I-bit output (we selectively connect each path's transitions from 0 to VDD in 1
output to the overall topology's output every TsIKputh seconds). Let's use the decimator should be shifted 50 ns later
and filter seen in Fig. 9.10, but with, as discussed in Sec. 7J .3, L = 2 (the adder and only course, the ADC's output wi
one Sinc filter). The final output word size is 7-bits, the effective I-bit output by the start-up transient). We can es·
6
modulator and then 3-bits (each) for the addition and the Sinc filter. We won't VDDI2 6 or 78 mY. We use 2
of the filter) because in ord
vlixed-Signal Circuit Design Chapter 9 A High-Speed Data Converter 321
elk
1
~bar
on.
Figure 9.32 K-delta-l-sigma modulator.
..
• T· - - - - - - ~ - - - - - - -..,
•....... , ...... .
-: ------- ~- ------ Output synchronize the output data to an external clock. This means that the output will change
at the rate of the ring oscillator (roughly every 5 ns or 200 MHz). An input signal
..
clock frequency of (roughly) 200 MHz/16 or 12.5 MHz will be attenuated by -3.9 dB. Figure
9.34 shows the simulation results for the ADC (modulator and filter) when the input
signal is 10 MHz (same as Fig. 9.33 but showing the output of the digital filter). These
8
1 ............. ..
.;.......L....
. .
+ input
+--.
conversion rates are comparable to any high-speed converter topology implemented in a
.i....... i........ - mput
500 nm CMOS process (even faster if we use less decimation early in the digital filter) .
-,-------,-------
IOns 4S0ns SOOns S.Sv·~_~_......"V(v.:.:i:.:!.nl_ _ _ _ _ _ _ _V""(s:.:u.::.:m,,,,_d=l-I_ _ _~
S.OV
itor in Fig. 9.30. 4.SV
4.0V
3.SV
3.0V
minus the digital filter) we 2.SV
2.0V
:l VDD of 5 Y. The resistors
1.SV
lod of summing the digital 1.0V
g up the simulation, they are O.SV
The finite transition times, O.OV
riewing analog data. Figure -O.svr+---i---i---i---i---i---i---i---i--';--
Ons 30n5 60ns 90ns 120n5 150n5 180ns 210ns 240n5 270n5 JOOns
input signal.
ile ADC, we need to add the Figure 9.33 Simulating the ADC in Fig. 9.32 with a 10 MHz input signal.
,igma topology seen in Fig.
ldulator clocked at Is.new Figure 9.35 shows a simulation where the ADC's input is a ramp signal that
:tively connect each path's transitions from 0 to VDD in 1 )..ls. The delay through the filter is 50 ns so the input signal
is). Let's use the decimator should be shifted 50 ns later in time when comparing the ADC's input to its output. Of
3, L = 2 (the adder and only course, the ADC's output will then be valid only after this delay (so we neglect the
ffective I-bit output by the start-up transient). We can estimate the minimum step size in the output of the ADC as
the Sinc filter. We won't VDD!2 6 or 78 mY. We use 26 instead of2 7 (the exponent is the number of bits coming out
of the filter) because in order for the output signal to swing rail-to-rail we have to
...~.;:1·';~'
..
,,-;
~;
~.-;1
~.".
1i
--- - - - - -
l
322 CMOS Mixed-Signal Circuit Design i Chapter 9 A High-Speed Data C
I QUESTIONS
II
~.OV
9.1 What is a time-interlea\
3.5V
different from the K-I
implementation of a
3.0V
Delta-Sigma modulators
2.5V
2.0V
1.5V
I 9.2 Using the modulator fro
the K- Delta-I-Sigma top
1.0V ------+-- 9.3 Repeat question 9.2 but
0.5V integrator isn't critical
O.OV-t---i---i---i---i---i---;---i---;---;------1 converter using differenl
Dns 30n5 60ns 90ns 120n5 150n5 180ns 210ns 2040n5 270n5 300n5
9.4 Show the details of (der

Figure 9.34 Same as Fig. 9.33 (l0 MHz input) but looking at the output of the digital filter. modulator) how the patt
5.0V,--_-,----_...,..-'-'VI=oU"'IJ-,---_-,---_-,---_--,--_--,--:-VI"-vi""nJ'-;-_--,------::?l
,
.. .
~.5V -- - -- - - j--. -----;"- ----. --~ ------. ~ ------- -;- --. ----~ -------j-------;
" ,
Explain how this filter
outputs. Does this filter
:::FFt'j.'."L 9.5 Sketch the decimate by

Ensure the proper clock
:: ·····,·····'"iiFI 9.6 Explain, in your own v

3-bit Flash converter
improvement in SNR as
:::~ --- ---1-' -::::T::-:::: t::::::::::::::::::::::::: t::::::::::::::: I::::::: t:::::::
9.7 What is the frequency n
o.ov--jL--i---i---i---i---i---i---i---i----r---i
o.o~s 0.1 ~s 0.2~s 0.3~s O.~~s 0.5~s 0.6~s 0.7~s 0.8~s 0.9~s 1.0~s
Figure 9.35 Simulating the modulator with a ramp input signal. Shift
input later in time by 50 ns to compare to output. 9.9 What is the frequency n
multiply it by two before applying it to the ideal DAC used to display the digital data as
an analog output voltage (as discussed earlier). 9.11 Show how the switche~
seen in Fig. 9.20 can be
Remember that increasing the output word size (increasing resolution) requires
additional filtering. Also, again, recall that to increase the signal conversion bandwidth
we need to reduce the amount of decimation used immediately following the modulator
and prior to the adder that sums the Kpa'h outputs together (see Fig. 9.7b for the decimate
by Kpa'hl2 example).
9.3 Conclusion
This chapter has proposed a new topology for high-speed analog-to-digital conversion
using the mixed-signal circuit design techniques presented in this book. The topology
should prove useful when designing high-speed ADCs in nanometer CMOS. Future work
where z = e j2 1[jT, . Usin
can be focused in many areas including, but not limited to: fully-differential signal paths,
paths in parallel, Fig
the integrator (amplifier) design, higher-order (perhaps passive, Sec. 6.2.1) topologies,
topology's outputs.
bandpass converters, segmenting feedback paths, digital calibration (e.g. for offset, Sec.
7.1.9) and the design of the digital filter (including the decimating stage).
QUESTIONS
9.1 What is a time-interleaved data converter? Why is a time-interleaved converter
different from the K-Delta-l-Sigma converter seen in Fig. 9.4? Sketch the
implementation of a time-interleaved data converter implemented with
Delta-Sigma modulators. Also sketch the clock signals used in the topology.
9.2 Using the modulator from Ex. 9.1 show that capacitor matching isn't important in
the K-Delta-l-Sigma topology.
9.3 Repeat question 9.2 but show that thc opcn-Ioop gain of the amplifier used in the
integrator isn't critical (compare, using simulations, the performance of the
converter using different gains).
to.ns 270ns 300n5
9.4 Show the details of (derive from the time-domain outputs of the K-Delta-l-Sigma
.he output of the digital filter, modulator) how the path filter seen in Fig. 9.4 has a z-domain transfer function of
1 Z-8
I
Explain how this filter performs a moving-average filtering of the modulator's
outputs. Does this filter decimate the K-Delta-l-Sigma outputs? Why or why not?
9.5 Sketch the decimate by Ki4 topology similar to the topologies seen in 9.7.
Ensure the proper clock signals are used in your sketch.
9.6 Explain, in your own words, why oversampling (averaging the outputs) using a
3-bit Flash converter (eight comparators), won't result in as significant
improvement in SNR as the K-Delta-I-Sigma topology.
9.7 What is the frequency response (an equation) of the filter seen in Fig. 9.1 0'1
9.8 What is the frequency response (an equation) of the filter seen in Fig. 9.12'1
p input signal. Shift
re to output. 9.9 What is the frequency response (an equation) ofthe filter seen in Fig. 9.14?
9.10 What is the frequency response (an equation) of the filter seen in Fig. 9.16?
to display the digital data as
9.11 Show how the switches on the inputs and outputs of the 8 modulators in parallel
seen in Fig. 9.20 can be described using the unit matrix and delays or
)reasing resolution) requires
.ignal conversion bandwidth 1 0 0 0 0 0 0 0
ely following the modulator o1 0 0 0 0 0 0 Z-118
:e Fig. 9.7b for the decimate 001 0 0 0 0 0 z·218
000 I 0 000 z-3/8
o 000 I 000 Z-4/8
o0 0 0 0 I 0 0
analog-to-digital conversion 0000001 0
in this book. The topology o0 0 0 0 0 0 I
lometer CMOS. Future work
lIly-differential signal paths, where z = . Using these relationships show how to relate the inputs of the K
sive, Sec. 6.2.1) topologies, paths in parallel, Fig. 9.20, to the transfer function H(z) and the resulting
,bration (e.g. for offset, Sec. topology's outputs.
iting stage).
9.12 In the previous question we showed that we can think of the switches on the input
or output of the K-path topology as multiplying the signals by I or O. Let's take
this a step further and ask "What can we accomplish if we multiply the signals by
I, 0, or -I (the analog multiplication by -I is implemented by swapping the
fully-differential amplifier's inputs)?" Reviewing Fig. 8.19 from the last chapter
Index
we see that proper selection and sequence of these multiplying terms can result in
modulating or demodulating our signals. Remembering that our (desired) analog
input spectrum extends from DC to some frequency B (lowpass data conversion)
we see that this movement of the spectrum is undesirable since it moves our
desired input signal spectrum directly up into the larger-amplitude modulation A
noise after it's passed through the modulator (again assuming a lowpass modulator
AAF. See Antialiasing filter.
is used). This makes the signal difficult to recover and lowers the topology's SNR. Accumulate-and-dump circuit, 129,
Perform a literature search and comment on these problems ensuring that your Accumulator, 19, 129, 134,235-236
understanding of the issues is clear and that you've referenced the literature used Accuracy, 195,200,269
to formulate your ideas. Activc-RC Integrator, 73, 75,
filter, 80, 82-83, 87-88,97-98,
9.13 The effective sampling frequency of the K-Delta-l-Sigma ADC discussed in Sec. 109, 112, 11 6
9.2 is roughly 1.6 GHz. Can any component of the ADC operate at, or be clocked Adaptive filtering, 93
ADe. See Analog-to-digital convert.
at, 1.6 GHz? Verify your answers using SPICE and the 500 nm, 5 V, CMOS
Adder, 94, 126, 145, 147, 151, 156,
models used to generate these figures. What is the most critical component then, 309,320,322
from a timing perspective, (the DFF used to capture the eight bits coming out of Aliasing, 21, 27-72, 93, 127-129, 1~
the modulators) and what is critical in that component (the DFF's setup and hold 306,317
times)? What happens if an error is made in the most critical component? (The quantization noise, 169
Amplitude modulation, 285, 324
wrong count is captured. For example, we should capture 6 logic Is but we Analog RC filter, 80, 82-83, 87-88,
actually capture 5 or 7 logic Is. Since we have a significant amount of averaging 103-106,109,112,116
in the digital filter the effects should be small. If an equal number of positive and Analog Sinc averaging filter, 10-11
negative errors are made the errors average to zero and don't affect the converter's Analog-to-digital eonverter (ADC),
performance. ) 164-224,225-284
I-bit, 236
bandpass, 134,287-300
gain, 246
high-speed, 301-324
Nyquist-rate, 43, 63,220-225,
pipeline, 38
SPICE models for. 119-123, It
Antenna. 292
Antialiasing filter (AM). 27-40. 7'::
198-199,203,205-206,302
Aperture jitter, 179,202, 317
Autocorrelation function (ACF), 1~
Autozeroing, 57-58, 62, 71
Average power, 183-187, 198
Average value, 44,168,183-187,2
315
Averaging,
bandpass filter, ) 9, 134-139, 1
clock jitter, 198
decimation, 209-211
filter, 13-14, 126, 131, 133-13
234,239-241,266-267
highpass filter, 19, 129, 134
improving signal-to-noise rati,
190-194
Averaging (continued),
interpolating filter, 43-50, 71, 139-142, 199,
235, 273
Index limiting bandwidth, 13-14

linearity requirements, 194-195
noise, 250
quantization noise, 202, 211
without decimation, 132-133
B
A B, bandwidth of the input signal, 129-130, 133-134,
AAF. See Antialiasing filter. 182, 198-199, 208-209, 212, 220, 229,
Accumulate-and-dump circuit, 129, 132 237-241, 248, 250, 267, 285, 290, 296, 324
Accumulator, 19, 129, 134, 235-236 B device. See Nonlinear-dependent source.
Accuracy, 195, 200, 269 Bandpass filter, 19, 96, 103-111, 129, 134-139, 160
Active-RC Integrator, 73, 75, Bandpass modulators, 263, 285-298, 301, 324
filter, 80, 82-83, 87-88, 97-98, 101, 103-106, Bennett’s criteria, 165-166
109, 112, 116 Bilinear transfer function, 95
Adaptive filtering, 93 Binary offset, 123-125, 204-205, 274
ADC. See Analog-to-digital converter. Biquad filters, 73, 99-101
Adder, 94, 126, 145, 147, 151, 156, 158-159, 273, Biquadratic transfer function, 99
309, 320, 322 Bottom plate of a capacitor, 67
Aliasing, 21, 27-72, 93, 127-129, 140, 143-144, Bottom plate sampling, 39-40, 54, 219
306, 317
quantization noise, 169
Amplitude modulation, 187, 207, 285, 288, 315 C
Analog RC filter, 80, 82-83, 87-88, 97-98, 101,
103-106, 109, 112, 116 CAI, See continuous-time analog integrator.
Analog Sinc averaging filter, 10-11 Calibration, 322
Analog-to-digital converter (ADC), 21, 27, 94, Canonic digital filter, See Digital filter.
164-224, 225-284 Capacitance,
1-bit, 236 bottom plate, 54
bandpass, 134, 287-300 input, 86, 93, 247, 282, 319
gain, 246 load, 88-89
high-speed, 301-324 noise calculation, 307
Nyquist-rate, 43, 63, 220-225, 241, 306-308 parasitic, 66, 69, 83-84, 219, 279-281
pipeline, 38 Capacitive feedthrough, 39, 251, 257
SPICE models for, 119-123, 160, 176 Cascade of integrators and combs filters (CIC
Antenna, 292 filters), 142
Antialiasing filter (AAF), 27-40, 73, 93, 139, 144, Cascaded modulators, 233, 264, 275-280
198-199, 203, 205-206, 302 Charge injection, 39-40, 251, 257, 294
Aperture jitter, 179, 202, 317 Charge pump, 120
Autocorrelation function (ACF), 183 Chopper stabilization, 71
Autozeroing, 57-58, 62, 71 CIC filters, see Cascade of integrators and combs
Average power, 183-187, 198 filters
Average value, 44, 168, 183-187, 200, 212, 244, Clock generation, 53, 316-318
315 Clock jitter, 178-189
Averaging, Coherent sampling, 175-176, 202
bandpass filter, 19, 134-139, 160, 290-292 Comb filter, 8-21, 25, 129-131, 133-143, 224
clock jitter, 198 Common-mode feedback (CMFB), 60-61, 88-89
decimation, 209-211 Common-mode rejection ratio (CMRR), 87, 252
filter, 13-14, 126, 131, 133-134, 201, 220, 223, Common-mode voltage, VCM = 500 mV in this book
234, 239-241, 266-267 Comparator,
highpass filter, 19, 129, 134 clocked, 163, 319-320
improving signal-to-noise ratio (SNR), 13, gain, 244-246, 259, 262-263, 295
190-194 hysteresis, 246-247
326 Index
Comparator (continued),
LSB, 204 E
noise, 163, 246-247, 250
offset, 246-247 Effective number of bits, Neff , 173, 176, 179,
placement, 261 181-182, 188, 202
Constant delay, 10, 31, 145, 171 Error feedback, 235, 271-275, 283
Continuous-time analog integrator (CAI), 73, 75, 95 Expected value, 186
Continuous-time comb filter, 10-11
Continuous-time Fourier transform, 23
Convolution, 35, 175 F
Correlated double sampling (CDS), 59, 66, 71
Cosine window. See Hanning window. Feedback gains in a DAI, 260
Counter, 45, 126-129, 130, 270-271 Filters,
active-RC, 75
accumulate and dump, 129
D bandpass, 19, 96, 103-111, 129, 134-139, 160
DAC. See Digital-to-analog converter. bilinear, 95
DAI. See Discrete analog integrator. biquad, 73, 99-101
dBc (decibels with respect to the carrier), 177, 189 comb filter, 8-21, 25, 129-131, 133-143, 224
Dead zones, 215, 217, 232 decimating filters, 143-144, 157, 203, 239
Decimation, 33-34, 127-129, 132, 222-223, digital. See Digital filter.
306-312, 321-322 exact frequency response of discrete-time filter,
bandwidth limitations, 34 94
decimating filter, 143-144, 157, 203, 239 finite impulse response (FIR), 133-134,
Delta modulation, 199 145-146, 161
Delta-sigma modulation, 199, 233-234 See gm-C filters. See transconductor-C filter.
noise-shaping. highpass, 19, 129, 134
Demodulator, 199-200, 235-236, 271-272 in a higher-order modulator, 267
Diff-amp, 61, 86, 89, 222 infinite impulse response (IIR), 134
Differentiator, 14-15, 119, 275-276 integrating filters, 73-118
Digital averaging filter, 192, 220 interpolating filters, 139-142
Digital comb filter, 11-18 ladder filter, 117-118
Digital filter, 119-162 lowpass, 75
biquad, 155-159 MOSFET-C, 83
canonic, 151-155 Q peaking and instability, 112
finite impulse response (FIR), 133-134, Sinc, 133
145-146, 161 SNR, 82-83, 87
infinite impulse response (IIR), 134 stability in digital filters, 146
stability, 146-147 switched-capacitor, 90-95
Digital integrator, 19-21, 235 transconductor-C filter, 97
Digital I/Q extraction to baseband, 297-298 tuning, 80, 83, 86, 93, 98
Digital resonator, 134-139, 160 Finite impulse response (FIR) filter, 133-134,
Digital signal processing (DSP), 27, 32, 203 145-146, 161
Digital-to-analog converter (DAC), 69, 119-123, Finite op-amp gain-bandwidth product, 55-57,
204-205, 213-214, 235-236, 272-275 78-79
Dirac delta impulse, 23, 28 First-order noise shaping, 208, 210, 224, 233, 238,
Discrete analog integrator (DAI), 66-70, 90-93, 254
233, 251, 260 FIR. See Finite impulse response.
Discrete-time integrator, 90-95 Forward modulator gain, 243
Distortion, 35, 37, 49, 65, 71, 176-178, 187, Fourier series, 23
206-208, 213-214, 225-226, 249, 251-252, 269, Fourier transform, 24
273, 288-289
Dither, 166, 195-198, 242, 282
Droop, 37, 39-41, 47-48, 127, 129, 132, 142, 157, G
209, 212, 223, 241, 267
DSP. See Digital signal processing. Gain error term, 176-177, 204, 213-214, 219,
Dynamic range, 83, 177, 251, 276, 279 247-249, 280
gm-C (transconductor-C) integrators, 86-90
Gaussian probability distribution, 187, 197
Index 327
H M
Hanning window, 175 MASH modulator. See Noise-shaping
Harmonics, Matching, 53, 55, 94, 200, 211, 212, 230, 279, 323
square wave, 189 Matlab, 171
High-frequency transconductor, 89-90 Mean, 186
Highpass filter, 19, 129, 134 Miller integrator, 75
Higher order modulators, 267 Mixed-signal system block diagram, 27
Hold register, 46-50 Modulation noise, 206-208, 212, 237
Hysteresis, 246-247 Modulator,
bandpass, 287-297
I cascaded, 275
first-order, 233
I, in phase or real component, 4-6, 285-286, gain, 243
297-299 higher-order, 265-269
IIR. See Infinite impulse response filter. interpolative, 271-272
Impulse sampling, 28-31 multibit, 269
Infinite impulse response (IIR) filter, 134 noise-shaping, 199-201, 233
Integrator, predictive, 200
analog. See Continuous-time analog integrator. second-order, 253
digital, 19-21, 235 MOSFET-C Integrators, 83-85
discrete analog integrator (DAI), 66-70, 90-93, Multibit modulators, 269
233, 251 Multiplexer (MUX), 236, 297
gain, 113, 244-246, 248, 255, 257-260, 264, Multipliers, 34, 64, 94, 291, 297-298
276, 303 Multistage noise shaping modulator (MASH), 275
leakage, 247-248, 282 MUX. See Multiplexer.
Interpolation, 32, 43-46, 48-50, 71, 139-142, 235,
273
Interpolative modulators, 271-272 N
Inverse Fourier transform, 23
Noise,
averaging, 190
J clock jitter,
correlated double sampling (CDS), 59, 66, 71
Jitter. See Clock jitter. modulation, 206-208, 212
quantization noise, See Quantization noise.
Noise transfer function (NTF), 200-201, 205-208,
K 224, 233, 253-254
Noise-shaping (NS), 199-201, 233, 253
K, oversampling ratio, averaging factor, or Non-overlapping clock generation, 51, 53, 304, 317
interpolation increase, 33, 43-50 Nonrecursive filters, 133
clock jitter, 181-182 Number representation, 123-126
K-Delta-1-Sigma, xvi, 222, 303-304, 320-324 Nyquist,
K-path, Kpath, 50-53, 220-224, 228, 230, 301-302, differences between noise-shaping converters,
317 241
frequency, 17, 21, 27, 29, 31, 37-40
rate ADC, 43, 63, 220-225, 241, 306-308
L
Ladder filter, 117-118 O
Least significant bit (LSB), 119, 204 Offset,
Limit cycle oscillations, 241, 315 autozero, 57-59, 62
Linear phase, 25, 30-31, 145 comparator, 221-222, 224, 246
Linearity, 212, 214 DAC, 214
Linearity requirements for averaging, 191-195 op-amp, 54-55, 58-62, 66, 72, 212, 247-250
Lowpass filters, 73-74 Offset binary format, 123-125, 204-205, 274
LSB. See Least significant bit.
328 Index
Overflow, 124-126, 143, 145-148, 211, 214-215,

221, 273 R
Oversampling,
Oversampling ratio. See K, oversampling ratio Random signals, 185, 196, 216
or averaging factor. quantization noise, 168-169
spectral density, 190
standard deviation, 186
P variance, 186
RCF. See Reconstruction filter.
Passive noise-shaping, 205-207, 216-219 Reconstruction filter (RCF), 27, 29, 32, 39, 87, 166,
Path settling time, 302 139, 185, 187, 235, 273
Pattern noise, 241 Resolution, 13, 56-57, 83, 176, 191, 194-195,
PDF, probability density function, 185 199-200, 203, 209-210, 215, 230, 237-240,
average value (mean or expected value), 186 253-254, 265, 269, 273, 306-307, 322
Gaussian, 186-187, 197-198 loss because of jitter, 178-181
standard deviation, 186 Return-to-zero (RZ), 35, 37, 39, 42
variance, 186 Ripple, 241-242, 282, 288-289
Phase-delay relationship, 4 RMS quantization noise voltage, 166, 168-170, 211,
Phase, 237, 249, 253, 266-267
discrete analog integrator (DAI), calculating from a spectrum, 185, 187, 193
digital filter, 10-11, 13-15, 17-21, 130, 151 Root mean square (RMS) voltage, 168
linear, 9, 30-31, 145, 171 RZ. See Return-to-zero.
noise, 188-189
response, 76, 79-81, 88, 104
shift, 4-5, 8, 95-96, 141 S
Phase-locked loop, 180
Pipeline ADC, 38, 122, 176, 220, 307 Sample and hold (S/H), 27, 35-43, 54-66
PLL. See Phase-locked loop. matching of the capacitors used,
Power single-ended to differential, 65
average, 183-184, 186-187 subtraction, 63
Power spectral density (PSD), 166, 172, 183, 188, Sample frequency reduction. See Decimation.
190, 193 Sampler, 28-35
jitter, 186-189, 198 Sampling and Aliasing,
quantization noise, 166, 168, 193 coherent. See coherent sampling.
Predictive coder. See Predictive modulator. Sampling gate, 28
Predictive modulator, 199-200 Second-order noise-shaping, 227-229, 253
Probability density function, See PDF. Settling time, 57, 60-61, 221, 248-249, 302
PSD. See Power spectral density. SFDR. See Spurious-free-dynamic range.
SFFM. See Single frequency frequency modulation.
S/H. See Sample and hold.
Q Side lobes, 47-48
Sigma-delta modulation, See noise-shaping
Q (pole quality factor), 99-106 Signal-to-noise and distortion ratio(SINAD). See
high Q, 107-114, 117 Signal-to-noise plus distortion ratio (SNDR).
peaking and instability, 112-113 Signal-to-noise plus distortion ratio (SNDR), 93,
QAM, See Quadrature amplitude modulation. 176-178, 187, 197, 202
Quadrature amplitude modulation, 285 Signal-to-noise ratio (SNR), 70, 82-83, 87, 137,
Quadrature or imaginary component, 4-6, 285-290, 163-202, 208-229, 238-242, 247-248, 250-253,
297-299 265
Quantization noise, 122, 163-178, 185-196, 211, Signal transfer function (STF), 200-201, 205-206
224, 233-234, 237, 240, 242-243, 251, 253, Sinc filter, See digital averaging filter.
266, 273-276, 279, 312-314 Sinc function, 32, 36-39, 47-49
Quantize, 33 Sinc-shaped digital filter, 126-144
Quantizer, 43, 125, 163-164, 203-204, 235-239, Slew-rate, 57, 179, 248-249
269, 271-274, 314 Smoothing filter, See reconstruction filter.
SNR. See Signal-to-noise ratio.
SNDR. See Signal-to-noise plus distortion ratio.
Spike, 177
Index 329
Spurious free dynamic range (SFDR), 177, 242

Squarewave, 22, 25, 126-128, 166, 175 Z
Stability,
digital filter, 146 z
filter, 112 defined, 7, 12
noise-shaping modulator, 258-264, 269, 275, domain, 6-8
293 to s-transform (practical), 51, 149
Standard deviation, 186, 198 z-plane, 7, 15
Subtraction, 63, 126, 271 Zero-Order Hold (ZOH), 27
Switched-capacitor filters, 91-95, 98-99, 106-111 Zero padding, 44-45
Switches,
capacitive feedthrough, 39, 251
charge injection, 39-40, 251, 257, 294
MOSFET, 318
T
Taylor series, 6
T/H, See Track-and-hold.
Thermometer code, 308
Time-domain description of reconstruction, 31-33
Time-interleaved ADC, 220-222, 232, 313, 323
Track-and-hold, 41-43
Transconductor-C filters, 86
bilinear, 97
biquad, 114
Triangular response, 133
Tuning, 80, 83, 86
orthogonal tuning, 98
Two’s complement, 123-126, 131, 137, 147,
204-205
subtraction, 126
U
Unit step function. See u(t).
u(t), 35-36
V
Variance, 168, 186
VCM , (VDD/2 or 0.5 V in this book)
VDD, (1.0 V in this book)
Von Hann window. See Hanning window.
W
White noise, 169, 172, 269
Windowing, 175-176
Wireless, 285, 291
I/Q extraction, 297-298

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What is the book about?

What is the book about?

What topics are covered in the book?

What topics are covered in the book?

Complemented with practical examples and discussions, CMOS Mixed-Signal

Circuit Design, Second Edition is an ideal textbook for graduate students in

R. JACOB (JAKE) BAKER, PHD, is an engineer, educator, and inventor.

Subscribe to our free Electrical Engineering eNewsletter at

Science and Technology R. Jacob Baker

IEEE Press Series on Microelectronic Systems

Chapter 1 Signals, Filters, and Tools 1

Chapter 2 Sampling and Aliasing 27

Effects of Finite Op-Amp Gain Bandwidth Product, fun 78

Cascading Sinc Filters 132

Dynamic Range 177

Effects of the Added Amplifier on Linearity 224

Implementation Concerns 274

9.3 Conclusion 322

Simulation examples are used throughout the book to provide an additional

e book to provide an additional

limitations when represei

Point 2 ~pendulum This function, the sine fun

(b) Movement of pendulum along the arc in (a) over time. 2

t = T14, T + T14, ...

Figure 1.3 A vector

Mixed-Signal Circuit Design Chapter I Signals, Filters, and Tools 3

4Y ~Oo (a) Portion of the sinewave

Length of 0.707 and Length of 1 and

~ Length of 0 and Length of 1 and

sin (2n/0' t+ ~ I cos (2n/o . t) (1.6) Before going too mu

where tdelo/T X 100 % is the percentage the delay is of the period.

a cycle (90 degrees, n12, or a

: sin (2rifo • t+ (1.5)

ction is called cosinusoidal or

",ith time. Note that we can say

SIQ(t) AI' cos 2rc/o • t + A Q' sin 2rc/o . t or Euler's formula

We can now write

4/ . cos 2n/o . t + AQ . sin2rifo . t or Euler's formula

---')ox Re{ elk} == cos k and lm{ elk} == sink ( 1.19)

close to writing the Taylor's series

The delayed cosine signal can be written as

AL.0.IL.2rr.'-:';:=A.IAO+2rr..-:.;:J AL.(-2rrfo·td) (1.24)

1.2 Comb Filters

Figure 1.9 A comb filter.

tail let's write l+cos2nj-(-ld) + j·sin2rrf·(-ld) ( 1.27)

(L21) The magnitude response of this filter is

I~:f I = Icos nJ- t I = Icos n 200 ~Hz I

Figure 1.13 Time domain i

Transmission line 1.2.1 The Digital Comb F

'ICE simulation results showing

1.2.1 The Digital Comb Filter

Time domain Frcquency domain

Figure 1.14 A digital delay.

The magnitude and phase I

rcle). Note that plotting a delay, Z·i

(1.37) to evaluate the frequency

tting cos2rrt + j. sin2rrt

These two points average to zero

1.2.2 The Digital Differentiator Figure 1.20 Magnitude a

Figure 1.20 shows the mag

I Labeling the angles f