Design for testing or design for testability (DFT) consists of IC design techniques that add

testability features to a hardware product design. The added features make it easier to develop
and apply manufacturing tests to the designed hardware. The purpose of manufacturing tests is to
validate that the product hardware contains no manufacturing defects that could adversely affect
the product's correct functioning.

Role of DFT

· Testing of Sequential Circuits

· Improving the chip manufacturing process

DFT accomplishes two significant goals in the chip manufacturing process:

· Reject Defective Modules (Product Quality)

· Monitor and Improve Manufacturing Process

MBIST is a self-testing and repair mechanism which tests the memories through an effective set
of algorithms to detect possibly all the faults that could be present inside a typical memory cell
whether it is stuck-at (SAF), transition delay faults (TDF), coupling (CF) or neighborhood
pattern sensitive faults (NPSF). It uses an inbuilt clock, address and data generators and also
read/write controller logic, to generate the test patterns for the test.

MBIST Algorithms

Memories are tested with special algorithms which detect the faults occurring in memories. A
number of different algorithms can be used to test RAMs and ROMs.

Checkerboard Algorithm

The 1s and 0s are written into alternate memory locations of the cell array in a checkerboard
pattern. The algorithm divides the cells into two alternate groups such that every neighboring cell
is in a different group. The checkerboard pattern is mainly used for activating failures resulting
from leakage, shorts between cells, and SAF.

March algorithm

Among the different algorithms proposed to test RAMs, March tests have proved to be simpler
and faster, and have emerged as the most popular ones for memory testing. There are various
types of March tests with different fault coverages. A March test applies patterns that “march” up
and down the memory address while writing values to and reading values from known memory
locations.
Advantages of MBIST: There are several advantages of MBIST insertion over functional/atspeed
testing such as:

· It allows for robust testing of memories

· Reduced test time

· All the memories of the design can be tested in parallel

· Lesser test cost

Disadvantages of MBIST: Inspite of many advantage of MBIST, there is only one remarkable
limitation. Insertion of MBIST causes increase in area. However, this increase in area is very
small in comparison to the benefits it provides.

Scan chains – the backbone of DFT

What are scan chains: Scan chains are the elements in scan-based designs that are used to shift-in
and shift-out test data. A scan chain is formed by a number of flops connected back to back in a
chain with the output of one flop connected to another. The input of first flop is connected to the
input pin of the chip (called scan-in) from where scan data is fed. The output of the last flop is
connected to the output pin of the chip (called scan-out) which is used to take the shifted data
out. The figure below shows a scan chain.

Purpose of scan chains: As said above, scan chains are inserted into designs to shift the test data
into the chip and out of the chip. This is done in order to make every point in the chip
controllable and observable as discussed below.

How normal flop is transformed into a scan flop: The flops in the design have to be modified in
order to be put in the scan chains. To do so, the normal input (D) of the flip-flop has to be
multiplexed with the scan input. A signal called scan-enable is used to control which input will
propagate to the output.

If scan-enable = 0, data at D pin of the flop will propagate to Q at the next active edge

If scan-enable= 1, data present at scan-in input will propagate to Q at the next active edge

Scan terminology: Before we talk further, it will be useful to know some signals used in scan
chains which are as follows:

Scan-in: Input to the flop/scan-chain that is used to provide scan data into it
Scan-out: Output from flop/scan-chain that provides the scanned data to the next flop/output

Scan-enable: Input to the flop that controls whether scan_in data or functional data will
propagate to output

Purpose of testing using scan: Scan testing is carried out for various reasons, two most prominent
of them are:

To test stuck-at faults in manufactured devices

To test the paths in the manufactured devices for delay; i.e. to test whether each path is working
at functional frequency or not

How Chain length is decided: By chain length, we mean the number of flip-flops in a single scan
chain. Larger the chain length, more the number of cycles required to shift the data in and out.
However, considering the number of flops remains same, smaller chain length means more
number of input/output ports is needed as scan_in and scan_out ports. As

Number of ports required = 2 X Number of scan chains

Since for each scan chain, scan_in and scan_out port is needed. Also,

Number of cycles required to run a pattern = Length of largest scan chain in design

Scan is the internal modification of the design’s circuitry to increase its test-ability. ATPG stands
for Automatic Test Pattern Generation; as the name suggests, this is basically the generation of
test patterns. In other words, we can say that Scan makes the process of pattern generation easier
for detection of the faults we discussed earlier.

To test a fault we need to initialize the flops to the required values as we had shown while
discussing about stuck-at faults and at-speed faults. In a bigger sequential circuit (without scan),
it is difficult to control the flop’s value through primary inputs and observe the captured response
in primary outputs. To solve this issue we do ‘Scan Insertion’ during synthesis.

The goal of ‘Scan Insertion’ is to make a difficult-to-test sequential circuit behave (during testing
process) like an easier-to-test combinational circuit. Achieving this goal involves two steps –
 1. Converting Regular Flop to Scan Flop

All the flops in the design are converted into scan flops (as shown in Figure 4), except –

• The ones that are excluded by user. These are called non-scan flops.

• The ones that have DFT DRC violation(s).

2. Stitching the Scan Flops to form Scan Chains

The scan flops are stitched to form scan chain(s) (as shown in Figure 5). The number of scan
chains depends upon various user inputs like –

• Length of scan chain

• Clock domain mixing

• Power domain mixing

• Voltage domain mixing

The idea of the Internal Scan is to connect internal Flip-Flops and latches so that we can observe
them in test mode. Scan remains one of the most popular structured techniques for digital
circuits. This above process is known as Scan chain Insertion. In the VLSI industry, it is also
known as DFT Insertion or DFT synthesis.

Tessent Scan uses the following inputs:

.Design (netlist) -A Verilog gate-level netlist needs to be provided as input.

.Circuit Setup (or Dofile or Tcl file) -This is the set of commands that gives the tool

information about the circuit and how to insert test structures. You can issue these

commands interactively in the tool session or place them in a dofile or Tcl file.

.Library -The Tessent Cell library contains descriptions of all the cells the design

uses. The library also includes information that the tool uses to map non-scan cells to
scan cells and to select components for added test logic circuitry.

.Input TCD File -If there are pre-existing scan segments that are described in a

*.tcd_scan file, then you need to provide them as input to Scan Insertion. You can read

them in using the set_design_sources command. The full syntax of tcd_scan file appears

in the Scan section of the Tessent Shell Reference Manual. Also, if there are CTL

models for pre-existing scan segments, these can be converted using stil2mgc and then

read in.

.Test Procedure File -This file defines the stimulus for shifting scan data through the

defined scan chains. This input is only necessary on designs containing pre-existing scan

circuitry or requiring initialization for test mode (test setup).

Tessent Scan produces the following outputs:

Design (Netlist) -This netlist contains the original design modified with the inserted

test structures. The output netlist format is gate-level Verilog.

TCD (Tessent Core Description) -This file contains all the Scan modes that were

specified during scan insertion. The ATPG tool uses this file to generate patterns. If you

read in any .tcd files from a previous insertion pass or from a lower level core, the scan

modes are appended to the input *.tcd file and written out into the tsdb_outdir directory.

The ATPG tool uses the inputs shown in Table 8-1:

Table 8-1. ATPG Inputs

Design The supported design data format is gate-level Verilog.

Other inputs also include 1) a cell model from the design

library and 2) a previously-saved, flattened model.

Test Procedure File This file defines the operation of the scan circuitry in your

design. You can generate this file by hand, or Tessent Scan

can create this file automatically when you issue the

command write_atpg_setup.

Library The design library contains descriptions of all the cells used

in the design. The tool uses the library to translate the

design data into a flat, gate-level simulation model for use

by the fault simulator and test generator.

Fault List The tool can read in an external fault list. The tool uses this

list of faults and their current status as a starting point for

test generation.

Test Patterns The tool can read in an external fault list. The tool uses this

list of faults and their current status as a starting point for

test generation.

The ATPG tool produces the outputs described in Table 8-2:

Table 8-2. ATPG Outputs

314

Test Patterns The tool generates files containing test patterns. They can

generate these patterns in a number of different simulator

and ASIC vendor formats.

ATPG Information Files These consist of a set of files containing information from
the ATPG session. For example, you can specify creation of

a log file for the session

Fault List This is an ASCII-readable file that contains internal fault

information in the standard Tessent fault format.

Tessent MemoryBIST Inputs

To insert memory BIST into your design, you must have either an RTL or a gate-level netlist as

well as memory BIST libraries.

If the design contains standard cells, the Tessent cell library or ATPG library is also required.

For other IP blocks that do not have either RTL or library models, the simulation model can be

loaded using the read_verilog or read_vhdl command with the -interface_only option. This

instructs the tool to ignore the internals of all modules specified in the filename argument and

extract only the module port definitions and parameters.

Tessent MemoryBIST Outputs

Using Tessent MemoryBIST, you can perform the following:

.Test multiple memories using one memory BIST controller that has one or more BIST

steps, where BIST steps are run in sequence.

.Test memories in parallel in one BIST step or in sequence in several BIST steps.

.Define one or more custom test memory algorithms that are hard coded into the memory

BIST controller.

.Choose memory test algorithms from the Tessent library of algorithms to be hard coded

into the memory BIST controller.

.Run the memory BIST controller for all steps with the specific algorithms assigned at
generation time (default configuration).

.Run the memory BIST controller in diagnostic mode where you can freeze on a specific

BIST step, specific memory test port, or specific error count.

.Select a hard-coded memory BIST algorithm to be applied to a specific memory BIST

step at the tester.

.Select an algorithm from a library of algorithms to be applied to a specific memory

BIST step.

.Define a custom algorithm at tester time to be applied to a specific memory BIST step.

.Perform repair analysis on memories implementing different redundancy schemes such

as row only, column only, or row and column.

c violations meant clock

d violations meant design and data

e means timing analysis path

Tessent BoundaryScan

Tessent BoundaryScan is a complete solution for the creation and integration of boundary scan

cells and related control logic for embedded test and diagnosis of integrated circuit I/Os, as well

as test and diagnosis of board-level interconnects between ICs. Tessent BoundaryScan provides

a completely automated solution for adding standard boundary scan support to ICs of any size

or complexity, reducing IC engineering development effort and improving time-to-market.

Tessent BoundaryScan Inputs

To use this flow, you must have either an RTL or a gate-level netlist with I/O pads already

inserted into the design. For an RTL netlist, you must have the Tessent cell library or the pad

library for the pad cells. For a gate-level netlist, you must have the Tessent cell library or the

ATPG library for the standard cells, in addition to the Tessent cell library for the I/O pad cells.

The pad library supported by Tessent BoundaryScan-LV is natively supported in Tessent Shell

if the Tessent cell library for the I/O pad cells is not present.

Tessent BoundaryScan Outputs

The tool creates and interconnects RTL-level boundary scan logic compliant with the IEEE

1149.1-2001 standard.

.Instruction Support -Full support of required IEEE standards 1149.1 instructions.

.Extension Support -Support of base extensions to IEEE 1149.1, such as the Device

ID register.

.Compliant Verilog -Generation of Verilog (IEEE 1364-2001) that is compliant with

Questa ® SIM (Verilog), Synopsys' Design Compiler, and other industry synthesis tools.

.RTL-Level Boundary Scan Generation -Insertion and interconnection of boundary

scan circuitry at the RTL level, moving generation of test circuitry to earlier in the

design process.

.Customized Boundary Scan -Generation of default or user-customized boundary

scan architectures.

.Automatic Connection -Automatic connection of boundary scan to internal scan

logic.

.Test Bench Generation -Generation of a test bench to test the boundary scan logic

after interconnection with the core application logic.

.Test Vector Generation -Generation of boundary scan test vectors in a variety of

ASIC vendor test data formats, as well as ASCII, binary, STIL, WGL and other pattern

formats.

.Setup File Generation -Generation of ATPG setup files, for designs with generated

boundary scan circuitry controlling internal scan circuitry.

.Compliant BSDL -Production of BSDL output that is compliant with IEEE standard

IEEE 1149.1-2001 specification.

Tessent Diagnosis

Tessent Diagnosis-specific features include many capabilities.

Some of these capabilities are:

.Fault model independent analysis for suspect identification, suspect scoring, and

classification.

.Logic and chain diagnosis.

.Direct diagnosis with compressed patterns.

.Links to Calibre ® for physical view.

Tessent Diagnosis Inputs

Tessent Diagnosis has the following inputs:

.Design -This must be a flattened design, created previously using the

write_flat_model command in Tessent FastScan or Tessent TestKompress.

.Test Patterns -STIL, WGL, binary or ASCII version of the patterns applied on the

tester.

.Failure file -This file contains ATE failure data presented in the correct Tessent

failure file format for the diagnose_failures command.

Tessent Diagnosis Outputs

Tessent Diagnosis produces the following outputs:

\u2022

Failure Diagnosis Report -This is a human-readable diagnosis report that is

displayed onscreen or written in ASCII format to a file. Additionally, the report can be

written to a file in Comma Separated Value (CSV) format.

Tessent FastScan and Tessent TestKompress

Tessent FastScan and Tessent TestKompress share a great deal of functionality. Tessent

TestKompress contains the entire Tessent FastScan feature set (the \u201cpatterns -scan\u201d
context),

and in addition provides functionality for EDT IP creation (the \u201cdft -edt\u201d context).

Both products share the following features:

62

.Can be used within a Tessent flow or as a point tool in other design flows.

.Contain an internal high-speed fault simulator.

.Produce a number of standard test pattern data formats.

.Contain a powerful design rules checker.

.Read most standard gate-level netlists.

.Produce very high coverage test pattern sets for full-scan and scan-sequential designs.

Scan-sequential designs contain well-behaved sequential scan circuitry, including non-

scan latches, sequential memories, and limited sequential depth.

.Contain functionality for handling embedded RAM and ROM.

.Support the same pattern types and fault models.

.Provide the same test coverage.

.Provide the same diagnostics.

\u2022

Contain the same command set, with the exception that Tessent TestKompress contains

additional commands for EDT IP creation and use.

In addition to the previous features, Tessent TestKompress includes the following:

\u2022

Increases production throughput: scan test time is much shorter than any other scan

methodology.

Tessent FastScan and Tessent TestKompress Inputs

Tessent FastScan and Tessent TestKompress have the following inputs:

.Design -The supported netlist formats are: gate-level Verilog, RTL Verilog, RTL

System Verilog, and RTL VHDL.

.Test Procedure File -This file defines the operation of the scan circuitry in your

design. You can generate the file by hand or by using the write_atpg_setup command in

Tessent Scan.

.Library -This file contains model descriptions for all library cells used in your

design.

.Test Patterns -This is a set of externally generated test patterns that you can use as

the pattern source for simulation.

Tessent TestKompress has the following inputs:

EDT IP Creation Phase:

o Design -This must be a gate-level netlist with scan. The supported netlist format is

Verilog.

o Test Procedure File -This file defines the operation of the scan circuitry in your

design. You can generate the file by hand or by using the write_atpg_setup
command in Tessent Scan.

o Library -This file contains model descriptions for all library cells used in your

design.

EDT Pattern Generation Phase:

o Design -This must be a scan-inserted, gate-level netlist with EDT circuitry. The

supported netlist format is Verilog.

o EDT Dofile -Created by Tessent TestKompress in the IP Creation Phase, this file

contains setup commands for the Pattern Generation Phase.

o EDT Test procedure file -Created by Tessent TestKompress in the IP Creation

Phase, this file contains test procedure steps for the Pattern Generation Phase.

Library -This file contains model descriptions for all library cells used in your

design.

Tessent FastScan and Tessent TestKompress Outputs

Tessent FastScan and Tessent TestKompress produce the following outputs:

.Test Patterns -This file set contains test patterns in one or more of the supported

simulator or ASIC vendor pattern formats. For more information on the available test

pattern formats, refer to the write_patterns command reference page within this manual,

or the \u201cHow to Save the Test Patterns\u201d section in the Tessent Scan and ATPG User\
u2019s

Manual.

.ATPG Information Files -These files contain session information that you can save

using various commands.

.Fault List -This is an ASCII file that contains internal fault information in the

standard Tessent fault format.

Tessent TestKompress produces the following outputs:

EDT IP Creation Phase:

o EDT IP Files -These files contain the EDT IP described in Verilog or VHDL

RTL, as well as connectivity and a black box representation of the core design.

o Design Compiler Synthesis Script -This is a synthesis script, typically used as a

template for synthesizing the EDT IP into the design.

o EDT Dofile -This file contains setup commands for the EDT Pattern Generation

Phase.

o EDT Test Procedure File -This file contains test procedure steps for the Pattern

Generation Phase.

o Bypass Files -These files consist of a dofile and a test procedure file for optionally

performing Tessent FastScan ATPG on the design with EDT.

EDT Pattern Generation Phase:

Test Patterns -This file set contains test patterns in one or more of the supported

simulator or ASIC vendor pattern formats. For more information on the available

test pattern formats, refer to the write_patterns command description in this manual.

Tessent IJTAG

Tessent IJTAG is the Siemens EDA implementation of the IEEE 1687-2014 (IJTAG) standard

for PDL command retargeting and ICL extraction.Tessent IJTAG Inputs

Tessent IJTAG has the following input:

ICL Files -Instrument Connectivity Language (ICL) descriptions of your design.

Tessent IJTAG Outputs

Tessent IJTAG produces the following outputs:

.Test Patterns -Retargeted PDL patterns in many different ATE tester specific formats

and Verilog HDL simulation test benches.

.Extracted ICL Files -Top-level ICL expressing the interconnection of IJTAG

instruments within a design netlist.

Tessent LogicBIST

Tessent LogicBIST contains all the features that are needed to implement Hybrid TK/LBIST

Flow in a design.

The product includes the following features:

.Insertion of DFT into the design to make it BIST-ready. This involves scan stitching, x-

bounding, and bounding of multicycle and false paths.

.Test point insertion to improve the random pattern testability of the design.

.Hybrid TK/LBIST generation and insertion into the incoming design. This includes

sharing the logic between the EDT and LBIST controllers, thereby reducing the overall

area overhead. Additionally, the tool also generates logic that enables you to do low

power shift during LBIST.

.IJTAG network insertion and extraction, which is necessary to set up Logic BIST and

observe the MISR signature.

.Fault simulation of the pseudo-random patterns applied during an LBIST session.

.Generation of top-level patterns that enables merging of patterns for multiple LBIST

controllers.

chip design flow

· customer requirements
 · specification

· architecture

· hardware description language

· gates and nets

· Transistors ,wires, and vias

· shapes

building the chip

· masks

· etches ,diffusions, and depositions

· dicing and packaging

hdf files have info about all delays ,faults

no timing simulations have no delays

atpg lo algorithm

scan clock frequency 40mhz

functional clock frequency 1 ghz

Fault coverage refers to the percentage of some type of fault that can be detected during the test
of any engineered system.

Fault Coverage is percentage of detected fault from all fault in design.

And Test coverage is percentage of detected fault from detectable fault in design .

Detectable fault not contain the fault which are Tied, unused or redundant
What does test procedure files have?

Ans: The test procedure file contains all the scan information of your test ready netlist.

1. The number of the scan chains

2. The number of scan cells in each scan chain.

3. The shift clocks.

4. The capture clocks

5. Any test setup procedure required before starting the test pattern generation

6. The timing of the different clocks.

7. The time for forcing the Primary input , bidi inputs , scan inputs etc

8. The time to measure the primary outputs, scan outputs , etc ..

9. The pins which have to be held at some state in the different procedure as load_unload, shift
etc ..

What problems u faced while inserting test points.

Ans: The problems u faces while inserting test points ,

I don't think there is any problem, except

1. Selecting the best candidate location for the test points.

2. Area over head

If enable pin of tri-state is 0, the output is Z. how does tool treat this Z as in DFT. How is Z
handled.

Ans: It depends on the tester. We can customize the tool to generate the patterns