Wong 2010

INVITED
PAPER
Phase Change Memory

A comprehensive and thorough review of PCM technologies, including a
discussion of material and device issues, is provided in this paper.
By H.-S. Philip Wong, Fellow IEEE , Simone Raoux, Senior Member IEEE , SangBum Kim,
Jiale Liang, Student Member IEEE , John P. Reifenberg, Bipin Rajendran, Member IEEE ,
Mehdi Asheghi, and Kenneth E. Goodson
ABSTRACT | In this paper, recent progress of phase change nology have made it possible to demonstrate PCMs that
memory (PCM) is reviewed. The electrical and thermal proper- rival incumbent technologies such as Flash [4]. The
ties of phase change materials are surveyed with a focus on the characteristics of PCM most closely approximate that of
scalability of the materials and their impact on device design. the dynamic random access memory (DRAM) and the Flash
Innovations in the device structure, memory cell selector, and memory (Table 1) [5].
strategies for achieving multibit operation and 3-D, multilayer Reports on PCM have grown rapidly in recent years
high-density memory arrays are described. The scaling prop- (Fig. 1). The worldwide research and development effort
erties of PCM are illustrated with recent experimental results on emerging memory devices and PCM in particular can be
using special device test structures and novel material synthe- understood from two perspectives. First, from a system
sis. Factors affecting the reliability of PCM are discussed. point of view, processor performance is increasingly li-
mited by memory access and power consumption of the
KEYWORDS | Chalcogenides; emerging memory; heat conduc- memory subsystem. Recent efforts in extending the scala-
tion; nonvolatile memory; PCRAM; phase change material; bility of SRAM and incorporating embedded DRAM in
phase change memory (PCM); PRAM; thermal physics advanced technologies are evidence of the importance of
the memory technology. The emergence of Flash as a po-
tential solid-state replacement for the hard disk drive
I. INTRODUCTION (HDD) for selected applications has highlighted the enor-
The concept of using the amorphous to crystalline phase mous potential of a high-density, embedded memory
transition of chalcogenides for an electronic memory tech- technology within the memory hierarchy. At the same
nology has been pursued for many years [1]–[3]. While the time, memory device research has had a renaissance of
early work disclosed many of the fundamental concepts of new ideas [6], [7]. New memory devices, most of them
the phase change memory (PCM), it is only in the past nonvolatile, have been explored and some have progressed
10–15 years that advances in materials and device tech- beyond the observation of a hysteresis effect to device-level
demonstrations. These new memory devices, such as PCM,
have read/write/retention/endurance characteristics dif-
Manuscript received March 5, 2010; accepted May 24, 2010. Date of publication ferent from conventional static random access memory
October 25, 2010; date of current version November 19, 2010. The work of
H.-S. P. Wong, S. Kim, J. Liang, J. P. Reifenberg, M. Asheghi, and K. E. Goodson was (SRAM), DRAM, and Flash. The very high density offered
supported in part by Intel Corporation, the Semiconductor Research Corporation under by some of the new device technologies may also lead to
Contract 2009-VJ-1996, the National Science Foundation under Grant CBET-0853350,
the member companies of the Stanford Non-Volatile Memory Technology Research the replacement of the HDD by solid-state devices for
Initiative (NMTRI), the Lawrence Berkeley National Laboratory Molecular Foundry, some applications [8], [9]. There is an enormous opportu-
NXP, Samsung, Ovonyx, and IBM.
H.-S. P. Wong, S. Kim, and J. Liang are with the Department of Electrical Engineering, nity to completely rethink the design of the memory sub-
Stanford University, Stanford, CA 94305 USA (e-mail: [email protected]; system to gain orders of magnitude improvements in
[email protected]; [email protected]).
S. Raoux and B. Rajendran are with IBM T.J. Watson Research Center, speed and/or power consumption. A revolution in the
Yorktown Heights, NY 10598 USA (e-mail: [email protected]; memory subsystem will bring about a fundamental change
[email protected]).
J. P. Reifenberg is with the Intel Corporation, Santa Clara, CA 95054, USA (e-mail: in how one can extract performance out of technology
[email protected]). improvements.
M. Asheghi and K. E. Goodson are with the Department
of Mechanical Engineering, Stanford University, Stanford, CA 94305 USA In this paper, we focus on one of the more Bmature[
(e-mail: [email protected]; [email protected]; [email protected]). emerging memory technologiesVPCMVand summarize
Digital Object Identifier: 10.1109/JPROC.2010.2070050 the important material and device learning in recent years
0018-9219/$26.00 Ó 2010 IEEE Vol. 98, No. 12, December 2010 | Proceedings of the IEEE 2201
Wong et al.: Phase Change Memory
Table 1 Device Characteristics of DRAM, Flash, and PCM [5]. Information Is Gathered From the ITRS and Does Not Represent the
Best-of-Breed for Specific Product and Research Advances
[10], with a focus on how fundamental physics interact view are emphasized. Device density in the memory array
with device properties and the device scaling potential of is essentially determined by the memory cell selector. The
PCM. We start with a description of the basic device requirements, implementation, and recent demonstrations
operation (Section II). The properties of the phase change are discussed in Section V. The vision of a high-density
material, reviewed in Section III, are of fundamental im- memory will eventually be realized via multibit operation
portance to device optimization for the targeted applica- of the memory cell and 3-D stacking of the memory array.
tion (such as finding the best speed, retention, and This is reviewed in Section VI. Reliability is discussed in
endurance tradeoff) as well as the scalability of PCM. The Section VII. Any new semiconductor technology, including
device design and device structural innovations are re- PCM, must be scalable for many generations. The potential
viewed in Section IV. Throughout the materials and device for the PCM to scale to nanoscale dimensions is explored
discussions, the thermal properties of the materials and in Section VIII. Finally, we offer a view of the future and
design considerations from a thermal management point of conclude the paper in Section IX.
I I. DEVICE OPERATION
Fig. 2 shows one common PCM cell. PCM utilizes the large
resistivity contrast between crystalline (low resistivity)
and amorphous (high resistivity) phases of the phase
change material. Set and reset state of PCM refers to low
and high-resistance state, respectively. As fabricated, the
phase change material is in the crystalline, low-resistance
state because the processing temperature of the (BEOL)
metal interconnect layers is sufficient to crystallize the
phase change material. To reset the PCM cell into the
amorphous phase, the programming region is first melted
and then quenched rapidly by applying a large electrical
current pulse for a short time period. Doing so leaves a
region of amorphous, highly resistive material in the PCM
cell. This amorphous region is in series with any crystalline
region of the PCM and effectively determines the re-
Fig. 1. The number of publications on PCM has increased over the sistance of the PCM cell between the top electrode contact
last ten years. Data are obtained by searching the IEEE Xplore for all
(TEC) and the bottom electrode contact (BEC). To set the
IEEE, AIP, and IET journals and conference proceedings using the
Boolean expression: (phase Gand9 change Gand9 memory) Gor9
PCM cell into the crystalline phase, a medium electrical
(phase Gand9 change Gand9 chalcogenide) Gor9 ovonics Gor9 ovonic current pulse is applied to anneal the programming region
Gor9 PCM Gor9 PRAM Gor9 PCRAM. at a temperature between the crystallization temperature
2202 Proceedings of the IEEE | Vol. 98, No. 12, December 2010
longer than the crystallization time it leads to memory

switching and the cell reaches the low-resistance state for
an applied voltage larger than V th .
The set process critically depends on the above men-
tioned electronic threshold switching effect [11]. When the
electric field across the amorphous region reaches a
threshold value, the resistance of the amorphous region
goes into a lower resistance state which has resistivity that
is comparable to the crystalline state. This electronic
threshold switching phenomenon, the physics of which is
yet to be fully explored, is the key to successful set prog-
ramming of the PCM. When the PCM is in the reset state,
Fig. 2. (a) The cross-section schematic of the conventional PCM cell. the resistance of the PCM cell is too high to conduct
The electrical current passes through the phase change material enough current to provide Joule heating to crystallize the
between the top electrode and heater. Current crowding at the PCM cell. The electronic threshold switching effect lowers
‘‘heater’’ to phase change material contact results in a programmed
the resistance of the phase change material to the dynamic
region illustrated by the mushroom boundary. This is typically
referred to as the mushroom cell. (b) PCM cells are programmed resistance and enables set programming.
and read by applying electrical pulses which change temperature Reset programming consumes the largest power since
accordingly. the cell needs to reach the melting temperature. Reset
current is also determined by various material properties
(Section III) such as the resistivity and thermal conduc-
and the melting temperature for a time period long enough tivity as well as the device structure (Section IV). In gen-
to crystallize. To read the state of the programming region, eral, the operating speed of PCM is limited by the set
the resistance of the cell is measured by passing an elec- programming time because it takes finite time to fully
trical current small enough not to disturb the current state. crystallize the amorphous region.
The schematic pulse shapes are summarized in Fig. 2(b).
Fig. 3 shows current–voltage (IV) curves of the set III . MATERIAL PROPERTIES
and reset states. The set and reset states have large resis-
tance contrast for voltages below the threshold switching Almost any material including metals, semiconductors,
voltage ðV th Þ. The reset state is in the high-resistance state and insulators can exist in an amorphous phase and a
below V th (subthreshold region) and shows electronic crystalline phase. However, a very small subset of these
threshold switching behavior at V th , i.e., a negative differ- materials have simultaneously all the properties that make
ential resistance. This is reversible if the voltage pulse is them useful for data storage technologies where the in-
removed very quickly. But if the voltage is applied for formation is stored in form of the phase of the material.
These phase change materials are at the heart of PCM
technology. Despite the fact that PCM technology was de-
scribed already in the 1960s [1], [3] the technological suc-
cess of optical storage based on phase change materials was
only enabled after the discovery of a new class of materials
that fulfilled all the requirements for this technology. It
was found that semiconductor alloys along the GeTe–
Sb2 Te3 pseudobinary line had large optical contrast and
could be rapidly and repeatedly switched between the
amorphous, low reflectivity and crystalline, high reflectiv-
ity phases using laser pulses [13]. This discovery led to the
very successful rewritable optical storage technology with
its third generation 100-GB capacity Blu-ray disks
announced recently [14]. This success sparked new
interest in PCM technology and intense materials research
[15], [16] is being performed to find materials optimized
for this technology [17].
A. Electrical and Switching Properties

Fig. 3. IV characteristics of set and reset state. The reset state
shows switching behavior at the threshold switching voltage ðV th Þ. The
So what is the unique combination of properties
reset state stays in the high-resistance state below V th (subthreshold that makes these materials useful for PCM? Phase
region) and switches to the low-resistance state at V th . After [12]. change materials have a large electrical contrast; for
Vol. 98, No. 12, December 2010 | Proceedings of the IEEE 2203
some materials the difference between the resistance in voltages and exponential for high voltages. At a certain
the amorphous and crystalline phase can be up to five material-dependent threshold field on the order of
orders of magnitude [18] (see Fig. 4). This large electrical 10–100 V/m [23] the resistivity of the amorphous phase
contrast allows for a large on/off ratio in PCM cells. In change material suddenly decreases by orders of magni-
practical devices it is typically two orders of magnitude tude, negative differential resistance is observed, and so-
because 1) the resistance of the PCM cell in the set state called threshold switching occurs (Fig. 3). The mechanism
ðRset Þ is not only determined by the phase change material behind threshold switching is still being debated and sev-
itself but also determined by the rest of the device eral models have been suggested as a possible mechanism.
structure such as the contact resistance and the resistance The thermal instability model attributes threshold switch-
of the heater, and 2) the resistance of the PCM cell in the ing to thermal runaway caused by Joule heating [24]. This
reset state ðRreset Þ is lower than would be expected from the model is based on a simple observation that the current
as-deposited amorphous phase because melt-quenched through the phase change material increases exponentially
materials have lower resistivity than the as-deposited due to temperature-dependent conductivity of the phase
amorphous material. As can be seen from the drop in change material as temperature increases. Considering
resistance, various phase change materials have different that the typical threshold switching speed is faster than the
crystallization temperatures. Materials need to be selected thermal time constant, electronic mechanisms are favored
that have a high enough crystallization temperature so that over purely thermal mechanisms [25]. An electronic model
they are stable in the amorphous phase for ten years at attributes threshold switching to strong carrier generation
operating temperature of the PCM cells which is, e.g., caused by high electric field and large carrier density
85 C for embedded memory applications or even 150 C [26]–[28]. In another electronic model, the threshold
for automotive applications. On the other hand, when switching is attributed to energy gain of electrons in a high
switching to the crystalline state is required during a write electric field leading to a voltage–current instability [11].
operation it should occur on the nanosecond time scale. The crystallization model attributes threshold switch-
This is a difference in response time to crystallization of ing to the actual crystallization based on a nucleation
17 orders of magnitude [19]. For ultrascaled devices, model in which the nucleation is facilitated by the electric
switching on the 1-ns time frame has been demonstrated field [29]. Reversible characteristic of threshold switching
[20], [21] while data retention at 85 C for ten years has is explained by dissolution of premature crystalline em-
also been shown (for larger devices based on 90- and bryos upon removal of the electric field. Detailed expe-
180-nm technology) [22] but not at 150 C. rimental validation of these models is further required
The electrical conductivity in the amorphous phase can because the internal parameters of the models cannot be
be described by thermally activated hopping transport [11]. precisely determined. The dominant threshold switching
A Poole–Frenkel transport of carriers through traps leads mechanism can be different for various phase change
to a current which is linear with voltage for very small materials depending on material properties and a combi-
nation of the suggested models may be required to explain
all the observations.
The threshold field translates into a certain threshold
voltage for PCM devices and is typically in the 1–2-V
range. At voltages above the threshold voltage there is a
several nanosecond delay time between the application of
the voltage and the threshold switching. This delay time
becomes longer and shows a strong voltage dependence
close to the threshold voltage [30]. From a PCM standpoint
threshold switching is crucial because without this effect
PCM would not be a viable technology. It allows enough
current flow through the material to heat it above the
crystallization temperature and switch it to the crystalline
state. The threshold switching itself is reversible and if the
voltage is removed quickly the cell returns to the high-
resistance amorphous state without memory switching.
Fig. 4. Resistivity as a function of temperature during a heating cycle There is also a short delay time between the end of the
at 1 K/s for initially amorphous, as-deposited 50-nm-thick films of voltage pulse and the full recovery of the high resistance of
various phase change materials. Initially, the thin films have a high the amorphous phase. Only if the voltage pulse is long
resistance that drops sharply when the crystallization temperature
enough to heat the material above its crystallization tem-
is reached, and it stays low upon cooling. GSTVGe 2 Sb2 Te 5 ,
N-GSTV7 at. % N-doped GST, GeSb–Ge:Sb ratio 15:85, AISTVSb2 Te
perature to allow it to crystallize does memory switching
doped with 7 at. % Ag and 11 at. % In. Reprinted with permission occur and the cell is in the low-resistance state after the
from [18], copyright American Institute of Physics (2007). pulse.
With respect to switching speed, several time constants

are important including the crystallization time, the delay
time between the applied voltage and the threshold
switching event, and the recovery time after switching.
The most limiting time constant is the crystallization time.
Crystallization times vary greatly with material compo-
sition, film thickness [34], and also between first crystal-
lization of as-deposited amorphous material and
recrystallization of melt-quenched, amorphous material
[34], [35]. The latter is typically (and sometimes orders of
magnitude) faster since in all practical cases it does not
require incubation and nucleation (formation of supercri-
tical nuclei) but only crystal growth from the amorphous-
crystalline interface. In addition, melt-quenched
amorphous materials have also a different medium range
order compared to as-deposited materials and this will in-
Fig. 5. Conductivity in the amorphous and crystalline phase of fluence nucleation rates and crystallization times [36]. The
Ge 2 Sb2 Te 5 as a function of time. Reprinted with permission
from [31], copyright American Institute of Physics (2009).
recrystallization time of melt-quenched amorphous mate-
rial is the relevant time scale for PCM because such an
amorphous-crystalline interface is present in PCM devices.
Static laser testers can give fast turnaround time results
The electrical conduction in the crystalline phase can be to measure crystallization times, and good correlation be-
described straightforwardly with the drift-diffusion behav- tween laser testing and device performance has been de-
ior of a doped semiconductor resulting in Ohmic behavior monstrated [35]. Fig. 7 shows the comparison between
for low voltages. Non-Ohmic behavior of PCM cells for electrical testing on bridge devices in the as-deposited
higher voltages can be attributed to Joule heating by the amorphous state and melt-quenched amorphous state
current. Switching back from the crystalline phase to the compared to results from static laser testing of Ge15 Sb85
amorphous phase can be done in two waysVby ion implan- blanket films [35]. Bridge devices were fabricated using
tation (at or close to room temperature) [32] or by melting low-temperature lithographic processes and as-fabricated
and quenching the melt fast enough that it solidifies in the devices were in the amorphous-as-deposited state. These
amorphous state. In technological devices including PCM devices could be switched to low resistance and subse-
cells, melt-quenching is realized by applying a high and quently back to high resistance but never to the very high
short voltage pulse [Fig. 2(b)]. After the reamorphization resistance they showed right after fabrication. This can be
and cooling the material undergoes structural relaxation due to several effects: the reamorphization pulse did not
leading to a resistance drift to higher values over time fol- reamorphize the full bridge length, the first switching was
lowing a power law according to R ¼ R0 ðt=t0 Þ where R connected to a breakthrough of a resistive interfacial layer
and R0 are the current and initial resistances, t and t0 are at the contact interface, or the melt-quenched material has
the current and initial times, and is the drift exponent a different resistance than the as-deposited material. The
[12]. Fig. 5 shows the conductivity of a PCM cell in the
amorphous and crystalline state over time [31]. While the
conductivity in the crystalline state is nearly constant it
changes substantially in the amorphous state. The origin of
this resistance drift in the amorphous phase is still being
debated but it is clear that is has serious consequences for
the capability to store multiple bits per cell by setting it to
different resistance values. The drift exponent is typically
of order ¼ 0:1 [31] and depends on the temperature [33].
While resistance drift to higher values in fact increases the
on/off ratio (as can be seen from Fig. 5) and thus improves
device performance, it is a major concern for multilevel
storage. Explanations for resistance drift include stress
release [12], [31], decrease of defect density [11], shift of
the Fermi level, or increase of the band gap [12]. The drift
behavior of the amorphous phase is also represented in Fig. 6. V th of the amorphous phase as a function of time after reset
threshold switching voltage ðV th Þ drift and the V th drift programming for various annealing temperatures ðT A Þ. Cells are
speed also depends on the temperature (Fig. 6) [2]. programmed and V th is read at room temperature. After [2].
Fig. 7. Comparison of electrical testing and optical testing for the crystallization times of as-deposited and melt-quenched Ge 15 Sb85 material.
Electrical testing was performed on bridge devices and optical testing using a static laser tester. Reprinted with permission from [35].
effect will also reduce the on/off ratio of actual devices Ge–Sb alloys [44], Si–Sb–Te alloys [45], and Si–Sb alloys
compared to as-deposited thin films as shown in Fig. 4. [46] but for most of these materials large scale memory
Fast crystallization times can be correlated to the array data are still missing.
structural properties of the phase change materials. Fast The melting temperature of a phase change material
switching materials often show a simple cubic or rocksalt determines how much power is needed to melt-quench
structure with random atomic distributions that require and reamorphize the material. Melting temperatures for
little atomic movement to change from the amorphous to typical phase change materials are in the range of 500 C–
the crystalline state [19]. In addition it was found that 700 C [47].
resonance bonding plays an important role for fast switch-
ing phase change materials [37]. A low degree of ionicity B. Thermal Properties
and low tendency towards hybridization is typical for fast The spatial distribution of thermal resistances is the
switching phase change materials [17]. These parameters key factor determining the PCM programming current.
can guide us to find better materials with improved com- The intrinsic thermal resistance arises from energy carrier
position and switching characteristics. scattering in the bulk of the material, while the thermal
Other material parameters that are important for PCM boundary resistance (TBR) arises from scattering in the
include thermal properties (see next section), data reten- interface region. The electrode contacts, commonly made
tion properties which are related to the activation energy of TiN, are the dominant heat sinks in PCM devices [48],
for crystallization, and cyclability. Data retention and loss [49]. Consequently, understanding thermal conduction in
can be described by a percolation model [38], [39] which thin film phase change materials, thin film electrode
can explain the very different retention times for nomi- materials, and at their interfaces is essential for reducing
nally identical cells and the stochastic nature of data loss, programming energy.
for example, a cell that shows bad data retention in one The most common thin film thermal conductivity mea-
switching cycle can show good retention in the next cycle. surement techniques for phase change materials are the 3!
Doping with oxygen [40] or nitrogen [41] can improve data method [50], nanosecond transient thermoreflectance
retention but on the other hand doping will also slow down (TTR) [51], and picosecond time-domain thermo-
the crystallization process [42]. Other materials proposed reflectance [52], [53]. Measurements on the common
for better data retention include In–Ge–Te alloys [43], phase change material Ge2 Sb2 Te5 (GST) show thermal
conductivities at room temperature in ranges of 0.14–0.29,

0.28–0.55, and 0.83–1.76 W/m/K in the amorphous, rock-
salt, and hexagonal phases, respectively [54]. The rocksalt
phase thermal conductivity exhibits a slow increase with
temperature consistent with other highly defective crystal-
line materials [52], [53]. Significantly, the thermal con-
ductivities in the amorphous and rocksalt phases are close
to the minimum thermal conductivity approximation [53].
Recently, high-density nanostructured materials have ex-
hibited thermal conductivities well below this approxima-
tion [55]. Nanostructured phase change regions have the
potential to offer dramatically reduced programming cur-
rents through exceptionally low thermal conductivities.
Another key challenge is extending thermal conductivity
measurements to the melting temperature, which is noto-
riously difficult due to the volatility of many phase change
materials. These measurements will shed light on the re-
lative electron and phonon contributions in conduction at
Fig. 8. Thermal conductivity of Ge 2 Sb2 Te 5 versus temperature.
device operating conditions, informing better material The electron contribution in the rocksalt phase, predicted using
selection. the WFL rule, is highly sensitive to the activation energy.
Data are limited for chalcogenide phase change mate-
rials other than Ge2 Sb2 Te5 . Room temperature thermal
conductivities fall in a similar range for a variety of stoi-
chiometries ranging in Sb concentration from GeTe and increase in the electron component of the thermal con-
Ge2 Sb2 Te5 [51]. The crystalline phases of AgInSbTe and ductivity, but also due to an increase in the sound velocity
GeSb exhibit larger thermal conductivities of 1.05 and in the rocksalt phase. Fig. 8 summarizes many of the
2.47 W/m/K, respectively, due to a larger electron contri- existing data for the temperature-dependent thermal con-
bution [56]. Current and future PCM devices [57], [58] ductivity of Ge2 Sb2 Te5 , overlaid with an estimation of
will likely incorporate multiple phase change materials, electron contribution using the WFL. The amorphous
requiring significantly more data to inform physical phase and thin film hexagonal phase data generally agree
models for the stoichiometry dependence of phase change well over a large number of studies (not shown). In con-
material thermal properties. trast, the rocksalt phase thermal conductivity measure-
Data are also limited, but much needed, for thin ments, which are critical for device simulations, show
film electrode materials since the top and bottom elec- different temperature trends. Process conditions, defect
trode contacts dominate heat dissipation in conventional concentration, temperature history, thickness, and electri-
PCM devices. Values for thin film TiN range from 10 to cal properties may all influence the temperature depend-
19.2 W/m/K [52], [59]. Engineering the electrode to have ence. The data in [52] roughly track the temperature
acceptable electrical conductivity and very low thermal dependence of the volumetric GST heat capacity, while
conductivity is a key step toward reducing programming those in [53] show a stronger temperature trend, possibly
current. Composite electrodes may leverage TBR to due to the increasing role of electrons. The modified WFL
increase the device effective thermal resistance. rule offers the only current model for predicting the high-
Reifenberg et al. [52] report that the rocksalt GST/TiN temperature rocksalt phase thermal conductivity, near
TBR dominates the device thermal resistance up to 325 C, 1 W/m/K at the melting temperature. In light of the
decreasing from 26 to 18 m2 K/GW over the temperature different observed temperature behaviors, the validity of
range 27 C G T G 325 C, equivalent in thermal resis- this approximation at high temperature needs to be con-
tance to nearly 500 nm of TiN at room temperature. firmed. Simultaneous temperature-dependent measure-
The extent to which the thermal resistance can be in- ments of the in-plane and out-of-plane electrical and
creased without adversely affecting the electrical proper- thermal properties will significantly improve device models
ties is a key challenge in optimizing PCM. Risk et al. [56] by offering improved insight into the temperature scaling
report the thermal and electrical conductivities of four of the thermal conductivity and the role of electrons. The
phase change materials. The data obey a modified existence of the interface WFL rule and Seebeck effect [60]
Wiedemann–Franz Lorenz (WFL) rule in the amorphous complicates device scaling calculations, and measurements
and crystalline phases, where the electron component of of these effects are essential to properly account for their
the thermal conductivity accounts for the difference be- role in device performance.
tween phases. Lyeo et al. [53] suggest the increase in ther- Future measurements will reveal the key thermal
mal conductivity between the phases is due in part to an physics required for advanced PCM implementations.
Measurements of the Seebeck coefficient and its phase and (defined by film deposition) in one direction and the
temperature dependence will improve device simulations BTrench[ width in the other direction. When scaled down
and scaling. Further exploration of the electrical interface to the 90-nm technology, the BTrench[ structure shows a
resistance (EIR) and TBR are essential for optimizing reset current of 400 A for a 400-nm2 contact area [65].
device materials and geometries. Last, full-cycle crystalli- Although the BTrench[ cell achieves low program-
zation studies [2] will offer important insight into how ming current by effectively reducing the BEC/GST area, it
transient thermal conditions affect device performance still requires lithography to define the GST dimension for a
metrics such as resistance drift, threshold switching volt- small contact with the underlying heater. To realize an
age, cycling behavior, interface degradation, and reliability. ultrasmall lithography-independent contact area, the
From this discussion it is clear that the search for the cross-spacer PCM architecture has been demonstrated
best phase change material is a multiparameter optimiza- using a 180-nm technology [66]. By replacing the
tion process with some seemingly contradictory require- BTrench[ width by the thickness of both the phase
ments such as high stability of the amorphous phase at change material and the low-temperature oxide spacer
operating temperature, but very fast crystallization of the sidewalls, this fully litho-independent process leads to an
amorphous phase at switching temperature. Many material ultralow reset current of 80 A for a 500-nm2 cell [66].
parameters will also change with size of the phase change Another issue associated with the BTrench[ device is
material when devices are scaled to smaller and smaller the alignment tolerance. The BWall[ structure, utilizing
dimensions (see Section VIII-A). Much research is still the self-aligned (SA) approach, was hence developed with
required to understand the fundamental relationship be- a 90-nm technology [67]. The BWall[ structure simplifies
tween material composition and structure, and phase the overall process integration by reducing one critical
change properties for a physics/chemistry-based design of mask and depositing the chalcogenide material on a flat
new phase change materials. surface. A 200-A reset current was obtained for a
0.0108-m2 cell at the 45-nm technology node [68].
The Bpore[ structure is another litho-independent
IV. DEVICE DESIGN technology that gives very small contact area and low reset
current [69]. The pore diameter can be accurately defined
A. Device Structures and Programmed by an intentionally created keyhole with conformal depo-
Volume Scaling sition. Less than 250-A reset current has been realized for
The large programming current is still a key issue that a pore PCM cell with a patterned 40-nm diameter.
limits the adoption of PCM in many applications. Further- Similar to the device structures that evolve from the
more, large programming current in PCM imposes a BTrench[ cells, a ring-shaped contact is another effective
stringent requirement on the current delivered by the approach for decreasing the contact area and hence the
memory cell selector (see Section V) integrated in series reset current. In ring-shaped contact, the current flows
with the PCM. In order to provide the current required to through the perimeter of the contact hole instead of the
switch the states of PCM, the area of the memory cell entire contact area. Since the area of the ring-type contact
selector may not be scaled down as fast as the memory cell is only linearly dependent on the diameter of the contact
itself, thus the size of the cell selection device becomes the and the thickness of the deposition metal, it not only has
limiting factor for the device density and annihilates the linear relationship with the resolution of the lithographic
small size advantage of PCM technology. Therefore, re- capability compared to the quadratic relationship of a
ducing the programming current is necessary for achieving conventional contact, but it also shows more robust char-
both high-density and low power consumption of PCM. acteristics against contact size variation [70], [71]. To im-
To decrease the reset current, one way is to increase prove the flatness of the ring-type contact (avoiding
the heater thermal resistance by reducing the contact area recessed core dielectrics inside the contact hole), non-
[61]. The feature size of the conventional mushroom recessed ring-type contact has also been demonstrated
structure [Fig. 2(a)] [61], [62] of PCM is limited by litho- using a 90-nm technology and it shows 450-A reset
graphy and process capability. This was recognized early current for a patterned 60-nm diameter contact hole [72].
on and many innovative device structures have been Along with the reduction of the contact area of the
explored to reduce the effective bottom electrode contact PCM cell, another way to reduce the programming current
(BEC)/GST interface to the sublithographic regime. is through current localization and thermal environment
The edge-contact-type cell was first fabricated using a optimization. Evolving from the conventional planar
0.24-m technology and demonstrated a very low reset (mushroom) structure to confined cell structure, the reset
current 200 A [63]. However, this lateral structure oc- current is localized in the thermally isolated cell and can
cupies a large layout area. Later, reset current reduction significantly decrease by 65% even without contact area
using the BTrench[ structure was demonstrated in a reduction [73]. Also, the thermal disturbance between
180-nm technology [64]. The contact area of the neighbor cells is greatly improved for the confined cell,
BTrench[ cell is defined by the vertical heater thickness which illustrates the importance of thermal environment
signs highlights the key thermal design principles for

PCM. The conventional mushroom cell structures dem-
onstrate favorable scaling [82] because the effective
thermal resistance scales inversely with contact area. The
edge-contact cell shows dramatically lower programming
current by using current crowding to maximize the heat
generation density near the device active region [63].
Confined cell designs show reduced programming current
and enhanced reliability and scaling by controlling the
temperature profile and leveraging TBR [74], [78], [83]–
[85]. A number of devices reduce the programming
current by engineering a larger TBR near the device active
region [86]–[89].
Compact models and finite-element simulations lend
insight into the key thermal design elements. Compact
Fig. 9. Reset current as a function of equivalent contact diameter,
models use resistor and capacitor networks for calculating
showing a linear scaling trend with the effective contact area as the the temperature and electrical current at discrete node
device feature size goes down. A constant 40-MA/cm2 current locations [81], [90]–[92]. They offer a convenient means
density is required to program the PCM cell. References are labeled for geometry optimization and, in their simplest form,
according to the number listed in Table 2 (column 1). yield closed form expressions capturing key device scaling
physics such as Ireset ðRe;eff Rth;eff Þ1=2 [81], where Ireset is
the reset current, Re;eff is the total device electrical resis-
control and cell geometry design. In order to achieve tance, and Rth;eff is the effective thermal resistance from
higher aspect ratio of the confined PCM cell, the chemical the active region. Finite-element simulations offer detailed
vapor deposition (CVD) technique for phase change mate- information about how the spatial distribution of thermal
rial has been developed, and a reset current as low as properties influences programming current, while calcula-
260 A has been realized using a 45-nm technology [74]. tions in [78] show its importance in reset current scaling.
To further reduce the reset current, self-aligned CVD PCM By reducing the temperature gradient in the lateral di-
cell combined with double-cutting process to reduce the rection, as seen in Fig. 10 [80], the TBR enforces a tem-
contact area has resulted in a 7.5-nm width, 30-nm depth perature profile that minimizes overheating in the center of
dash-type confined structure which gives a 160-A reset the active region while favoring the formation of an
current for sub-20-nm technology [75]. amorphous volume that completely encapsulates the bot-
PCM technology using various sublithographic techni- tom electrode contact. This phase distribution results in the
ques and cell structures has greatly reduced the reset minimum reset current. The combined effects of favorable
current and optimized the thermal control, which has temperature profile and increased effective thermal resis-
mitigated the arguably greatest obstacle for the production tance lead to reduced programming current. Additionally,
of PCM technology. Fig. 9 shows the reset current reduc- calculations in [78] show that the presence of TBR im-
tion as a function of the equivalent diameter of a circular proves reset current scaling with device dimension. Model-
contact and the effective contact area for different cell ing results suggest engineering the spatial distribution of
structures discussed above. We can clearly see the reset thermal resistances is essential for advanced PCM design.
current scales with the effective contact area of the PCM While current models do an excellent job informing
and that a constant current density 40 MA/cm2 is re- basic thermal device design, the extreme electrical and
quired to program the average PCM cell. Those with thermal conditions near the active region severely limit
carefully engineered cell structures and materials can be understanding of how nanoscale physics may affect future
programmed using 10 MA/cm2 . The technology char- device generations, illustrated schematically in Fig. 11.
acteristics of some of the recently published PCM device Lumped RC models adequately capture the physics im-
structures outlined above are summarized in Table 2. portant for general device scaling [81], but do not provide
the detailed temperature profile necessary for predicting
B. Thermal Design scaling of more advanced designs such as the confined cell
The review of various device structures in the previous [78]. Diffusion- and drift-diffusion-based finite-element
section illustrates the importance of thermal design for the calculations readily incorporate more sophisticated physics
PCM. The thermal design of PCM cells strongly affects the such as interface effects. However, as the characteristic
programming current, reliability, and scaling [78]–[80]. device dimensions approach the phonon and electron
Successful PCM implementations require careful analysis mean free paths, ballistic transport effects will become
and engineering of the heat generation and thermal- increasingly important for resolving the temperature and
resistance distributions [81]. The wide range of cell de- electrical current distributions. The heat generation and
Table 2 Characteristics of PCM Cell Device Structures
large temperature differences and nonequilibrium phonon

distributions. These effects introduce many thermal
design questions and modeling challenges for advanced
PCM. 1) How does the interface Seebeck effect influence
the distribution of heat generation, and consequently
device thermal efficiency? 2) What is the spatial extent of
this effect, and do detailed device simulations require
solutions of the Boltzmann transport equation? 3) Does
the interface WFL rule apply and how does this affect
thermal interface engineering to reduce programming
current? 4) How does coupling between electrons and
phonons influence the TBR and temperature profile?
Fig. 10. Temperature profiles for a confined cell device with 5) What is the appropriate TBR model at interfaces with
(a) no TBR, (b) 50-m2 K/GW TBR. The TBR reduces the reset current
by increasing the thermal resistance and enforcing a temperature
large T, such as the GST-bottom contact interface, and
profile favoring reduced reset current. how does it influence device scaling?
V. MEMORY CELL SELECTOR

thermal-resistance distributions will depend intimately on
Memory cells organized in an array must have a means to
electron phonon scattering physics in the interface region,
select the individual memory cells for reading and writing.
requiring the solution of the Boltzmann transport equation
The cell selection can be on an individual cell basis (bit-
to accurately capture the scaling of programming current,
alterable) or for a group of cells (e.g., an entire block of
phase distribution, and threshold switching voltage. Addi-
cells as in nand Flash). The memory cell selection device
tionally, coupled electron–phonon interactions near the
ensures there is no write disturb, the selected cell is writ-
interface give rise to a host of increasingly important
able, and there is adequate read signal-to-noise margin.1
effects: the interface Seebeck effect [93], the interface
For resistive memory cells, the memory cell selector also
WFL rule and its applicability [60], the role of electron–
minimizes static power dissipation by the resistive net-
phonon coupling in TBR [94], and the role of anharmonic
work. In fact, the density of the memory cell is in large part
phonon scattering in TBR, specifically at interfaces with
determined by the size of the memory cell selector. For nand
Flash, the data storage element (the floating gate) and the
memory cell selector are intimately integrated into one
single, compact device. Thus, nand Flash achieves very
high device density.
Ideally, the memory cell selection device has high
on-state conductivity, infinite off-state resistance, and
occupies a small layout area. Most of the PCM integration
steps are performed at back-end of the line (BEOL) pro-
cessing temperature conditions (G 450 C). Therefore, a
key challenge of integrating the memory cell selector is the
formation of a high-quality access device on top of pre-
existing CMOS address/decode/sensing circuitry. An ideal
back-end compatible access device suitable for driving
memory elements in a reasonably large array (say 1000
1000 elements) should have a drive current capability well
in excess of 106 A/cm2 , and an on/off ratio greater than
106 to limit power consumption due to leakage paths and
ensure successful read and write.
Metal–oxide–semiconductor field-effect transistors
(MOSFETs) [4], bipolar transistors (BJT) [65], and diodes
[70] have been used. BJTs and diodes have similar device
Fig. 11. The thermal design considerations increase quickly in physical structures, differing only in the doping of the junctions and
complexity as PCM devices scale. In the figure, d represents the
characteristic length scale in the device, deff is an effective length scale
for reduced geometries, R indicates electrical or thermal resistance,
R eff represents an effective resistance (electrical or thermal), 1
A cross-point array of ð106 Þ resistive memory cells can satisfy the
is the carrier mean free path, ph indicates a phonon, and read/write requirements only if the on-state resistance of the cell is of the
e indicates an electron. order of a few M and above. See [95].
Table 3 Memory Cell Selection Diode Published in the Literature
the presence of the base contact [96]. Diodes can have the tact, depending on gate to contact distance) for the PCM
minimum 4 F2 layout area (F is the minimum lithographic with a MOSFET selector.2
feature size). By sharing the base contact with several cells, Memory cell selectors demonstrated recently include
the footprint of a BJT selector ranges from 8 F2 to about the use of pn-junction diode [62], [70], [98]–[100],
5.5 F2 [68]. The device width of the MOSFET selector is Schottky diode [101], metal-insulator transition (MIT)
largely determined by the programming current required. [102], and the ovonic threshold switch (OTS) [57]
Unlike nand for which the programming current per cell (Table 3). PN-junction diodes with various materials
is small, PCM requires a substantial reset programming have been studied, including polySi, epitaxially grown sili-
current. Fig. 9 summarizes PCM programming current as a con, doped semiconducting metal oxide, and Ge nanowire.
function of the bottom electrode contact area. The large Suffice it to say that it has been difficult to find a cell
reset current calls for good a quality diode/BJT or a wide selection diode that simultaneously satisfies the on/off
device width for a MOSFET selector. For device structures ratio requirement (depends on the memory subarray size)
where the contact area depends on the lithographic di- and the on-current required to program the PCM. While
mension linearly (e.g., ring shape, Trench, wall-type), conventional wisdom would search for a selector with a
special care is required to ensure reset current scaling high on/off ratio, recent analysis [95] suggests that a
down with technology node. Otherwise, the current device with sufficient nonlinearity between the low-bias
density required scales up as the technology scales down. (nonselected) and high-bias (selected) regime will
The trend line indicates that the current density required suffice. This may widen the choice of materials and de-
of the diode (or BJT) is in the range of 10–20 MA/cm2 for vice types for the selector. At the same time, innovative
the best PCM devices. For a contact diameter of 10 nm, the thermal design may substantially lower the programming
reset current is projected to be about 40 A. Assuming a current density required. It remains hopeful that
future low-power MOSFET selector with a 1.2-mA/m stackable cross-point arrays of PCM will be realized in
current drive [5], the MOSFET selector device width the future.
should be 33 nm (3.3 F for a 10-nm technology), resulting
in a footprint [68], [97] of about 17–22 F2 (with a device 2
The footprint can be 8–10 F2 for programming density of
pitch of 4–5 F in the length direction with a shared con- 10 MA/cm2 .
Fig. 12. Cost projections for multibit and multilayered PCM.

After [104].
Fig. 13. Higher doping results in a more gradual resistance transition,

as seen in this plot of resistivity versus temperature for different
nitrogen doping levels in Ge 2 Sb2 Te 5 . Doping is an excellent materials
VI. MULTIBIT OPERATION AND
engineering option to enable multibit operation in PCM. After [107].
3- D INT E GRAT ION
There are two methods to increase the available storage
capacity per unit area of a memory chip: 1) multibit
operation wherein each memory element is programmed perties of the chalcogenide layer or by stacking multiple
to store more than one bit of information and 2) multi- layers with differing electrothermal properties as the
layered architecture wherein multiple layers of memory storage medium. Implanting species such as nitrogen into
elements are stacked one above the other, sharing the the GST films (Fig. 13) was shown to modulate the RT
addressing and sense-amplification circuitry among the curve of the thin film, making the transition between the
memory layers [103]. Owing to factors related to mask high- and low-resistance states more gradual with tem-
costs, fabrication yields and reliability concerns, the pay- perature, thus enabling multibit storage [106], [107]. It
off associated with multilayered systems is lesser when was shown that two or three stable intermediate-
compared to multibit systems (Fig. 12). In this section, we resistance levels could be attained in a cell by stacking
will review the PCM related advances in both these multiple chalcogenide layersVin one demonstration, the
directions. stack composed of a series stack of pure GST and silicon-
doped GST separated by a thin metallic tungsten layer
A. Multiple Bits per Element [108], another example used a bilayer stack made of
Two factors have enabled the realization of multibit Ge2 Sb2 Te5 and Sb2 Te3 [109] and a third had a trilayer
PCM: 2) the resistivity contrast exhibited by the different stack of Si16:4 Sb32:5 Te51:1 separated by TiN thin films
phases of phase change materials typically exceeds 2–3 acting as local heaters [110] (Fig. 14). These cell structures
orders of magnitude (see Fig. 4), and this high on/off relied on the differences in the heating profile generated
ratio can be exploited for populating intermediate states due to Joule heating, owing to the differences in
for data storage and 2) it is possible to engineer the device resistivity states of the chalcogenide layers, in order to
structure, the electrical and thermal properties of the achieve the stable intermediate-resistance states.
phase change materials, and programming strategies to These demonstrations thus depended on precisely en-
access intermediate-resistance states by controlling the gineering the cell structure to achieve the intermediate-
dimensions of the least resistive current paths within the resistance states; however, even conventional cell
memory element. This was realized since the early days of structures such as the common Bmushroom[ phase change
research on phase change materialsVa patent issued in element could be programmed to store multibit data by
1995 to S. Ovshinsky and co-workers already mentions the iterative programming techniques [107]. It was shown that
possibility of programming the memory cell to store by varying the amplitude or slope of the trailing edge of
intermediate-resistance levels for data storage [105]. the programming pulses to control the evolution of
Some of the earlier proposals for multilevel cell (MLC) temperature in the cell (Fig. 15), up to 16 intermediate
realization in PCM were based on engineering the pro- levels could be programmed in a cell, thus demonstrating a
Fig. 14. Measured RV curve of stacked phase change cell employed
Fig. 16. Typical Rcell Ipulse curve obtained by varying the current pulse
to obtain multibit storage in [110]. Shown in the inset is a schematic
amplitude for a mushroom PCM cell. Before the application of the
of the stack of phase change materials within the cell.
programming current pulse, an initialization pulse was applied to
fully reset the cell. Programming currents with amplitude in the
0–400-A range leads to annealing of the amorphous volume and
4-b cellVthis was (and remains at the time of writing) the a decrease in the cell resistance (the branch to the left of the minimum
R cell point), while programming currents with amplitude in the
most advanced multibit demonstration among any emerg-
500–1500-A range lead to melting of the critical volume and an
ing memory technologies. These programming techniques increase in the cell resistance (the branch to the right of the minimum
are based on the fact that the cell resistance Rcell can be R cell point). After [107].
increased by applying programming pulses of larger
amplitudes that result in melting of larger volumes of
the amorphous region (right branch in Fig. 16), or can be
decreased by applying pulses of lower amplitude (left resistance distributions because of nanoscale variations in
branch in Fig. 16), or sequences of annealing pulses of the cell structure and operating characteristics. Based on a
appropriate magnitude to crystallize and shrink the size of read–verify–write algorithm, an average of three iterative
the amorphous volume [111]. programming cycles were found to be adequate to
As in nand Flash MLC, it is necessary to apply program a collection of 100 cells to 16 intermediate
iterative programming to achieve tight and separable levels (Fig. 17). It has been shown that such iterative
programming techniques could be used to achieve write
Fig. 15. Electrothermal simulation reveals that the shape and size Fig. 17. 10 10 array test structure programmed into 16 levels,
of the amorphous plug can be controlled by the pulse-tail duration enabling 4 b/cell operation. Iterative programming techniques relying
(linear ramp-down at pulse-end). The amorphous constriction in the on adjustment of pulse slopes depending on measured resistance is
current path determines the overall cell resistance. After [107]. essential to achieve narrow distributions. After [107].
Fig. 18. The iterative programming algorithm employed to demonstrate 2 b/cell operating in BJT selected 256-Mb PCM array (left).
On the right, well separated resistance distributions (solid lines) that are stable after a bake for 1 h at 150 C (dotted lines) obtained are
also shown. Note that the levels 01, 10, and 11 all differ only by a factor of 2. After [112].
performance of 3.5-MB/s and read performance of 120 ns cell [116] and the parallel multiconfined cell (Fig. 19) [58]
on a 256-Mb BJT selected PCM array implementing 2 b/ are other examples that use this parallel resistance
cell (Fig. 18) [112]. combination philosophy in obtaining intermediate-resis-
In most of the cell structures discussed so far (except tance levels. In these instances, the parallel combination
the cell used in the 256-Mb chip demonstration [112]), the consists of materials with different thermal and crystal-
overall cell resistance is determined by the series combi- lization properties.
nation of multiple resistances (that could be modulated by
programming pulses) within the memory element. In such B. 3-D Stackable Memory (Multiple Layers per Chip)
schemes, the programmed resistance states typically span A vision for high-density memory is the cross-point
the entire available resistance spectrum in a uniform man- architecture with a memory cell integrated with a cell
ner. For example, note that the 16 levels shown in Fig. 17 selector within a 4 F2 footprint that can be stacked in the
are engineered to be Bequally spaced[ in the logarithmic third dimension (Fig. 20). To realize this, the selector
scale. However, it has been observed that the measured should have a 4 F2 footprint that can be scaled with the
cell resistance drifts to higher values exhibiting a power- bitline/wordline pitch, a large on/off current ratio, and
law behavior of the form RðtÞ ¼ R0 ðt=t0 Þ , where R0 is an on-state current that is sufficient for programming
the measured resistance at time t0 and is the drift the memory (the reset current for the case of PCM).
coefficient [12]. The drift coefficient itself is found to
increase with the programmed resistance state [113], and
thus the uniform use of the available resistance spectrum
for data storage might lead to retention and reliability
concerns [114].
It is also possible to engineer the programming tech-
nique or the cell structure such that the overall cell re-
sistance is determined by the parallel combination of
multiple resistances; in such cell structures where resis-
tances are added in parallel, the low-resistance region of
the resistance spectrum is populated with more interme-
diate state levels. The iterative programming scheme
using the sequence of set pulses to control the cell
resistance, employed in the 256-Mb chip demonstration
[112], is an example of this strategy; note that the read
currents (and hence the resistance) of the levels 01, 10,
and 11 all differ by a factor of 2 in Fig. 18. Here, the
intermediate-resistance states were obtained by first
creating an amorphous plug covering the bottom electrode
Fig. 19. The programmed resistance levels as a function of the
and then creating conductive paths of different widths amplitude of programming current for the parallel multiconfined cell.
through the amorphous region by the application of Shown in the inset is the schematic of the cell structure. The target
sequences of annealing pulses [115]. The lateral top-heater resistance levels were 10, 15–45, 60–110, and 500 K. After [58].
Fig. 20. Cross-point memory with a memory cell integrated with a

cell selector within a 4 F 2 footprint. This structure can be stacked
in the third dimension.
Fig. 21. Scanning electron microscope (SEM) cross section of a
PCM cell driven by an OTS switch (left) and the IV characteristics
of a PCMþOTS cell in set and reset. Voltage is normalized to the
threshold voltage of the set state. Cell current is normalized to the
Furthermore, the fabrication process should be compat- least current required to amorphize the material. After [57].
ible (e.g., material and process temperature) with CMOS
BEOL and the memory cell as discussed in Section V.
The trend for the reset current (Fig. 9) shows an
average of 40 MA/cm2 with the lower bound of about VII. RELIABILITY
10 MA/cm2 . This large current is fairly difficult to achieve
When billions of memory cells are integrated in a single
even for single crystal silicon diodes. A pþ inþ diode
memory chip, the intrinsic reliability characteristics of
provides the best combination of high on-current and low
memory devices become critically important for cost re-
off-current. The diode is in the high-level injection regime
duction and performance improvement because chip yield,
when fully turned on and the i-region acts like a resistor in
density, and operating speed are limited by reliability
this regime. The i-region is fully depleted in the off-state
characteristics of the worst cell. In addition, almost all
to reduce off-current. A low contact resistance (specific
memory devices in the memory hierarchy use peripheral
contact resistivity G 107 -cm2 ) to the diode is required
circuitry techniques to improve chip-level reliability.
for high on-current. Diodes or BJTs that are not fully
These techniques are tailored specifically to each memory
isolated by dielectrics also can suffer from parasitic leakage
technology because their physics and mechanisms related
and parasitic BJT conduction from neighboring cells that
to main reliability issues are unique for each technology,
can limit their density [117].
i.e., error-correction code and wear leveling techniques for
Two recent experiments have demonstrated progress
nand Flash technology. Therefore, we need to understand
in potentially achieving multilayered PCM arrays.
the physics, mechanisms, and characteristics related to the
Sasago et al. [62] used a low-thermal budget process to
reliability of PCM to improve cost and performance, and
fabricate a 4 F2 poly-silicon diode with a drive current
develop appropriate peripheral circuitry techniques.
capability in excess of 8 MA/cm2 and on/off ratio more
Since high-density integration of PCM devices are at
than 104 . They were able to boost the on-current by
the early stage, much more work is needed to fully
carefully engineering the interfacial contact resistance
understand the reliability of PCM. Endurance (cyclability)
between the poly-silicon layer and the metal electrodes.
is an important reliability characteristic because higher
Kau et al. [57] used a stackable cross-point PCM utilizing
endurance broadens the application area where frequent
the OTS property of chalcogenide materials to make the
read/write is required. Thermal disturbance is another
memory cell selector (Fig. 21). Since both the memory
reliability characteristic which is unique to PCM due to its
device and the selector exhibit threshold switching be-
deliberate use of heat as a programming mechanism. In
havior, the programming voltage conditions have to be
this section, we discuss reliability of PCM in terms of
carefully chosen to avoid disturbing the state of the cells
material and device characteristics.
in the unselected bit and word lines. Both these technol-
ogy demonstrations could enable stackable PCM arrays,
which might be required to make a competitive and eco- A. Endurance
nomically viable storage class memory technology [8]. Cyclability is an important materials issue. The two
However, so far, there has not been a demonstration of main failure modes of a PCM cell are either stuck open or
3-D stacked PCM memory cells despite the strong moti- stuck close. Stuck open is mainly caused by void formation
vation of doing so. at the bottom electrode interface. Many phase change
Fig. 22. Transmission electron microscope (TEM) pictures of PCM cells

using undoped (left) and doped (right) Ge 2 Sb2 Te 5 phase change
material after 10-K cycles (left) and 100-M cycles (right). While large
voids start to form on top of the bottom electrode only after 10-K
cycles for the undoped material, the cell with doped material shows no
voids even after 100-M cycles. Reprinted with permission from [119].
Fig. 23. The simulated temperature (T 2 , see inset) in the adjacent cell
materials including the materials on the GeTe–Sb2 Te3 [bit (2)] during thermal disturbance from programmed bit (1) for
various technology nodes under isotropic scaling. The simulated
pseudobinary line show a relatively large increase in mass
temperature is at the end of a 50-ns program pulse in bit 1 (squares)
density upon crystallization of about 5%–8% [118] leading and the corresponding steady-state value (circles). The temperature
to stresses in the material and void formation upon re- does not increase for smaller technology nodes due to scaling of the
peated cycling. Doping of the material can improve the thermal disturbance distance. Adapted from [123].
cyclability because in many cases it leads to finer grains
and less void formation [119]; see Fig. 22. The other failure
mechanism, stuck close, is often caused by elemental
at the early stage after reset programming [2]. Therefore,
segregation upon repeated cycling. It was observed that
thermal disturbance has been the main concern for
repeated cycling leads to Sb enrichment at the bottom
scaling of PCM because shorter distance between cells
electrode [120]. Sb rich materials have a lower crystalli-
can potentially lead to a larger amount of thermal
zation temperature leading to data loss and crystallization
disturbance.
of the region above the bottom electrode at much lower
The amount and duration of thermal disturbance and
temperatures than the original material composition.
their scaling properties have been modeled and simulated
Important material parameters for PCM reliability
[61], [122], [123]. Their results show that isotropic scaling
include the chemical stability of the material in contact
where the cell dimensions are scaled by the same scaling
with the electrodes and the melting temperature. In a
factor causes thermal disturbance to proportionately scale
typical mushroom cell (Fig. 2) the interface between the
by the same scaling factor (Fig. 23). Therefore, isotropic
bottom electrode and the phase change material is the
scaling makes thermal disturbance neither better nor
most critical one because this is the region where the phase
worse than the current node. However, when cell dis-
change material is repeatedly melted. A thin Ti layer is
tances are scaled more aggressively at successive technol-
often used as an adhesion layer but it was observed that for
ogy generations to improve density and performance,
a Ge2 Sb2 Te5 /Ti interface, severe interdiffusion between
thermal disturbance can be exacerbated. Therefore, any
the Ti and the phase change material occurs [121]. It could
scaling optimization should involve the careful evaluation
be avoided using a Ge2 Sb2 Te5 /TiN interface. This bottom
of thermal disturbances.
electrode interface needs to be carefully tailored to avoid
failure at this location due to interactions between the
electrode material and the phase change material. VI II . DEVICE AND MATERIAL S CALING
TO THE NANOME TE R S IZ E
B. Thermal Disturbance of PCM
Considering the large temperature rise required for A. Materials Scaling Properties
PCM reset programming, the adjacent cells are thermally Nanomaterials have properties that are different from
disturbed during reset programming of the selected cell. bulk materials of the same composition because surface
Thermal disturbance (thermal crosstalk, proximity dis- and interface atoms play an increasing role. The same is
turb) can result in the partial crystallization of the cell true for phase change nanomaterials. It is important to
causing retention failure. At the same time, the drift know how phase change properties change with size in
behavior is also affected by thermal disturbance because order to be able to evaluate the scalability of PCM technol-
the drift is dependent on temperature [33]. The drift ogy. If PCM cells are scaled down to dimensions where the
behavior expedited by thermal disturbance leads to wider phase change material is so small that the properties of the
resistance distributions when cells are thermal disturbed phase change materials are size dependent these changing
properties will modify the cell operation, and it is crucial

to know in which way.
Scaling studies of phase change materials have been
done on thin films, nanowires, nanoparticles, and PCM
devices (see [76], [120], and [124] for overviews). It was
found that many properties of the phase change materials
do depend on size, in particular below the 10-nm range.
These changing properties include crystallization tem-
peratures and times, related activation energies for crys-
tallization, melting temperatures, resistances, and optical
and thermal properties. What becomes clear from studying
the literature is the dramatically increased effect of
interfaces [125]–[127]. Crystallization temperatures can
vary by up to 200 C and can be increased or decreased for
very thin phase change films depending on the interface
material [125], [127] while crystallization times can also be
changed (increased or decreased) by changing the
interfaces [127]. Melting temperatures are reduced for
thinner films [120] which is advantageous because it will
reduce the power to melt-quench the material. Resistances
on the other hand are increased when film thickness is
reduced [126]. Fig. 24. TEM images of size selected samples. All scale bars are 10 nm.
While these dependencies increase the complexity of (a) Small nanoparticles of 1.8 0.44 nm. (b) Medium nanoparticles of
materials optimization they also enable us to tune inter- 2.6 0.39 nm. (c) Large nanoparticles of 3.4 0.74 nm. d) Dynamic
light scattering results of another instance of size selected
facial properties in such a way that switching properties nanoparticles. Reprinted with permission from [133], copyright
are improved, e.g., by introducing interfaces that reduce Royal Society of Chemistry (2010).
crystallization times or increase crystallization tempera-
tures. In fact, some devices have only been enabled by
scaling film thicknesses to very small values, e.g., devices
[133]. Fig. 24 shows TEM images of these GeTe nano-
of pure Sb have been fabricated [23] that operated at room
particles of various sizes. Down to these small sizes
temperature even though bulk pure Sb is always crystal-
phase change materials still do not lose their phase
line. Only by scaling the film thickness to 4 nm in these
change properties. These nanoparticles are as small as
devices was it possible to stabilize the amorphous phase at
about two to three times the lattice constant, so this will be
room temperature because the crystallization temperature
close to the ultimate scaling limit of phase change tech-
of Sb increases substantially when film thickness is
nology as far as the phase change materials themselves are
reduced.
concerned.
Phase change nanoparticles have been fabricated by
The great challenges for the materials scientist from
a variety of techniques including pulsed laser ablation
the technological standpoint will include finding phase
[128], [129], electron-beam lithography [18], self-
change materials that do not show void formation or
assembly base lithography techniques using sputter
elemental segregation, tailoring the increasingly important
deposition [130], [131] or spin-on phase change materials
interfaces that support high cyclability, good data reten-
[132], and solution-based chemistry [133]. In general,
tion, and fast switching, and continuing the study of
large nanoparticles show properties similar to bulk, but
scaling properties of phase change materials as dimensions
the smallest nanoparticles below about 10 nm show size-
shrink to the few nanometer length scale.
dependent crystallization, in most cases increased crystal-
lization temperatures, and reduced melting temperature.
Both are beneficial for PCM applications and demon- B. Device Scaling Properties
strate the favorable scaling properties of phase change One aspect that has drawn little attention so far but
materials. will be important for device scaling is the scaling of the
The ultimate limits of scaling will be reached when threshold switching effect. Depending on the model,
materials do not exist stably anymore in both phases. For defects play an important role as traps or as the main
the phase change material GeTe it has been demonstrated transport channel for threshold switching [11], [12], [33].
that nanoparticles can be synthesized in the amorphous The average distance between these defects is on the order
phase and can be crystallized by heating them over their of a few nanometers [11] and it is not clear if this physical
(remarkably increased compared to bulk) crystallization picture of the threshold switching properties can remain
temperature for nanoparticle sizes as small as 1.8 nm valid when the defect distance becomes comparable to the
Fig. 25(a) and (b) shows the device structure of the

PCM cell with the ATE in comparison with a conventional
one. The ATE metal layer is placed inside the chalcogenide
layer. Due to the large thermal and electrical conductiv-
ities of the ATE layer, the threshold switching is confined
in the GST1 layer and the reset resistance is determined by
the size of the amorphous volume in the GST1 layer
[Fig. 25(c) and (d)]. Therefore, the threshold switching,
resistance drift, and crystallization temperature depen-
dence on the GST thickness can be studied by varying the
GST1 layer thickness. It has been shown that the threshold
Fig. 25. (a) Schematic view of typical T-shape PCM. (b) Reset state and switching voltage is linearly increasing with GST1 layer
(c) set process of the PCM cell with the ATE. Adapted from [135]. thickness with a nonzero offset (Fig. 26). The resistance
drift did not show any dependence on the thickness. The
crystallization temperature increased for thinner GST1
film thickness. The same applies to the finite distance the layers, showing the same trend for increasing crystalliza-
electrons need to gain enough energy for threshold tion temperature for thinner phase change material layers
switching [134]; it is not clear how threshold switching measured by X-ray diffraction [136].
properties will change when the film thickness becomes
comparable to this distance. In this section, we review 2) Phase Change Material Nanowire Devices: Nanowire
some of the device structures specifically designed to PCM devices with phase change material nanowires ena-
investigate the scaling behavior of PCM for small bled 2-D scalability studies without resorting to complex
thicknesses of the amorphous region and summarize the lithography, special device structures, or etching of the
findings. phase change material into nanometer size [137]–[140].
The mechanism of bottom-up synthesis of these nanowires
1) 1-D Thickness Scaling Study With the Additional Top is the vapor–liquid–solid (VLS) process with catalysts.
Electrode PCM Cell: As we have seen in previous sections, Nanowires were grown from various phase change mate-
material properties of phase change materials change as rials such as Ge2 Sb2 Te5 [137], [138], GeTe [139], [140],
the size of the material decreases. It is important to Sb2 Te3 [139], and In2 Se3 [140]. After making contacts to
understand how these changes in phase change material the nanowires (Fig. 27), the nanowires were successfully
properties would affect the operation of actual PCM cells. changed between reset (amorphous) and set (crystalline)
The PCM cell with the additional top electrode (ATE) states by electrical currents. The diameter of the nano-
resembles the structure of a mushroom- or T-type cell, wires was varied between 20 and 226 nm and the de-
which is the most common among PCM devices in devel- pendence of material properties and device characteristics
opment, while enabling the study of 1-D scaling char- on the diameter was studied including crystallization
acteristics of the phase change materials [135]. kinetics, melting temperature, and programming power.
Fig. 26. (a) IV curves and (b) V th for varying GST1 thickness (6–23 nm). Total chalcogenide height (GST1 + W (tungsten) ATE + GST2) is 257 nm for
all devices. All devices are first programmed to the reset state before IV measurement. Adapted from [135]. Trend lines for other phase change
materials from [23] are added for comparison. GeSb had a Ge:Sb ratio of 15:85, and AIST was Sb2 Te doped with 7 atomic % Ag and 11 atomic % In.
Fig. 27. SEM images of PCM devices incorporating individual GeTe

and Sb2 Te 3 nanowires. Insets show high-resolution TEM images of
respective nanowires. Reprinted with permission from [139].
Fig. 29. Dependence of the threshold switching voltage ðV th Þ on the

apparent amorphous region length ðlapp:amÞ. lapp:am is calculated
In phase change nanowires, size-dependent effects
from the RESET resistance ðR OFF Þ, cross-sectional area ðSÞ, and
have been observed as well [137], [138], [141]. For smaller resistivity of the amorphous phase ðam Þ. V th scaling changed from
nanowires crystallization times and temperatures and acti- constant-field to constant-voltage scaling at 10 nm of lapp:am.
vation energies are reduced, and this is attributed to en- Reprinted with permission from [139]. GST data from Fig. 26(b)
hanced heterogeneous nucleation at the surfaces [138]. For have been added for comparison.
instance, increased surface area-to-volume ratio resulted
in smaller activation energy for crystallization (Fig. 28)
[137]. This is different from ultrathin films where both scaling with the length of the amorphous region below
increased or decreased crystallization times and tempera- 10 nm (Fig. 29) [139].
tures can be found depending on the interfaces. The
reduced melting temperature due to large surface area-to- 3) Phase Change Bridge (PCB) Cell: The PCB device is a
volume resulted in low programming power [140]. It cell design uniquely suited to study the electrical scaling
might be possible to tailor nanowire properties by modify- characteristics of phase change materials [44], [143]. It
ing the interfaces by, e.g., growing core-shell nanowires comprises a narrow line of thin phase change material
with well-defined interfaces. Currently, phase change bridging two underlying electrodes (Fig. 30). The thickness
nanowires typically have a thin oxide surface layer, often
GeO2 [142]. Pressure-induced stress effects may also play a
role and will be different for nanowires and thin film
stacks of the same material. The threshold switching volt-
age scaling changed from constant field to constant voltage
Fig. 30. The schematic of the experimental setup (left) and the
SEM image of the fabricated PCB device (right). Electrical pulses
generated by the arbitrary waveform generator (AWG) are supplied to
the device under test (DUT), and the device behavior is monitored
Fig. 28. Size-dependent activation energies ðEa Þ for recrystallization using two oscilloscope channels measuring the device voltage and
of Ge 2 Sb2 Te 5 nanowires. The activation energies vary from 1.98 eV current independently. The inset shows the active device volume
for a 30-nm nanowire, to 2.34 eV for a 200-nm nanowire. Reprinted located above the narrow dielectric gap between the two electrodes.
with permission from [137]. After [144].
havior [133]. It remains to be seen how such small active

memory regions can be integrated into an efficient mem-
ory array. Scaling studies of PCM devices show observable
changes in device characteristics as device dimensions
(e.g., the amorphous region size) are scaled down and
therefore this scaling behavior must be accounted for in
future PCM designs.
The material properties and thermal properties of the
device present a rich set of possibilities for optimizing the
device characteristics to suit a variety of applications. As
future generations of PCM scale and incorporate more
sophisticated materials, improvements in performance
demand intimate understanding of phase change and
electrode bulk and interface properties. Carefully engi-
neered composite electrode and phase change materials
Fig. 31. Reset current scaling trend predicted (lines) using
electrothermal simulations for the PCB memory cell compare very
may significantly increase the thermal efficiency of de-
well with experimental data (symbols). Also note the open symbol vices without affecting their electrical performance. Mea-
showing lowest achieved reset current of roughly 90 A at longer surements must reveal the coupled nature of electron and
bridge length L ¼ 80 nm and H ¼ 3 nm. After [44]. phonon transport at device interfaces. Improved under-
standing of the thermoelectric effect in phase change
materials will shed light on how to tailor the heat gene-
of the phase change material H determines one critical ration distribution in the device. Nanoengineered inter-
dimension for current conduction within the memory faces in composite electrodes and at the electrode/phase
element. Since this dimension can be controlled by the change material interface may overcome the interface
deposition process, the structure enables a relatively WFL rule, allowing precise control of the temperature
straightforward scaling analysis of various electrical pro- profile through engineering the spatial distribution of
perties. Further, the cross-sectional area ðW HÞ depends thermal properties.
only linearly on lithography, resulting in much less sen- Understanding the electrical properties (conduction
sitivity to process induced variations. mechanism, threshold switching physics, properties of the
The device scaling trends are captured in Fig. 31 where traps, and their relaxation behavior) is essential to have a
the reset currents obtained by electrothermal simulations complete picture of the reliability of PCM. It is also es-
are plotted as a function of the critical parameters of the sential for a robust multibit memory operation. Power
device geometry. It can be seen that the required reset consumption of PCM, while still high in today’s technol-
current drops steadily as the device width W gets ogy, is expected to decrease as device size is scaled down.
narrowerValso note the close agreement between the Orders-of-magnitude improvement in the endurance and
simulations (lines) and measurement data (symbols). faster switching is required to open up DRAM-like appli-
The PCB structure is ideally suited for a variety of cation opportunities for the PCM. Substantial increase in
characterization experiments [23], [144]. For instance, the device density is required for high-density nonvolatile
critical field necessary for threshold switching for different storage that rivals nand and HDDs [8], [9].
materials has been obtained by plotting the measured The key technology for a high-density memory array,
threshold voltage of the PCB device as a function of the either in 2-D or 3-D stackable form, is not the PCM itself.
device length (Fig. 31). Device structures similar to the Rather, it is the memory cell selectorVbe it the transistor,
PCB device have also been used to demonstrate other the diode, the OTS [57] or other yet to be invented selector
second-order effects such as the thermoelectric Thomson switch. The memory cell selector occupies the most layout
effect in phase change materials and thermal disturbance area in the memory cell and it is difficult to meet the
in PCM [2], [145]. required specifications.3
With PCM developed to a point where it can now be
deployed in actual systems, an enormous opportunity is
IX. FUTURE OUTLOOK opened up to re-architect the way we use memory and
PCM has achieved significant milestones in recent years storage to achieve higher energy efficiency and enrich user
with a 90-nm product positioned as a nor replacement applications. h
[146] and a 45-nm technology demonstration [68]. Ad-
vanced research into the material properties of phase
change materials suggests that the phase change material 3
nand Flash has the unique feature that the storage element and the
can be scaled to single-digit nanometer sizes (2–5 nm) in memory cell selector is conveniently integrated into one compact
all three dimensions and still exhibit phase change be- transistor without requiring an explicit contact.
Acknowledgment and discussions. The contributions of the members of the

The authors would like to thank current and former IBM/Macronix PCRAM Joint Project are greatly acknowl-
students (Y. Zhang, M. Caldwell) who have contributed edged, as well as management support at the IBM Almaden
significantly to the material in this paper. They would also Research Center and the IBM T. J. Watson Research
like to thank Dr. Jim McVittie for the technical support Center.
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ABOUT THE AUTHORS

H.-S. Philip Wong (Fellow, IEEE) received the SangBum Kim received the B.S. degree from
B.Sc. (honors) degree from the University of Seoul National University, Seoul, Korea, in 2001
Hong Kong, Hong Kong, in 1982, the M.S. degree and the M.S. and Ph.D. degrees from Stanford
from the State University of New York at Stony University, Stanford, CA, in 2005 and 2010, re-
Brook, Stony Brook, in 1983, and the Ph.D. degree spectively, all in electrical engineering. His Ph.D.
from Lehigh University, Bethlehem, PA, in 1988, dissertation focused on scalability and reliability
all in electrical engineering. of phase change memory (PCM) including scaling
He joined the IBM T. J. Watson Research Center, rule analysis, germanium nanowire diode as a
Yorktown Heights, NY, in 1988. In September scalable selection device, thermal disturbance,
2004, he joined Stanford University, Stanford, drift, and threshold switching.
CA, as a Professor of Electrical Engineering. While at IBM, he worked on He has held intern positions at Samsung Advanced Institute of
CCD and CMOS image sensors, double-gate/multigate MOSFET, device Technology (SAIT) in 2007 working on PCM characterization and IBM. T. J.
simulations for advanced/novel MOSFET, strained silicon, wafer bonding, Watson Research Center, Yorktown Heights, NY, in 2007 on higher k gate
ultrathin body SOI, extremely short gate FET, germanium MOSFET, dielectrics. He is currently a Postdoctoral Researcher at IBM T. J. Watson
carbon nanotube FET, and phase change memory. He held various posi- Research Center. His current research focuses on characterization and
tions from Research Staff Member to Manager, and Senior Manager. modeling of PCM devices.
While he was a Senior Manager, he had the responsibility of shaping and Dr. Kim was awarded The Korea Foundation for Advanced Studies
executing IBM’s strategy on nanoscale science and technology as well as (KFAS) Scholarship and Samsung Scholarship to support his M.S. and
exploratory silicon devices and semiconductor technology. His research Ph.D. program, respectively.
interests are in nanoscale science and technology, semiconductor
technology, solid state devices, and electronic imaging. He is interested
in exploring new materials, novel fabrication techniques, and novel de-
vice concepts for future nanoelectronics systems. Novel devices often
enable new concepts in circuit and system designs. His research also
includes explorations into circuits and systems that are device driven. His
Jiale Liang (Student Member, IEEE) received the
present research covers a broad range of topics including carbon nano-
B.S. degree in microelectronics from the De-
tubes, semiconductor nanowires, self-assembly, exploratory logic devices,
partment of Microelectronics, Peking University,
nanoelectromechanical devices, novel memory devices, and biosensors.
Beijing, China, in 2007 and the M.S. degree in
Dr. Wong served on the IEEE Electron Devices Society (EDS) as elected
electrical engineering from Stanford University,
AdCom member from 2001 to 2006. He served on the International
Stanford, CA, in 2009, where she is currently
Electron Devices Meeting (IEDM) committee from 1998 to 2007 and was
working towards the Ph.D. degree in electrical
the Technical Program Chair in 2006 and General Chair in 2007. He
engineering.
served on the International Solid-State Circuits Conference (ISSCC)
She is currently working on the fabrication
program committee from 1998 to 2004, and was the Chair of the Image
and characterization of low-temperature selec-
Sensors, Displays, and Microelectromechanical Systems (MEMS) sub-
tion device for memory applications. She also works on the simulation
committee from 2003 to 2004. He serves on the Executive Committee of
and modeling of novel device and memory structures. Her research
the Symposia of Very Large Scale Integration (VLSI) Technology and
interests are device modeling, fabrication, and characterization.
Circuits. He was the Editor-in-Chief of the IEEE T RANSACTIONS ON
NANOTECHNOLOGY in 2005–2006. He is a Distinguished Lecturer of the
IEEE Electron Devices Society (since 1999) and Solid-State Circuit Society
(2005–2007).
Simone Raoux (Senior Member, IEEE) received John P. Reifenberg received the B.S. degree in
the M.S. degree in physics and the Ph.D. degree mechanical engineering with Departmental, Col-
in physics from Humboldt University, Berlin, lege and University Honors from Carnegie Mellon
Germany, in 1984 and 1988, respectively. University, Pittsburgh, PA, in 2003 and the M.S.
She is a Research Staff Member at the IBM T. J. and Ph.D. degrees in mechanical engineering from
Watson Research Center, Yorktown Heights, NY. Stanford University, Stanford, CA, in 2006 and
From 1988 to 1991, she worked as a Staff Scientist 2010, respectively. His graduate research focused
at the Institute for Electron Physics, Berlin, on photothermal and electrical metrology techni-
Germany, doing research in the field of electrical ques, modeling, and experiment design for under-
breakdown. From 1992 to 2000, she was a Staff standing nanoscale thermal phenomena in phase
Scientist at Lawrence Berkeley National Laboratory and performed change memory devices.
research in the fields of vacuum arc deposition, ion implantation, During his graduate work, he interned at the Intel Corporation
photoemission electron microscopy, X-ray magnetic circular dichroism, developing phase change memory device measurement techniques. He is
and near-edge X-ray absorption fine structure spectroscopy. She joined now a Senior Process Engineer at the Intel Corporation, Santa Clara, CA.
IBM in 2000, first at the IBM Almaden Research Center, and later moved His responsibilities center on the development of electron beam
to the IBM T. J. Watson Research Center in 2009. Her research at IBM lithography systems to advance photomask technology. His interests
included materials for magnetic recording and magnetic nanoparticles. are in nanoscale thermal physics, nanoscale materials design and
Her current research interests focus on the physics and materials science metrology, device modeling, design of experiment, and manufacturing
of phase change materials for application in memory technology and optimization.
synaptronics. She edited a book on phase change materials, contributed Dr. Reifenberg’s graduate studies were supported by a National
chapters to four other books, she is author and coauthor of more than Defense Science and Engineering Graduate (NDSEG) Fellowship through
120 peer-reviewed articles and 180 international conference contribu- the Office of Naval Research (ONR), and he was awarded an Honorary
tions, and she holds 14 patents. Stanford Graduate Fellowship.
Bipin Rajendran (Member, IEEE) received the Kenneth E. Goodson received the Ph.D. degree
B.Tech. (honors) degree in instrumentation engi- from the Massachusetts Institute of Technology
neering from Indian Institute of Technology, (MIT), Cambridge, in 1993.
Kharagpur, India, in 2000 and the M.S. and Ph.D. He is the Professor and Vice Chair of Mechan-
degrees in electrical engineering from Stanford ical Engineering at Stanford University, Stanford,
University, Stanford, CA, in 2003 and 2006, CA, where his group studies thermal phenomena
respectively. in electronic nanostructures and energy conver-
Currently, he is a Research Staff Member at IBM sion devices. His doctoral alumni include Profes-
T. J. Watson Research Center, Yorktown Heights, sors at the University of California Berkeley, MIT,
NY. He has published more than 25 papers in peer- the University of California Los Angeles, The
reviewed journals and conferences, and has been issued eight U.S. University of Illinois at Urbana-Champaign, and The University of
patents. His research interests include design and characterization of Michigan, as well as staff at Intel, AMD, and IBM. He has coauthored
novel semiconductor devices and novel materials for memory and logic more than 120 archival journal articles, 24 patents, two books, and eight
applications. At IBM, he is involved in exploratory research on phase book chapters. He is a founder and former CTO of Cooligy, which builds
change memory, involving process integration, device modeling, and microcoolers for computers and was acquired in 2005 by Emerson.
electrical characterization. Dr. Goodson received the Allan Kraus Thermal Management Medal
from the American Society of Mechanical Engineers (ASME), the Office of
Mehdi Asheghi received the Ph.D. and postdoc- Naval Research (ONR) Young Investigator Award, and the National
toral degrees from Stanford University, Stanford, Science Foundation (NSF) Career Award. He received the Outstanding
CA, in 1999 and 2000, respectively, conducting Reviewer Award from the ASME Journal of Heat Transfer, for which he
research in the area of nanoscale thermal engi- served as an Associate Editor. He was a JSPS Visiting Professor at The
neering of microelctronic devices. Tokyo Institute of Technology and is the Editor-in-Chief of Nanoscale and
Currently, he is a Consulting Associate Profes- Microscale Thermophysical Engineering. His research has been recog-
sor at Stanford University, focusing on further nized through keynote lectures at INTERPACK, ITHERM, and Therminic as
development of PCRAM technology. He led a well- well as best paper awards at SEMI-THERM, SRC TECHCON, and the IEDM.
known and funded research program (2000–2006)
at the Carnegie Mellon University, Pittsburgh, PA,
that focused on nanoscale thermal phenomena in semiconductor and
data storage devices. He is the author of more that 110 book chapters,
journal publications, and fully reviewed conference papers.

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INVITED

Phase Change Memory

longer than the crystallization time it leads to memory

A. Electrical and Switching Properties

With respect to switching speed, several time constants

conductivities at room temperature in ranges of 0.14–0.29,

signs highlights the key thermal design principles for

Table 2 Characteristics of PCM Cell Device Structures

large temperature differences and nonequilibrium phonon

V. MEMORY CELL SELECTOR

Table 3 Memory Cell Selection Diode Published in the Literature

Fig. 12. Cost projections for multibit and multilayered PCM.

Fig. 13. Higher doping results in a more gradual resistance transition,

Fig. 20. Cross-point memory with a memory cell integrated with a

Fig. 22. Transmission electron microscope (TEM) pictures of PCM cells

properties will modify the cell operation, and it is crucial

Fig. 25(a) and (b) shows the device structure of the

Fig. 27. SEM images of PCM devices incorporating individual GeTe

Fig. 29. Dependence of the threshold switching voltage ðV th Þ on the

havior [133]. It remains to be seen how such small active

Acknowledgment and discussions. The contributions of the members of the

REFERENCES Aachen, Germany, pp. 23–28, in chalcogenide–glass thin films,[ J.

ABOUT THE AUTHORS

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