Asus UX433FN - 2.0

UX433 SCHEMATIC Revision 0.
1
Power
SYSTEM PAGE REF.
Connected Standby PW_IMVP8
PAGE Content Page 80,81
FA: UMA
1 Block Diagram BLOCK DIAGRAM FN: DGPU=Nvidia MX150 + V2G +3VSUS/+5VSUS
2 System Setting Page 87
3 CPU_DISPLAY
4 CPU_DDR3L +1.8VSUS
5 CPU_LPC,SPI,SMB,CLINK Page 83
6 CPU_POEWR Page 13~15, 19 Speaker L/R
EC
Page 45
eDP woofer: 1W
7
8
CPU_XDP
CPU_MISC,JTAG,CLK
eDP
2 lane
CPU LPDDR3
CHA LPDDR3 on-board
DCR=7.2(ohm) +1.2V / +VTT / +1.8V
Page 39 Page 83
9 CPU_CFG,RSVD Page 48 DDI12 32bits * 2
HDMI
10
11
CPU_POWER_CAP
TBT_Alpine-Ridge
GDDR5 on-board
32bits * 2
Whisky-Lake LPDDR3
CHB LPDDR3 on-board
+1.05VSUS
12 TBT&TSP65982&Type_C_port1 Page 3~9

32bits * 2
Smart AMP Page 84
13 LPDDR3_TERMINATION Page 70~79 PCIE_9~12 TAS5766M +5VSUS_R

14 LPDDR3_ON-BOARD_A DGPU_N17S-LG Page 39 Page 86
15 LPDDR3_ON-BOARD_B I2S
16 Charger
19 LPDDR3 CA_DQ VOLTAGE Page 89
20 CPU_PCH_CFG,DISPLAY
Audio Jack
21 CPU_PCH_CGPIO, LPIO, MISC CPU_SMB HDA Audio Codec Load Switch
Debug Conn.
22 CPU_PCH_SATA,JTAG,AUDIO,RTC
ALC3228 Page 88
23 CPU_PCH_PCIE,USB Page 44 Page 36 DMIC(CMOS Camera)
24 CPU_PCH_CLOCK SIGNALS LPC
Debug Conn.
25 CPU_PCH_SYS_POWER PWM Fan 1 PWM SATA_2 IO_BD
26 CPU_PCH_POEWR,GND Page 44
CNL-PCH
27 CPU_PCH_POEWR,GND
Page 50
PCIE_13~16 NGFF M.2 SSD
LP
28 PCH_SPI ROM,OTH, TPM Keyboard EC Page 51
29 D_DOOR_OPEN Page 31
ITE IT8225 BGA
30 KBC_IT8995 SMB0 7.1*7.1*0.97 CNVi
WLAN / BT
31 EC_KB_TP BAT/Charger Page 30
SIP ( Intel 9560 )
32 Lid Switch Page 60.89
SPI BRI
37 AUD_ALC295 SPI
39 AUD_SMA_TSA5766M PW_PROTECTION SMB1 SPI ROM I2C1
thermal sensor
41 TBT_TPS65982&Type_C_Port2 128M
Page 20~28
Touch Pad
44 BUG_Debug Page 90
Page 28
45 CRT_LCD Panel_CMOS_DMIC
0.2 BSU
DIMM
50 FAN Thermal Sensor
Page 31
51 M2_SSD Page 14
52 USB 2.0_5
CMOS Camera
53 IO_BD
56 LED_Indicator USB 2.0_4
57 DSG_Discharge Card Reader
58 PRO_PROTECT
60 DC_DC & BAT Conn.
62 ME_Conn & Skew Hole PCI-E* X1
PCIE USAGE
DEFAULT/OPTION Co-lay Clock
63 EMI RF Reserve DGPU
64 B TO B CONN
PCIE 5
DGPU
Port5 USB 3.0_1 USB 3.0 USB 2.0_1
Type A
65
PCIE 6
DGPU
67
PCIE 7
DGPU
68
PCIE 8
WLAN SIP
69
PCIE 9 Port0 USB 2.0
Type A(IO)
USB 2.0_2 Discharge Circuit
70
PCIE 10
IO_BD Page 57
71
PCIE 11
72
PCIE 12
SSD
USB 3.0_3 Reset Circuit
SATA SSD
73
PCIE 13
SSD
Port1 USB 3.0 USB 2.0_6
SATA SSD Page 25
74
PCIE 14
SSD
USB 3.0_4 Type C
SATA SSD
75
PCIE 15 / SATA 0
SSD SATA SSD DC & BATT. Conn.
76
PCIE 16/ SATA 1
77 USB 2.0 USB 3.0 Page 60
1 USB 3.0 (MB) USB3_1 USB 3.0 (MB)
80_PW_IMVP8 (1) 2 USB 3.0 (I/O) USB3_2 Skew Holes

81_PW_IMVP8 (2) 3 USB3_3 USB 3.0 Type C (MB) Page 62
83_PW_+1.2V/ +1.8VSUS 4 Card reader USB3_4 USB 3.0 Type C (MB)
84_PW_+1.0VSUS 5 Camera
EMI RF reserve
87_PW_+3VADSW/+5VSUS 6 USB 3.0 Type C (MB)
Page 63
88_PW_LOAD SWITCH 7
89_PW_CHARGER(ISL9237 (NVDC +HPB)) 8
90_PW_PROTECTION 9 Project Name Rev
10 SIP BT UX432 R1.0
Title : Block Diagram

Size
Dept.: ASUSTeK COMPUTER INC. Engineer: Tony1_chang
Custom
Date: Wednesday, July 18, 2018 Sheet 1 of 102
Power on Int.& Ext Power on Int.& Ext
PCH_CPT PCH_IBEX GPIO Use As Signal Name Default States Pull up / down Power PCH_IBEX GPIO Use As Signal Name Default States Pull up / down Power EC Pin Name Config Signal Name Default status Ext Pull up / down Power
Design IP Source:
GPIO GPP_A0 Native1 RC_IN# EXT PU 10K +3VS GPP_D23 GPO N/A IT8225 GPA0 O PWR_LED LOW
GPP_A1 Native1 LPC_AD0 GPP_E0 GPO N/A +3VS GPIO GPA1 OD CHG_LED# HIGH EXT 10K PU@ +3VA_EC
SM_BUS ADDRESS :
GPP_A2 Native1 LPC_AD1 GPP_E1 GPO N/A +3VS GPA2 OD CHG_FULL_LED# HIGH EXT 10K PU@ +3VA_EC PCH Master
GPP_A3 Native1 LPC_AD2 GPP_E2 GPO N/A +3VS GPA3 Alt N/A LOW SM-Bus Device SM-Bus Address
GPP_A4 Native1 LPC_AD3 GPP_E3 GPO N/A GPA4 O CLICK_WAKE(NC) LOW EXT 10K PU@ +3VA_EC
GPP_A5 Native1 LPC_FRAME# GPP_E4 NATIVE SATA0_DEVSLP +3VS GPA5 Alt FAN0_PWM LOW
GPP_A6 Native1 INT_SERIRQ EXT PU 10K +3VS GPP_E5 GPO N/A +3VS GPA6 Alt N/A LOW
GPP_A7 GPO GPP_A7 EXT PU 10K +3VS GPP_E6 GPO N/A +3VS GPA7 O N/A HIGH
GPP_A8 Native PM_CLKRUN# EXT PU 8.2K +3VS GPP_E7 GPO N/A GPB0 Alt AC_IN_OC# HIGH EXT 100K PU power side +3VA
GPP_A9 Native1 CLK_KBCPCI_PCH GPP_E8 GPO N/A +3VS GPB1 I LID_SW# LOW EXT 10K PU +3VA
GPP_A10 Native CLK_TPMPCI_PCH GPP_E9 NATIVE USB_OC_1_2# EXT PU 10K +3VSUS GPB2 OD EC_GPB2 (NC) LOW EXT 10K PU +3VA_EC
GPP_A11 GPO N/A GPP_E10 NATIVE USB_OC_3_4# EXT PU 10K +3VSUS GPB3 Alt PWR_SW# HIGH EXT 10K PU +3VA
GPP_A12 GPO N/A GPP_E11 NATIVE USB_OC_5_6# EXT PU 10K +3VSUS GPB4 I PS_ON HIGH EC Master (SMB1) SM-Bus Address
GPP_A13 Native1 SUSWARN# EXT PU 10K +3VSUS GPP_E12 NATIVE USB_OC_7_8# EXT PU 10K +3VSUS GPB5 OD ACE_I2C_IRQ1Z High EXT 10K PU +3VA_EC SM-Bus Device
GPP_A14 Native1 PCH_SUS_STAT# GPP_E13 GPO N/A GPB6 OD RC_IN# LOW EXT 10K PU +3VS DIMM TEMP G781-1P8F 9Ah
GPP_A15 Native1 PCH_SUSACK# GPP_E14 NATIVE HDMI_HP R1.1 GPC0 O NC LOW PD controller TPS65982 74h
GPP_A16 GPO N/A GPP_E15 GPI EXT_SMI# EXT PU 10K +3VS GPC1 Alt SMB1_CLK LOW EXT 4.7K PU +3VA_EC Smart Amp TAS5766M 98h
GPP_A17 GPO N/A +3VSUS GPP_E16 GPI EXT_SCI# EXT PU 10K +3VS GPC2 Alt SMB1_DAT LOW EXT 4.7K PU +3VA_EC EC Master (SMB2)
GPP_A18 GPO GPP_E17 NATIVE EDP_HPD_CON EXT PD 100K +3VS GPC3 O PM_PWRBTN# HIGH EXT 10K PU@ +3VSUS PD controller TPS65982 SM-Bus Address
PU10K@
GPP_A19 GPO GPP_E18 GPO DDPB_SCL_PCH(NC) +3VS GPC4 O N/A LOW +3VS
GPP_A20 GPO GPP_E19 GPO DDPB_SDA_PCH(NC) +3VS GPC5 I PM_SUSC# LOW EXT 100K PD
GPP_A21 GPO GPP_E20 NATIVE DDPC_SCL_PCH EXT PU 2.2K +3VS GPC6 Alt BAT1_IN_OC# HIGH EXT 10K PD
GPP_A22 GPO GPP_E21 NATIVE DDPC_SDA_PCH EXT PU 2.2K +3VS R1.1 GPC7 O NC LOW
PCI Express USB Port
GPP_A23 GPO GPP_E22 GPO N/A GPD0 I PCH_SLP_S0# LOW
PCIE 1 N/A USB 1 Type C USB 3.0(MB)
GPP_B0 Native VCCPRIM_VID0 (NC_out) GPP_E23 GPO N/A GPD1 OD ME_AC_PRESENT LOW EXT 100K PU +3VA_DSW
PCIE 2 N/A USB 2 N/A
GPP_B1 Native VCCPRIM_VID1 (NC_out) GPP_F0 GPO N/A GPD2 Alt BUF_PLT_RST# HIGH
GPP_B2 GPO N/A GPP_F1 GPO N/A GPD3 OD EXT_SCI# LOW EXT 10K PU +3VS
GPP_B3 GPO N/A GPP_F2 GPO N/A GPD4 OD EXT_SMI# LOW EXT 10K PU +3VS
PCIE 5 N/A USB 5 CMOS Camera
GPP_B4 GPO N/A GPP_F3 GPO N/A GPD5 O OP_SD# HIGH PCIE 6 WLAN x1 USB 6 N/A
GPP_B5 GPO N/A +3VS GPP_F4 GPO N/A GPD6 Alt FAN0_TACH LOW EXT 10K PU +3VS
GPP_B6 GPO N/A +3VS GPP_F5 GPO N/A GPD7 O N/A LOW +3VS
PCIE 8 N/A USB 8 BT
GPP_B7 GPO N/A +3VS GPP_F6 GPO N/A GPE0 O SUSB_EC# HIGH EXT 10K PD
PCIE 9 SSD x4 USB 9 Finger Print
GPP_B8 GPO N/A +3VS GPP_F7 GPO N/A GPE1 O SUSC_EC# HIGH EXT 10K PD
PCIE 10 SSD x4 USB 10 N/A
GPP_B9 GPO N/A +3VS GPP_F8 GPO N/A GPE2 O 1.2V_ON
LOW PCIE 11 SSD x4
GPP_B10 Native CK_REQ_P5# EXT PU 10K +3VS GPP_F9 GPO N/A GPE3 O LAN_WAKE#(NC) HIGH SATA Port
PCIE 12 SSD x4
GPP_B11 Native MPHY_PWREN EXT PU 20K +3VSUS GPP_F10 GPO N/A GPE4 O EC_GPE4 (NC) HIGH SATA 0 N/A
GPP_B12 Native PCH_SLP_S0# GPP_F11 GPO N/A GPE5 I PM_SUSB# LOW EXT 100K PD SATA 1 N/A
GPP_B13 Native PLT_RST# GPP_F12 GPO N/A GPE6 O CAP_LED# LOW EXT 10K PU +3VS SATA 2 SSD
GPP_B14 GPO N/A INT PD 20K +3VS GPP_F13 GPO N/A GPE7 O THRO_CPU# HIGH PU 1K +VCCSTG SATA 3 N/A
GPP_B15 GPI CIO_PLUG_EVENT EXT PU 10K +3V GPP_F14 GPO N/A GPF0 O 5VSUS_ON LOW EXT 10K PU/ 1M PD +3VA_EC
Device Identification
GPP_B16 GPO GPIO_3_FORCE_PWR EXT PD 100K +3VS GPP_F15 GPO N/A GPF1 O VSUS_ON
LOW EXT 10K PU PD 1M@ +3VA_EC
CPU Thermal Senser
GPP_B17 GPO N/A +3VS GPP_F16 GPO N/A GPF2 Alt P_SMB0_CLK
LOW EXT 4.7K PU +3VA_EC
1st
GPP_B18 GPO N/A INT PD 20K +3VS GPP_F17 GPO N/A GPF3 Alt P_SMB0_DATA LOW EXT 4.7K PU +3VA_EC
2nd
GPP_B19 GPO BT_ON_PCH PU10K@ GPP_F18 GPO N/A GPF4 Alt TP_CLK LOW EXT 4.7K PU +3VS
GPP_B20 GPO N/A +3VS GPP_F19 GPO N/A GPF5 Alt TP_DAT LOW EXT 4.7K PU +3VS Memory Thermal Senser
GPP_B21 GPO N/A +3VS GPP_F20 GPO N/A GPF6 Alt PECI_EC LOW 1st 06G023048020 G781-1
GPP_B22 GPO N/A INT PD 20K +3VS GPP_F21 GPO N/A GPF7 O PCH_SPI_OV
HIGH 2nd
GPP_B23 Native SML1ALERT# EXT PU 100K +3VSUS GPP_F22 GPO N/A GPG0 O DGPU_LIMIT LOW
GPP_C0 Native SMB_CK (NC) EXT PU 2.2K +3VSUS GPP_F23 GPO N/A GPG1 O PCH_SUSACK# HIGH
GPP_C1 Native SMB_DATA (NC) EXT PU 2.2K +3VSUS GPP_G0 Native SDIO_CMD +3VS GPG2 I PWRLIMIT_EC# LOW EXT 100K PU +3VA_EC
GPP_C2 GPO N/A INT PD 20K +3VSUS GPP_G1 Native SDIO_D0 +3VS GPG6 O N/A
LOW
GPP_C3 Native SML0_CK (NC) EXT PU 2.2K +3VSUS GPP_G2 Native SDIO_D1 +3VS GPH0 Alt PM_CLKRUN# HIGH EXT 8.2K PU +3VS
GPP_C4 Native SML0_DATA (NC) EXT PU 2.2K +3VSUS GPP_G3 Native SDIO_D2 +3VS R1.1 GPH1 Alt SMB3_CLK HIGH
GPP_C5 GPO N/A INT PD 20K +3VSUS GPP_G4 Native SDIO_D3 +3VS R1.1 GPH2 Alt SMB3_DAT HIGH
GPP_C6 Native SML1_CK (NC) EXT PU 2.2K +3VSUS GPP_G5 Native SDIO_CD# +3VSUS GPH3 O PM_RSMRST# HIGH EXT 10K PD
GPP_C7 Native SML1_DATA (NC) EXT PU 2.2K +3VSUS GPP_G6 Native SDIO_CLK GPH4 O DPWROK_EC LOW EXT 10K PD
GPP_C8 GPO N/A +3VS GPP_G7 Native SDIO_WP GPH5 O PM_PWROK

LOW EXT 100K PD
GPP_C9 GPO N/A +3VS GPD0 Native PM_BATLOW_R# EXT PU 8.2K +3VA_DSW GPH6 O PM_SYSPWROK EXT PD 10K PU10K@ +3VSUS
GPP_C10 GPO N/A +3VS GPD1 Native ME_AC_PRESENT_PCH EXT PU 100K +3VA_DSW GPH7 O LCD_BACKOFF# LOW
GPP_C11 GPO N/A +3VS GPD2 GPO PCH_GPD2#(NC) +3VA_DSW GPI0 I PM_SLP_SUS# LOW EXT 10K PU@/ 100K PD@ +3VA_EC
GPP_C12 GPI DIMM_SEL0 EXT PU 10K +3VSUS GPD3 Native PM_PWRBTN# EXT PU 10K@ GPI1 I 3VSUS_PWRGD LOW EXT 100K PU +3VS
GPP_C13 GPI DIMM_SEL1 EXT PU 10K +3VSUS GPD4 Native PM_SUSB# EXT PD 100K GPI2 I ALL_SYSTEM_PWRGD LOW EXT 10K PU +3VS
GPP_C14 GPI DIMM_SEL2 EXT PU 10K +3VSUS GPD5 Native PM_SUSC# EXT PD 100K check!!! GPI3 I IMVP8_PWRGD LOW EXT 10K PU +3VS
GPP_C15 GPO N/A +3VSUS GPD6 GPO N/A GPI4 I 3VA_DSW_PWRGD LOW EXT 100K PU +3VA_DSW
GPP_C16 GPO N/A GPD7 GPO WLAN_ON#(NC) EXT PU 10K@ GPI5 I ME_SusPwrDnAck_EC LOW EXT 10K PU +3VSUS
GPP_C17 GPO N/A +3VSUS GPD8 Native SUS_CK GPI6 Alt A/D_MAX_POWER LOW EXT PD 0 PU100K@ +3VACC
GPP_C18 Native I2C1_SDA(NC) EXT PU 4.7K +3VS GPD9 GPO N/A GPI7 Alt MB_MAX_POWER LOW EXT PD 93.1K PU100K@ +3VACC
GPP_C19 Native I2C1_SCL(NC) EXT PU 4.7K +3VS GPD10 Native SLP_S5#(NC) GPJ0 O N/A
LOW
GPP_C20 GPO N/A +3VSG GPD11 Native LAN_PWREN(NC) EXT PU 10K +3VA_DSW GPJ1 O 3VADSW_ON
LOW EXT 100K PU +3VA_EC
GPP_C21 GPO N/A GPJ2 O N/A LOW

GPP_C22 GPO N/A +3VSUS GPJ3 O EC_GPJ3 (NC) LOW
GPP_C23 GPO N/A +3VS R1.1 GPJ4 O NC LOW
GPP_D0 GPO N/A GPJ5 O N/A LOW
GPP_D1 GPO N/A GPJ6 O WIN_KEY# (NC) LOW EXT 10K PU@ +3VS
GPP_D2 GPO N/A GPJ7 O N/A HIGH

GPP_D3 GPO N/A *1: EC config GPI; Function output
GPP_D4 GPO N/A
GPP_D5 GPO N/A
GPP_D6 GPO N/A
GPP_D7 GPO N/A
GPP_D8 GPO N/A
GPP_D9 GPI PCB_ID0 EXT PU10K@/PD 10K +3VS
GPP_D10 GPI PCB_ID1 EXT PU10K@/PD 10K +3VS
GPP_D11 GPO N/A
GPP_D12 GPO N/A +3VSUS
GPP_D13 GPI TOUCHPAD_INTR# EXT PU 10K +3VS check @
GPP_D14 GPO N/A +3VSUS

GPP_D15 GPO WLAN_BT_LED EXT PU 10K@ +3VSUS
GPP_D16 GPO SPI_INT# EXT PU 10K +3VS
GPP_D17 GPO Touch_Reset# EXT PU 10K +3VS
GPP_D18 GPO N/A
GPP_D19 GPO N/A
GPP_D20 GPO N/A
<Variant Name>
GPP_D21 GPO N/A
Project Name Rev
GPP_D22 GPO N/A UX432 R1.0
Title : System Setting

Size
Dept.: Engineer:
ASUSTeK COMPUTER INC. NB3 Tony1_chang
D
Display Port Main Board
EDP EDP Intel Version ASUS P/N
DDI1 N/A ES-0 01001-01540000
DDI2 HDMI ES-1 01001-01640000
01001-01660100
ES-2
01001-01660000 R1.0
0417
follow PPM Keypart list V04
U0301A
AL5 AG4
DDI1_TXN_0 EDP_TXN_0 EDP_TXN0 45
AL6 AG3
DDI1_TXP_0 EDP_TXP_0 EDP_TXP0 45
AJ5 AG2
DDI1_TXN_1 EDP_TXN_1 EDP_TXN1 45
AJ6 AG1
DDI1_TXP_1 EDP_TXP_1 EDP_TXP1 45
AF6 AJ4
DDI1_TXN_2 EDP_TXN_2
AF5 AJ3
DDI1_TXP_2 EDP_TXP_2
AE5 AJ2 R0.1
DDI1_TXN_3 EDP_TXN_3 NEED CONFIRM
AE6 AJ1
DDI1_TXP_3 EDP_TXP_3 2 Lane only? (depand on EDP panel)
AC4
48 HDMI_DATA2N_PCH DDI2_TXN_0
AC3 AH4
48 HDMI_DATA2P_PCH DDI2_TXP_0 EDP_AUX# EDP_AUXN 45
AC1 AH3
48 HDMI_DATA1N_PCH DDI2_TXN_1 EDP_AUX_P EDP_AUXP 45
AC2
48 HDMI_DATA1P_PCH DDI2_TXP_1
AE4 AM7
48 HDMI_DATA0N_PCH DDI2_TXN_2 DISP_UTILS
AE3
48 HDMI_DATA0P_PCH DDI2_TXP_2
AE1 AC7
48 HDMI_CLKN_PCH DDI2_TXN_3 DDI1_AUX#
AE2 AC6
48 HDMI_CLKP_PCH DDI2_TXP_3 DDI1_AUX_P
AD4
DDI2_AUX#
AD3
DDI2_AUX_P
AG7 +3VS
DDI3_AUX#
AG6
DDI3_AUX_P
CN6
GPP_E13/DDPB_HPD0/DISP_MISC0
CM6 R0302 1 2 10KOhm
GPP_E14/DDPC_HPD1/DISP_MISC1 HDMI_HP 48
CP7 EXT_SMI# R0303 1 2 10KOhm
GPP_E15/DPPD_HPD2/DISP_MISC2 EXT_SMI# 30
CP6 EXT_SMI# SL0304 1 2 EXT_SCI#_X1
GPP_E16/DPPE_HPD3/DISP_MISC3 0201 EXT_SCI# 30
CM7 EXT_SCI#_X1
GPP_E17/EDP_HPD/DISP_MISC4 EDP_HPD_CON 45
EDP_HPD_CON
CK11
EDP_BKLTEN LCD_BACKEN_PCH 45
CG11
EDP_VDDEN L_VDDEN_PCH 45
CH11
EDP_BKLTCTL L_BKLTCTL_PCH 45
AM6
DISP_RCOMP
EDP_COMP
CC8
GPP_E18/DPPB_CTRLCLK/
CC9 CNV_BT_HOST_WAKE#
GPP_E19/DPPB_CTRLDATA
CH4
48 DDPC_SCL_PCH GPP_E20/DPPC_CTRLCLK
CH3
48 DDPC_SDA_PCH GPP_E21/DPPC_CTRLDATA
disconnect DDC to Titan Ridge (Roger 5/5) CP4

GPP_E22/DPPD_CTRLCLK
CN4
GPP_E23/DPPD_CTRLDATA
CR26
GPP_H16/DDPF_CTRLCLK
CP26
GPP_H17/DDPF_CTRLDATA
BGA1528P
PDG#543016 DDI1 mapping DDPB

DDI2 mapping DDPC
HDMI +VCCIO
DDI2_0 Lane2
2
R0301
DDI2_1 Lane1 24.9Ohm

1%
<Variant Name>
1
DDI2_2 Lane0
Project Name Rev
EDP_COMP
UX432 R1.0
DDI2_3 CLK COMPENSATION PU FOR DP
Title : CPU_DISPLA
Y
DDPC I2C Page. 147 Size

Dept.: Engineer:
Custom
LPDDR3 Non-Interleaved
U0301B
14 M_A_DQ[15:0] LPDDR3/DDR4
U0301C
IL/NIL LPDDR3/DDR4 14 M_A_DQ[31:16]
IL/NIL
A26 V32 J22 AF28
DDR0_DQ_0/DDR0_DQ_0 DDR0_CKN_0/DDR0_CKN_0 M_A_DIM0_CK_DDR0_DN 13,14 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKN_0/DDR1_CKN_0 M_B_DIM0_CK_DDR0_DN 13,15
M_A_DQ0 D26 V31 M_A_DQ16 H25 AF29
DDR0_DQ_1/DDR0_DQ_1 DDR0_CKP_0/DDR0_CKP_0 M_A_DIM0_CK_DDR0_DP 13,14 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKP_0/DDR1_CKP_0 M_B_DIM0_CK_DDR0_DP 13,15
M_A_DQ1 D28 T32 M_A_DQ17 G22 AE28
DDR0_DQ_2/DDR0_DQ_2 DDR0_CKN_1/DDR0_CKN_1 M_A_DIM0_CK_DDR1_DN 13,14 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKN_1/DDR1_CKN_1 M_B_DIM0_CK_DDR1_DN 13,15
M_A_DQ2 C28 T31 M_A_DQ18 H22 AE29
DDR0_DQ_3/DDR0_DQ_3 DDR0_CKP_1/DDR0_CKP_1 M_A_DIM0_CK_DDR1_DP 13,14 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKP_1/DDR1_CKP_1 M_B_DIM0_CK_DDR1_DP 13,15
M_A_DQ3 B26 M_A_DQ19 F25
DDR0_DQ_4/DDR0_DQ_4 DDR1_DQ_4/DDR0_DQ_20
M_A_DQ4 C26 U36 M_A_DQ20 J25 T28
DDR0_DQ_5/DDR0_DQ_5 DDR0_CKE_0/DDR0_CKE_0 M_A_DIM0_CKE0 13,14 DDR1_DQ_5/DDR0_DQ_21 DDR1_CKE_0/DDR1_CKE_0 M_B_DIM0_CKE0 13,15
M_A_DQ5 B28 U37 M_A_DQ21 G25 T29
DDR0_DQ_6/DDR0_DQ_6 DDR0_CKE_1/DDR0_CKE_1 M_A_DIM0_CKE1 13,14 DDR1_DQ_6/DDR0_DQ_22 DDR1_CKE_1/DDR1_CKE_1 M_B_DIM0_CKE1 13,15
M_A_DQ6 A28 U34 M_A_DQ22 F22 V28 M_B_DIM0_CKE1
DDR0_DQ_7/DDR0_DQ_7 DDR0_CKE_2/NC M_A_DIM0_CKE2 13,14 DDR1_DQ_7/DDR0_DQ_23 DDR1_CKE_2/NC M_B_DIM0_CKE2 13,15
M_A_DQ7 B30 U35 M_A_DQ23 D22 V29 M_B_DIM0_CKE2
DDR0_DQ_8/DDR0_DQ_8 DDR0_CKE_3/NC M_A_DIM0_CKE3 13,14 DDR1_DQ_8/DDR0_DQ_24 DDR1_CKE_3/NC M_B_DIM0_CKE3 13,15
M_A_DQ8 D30 M_A_DQ24 C22 M_B_DIM0_CKE3
DDR0_DQ_9/DDR0_DQ_9 DDR1_DQ_9/DDR0_DQ_25
M_A_DQ9 B33 AE32 M_A_DQ25 C24 AL37
DDR0_DQ_10/DDR0_DQ_10 DDR0_CS#_0/DDR0_CS#_0 M_A_DIM0_CS0# 13,14 DDR1_DQ_10/DDR0_DQ_26 DDR1_CS#_0/DDR1_CS#_0 M_B_DIM0_CS0# 13,15
M_A_DQ10 D32 AF32 M_A_DQ26 D24 AL35
DDR0_DQ_11/DDR0_DQ_11 DDR0_CS#_1/DDR0_CS#_1 M_A_DIM0_CS1# 13,14 DDR1_DQ_11/DDR0_DQ_27 DDR1_CS#_1/DDR1_CS#_1 M_B_DIM0_CS1# 13,15
M_A_DQ11 A30 AE31 M_A_DQ27 A22 AL36
DDR0_DQ_12/DDR0_DQ_12 DDR0_ODT_0/DDR0_ODT_0 M_A_DIM0_ODT0 13,14 DDR1_DQ_12/DDR0_DQ_28 DDR1_ODT_0/DDR1_ODT_0 M_B_DIM0_ODT0 13,15
M_A_DQ12 C30 AF31 M_A_DQ28 B22 AL34
DDR0_DQ_13/DDR0_DQ_13 NC/DDR0_ODT_1 DDR1_DQ_13/DDR0_DQ_29 NC/DDR1_ODT_1
M_A_DQ13 B32 M_A_DQ29 A24 AG36
DDR0_DQ_14/DDR0_DQ_14 DDR1_DQ_14/DDR0_DQ_30 DDR1_CAB_9/DDR1_MA_0 MEM_CAB_2<9> 13,15
M_A_DQ14 C32 AC37 M_A_DQ30 B24 AG35
14 M_A_DQ[47:32] DDR0_DQ_15/DDR0_DQ_15 DDR0_CAB_9/DDR0_MA_0 MEM_CAA_2<9> 13,14 14 M_A_DQ[63:48] DDR1_DQ_15/DDR0_DQ_31 DDR1_CAB_8/DDR1_MA_1 MEM_CAB_2<8> 13,15
M_A_DQ15 H37 AC36 M_A_DQ31 G31 AF34
DDR0_DQ_16/DDR0_DQ_32 DDR0_CAB_8/DDR0_MA_1 MEM_CAA_2<8> 13,14 DDR1_DQ_16/DDR0_DQ_48 DDR1_CAB_5/DDR1_MA_2 MEM_CAB_2<5> 13,15
M_A_DQ32 H34 AC34 M_A_DQ48 G32 AG37
DDR0_DQ_17/DDR0_DQ_33 DDR0_CAB_5/DDR0_MA_2 MEM_CAA_2<5> 13,14 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_MA_3
M_A_DQ33 K34 AC35 M_A_DQ49 H29 AE35
DDR0_DQ_18/DDR0_DQ_34 NC/DDR0_MA_3 DDR1_DQ_18/DDR0_DQ_50 NC/DDR1_MA_4
M_A_DQ34 K35 AA35 M_A_DQ50 H28 AF35
DDR0_DQ_19/DDR0_DQ_35 NC/DDR0_MA_4 DDR1_DQ_19/DDR0_DQ_51 DDR1_CAA_0/DDR1_MA_5 MEM_CAB_1<0> 13,15
M_A_DQ35 H36 AB35 M_A_DQ51 G28 AE37
DDR0_DQ_20/DDR0_DQ_36 DDR0_CAA_0/DDR0_MA_5 MEM_CAA_1<0> 13,14 DDR1_DQ_20/DDR0_DQ_52 DDR1_CAA_2/DDR1_MA_6 MEM_CAB_1<2> 13,15
M_A_DQ36 H35 AA37 M_A_DQ52 G29 AC29
M_A_DQ37 K36 AA36 M_A_DQ53 H31 AE36
M_A_DQ38 K37 AB34 M_A_DQ54 H32 AB29
M_A_DQ39 N36 W36 M_A_DQ55 L31 AG34
DDR0_DQ_24/DDR0_DQ_40 DDR0_CAA_1/DDR0_MA_9 MEM_CAA_1<1> 13,14 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_7/DDR1_MA_10 MEM_CAB_2<7> 13,15
M_A_DQ40 N34 Y31 M_A_DQ56 L32 AC28
DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_7/DDR0_MA_10 MEM_CAA_2<7> 13,14 DDR1_DQ_25/DDR0_DQ_57 DDR1_CAA_7/DDR1_MA_11 MEM_CAB_1<7> 13,15
M_A_DQ41 R37 W34 M_A_DQ57 N29 AB28
M_A_DQ42 R34 AA34 M_A_DQ58 N28 AK35
DDR0_DQ_27/DDR0_DQ_43 DDR0_CAA_6/DDR0_MA_12 MEM_CAA_1<6> 13,14 DDR1_DQ_27/DDR0_DQ_59 DDR1_CAB_0/DDR1_MA_13 MEM_CAB_2<0> 13,15
M_A_DQ43 N37 AC32 M_A_DQ59 L28
DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_0/DDR0_MA_13 MEM_CAA_2<0> 13,14 DDR1_DQ_28/DDR0_DQ_60
M_A_DQ44 N35 M_A_DQ60 L29 AJ35
DDR0_DQ_29/DDR0_DQ_45 DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_2/DDR1_MA_14 MEM_CAB_2<2> 13,15
M_A_DQ45 R36 AC31 M_A_DQ61 N31 AK34
DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_2/DDR0_MA_14 MEM_CAA_2<2> 13,14 DDR1_DQ_30/DDR0_DQ_62 DDR1_CAB_1/DDR1_MA_15 MEM_CAB_2<1> 13,15
M_A_DQ46 R35 AB32 M_A_DQ62 N32 AJ34
15 M_B_DQ[15:0] DDR0_DQ_31/DDR0_DQ_47 DDR0_CAB_1/DDR0_MA_15 MEM_CAA_2<1> 13,14 15 M_B_DQ[31:16] DDR1_DQ_31/DDR0_DQ_63 DDR1_CAB_3/DDR1_MA_16 MEM_CAB_2<3> 13,15
M_A_DQ47 AN35 Y32 M_A_DQ63 AJ29
DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_3/DDR0_MA_16 MEM_CAA_2<3> 13,14 DDR1_DQ_32/DDR1_DQ_16
M_B_DQ0 AN34 M_B_DQ16 AJ30 AJ37
DDR0_DQ_33/DDR1_DQ_1 DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_4/DDR1_BA_0 MEM_CAB_2<4> 13,15
M_B_DQ1 AR35 W32 M_B_DQ17 AM32 AJ36
DDR0_DQ_34/DDR1_DQ_2 DDR0_CAB_4/DDR0_BA_0 MEM_CAA_2<4> 13,14 DDR1_DQ_34/DDR1_DQ_18 DDR1_CAB_6/DDR1_BA_1 MEM_CAB_2<6> 13,15
M_B_DQ2 AR34 AB31 M_B_DQ18 AM31 W29
DDR0_DQ_35/DDR1_DQ_3 DDR0_CAB_6/DDR0_BA_1 MEM_CAA_2<6> 13,14 DDR1_DQ_35/DDR1_DQ_19 DDR1_CAA_5/DDR1_BG_0 MEM_CAB_1<5> 13,15
M_B_DQ3 AN37 V34 M_B_DQ19 AM30
DDR0_DQ_36/DDR1_DQ_4 DDR0_CAA_5/DDR0_BG_0 MEM_CAA_1<5> 13,14 DDR1_DQ_36/DDR1_DQ_20
M_B_DQ4 AN36 M_B_DQ20 AM29 Y28
DDR0_DQ_37/DDR1_DQ_5 DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_9/DDR1_BG_1 MEM_CAB_1<9> 13,15
M_B_DQ5 AR36 V35 M_B_DQ21 AJ31 W28
DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_8/DDR0_ACT# MEM_CAA_1<8> 13,14 DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_8/DDR1_ACT# MEM_CAB_1<8> 13,15
M_B_DQ6 AR37 W35 M_B_DQ22 AJ32
DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_9/DDR0_BG_1 MEM_CAA_1<9> 13,14 DDR1_DQ_39/DDR1_DQ_23 IL/NIL
M_B_DQ7 AU35 M_B_DQ23 AR31 H24
DDR0_DQ_40/DDR1_DQ_8 IL/NIL DDR1_DQ_40/DDR1_DQ_24 DDR1_DQSN_0/DDR0_DQSN_2 M_A_DQS_DN2 14
M_B_DQ8 AU34 C27 M_B_DQ24 AR32 G24 M_A_DQS_DN2
DDR0_DQ_41/DDR1_DQ_9 DDR0_DQSN_0/DDR0_DQSN_0 M_A_DQS_DN0 14 DDR1_DQ_41/DDR1_DQ_25 DDR1_DQSP_0/DDR0_DQSP_2 M_A_DQS_DP2 14
M_B_DQ9 AW35 D27 M_A_DQS_DN0 M_B_DQ25 AV30 C23 M_A_DQS_DP2
DDR0_DQ_42/DDR1_DQ_10 DDR0_DQSP_0/DDR0_DQSP_0 M_A_DQS_DP0 14 DDR1_DQ_42/DDR1_DQ_26 DDR1_DQSN_1/DDR0_DQSN_3 M_A_DQS_DN3 14
M_B_DQ10 AW34 D31 M_A_DQS_DP0 M_B_DQ26 AV29 D23 M_A_DQS_DN3
M_B_DQ11 AU37 C31 M_A_DQS_DN1 M_B_DQ27 AR30 G30 M_A_DQS_DP3
M_B_DQ12 AU36 J35 M_A_DQS_DP1 M_B_DQ28 AR29 H30 M_A_DQS_DN6
M_B_DQ13 AW36 J34 M_A_DQS_DN4 M_B_DQ29 AV32 L30 M_A_DQS_DP6
M_B_DQ14 AW37 P34 M_A_DQS_DP4 M_B_DQ30 AV31 N30 M_A_DQS_DN7
15 M_B_DQ[47:32] DDR0_DQ_47/DDR1_DQ_15 DDR0_DQSN_3/DDR0_DQSN_5 M_A_DQS_DN5 14 15 M_B_DQ[63:48] DDR1_DQ_47/DDR1_DQ_31 DDR1_DQSP_3/DDR0_DQSP_7 M_A_DQS_DP7 14
M_B_DQ15 BA35 P35 M_A_DQS_DN5 M_B_DQ31 BA32 AL31 M_A_DQS_DP7
DDR0_DQ_48/DDR1_DQ_32 DDR0_DQSP_3/DDR0_DQSP_5 M_A_DQS_DP5 14 DDR1_DQ_48/DDR1_DQ_48 DDR1_DQSN_4/DDR1_DQSN_2 M_B_DQS_DN2 15
M_B_DQ32 BA34 AP35 M_A_DQS_DP5 M_B_DQ48 BA31 AL30 M_B_DQS_DN2
DDR0_DQ_49/DDR1_DQ_33 DDR0_DQSN_4/DDR1_DQSN_0 M_B_DQS_DN0 15 DDR1_DQ_49/DDR1_DQ_49 DDR1_DQSP_4/DDR1_DQSP_2 M_B_DQS_DP2 15
M_B_DQ33 BC35 AP34 M_B_DQS_DN0 M_B_DQ49 BD31 AU31 M_B_DQS_DP2
DDR0_DQ_50/DDR1_DQ_34 DDR0_DQSP_4/DDR1_DQSP_0 M_B_DQS_DP0 15 DDR1_DQ_50/DDR1_DQ_50 DDR1_DQSN_5/DDR1_DQSN_3 M_B_DQS_DN3 15
M_B_DQ34 BC34 AV34 M_B_DQS_DP0 M_B_DQ50 BD32 AU30 M_B_DQS_DN3
M_B_DQ35 BA37 AV35 M_B_DQS_DN1 M_B_DQ51 BA30 BC31 M_B_DQS_DP3
M_B_DQ36 BA36 BB35 M_B_DQS_DP1 M_B_DQ52 BA29 BC30 M_B_DQS_DN6
M_B_DQ37 BC36 BB34 M_B_DQS_DN4 M_B_DQ53 BD29 BH31 M_B_DQS_DP6
M_B_DQ38 BC37 BF34 M_B_DQS_DP4 M_B_DQ54 BD30 BH30 M_B_DQS_DN7
M_B_DQ39 BE35 BF35 M_B_DQS_DN5 M_B_DQ55 BG31 M_B_DQS_DP7
DDR0_DQ_56/DDR1_DQ_40 DDR0_DQSP_7/DDR1_DQSP_5 M_B_DQS_DP5 15 DDR1_DQ_56/DDR1_DQ_56
M_B_DQ40 BE34 M_B_DQS_DP5 M_B_DQ56 BG32 Y29 +1.2V
DDR0_DQ_57/DDR1_DQ_41 DDR1_DQ_57/DDR1_DQ_57 NC/DDR1_ALERT# GND
M_B_DQ41 BG35 W37 BK32 AE34
M_B_DQ42 BG34
DDR0_DQ_58/DDR1_DQ_42 NC/DDR0_ALERT#
W31
GND UX432 Modify check with intel
M_B_DQ57
M_B_DQ58 BK31
DDR1_DQ_58/DDR1_DQ_58 NC/DDR1_PAR
BU31 R0402 1 2 1%
DDR0_DQ_59/DDR1_DQ_43 NC/DDR0_PAR DDR1_DQ_59/DDR1_DQ_59 DRAM_RESET#
M_B_DQ43 BE37 F36 M_B_DQ59 BG29 470Ohm
DDR0_DQ_60/DDR1_DQ_44 DDR_VREF_CA +V_DDR_CA_VREF01_DIMM 19 DDR1_DQ_60/DDR1_DQ_60
M_B_DQ44 BE36 D35 M_B_DQ60 BG30 BN28
DDR0_DQ_61/DDR1_DQ_45 DDR0_VREF_DQ_0 +V_DDR_WR_VREF01_DIMM 19 DDR1_DQ_61/DDR1_DQ_61 DDR_COMP_0 R0.1
M_B_DQ45 BG36 D37 M_B_DQ61 BK30 BN27 SM_RCOMP_0 0328
DDR0_DQ_62/DDR1_DQ_46 DDR0_VREF_DQ_1 DDR1_DQ_62/DDR1_DQ_62 DDR_COMP_1
M_B_DQ46 BG37 E36 M_B_DQ62 BK29 BN29 SM_RCOMP_1 follow WHL-U LPDDR3 CRB design,
DDR0_DQ_63/DDR1_DQ_47 DDR1_VREF_DQ +V_DDR_WR_VREF02_DIMM 19 DDR1_DQ_63/DDR1_DQ_63 DDR_COMP_2 DRAM_RESET# add 470ohm pill-high to +1.2V (confirmed with intel)
M_B_DQ47 C35 M_B_DQ63 SM_RCOMP_2
DDR_VTT_CNTL DDR_VTT_CTRL 14
BGA1528P
BGA1528P
LPDDR3 COMPENSATION SIGNALS
R0403 1 2 200OHM 1%
SM_RCOMP_0 nbs_r0201_h10_000s
R0401 1 2 80.6Ohm 1%
R0406 1 2 162Ohm 1%
GND
2nd source:
200 Ohm >>10G211200017030(YAGEO), 10101-00081000(TA-I)
162 Ohm>>10101-00951000(TA-I), 10101-00953000(YAGEO)
<Variant Name>
Project Name Rev
UX432 R1.0
Title : CPU_LPDDR3
Size
C
Dept.: NB1RD2EE2 Engineer: Tony1_chang
Main Board
U0301E
CH37 CK14
28 SPI_CLK_SPI SPI0_CLK GPP_C0/SMBCLK TO XDP & DIM_SPD
CF37 CH15 SMB_CK
28 SPI_SO_SPI SPI0_MISO GPP_C1/SMBDATA
CF36 CJ15 SMB_DATA
28 SPI_SI_SPI SPI0_MOSI GPP_C2/SMBALERT#
CF34
28 PCH_SPI_DQ2 SPI0_IO2
CG34 CH14
28 PCH_SPI_DQ3 SPI0_IO3 GPP_C3/SML0CLK
CG36 CF15 SML0_CK
28 SPI_CS#0_SPI SPI0_CS0# GPP_C4/SML0DATA
CG35 CG15 SML0_DATA
SPI0_CS1# GPP_C5/SML0ALERT#
CH34 GPP_C5
SPI0_CS2#
CN15
GPP_C6/SML1CLK
CM15 SML1_CK
GPP_C7/SML1DATA
CC34 SML1_DATA
GPP_B23/SML1ALERT#/PCHHOT#
CF20 SML1ALERT#
GPP_D1/SPI1_CLK/BK1/SBK1
CG22
GPP_D2/SPI1_MISO_IO1/BK2/SBK2
CF22
GPP_D3/SPI1_MOSI_IO0/BK3/SBK3
CG23 CA29
GPP_D21/SPI1_IO2 GPP_A1/LAD0/ESPI_IO0 LPC_AD0 30,44
CH23 BY29
GPP_D22/SPI1_IO3 GPP_A2/LAD1/ESPI_IO1 LPC_AD1 30,44
CG20 BY27
GPP_D0/SPI1_CS0#/BK0/SBK0 GPP_A3/LAD2/ESPI_IO2 LPC_AD2 30,44
BV27
GPP_A4/LAD3/ESPI_IO3 LPC_AD3 30,44 R0.1
CA28 0417
GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# 30,44
CA27 T0504 1 R0512 0 OHM => 33 OHM, follow UX432FDX
GPP_A14/SUS_STAT#/ESPI_RESET#
CH7 SUS_STAT#
CL_CLK R0512 33Ohm
CH8 BV32 1 2
CL_DATA GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_KBCPCI_PCH 30
CH9 BV30 CLK_KBCPCI_PCH_X1
CL_RST# GPP_A10/CLKOUT_LPC1 CLK_DEBUG 44
BY30
GPP_A8/CLKRUN# PM_CLKRUN# 30
PM_CLKRUN#
BV29
30 RC_IN# GPP_A0/RCIN#/TIME_SYNC1
BV28
30 INT_SERIRQ GPP_A6/SERIRQ
INT_SERIRQ
BGA1528P
For Debug Code Output +3VSUS

+3VS
R0522 1 2 8.2KOhm
hh_r0201_h12 PM_CLKRUN#
2
R0519 1
1% 2 10KOhm R0501 R0502
hh_r0201_h12 INT_SERIRQ 2.2KOhm 2.2KOhm
hh_r0201_h12 hh_r0201_h12
1
UX305UA CRB 1.1 P.20 150K PU ok 0318 change to 100K 0324
SMB_DATA 44
+3VSUS R1.1-5 SMB_DATA
SMB_CK 44
R0508 1 2 100KOhm SMB_CK
SML1ALERT#
R0503 1 2 2.2KOhm hh_r0201_h12
R0504 1 2 2.2KOhm hh_r0201_h12 SML1_CK
SML1_DATA
R0505 1 2 2.2KOhm hh_r0201_h12

TP for Boundary Scan Test
R0506 1 2 2.2KOhm hh_r0201_h12 SML0_CK
SML0_DATA
R0.1 R0.1
R0507 1 2 100KOhm 0221 0409
Add R0507 pul-high SPI_SI_SPI (follow UX432_0206)。 Remove T0503 for layout purpose.
SPI_SI_SPI
UX391RA add Transport Layer Security (TLS) Confidentiality
+3VA_DSW
UX305UA remove 0429
2
R0509
0Ohm
hh_r0402
1
@
GPP_C5
1
R0510
20KOhm
@
2
GPP_C5: weak internal pull down GPP_C2: weak internal pull down
<Variant Name>
PU ESPI BUS PU Enable Project Name Rev
Disable Intel ME TLS ipher suite UX432 R1.0

PD LPC is selected for EC (Default) PD ( no confodentiality)(Default)
Title : CPU_LPC,SPI,SMB,CLINK
Size
Dept.: Engineer:
Custom
Check SVID PDG1.2 P.252 topology is ok 0324 check this topology with power team!!
Imax 31A +VCCGT C0672 C0615 C0623 close to CPU 1203
Imax = 70A +VCCGT
+1.2V +VCCIO
1300 mils
+VCCCORE +VCCCORE
U0301N
2800 mils ES1=+VCCGT
+1.05V_VCCST Imax = 3.6A
U0301M Imax = 3.3A AK24
AD36
VCCIO1
AK26 144 mils
ES2=+VCCCORE
R1.0-3 132 mils VDDQ1 VCCIO2
A5 D15 AH32 AL24
VCCGT1 VCCGT36 VDDQ2 VCCIO3
U0301L A6 D17 AH36 AL25
VCCGT2 VCCGT37 VDDQ3 VCCIO4
AN9 AW24 A8 D18 AM36 AL26
2
AN10
VCCCORE5 VCCCORE35
AW25 A11
VCCGT3 VCCGT38
D20 AN32
VDDQ4 VCCIO5
AL27
UX432 Del +VCC_EDRAM_EOPIO
AN24
VCCCORE1 VCCCORE36
AW26 SVID DATA 100Ohm
check PDG 1.2 R.252 0324
R0.1
0222 A12
VCCGT4 VCCGT39
E4 AW32
VDDQ5 VCCIO6
AM25
UX432 Del +VCC_EDRAM_EOPIO
VCCCORE2 VCCCORE37 ES1/ES2 co-lay VCCGT5 VCCGT40 VDDQ6 VCCIO7
AN26 AW27 R0606 A14 F5 AY36 AM27
VCCCORE3 VCCCORE38 ES1 +VCCGT ES2 +VCCORE VCCGT6 VCCGT41 VDDQ7 VCCIO8
AN27 AY24 A15 F6 BE32 BH24
VCCCORE4 VCCCORE44 (Follow ux432ud) VCCGT7 VCCGT42 VDDQ8 VCCIO9
1
AP2 AY26 A17 F7 BH36 BH25
VCCCORE6 VCCCORE45 VCCGT8 VCCGT43 VDDQ9 VCCIO10
AP9 BA5 A18 F8 R32 BH26
VCCCORE9 VCCCORE48 VCCGT9 VCCGT44 VDDQ10 VCCIO11
AP24 BA7 A20 F11 Y36 BH27
VCCCORE7 VCCCORE49 P_SVID_DATA_50OHM_X2 80 VCCGT10 VCCGT45 VDDQ11 VCCIO12
AP26 BA8 P_SVID_DATA_X3 AA9 F14 BJ24
VCCCORE8 VCCCORE50 VCCCORE75 VCCGT46 VCCIO13
AR5 BA25 +VCCCORE_WHL AB2 F17 BJ26
AR6 BA27 AB8 F20 C0602 close to U0301 PIN BP11 +1.05V_VCCST BP16
AR7 BB2 AB9 G11 BC28 BP18
VCCCORE15 VCCCORE51 VCCCORE78 VCCGT49 RSVD6 VCCIO16
AR8 BB26 AB10 G12 R0.1
AR10
VCCCORE16 VCCCORE52
BC5 AC8
VCCCORE79 VCCGT50
G14 0314 10mils Imax = 0.06A BP11 BG8
+VCCSA
UX432 DEL +VCC_EDRAM_1P8
Check P.80 need pull down 100 to ground 0319
C0602 1UF/6.3V
VCCCORE10 VCCCORE56 VCCCORE80 VCCGT51 C0602 0402=>0201, VCCST1 VCCSA2
AR25 BC6 AD9 G15 1 2 hh_c0201_h14 BP2 BG10
VCCCORE11 VCCCORE57 VCCCORE81 VCCGT52 for layout placement purpose VCCST2 VCCSA1 Imax = 6 A
AR27 BC7 AE8 G17 +VCCSTG BH9
VCCCORE12 VCCCORE58 VCCCORE82 VCCGT53 VCCSA3
AT9 BC9 AE9 G18 BJ8
AT24
VCCCORE19 VCCCORE59
BC10 AE10
VCCCORE83 VCCGT54
G20
+VCCPLL_OC 10mils Imax = 0.02A BG1
VCCSA5
BJ9 250 mils
VCCCORE17 VCCCORE53 VCCCORE84 VCCGT55 VCCSTG1 VCCSA6
AT26 BC26 AF2 H5 BG2 BJ10
VCCCORE18 VCCCORE54 VCCCORE85 VCCGT56 VCCSTG2 VCCSA4
AU5 BC27 AF8 H6 BK8
VCCCORE24 VCCCORE55 VCCCORE86 VCCGT57 20 mils Imax = 0.12A VCCSA9
AU6 BD5 AF10 H7 BL27 BK25
AU7
VCCCORE25 VCCCORE63
BD8 SVID CLOCK AG8
VCCCORE87 VCCGT58
H8 BM26
VCCPLL_OC1 VCCSA7
BK27
VCCCORE26 VCCCORE64 VCCCORE88 VCCGT59 VCCPLL_OC2 VCCSA8
AU8 BD10 AG9 H11 +1.05V_VCCPLL BL8
VCCCORE27 VCCCORE60 VCCCORE89 VCCGT60 Imax = 0.13A VCCSA13
AU9 BD25 AH9 H12 BR11 BL9
1
VCCCORE28 VCCCORE61 P_SVID_CLK_50OHM_X2 80 VCCCORE90 VCCGT61
C0623 20 mils VCCPLL1 VCCSA14
AU24 BD27 P_SVID_CLK_X3 AJ8 H14 1UF/6.3V BT11 BL10 U0301O
VCCCORE20 VCCCORE62 VCCCORE91 VCCGT62 VCCPLL2 VCCSA10
AU25 BE9 AJ10 H15 hh_c0201_h14 BL24
VCCCORE21 VCCCORE69 VCCCORE92 VCCGT63 VCCSA11
2
AU26 BE24 AK2 H17 BL26 K12 AA24
VCCCORE22 VCCCORE65 VCCCORE93 VCCGT64 VCCSA12 RSVD42 RSVD60
AU27 BE25 AK9 H18 BM24 K14 AA26
1
check PDG 1.2 R.252 0324 C0620 C0615
AV2 BE26 R0.1 AL8 H20 C0623 close to U0301 BL27 BM26 0.1UF/6.3V 1UF/6.3V BN25 K15 AB25
AV5 BE27 0308 +1.05V_VCCST AL9 J7 hh_c0201 hh_c0201_h14 K17 AC24
VCCCORE32 VCCCORE68 change vcc/vss sense net name, VCCCORE96 VCCGT67 RSVD45 RSVD63
2
AV7 BF2 AL10 J8 BP28 K18 AC25
VCCCORE33 VCCCORE70 follow pwr new circuit. VCCCORE97 VCCGT68 VCCIO_SENSE RSVD46 RSVD64
AV10 BF9 AM8 J11 R0.1 BP29 K20 AC26
VCCCORE29 VCCCORE73 0308 VCCCORE98 VCCGT69 VSSIO_SENSE RSVD47 RSVD65
AV27 BF24 change vcc/vss sense net name, B3 J14 0314 L25 AD24
VCCCORE31 VCCCORE71 VCCGT11 VCCGT70 C0615 0402=>0201, RSVD48 RSVD66
AW5 BF26 follow pwr(2100) new circuit. B4 J17 BE7 M24 AD26
2
VCCCORE39 VCCCORE72 VCCGT12 VCCGT71 for layout placement purpose VSSSA_SENSE P_VCCSA_VSSSENSE_50OHM 80R0.1 RSVD49 RSVD67
AW6 BG27 B6 J20 BG7 0308 M26
SVID ALERT 0402 change to 0201 0105
R0605
VCCCORE40 VCCCORE74 VCCGT13 VCCGT72 VCCSA_SENSE P_VCCSA_VCCSENSE_50OHM 80change vcc/vss sense net name, RSVD50
AW7 56Ohm B8 K2 P24 V25
VCCCORE41 VCCGT14 VCCGT73 follow pwr new circuit. RSVD51 RSVD68
AW8 AN6 B11 K11 C0615 C0620 close to U0301 PIN BR11 BT11 P26 T25
VCCCORE42 VCC_SENSE P_VCCCORE_VCCSENSE_50OHM 80 VCCGT15 VCCGT74 BGA1528P 0308 RSVD52 RSVD69
AW9 AN5 hh_r0201_h12 B14 L7 change vcc/vss sense net name, R24
VCCCORE43 VSS_SENSE P_VCCCORE_VSSSENSE_50OHM 80 VCCGT16 VCCGT75 RSVD53
1
AW10 check PDG 1.2 R.252 0324 B17 L8 follow pwr(2100) new circuit. R25
VCCCORE34 VCCGT17 VCCGT76 RSVD54
AA3 B20 L10 R26
VIDALERT# VCCGT18 VCCGT77 RSVD55
BB9 1 2 C2 M9
WHL U42 E1 and E2 colay
P_SVID_ALERT#_X3 R0604 220Ohm
RSVD1 P_SVID_ALERT#_50OHM_X2 80 VCCGT19 VCCGT78
BC24 AA1 P_SVID_ALERT#_X3 C3 N7 W25
RSVD2 VIDSCK VCCGT20 VCCGT79 RSVD56
AY9 P_SVID_CLK_X3 RES 220 OHM 1/16W (0402) 1% C6 N8 V24
RSVD3 VCCGT21 VCCGT80 RSVD57
BB24
RSVD4 VIDSOUT
AA2
P_SVID_DATA_X3
C7
C8
VCCGT22
VCCGT23
VCCGT81
VCCGT82
N9
N10 Rshunt need to be less than 0.2 mOhm Y25
RSVD58
Y3 +VCCSTG C11 P2 Y24
RSVD5 VCCGT24 VCCGT83 RSVD59
C12 P8 R0.1
VCCGT25 VCCGT84
BG3 C14 R9 0222
VCCSTG1_1 Imax = 0.02A 10mils VCCGT26 VCCGT85 ES1/ES2 co-lay
C15 T8
VCCGT27 VCCGT86 ES1 +VCCGT ES2 +VCCORE +VCCCORE
C17 T9 +VCCCORE_WHL
VCCGT28 VCCGT87 (Follow ux432ud)
C18 T10 R0.1
BGA1528P VCCGT29 VCCGT88 BGA1528P
C20 U8 0222
VCCGT30 VCCGT89 ES1/ES2 co-lay
D4 U10
VCCGT31 VCCGT90 ES1 +VCCGT ES2 +VCCORE
D7 V2
VCCGT32 VCCCORE100 (Follow ux432ud)
D11 V9 +VCCCORE_WHL 0312
+VCCSTG VCCGT33 VCCGT91
D12 W8 Remove ES1/ES2 colay circuit, ES2 only.
VCCGT34 VCCGT92
D14 W9
VCCGT35 VCCGT93
Y10 Y8
VCCCORE99 VCCCORE101
E3
1
VCCGT_SENSE P_VCCGT_VCCSENSE_50OHM 80R0.1
D2 0308
C0624 C0624 place close to U0301 BG3 VSSGT_SENSE P_VCCGT_VSSSENSE_50OHM 80change vcc/vss sense net name,
Imax = 0.02A 1UF/6.3V follow pwr new circuit.
2
hh_c0201_h14 0308
BGA1528P
change vcc/vss sense net name,
follow pwr(2100) new circuit.
+VCCGT +1.2V
132 mils
CPU - VCCGT DECAPS- Underneath the package CAP above 10UF move to PWR page
31A 3.3A
CPU - VDDQ DECAPS- Place close to the package
+VCCGT DeCap
1
C0618
1
C0628 C0629 C0630 C0631 C0642 C0644 C0647 C0649
1
C0662
1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V CPU Back Side 10UF/6.3V
hh_c0402_h28_pw
10UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V
hh_c0201_h14 hh_c0201_h14 hh_c0201_h14 hh_c0201_h14
0201 1uF/6.3V X5R h14 *8 hh_c0402_h28_pw hh_c0201_h14 hh_c0201_h14 hh_c0201_h14 hh_c0201_h14
2
2
2
2
0402 4.7uF/6.3V *10
+VDDQ DeCap
CPU Back Side
0201 1uF/6.3V X5R h14 *4
1
C0640 C0613 C0665 C0684 C0614 C0659
0.33mm 4.7UF *10
2
1UF/6.3V
hh_c0201_h14
1UF/6.3V
hh_c0201_h14
1UF/6.3V
hh_c0201_h14
1UF/6.3V
hh_c0201_h14
22UF/6.3V
hh_c0603_h39
22UF/6.3V
hh_c0603_h39
C0658
4.7UF/6.3V
C0660
4.7UF/6.3V
C0666
4.7UF/6.3V
C0608
4.7UF/6.3V
0402 10UF*2
0603 22uF/6.3V X5R h39 *2
1
2
2
R0.1
0221 @
C0634/C0636/C0648/C0650改為上件(follow UX432_0206)。
0314
+VCCGT 4.7UF/6.3V 11G232247525360(0.6mm) => 11203-0070F100(0.33mm), for layout placement purpose
C0656 C0601 C0604 C0607
2
4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V
HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2
1
+VCCST +1.05V_VCCST +VCCST +1.05V_VCCPLL
20 mils
20 mils 60 mA
120mA
C0603
2
4.7UF/6.3V
1
C0616
C0652 C0654 C0634 C0636 C0648 C0650 0.1UF/6.3V @
1
4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V hh_c0201 HH_C0402_H13_T0D2
2
HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2
1
C0616 change to 0.1uF follow KBL PDG 0222
CPU - VCCIO DECAPS- Place close to the package
+VCCIO
3.6A
CPU - VCCSA DECAPS- Underneath the package CAP above 10UF move to PWR page
+VCCIO DeCap
340 mils CPU Back Side
C0670 C0667 C0668 C0669
0201 1uF/6.3V X5R h14 * 4
2
+VCCSA 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V
+VCCSA DeCap HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 0402 4.7uF/6.3V X5R h13 * 4
1
CPU Back Side
6A 0201 1uF/6.3V X5R h14 *5
0402 10uF/6.3V X5R h28 *2
0402 4.7uF/6.3V *8 R0.1
0314
+VCCIO 4.7UF/6.3V 11G232247525360(0.6mm) => 11203-0070F100(0.33mm), for layout placement purpose
1
C0626 C0639
10UF/6.3V 10UF/6.3V
hh_c0402_h28_pw hh_c0402_h28_pw
1
C0619 C0605 C0621 C0627
1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V
hh_c0201_h14 hh_c0201_h14 hh_c0201_h14 hh_c0201_h14
2
1
1
C0651 C0633 C0653 C0635 C0637
1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V
hh_c0201_h14 hh_c0201_h14 hh_c0201_h14 hh_c0201_h14 hh_c0201_h14
2
C0609 C0610 C0611 C0612 C0632 C0622 C0617 C0625
2
4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V
HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2
1
Power Plane: R0.1
0314
+VCCSA 4.7UF/6.3V 11G232247525360(0.6mm) => 11203-0070F100(0.33mm), for layout placement purpose
+VCCCORE
+VCCSA System Agent power rail
+VCCGT Sliced graphics power rail
+1.05V_VCCPLL=+VCCST CPU PLL power rails

VCCSTG =1.05V IO power rail
+VCCPLL_OC=+1.2V CPU digital PLL power rails

CPU Memory power rail, voltage dependent on
+VDDQ_CPU=+1.2V memory technology
+VCCST Sustain voltage for processor in Standby modes
+VCCIO = 1.05V Voltage for the memory controller and shared cache
<Variant Name>
Project Name Rev
UX432 R1.0
Title : CPU_POEWR
Size
Dept.: Engineer:
E
+1.05V_VCCST UX3900UA add XDP debug schematic Main Board
CATERR:This signal indicates that the system has experienced a catastrophic error and cannot
continue to operate.
2
hh_r0201_h12
+1.05V_VCCST
XDP
R0801 +VCCSTG
49.9Ohm U0301D
1%
T0811
TPC26T_50 1 AA4 T6 R0803 1 2 51OHM
1
CATERR# PROC_TCK
CATERR# AR1 U6 XDP_TCLK_CPU XDP_TMS_CPU hh_r0201_h10
30 PECI_EC PECI PROC_TDI
PECI_EC Y4 Y5 XDP_TDI_CPU R0805 1 2 51OHM
PROCHOT# PROC_TDO
R0802 1KOhm H_PROCHOT_D# BJ1 T5 XDP_TDO_CPU XDP_TDI_CPU hh_r0201_h10
THRMTRIP# PROC_TMS
1 2 THERMTRIP# AB6 XDP_TMS_CPU
PROC_TRST#
T0803 1 U1 XDP_TRST_CPU#
BPM#_0
T0805 1 XDP_BPM0 U2 W6
BPM#_1 PCH_TCK
T0806 1 XDP_BPM1 U3 U5 PCH_JTAG_TCK R0817 1 2 51OHM
BPM#_2 PCH_TDI
T0807 1 XDP_BPM2 U4 W5 XDP_TDI_CPU PCH_JTAG_TCK hh_r0201_h10
BPM#_3 PCH_TDO
XDP_BPM3 P5 XDP_TDO_CPU
PCH_TMS @
Y6 XDP_TMS_CPU
PCH_TRST#
P6 XDP_TRST_CPU#
PCH_JTAGX
XDP_TCLK_CPU
CE9 W2
GPP_E3/CPU_GP0 PROC_PREQ#
CN3 W1 XDP_PREQ#
GPP_E7/CPU_GP1 PROC_PRDY#
CB34 XDP_PRDY#
GPP_B3/CPU_GP2
CC35
GPP_B4/CPU_GP3
BP27 +VCCSTG
PROC_POPIRCOMP
PROC_POPIRCOMP BW25
PCH_OPIRCOMP
PCH_OPIRCOMP L5
OPCE_RCOMP
N5
OPC_RCOMP
R0804 1 2 51OHM hh_r0201_h10
XDP_TDO_CPU
R0806 1 2 51OHM hh_r0201_h10
BGA1528P
2
hh_r0201_h12 hh_r0201_h12 XDP_TCLK_CPU
R0813 R0812
UX432 Del OPC_RCOMP BY ES1
49.9Ohm 49.9Ohm
1% 1%
UX432 Del OPCE_RCOMP ES1
1
For CFL U43e, Pins L5 and N5 are OPCE_RCOMP and
OPC_RCOMP respectively while in WHL, CNL SoCs these
pins are RSVD.
Whisky Lake Check
On Package Cache resistance Compensation

from processor: Refer to the appropriate platform
design guide for implementation details and values.
Unconnected for Processors without OPC. TP for Boundary Scan Test
1 T0808
No OPC Check remove 且R0811 R0810量測兩端為0V 0126 XDP_TDO_CPU
1 T0809
XDP_TMS_CPU
1 T0810
XDP_TRST_CPU#
CPU SIDEBAND SIGNALS +VCCSTG
1 T0802
XDP_TDI_CPU
1 T0812
Check merge 0118 XDP_TCLK_CPU
1
1KOhm
R0809
2
1 T0815
R0808
THRO_CPU# 30,80
+3VA_EC OD PCH_JTAG_TCK
1 2
IMVP8_VRHOT# 30,80
+5VS OD
2 1 SL0803
H_PROCHOT_D# H_PROCHOT_D#_R
0201 PWRLIMIT#_CPU 89
+5VS OD
499Ohm
hh_r0201_h10
1 T0801
XDP_PRDY# 1 T0804
XDP_PREQ#
New topology no prochot# decap. eds prochot pulse width 500us 0105
<Variant Name>
Project Name Rev
UX432 R1.0
Title : CPU_MISC,JT
AG,CLK
Size
Dept.: Engineer:
B
Main Board
U0301Q
1 T0905 T4 F37
CFG_0 RSVD_TP5
CFG0 F34
RSVD_TP4
R4 CP36
CFG_1 IST_TRIG
T3 CN36
CFG_2 RSVD_TP3
R3
CFG_3
CFG3 J4
CFG_4
CFG4 M4 BJ36
CFG_5 RSVD22
J3 BJ34
CFG_6 RSVD23
M3
CFG_7
R2 BK34
CFG_8 TP1
N2 BR18
CFG_9 TP3
R1
CFG_10
N1
CFG_11
J2
CFG_12
L2 BT9
CFG_13 RSVD24
J1 BT8
CFG_14 RSVD25
L1
CFG_15
BP8
RSVD26
L3 BP9
CFG_16 RSVD27
N3
CFG_18
L4 CR4
CFG_17 RSVD28
N4
CFG_19
CP3
RSVD29
CR3
RSVD30
AB5
CFG_RCOMP
CFG_RCOMP
W4
ITP_PMODE
ITP_PMODE
CG2
RSVD7
CG1
RSVD8
AT3
2
RSVD31
R0902 AU3
RSVD32
49.9Ohm
1% H4
RSVD9
hh_r0201_h12 H3
RSVD10
1
AN1
RSVD33
BV24 AN2
RSVD11 RSVD34
BV25
RSVD12
AN4
RSVD35
AN3
RSVD36
AL2
RSVD37 R1.1
AL1 0312
RSVD38
G3 Follow Intel David recommdation.
RSVD70
G4
UX432 Del LPM_ZVM_N BY ES1 RSVD71
AL4
RSVD39
AL3 R0906 1 2 0Ohm
RSVD40
BK36 BP34
RSVD13 TP1_1
BK35 BP36 1 T0901
RSVD14 TP2_2
BP35 TP2_2
TP2_3
W3
RSVD15
AM4 C34
RSVD16 RSVD72 UX432 Del R0903 ES1
AM3 A34
RSVD17 RSVD_TP1
B35
RSVD_TP2
CR35 1 T0902
RSVD41
RSVD41
A35
D34
RSVD18
AH26
UX432 Del LPM_ZVM_N BY ES1
RSVD19 RSVD73
AJ27 1
G2
RSVD74 UX432 Del MSM_N ES1 TPC26T_50 T0910
CFG3
RSVD20
G1 E1 R0905 1 @ 2 100KOhm TPC26T_50 1 T0911
RSVD21 SKTOCC# +1.05V_VCCST
ITP_PMODE
BGA1528P
CFG STRAPS
R0901 1KOhm
1 2
CFG4
1 0 NOTE
<Variant Name>
Project Name Rev

CFG4 DISABLE ENABLE eDP ENABLE
UX432 R1.0
Title : CPU_CFG,RSVD
Size
Dept.: Engineer:
Custom
+VCCCORE
4.7uF 0402 H=0.33 *18
CPU - VCC DECAPS- Underneath the package
CAP above 10UF move to PWR page
C1080 C1081 C1082 C1083 C1084 C1085
2
4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V
1
C1002 C1001 C1003 C1004 C1005 C1006
2
4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V
1
+VCCCORE DeCap
0201 1uF/6.3V X5R h14 *30
0402 4.7uF/6.3V X5R h13 * 18
C1007 C1008 C1009 C1086 C1087 C1088
2
4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V R0.1
HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 0314
1
+VCCCORE 4.7UF/6.3V 11G232247525360(0.6mm) => 11203-0070F100(0.33mm), for layout placement purpose
1
C1028 C1030 C1031 C1034 C1036 C1037 C1040 C1041 C1043 C1044
1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V
hh_c0201_h14 hh_c0201_h14 hh_c0201_h14 hh_c0201_h14 hh_c0201_h14 hh_c0201_h14 hh_c0201_h14 hh_c0201_h14 hh_c0201_h14 hh_c0201_h14
2
1
1
C1045 C1046 C1047 C1048 C1049 C1050 C1051 C1052 C1053 C1054
2
1
1
C1055 C1056 C1057 C1058 C1059 C1060 C1062 C1061 C1063 C1065
2
Project Name Rev
UX432 R1.0
Title : CPU_POWER_CAP
Size
B
+VTT +VTT +VTT
R1301 1 2 68Ohm 1% R1329 1 2 68Ohm 1% R1341 1 2 80.6Ohm 1%

4,14 MEM_CAA_1<0> 4,15 MEM_CAB_1<0> 4,14 M_A_DIM0_CS0#
R1302 1 2 68Ohm 1% R1322 1 2 68Ohm 1% R1342 1 2 80.6Ohm 1%
4,14 MEM_CAA_1<1> 4,15 MEM_CAB_1<1> 4,14 M_A_DIM0_CS1#
R1303 1 2 68Ohm 1% R1324 1 2 68Ohm 1% R1343 1 2 80.6Ohm 1%
4,14 MEM_CAA_1<2> 4,15 MEM_CAB_1<2> 4,15 M_B_DIM0_CS0#
R1304 1 2 68Ohm 1% R1326 1 2 68Ohm 1% R1344 1 2 80.6Ohm 1%
4,14 MEM_CAA_1<3> 4,15 MEM_CAB_1<3> 4,15 M_B_DIM0_CS1#
R1305 1 2 68Ohm 1% R1328 1 2 68Ohm 1% R1345 1 2 80.6Ohm 1%
4,14 MEM_CAA_1<4> 4,15 MEM_CAB_1<4> 4,14 M_A_DIM0_CKE0
R1306 1 2 68Ohm 1% R1340 1 2 68Ohm 1% R1346 1 2 80.6Ohm 1%
R1307 1 2 68Ohm 1% R1321 1 2 68Ohm 1% R1347 1 2 80.6Ohm 1%
R1308 1 2 68Ohm 1% R1323 1 2 68Ohm 1% R1348 1 2 80.6Ohm 1%
R1309 1 2 68Ohm 1% R1325 1 2 68Ohm 1% R1349 1 2 80.6Ohm 1%
4,14 MEM_CAA_1<8> 4,15 MEM_CAB_1<8> 4,15 M_B_DIM0_CKE0
R1310 1 2 68Ohm 1% R1327 1 2 68Ohm 1% R1350 1 2 80.6Ohm 1%
4,14 MEM_CAA_1<9> 4,15 MEM_CAB_1<9> 4,15 M_B_DIM0_CKE1
R1351 1 2 80.6Ohm 1%
4,15 M_B_DIM0_CKE2
R1352 1 2 80.6Ohm 1%
4,15 M_B_DIM0_CKE3
R1353 1 2 80.6Ohm 1%
4,14 M_A_DIM0_ODT0
R1319 1 2 68Ohm 1% R1335 1 2 68Ohm 1% R1354 1 2 80.6Ohm 1%
4,14 MEM_CAA_2<0> 4,15 MEM_CAB_2<0> 4,15 M_B_DIM0_ODT0
R1312 1 2 68Ohm 1% R1337 1 2 68Ohm 1%
4,14 MEM_CAA_2<1> 4,15 MEM_CAB_2<1>
R1314 1 2 68Ohm 1% R1331 1 2 68Ohm 1%
4,14 MEM_CAA_2<2> 4,15 MEM_CAB_2<2>
R1316 1 2 68Ohm 1% R1334 1 2 68Ohm 1%
4,14 MEM_CAA_2<3> 4,15 MEM_CAB_2<3>
R1318 1 2 68Ohm 1% R1336 1 2 68Ohm 1%
4,14 MEM_CAA_2<4> 4,15 MEM_CAB_2<4>
R1320 1 2 68Ohm 1% R1338 1 2 68Ohm 1%
4,14 MEM_CAA_2<5> 4,15 MEM_CAB_2<5>
R1311 1 2 68Ohm 1% R1339 1 2 68Ohm 1%
4,14 MEM_CAA_2<6> 4,15 MEM_CAB_2<6>
R1313 1 2 68Ohm 1% R1330 1 2 68Ohm 1% +VTT
4,14 MEM_CAA_2<7> 4,15 MEM_CAB_2<7>
R1315 1 2 68Ohm 1% R1332 1 2 68Ohm 1%
4,14 MEM_CAA_2<8> 4,15 MEM_CAB_2<8>
R1317 1 2 68Ohm 1% R1333 1 2 68Ohm 1% R1355 1 2 37.4Ohm 1%
4,14 MEM_CAA_2<9> 4,15 MEM_CAB_2<9> 4,15 M_B_DIM0_CK_DDR0_DP
R1356 1 2 37.4Ohm 1%
4,15 M_B_DIM0_CK_DDR0_DN
1
C1301
1UF/6.3V
2
GND
Clo se t o LPDDR3 t erminatio n resistance (0402 siz e)
+VTT
+VTT R1357 1 2 37.4Ohm 1%

4,14 M_A_DIM0_CK_DDR0_DP
R1358 1 2 37.4Ohm 1%
4,14 M_A_DIM0_CK_DDR0_DN
1
C1302
1UF/6.3V
1
C1311 C1312 C1305 C1306 C1307 C1308
2
1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V
2
GND
+VTT
R1362 1 2 37.4Ohm 1%
4,15 M_B_DIM0_CK_DDR1_DP
GND R1361 1 2 37.4Ohm 1%
4,15 M_B_DIM0_CK_DDR1_DN
1
C1303
1UF/6.3V
2
GND
+VTT
R1360 1 2 37.4Ohm 1%
R1359 1 2 37.4Ohm 1%
4,14 M_A_DIM0_CK_DDR1_DN
1
C1304
1UF/6.3V
2
GND
<Variant Name>
Project Name Rev
UX432 R1.0
Title : LPDDR3_TERMINATION
Size
B
SWAP : a300.1260a_ddr_swap.xlsx(page14,15)
+1.8V +1.8V
U1401A U1401B U1402B
L8 P9 B2 A3 U1402A B2 A3
GND
DM0 DQ0 VSS1 VDD1_1 VSS1 VDD1_1
G8 N9 M_A_DQ28 B5 A4 L8 P9 B5 A4
GND
DM1 DQ1 VSS2 VDD1_2 DM0 DQ0 VSS2 VDD1_2
P8 N10 M_A_DQ25 C5 A5 G8 N9 M_A_DQ53 C5 A5
D8 N11 M_A_DQ30 E4 A6 P8 N10 M_A_DQ52 E4 A6
M8 M_A_DQ27 E5 A10 D8 N11 M_A_DQ48 E5 A10
R2
DQ4
M9 M_A_DQ24
Byte3 F5
VSS5 VDD1_5
U3
DM3 DQ3
M8 M_A_DQ55
Byte6 F5
VSS5 VDD1_5
U3
4,13 MEM_CAA_1<0> CA0 DQ5 VSS6 VDD1_6 DQ4 VSS6 VDD1_6
P2 M10 M_A_DQ31 H2 U5 R2 M9 M_A_DQ51 H2 U5
4,13 MEM_CAA_1<1> CA1 DQ6 VSS7 VDD1_7 4,13 MEM_CAA_2<0> CA0 DQ5 VSS7 VDD1_7
N2 M11 M_A_DQ29 J12 U4 P2 M10 M_A_DQ50 J12 U4
N3 F11 M_A_DQ26 K2 U6 N2 M11 M_A_DQ49 K2 U6
M3 F10 M_A_DQ20 L6 U10 +1.2V N3 F11 M_A_DQ54 L6 U10 +1.2V
F3 F9 M_A_DQ23 M5 M3 F10 M_A_DQ63 M5
4,13 MEM_CAA_1<5> CA5 DQ10 VSS11 4,13 MEM_CAA_2<4> CA4 DQ9 VSS11
E3 F8 M_A_DQ18 N4 A8 F3 F9 M_A_DQ57 N4 A8
4,13 MEM_CAA_1<6>
E2
CA6 DQ11
E11 M_A_DQ16
Byte2 N5
VSS12 VDD2_1
A9
4,13 MEM_CAA_2<5>
E3
CA5 DQ10
F8 M_A_DQ61 N5
VSS12 VDD2_1
A9
4,13 MEM_CAA_1<7>
D2
CA7 DQ12
E10 M_A_DQ21 R4
VSS13 VDD2_2
D4
4,13 MEM_CAA_2<6>
E2
CA6 DQ11
E11 M_A_DQ60
Byte7 R4
VSS13 VDD2_2
D4
C2 E9 M_A_DQ22 R5 D5 D2 E10 M_A_DQ62 R5 D5
D9 M_A_DQ19 T2 D6 C2 E9 M_A_DQ58 T2 D6
DQ15 VSS16 VDD2_5 4,13 MEM_CAA_2<9> CA9 DQ14 VSS16 VDD2_5
K3 T8 M_A_DQ17 T3 G5 D9 M_A_DQ56 T3 G5
4,13 M_A_DIM0_CKE0 CKE0 DQ16 VSS17 VDD2_6 DQ15 VSS17 VDD2_6
K4 T9 M_A_DQ0 T4 H5 K3 T8 M_A_DQ59 T4 H5
4,13 M_A_DIM0_CKE1 CKE1 DQ17 VSS18 VDD2_7 4,13 M_A_DIM0_CKE2 CKE0 DQ16 VSS18 VDD2_7
T10 M_A_DQ6 T5 H6 K4 T9 M_A_DQ32 T5 H6
M_A_DQ[63:0] 4 DQ18 VSS19 VDD2_8 4,13 M_A_DIM0_CKE3 CKE1 DQ17 VSS19 VDD2_8
J3 T11 M_A_DQ3 H12 T10 M_A_DQ36 H12
J2
CK_t DQ19
R8 M_A_DQ2
Byte0 B6
VDD2_9
J5 J3
DQ18
T11 M_A_DQ33 B6
VDD2_9
J5
M_A_DQS_DP[7:0] 4 4,13 M_A_DIM0_CK_DDR0_DN CK_c DQ20
R9 M_A_DQ4 B12
VSSQ1 VDD2_10
J6
J2
CK_t DQ19
R8 M_A_DQ35
Byte4 B12
VSSQ1 VDD2_10
J6
DQ21 VSSQ2 VDD2_11 4,13 M_A_DIM0_CK_DDR1_DN CK_c DQ20 VSSQ2 VDD2_11
B3 R10 M_A_DQ7 C6 K5 R9 M_A_DQ37 C6 K5
M_A_DQS_DN[7:0] 4 ZQ0 DQ22 VSSQ3 VDD2_12 DQ21 VSSQ3 VDD2_12
FBA_ZQ0 B4 R11 M_A_DQ1 D12 K6 B3 R10 M_A_DQ34 D12 K6
ZQ1 DQ23 VSSQ4 VDD2_13 ZQ0 DQ22 VSSQ4 VDD2_13
FBA_ZQ1 C11 M_A_DQ5 E6 K12 FBA_ZQ2 B4 R11 M_A_DQ39 E6 K12
DQ24 VSSQ5 VDD2_14 ZQ1 DQ23 VSSQ5 VDD2_14
U12 C10 M_A_DQ9 F6 L5 FBA_ZQ3 C11 M_A_DQ38 F6 L5
DNU1 DQ25 VSSQ6 VDD2_15 DQ24 VSSQ6 VDD2_15
U1 C9 M_A_DQ14 F12 P4 U12 C10 M_A_DQ43 F12 P4
DNU2 DQ26 VSSQ7 VDD2_16 DNU1 DQ25 VSSQ7 VDD2_16
T1 C8 M_A_DQ13 G6 P5 U1 C9 M_A_DQ44 G6 P5
B1 B11 M_A_DQ8 G9 P6 T1 C8 M_A_DQ40 G9 P6
A12
DNU4 DQ28
B10 M_A_DQ15
Byte1 H10
VSSQ9 VDD2_18
U9 B1
DNU3 DQ27
B11 M_A_DQ41
Byte5 H10
VSSQ9 VDD2_18
U9
A1 B9 M_A_DQ11 K10 U8 A12 B10 M_A_DQ46 K10 U8
R1409 1 1% 2 240Ohm A2 B8 M_A_DQ10 L9 A1 B9 M_A_DQ45 L9
DNU7 DQ31 VSSQ12 DNU6 DQ30 VSSQ12
FBA_ZQ0 A13 M_A_DQ12 M6 F2 A2 B8 M_A_DQ42 M6 F2
DNU8 VSSQ13 VDDCA1 DNU7 DQ31 VSSQ13 VDDCA1
B13 M12 G2 A13 M_A_DQ47 M12 G2
DNU9 VSSQ14 VDDCA2 DNU8 VSSQ14 VDDCA2
R1410 1 1% 2 240Ohm T13 L10 N6 H3 B13 N6 H3
DNU10 DQS0_t VSSQ15 VDDCA3 DNU9 VSSQ15 VDDCA3
FBA_ZQ1 U2 G10 M_A_DQS_DP3 P12 L2 T13 L10 P12 L2
DNU11 DQS1_t VSSQ16 VDDCA4 DNU10 DQS0_t VSSQ16 VDDCA4
U13 P10 M_A_DQS_DP2 R6 M2 U2 G10 M_A_DQS_DP6 R6 M2
R1411 1 1% 2 240Ohm D10 M_A_DQS_DP0 T6 U13 P10 M_A_DQS_DP7 T6
DQS3_t VSSQ18 DNU12 DQS2_t VSSQ18
FBA_ZQ2 L3 M_A_DQS_DP1 T12 A11 D10 M_A_DQS_DP4 T12 A11
4,13 M_A_DIM0_CS0# CS0_n VSSQ19 VDDQ1 DQS3_t VSSQ19 VDDQ1
L4 C12 L3 M_A_DQS_DP5 C12
4,13 M_A_DIM0_CS1# CS1_n VDDQ2 CS0_n VDDQ2
R1412 1 1% 2 240Ohm L11 C3 E8 M_A_DIM0_CS0# L4 C3 E8
DQS0_c VSSCA1 VDDQ3 CS1_n VSSCA1 VDDQ3
FBA_ZQ3 J8 G11 M_A_DQS_DN3 D3 E12 M_A_DIM0_CS1# L11 D3 E12
4,13 M_A_DIM0_ODT0 ODT DQS1_c VSSCA2 VDDQ4 DQS0_c VSSCA2 VDDQ4
P11 M_A_DQS_DN2 F4 G12 J8 G11 M_A_DQS_DN6 F4 G12
DQS2_c VSSCA3 VDDQ5 ODT DQS1_c VSSCA3 VDDQ5
C4 D11 M_A_DQS_DN0 G3 H8 M_A_DIM0_ODT0 P11 M_A_DQS_DN7 G3 H8
NC1 DQS3_c VSSCA4 VDDQ6 DQS2_c VSSCA4 VDDQ6
K9 M_A_DQS_DN1 G4 H9 C4 D11 M_A_DQS_DN4 G4 H9
NC2 VSSCA5 VDDQ7 NC1 DQS3_c VSSCA5 VDDQ7
R3 J4
EPIDA & Samsung suggest 240 1% ohm
H11 K9 M_A_DQS_DN5 J4 H11
NC3 VSSCA6 VDDQ8 NC2 VSSCA6 VDDQ8
M4 J9 R3 M4 J9
VSSCA7 VDDQ9 NC3 VSSCA7 VDDQ9
P3 J10 P3 J10
MT52L1G32D4PG-093WT:B VSSCA8 VDDQ10 MT52L1G32D4PG-093WT:B
VSSCA8 VDDQ10
Intel suggest 243 1% ohm
K8 K8
nbs_bga_178p_001c VDDQ11 MT52L1G32D4PG-093WT:B nbs_bga_178p_001c VDDQ11
K11 K11
VDDQ12 nbs_bga_178p_001c VDDQ12
03009-00160400 L12 03009-00160400 L12
VDDQ13 VDDQ13
N8 03009-00160400 N8
VDDQ14 VDDQ14
N12 N12
VDDQ15 VDDQ15
R12 R12
VDDQ16 VDDQ16
U11 U11
VDDQ17 VDDQ17
H4 H4
Vref(CA) +V_VREF_CA_DIMM0 15,19 Vref(CA)
J11 J11 +V_VREF_CA_DIMM0
Vref(DQ) +V_VREF_DQ_DIMM0 19 Vref(DQ)
+V_VREF_DQ_DIMM0
1
MT52L1G32D4PG-093WT:B
C1452 C1401 C1455 C1454
nbs_bga_178p_001c
0.047UF/6.3V 0.047UF/6.3V 0.047UF/6.3V 0.047UF/6.3V
2
03009-00160400
GND
GND
VTT Enable
+1.2V +3VS
R1418
1
SL1401 1 2
1
C1439
4 DDR_VTT_CTRL 0201 200KOhm
0.1UF/6.3V
C1491 close to C1475 nbs_c0201_h13_000s 1%
2
C1492 close to C1482
2
U1405
+1.8V 1 5
NC VCC
2
INA
DDR_PG_CTRL_RR 3 4
GND OUT_Y DDR_PG_CTRL 86
TC7SZ07FU
1
C1491
1
C1492 GND 06G004575010
0201 size
0.1UF/6.3V 0.1UF/6.3V
hh_c0201 hh_c0201
2
@ @
UX432 Delete @R1419 DDR_PG_CTRL_RR PULL DOWN (UX370)
GND
UX432 U1405 Change to 06G004575010
1
C1476 C1478 C1475 C1479 C1477 C1480 C1482 C1481
0402 size
1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V
2
GND
C1402 Close to U1401

C1403 Close ro U1402
C1404 Close to U1501
+1.2V C1408 Close to U1502
+1.2V
hh_c0402_h28_pw
1
C1412
2
10UF/6.3V
1
0603 size 0402 size
C1402 C1403 C1404 C1408 C1411 10UF/6.3V
10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V C1447
2
2
2
GND
R0.1
GND
0329
+1.2V CAP * 6
4.7UF/@ => 10UF/NA
1
hh_c0402_h28_pw hh_c0402_h28_pw hh_c0402_h28_pw hh_c0402_h28_pw hh_c0402_h28_pw C1448 C1441 C1440 C1442 C1443 C1444 C1449 C1456 C1459 C1460
follow sim-team advise
2
10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 1UF/6.3V 10UF/6.3V 1UF/6.3V 10UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V
0402 size C1405 C1406 C1407 C1409 C1410 hh_c0402_h28_pw hh_c0402_h28_pw
2
1
1
R0.1
GND 0409 GND
C1441, C1442 1UF/6.3V => 10UF/6.3V, for AC PI optimization.
1
C1413 C1414 C1415 C1416 C1417 C1418 C1419 C1420 C1421 C1422 C1461 C1434 C1436 C1433 C1437 C1435
0402 size
1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V
2
0402 size
GND GND
1
C1423 C1424 C1425 C1426 C1427 C1429 C1431 C1428 C1432 C1430 C1462 C1463 C1464 C1465 C1466 C1467 C1468 C1469
1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 0.1UF/6.3V 0.1UF/6.3V 0.1UF/6.3V 0.1UF/6.3V 0.1UF/6.3V 0.1UF/6.3V 0.1UF/6.3V 0.1UF/6.3V
@ @ @ @
2
GND GND
<Variant Name>
Project Name Rev
UX432 R1.0
Title : LPDDR3_ON-BOARD_A
Size
D
+1.8V +1.8V
SWAP : a300.1260a_ddr_swap.xlsx(page14,15) U1502B

U1501A U1501B
B2 A3
U1502A VSS1 VDD1_1
L8 P9 B2 A3 B5 A4
GND
DM0 DQ0 VSS1 VDD1_1 VSS2 VDD1_2
G8 N9 M_B_DQ29 B5 A4 L8 P9 C5 A5
GND
P8 N10 M_B_DQ30 C5 A5 G8 N9 M_B_DQ45 E4 A6
D8 N11 M_B_DQ28 E4 A6 P8 N10 M_B_DQ41 E5 A10
DM3 DQ3
M8 M_B_DQ25
Byte3 E5
VSS4 VDD1_4
A10 D8
DM2 DQ2
N11 M_B_DQ44 F5
VSS5 VDD1_5
U3
R2
DQ4
M9 M_B_DQ27 F5
VSS5 VDD1_5
U3
DM3 DQ3
M8 M_B_DQ46
Byte5 H2
VSS6 VDD1_6
U5
4,13 MEM_CAB_1<0> CA0 DQ5 VSS6 VDD1_6 DQ4 VSS7 VDD1_7
P2 M10 M_B_DQ31 H2 U5 R2 M9 M_B_DQ43 J12 U4
4,13 MEM_CAB_1<1> CA1 DQ6 VSS7 VDD1_7 4,13 MEM_CAB_2<0> CA0 DQ5 VSS8 VDD1_8
N2 M11 M_B_DQ26 J12 U4 P2 M10 M_B_DQ40 K2 U6 +1.2V
N3 F11 M_B_DQ24 K2 U6 +1.2V N2 M11 M_B_DQ47 L6 U10
M3 F10 M_B_DQ3 L6 U10 N3 F11 M_B_DQ42 M5
4,13 MEM_CAB_1<4> CA4 DQ9 VSS10 VDD1_10 4,13 MEM_CAB_2<3> CA3 DQ8 VSS11
F3 F9 M_B_DQ5 M5 M3 F10 M_B_DQ51 N4 A8
4,13 MEM_CAB_1<5> CA5 DQ10 VSS11 4,13 MEM_CAB_2<4> CA4 DQ9 VSS12 VDD2_1
E3 F8 M_B_DQ0 N4 A8 F3 F9 M_B_DQ53 N5 A9
4,13 MEM_CAB_1<6>
E2
CA6 DQ11
E11 M_B_DQ4
Byte0 N5
VSS12 VDD2_1
A9
4,13 MEM_CAB_2<5>
E3
CA5 DQ10
F8 M_B_DQ49 R4
VSS13 VDD2_2
D4
4,13 MEM_CAB_1<7>
D2
CA7 DQ12
E10 M_B_DQ6 R4
VSS13 VDD2_2
D4
4,13 MEM_CAB_2<6>
E2
CA6 DQ11
E11 M_B_DQ52
Byte6 R5
VSS14 VDD2_3
D5
C2 E9 M_B_DQ7 R5 D5 D2 E10 M_B_DQ50 T2 D6
D9 M_B_DQ2 T2 D6 C2 E9 M_B_DQ55 T3 G5
M_B_DQ[63:0] 4 DQ15 VSS16 VDD2_5 4,13 MEM_CAB_2<9> CA9 DQ14 VSS17 VDD2_6
K3 T8 M_B_DQ1 T3 G5 D9 M_B_DQ48 T4 H5
4,13 M_B_DIM0_CKE0 CKE0 DQ16 VSS17 VDD2_6 DQ15 VSS18 VDD2_7
K4 T9 M_B_DQ17 T4 H5 K3 T8 M_B_DQ54 T5 H6
M_B_DQS_DP[7:0] 4 4,13 M_B_DIM0_CKE1 CKE1 DQ17 VSS18 VDD2_7 4,13 M_B_DIM0_CKE2 CKE0 DQ16 VSS19 VDD2_8
T10 M_B_DQ23 T5 H6 K4 T9 M_B_DQ32 H12
DQ18 VSS19 VDD2_8 4,13 M_B_DIM0_CKE3 CKE1 DQ17 VDD2_9
J3 T11 M_B_DQ18 H12 T10 M_B_DQ33 B6 J5
M_B_DQS_DN[7:0] 4 4,13 M_B_DIM0_CK_DDR0_DP
J2
CK_t DQ19
R8 M_B_DQ21
Byte2 B6
VDD2_9
J5 J3
DQ18
T11 M_B_DQ34 B12
VSSQ1 VDD2_10
J6
4,13 M_B_DIM0_CK_DDR0_DN CK_c DQ20
R9 M_B_DQ16 B12
VSSQ1 VDD2_10
J6
4,13 M_B_DIM0_CK_DDR1_DP
J2
CK_t DQ19
R8 M_B_DQ38
Byte4 C6
VSSQ2 VDD2_11
K5
DQ21 VSSQ2 VDD2_11 4,13 M_B_DIM0_CK_DDR1_DN CK_c DQ20 VSSQ3 VDD2_12
B3 R10 M_B_DQ22 C6 K5 R9 M_B_DQ36 D12 K6
ZQ0 DQ22 VSSQ3 VDD2_12 DQ21 VSSQ4 VDD2_13
FBB_ZQ0 B4 R11 M_B_DQ19 D12 K6 B3 R10 M_B_DQ37 E6 K12
ZQ1 DQ23 VSSQ4 VDD2_13 ZQ0 DQ22 VSSQ5 VDD2_14
FBB_ZQ1 C11 M_B_DQ20 E6 K12 FBB_ZQ2 B4 R11 M_B_DQ35 F6 L5
DQ24 VSSQ5 VDD2_14 ZQ1 DQ23 VSSQ6 VDD2_15
U12 C10 M_B_DQ10 F6 L5 FBB_ZQ3 C11 M_B_DQ39 F12 P4
DNU1 DQ25 VSSQ6 VDD2_15 DQ24 VSSQ7 VDD2_16
U1 C9 M_B_DQ8 F12 P4 U12 C10 M_B_DQ60 G6 P5
T1 C8 M_B_DQ11 G6 P5 U1 C9 M_B_DQ57 G9 P6
B1
DNU3 DQ27
B11 M_B_DQ13
Byte1 G9
VSSQ8 VDD2_17
P6 T1
DNU2 DQ26
C8 M_B_DQ56 H10
VSSQ9 VDD2_18
U9
A12
DNU4 DQ28
B10 M_B_DQ14 H10
VSSQ9 VDD2_18
U9 B1
DNU3 DQ27
B11 M_B_DQ61
Byte7 K10
VSSQ10 VDD2_19
U8
A1 B9 M_B_DQ15 K10 U8 A12 B10 M_B_DQ58 L9
DNU6 DQ30 VSSQ11 VDD2_20 DNU5 DQ29 VSSQ12
A2 B8 M_B_DQ12 L9 A1 B9 M_B_DQ59 M6 F2
DNU7 DQ31 VSSQ12 DNU6 DQ30 VSSQ13 VDDCA1
R1501 1 1% 2 240Ohm A13 M_B_DQ9 M6 F2 A2 B8 M_B_DQ62 M12 G2
DNU8 VSSQ13 VDDCA1 DNU7 DQ31 VSSQ14 VDDCA2
FBB_ZQ0 B13 M12 G2 A13 M_B_DQ63 N6 H3
DNU9 VSSQ14 VDDCA2 DNU8 VSSQ15 VDDCA3
T13 L10 N6 H3 B13 P12 L2
DNU10 DQS0_t VSSQ15 VDDCA3 DNU9 VSSQ16 VDDCA4
R1510 1 1% 2 240Ohm U2 G10 M_B_DQS_DP3 P12 L2 T13 L10 R6 M2
FBB_ZQ1 U13 P10 M_B_DQS_DP0 R6 M2 U2 G10 M_B_DQS_DP5 T6
DNU12 DQS2_t VSSQ17 VDDCA5 DNU11 DQS1_t VSSQ18
D10 M_B_DQS_DP2 T6 U13 P10 M_B_DQS_DP6 T12 A11
DQS3_t VSSQ18 DNU12 DQS2_t VSSQ19 VDDQ1
R1511 1 1% 2 240Ohm L3 M_B_DQS_DP1 T12 A11 D10 M_B_DQS_DP4 C12
4,13 M_B_DIM0_CS0# CS0_n VSSQ19 VDDQ1 DQS3_t VDDQ2
FBB_ZQ2 L4 C12 L3 M_B_DQS_DP7 C3 E8
4,13 M_B_DIM0_CS1# CS1_n VDDQ2 CS0_n VSSCA1 VDDQ3
L11 C3 E8 M_B_DIM0_CS0# L4 D3 E12
DQS0_c VSSCA1 VDDQ3 CS1_n VSSCA2 VDDQ4
R1512 1 1% 2 240Ohm J8 G11 M_B_DQS_DN3 D3 E12 M_B_DIM0_CS1# L11 F4 G12
4,13 M_B_DIM0_ODT0 ODT DQS1_c VSSCA2 VDDQ4 DQS0_c VSSCA3 VDDQ5
FBB_ZQ3 P11 M_B_DQS_DN0 F4 G12 J8 G11 M_B_DQS_DN5 G3 H8
DQS2_c VSSCA3 VDDQ5 ODT DQS1_c VSSCA4 VDDQ6
C4 D11 M_B_DQS_DN2 G3 H8 M_B_DIM0_ODT0 P11 M_B_DQS_DN6 G4 H9
NC1 DQS3_c VSSCA4 VDDQ6 DQS2_c VSSCA5 VDDQ7
K9 M_B_DQS_DN1 G4 H9 C4 D11 M_B_DQS_DN4 J4 H11
NC2 VSSCA5 VDDQ7 NC1 DQS3_c VSSCA6 VDDQ8
R3 J4 H11 K9 M_B_DQS_DN7 M4 J9
NC3 VSSCA6 VDDQ8 NC2 VSSCA7 VDDQ9
GND M4 J9 R3 P3 J10
VSSCA7 VDDQ9 NC3 VSSCA8 VDDQ10
P3 J10 K8
MT52L1G32D4PG-093WT:B VSSCA8 VDDQ10 VDDQ11
K8 K11
nbs_bga_178p_001c VDDQ11 MT52L1G32D4PG-093WT:B VDDQ12
K11 L12
VDDQ12 nbs_bga_178p_001c VDDQ13
03009-00160400 L12 N8
VDDQ13 VDDQ14
N8 N12
EPIDA & Samsung suggest 240 1% ohm
03009-00160400 GND
VDDQ14 VDDQ15
GND N12 R12
VDDQ15 VDDQ16
R12 U11
VDDQ16 VDDQ17
U11
Intel suggest 243 1% ohm VDDQ17
Vref(CA)
H4
H4 J11 +V_VREF_CA_DIMM0
Vref(CA) +V_VREF_CA_DIMM0 14,19 Vref(DQ)
J11 +V_VREF_DQ_DIMM1
Vref(DQ) +V_VREF_DQ_DIMM1 19
1
MT52L1G32D4PG-093WT:B
1
MT52L1G32D4PG-093WT:B nbs_bga_178p_001c C1537 C1501
nbs_bga_178p_001c C1533 C1534 03009-00160400 0.047UF/6.3V 0.047UF/6.3V
2
03009-00160400 0.047UF/6.3V 0.047UF/6.3V
2
GND
GND
<Variant Name>
Project Name Rev
UX432 R1.0
Title : LPDDR3_ON-BOARD_B
Size
D
CHA - VREF_DQ (All close to memory) CHB - VREF_DQ (All close to memory)
4 +V_DDR_WR_VREF02_DIMM
4 +V_DDR_WR_VREF01_DIMM
1
C1902
1
C1901 0.022UF/16V
0.022UF/16V
2
2
+1.2V
+1.2V
2
+V_VREF_RC1 +V_VREF_RC2
R1904 R1909
0402
1
R1903
24.9Ohm
10Ohm
1%
0402 R1908
24.9Ohm
10Ohm
1%
1
R1901 1%
1
1
1
8.2KOhm R1906
2
1% 8.2KOhm
1%
2
GND
10 mils GND
+V_VREF_DQ_DIMM0 14 10 mils
+V_VREF_DQ_DIMM1 15
1
R1902 R1907
8.2KOhm 8.2KOhm
1% 1%
2
UX432 Delete SL1905 SL1901 SL1915 DDDR DQ CA 直接short過去 P19
Power plan:1.2V
GND GND
VREF_CA (All close to memory)

+1.2V
1
R1912
0402 8.2KOhm
1%
2
R1916
5.1OHM
1 1% 2
10 mils
4 +V_DDR_CA_VREF01_DIMM +V_VREF_CA_DIMM0 14,15
1
C1903
0.022UF/16V
UX432 Delete SL1905 SL1901 SL1915 DDDR DQ CA 直接short過去 P19
1
R1913
8.2KOhm
+V_VREF_CA_RC 1%
2
1
R1911
24.9Ohm
1%
2
GND GND
<Variant Name>
Project Name Rev
UX432 R1.0
Title : LPDDR3 CA_DQ VOL

TAGE
Size
Custom
R0.1
CFL CRB v0.8 page#44
0314
Add 0 ohm, follow UX432FDX
+3VA_DSW +3VSUS
U0301I POWER CHECK
CR30 R2009
53 CNV_L0_RXN CNV_WR_D0N
CP30 CN27 1 2
2
53 CNV_L0_RXP CNV_WR_D0P GPP_H18/CPU_C10_GATE# CPU_C10_GATE# 30,56
CPU_C10_GATE#_R R2002 R2006
CM30 CM27 0Ohm 4.7KOhm 4.7KOhm
53 CNV_L1_RXN CNV_WR_D1N GPP_H19/TIMESYNC_0
CN30 hh_r0201_h12 hh_r0201_h12
53 CNV_L1_RXP CNV_WR_D1P
CF25 @
GPP_H21
1
R0.1 CN32 CN26 GPPC_H21
0129 53 CNV_L0_TXN CNV_WT_D0N GPP_H22
CM32 CM26 GPPC_H21
Remove CNVI connection 53 CNV_L0_TXP CNV_WT_D0P GPP_H23
0130 CK17 GPPC_H23
Add CNVI connection GPP_F10
1
CP33 R0.1
53 CNV_L1_TXN CNV_WT_D1N R2003 0221
CN33
53 CNV_L1_TXP CNV_WT_D1P 20KOhm GPPC_H21 pull-high +3VUSU (follow UX432_0206)。
BV35
GPD7 @
CN31 CN20 GPD7
53 CNV_CLK_RXN CNV_WR_CLKN GPP_F3
2
CP31
53 CNV_CLK_RXP CNV_WR_CLKP
CG25
GPP_D4/IMGCLKOUT0/BK4/SBK4
CP34 CH25
53 CNV_CLK_TXN CNV_WT_CLKN GPP_H20/IMGCLKOUT_1
CN34
CNV_WT_CLKP
53 CNV_CLK_TXP
CR20 GPPC_H21:
GPP_F12/EMMC_DATA0
CP32 CM20
CNV_WT_RCOMP_0 GPP_F13/EMMC_DATA1
CNV_RCOMP CR32 CN19
CNV_WT_RCOMP_1 GPP_F14/EMMC_DATA2
CP20 CM19 PU 24Mhz
2
GPP_F0/CNV_PA_BLANKING GPP_F15/EMMC_DATA3
R2001 CK19 CN18
GPP_F1 GPP_F16/EMMC_DATA4
150OHM CG17 CR18 PD 38.4/19.2MHZ
GPP_F2 GPP_F17/EMMC_DATA5
1% CP18
GPP_F18/EMMC_DATA6
CR14 CM18
GPP_C8/UART0_RXD GPP_F19/EMMC_DATA7
1
CP14
GPP_C9/UART0_TXD
CN14 CM16
R2001 Close U0301 <500 mils CM14
GPP_C10/UART0_RTS# GPP_F20/EMMC_RCLK
CP16 +3VA_DSW
GPP_C11/UART0_CTS# GPP_F21/EMMC_CLK
CR16
GPP_F11/EMMC_CMD
CJ17 CN16
GPP_F8/CNV_MFUART2_RXD GPP_F22/EMMC_RESET#
CH17
2
GPP_F9/CNV_MFUART2_TXD
CK15 R2015 1 2 200OHM 1% R2004
EMMC_RCOMP
CF17 nbs_r0201_h10_000s
GPP_F23/A4WP_PRESENT 100KOhm
1
GND
BGA1528P
R1.1
0521 GPD7
Follow X705 EMMC_RCOMP add R2015= 200 ohm pull low.
1
PDG P.257: eMMC_RCOMP requires the RCOMP termination even if eMMC not used.
R2005
20KOhm
@
2
R1.1
0521
add C10 gate AND gate, follow UX450 & X705。
ESPI +3VA_DSW GPD7:
PD XTAL INPUT IS SINGLE ENDED
2
R2007
4.7KOhm PU XTAL IS ATTACHED
+3VA_DSW
hh_r0201_h12
@
1
SL2003 U2001 GPPC_H23
UX432UA Change Follow CRB
2 1 @ 1 5
2
0402 INB VCC
CPU_C10_GATE# CPU_C10_GATE#_SL 2 R2008
25,30,57,58,88 PM_SUSB# INA
3 4 4.7KOhm
GND OUTY VCCIO_Gate 88
hh_r0201_h12
74LVC1G08GW @
1
06G004092010
1
R2014
GND 100KOhm <Variant Name>
@
GPPC_H23: INTERNAL WEAK PD
Project Name Rev
2
R2013 0Ohm
1 @ 2
PU SAF UX432 R1.0
Title : CPU_PCH_CSI2,EMMC
GND
PD MAF
Size
Dept.: Engineer:
B
Remove ISH ALS_INT# 0331
Main Board
R0.1
0308
add 10Kohm pull-high +3VS (follow FDX)
WHL-U PDG V0.8 P.131: An external Pull-up 8.2 KΩ ~10 KΩ to V3.3S power rail is required. +3VS
R0.1
0306 U0301F
reference ux331
CC27
R0.1 64 FP_CS# GPP_B15/GSPI0_CS0#
0129 CC32 R0.1
GPP_A7/PIRQA#/GSPI0_CS1# 0308
Add BT_ON for WLAN SIP R2155 1 2 22Ohm PIRQA# CE28 CN22 R2154 1 2 10KOhm
0130 FP_SPI 64 FP_CLK
FP_CLK_R CE27
GPP_B16/GSPI0_CLK GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
CR22 PCB_ID0
add 10Kohm pull-high +3VS (follow FDX)
TOUCHPAD_INTR#
remove BT_ON for WLAN SIP 64 FP_MISO WHL-U PDG V0.8 P.131: An external Pull-up 8.2 KΩ ~10 KΩ
GPP_B17/GSPI0_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK
0305 CE29 CM22 PCB_ID1 to V3.3S power rail is required.
Add BT_ON for WLAN SIP 64 FP_MOSI GPP_B18/GSPI0_MOSI GPP_D11/ISH_SPI_MISO/GSPI2_MISO
CP22 UX432 CHECK GSPI2_MOSI R2156 1 2 10KOhm
0410 GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI
Remove typical WLAN(8265) net (for layout purpose) CA31 SPI0_MOSI R0.1 PIRQA#
GPP_B19/GSPI1_CS0# 0308
CA32 CK22
GPP_A11/PME#/GSPI1_CS1#/ SD_VDD2_PWR_EN# GPP_D5/ISH_I2C0_SDA Add GPU_EVENT# pull-high (follow UX432FDX & UX461UN)
CC29 CH20 R2157 1 /VGA 2 10KOhm
75 GPU_EVENT# GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
CC30 GPU_EVENT#
GPU 30,78 GC6_FB_EN
CA30
GPP_B21/GSPI1_MISO
CH22
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA
CJ22
GPP_D8/ISH_I2C1_SCL
R0.1 CK20
0129 53 CNV_BRI_RSP GPP_F5/CNV_BRI_RSP
R2112 1 2 75Ohm CG19 CJ27
Remove CNVI connection 53 CNV_RGI_DT GPP_F6/CNV_RGI_DT GPP_H10/I2C5_SDA/ISH_I2C2_SDA
CNV_RGI_DT R2113 1 2 75Ohm CNV_RGI_DT_R CJ20 CJ29
0130
Add CNVI connection CNVi Wlan 53 CNV_BRI_DT
CNV_BRI_DT_R CH19
GPP_F4/CNV_BRI_DT GPP_H11/I2C5_SCL/ISH_I2C2_SCL
For ﬁnger printer Reset use
53 CNV_RGI_RSP GPP_F7/CNV_RGI_RSP
CM24
GPP_D13/ISH_UART0_RXD /SML0BDATA/I2C4B_SDA TOUCHPAD_INTR# 31
CN23 1 T2103
GPP_D14/ISH_UART0_TXD /SML0BCLK/I2C4B_SCL
CR12 CM23 HID_KB_INT#_PCH
78 DGPU_PWROK GPP_C20/UART2_RXD GPP_D15 /ISH_UART0_RTS#/GSPI2_CS1#
CP12 CR24
78 GPU_RST# GPP_C21/UART2_TXD GPP_D16 /ISH_UART0_CTS#/SML0BALERT# FP_SPI_INT 64
UX433 EMI recommend CN12
78 DGPU_PWR_EN# GPP_C22/UART2_RTS#
CM12 CG12 R0.1
GPP_C23/UART2_CTS# GPP_C12/UART1_RXD/ISH_UART1_RXD
CH12 DIMM_SEL0 R2158 0306 Change to +3VS 0506
GPP_C13/UART1_TXD/ISH_UART1_TXD reference ux331
CM11 CF12 DIMM_SEL1 0Ohm
GPU_RST#
R0.1 0312 RemoveTouch module CN11
GPP_C16/I2C0_SDA GPP_C14 /UART1_RTS#/ISH_UART1_RTS#
CG14 DIMM_SEL2 2 1
GPP_C17/I2C0_SCL GPP_C15 /UART1_CTS#/ISH_UART1_CTS# FP_SPI_RST# 64
FP_RST# 6. The signal is high-Z output with
CK12 BW35 R0.1 need confirm:
GPP_C18/I2C1_SDA GPP_A18/ISH_GP0 no glitch-free pull-down resistor during the pin power sequencing
1
C2101 31 I2C1_SDA_TCH_PAD 0326 Why ux331 connect to GPP.D19 too? (ux461 not)
CJ12 BW34
100PF/50V Touch pad 31 I2C1_SCL_TCH_PAD GPP_C19/I2C1_SCL GPP_A19/ISH_GP1
CA37
remove FP_SPI_RST# D2101, confirmed:
follow UX461 no need connect to GPP_D19.
GPP_A20/ISH_GP2
@/EMI T2101 1 CF27 CA36
2
GPP_H4/I2C2_SDA GPP_A21/ISH_GP3
T2102 1SMB2_DAT_PCH CF29 CA35 +3VSUS
GPP_H5/I2C2_SCL GPP_A22/ISH_GP4
SMB2_CLK_PCH CA34
GPP_A23/ISH_GP5
R0.1 CH27 BW37
0330 GPP_H6/I2C3_SDA GPP_A12/ISH_GP6 /BM_BUSY#/SX_EXIT_HOLDOFF#
CH28
Add T2101, T2102, T2103 GPP_H7/I2C3_SCL
R0.1 for EC test purpose R0.1
0319 CJ30 0308
GPU_RST# add 100pF reservation GPP_H8/I2C4_SDA R2122 改為上件 (follow UX432FDX & UX461UN)
CJ31 R2122 /VGA 10KOhm
GPP_H9/I2C4_SCL
DGPU_PWR_EN# 1 2
I2C1 pull high Remove to P.31 R5312 10KOhm

BGA1528P 1 /VGA 2
GPU_RST#
UX390 check Remove PCB ID 1203
GND
+3VS
No Reboot Boot BIOS Strap Bit BBS
R2121 1 2 10KOhm R2120 1 2 10KOhm

PCB ID0 GPP_D9
PCB_ID0
@
R2124 1 2 10KOhm R2123 1 2 10KOhm
PCB ID1 GPP_D10
PCB_ID1
@
UX305UA remove 0429 UX305UA remove 0429
+3VSUS
Onboard Memory PCB-ID: /RAM

1 2 1 /RAM 2
GPC_12 => DIMM_SEL0 R2101 10KOhm R2102 10KOhm
GPC_13 => DIMM_SEL1 DIMM_SEL0
1 /RAM 2 1 /RAM 2
GPC_14 => DIMM_SEL2 R2103 10KOhm R2104 10KOhm
DIMM_SEL1
R2105 1 /RAM 2 10KOhm R2106 1 /RAM 2 10KOhm NOTE: Enable No Reboot
DIMM_SEL2 PCH will disable the TCO
Timer system reboot feature.
This function is useful when running ITP/XDP.
PCH_GPPB18: weak internal pull down PCH_GPPB22: weak internal pull down
PU Enable PU LPC
PD Disable PD SPI (Default)
UX391RA add 0803

Samsung(新料) x32 16Gb(8GB) 03009-00031200 LPD3 2133 512M*32 FBGA178 DD SAMSUNG/K4E6E304EC-EGCG
Samsung(新料) x32 32Gb(16GB) 03009-00160700 LPD3 2133 1024M*32 FBGA178 QD SAMSUNG/K4EBE304EC-EGCG
Micron x32 16Gb(8GB) 03009-00030900 LPD3 2133 512M*32 FBGA178 DD MICRON/MT52L512M32D2PF-093 WT:B
Micron x32 32Gb(16GB) 03009-00160400 LPD3 2133 1024M*32 FBGA178 QD MICRON/MT52L1G32D4PG-093 WT:B
+3VSUS
2
R2114
100KOhm
1
SPI0_MOSI
PCH_GPPD12:
External pull-up is required
(CNL_PCH EDS 0.7 #56)
R0.1
0129
Remove CNVI Intel Feedback
0130
Add CNVI Intel Feedback
UX432 ADD R2108 Intel Feedback

R2.0
0716
+1.8VSUS +1.8VSUS Follow INTEL advise, R2108 => NC
<Variant Name>
Project Name Rev
R2107 1 2 20KOhm R2108

1
@
2 20KOhm UX432 R1.0
CNV_BRI_RSP CNV_RGI_RSP
Title : CPU_CFG,RSVD,GND
Size
Dept.: Engineer:
ASUSTeK COMPUTER INC. NB2EE1 Tony1_chang
Custom
HD Audio
R0.1
0420
33ohm => 0ohm
Follow WHL_U_PDG_Rev0.9, page265:
Resistor values should be 33 ohms for 3.3v
bus voltage or 0 ohm for 1.8v signaling Touch Panel Pull high
U0301G
RN2201 near PCH
BN34 CH36
HDA_SYNC/I2S0_SFRM GPP_G0/SD_CMD
ACZ_SYNC_AUD_X1 BN37 CL35 +3VS
HDA_BCLK/I2S0_SCLK GPP_G1/SD3_DATA0
R2201 1 2 0Ohm ACZ_BCLK_AUD_X1 BN36 CL36
36 ACZ_BCLK_AUD HDA_SDO/I2S0_TXD GPP_G2/SD3_DATA1
R2204 1 2 0Ohm ACZ_BCLK_AUD_X1 ACZ_SDOUT_AUD_X1 BN35 CM35
36 ACZ_SYNC_AUD 36 ACZ_SDIN0_AUD HDA_SDI0/I2S0_RXD GPP_G3/SD3_DATA2
R2205 1 2 0Ohm ACZ_SYNC_AUD_X1 ACZ_SDIN0_AUD BL36 CN35
HDA_SDI1/I2S1_RXD/SNDW1_DATA GPP_G4/SD_DATA3
ACZ_RST#_AUD R2206 1 2 0Ohm ACZ_RST#_AUD_X1 BL35 CH35 R2207 1 2 10KOhm
36 ACZ_SDOUT_AUD HDA_RST#/I2S1_SCLK/SNDW1_CLK GPP_G5/SD_CD#
CK23 CK36
ACZ_SDOUT_AUD_X1
UX432 Mount ACZ_RST#_AUD_X1
GPP_D23/I2S_MCLK GPP_G6/SD_CLK
CK34
TPanel_Reset# @
GPP_G7/SD_WP
BL37
I2S1_SFRM/SNDW2_CLK
BL34
I2S1_TXD/SNDW2_DATA
R2209 1 2 10KOhm
R0.1 TPanel_INT#
0129 CJ32
Remove CNVI connection 53 RF_RESET_B GPP_H1/I2S2_SFRM/ CNV_BT_I2S_BCLK/CNV_RF_RESET#
0130 CH32
GPP_H0/I2S2_SCLK/ CNV_BT_I2S_SCLK
Add CNVI connection CH29
53 CLKREQ0 GPP_H2/I2S2_TXD/ CNV_BT_I2S_SDI/MODEM_CLKREQ
ACZ_OP_SD 39 CH30
GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO
Q2201B BW36
GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
R2210 1 2 33Ohm CP24 BY31
EM6K1-G-T2R 64 DMIC_CLK_PCH GPP_D19/DMIC_CLK0/SNDW4_CLK GPP_A16/SD_1P8_SEL
Power: +VCCPGPPD
3
DMIC_CLK_PCH_X1 CN24
64 DMIC_DATA_PCH GPP_D20/DMIC_DATA0/SNDW4_DATA
CK33
5 SD_1P8_RCOMP
1 CK25 CM34 R2211 1 2
ACZ_RST#_AUD UX432 Add Reset T2201
GPP_D17/DMIC_CLK1/SNDW3_CLK SD_3P3_RCOMP
200OHM 1%
4
1 CJ25
1
R0.1 T2202 TPanel_Reset# nbs_r0201_h10_000s
0312 GPP_D18/DMIC_DATA1/SNDW3_DATA
C2206 TPanel_INT#
Follow PDG V0.8 P.271,
move C2206 after R. 27PF/50V R0.1 CF35 R0.1
GPP_B14/SPKR
2
0312 0403 GND
remove TP Follow CRB SD_RCOMP add R2211= 200 ohm pull low.
PDG P.285: SD_3P3_RCOMP and SD_1P8_RCOMP precision resistors are still needed, even if SDXC interface is not used.
GND BGA1528P
GND
UX432 Add PDG Figure 7-31 RS2 33 ohm C2 27 PF R0.1

0129
Remove CNVI Intel Feedback
0130
Add CNVI Intel Feedback
FLASH DESCRIPTOR STRAP VCCHDA=+1.8VS Top-Block Swap Override

C2202,C2203,C2204, CFL PDG: 2PF CNVI INTEL Feedback
+VCCHDA
Remove 0429 EDS 4.3.1
EDS 31.7.1.3
ACZ_RST#_AUD_X1
2
R2208 75KOhm
R2202 ACZ_SDOUT_AUD_X1 RF_RESET_B 1 2 1%
HDA_SDO 1KOhm
ACZ_SDIN0_AUD
0=Enable
1
1=Disable Override C2202 C2203 C2204
1
2PF/50V 2PF/50V 2PF/50V
2
ACZ_SDOUT_AUD_X1
ACZ_SDOUT:(1) PCH: Internal PD 20k GND

GND
ohm, VIL=0.35V, VIH=0.65~3.3V (2)
1
R2203
ALC269:VIL<0.35*3.3V, VIH>0.65*3.3V 330Ohm
hh_r0402
2
Q2201_D
Q2201A
EM6K1-G-T2R
6
PCH_GPPB14: weak internal pull down
2
30 PCH_SPI_OV
1
PU Enable
ACZ_SDOUT is a signal used for Flash
Descriptor security Override/ME debug mode PD Disable (default)
HIGH : get overrideen, LOW : disable override
GND
Intel: To enable Flash Descriptor Security Override, this

signal should be pulled up to VCCHDA through a 1
KΩ to 2.2 KΩ ±5% resistor.
<Variant Name>
Project Name Rev
UX432 R1.0
Title : CPU_PCH_AUDIO,SDIO,SDXC
Size
C
Dept.: Engineer:
USB 2.0 USB 3.0
1 USB 3.0 (MB) USB3_1 USB 3.0 (MB)
2 USB 3.0 (I/O) USB3_2
3 USB3_3 USB 3.0 Type C (MB)

4 Card reader USB3_4 USB 3.0 Type C (MB)
5 Camera
6 USB 3.0 Type C (MB)
R0.1 7
0306
Move PCIE_[9:12] => PCIE_[5:8] (follow UX432FDX)
8
U0301H
BW9 CB5 9
PCIE5_RXN/USB31_5_RXN PCIE1_RXN/USB31_1_RXN U3_U3RXDN1 52
BW8 CB6
70 PCIENB_RXN[3:0] 1 /VGA PCIENB_RXN0
PCIE5_RXP/USB31_5_RXP PCIE1_RXP/USB31_1_RXP U3_U3RXDP1 52 MB U3
CX2304 1 2 0.22UF/6.3V PCIENB_RXP0 BW4 CA4 10
70 PCIENB_RXP[3:0] PCIE5_TXN/USB31_5_TXN PCIE1_TXN/USB31_1_TXN U3_U3TXDN1 52 SIP BT
PCIEG_RXN0 CX2303 1 2 0.22UF/6.3V PCIENB_TXN0 BW3 CA3
PCIE5_TXP/USB31_5_TXP PCIE1_TXP/USB31_1_TXP U3_U3TXDP1 52
DGPU PCIEx4 1 130 PCIEG_RXP0
/VGA
PCIENB_TXP0
BU6
PCIE2_RXN
BY8 R0.1
PCIE6_RXN/USB31_6_RXN /USB31_2_RXN/SSIC_1_RXN 0129
/VGA PCIENB_RXN1 BU5 BY9
70 PCIEG_RXN[3:0] PCIE6_RXP/USB31_6_RXP PCIE2_RXP /USB31_2_RXP/SSIC_1_RXP Add IO U3 Type.A
1 2 BU4 CA2
70 PCIEG_RXP[3:0] 2 CX2306 0.22UF/6.3V PCIENB_RXP1
PCIE6_TXN/USB31_6_TXN PCIE2_TXN /USB31_2_TXN/SSIC_1_TXN
IO U3 0208
PCIEG_RXN1 CX2310 1 2 0.22UF/6.3V PCIENB_TXN1 BU3 CA1 Remove IO U3 Type.A (follow marketing spec)
PCIE6_TXP/USB31_6_TXP PCIE2_TXP /USB31_2_TXP/SSIC_1_TXP
PCIEG_RXP1 PCIENB_TXP1
/VGA BT7 BY7
PCIE7_RXN PCIE3_RXN/USB31_3_RXN U3_U3RXDN3 54
/VGA PCIENB_RXN2 BT6 BY6
PCIE7_RXP PCIE3_RXP/USB31_3_RXP U3_U3RXDP3 54
1 2 BU2 BY4
3 CX2308 0.22UF/6.3V PCIENB_RXP2
PCIE7_TXN PCIE3_TXN/USB31_3_TXN U3_U3TXDN3 54 MB TYPE C U3
PCIEG_RXN2 CX2305 1 2 0.22UF/6.3V PCIENB_TXN2 BU1 BY3
PCIE7_TXP PCIE3_TXP/USB31_3_TXP U3_U3TXDP3 54
/VGA BU9 BW6
PCIE8_RXN PCIE4_RXN/USB31_4_RXN U3_U3RXDN4 54
/VGA PCIENB_RXN3 BU8 BW5
PCIE8_RXP PCIE4_RXP/USB31_4_RXP U3_U3RXDP4 54
1 2 BT4 BW2
4 CX2309 0.22UF/6.3V PCIENB_RXP3
PCIE8_TXN PCIE4_TXN/USB31_4_TXN U3_U3TXDN4 54 MB TYPE C U3
PCIEG_RXN3 CX2307 1 2 0.22UF/6.3V PCIENB_TXN3 BT3 BW1
PCIE8_TXP PCIE4_TXP/USB31_4_TXP U3_U3TXDP4 54
/VGA BP5 CE3
R0.1 PCIE9_RXN USB2_1N USB_PN1 52
0129 BP6 CE4 MB with U3
PCIE9_RXP USB2_1P USB_PP1 52
Add WLAN SIP 8265.D2WMLG.S pcie link BR2
0130
Remove WLAN SIP 8265.D2WMLG.S pcie link REMOVE WLAN PCIE BR1
PCIE9_TXN
PCIE9_TXP USB2_2N
CE1
USB_PN2 64
CE2
Merge 0119
0305 IO with U3
Add WLAN SIP 8265.D2WMLG.S pcie link USB2_2P USB_PP2 64
BN6
0306 PCIE10_RXN
BN5 CG3 R0.1
Move PCIE_8 => PCIE_9 (follow UX432FDX)
PCIE10_RXP USB2_3N 0305
If unused, OC [x] pins require a pull-up to V3.3A with 8.2–
0410 BR4 CG4
Remove typical WLAN(8265) net (for layout purpose) PCIE10_TXN USB2_3P Chage PCH USB2.0 port (follow UX432FDX) 10 KΩ resistors.
BR3 +3VSUS
PCIE10_TXP
CD3
USB2_4N USB_PN4 64 R0.1
BN10 CD4 CR (IO BD) 0129 R2380 2.2KOhm
PCIE11_RXN/SATA0_RXN USB2_4P USB_PP4 64
BN8 Remove USB CR connection (p.23 & 64) 1 2
PCIE11_RXP/SATA0_RXP 0222
BN4 CG5 USB_OC_1_2# hh_r0201_h12
PCIE11_TXN/SATA0_TXN USB2_5N USB_PN5 64 Camera Add USB CR connection (to p.64)
BN3 CG6 USB_OC_3_4#
PCIE11_TXP/SATA0_TXP USB2_5P USB_PP5 64
USB_OC_5_6#
BL6 CC1 USB_OC_7_8#
PCIE12_RXN/SATA1A_RXN USB2_6N USB_PN6 54 TYPE C U2
BL5 CC2
PCIE12_RXP/SATA1A_RXP USB2_6P USB_PP6 54
BN2
PCIE12_TXN/SATA1A_TXN
PCIE SSD X4 + SATA colay BN1 CG8
PCIE12_TXP/SATA1A_TXP USB2_7N
CG9
USB2_7P R0.1
BK6
51
51
PCIE9_L3_SSD_RX_N
PCIE9_L3_SSD_RX_P
BK5
PCIE13_RXN
PCIE13_RXP USB2_8N
CB8
0129
Add WLAN SIP 8265.D2WMLG.S USB link
0130
PE_DET SATA General Purpose
L3 BM4 CB9
51 PCIE9_L3_SSD_TX_N PCIE13_TXN USB2_8P Remove WLAN SIP 8265.D2WMLG.S USB link
BM3 0305
51 PCIE9_L3_SSD_TX_P PCIE13_TXP Add WLAN SIP 8265.D2WMLG.S USB link
CH5
USB2_9N 0306
BJ6 CH6 R0.1 0306 Remove Finger print Port.8 => Port.10 +3VS
51 PCIE10_L2_SSD_RX_N PCIE14_RXN USB2_9P
BJ5 0410
51 PCIE10_L2_SSD_RX_P PCIE14_RXP Remove typical WLAN(8265) net (for layout purpose)
L2 BL2 CC3
51 PCIE10_L2_SSD_TX_N PCIE14_TXN USB2_10N
BL1 CC4 1 2
PCIE X4 same contr oller 0323 51 PCIE10_L2_SSD_TX_P PCIE14_TXP USB2_10P Remove BT R2302 10KOhm
MSATA_MPCIE_DET# hh_r0201
BG5 CC5 R2315 1 2 113Ohm 1%
51 PCIE11_L1_SSD_RX_N PCIE15_RXN/SATA1B_RXN USB2_COMP
BG6 CE8
0402 change to 0201 0105
USBCOMP hh_r0201_h10
51 PCIE11_L1_SSD_RX_P PCIE15_RXP/SATA1B_RXP USB2_ID
BL4 CC6
L1 51 PCIE11_L1_SSD_TX_N PCIE15_TXN/SATA1B_TXN USB2_VBUSSENSE
USB2_ID_OTG
BL3 USB2_VBUSSENSE
51 PCIE11_L1_SSD_TX_P PCIE15_TXP/SATA1B_TXP
CK6
GPP_E9/USB2_OC0#/GP_BSSB_CLK
BE5 CK5 USB_OC_1_2#
51 PCIE12_L0_SSD_RX_N PCIE16_RXN/SATA2_RXN GPP_E10/USB2_OC1#/GP_BSSB_DI
BE6 CK8 USB_OC_3_4#
51 PCIE12_L0_SSD_RX_P PCIE16_RXP/SATA2_RXP GPP_E11/USB2_OC2#
BJ4 CK9
L0 51 PCIE12_L0_SSD_TX_N PCIE16_TXN/SATA2_TXN GPP_E12/USB2_OC3#
USB_OC_5_6# When used as DEVSLP, no external pull-up or pull-down terminaon r equired from SATA Host DEVSLP.
BJ3 USB_OC_7_8#
51 PCIE12_L0_SSD_TX_P PCIE16_TXP/SATA2_TXP
CP8
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
CR8 R1.2 SATA_DEVSLP change to DEVSLP2
CE6 CM8
PCIE_RCOMP# GPP_E6/DEVSLP2 SATA2_DEVSLP 51
1 2 CE5
PCIE RCOMP 100 OHM 1% PCIE_RCOMPN
PCIE_RCOMP_P
CN8 1
SATA POR T2 0323
R2316 100Ohm PCIE_RCOMPP T2301 TPC26T_50
GPP_E0/SATAXPCIE0/SATAGP0
RES 100 OHM 1/16W (0402)1% CR28 CM10 SATAGP0
GPP_H12/M2_SKT2/CFG_0 GPP_E1/SATAXPCIE1/SATAGP1
CP28 CP10 R2381 0Ohm
GPP_H13/M2_SKT2/CFG_1 GPP_E2/SATAXPCIE2/SATAGP2 MSATA_MPCIE_DET# 51
CN28 MPCIE_DET#_R 1 2
PDG1.2 P.848 Unused SATAGP[2:0] pins can be le as no connect and need to be
GPP_H14/M2_SKT2/CFG_2
CM28 CN7 default to GPIO funconality , refer to an unused GPIO for
GPP_H15/M2_SKT2/CFG_3 GPP_E8/SATALED#/SPI1_CS1# R1.1
terminaon guidance.
GPPA7 set to GPO remove PU 10K 0402 PDG1.2 P827 UFS_RESET#
AR3
0530
follow eric request, reserve 0 ohm for test.
BGA1528P
2
USB2_ID_OTG USB2_VBUSSENSE
R2322 USB2_ID R2321
1KOhm PD 1K: OTG
PD 0ohm: non OTG
1
PCIE USAGE R1.1-23
PCI-E* X1 DEFAULT/OPTION Co-lay Clock
DGPU UX390 Remove SL 1203

PCIE 5 Port5
DGPU
PCIE 6
DGPU
PCIE 7
DGPU
PCIE 8
WLAN SIP
PCIE 9 Port0
PCIE 10
PCIE 11
PCIE 12
SSD SATA SSD
PCIE 13 Port1
SSD SATA SSD
PCIE 14
SSD SATA SSD
PCIE 15 / SATA 0
SSD SATA SSD
PCIE 16/ SATA 1
<Variant Name>
Project Name Rev
UX432 R1.0
Title : CPU_PCH_PCIE,USB,SA
TA
Size
Dept.: Engineer:
Custom
R0.1
0129
Add WLAN SIP 8265.D2WMLG.S pcie clock link
0130
remove WLAN SIP 8265.D2WMLG.S pcie clock link
0305 PDG P.827 No external resistors
Add WLAN SIP 8265.D2WMLG.S pcie clock link required.
0328
WLAN_CLK Poet.5 =>Port.1, follow UX432FDX U0301J
WLAN 0410
Remove typical WLAN(8265) net (for layout purpose) AW2 AU1
T2411 R0.1
CLKOUT_PCIE_N_0 CLKOUT_ITPXDP# 0305
AY3 AU2
CLKOUT_PCIE_P_0 CLKOUT_ITPXDP_P add for WLAN SIP (follow UX432FDX)
CF32
GPP_B5/SRCCLKREQ0#
BT32
1
GPD8/SUSCLK SUS_CLK 53
BC1
51 PCIE1_SSD_CLK# CLKOUT_PCIE_N_1
SSD BC2 CK3
51 PCIE1_SSD_CLK CLKOUT_PCIE_P_1 XTAL_IN
CE32 CK2 XTAL24_IN
51 CK_REQ_P1# GPP_B6/SRCCLKREQ1# XTAL_OUT
CLK_REQ_SSD# XTAL24_OUT
BD3 CJ1
CLKOUT_PCIE_N_2 CLK_BIASREF
R0.1 BC3 CM3 XCLK_BIASREF
0323 CLKOUT_PCIE_P_2 CLKIN_XTAL REFCLK0 53
CF30 Close CJ1
Add clk test point for test purpose. GPP_B7/SRCCLKREQ2#
0328 BN31
RTCX1
2
Remove Port2/3 clk test point, no enough space.
1
BH3 BN32 RTC_X1
CLKOUT_PCIE_N_3 RTCX2 R2401
BH4 RTC_X2 R2404
CLKOUT_PCIE_P_3 10KOhm
CE31 BR37
GPP_B8/SRCCLKREQ3# SRTCRST# 60.4Ohm
R0.1 BR34 SRTC_RST#
0129 RTCRST# hh_r0402
2
BA1 RTC_RST#
1
Add Micro SD_RTL_RTS5226S pcie clock link CLKOUT_PCIE_N_4 1%
0222 BA2
Remove Micro SD_RTL_RTS5226S pcie clock link Remove PCIE CR CLKOUT_PCIE_P_4
CE30
GPP_B9/SRCCLKREQ4#
GND GND
BE1
70 CLK_PCIE_PEG#_PCH CLKOUT_PCIE_N_5
BE2 change 60.4 ohm 1 %, connect to GND
To NV VGA 70 CLK_PCIE_PEG_PCH CLKOUT_PCIE_P_5
CF31
70 PEX_CLKREQ# GPP_B10/SRCCLKREQ5# follow CFL CRB(for CNVi), Roger 5/3
R0.1
0328
GPU_CLK Poet.1 =>Port.5, follow UX432FDX BGA1528P
R0.1
VGA CLK SRC RTC XTAL 32.768KHz XTAL 24MHz 0314
Add 0 ohm.
+3VS
SRC0
R0.1
R2403 1 2 10KOhm hh_r0201_h12 0309 C2401 27PF/50V
PEX_CLKREQ# move to p.70, follow UX433FDX. R2433 1 2 0Ohm 1 2
PEX_CLKREQ# C2426 R2408
XTAL24_IN XTAL24_IN_R
2 1 1 0Ohm 2
SRC1
3
R2402 1 2 10KOhm hh_r0201_h12 RTC_X1_R RTC_X1
CLK_REQ_SSD# GND
1
15PF/50V
R2407 X2401
1
4
R0.1 X2403 R2415 200KOhm 24MHZ
0308 1%
Add CLKREQ_WLAN# pull high follow UX432FDX 32.768Khz 10MOhm
2
0410 hh_r0201_h12
2
Remove typical WLAN(8265) net (for layout purpose) 07009-00112500 5%
2
C2402 27PF/50V
1
R2434 1 2 0Ohm 1 2
C2428 R2410
XTAL24_OUT XTAL24_OUT_R
2 1 1 0Ohm2
PDG P.820 Any un-used, disabled, and non-mapped SRCCLKREQ# signal must be left as no RTC_X2_R RTC_X2 07009-00065700
connects at the PCH side on the platform. GND
GND
15PF/50V
R0.1
0402
Follow XTAL vender advise & UX432FDX, C2401 / C2402 18PF => 27PF
+3VA_RTC
R2421 1 2 20KOhm
SRTC_RST# 32
hh_r0201_h10 1% SRTC_RST#
1
1
C2407
1
SGL_JUMP
1UF/6.3V
JRST2401
2
hh_c0201_h14
2
JA - SRTC RST_N
2
SAVE ME RTC REGISTER -(1-X) DEFAULT
CLEAR ME RTC REGISTER - (1-2)
JA
GND GND
R2420 1 2 20KOhm
RTC_RST# 32
hh_r0201_h10 1% RTC_RST#
No RTC
1
@
1
C2406
1
SGL_JUMP
1UF/6.3V +3VA
hh_c0201_h14 JRST2402
2
+3VA_RTC
2
JB - RTC REST_N JB
2
CLEAR CMOS - (1-2)
1
SAVE CMOS - (1-X) DEFAULT R2409
1.5KOhm
hh_r0201_h12
GND GND
2
5%
20 mils
SL2402 1 2
0402
1
R2411
39KOHM
1
C2435 hh_r0201_h12
1UF/6.3V
2
An RC delay circuit with a hh_c0201_h14
2
time delay in the range of
18 ms to 25 ms should be
provided.
+V3.3A_RTC GENERATION
<Variant Name>
Project Name Rev
UX432 R1.0
Title : CPU_PCH_CLOCK SIGNALS,RTC

Size
Dept.: Engineer:
C
Main Board
U0301K R2.0
0712
Disconnect PCH_SLP_S0# to EC GPD0 for C10 fan full-speed issue.
BJ35 BJ37 1 2 SL2502 1 T2593
GPP_B13/PLTRST# GPP_B12/SLP_S0# 0201
PLT_RST# CN10 BU36 PCH_SLP_S0_R# 1 2 SL2514 PCH_SLP_S0#
SYS_RESET# GPD4/SLP_S3# 0201 PM_SUSB# 20,30,57,58,88
PDG 1.2 P.572 PROCPWRGD is used only for power sequence debug and is not required to be connected to anything on PM_SYSRST_R# BR36 BU27 SLP_S3_R# 1 2 SL2515
the platform. RSMRST# GPD5/SLP_S4# 0201 PM_SUSC# 30,57,58,86
PM_RSMRST#_PCH BT29 SLP_S4_R#
GPD10/SLP_S5#
T2501 1 AR2
PROCPWRGD
R2560 1 2 60.4Ohm H_CPUPWRGD_R BJ2 BU29
58 VCCST_PWRGD_PCH VCCST_PWRGOOD SLP_SUS# PM_SLP_SUS# 30,58
VCCST_PWRGD_PCH_X1 BT31
SLP_LAN#
CR10 BT30
SYS_PWROK GPD9/SLP_WLAN#
PM_SYSPWROK_PCH BP31 BU37 1 T2507 +3VSUS
PCH_PWROK GPD6/SLP_A#
SL2501 2 1 PM_PWROK_PCH BP30 SLP_A# R0.1
30,58 DPWROK_EC 0201 DSW_PWROK 0312
DPWROK_R BU28 1 2 SL2518
GPD3/PWRBTN# 0201 PM_PWRBTN# 30 follow PDG V0.8 P.130, reserve SLP_S0# Pull-high 100k.
UX432 Delete @R2514 ME_SusPwrDnAck_R (UX370) R2562 1 2 0Ohm @ BV34 BU35 PM_PWRBTN#_R
30 SUSWARN# GPP_A13/SUSWARN#/SUSPWRDACK GPD1/ACPRESENT
R2563 1 2 0Ohm @ ME_SusPwrDnAck_R BY32 BV36 ME_AC_PRESENT_PCH @
30 PCH_SUSACK# GPP_A15/SUSACK# GPD0/BATLOW#
SUSACK_R# PM_BATLOW_R# R2561 100KOhm
T2592 1 BU30 PCH_SLP_S0# 1 2
WAKE#
T2591 1
PCIE_WAKE# BU32 BR35 R2526 1 2 10KOhm
R0.1 GPD2/LAN_WAKE# INTRUDER#
0129 T2505 1
PCH_GPD2# BU34 SM_INTRUDER# ME_SusPwrDnAck_R
GPD11/LANPHYPC
Add pcie wake for WLAN SIP LAN_PWREN CC37 R2528 1 2 10KOhm
0130 GPP_B11/EXT_PWR_GATE#
R0.1 CC36 MPHY_PWREN PM_SYSRST_R#
Remove pcie wake for WLAN SIP GPP_B2/VRALERT#
0305 0326 R0.1 R2506 1 2 100KOhm
un-connectPCH_SUSACK#&SUSWARN#&, follow EC design IP.
Add pcie wake for WLAN SIP (follow UX432FDX)
0410 INPUT3VSEL
BT27 CHECK 0312 MPHY_PWREN
R2506 20K => 100K, follow UX432FDX, PDG V0.8 P.130
Remove typical WLAN(8265) net (for layout purpose) INPUT3VSEL +3VA_RTC
R2559 1MOhm
BGA1528P
SM_INTRUDER# 1 2
+3VA_DSW
Power Sequence +3VA_DSW 1%
R2503
R2512 8.2KOhm
PM_BATLOW_R# 1 2
UX432UA CHECK R2523 1 2 1KOhm
PCIE_WAKE#
09'MoW04: hh_r0201_h12
RN2501A 2 1
2
Optional if ME FW is PCH_GPD2# 10KOHM
Ignition FW
UX432 Delete @U2501 @R2501 R2508 (UX370)
Remove +3VSUS route follow UX330UA LAN_PWREN RN2501B 4 3
10KOHM
100KOhm
Intel Review 1221
1
1 2 SL2503
0201 BUF_PLT_RST# 30,51,78
PLT_RST# UX432 Delete @R2530 ALL_SYSTEM_PWRGD connecnt to PM_PWROK_PCH P25
R2540 1KOhm
PLT_RST# 32,58 30 PM_SYSPWROK
1 2 PM_SYSPWROK_PCH R2516 1 2 10KOhm
PM_RSMRST#_PCH
R2552 2 1 1KOhm R2531 10KOhm

30 PM_PWROK
PM_PWROK_PCH DPWROK_EC 1 2
R2542 2 1 1KOhm
30,58 PM_RSMRST#

PM_RSMRST#_PCH
R2541 2 @ 1 10KOhm Remove PM_PWROK_PCH PD_R2534
30 ME_AC_PRESENT
ME_AC_PRESENT_PCH
T2503 1 1
1
PM_RSMRST#_PCH D2207: Prevent EC drive hign, R2538 R2539 D2505 3
T2504 1 SUS_PWRGD sink low in S5-->G3. 10KOhm 100KOhm BAT54CTB 2
PM_SYSRST_R#
GND
2
UX431 EMI D2501
GND GND 1
30,80 IMVP8_PWRGD
2
3 PCH STRAPS Roger 3/21
PLT_RST# 3VA_DSW_PWRGD
+3VA_DSW
BAT54AW
1
C2501
1
100PF/50V D2503 3
@/EMI DPWROK_R BAT54CTB 2
2
R2504
4.7KOhm
D2502 2 @
30,58,87 3VA_DSW_PWRGD
3
UX432 U2503 Change to D2504 Del @R2504 R2502 Add R2511 R2507 3VA_DSW_PWRGD BAT54CTB
1
1
Power failure solution (S0-->G3,S5-->G3): INPUT3VSEL
2
MS Gate for VCCIO R2505
4.7KOhm
1
UX431 DEL D2504 CFL: 3V SELECT STRAP
LOW 3.3V +/-5%

HIGH 3.0V +/-5%
<Variant Name>
Project Name Rev
UX432 R1.0
Title : CPU_PCH_SYS_POWER
Size
Dept.: ASUS Engineer: Tony1_chang
Custom
+1.05VSUS_VCCPRIM
+1.05VSUS_VCCPRIM
1
C2623 +3VSUS_PCH
1UF/6.3V 66 mils
hh_c0201_h14 Imax = 1.65A U0301P
2
BP20
VCCPRIM_1P051
BW16 CB16 Imax = 0.2A 15mils
VCCPRIM_1P059 VCCPRIM_3P33
BW18
VCCPRIM_1P0510
BW19 +3VA_RTC
VCCPRIM_1P0511
+1.8VSUS_VCCPRIM BY16
VCCPRIM_1P0512
C2623 place close t o Pin#BP 20 CA14 BR23 Imax = 0.002A 10mils
VCCPRIM_1P0514 VCCRTC
40mils Imax = 0.7A CC15 BY20
VCCPRIM_1P81 VCCPRIM_1P0513 +1.05VSUS_VCCPRIM
CD15 BP24
VCCPRIM_1P84 DCPRTC
+3VSUS_PCH CD16
1
VCCPRIM_1P85 C2610
DCPRTC close to BP24 C2608 C2609
CP17
1
C2610 1UF/6.3V 0.1UF/6.3V
VCCPRIM_1P88
BR20 hh_c0201_h14 hh_c0201
VCCPRIM_1P053 +1.05VSUS_VCCPRIM
30mils
2
Imax = 0.2A CB22 0.1UF/6.3V
VCCPRIM_3P34 0.1A
2
CB23 BT12 hh_c0201
VCCPRIM_3P35 VCCAPLL_1P053 +1.05VCCAPLL
CC22
+1.05VSUS VCCPRIM_3P36
CC23 BP14 0.009A
VCCPRIM_3P37 VCCA_BCLK_1P05
CD22
VCCPRIM_3P38
UX432 Del Short lane CD23
CP29
VCCPRIM_3P39 VCCAPLL_1P051
BR14 0.1A +1.05VCCA_XTAL
VCCPRIM_3P310
BU12 0.034A
VCCA_SRC_1P05
170.4 mils BU15
VCCPRIM_CORE1
+VCCPRIM_CORE BU22 CP5 0.002A C2626 Close pin CP5
VCCPRIM_CORE2 VCCA_XTAL_1P05
BV15
VCCPRIM_CORE3
1
Imax = 0.6A C2626
2
BV16 BY24
C2617
BV18
VCCPRIM_CORE4 VCCDPHY_1P242
CA24 30 mils
1.24VCC_LDOSRAM
1UF/6.3V VCCDPHY_EC_1P24 merge to VCCDPHY_1P24, PCH EDS page#52
1UF/6.3V VCCPRIM_CORE5 VCCDPHY_1P244 hh_c0201_h14
2
BV19
2
VCCPRIM_CORE6 C2601 1.24V for CNVi logic. This rail is generated internally with a LDO and needs
Imax = 4.26A hh_c0201_h14 BV20 BY23
VCCPRIM_CORE7 VCCDPHY_1P241 4.7UF/6.3V C2601 close to CP25 to be routed to the motherboard so that the rail can be supplied back to the
1
BV22 CA23 SoC. Refer to the Cannon Lake -U/Y PDG for implementation details.
C2617 place close t o Pin#BV18 VCCPRIM_CORE8 VCCDPHY_1P243
BW20 CP25
VCCPRIM_CORE9 VCCDPHY_EC_1P24 +3VA_DSW
BW22
VCCPRIM_CORE10
CA12 BT23 0.001A 10 mils +1.05VSUS_VCCPRIM
VCCPRIM_CORE11 VCCDSW_3P32
CA16
VCCPRIM_CORE12
CA18 BR12 Imax = 0.027A 10 mils
VCCPRIM_CORE13 VCCA_19P2_1P05
CA19
VCCPRIM_CORE14
CHECK CRB +1.05VCCDSW no connect CA20
CB12
VCCPRIM_CORE15 +1.8VSUS_VCCPRIM
VCCPRIM_CORE16
CB14
VCCPRIM_CORE17
10mils 0.024A CB15 CC18 Imax = 0.6A
VCCPRIM_CORE18 VCCPRIM_1P82 40 mils
TPC26T_50 1 T2601 BT24 CC19
VCCDSW_1P05 VCCPRIM_1P83
C2614
+1.05VCCDSW CD18
VCCPRIM_1P86
1UF/6.3V 1 2 hh_c0201_h14 BU14 CD19
+1.05VCCAPLL VCCAPLL_1P054 VCCPRIM_1P87
0.1A CP23 +3VSUS_PCH
VCCPRIM_1P89
BV12
VCCPRIM_MPHY_1P051
BW12 BW23
Imax = 0.2A 20 mils
+VCCMPHYG VCCPRIM_MPHY_1P053 VCCPRIM_3P32
BW14
Imax = 2.88A VCCPRIM_MPHY_1P054
BY12
VCCPRIM_MPHY_1P055
115.2mils BY14
VCCPRIM_MPHY_1P056
BV2 BP23
15mils +1.05VSUS_VccAMPHYPLL Imax = 0.152A VCCAMPHYPLL_1P05 VCCPRIM_3P31
0.1A BR15 CB36

+1.05VCCAPLL VCCAPLL_1P052 GPP_B0/CORE_VID0
+3VA_DSW CB35
GPP_B1/CORE_VID1
15mils 0.13A CC12
+1.05VSUS_VCCPRIM VCCDUSB_1P05
10mils 0.001A BR24
Page 22 VCCDSW_3P31
10mils 0.004A BT20
+VCCHDA VCCHDA
+1.05VSUS_VCCPRIM 0.002A BV23

+VCCSPI VCCSPI
66 mils Imax = 1.65A BT18
VCCPRIM_1P054
BT19
VCCPRIM_1P055
BU18
VCCPRIM_1P057
BU19
VCCPRIM_1P058
BT22
VCCPRIM_1P056
BP22
VCCPRIM_1P052
20mils BV14
+VCCMPHYG VCCPRIM_MPHY_1P052
BGA1528P
+1.05VSUS Combine +1.0VSUS_PCH to +1.0VSUS 0423 +3VSUS / +1.8VSUS

C2613 C2603 C2619 C2631 place close t o Pin#BV12
C2606,C2607 close to the CP29

+1.05VSUS +1.05VSUS_PCH +1.05VSUS_VCCPRIM +1.05VSUS_PCH +VCCMPHYG Imax = 0.24A
Imax = 2.88A 115.2 mils +3VSUS +3VSUS_PCH
15 mils
73.2 mils
1
C2611 C2631 C2619 C2603 C2613
2
1UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V
Imax = 1.83A
1
hh_c0201_h14 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 HH_C0402_H13_T0D2 R0.1 C2618 C2606 C2676
1
2
0319 @ 1UF/6.3V 1UF/6.3V C2607 1UF/6.3V C2675
VCCHDA connect to +1.8VS,
follow UX433FDX 0.1UF/6.3V 0.1UF/6.3V
2
0403
VCCHDA connect to +1.8VSUS,
follow UX433FDX fix leakage issue
hh_c0201
R0.1 +VCCHDA
0314 R2602 1 0Ohm 2
+VCCMPHYG 4.7UF/6.3V 11G232247525360(0.6mm) => 11203-0070F100(0.33mm), for layout placement purpose +1.8VSUS Iccmax = 36 mA
+1.8VS
R2601 1 0Ohm 2 @ VCCHDA to +1.8VSUS
1
C2612 C2615 remove the reservative power of 3.3V
Filter requirement for +1.05VSUS LC size 0603->0402 DCR MAX 0.3 ohm 0126 0.1UF/6.3V 1UF/6.3V Keep the same Power Rail between the Codec side and CPU side
2
Distance:400 mils +VCCSPI
15 mils
C2628 place close t o Pin#BV2
+3VA_DSW
+1.05VSUS_PCH +1.05VSUS_VccAMPHYPLL
+3VSUS_PCH
L2601
1 2 Imax = 0.152A
15 mils
1
C2616 @
1
120Ohm/100Mhz C2627
1UF/6.3V
1
C2602 C2625 C2628 1UF/6.3V
Irat=300mA hh_c0201_h14
22UF/6.3V 22UF/6.3V 1UF/6.3V @
2
nbs_l0402_h24_000s hh_c0603_h39 hh_c0603_h39 hh_c0201_h14 hh_c0201_h14
2
+1.8VSUS +1.8VSUS_VCCPRIM
C2622, C2605 Place close to the CP17 & CP23
+1.05VSUS_PCH +1.05VCCA_XTAL
Imax = 0.7A
1
L2603
2 Imax = 0.004A
SL2604
1
0603
2
40mils
15 mils 120Ohm/100Mhz
1
C2622 C2605
1
C2604 C2624
Irat=300mA 1UF/6.3V 1UF/6.3V
22UF/6.3V 22UF/6.3V
nbs_l0402_h24_000s hh_c0603_h39 hh_c0603_h39
2
2
2
R0.1
0312
Sort-land => Bead, follow UX432FDX & PDG_V0.8 P.504
+1.05VSUS_PCH
+1.05VCCAPLL
UX432 DEL 1.24VCC_LDOSRAM C2619 C2620
15 mils SL2607
1 2 Imax = 0.1A
0402
R0.1
1
nbs_c0402_h13_001s 0314
2
C2621 C2629 +1.05VCCAPLL 4.7UF/6.3V 11G232247525360(0.6mm)=>11203-0070F100(0.33mm), for layout placement purpose
4.7UF/6.3V
2.2PF/25V 2.2PF/25V C2630
2
1
@/EMI @/EMI
<Variant Name>
Project Name Rev
UX432 R1.0
Title : CPU_PCH_POEWR,GND
Size
Dept.: Engineer:
D
U0301R
U0301S
U0301T
BT35 BY25
CR34 BL7 VSS_145 VSS_217
VSS_1 VSS_73 D6 J18
BT5 AE25 VSS_146 VSS_218 N6 CF23
VSS_2 VSS_74 AL32 AU32 VSS_290 VSS_362
BY5 BM33 VSS_147 VSS_219 B37 V4
VSS_3 VSS_75 BT36 BY28 VSS_291 VSS_363
CP35 CM5 VSS_148 VSS_220 CB3 BE30
VSS_4 VSS_76 D8 J21 VSS_292 VSS_364
CM37 AE27 VSS_149 VSS_221 P10 CF28
VSS_5 VSS_77 AL7 AV25 VSS_293 VSS_365
CK37 BM35 VSS_150 VSS_222 B5 W10
VSS_6 VSS_78 D9 BY33 VSS_294 VSS_366
AW1 CM9 VSS_151 VSS_223 CB33 BE31
VSS_7 VSS_79 AM10 J24 VSS_295 VSS_367
CM1 AE30 VSS_152 VSS_224 P3 CF3
VSS_8 VSS_80 BU11 AV28 VSS_296 VSS_368
BD6 BM36 VSS_153 VSS_225 B7 W27
VSS_9 VSS_81 E23 BY35 VSS_297 VSS_369
AY4 CN13 VSS_154 VSS_226 CB4 CF4
B34 AE7 VSS_155 VSS_227 P33 W30
VSS_11 VSS_83 E27 AV3 VSS_299 VSS_371
E35 BM9 VSS_156 VSS_228 B9 BF3
VSS_12 VSS_84 AM33 BY36 VSS_300 VSS_372
A4 CN17 VSS_157 VSS_229 CB7 CG33
VSS_13 VSS_85 BU23 J36 VSS_301 VSS_373
AE24 AF27 VSS_158 VSS_230 P36 W7
AE26 BN30 VSS_159 VSS_231 BA10 BF33
AF25 CN21 VSS_160 VSS_232 CC11 CG7
VSS_16 VSS_88 BU24 AV36 VSS_304 VSS_376
AG24 AF3 VSS_161 VSS_233 P4 BF36
VSS_17 VSS_89 E31 C1 VSS_305 VSS_377
AG26 BN7 VSS_162 VSS_234 BA28 Y26
VSS_18 VSS_90 BU25 K21 VSS_306 VSS_378
AH24 CN25 VSS_163 VSS_235 P7 BF4
AH25 AF30 VSS_164 VSS_236 BA3 CH31
VSS_20 VSS_92 AN25 C21 VSS_308 VSS_380
B2 CN29 VSS_165 VSS_237 CC20 Y27
VSS_21 VSS_93 BU7 K22 VSS_309 VSS_381
B36 AF33 VSS_166 VSS_238 R27 BG25
C36 BP15 VSS_167 VSS_239 BB3 Y30
C37 AF36 VSS_168 VSS_240 CC25 BG28
VSS_24 VSS_96 BV11 K24 VSS_312 VSS_384
CN1 AF4 VSS_169 VSS_241 R28 CJ11
VSS_25 VSS_97 F12 AV8 VSS_313 VSS_385
CN2 CN5 VSS_170 VSS_242 BB33 Y33
CN37 AF7 VSS_171 VSS_243 CC28 CJ14
VSS_27 VSS_99 F15 K25 VSS_315 VSS_387
CP2 BP25 VSS_172 VSS_244 R29 Y35
VSS_28 VSS_100 AN30 AW28 VSS_316 VSS_388
D1 CN9 VSS_173 VSS_245 BB36 BH28
VSS_29 VSS_101 F18 C33 VSS_317 VSS_389
A32 AG10 VSS_174 VSS_246 CC31 CJ19
VSS_30 VSS_102 AN31 K27 VSS_318 VSS_390
F33 BP3 VSS_175 VSS_247 R30 Y7
VSS_31 VSS_103 BV3 AW29 VSS_319 VSS_391
A3 CP1 VSS_176 VSS_248 BB4 BH29
VSS_32 VSS_104 F2 C4 VSS_320 VSS_392
BJ7 BP32 VSS_177 VSS_249 CC7 CJ23
CJ36 CP11 VSS_178 VSS_250 R31 BH32
A36 AH27 VSS_179 VSS_251 BC25 CJ28
VSS_35 VSS_107 F21 C9 VSS_323 VSS_395
BK10 BP33 VSS_180 VSS_252 CD11 BH33
CJ4 CP13 VSS_181 VSS_253 T27 CJ33
AB27 AH28 VSS_182 VSS_254 CD12 BH35
VSS_38 VSS_110 F24 CA11 VSS_326 VSS_398
BK2 BP4 VSS_183 VSS_255 T30 CJ35
VSS_39 VSS_111 BV4 K3 VSS_327 VSS_399
CK1 CP15 VSS_184 VSS_256 BC29 BP19
VSS_40 VSS_112 F3 AW31 VSS_328 VSS_400
AB3 AH29 VSS_185 VSS_257 CD14 BR16
VSS_41 VSS_113 AP3 CA15 VSS_329 VSS_401
BK28 BP7 VSS_186 VSS_258 T33 BY18
VSS_42 VSS_114 BW11 K30 VSS_330 VSS_402
AB30 CP19 VSS_187 VSS_259 T35 BY19
VSS_43 VSS_115 F4 AY33 VSS_331 VSS_403
BK3 AH30 VSS_188 VSS_260 BC32 CC16
VSS_44 VSS_116 AP33 CA22 VSS_332 VSS_404
CK4 CP21 VSS_189 VSS_261 CD24 BU16
VSS_45 VSS_117 BW15 K31 VSS_333 VSS_405
AB33 AH31 VSS_190 VSS_262 T36 CC14
VSS_46 VSS_118 G21 AY35 VSS_334 VSS_406
BK33 BR19 VSS_191 VSS_263 CD25 BR22
VSS_47 VSS_119 AP36 K32 VSS_335 VSS_407
CK7 CP27 VSS_192 VSS_264 T7 BU20
VSS_48 VSS_120 G27 B12 VSS_336 VSS_408
AB36 AH33 VSS_193 VSS_265 BC8 CD20
VSS_49 VSS_121 AP4 K4 VSS_337 VSS_409
BK4 BR25 VSS_194 VSS_266 CE33 BT14
VSS_50 VSS_122 G33 B15 VSS_338 VSS_410
CL2 AH35 VSS_195 VSS_267 U26 BP12
VSS_51 VSS_123 AR28 CA25 VSS_339 VSS_411
AB4 CP37 VSS_196 VSS_268 BD28 CB24
VSS_52 VSS_124 G35 K9 VSS_340 VSS_412
BK7 AJ25 VSS_197 VSS_269 CE35 CC24
VSS_53 VSS_125 G36 B18 VSS_341 VSS_413
CM13 BT15 VSS_198 VSS_270 U7 J5
VSS_54 VSS_126 AT33 CB11 VSS_342 VSS_414
AB7 AJ28 VSS_199 VSS_271 BD33 U24
VSS_55 VSS_127 BW24 L27 VSS_343 VSS_415
BL25 BT16 VSS_200 VSS_272 CE36 BD7
VSS_56 VSS_128 G9 B21 VSS_344 VSS_416
CM17 CP9 VSS_201 VSS_273 V26 AR4
VSS_57 VSS_129 AT35 L33 VSS_345 VSS_417
AC10 AJ7 VSS_202 VSS_274 BD35 AU4
VSS_58 VSS_130 H21 B23 VSS_346 VSS_418
BL28 CR2 VSS_203 VSS_275 CE7 AW4
CM21 AK3 VSS_204 VSS_276 V27 BA6
VSS_60 VSS_132 BW7 B25 VSS_348 VSS_420
AC27 CR36 VSS_205 VSS_277 BD36 BC4
VSS_61 VSS_133 H27 CB18 VSS_349 VSS_421
BL29 AK33 VSS_206 VSS_278 CF11 BE4
CM25 D21 VSS_207 VSS_279 V3 BE8
VSS_63 VSS_135 BY11 B27 VSS_351 VSS_423
AC30 AK36 VSS_208 VSS_280 BE10 BA4
VSS_64 VSS_136 AU10 CB19 VSS_352 VSS_424
BL30 BT25 VSS_209 VSS_281 CF14 BD4
VSS_65 VSS_137 BY15 L6 VSS_353 VSS_425
CM29 D25 VSS_210 VSS_282 V30 BG4
VSS_66 VSS_138 H9 B29 VSS_354 VSS_426
BL31 AK4 VSS_211 VSS_283 BE28 CJ2
CM31 BT28 VSS_212 VSS_284 CF19 CJ3
VSS_68 VSS_140 BY22 N25 VSS_356 VSS_428
AD33 AL28 VSS_213 VSS_285 V33 AM5
VSS_69 VSS_141 J12 B31 VSS_357 VSS_429
BL32 BT33 VSS_214 VSS_286 BE29 CM4
CM33 D5 VSS_215 VSS_287 CF2 AC5
VSS_71 VSS_143 J15 N27 VSS_359 VSS_431
AD35 AL29 VSS_216 VSS_288 V36 AG5
VSS_72 VSS_144 CB25 VSS_360 VSS_432
VSS_289 BE3 CR6
VSS_361 VSS_433
BGA1528P
BGA1528P
BGA1528P
<Variant Name>
Project Name Rev
UX432 R1.0
Title : CPU_PCH_POEWR,GND
Size
Dept.: Engineer:
B
System Management Interface
SPI PCH Power
+3VS
+12VS
+3VSUS +3VSUS_SPI
20 mils
20 mils D2801
1
2
2
3
2
+3VA_EC R2806
4.7KOhm
R2807
4.7KOhm
hh_r0201_h12 hh_r0201_h12
BAT54AW
1
30,75,79,80 SMB1_CLK_EC 6 1 SMB1_CLK_S 50
Q2806A
EM6K1-G-T2R
CPU Thermal Sensor
5 SPI_SI_SPI
R2801 1
hh_r0201_h10
2 15Ohm
SPI_SI_SPI_3
EC PORT 1
5
30 EC_SI_PCH
30,75,79,80 SMB1_DAT_EC 3 4 SMB1_DAT_S 50
R2802 1 2 15Ohm Q2806B +3VSUS

5 SPI_SO_SPI
SPI_SO_SPI_3 EM6K1-G-T2R
hh_r0201_h10
30 EC_SO_PCH
R0.1 +5VSUS
0308
R2803 1 2 15Ohm
5 SPI_CLK_SPI change net name,
2
2
hh_r0201_h10 SPI_CLK_SPI_3 follow pwr new circuit & UX433FDX
R2808 R2809
30 EC_SCK_PCH
4.7KOhm 4.7KOhm
hh_r0201_h12 hh_r0201_h12
1
1
SL2801 1 2
5 SPI_CS#0_SPI 0201
SPI_CS#0_SPI_3
2
30 EC_SCE#_PCH
6 1 SMB1_CLK_P 90
Q2809A
EM6K1-G-T2R
R0.1
0221 UP1905
5
R2832/R2834 @==> N/A(follow UX432_0206)。
0319
R2832/R2834 N/A==> @(follow UX433FDX)。
PCH SPI 128M (for IT8225)

0320 SMB1_DAT_P 90
+3VSUS_SPI 3 4
R2832/R2834 @==> N/A(follow UX432_0206)。
Q2809B
EM6K1-G-T2R
1
T2801 TPC26T_50
1
2
R0.1 T2802 TPC26T_50 C2803
0221 1
2
T2803 TPC26T_50 R2832 0.1UF/6.3V
R2832/R2834 @==> N/A(follow UX432_0206)。
2
0319 R2834 U2801 100KOhm
R2832/R2834 N/A==> @(follow UX433FDX)。 13
0320 100KOhm GND6
12 +5VSUS +3VA_DSW
R2832/R2834 @==> N/A(follow UX432_0206)。 GND5
1
11
GND4
1
10
GND3
9
GND2
1 8
CS# VCC
SPI_CS#0_SPI_3 2 7 R2805 1 2 15Ohm
DO(IO1) IO3 PCH_SPI_DQ3 5
R2804 1
SPI_SO_SPI_3 2 15Ohm 3 6 PCH_SPI_DQ3_2
5 PCH_SPI_DQ2 IO2 CLK
4 5
2
PCH_SPI_DQ2_2 SPI_CLK_SPI_3
2
GND1
05006-00093200
DI(IO0)
SPI_SI_SPI_3 +3VA_EC R2810
4.7KOhm
R2811
4.7KOhm
2
W25Q128JVPIQ hh_r0201_h12 hh_r0201_h12
R2817
R0.1 TPC26T_50 1 T2813
1
0409 TPC26T_50 1 T2809 100KOhm
Remove T2804 for layout purpose.
TPC26T_50 1 T2810 @
30 SMB3_CLK 6 1 SMB3_CLK_SA 39
1
Q2808A
EC PORT 3
EM6K1-G-T2R Q2808B
Smart AMP
5
EM6K1-G-T2R
30 SMB3_DAT 3 4 SMB3_DAT_SA 39
R0.1
0409
U2801 05006-00090900 => 05006-00093200, follow UX432FDX.
2nd : 05006-00093700
main : 05006-00093200
<Variant Name>
Project Name Rev
UX432 R1.0
Title : PCH-SPI ROM,OTH

Size
Dept.: RD3-SYS2-EE2 Engineer: Tony1_chang
B
UX431 EMI UX433 EMI (Close U3001)
EC 8995
Power
Only 3V Torlence
+3VS +3VA_EC +3VPLL +3VA_EC +3VACC PWR_SW# ALL_SYSTEM_PWRGD
GPB[0,1,2,3,4,5,6]
1
SL3001 SL3006
GPC[3,4,5,6,7]
1
C3003
1 2 1 2 C3024
GPD[0,4,6,7] 0603 0603 100PF/50V
1000PF/25V
GPE[4]
2
1
1
C3002 C3022 C3023 C3006 C3004 C3005 C3007 C3001 @/EMI nbs_c0201_h13_000s
2
GPF[6,7] 0.1UF/6.3V 0.1UF/6.3V 0.1UF/6.3V 0.1UF/6.3V 0.1UF/6.3V 0.1UF/6.3V 0.1UF/6.3V 0.1UF/6.3V @/EMI
GPH[7] SL3007
2
1 2 GND
GPI [0 :7] 0603
GPJ[0:7]
GND GND GND GND GND GND GND GND EC_AGND A/D_MAX_POWER BUF_PLT_RST#
1
1
C3009
C3025
100PF/50V
UX431 Delete +3VA_EC C3022 10UF C3023 10UF 1000PF/25V
2
Can be adjusted to @/EMI nbs_c0201_h13_000s
2
@/EMI
Open-Drain for port:
+3VS GND
GPA0~GPA3 R0.1
GPB0~GPB7 0323
Add EMI CAP C3024/C3025 reserve,
GPD0~GPD7 close U3001
GPE0~GPE7
GPF0~GPF7 +3VPLL
LCD_BACKOFF# 45
GPH0~GPH6 +3VA_EC
+3VACC +3VA
GPJ0~GPJ5
U3001 R3007 10KOhm
D10
K10
D4
D5
K4
E4
E9
1 2
J5
J4
PWR_SW# R3008 10KOhm
7 8 RN3005D K1 M5 LID_SW# R3009 1 2 100KOhm
5,44 LPC_AD0 47OHM EIO0/LAD0/GPM0 PWM0/GPA0 PWR_LED 56
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VSTBY(PLL)
VCC
GPH7
AVCC
5 6 RN3005C LPC_AD0_R J2 N5 AC_IN_OC# 1 2
5,44 LPC_AD1 47OHM EIO1/LAD1/GPM1 PWM1/GPA1 CHG_LED# 64
3 4 J1 M6
EC Require 5,44 LPC_AD2 47OHM
RN3005B LPC_AD1_R
EIO2/LAD2/GPM2 PWM2/GPA2 CHG_FULL_LED# 64 R0.1
0308 +3VA_EC
1 2 RN3005A LPC_AD2_R H2 N6
5,44 LPC_AD3 47OHM EIO3/LAD3/GPM3 PWM3/GPA3 change net name,
LPC_AD3_R K2 K6
5 CLK_KBCPCI_PCH ESCK/LPCCLK/GPM4 PWM4/GPA4 follow pwr new circuit & UX433FDX
CLK_KBCPCI_PCH H1 J6
5,44 LPC_FRAME# ECS#/LFRAME#/GPM5 PWM5/GPA5 FAN1_PWM 67
M4 M7
25,51,78 BUF_PLT_RST# ERST#/LPCRST#/GPD2 PWM6/SSCK/GPA6 KB_LED_PWM 31 UX305UAB KB_BL
G2 K7 RN3002B 3 4.7KOhm 4
5 INT_SERIRQ ALERT#/SERIRQ/GPM6 PWM7/RIG1#/GPA7
SL3017 1 2 L2 SMB3_CLK RN3002A 1 4.7KOhm 2
3 EXT_SMI# 0201 PLTRST#/ECSMI#/GPD4
EXT_SMI#_X1 N4 A4 Need external PU SMB3_DAT RN3001A 1 2
3 EXT_SCI# ECSCI#/GPD3 AC_IN#/GPB0 AC_IN_OC# 89 4.7KOhm
F1 A3 Need external PU SMB1_DAT_EC RN3001B 3 4
GA20/GPB5 LID_SW#/GPB1 LID_SW# 56,64 4.7KOhm
H4 D2 SMB1_CLK_EC RN3001C 5 6
5 RC_IN# KBRST#/GPB6 CTX0/TMA0/GPB2 4.7KOhm
L1 A1 2 1 SL3039 P_SMB0_DATA RN3001D 7 8
32 EC_RST# WRST# VSTBY0 0201 +3VA 4.7KOhm
3VA_ALW C3026 0.1UF/6.3V P_SMB0_CLK
GND
E2 E5 1 2
UX432 ADD DGPU_LIMIT 78 DGPU_LIMIT SSCE1#/GPG0 CRX0/GPC0 TP_Disable# 31
R3004 100KOhm
R3024 1 2 15Ohm B5 EC_GPG2 R3063 1 2 100KOhm
28 EC_SCK_PCH FSCK
EC_SCK_PCH_X1 D1 C2 R1.1 PWRLIMIT_EC# 1 2
DSR0#/GPG6 GPC4 PM_SUSB# 20,25,57,58,88 0312
R3028 1 2 15Ohm A6 R3017 100KOhm
28 EC_SO_PCH FMISO Follow X705
R3001 1 2 15Ohm EC_SO_PCH_X1 B6 E1 3VADSW_ON 1 2
28 EC_SI_PCH FMOSI GPC6 BAT1_IN_OC# 60,89
EC_SI_PCH_X1 A7 M2 1 T3002 R0.1 R3015 10KOhm
28 EC_SCE#_PCH FSCE# SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7 0320
E7 SMB2_CLK 5VSUS_ON 1 2
SSCE0#/GPG2 R3017=100K OHM => 10K OHM
EC_GPG2 N1 2 1 SL3002 follow UX432FDX R3061 1MOhm
RI1#/GPD0 CPU_C10_GATE# 20,56
UX432 check GPG2 Mount? J12 N3 EC_GPD0 2 0201 1 SL3010 R0403 1 2
31 KSI0 KSI0/STB# RI2#/GPD1 0201 ME_AC_PRESENT 25 R3017=10K OHM => 100K OHM
J13 N7 EC_GPD1 Power already tuned value to 1.1V enable.
31 KSI1 KSI1/AFD# GINT/CTS0#/GPD5 OP_SD# 39
J9 M11 OP_SD# GND
31 KSI2 KSI2/INIT# TACH0A/GPD6 FAN1_TACH 67
H12 M12
31 KSI3 KSI3/SLIN# TACH1A/TMA1/GPD7 Remove Fan_Tach_GPU
H9 R3060 100KOhm
31 KSI4 KSI4
H10 N2 2 1 SL3003 VSUS_ON 1 2
31 KSI5 KSI5 L80HLAT/BAO/GPE0 SUSB_EC# 57,78,88
H13 A13 EC_GPE0 2 0201 1 SL3012 R0.1 R2.0
31 KSI6 KSI6 EGAD/GPE1 0201 SUSC_EC# 52,54,64,88 0309 0712
G9 B12 EC_GPE1
31 KSI7 KSI7 EGCLK/GPE3 5VSUS_ON 87 Add WLAN_PWR_GT for WLAN SIP change PCH_SLP_S0#=>CPU_C10_GATE# to EC GPD0
A12 follow UX432FDX for C10 fan full-speed issue.
EGCS#/GPE2 1.2V_ON 86,88
M8 A5 0315
31 KSO0 KSO0/PD0 BTN#/GPE4 VSUS_ON 57,83,88 Remove WLAN_PWR_GT for WLAN SIP
J7 N8
31 KSO1 KSO1/PD1 RTS1#/GPE5 3VADSW_ON 87
N9 M1
31 KSO2 KSO2/PD2 SOUT0/LPCPD#/GPE6
M9 M3
31 KSO3 KSO3/PD3 L80LLAT/GPE7 THRO_CPU# 8,80
K8
31 KSO4
J8
KSO4/PD4 UX432 Del CHG_FULL_LED# CHG_LED# pull high @R3021 @R3022 Vsus_o n Pulldown @R3019 P30 省空間
31 KSO5 KSO5/PD5
N10 F4
31 KSO6 KSO6/PD6 DTR1#/GPG1/ID7 PCH_SUSACK# 25
M10
31 KSO7 KSO7/PD7
N11 +3VA_EC
31 KSO8 KSO8/ACK#
K9
ITE Version ASUS P/N 31 KSO9
N12
KSO9/BUSY
E6
UX432 Delete PM_PWRBTN# pull high @R3019
31 KSO10 KSO10/PE VFSPI
N13
IT8225VG-128/CX 06037-00260300 31 KSO11
M13
KSO11/ERR#
D8
31 KSO12 KSO12/SLCT CLKRUN#/GPH0/ID0 PM_CLKRUN# 5
L12 E8 +3VS
31 KSO13 KSO13 CRX1/SIN1/SMCLK3/GPH1/ID1 SMB3_CLK 28
L13 D7 AMP
31 KSO14 KSO14 CTX1/SOUT1/SMDAT3/GPH2/ID2 SMB3_DAT 28
K12 A9
31 KSO15 KSO15 GPH3/ID3 PM_RSMRST# 25,58
K13 B8
25 PM_PWRBTN# KSO16/SMOSI/GPC3 GPH4/ID4 DPWROK_EC 25,58
J10 A8 R3085 1 2 10KOhm
25,57,58,86 PM_SUSC# KSO17/SMISO/GPC5 GPH5/ID5 PM_PWROK 25
B7 IMVP8_PWRGD
GPH6/ID6 PM_SYSPWROK 25
F2 R3075 10KOhm
GPJ6
G1 G10 SL3097 1 2 RC_IN# 1 2
GPJ7 ADC0/GPI0 PM_SLP_SUS# 25,58
UX432 Delete USB_CHARGE_ON# @T3003 GPJ7 G13 0201
PM_SLP_SUS#
3VSUS_PWRGD 58
ADC1/GPI1
A11 G12
R2.0 56 CAP_LED# PS2CLK0/TMB0/CEC/GPF0 ADC2/GPI2 ALL_SYSTEM_PWRGD 58,80
B11 F9 R3065 10KOhm
0716 PS2DAT0/TMB1/GPF1 ADC3/GPI3 IMVP8_PWRGD 25,80
disconnect PWRLIMIT_EC#, follow A10 F13 IMVP8_PWRGD SUSB_EC# R3066 1 2 10KOhm
Battery 60,89 P_SMB0_CLK SMCLK0/GPF2 ADC4/GPI4 3VA_DSW_PWRGD 25,58,87
EC porting guide V1.3 B10 F10 SL3096 1 2 SUSC_EC# 1 2
60,89 P_SMB0_DATA SMDAT0/GPF3 ADC5/DCD1#/GPI5 0201 SUSWARN# 25
T3004 1 D9 F12 SUSWARN# R3002 100KOhm
PS2CLK2/GPF4 ADC6/DSR1#/GPI6 A/D_MAX_POWER 89
PWRLIMIT_EC# B9 E13 PM_SUSC# R3003 1 2 100KOhm
56 FN_LED# PS2DAT2/GPF5 ADC7/CTS1#/GPI7 MB_MAX_POWER 89
PM_SUSB# 1 2
UX432 ADD FN_LED# B4 E12 SL3099
31,32 PWR_SW# PWRSW/GPB3 TACH2/GPJ0
A2 D13 1 2 @
32 PS_ON_EC
B3
XLP_OUT/GPB4 GPJ1
D12 0402 GC6_FB_EN 21,78 UX432 ADD GC6 EN GND
28,75,79,80 SMB1_CLK_EC SMCLK1/GPC1 DAC2/TACH0B/GPJ2 PCH_SPI_OV 22
Thermal sensor /GPU/UP1905 B2 C13 R0.1
28,75,79,80 SMB1_DAT_EC SMDAT1/GPC2 DAC3/TACH1B/GPJ3
R3033 1 2 43Ohm B1 B13 R0.1 0323
VCORE
8 PECI_EC SMCLK2/PECI/GPF6 DAC4/DCD0#/GPJ4 PCH_SPI_OV follow Desing IP 移至GPJ2
AVSS
0129
VSS1
VSS2
VSS3
VSS4
VSS5
R0.1 T3001 1 PECI_EC_R C1 C12 1 T3003
SMDAT2/PECIRQT#/GPF7 DAC5/RIG0#/GPJ5 Add WLAN_PWR_GT for WLAN SIP
0308 SMB2_DAT HID_KB_INT# 0130
change net name, remove WLAN_PWR_GT for WLAN SIP
R0.1 IT8225VG-128/CX
D6
K5
F5
G4
G5
H5
E10
follow pwr new circuit & UX433FDX
0323
PCH_SPI_OV follow Desing IP 移至GPJ2
0329
name GPC7 net = SMB2_CLK 06037-00260300
name GPF7 net = SMB2_DAT
name GPJ5 net = HID_KB_INT#, follow deasign IP. UX432 Delete PCH_SUS_STAT# GPP_A14 @R3090 GPJ3 CLK_TPMPCI_PCH R0502 ADD T0505 (UX390)
EC_12
GND GND EC_AGND
1
C3008
0.1UF/6.3V
nbs_c0201_h13_000s
2
GND
<Variant Name>
Project Name Rev
UX432 R1.0
Title : CR_KBC_IT8521
Size
C
D3101 D3145 Main Board
D3107
KSI6 1 2
KSO4 1 2 KSI3 1 2
IECS0305C040FR
IECS0305C040FR IECS0305C040FR @/EMI
Keyboard_CON.
@/EMI @/EMI D3120
D3121 D3122 KSO5 1 2
IECS0305C040FR
BL_CON.
KSO2 1 2 KSO15 1 2
@/EMI
12018-00021100
IECS0305C040FR IECS0305C040FR FPC_CON_30P
D3123
@/EMI @/EMI MAX 462 mA
1 2 30
KSO11 30 KSO15 30
29
D3124 D3125 29 KSO0 30
IECS0305C040FR 28 R0.1
28 KSO7 30 0313
1 2 1 2 @/EMI 27
KSO7 KSO0 D3126 27 KSO5 30 J3104 12018-00082900 => 12018-00081800
26 (Follow ME connector list)
26 KSO2 30
IECS0305C040FR IECS0305C040FR 25
KSO10 1 2 25 KSO4 30
@/EMI @/EMI
IECS0305C040FR
24
24
23
KSO8 30 12018-00081800 +5VS
D3128 23 KSO6 30
@/EMI 22
D3127 22 KSO11 30 FPC_CON_4P
1 2 32 21
KSO8 D3129 SIDE2 21 KSO10 30
1 2 20
KSI5 20 KSO12 30 SIDE1 1
IECS0305C040FR 19 5 1
KSI0 1 2 19 KSI3 30 2
IECS0305C040FR @/EMI 18 2
18 KSI0 30 3
IECS0305C040FR 17 3
1
@/EMI C3101
17 KSI2 30 SIDE2 4
@/EMI 16 6 4 KB_LED_PWM_C 0.1UF/6.3V
D3131 16 KSI4 30
15
D3130 D3132 15 KSI6 30 J3104 @
2
1 2 14
KSI2 14 KSI7 30
1 2 1 2 13
KSI1 KSO12 13 KSI1 30
IECS0305C040FR 12 GND GND
12 KSI5 30
IECS0305C040FR IECS0305C040FR 11 Q3101A
3
@/EMI Q3101B
6
11 KSO13 30
@/EMI @/EMI 31 10 PJX138K_R1_00001 PJX138K_R1_00001
D3133 D3134 SIDE1 10 KSO1 30
9 2 5
D3135 9 KSO3 30 KB_LED_PWM 30
1 2 1 2 8 KB_LED_PWM
FN_LED_CON# KSI4
1
8 KSO9 30
4
1 2 7 07005-00660200
KSO13 7 KSO14 30
IECS0305C040FR IECS0305C040FR 6 GND
6
@/EMI @/EMI IECS0305C040FR 5
5 PWR_SW# 30,32
@/EMI 4
4 CAP_LED_CON# 56
3
D3136 D3137 D3138 3 POWER_LED#_R 56
2 POWER_LED#_KB
D3143
POWER_LED#_R 1 2 KSI7 1 2 KSO14 1 2
2
1
1 FN_LED_CON#
+5VSUS
FN_LED_CON# 56
UX431 EMI GND
KSO3 1 2
IECS0305C040FR IECS0305C040FR IECS0305C040FR
J3102
IECS0305C040FR
1
@/EMI @/EMI @/EMI C3104
D3139 D3140 @/EMI 0.1UF/6.3V KB_LED_PWM_C
D3144 @
2
CAP_LED_CON# 1 2 KSO1 1 2
1
C3103
KSO6 1 2
IECS0305C040FR IECS0305C040FR 100PF/50V
@/EMI @/EMI IECS0305C040FR GND GND
@/EMI
2
@/EMI
D3141 D3142
PWR_SW# 1 2 KSO9 1 2
IECS0305C040FR IECS0305C040FR
@/EMI @/EMI
+3VS_TP
30 Mils
+3VS
Touch Pad BOOTON

R0.1
同面cable !!
0417
R3107 @ => N/A, follow Eric request.
R1.1
0521
Add D3147, follow X705.
ELAN / AW Reverse
Finger Printer (USB) @ PWR_SW#
D3147 1N4148WS J3101
2 1
R0.1 1
0306 R3107 1 2 0Ohm 1
Remove Finger print 30 TP_Disable# 2 SIDE1
R0.1 GND R3108 1
/NUM_PAD 2 0Ohm TPAD_EN_R# 2 9 @
1
0309 3
R3109 1
/NUM_PAD 2 0Ohm NUM_GND 3
add number pad pin reservation +5VS 4
1
SGL_JUMP
D3106 GND NUM_5V 4
5
5 JRST3101
2
21 I2C1_SDA_TCH_PAD 6
I2C1_SCL_TCH_PAD 1 2 I2C1_SDA_TCH_PAD 6
2
21 I2C1_SCL_TCH_PAD 7 SIDE2
I2C1_SCL_TCH_PAD 7 10
IECS0305C040FR 21 TOUCHPAD_INTR# 8
8
@/EMI FPC_CON_8P
12018-00214300 GND
GND
D3105
I2C1_SDA_TCH_PAD 1 2 +3VS +3VS_TP
IECS0305C040FR
@/EMI PWR_SW#
1
C3108 C3102 C3122
2
R0.1 RN3101B 4.7KOhm 0.1UF/6.3V 0.1UF/6.3V 4.7UF/6.3V
D3108 0221 I2C1_SDA_TCH_PAD RN3101A 3 4 4.7KOhm @
1
Add TPAD_EN_R# EMI solution reservation @
2
(follow UX432_0206)。 I2C1_SCL_TCH_PAD 1 2
@
1
TPAD_EN_R# 1 2
1
SGL_JUMP
IECS0305C040FR JRST3102
GND
2
@/EMI
2
UX432 Change J3101 PIN2 Change to TP_Disable# connect to EC GPC 0 P30 P31 PEGA request：
TRST3102 放置TOP面，
NUM_5V
D3146 GND 並且周遭 5mm 內，請勿放置零件。
1
TOUCHPAD_INTR# 1 2 C3123
0.1UF/25V R1.1
IECS0305C040FR
2
@/EMI 0521
@/EMI follow PEGA request, and one more PWR_SW# Jumper.
R0.1
R0.1 0309
0319 add number pad pin define
TPAD_EN_R# add diode for EMI solution reservation GND
R0.1
0319
NUM_5V add 0.1UF for EMI solution reservation
Number pad pin define
<Variant Name>
Project Name Rev
UX432 R1.0
Title : EC_KB_TP
Size
Custom
Main Board
Modern standby project should use Silego solution for EC/RTC re set (Microsoft hardware requirements)
6.6.2 Power button behavior

o
https://docs.microsoft.com/en-us/windows-hardware/design/minimu m/minimum-hardware-requirements-overview#section-60---shared-mi nimum-hardware-requirements-for-components
UX362FA R1.3 board will verify this circuit 7/E
R2.0
0712
Follow design IP 032_Whiskey_RESET_Circuit_R10_0628 use Silego solution for EC/RTC reset (Microsoft hardware requirements)
+3VA_EC
R3212 1 2 100KOhm
D3201
BAT54CTB
2
R2.0 3
0713 1
Add R3214/R3213 = 0 OHM for testing purpose.
R3214 1 2 0Ohm
EC_RST# 30
Press PWR_SW# 15s, than reset EC
1
C3201 C3204
EC_RST#_R
1UF/6.3V 0.1UF/6.3V
2
R3206 1 2 10KOhm
PS_ON_EC 30
+3VA
SL3201 U3201 R3213 1 2 0Ohm
8
PS_ON 88
1 2 PS_ON_R
50 CPU_THERM#
EC_RST#
0402
D3202
SL3202 1 7 1
VDD PS_ON SRTC_RST# 24
1 2 2 6 3
75 GPU_THERM#_GPU 0402 THERM# RTC_RST#
THERM#_S 3 5 RTC_RST#_S 2
Power_SW# GND RTC_RST# 24
PLT_RST#
BAT54CTB
30,31 PWR_SW# Press PWR_SW# 20s clear RTC for ASUS CSC request
SLG4E42553VTR
4
06004-01330000
25,58 PLT_RST#
<Variant Name>
Project Name Rev
UX432 R1.0
Title : RST_Reset Circuit

Size
B
UX432 Del @D3601 UX432 Del @C3601 @C3602 @C3642 UX432 SL3601 SL3602 SL3614 SL3603 SL3604 SL3605 SL3649 SL3606 0 603 change to 0402
PVDD1/2
MOAT
+5VS
+5VS +5VS_PVDD +1.8VS +1.8VS_AUD_DVDD_IO
40mils 20mils DVDD-IO
400mA Place next to PIN41
+5VS +5VS_AUDIO SL3607 SL3649
Digital SL3601
Analog 1 2 1 2
1 2
AVDD1 0402 0402
0402 C3615
1
1
C3612
1
C3628 C3629
D3601 4.7UF/6.3V 0.1UF/6.3V 0.1UF/6.3V 10UF/6.3V
+3VA +3VA_AUDIO @ hh_c0201 hh_c0201
AZ5125-01H.R7G Digital
2
2
2
SL3602
1 2
0402
@/EMI
1
+1.8VS +1.8VS_codec
Digital Analog R0.1
SL3614 0313 Max = 0.8W Place next to PIN19
1 2 SL3607 & C3615 0603 => 0402
0402 AVDD2+CPVDD Because codec spk out is not use, Power Efficiency:80% ->1 W
so reduce +5VS power plane. I=0.2A@5V
MOAT
(for layout purpose)
+3VS +3VS_AUD_DVDD
10mils DVDD
R0.1 Place next to PIN46
0330 SL3603 SL3606
follow codec vender advise
add ESD D3601 = AZ5125 1 2 1 2
0402 0402
SL3604
UX432 Del @C3610
1
C3643
1
C3611
1 2 0.1UF/6.3V 0.1UF/6.3V
0402
hh_c0201 hh_c0201
2
SL3605
1 2
0402
Max = 0.8W Place next to PIN3

Power Efficiency:80% -> 1 W
I=0.2A@5V
GND_AUDIO
Place next to PIN38 Place next to PIN37

+5VS_AUDIO
LDO1_CAP
2
C3604
1
C3605
1
10UF/6.3V 0.1UF/6.3V R3649
hh_c0201 100KOhm C3641
2
2
4.7UF/6.3V
2
UX432 C3641 C3608 C3637 C3606 Change to 4.7UF
1
GND_AUDIO
GND_AUDIO
HP DETECT.
+5VS_PVDD
R3621 100KOhm
+3VS_AUD_DVDD
1 2
R3605 1% 200KOhm
SENSE_A_HP 38
HPOUT_JD 1 2
1
HPOUT_JD C3626
0.1UF/6.3V
2
49
48
47
46
45
44
43
42
41
40
39
38
37
U3601A
PVSS1
HP/LINE1-JD(JD1)
I2S-IN/I2S-OUT-JD(JD3)
PVDD2
SPK-OUT-R+
SPK-OUT-R-
SPK-OUT-L-
SPK-OUT-L+
PVDD1
LINE2-R(PORT-E-R)
LINE2-L(PORT-E-L)
AVDD1
LDO1-CAP
DMIC
R3646 1 2 33Ohm
DMIC_CLK 64
DMI_CLK R3601 1 2 33Ohm
DMIC_DATA 64
DMI_DATA
1
/EMI C3620 C3603 /EMI
1 36 C3608 1 2 4.7UF/6.3V 18PF/25V 18PF/25V
39 EAPD I2S-EN/SPDIF-OUT/DMIC-DATA34 /EAPD/DMIC-CLK-IN VREF
2
RTL
EAPDcommand PDB 2 35
PDB AVSS1 GND_AUDIO
3 34
+3VS_AUD_DVDD DVDD LINE1-L(PORT-C-L)
C3627 1 2 0.1UF/6.3V 4 33 LINE1_L
GPIO0/DMIC-DATA12 LINE1-R(PORT-C-R)
DMI_DATA 5 32 LINE1_R
GPIO1/DMIC-CLK 5VSTB/AUX_MODE +3VA_AUDIO
hh_c0201 DMI_CLK 6 31
I2C-DATA MIC2-CAP
7 30
I2C-CLK MIC2-R(PORT-F-R)/SLEEVE
R3620 1 2 33Ohm 8 29 MIC2_R_SLEEVE
39 I2S_DIN
R3610 1 2 22Ohm I2S_DIN_C 9
I2S-IN MIC2-L(PORT-F-L)/RING2
28 MIC2_L_RING2 C3625
Headphone
2
39 I2S_DOUT I2S-OUT1 MIC2-VREFO-R
R3609 1 2 22Ohm I2S_DOUT_C 10 27 MIC2_VREFO_R 10UF/6.3V
39 I2S_BCLK I2S-BCLK MIC2-VREFO-L
R3602 1 2 22Ohm I2S_BCLK_C 11 26 MIC2_VREFO_L
1
39 I2S_MCLK I2S-MCLK/I2S-OUT2 HPOUT-L(PORT-I-L) LINE1_L 38
R3611 1 2 22Ohm I2S_MCLK_C 12 25 AC_HP_L
39 I2S_LRCLK I2S-LRCK HPOUT-R(PORT-I-R) LINE1_R 38
I2S_LRCLK_C AC_HP_R
MIC2_L_RING2 38
AUDIOLINK_SDATA-OUT
PCB trace width of
AUDIOLINK_SDATA-IN
MIC2_R_SLEEVE 38
GND_AUDIO Ring2 & SLEEVE at least 40 mil
MIC2_VREFO_L 38
AUDIOLINK_SYNC
AUDIOLINK_BCLK
MIC2_VREFO_R 38
CPVDD/AVDD2
AC_HP_L 38
LDO3-CAP
LDO2-CAP
AC_HP_R 38
DVDD-IO
CPVEE
AVSS2
CBN
CBP
ALC3288-CG
13
14
15
16
17
18
19
20
21
22
23
24
R0.1
0312
add R3650=0 OHM, follow UX432FDX Please reserve close to chip
C3639 2.2UF/6.3V
06103-00360000 GND_AUDIO
1 2
C3638 I2S_LRCLK I2S_BCLK I2S_MCLK I2S_DOUT I2S_DIN
2
R3650 0Ohm 2.2UF/6.3V RTL command C3639&C3638 2.2uF R0.1
22 ACZ_BCLK_AUD 0312
1 2 ACZ_BCLK_AUD_R
1
22 ACZ_SYNC_AUD add I2S EMI solution reservation, follow UX432FDX
2 1
1
R3607 33Ohm C3631 C3617 C3618 C3632 C3624
22 ACZ_SDIN0_AUD
1
ACZ_SDIN0_AUD_X1 22PF/25V 22PF/25V 22PF/25V 22PF/25V 22PF/25V
22 ACZ_SDOUT_AUD
C3637 @ @ @ @
2
4.7UF/6.3V
+1.8VS_AUD_DVDD_IO
2
UX431 EMI GND_AUDIO Place next to PIN19
+1.8VS_codec
ACZ_BCLK_AUD R0.1
0222
1
R0.1
1
C3622 C3623 U3601B
0312 Update U3601 Footprint(follow ux432_0206)
C3606 0.1UF/6.3V 10UF/6.3V 50
2
Change C3601 0201 => 0402, follow UX432FDX PVSS2
C3601 4.7UF/6.3V hh_c0201 51
PVSS3
2
2
2
10PF/50V 52
1
PVSS4
@ 53
PVSS5
54
PVSS6
GND_AUDIO 55
PVSS7
56
PVSS8
57
PVSS9
58
PVSS10
ALC3288-CG
06103-00360000
Red Woods Design
Title : AUDIO_ALC3228
NB BU2
Engineer: Tony1_chang
Size Project Name Rev
Custom UX432 R1.0

Q3801A Q3801B
1
EM6K1-G-T2R
6
EM6K1-G-T2R
Audio Jack
20 mils 36 AC_HP_R
3 4 AC_HP_R_R
AC_HP_R_R 64
5
39 AMP_SHD#
5
1 6
36 AC_HP_L AC_HP_L_R 64
AC_HP_L_R
3 4
Q3802A Q3802B
EM6K1-G-T2R EM6K1-G-T2R
Depop Circuit 0729 R0.1

0130
Add main board audio jack
C3801 1 2 4.7UF/6.3V 0212
36 LINE1_R
move to IO BD
C3802 1 2 4.7UF/6.3V
36 LINE1_L
36 MIC2_VREFO_R
10 mils 36 MIC2_VREFO_L
1
R3805 R3806
2.2KOhm 2.2KOhm
2
SL3801
1 2
36 MIC2_L_RING2 0402 MIC2_L/RING2_Con 64
MIC2_L/RING2_Con
40 mils SL3802
1 2
36 MIC2_R_SLEEVE 0402 MIC2_R/SLEEVE_Con 64
MIC2_R/SLEEVE_Con
UX432 Del @/EMI @C3803 @C3804 @C3805 100PF

SL3804
1 2
36 SENSE_A_HP 0402 SENSE_A_HP_Con 64
SENSE_A_HP_Con
Project Name Rev
UX432 R1.0
Title : AUD_Headphone
Size
Dept.: Engineer:
B
+12VS
MUTE CONTROL
1
+3VA 100KOhm
3
Q3901B +3VS R3912
5 EM6K1-G-T2R
2
2
4
R3913
AMP_SHD# 38
2
10KOhm AMP_SHD#
R3908
10KOhm
3
1
Q3903B
D3902 5 EM6K1-G-T2R
1
BAT54AW
4
6
1 Q3903A
36 EAPD
3 2 EM6K1-G-T2R
2
1
30 OP_SD#
INTERNAL SPK Conn.

+3VS Max = 4W / Channel
I = 0.7 A (@Speaker : 8 Ohm)
SPK L+ L- R+ R- trace width
Speaker 4 ohm ==> 60mils
2
R3911 DLY_OP_SD#
10KOhm Speak ID
Short 0x98
6
Q3901A Open 0x9C
I2C Slave Address:
1
2 EM6K1-G-T2R 1001 100x = 98 & 1001 110x = 9C
22 ACZ_OP_SD 0X98 (ADR2=0/ADR1=0) R0.1
VTH MAX=1.5V, ACZ1.8V min=1.62V 0312
1
0X9C (ADR2=1/ADR1=0)
J3902 12017-00340300 => 12017-00650100
(Follow ME connector list)
MUTE CONTROL new solution for 1.8V HDA BUG 0318 ADD ADR2 at J3902, follow UX432FDX.
R3914 0Ohm 12017-00650100

R0.1 ADR1 1 2
0312 J3902
add R3914=0 OHM, Eric advice
6 8
36 I2S_DIN 6 SIDE2
ADR2 5
5
+3VA_AMP 4
36 I2S_MCLK 4
H_SPKL+_CON 3
3
R0.1 H_SPKL-_CON 2
36 I2S_BCLK 0312 2
R3909 100KOhm H_SPKR-_CON 1 7
R3909 0201 => 0402, Eric advice 1 SIDE1
ADR2 1 2 H_SPKR+_CON
36 I2S_DOUT
+3VA_DSW +3VA_AMP
65mA
WTOB_CON_6P
L3901
36 I2S_LRCLK
1 2
GPIO3 : (DIN)
120Ohm/100Mhz Reserved for Acousc E cho Cancellaon (AE C),
nbs_l0402_h22_000s @
1
C3985 Default Value : 0000
4.7UF/6.3V 0.1UF/6.3V 0000 : oﬀ ( low )
ADR2
R0.1 C3984 hh_c0201 0111 : SDOUT
DLY_OP_SD#
2
2
0312
L3901 0.3A => 1.5A, follow UX432FDX Reserve Snubber for EMI
LDOO
ADR1
L3902 40mils
1 2
TI_TAS5766M
H_SPKL+_CON
1
30Ohm/100Mhz C3958
49
48
47
46
45
44
43
42
41
40
39
Max = 4W / Channel = 8W U3901A /smart_amp 0.01UF/25V
@
Power Efficiency:85% -> 9.5 W
GND10
GND9
LDOO
XSMT/UVP
ADR1
LRCLK
DIN
BCLK
SCLK
GPIO3
ADR2
2
1
C3954
I=1.05A@9V 0.8 A@12V 0.5A@19V +3VA_AMP
2
1000PF/25V
R3902
2
1 38 Request by TI 10Ohm
DVDD GPIO2
2 37 @
CPVDD GPIO1
3 36
CAPP SCL SMB3_CLK_SA 28
1
AC_BAT_SYS CAPP 4 35
GND1 SDA SMB3_DAT_SA 28
5 34
CAPM GND8
6 33
1
60mils Close PIN13/14 60mils C3980 CAPM
1
VNEG AVDD +3VA_AMP
1UF/6.3V VNEG 7 32 R3905
DACL DACR
1 2 8 31
1
L3905 120Ohm DACL DACR C3981 10Ohm
INPL INPR
2
9 30
1
PVCC INPL INPR 1UF/6.3V C3955 @
INNL INNR
Irat=3A INNL 10 29 INNR 1000PF/25V
2
GND2 GND7
2
11 28
FAULT# GAIN/FSW
2
12 27
1
C3903 C3905 C3966 DLY_OP_SD# GAIN/FSW C3959
2
AVCC GVDD /smart_amp
10UF/25V 1UF/25V 1UF/25V PVCC 13 26 GVDD H_SPKL+ 0.01UF/25V
PVCC1 PVCC2
14 25 PVCC 30Ohm/100Mhz 40mils @
1
GND3 GND6 L3903
2
1 2
1
C3978
1UF/25V H_SPKL- H_SPKL-_CON
OUTNR
OUTPR
OUTNL
OUTPL
GND4
BSNR
GND5
BSPR
BSNL
BSPL
L3904 30Ohm/100Mhz 40mils
2
1 2
C3940
C3941
TAS5766MRMTR H_SPKR- H_SPKR-_CON
15
16
17
18
19
20
21
22
23
24
1
C3960
/smart_amp 0.01UF/25V
1
H_SPKR+ C3956 @
06040-01160000
2
1000PF/25V
0.22UF/25V
0.22UF/25V
1
2
2
R3906
10Ohm
2
@
H_SPKL+
R0.1
H_SPKR-
H_SPKR+
H_SPKL-
1
U3901B 0222
Update U3901 Footprint(follow ux432_0206)
50
GND11
51
1
GND12
52
C3942
C3943
R3907
GND13
53 10Ohm
GND14
54 @
2
GND15
55
1
C3957
2
GND16
56
0.22UF/25V
0.22UF/25V
1000PF/25V
1
GND17
57 C3961
2
GND18
2
58 0.01UF/25V
GND19
59 @
1
GND20 L3906 30Ohm/100Mhz
60
GND21 40mils
61 1 2
GND22 MLCC 0.22UF/25V (0603) X7R 10%
H_SPKR+_CON
/smart_amp
TAS5766MRMTR
Fixed by TI
2 1 2 1 2 1
DACR C3972 1UF/6.3V INPR CAPP C3970 1UF/6.3V CAPM DACL
C3971 INPL
1UF/6.3V GAIN/FSW Ra Rb
R0.1
0312
1
R3903/R3904 0201 => 0402, follow UX432FDX
R3903 R3904
51KOhm 51KOhm
1% 1%
VNEG INNL INNR LDOO
2
1
1
C3973 C3974 C3975 C3976
GVDD
1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V
1
C3977
1UF/25V
2
Project Name Rev
UX432 R1.0
Title : AUD_SMA_TSA5766M
Size
Dept.: Engineer:
C
Main Board
New Design Debug Port

R1.1
+3VSUS
20 mils +3VSUS 0126

WTOB_CON_4P
5 SMB_CK 1 SIDE1
1 5
5 SMB_DATA 2
2
3
3
4 SIDE2
4 6
JDEBUG4401
12017-00380100
change to sm all footprint
LPC Debug Port

Follow UX370UAR 12018-00102300
+3VS
30 mils JDEBUG4402
12
12
11 14
5,30 LPC_AD0 11 SIDE2
10
10
9
5,30 LPC_AD1 9
8
8
7
5,30 LPC_AD2 7
6
6
5
5,30 LPC_AD3 5
4
4
3
5,30 LPC_FRAME# 3
2 13
2 SIDE1
1
5 CLK_DEBUG 1
FPC_CON_12P
<Variant Name>
Project Name Rev
UX432 R1.0
Title : BUG_Debug
Size
Dept.: Engineer:
A4
LCD +3VS_LCD Power R0.1
0309
EDP Signals
R4501 330 OHM ==> 200 OHM,
follow UX432FDX
0312
add net name +3VS_LCD_R UX432 Delete EDP 2 LANE EDP_TXN2 EDP_TXN3
+3VS_LCD +3VS
1 2 RN4503A
0Ohm
R4501 1 2 200Ohm
+3VS_LCD_R
U4501
1 6 EDP_TXN1_C EDP_TXN1_CON
R4503
2
OUT IN
5 C4532 1 2 0.1UF/6.3V 09G092090400
1
1KOhm GND SET 3 EDP_TXN1
1 2 3 4 EDP_TXN1_C 90Ohm @
3 L_VDDEN_PCH FLAG/EN DSG C4533 1 2 0.1UF/6.3V
L_VDDEN_PCH_R 3 EDP_TXP1 L4515
EDP_TXP1_C
G517AH1TP1U
4
2
@ 06016-01100000
1
1
R4587 EDP_TXP1_C EDP_TXP1_CON
4.7UF/6.3V C4509
R4502 ILIM 14K = 1.5A 1UF/6.3V
14KOHM
100KOhm C4501 1% C4530 1 2 0.1UF/6.3V 3 4 RN4503B
3 EDP_TXN0 0Ohm
2
EDP_TXN0_C
C4531 1 2 0.1UF/6.3V
1
3 EDP_TXP0
EDP_TXP0_C
1
1 2 RN4504A
0Ohm
GND GND GND GND GND
EDP_TXN0_C EDP_TXN0_CON
+3VS_LCD C4539 1 2 0.1UF/6.3V 09G092090400
Panel Control Signals
1
3 EDP_AUXN 90Ohm @
EDP_AUXN_C
C4538 1 2 0.1UF/6.3V
3 EDP_AUXP L4517
EDP_AUXP_C
4
1
R4515
1KOhm EDP_TXP0_C EDP_TXP0_CON
D4503 3 4 RN4504B
2
0Ohm
1
3 LCD_BACKEN_PCH
3
2 LCD_BLEN_CON
30 LCD_BACKOFF#
BAT54AW
SL4521 1 2
3 L_BKLTCTL_PCH 0201 R0.1
LCD_PWM_CON 22 0312
SIDE2
J4501 12017-00181800 => 12017-00142000
20 24 (Follow ME connector list)
R0.1
0306 20 SIDE4
19
move Camera from p.45 to p.64 19
move TP from p.45 to p.64 EDP_TXN1_CON 18
18
EDP_TXP1_CON 17
17 0315A
16
16 Pin define follow Panel spec.
EDP_TXN0_CON 15 0323
15
EDP_TXP0_CON 14 J4501 30PIN => 20PIN
14
13
13
SL4502 1 2 EDP_AUXP_C 12
3 EDP_HPD_CON 0201 12
eDP_HPD_con_R EDP_AUXN_C 11
11
10
10
9
2
+3VS_LCD 30 miles 0.5A 9
R4505 R0.1 8
0306 8
100KOhm 7
move TP from p.45 to p.64 7
eDP_HPD_con_R 6
6
LCD_BLEN_CON 5
5
1
LCD_PWM_CON 4
4
3
3
2
GND 2
AC_BAT_SYS_LCD
30 miles 1 23
1 SIDE3
21
SIDE1
LED AC_BAT Power WTOB_CON_20P

J4501
AC_BAT_SYS AC_BAT_SYS_LCD 12017-00201000
F4501 20 miles GND GND

1 2
1.5A/32V
1
C4505
1UF/25V
2
GND
Touch Panel I2C Pull High

DMIC
R0.1
0222
Touch Reset Control
move D-MIC to p.64
TPanel_Report_SW
R0.1
Camera USB 0306
move TP from p.45 to p.64
R0.1
0222
move Camera to p.64
<Variant Name>
Project Name Rev
UX432 R1.0
Title : LCD_Panel-B
Size
C
HDMI Power
HDMI Signals
+12VS
C4801 0.1UF/6.3V 1 2 RN4801A
1
3 HDMI_DATA2N_PCH 0Ohm
1 2 HDMI_DATA2N_PCH_X1 HDMI_DATA2N_PCH_X2
R4801 UX432 Delete SL4802
nbs_c0201_h13_000s
100KOhm
1
@ +5VS_F
D2
2
90Ohm/100Mhz +5VS +5VS_HDMI
L4801
1
1
40 miles
G
F4801 1.5A/6V
2 3 1 2
3
C4802 0.1UF/6.3V 3 4 RN4801B
D
S
3 HDMI_DATA2P_PCH 0Ohm
1 2 HDMI_DATA2P_PCH_X1 HDMI_DATA2P_PCH_X2 07013-00220000
1
C4809
nbs_c0201_h13_000s
Q4802 2nd source
AP2304GN 07013-00220100 0.1UF/6.3V
2
nbs_c0201_h13_000s
FOLLOW X542UNV
C4803 0.1UF/6.3V 1 2 RN4802A GND
3 HDMI_DATA1N_PCH 0Ohm
1 2 HDMI_DATA1N_PCH_X1 HDMI_DATA1N_PCH_X2
nbs_c0201_h13_000s
HDMI 1.4 WHL PDG Change to 732 ohm
1
L4802
D1 90Ohm/100Mhz
@
HDMI Cost-reduced Level shiter
4
3 4 1 2
3 HDMI_DATA1P_PCH
C4804 0.1UF/6.3V
0Ohm
RN4802B UX432 Delete KB_PWR_LED_EN GPP_P15 @R4810 @R5603 P21 P48 P56 R4831 1% 470Ohm
1 2 HDMI_DATA1P_PCH_X1 HDMI_DATA1P_PCH_X2 R4836 1 1% 2 470Ohm HDMI_DATA2P_PCH_X1
nbs_c0201_h13_000s PWR_LED_R For HDMI SLEEP EA TEST HDMI_DATA2N_PCH_X1
R4832 1 1% 2 470Ohm
R4833 1 1% 2 470Ohm HDMI_DATA1P_PCH_X1
HDMI_DATA1N_PCH_X1
R4834 1 1% 2 470Ohm
R4835 1 1% 2 470Ohm HDMI_DATA0P_PCH_X1
C4810 0.1UF/6.3V 1 2 RN4803A R4809 @ 0Ohm HDMI_DATA0N_PCH_X1
3 HDMI_DATA0N_PCH 0Ohm 56 PWR_LED_R
1 2 HDMI_DATA0N_PCH_X1 HDMI_DATA0N_PCH_X2 1 2 R4838 1 1% 2 470Ohm
nbs_c0201_h13_000s +3VS R4837 1 1% 2 470Ohm HDMI_CLKP_PCH_X1
@ R4804 0Ohm HDMI_CLKN_PCH_X1
1
90Ohm/100Mhz 1 2 R0.1
L4803 0306
D0 Q4801A
6
R4831~R4838 732ohm => 470ohm(follow PBG_V0.8_P.114)
R0.1 UM6K33N
4
0312 2
R4809 N/A => @, R4804 @ => N/A
1
C4811 0.1UF/6.3V 3 4 RN4803B 07G005D19010 Id=100mA
3 HDMI_DATA0P_PCH 0Ohm
1 2 HDMI_DATA0P_PCH_X1 HDMI_DATA0P_PCH_X2 07G005C68010 Id=250mA Is=125mA
nbs_c0201_h13_000s 07G005D02010 Id=100mA
GND Ids=3.3/(470+50)*8=50.7mA
For under 1.65GHz
C4812 0.1UF/6.3V 1 2 RN4804A
3 HDMI_CLKN_PCH 0Ohm
1 2 HDMI_CLKN_PCH_X1 HDMI_CLKN_PCH_X2
nbs_c0201_h13_000s HDMI HPD 1
U4801
1
Line-1
L4804 +3VS HDMI_DATA0P_PCH_X2 2 9
Line-2 NC4
3 8
CLK 90Ohm/100Mhz
@ R4861 1MOhm
HDMI_DATA0N_PCH_X2
4
GND NC3
7
HDMI_DATA0P_PCH_X2
HDMI_DATA0N_PCH_X2
4
Line-3 NC2
1 2 HDMI_CLKP_PCH_X2 5 6 HDMI_CLKP_PCH_X2
Line-4 NC1
HDMI_CLKN_PCH_X2 HDMI_CLKN_PCH_X2
5
C4813 0.1UF/6.3V 3 4 RN4804B AZ1045-04F /EMI
3 HDMI_CLKP_PCH 0Ohm
1 2 HDMI_CLKP_PCH_X1 HDMI_CLKP_PCH_X2 2 1 SL4801 4 3 07G028076030
3 HDMI_HP 0201
nbs_c0201_h13_000s HDMI_HP_X1 GND
UM6K33N
1
Q4801B R4826 U4802
20KOhm 1
Line-1
nbs_r0201_h12_000s HDMI_DATA1P_PCH_X2 2 9
Line-2 NC4
HDMI_DATA1N_PCH_X2 3 8 HDMI_DATA1P_PCH_X2
HDMI DDC Level-shi er
2
GND NC3
4 7 HDMI_DATA1N_PCH_X2
1% Line-3 NC2
HDMI_DATA2P_PCH_X2 5 6 HDMI_DATA2P_PCH_X2
GND Line-4 NC1
HDMI_DATA2N_PCH_X2 HDMI_DATA2N_PCH_X2
AZ1045-04F /EMI
07G028076030
GND
HDMI CON.
+3VS +3VS +5VS_HDMI UX432 Delete D4801 D4802

R0.1 DDPC_SCL_PCH_X1 DDPC_SDA_PCH_X1
0129
HDMI_D ==> HDMI_A
12022-00131600(UX432FN) ==> 12022-00099600(UX331UN)
1
0315 C4805 C4806
J4801 = 12022-00132100 , follow connector list 100PF/50V 100PF/50V
@/EMI @/EMI
2
1
1
RN4806A RN4805A
HDMI_CON_19P
2.2KOHM 2.2KOHM
Hot_Plug_Detect
HDMI_HP_X1 19
+5VS_HDMI +5_Power P_GND1
18 20
2
2
DDC/CEC_Ground
17
SDA P_GND3
1 6 DDPC_SDA_PCH_X1 16 22
3 DDPC_SCL_PCH SCL
15
Q4807A
DDPC_SCL_PCH_X1 DDPC_SCL_PCH_X1
14
Utility UX431 EMI
CEC
EM6K1-G-T2R 13
TMDS_Clock-
HDMI_CLKN_PCH_X2 12
TMDS_Clock_Shield
11
D0 HDMI_CLKP_PCH_X2 10
TMDS_Clock+
TMDS_Data0-
HDMI_DATA0N_PCH_X2 9
TMDS_Data0_Shield
8
TMDS_Data0+
7
D1 HDMI_DATA0P_PCH_X2
TMDS_Data1-
TMDS_Data1_Shield
5
TMDS_Data1+ P_GND4
HDMI_DATA1P_PCH_X2 4 23
TMDS_Data2-
TMDS_Data2_Shield P_GND2
+5VS_HDMI 2 21
+3VS
+3VS D2 HDMI_DATA2P_PCH_X2 1
TMDS_Data2+
J4801
12022-00132100
GND
3
RN4806B RN4805B GND
2.2KOHM 2.2KOHM
New connector, need to check pin define.
<Variant Name>
4
5
Project Name Rev
4 3
3 DDPC_SDA_PCH
DDPC_SDA_PCH_X1 UX432 R1.0
Q4807B
EM6K1-G-T2R Title : HDMI-type D
Size
C
CPU Sensor
+3VS
7.5K => 90 'C
2
R0.1
0420
10K => 100 'C R5002
U5001 06G023123010(NCT7717U)=> 06023-00330000(NCT7717U-A),
7.5KOhm follow RD Tool recommendation for cost reason.
1%
1
U5001
SL5001 1 2 1 5 1 2 SL5002
28 SMB1_CLK_S 0201 SCL SDA 0201 SMB1_DAT_S 28
SML1_CLK_TH 2 SML1_DAT_TH
GND
3 4
32 CPU_THERM# ALERT# VDD +3VS
O/D NCT7717U-A
06023-00330000
1
C5005
0.1UF/6.3V
2
nbs_c0201_h13_000s
<Variant Name>
Title : FAN_Fan & Sensor
ASUS
Custom UX432 R1.0

SSD CONN. +3VS SL5101 @ +3VS_SSD
C5136 Close PIN 12 14 16
1.5A
C5103 Close PIN 70 72 74
1 2 80 MILS
0805
1
C5136 C5103
C5137 C5132 22UF/6.3V 22UF/6.3V
0.1UF/6.3V 0.1UF/6.3V hh_c0603_h39 hh_c0603_h39
2
nbs_c0201_h13_000s nbs_c0201_h13_000s
GND
SATA DEVSLP.
SL5102 +3VS_SSD
1 2
23 SATA2_DEVSLP 0201
SATA2_DEVSLP_R
J5101
2 1
Delete SATA2_DEVSLP_R R5317 0 ohm ADD SL5102 直接short r5101 0ohm nonDEVSLP P51 3.3V_1 GND/CONFIG_3
4 3
3.3V_2 GND1
6 5
NC1 PERN3 PCIE9_L3_SSD_RX_N 23
8 7
NC2 PERP3 PCIE9_L3_SSD_RX_P 23
10 9
DAS/DSS#(OD) GND2 L3
12 11 0.22UF/6.3V 1 2 C5111
3.3V_3 PETN3 PCIE9_L3_SSD_TX_N 23
14 13 PCIE9_L3_SSD_TX_N_C 0.22UF/6.3V 1 2 C5104
3.3V_4 PETP3 PCIE9_L3_SSD_TX_P 23
16 15 PCIE9_L3_SSD_TX_P_C
3.3V_5 GND3
18 17
3.3V_6 PERN2 PCIE10_L2_SSD_RX_N 23
20 19
PCIE Wake-up. 22
NC3
NC4
PERP2
GND/CONFIG_0
21
PCIE10_L2_SSD_RX_P 23
L2
24 23 0.22UF/6.3V 1 2 C5105
NC5 PETN2 PCIE10_L2_SSD_TX_N 23
NC6 PETP2 PCIE10_L2_SSD_TX_P 23
28 27 PCIE10_L2_SSD_TX_P_C
NC7 GND4
30 29
NC8 PERN1 PCIE11_L1_SSD_RX_N 23
32 31
NC9 PERP1 PCIE11_L1_SSD_RX_P 23
34 33
NC10 GND5 L1
36 35 0.22UF/6.3V 1 2 C5107
NC11 PETN1 PCIE11_L1_SSD_TX_N 23
DEVSLP(0/3.3V) PETP1 PCIE11_L1_SSD_TX_P 23
SATA2_DEVSLP_R 40 39 PCIE11_L1_SSD_TX_P_C
NC12 GND6
42 41
NC13 PERN0/SATA-B+ PCIE12_L0_SSD_RX_P 23
44 43 PCIE12_L0_SSD_RX_P_R
NC14 PERP0/SATA-B- PCIE12_L0_SSD_RX_N 23
46 45
NC15 GND7
PCIE12_L0_SSD_RX_N_R L0
48 47 0.22UF/6.3V 1 2 C5109
NC16 PETN0/SATA-A- PCIE12_L0_SSD_TX_N 23
1 2 SL5107 50 49 PCIE12_L0_SSD_TX_N_C 0.22UF/6.3V 1 2 C5110
25,30,78 BUF_PLT_RST# 0201 PERST#(0/3.3V)/NC PETP0/SATA-A+ PCIE12_L0_SSD_TX_P 23
1 2 SL5108 NGFF_PERST# 52 51 PCIE12_L0_SSD_TX_P_C
24 CK_REQ_P1# CLKREQ#(IO)(0/3.3V)/NC GND8
0201 54 53
NGFF_CLK#
PEWAKE#(IO)(0/3.3V)/NC REFCLKN PCIE1_SSD_CLK# 24
56 55 MPCIE_SSD_CLK#_C
NC/MFG1 REFCLKP PCIE1_SSD_CLK 24
58 57 MPCIE_SSD_CLK_C
NC/MFG2 GND9
68 67
SUSCLK(32KHZ)/(0/3.3V) NC17
70 69
UX432 Delete @R5103 @C5199 R5105 MSATA_MPCIE_DET# (UX370) 3.3V_7 PEDET /NC-PCIo/GND-SATA)/CONFIG_1
72 71 MSATA_MPCIE_DET#
3.3V_8 GND10
74 73
PULL HIGH PCH Side R2302 3.3V_9 GND11
NP_NC1
NP_NC2
75
GND/CONFIG_2
SIDE1
SIDE2
MINI_PCI_75P_REMOVE8
76
77
78
79
12003-00162800
23 MSATA_MPCIE_DET# R0.1
MSATA_MPCIE_DET# 0306
J5101 chnge to 12003-00162800,
PCIE : N.C follow ME RD request
SATA : GND GND
BOM
Project Name Rev
UX432 R1.0
Title : SATA HDD & ODD

Size
Custom
GND
UX432 Add L5207 L521 1
pin5 ,pin6 不要相連, 請獨自拉GND 後在下地 VUSB Switch +5V_USB3_1
+5V_USB3_1
1
60 mils J5201
7
5
1
20150703 add USB3.0 power switch C5233 C5234 C5235
VBUS
GND3
GND1
2
20150706 add one more USB3.0 power switch 8PF/25V 10PF/25V 12PF/25V D-
2
USB_U1-_CON 3
/RF /RF /RF D+
1 2 USB_U1+_CON 4
SIG_IN+ SIG_OUT+ GND
5
4 3 +5VSUS +5V_USB3_1 GND GND GND 6
STDA_SSRX-
BOM 上09022-00110000 SIG_IN- SIG_OUT-
U3_U3RXDN1_R
STDA_SSRX+
U3_U3RXDP1_R 7
GND_DRAIN
RFL11T2SA1AR R1.1 8
STDA_SSTX-
GND4
GND2
L5201 GND U5243 0521 U3_U3TXDN1_R 9
Follow RF request add 8PF, 10PF, 12PF x1. STDA_SSTX+
09022-00110000 1 8 U3_U3TXDP1_R
GND OUT1
/RF 2 7 10
8
6
IN1 OUT2 P_GND1
3 6 11
IN2 OUT3 P_GND3
4 5 1 T5201 @ TPC16B_P16_50 12
GND 30,54,64,88 SUSC_EC# EN#/EN OC# P_GND4
U5243_OC# 13
GND P_GND2
BD82034FVJ-E2
pin5 ,pin6 不要相連, 請獨自拉GND 後在下地
1
C5232 06016-01200000 USB_CON_9P
0.1UF/6.3V GND
12013-00159500
7
5
R0.1
GND3
GND1
2
R0.1 0312
0312 J5201 12013-00150500 => 12013-00159500
USB3.0 Bus add 0.1uF , follow UX432FDX (Follow ME connector list)

1 2 GND
SIG_IN+ SIG_OUT+
4
SIG_IN- SIG_OUT-
3 USB3.0 ESD-Protection
BOM 上09022-00110000 +5V_USB3_1
RFL11T2SA1AR D5202
GND4
GND2
L5202 2 1
09022-00110000 U3_U3RXDN1_R
/RF /EMI ESD101_B1_02ELS
8
6
D5203
2 1
GND
1
C5210 C5202 CE5202 U3_U3RXDP1_R
@/RF 1 2 RN5204A C5206 22UF/6.3V 22UF/6.3V /EMI ESD101_B1_02ELS
23 U3_U3RXDP1 0OHM 100UF/6.3V
@/RF 3 4 RN5204B U3_U3RXDP1_R 0.1UF/6.3V @ D5204
23 U3_U3RXDN1 0OHM
2
hh_c0201 U3_U3RXDN1_R @ 2 1
C5208 2 1 0.1UF/6.3V @/RF 1 2 RN5205A U3_U3TXDN1_R
23 U3_U3TXDP1 0OHM
C5201 2 1 0.1UF/6.3V U3_U3TXDP1_L @/RF 3 4 RN5205B U3_U3TXDP1_R GND GND GND GND /EMI ESD101_B1_02ELS
23 U3_U3TXDN1 0OHM
U3_U3TXDN1_L U3_U3TXDN1_R R0.1 D5205
hh_c0201 0312 2 1
add 100uF reservation,
RN5204 RN5205 要改上10G302000004030 follow UX432FDX U3_U3TXDP1_R
/EMI ESD101_B1_02ELS
R1.1 GND
0528
Type_A U3 ESD 07024-00080000*1 ==> 07024-01050000*4
USB 2.0 Common choke EMI-Protection USB2.0 ESD-Protection

0.85mm 10L
U5203
1 3
CONN
+5V_USB3_1
23 USB_PP1 Via_Input1 Via_Output1
PCH
USB_PP1 USB_U1+_CON
23 USB_PN1
2 4 USB_U1+_CON
Via_Input2 Via_Output2
USB_PN1 USB_U1-_CON
I/O4
I/O3
VDD
5 9
C1_1 Via9
4
ECMF_LP1 ECMF_LP1
6 10 D5201
C2_1 Via10
ECMF_LN1 ECMF_LN1 AZC099-04SP
7 11
1
C1_2 Via11
C5203 C5204 ECMF_LP1 07024-00200200
18PF/25V 18PF/25V 8 12 /EMI
C2_2 Via12
2
ECMF_LN1
15 13
Via15 Via13 2ND:07G022006330
ECMF_LP1
16 14
Via16 Via14
ECMF_LN1
R0.1 17 R5202
Via17
3
0309
I/O2
I/O1
18 1 0Ohm 2
GND
@
C5203/C5204 20PF = 18PF, follow empass rule R1_1
USB_PP1 R5203
19 1 0Ohm 2
@
R2_1
USB_PN1
USB_U1-_CON
20
R1_2
USB_U1+_CON GND
21
R2_2
USB_U1-_CON
nbs_empass_ecmf_8p_13v_006;nbs_empass_ecmf_8p_13v_006_t;nbs_empass_ecmf_8p_13v_006_b
R0.1
temp_M08_00001 1
0309
U5203 temp_M08_000008改為temp_M08_000011
<Variant Name>
Title : USB 3.0 + 2.0 CONN.

ASUS
Custom UX432 R1.0

Dual desi gn for CN Vi and discrete
WLAN_Intel_9560
Maximum power consu mption +3V_WLAN
with both Wi-Fi and BT active
WLAN: 3.3VS --> 1050 mW ~= 320 mA 40 mils
BT : 3.3VS --> 163mW ~= 50 mA
Peak current=1.36A
1
C5301 C5302
1
C5303
R2.0 - 01
1
@ 22UF/6.3V 10UF/6.3V 0.1UF/6.3V
C5304
hh_c0603_h39 hh_c0402_h28_pw hh_c0201
0.1UF/6.3V
2
2
2
CFL & CN L Do not use clock sh ari ng mo de hh_c0201
Mount /WLANGATE if ERP Fail GND GND

+3V_WLAN
G12
G10
G11
U5301
G9
G8
G7
G6
G5
G4
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
R5389 1 2 0Ohm
+3VA_DSW G1
GND36
GND47
GND46
GND45
GND44
GND43
GND42
GND41
GND40
GND35
GND34
GND33
GND32
GND31
GND30
GND29
GND28
GND27
GND26
GND25
GND24
GND23
GND22
GND21
GND20
GND19
GND18
GND17
GND16
GND39
1 76
R5390 1 2 0Ohm UIM_POWER_SRC/GPIO1 GND15
+3VSUS +3V_WLAN 2 75 +3V_WLAN
@ UIM_POWER_SNK GND14
3 74
UIM_SWP GND13
4 73
3.3V_1 3.3V_4
5 72
3.3V_2 3.3V_3 30 mils
6 71
R0.1 GND1 GND12 R0.1
0305 40 mils 7
RESERVED1 USB_D+
70 0305
Add Wlan power gating switch, follow UX432FDX 8 69 add typical WLAN(8265) net (follow UX432FDX)
0312 ALERT# USB_D- 0410
Remove Wlan power gating switch 9 68 Remove typical WLAN(8265) net (for layout purpose)
I2C_CLK GND11
10 67
I2C_DATA RESERVED10
11 66
COEX_TXD RESERVED9
12
COEX_RXD LED1#
65 not used
13 64
COEX3 LED2# R5304
14 63 1 1 2
SYSCLK/GNSS0 W_DISABLE2#
15 62 BT_ON_C T5302 CLKREQ0
TX_BLANKING/GNSS1 GND10
16
17
RESERVED2 PCM_CLK/I2S_SCK
61
60
(1.8V/3.3V) 71.5KOhm
GND2 PCM_IN/I2S_SD_IN
18 59
RESERVED3 PCM_OUT/I2S_SD_OUT/clkreq0
19 58
RESERVED4 PCM_SYNC/I2S_WS/rf_reset_b
20 57
GND3 LPSS_UART_CTS/rgi_rsp GND
21
22
RESERVED5 LPSS_UART_TXD/rgi_dt
56
55
follow CRB
RESERVED6 LPSS_UART_RXD/bri_rsp
23 54
GND4 LPSS_UART_RTS/bri_dt
24 53
RESERVED7 UART_WAKE#(3.3V)
25 52
+3V_WLAN RESERVED8 SDIO_CLK
not used 26
GND5 SDIO_CMD
51
T5303
1 27 50
SUSCLK(32kHz)(3.3V) SDIO_DATA0
not used T5301 1 SUS_CLK_C 28
W_DISABLE1# SDIO_DATA1
49
W_Disable# G3
GND38
A07 +3V_WLAN
GND48
A08 A50
A4WP_IRQ# GND51
A09 A49
A4WP_CLK 3.3V_6
A10 A48
R5307 10KOhm A4WP_DATA 3.3V_5
1 2 W_Disable#
A11
RESERVED11 RESERVED23
A47 38.4
A12 A46
RESERVED12 RESERVED22
R5308 10KOhm A13 A45
RESERVED13 NO_CONNECT
1 2 BT_ON_C A14 A44
A15
RESERVED14
LNA_EN
REFCLK0
CLKREQ0
A43
REFCLK0
CLKREQ0
24
22
(1.8V/3.3V)
A16 A42 CLKREQ0
RESERVED15 RF_RESET_B RF_RESET_B 22 1 2
A17 A41 RF_RESET_B R5301 22Ohm
RESERVED16 RGI_RSP CNV_RGI_RSP 21
A18 A40 CNV_RGI_RSP_R
RESERVED17 RGI_DT CNV_RGI_DT 21
A19 A39 R5302 1 2 22Ohm
20 CNV_CLK_TXP WT_CLKP BRI_RSP CNV_BRI_RSP 21
A20 A38 CNV_BRI_RSP_R
20 CNV_CLK_TXN WT_CLKN BRI_DT CNV_BRI_DT 21
A21 A37
TX
20
20
CNV_L0_TXP
CNV_L0_TXN
A22
WT_D0P
WT_D0N
WGR_D1N
WGR_D1P
A36
CNV_L1_RXN
CNV_L1_RXP
20
20
RGI(1.8V)
SDIO_RESET#
RESERVED18
RESERVED19
RESERVED20
RESERVED21
A23 A35
SDIO_WAKE#
CLink_RESET
SDIO_DATA3
SDIO_DATA2
20 CNV_L1_TXP WT_D1P WGR_D0N CNV_L0_RXN 20
CLink_DATA
REFCLKN0
BRI(1.8V)
REFCLKP0
A24 A34
CLink_CLK
PEWAKE#
CLKREQ#
20 CNV_L1_TXN T5304 WT_D1N WGR_D0P CNV_L0_RXP 20
PERST#
1 A25 A33
GND37
GND49
GND50
PERn0
PERp0
PETn0
PETp0
C_P32K(3.3V_Tolerant) WGR_CLKN CNV_CLK_RXN 20
GND6
GND7
GND8
GND9
SUS_CLK_C A32
R0.1
0305
WGR_CLKP CNV_CLK_RXP 20
RX (1.24V)
G2
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A26
A27
A28
A29
A30
A31
follow UX432FDX 9560
0C012-00140200
R0.1
0305
add typical WLAN(8265) net (follow UX432FDX)
0410
Remove typical WLAN(8265) net (for layout purpose)
GND
R2.0
0716
Follow INTEL advise, R5306 => NC
+1.8VSUS
R0.1
UX391RA add 0504
1
UX432 R5305 Change to mount
0305
add typical WLAN(8265) net (follow UX432FDX) @
0410
Remove typical WLAN(8265) net (for layout purpose) R5306
+1.8VSUS 10KOhm
2
hh_r0201_h12
CNV_BRI_DT
1
R5305
R5310 1 2
20KOhm UX432 ADD R25306 Intel Feedback
24 SUS_CLK 0201
SUS_CLK_C
2
CNV_RGI_DT
1
R5309
EMI request 20KOhm
2
SUS_CLK @
1
C5314
10PF/50V
@/EMI
PCH_GPPF6: weak internal pull HIGH
2
PU INTEGRATED CNVI DISABLE
PD INTEGRATED CNVI ENABLE
Project Name Rev
UX432 R1.0
Title : USB3.0 IO BD
Size
Dept.: RD3-SYS2-EE2 Engineer: Tony1_chang
C
Main Board
R1.1 Type-C Connector +USB_C_VBUS
USB3.0/USB 2.0 Signal USB3.0 ESD-Protection 0528

Type_A U3 ESD 07024-00080000*1 ==> 07024-01050000*4, for u3 gen.2 SI improve.
07G028076030 // 07024-00960000
1
23 U3_U3RXDN4 D5402
U3_U3RXDN4
23 U3_U3RXDP4 AZ5525-01F.R7G
U3_U3RXDP4 D5403 D5407 +USB_C_VBUS +USB_C_VBUS
C5407 0.1UF/6.3V 2 1 2 1 07024-00880000
23 U3_U3TXDN4
C5406 1 2 USB_C_U3A_TXN_C
0.1UF/6.3V U3_U3RXDN4_R U3_U3RXDN3_R
23 U3_U3TXDP4 @/EMI
2
1 2 USB_C_U3A_TXP_C /EMI ESD101_B1_02ELS /EMI ESD101_B1_02ELS
D5404 D5408 J5401
2 1 2 1 A1 B1
23 U3_U3RXDN3 GND1 GND4
U3_U3RXDN3 U3_U3RXDP4_R U3_U3RXDP3_R A2 B2
23 U3_U3RXDP3 SSTXp1 SSTXp2
U3_U3RXDP3 /EMI ESD101_B1_02ELS /EMI ESD101_B1_02ELS USB_C_U3A_TXP_R A3 B3 USB_C_U3B_TXP_R
SSTXn1 SSTXn2
C5408 0.1UF/6.3V D5405 D5409 USB_C_U3A_TXN_R A4 B4 USB_C_U3B_TXN_R R0.1
23 U3_U3TXDN3 VBUS1 VBUS4 0312
C5409 1 2 0.1UF/6.3V U3_U3TXDN3_C 2 1 2 1 A5 B5
23 U3_U3TXDP3 CC1 CC2 add D5402 = 07024-00880000 reserve,
1 2 U3_U3TXDP3_C USB_C_U3A_TXN_R USB_C_U3B_TXN_R USB_C_CC1 A6 B6 USB_C_CC2 follow EMI request
Dp1 Dp2
/EMI ESD101_B1_02ELS /EMI ESD101_B1_02ELS USB_C_U2_P_C A7 B7 USB_C_U2_P_C
Dn1 Dn2
D5406 D5410 T5405 1 USB_C_U2_N_C A8 B8 USB_C_U2_N_C 1 T5406
23 USB_PN6 SBU1 SBU2
2 1 2 1 USB_C_SUB1 A9 B9 USB_C_SUB2
23 USB_PP6 VBUS2 VBUS3
USB_C_U3A_TXP_R USB_C_U3B_TXP_R A10 B10
SSRXn2 SSRXn1
/EMI ESD101_B1_02ELS /EMI ESD101_B1_02ELS U3_U3RXDN3_R A11 B11 U3_U3RXDN4_R
SSRXp2 SSRXp1
R0.1 U3_U3RXDP3_R A12 B12 U3_U3RXDP4_R
0305 GND3 GND2
GND GND
Chage PCH USB2.0 port.4 => port.6 (follow UX432FDX)
1 3
NP_NC1 P_GND1
2 4
NP_NC2 P_GND2
5
P_GND3
6
USB 2.0 ESD-Protection P_GND4
7
P_GND5
8
07024-00200200 // 07G022006330 P_GND6
D5401 USB_CON_24P
1 6 12013-00117500
USB_C_U2_P_C I/O1 I/O4 USB_C_U2_N_C
2 5
+5VSUS
GND VDD
3 4
USB_C_CC2 I/O2 I/O3 USB_C_CC1
USB3.0 Common choke RF AZC099-04SP

/EMI
GND

/RF CC Logic TI Solution
8
6
09022-00110000
EC Pin Assignment is Needed
L5403
CC2EC won't be reserved anymore.
GND4
GND2
RFL11T2SA1AR
SIG_IN- SIG_OUT-
4 3
TPC26T_50 1 T5401
SIG_IN+ SIG_OUT+
1 2
TPC26T_50 1 T5402
GND3
GND1
UFPb
TPC26T_50 1 T5403
+5VSUS
TPC26T_50 1 T5407
7
5
GND
GND
25
24
23
22
21
20
19
18
17
U5402
GND6
GND5
GND4
GND3
GND2
LD_DET#
UFP#
POL#
AUDIO#
/RF +USB_C_VBUS
8
6
09022-00110000 R0.1
L5404 0312 TPC26T_50
GND4
GND2
revise net name FAULTb => FAULT
RFL11T2SA1AR T5408 1 1 16 1 T5404
SIG_IN- SIG_OUT- FAULT# DEBUG#
4 3 FAULT 2 15
IN1_1 OUT2
3 14
SIG_IN+ SIG_OUT+ IN1_2 OUT1
1 2 4 13
IN2 CC2
5 12 USB_C_CC2
AUX GND1
1 2 6 11
1
GND3
GND1
SL5401 C5405 C5404 C5410 C5411
1
CE3501
30,52,64,88 SUSC_EC# 0201 EN CC1
USB_C_CC1 0.1UF/6.3V 10UF/6.3V 22UF/6.3V 22UF/6.3V 100UF/6.3V
REF_RTN
CHG_HI
@
2
2
2
CHG
1
C5401
REF
7
5
4.7UF/6.3V
SN1507044RVCR
7
8
9
10
GND
2
R0.1
0312
add 100uF reservation,
@/RF 3 4 RN5403B follow UX432FDX
0OHM 06050-00280000
U3_U3RXDN4 @/RF 1 2 RN5403A U3_U3RXDN4_R
0OHM +3VSUS +3VSUS
U3_U3RXDP4 U3_U3RXDP4_R
1
@/RF 3 4 RN5404B R5407
0OHM
USB_C_U3A_TXN_C @/RF 1 2 RN5404A USB_C_U3A_TXN_R 100KOhm
0OHM
2
USB_C_U3A_TXP_C USB_C_U3A_TXP_R CHG /CC_logic/TI
R5401 R5403
2
CHG_HI 10KOhm 10KOhm CHG CHG_HI Description
/CC_logic/TI /CC_logic/TI/@
GND Set CC
1
GND Delete 0 0 STD
I limit = 1.67A CHG_HI
CHG 0 1 STD
7
5
2
GND3
GND1
R5406
10KOhm 1 0 1.5A @5V
1 2 /CC_logic/TI
SIG_IN+ SIG_OUT+
1
4 3 R0.1
SIG_IN- SIG_OUT- 0305
1 1 3A @5V
Chage PCH USB2.0 port.4 => port.6 (follow UX432FDX)
RFL11T2SA1AR 0309
GND4
GND2
L5401 U5405 temp_M08_000008改為temp_M08_000011
09022-00110000
/RF
8
6
USB 2.0 Common choke EMI-Protection the stub of USB2.0 needs to be as short as possible which is shown as below
GND
GND U5405
pin5 ,pin6 不要相連, 請獨自拉GND 後在下地 1 3

USB_PP6 USB_C_U2_P_C
7
5
2 4
GND3
GND1
USB_PN6 USB_C_U2_N_C
1 2 5 9
SIG_IN+ SIG_OUT+ C1_1 Via9
ECMF_LP3 ECMF_LP3
4 3 6 10
SIG_IN- SIG_OUT- C2_1 Via10
ECMF_LN3 ECMF_LN3
7 11
1
RFL11T2SA1AR
C1_2 Via11
GND4
GND2
L5402 C5403 C5402 ECMF_LP3
09022-00110000 18PF/25V 18PF/25V 8 12
C2_2 Via12
2
/RF ECMF_LN3
8
6
15 13
Via15 Via13
ECMF_LP3
GND
16 14
Via16 Via14
@/RF 1 2 RN5401A ECMF_LN3
0OHM
U3_U3RXDN3 @/RF 3 4 RN5401B U3_U3RXDN3_R 17 R5404
0OHM Via17
U3_U3RXDP3 U3_U3RXDP3_R 18 1 0Ohm 2
@
R1_1
@/RF 1 2 RN5402A USB_PP6 R5405
0OHM <Variant Name>
U3_U3TXDN3_C @/RF 3 4 RN5402B USB_C_U3B_TXN_R 19 1 0Ohm 2
@
0OHM R2_1
U3_U3TXDP3_C USB_C_U3B_TXP_R USB_PN6 Project Name Rev
R1_2
20 UX432 R1.0
Title :
USB_C_U2_P_C
R2_2
21 BAR_****
USB_C_U2_N_C
Size
nbs_empass_ecmf_8p_13v_006;nbs_empass_ecmf_8p_13v_006_t;nbs_empass_ecmf_8p_13v_006_b
C
Date: Wednesday, July 18, 2018 Sheet of 102
temp M08 000011 54
CAPS_LOCK LED(to KB) PWR LED(to IO BD) PWR LED(to KB)
+3VS
R2.0
0718
R5640 0201 => 0402, follow ERIC request.
2.2KOhm R5640
POWER_LED# 64 POWER_LED#_R 31
R0.1 2 1
0320 R0.1
3
R5639 0201 => 0402 0308
RN5601A RN5601B
Close KB PWR LED when lid close
100KOhm 100KOhm R5639 2.2KOhm
CAP_LED_CON# 31
1 2 Q5604A Q5604B
3
4
2 5
3
EM6K1-G-T2R 30,64 LID_SW#
4
5 Q5603B
6
EM6K1-G-T2R
4
2 Q5601A 1 2
30 PWR_LED
PWR_LED PWR_LED_R
3
EM6K1-G-T2R
R5604 150KOHM C5601
2
EM6K1-G-T2R 1UF/6.3V Q5601B
R5642 5
2 Q5603A 10MOhm
4
30 CAP_LED#
5%
1
@ R5601
2
10MOhm
GND 5%
IF=5mA @
2
VF Min. 2.55V GND GND
VF Max. 3.25V PWR_LED_R

PWR_LED_R 48
GND GND GND
+5VSUS
FN LED Charger LED PWR_SWITCH C10_ LED

R0.1 R0.1
0130 R0.1 0308
1
Add main board LED 0308 Add C10 LED for debug(follow ux432fdx) R5611
0212 Add on-board pwr sw for debug(follow ux432fdx)
move to IO BD R2.0 330Ohm
0716
Remove on-board pwr sw(R5607 / SW5602) for spacing reason.
+3VA_DSW +3VSUS nbs_r0603_h24_000s
2
+3VS /PR_remove
R0.1
0320
R5602 0201 => 0402
Power_LED
2
10 mils R5658 R5659
1
+
R0.1
R5602 2.2KOhm 0130 0Ohm 0Ohm LED5604
2
FN_LED_CON# 31 Add main board LED WHITE
R5657 R5603 1 2 0212 /PR_remove @/PR_remove
move to IO BD
1
10KOhm 10KOhm 07G01570133A
hh_r0201_h12 hh_r0201_h12
R0.1
3
/PR_remove
1
Q5602B 0314
Add +3VA_DSW power net
5 EM6K1-G-T2R
2
NET CHECK
4
6
2
Q5602A
2 EM6K1-G-T2R R5608 R5610
30 FN_LED#
10KOhm 10KOhm
1
hh_r0201_h12 hh_r0201_h12
/PR_remove /PR_remove
3
GND Q5611B
5 EM6K1-G-T2R
/PR_remove
4
6
Q5611A
20,30 CPU_C10_GATE# 2 EM6K1-G-T2R
GND
/PR_remove
1
GND
GND
<Variant Name>
Title : HALL_SW
ASUS
Custom UX432 R1.0

Main Board
+1.05VSUS
+1.2V discharge +3VA +1.2V +1.05VSUS discharge +3VA +VCCST discharge
+3VA +VCCST
1
2
R5719
1
1
@ 330Ohm
100KOhm 60.4Ohm R5721 R5702 R5712
@ 100KOhm 100KOhm 330Ohm
R5723 R5722
2
@ @
hh_r0402
2
1
2
2
1
+1.0VSUS_DISCHRG
R1.1 R5723 change to 0402 0615 +1.2V_DISCHRG Q5701B +VCCST_DISCHRG
3
EM6K1-G-T2R
3
3
EM6K1-G-T2R
Q5708B 5
5 Q5706_DIS 5 Q5704B
EM6K1-G-T2R
4
Q5701A SUSC_EC
4
4
6
EM6K1-G-T2R
6
6
EM6K1-G-T2R
Q5708A 2
30,83,88 VSUS_ON Q5704A
2 2
EM6K1-G-T2R
1
25,30,58,86 PM_SUSC# 88 P_LS_VCCST_OC_RC_10
1
1
R0.1 R0.1
C10 GATE discharge 0306 R5707@=>N/A (Follow PFG_V0.8 P.521) VS discharge +1.8VS
0322
0411 R5707 330=>300 (Follow PFG_V0.8 P.521) Add VS discharge circuit, follow UX432FDX.
+3VA
+3VA +VCCIO +VCCSTG +VCCPLL_OC
1
1
R5703
R5728
330Ohm
1
100KOhm
1
@
R5709 R5708 300Ohm R5706 @
2
330Ohm R5707 330Ohm
2
100KOhm
@
2
2
2
+1.8VS_DISCHRG
3
EM6K1-G-T2R
+VCCIO_DISCHRG +VCCSTG_DISCHRG +VCCPLL_OC_DISCHRG
5 Q5722B
3
EM6K1-G-T2R EM6K1-G-T2R EM6K1-G-T2R SUSB_EC
4
Q5721B Q5721A Q5720B
6
5 2 5 EM6K1-G-T2R
SUSB_EC_R Q5722A
4
2
30,78,88 SUSB_EC#
6
EM6K1-G-T2R
1
2 Q5720A
88 P_VCCIO_EN_10
1
+3VS +5VS
R0.1
0129 +12VS discharge
1
remove GPU discharge circuit, R5701
1
p.78 already have discharge circuit. +3VA +12VS_VCCIO
R5729 330Ohm
330Ohm @
@
2
R2.0
0713
2
1
1
R5730/R5731 @=>N/A, R5731
for timing reason. R5730
330Ohm +3VS_DISCHRG +5VS_DISCHRG
100KOhm
3
2
Q5723A Q5723B
2
2 5
SUSB_EC SUSB_EC
4
+12VS_VCCIO_DISCHRG
3
EM6K1-G-T2R
5 Q5724B
PM_SUSB
4
6
EM6K1-G-T2R
2 Q5724A
20,25,30,58,88 PM_SUSB#
1
R1.1
0530
Follow UX450 add +12VS_VCCIO discharge circuit, for tplt18 timming.
<Variant Name>
Project Name Rev
UX432 R1.0
Title : DSG_Discharge
Size
B
Dept.: Engineer:
+3VA_DSW +3VA_DSW +1.05V_VCCST
R0.1
VCCST_PWRGD for PCH
0320
1
add 0ohm NC at DPWROK_EC,
1.8VSUS_PWRGD
follow UX432FDX R5896
1
R0321
R5898, R5899 0402 => 0201, 100KOhm R5803
for layout purpose R5801 1KOhm
2
100KOhm
D5804
2
1 VCCST_PWRGD_PCH 25
25,30,87 3VA_DSW_PWRGD
3
R5898 1 @ 2 0Ohm 2
3
25,30 DPWROK_EC Q5801B
EM6K1-G-T2R
BAT54AW 5
3VSUS_PWRGD 30
3VSUS_PWRGD
4
1 2
SL5805 UX432 Delete R5802 直接short
6
83 1.0VSUS_PWRGD 0201 Q5801A
EM6K1-G-T2R
SL5808 1 2 2
88 P_3VSUS_PWRGD 0201
ALL_SYSTEM_PWRGD
1
C5801
1
R5899 1 @ 2 0Ohm
83 1.8VSUS_PWRGD 0.1UF/6.3V
+3VA_DSW @
2
+3VS
D5801
1 GND GND GND
UX432UA CHECK 3VSUS_PWRGD 3
1
2
20,25,30,57,88 PM_SUSB# 10KOhm PM_SLP_SUS# 25,30
2
R5806
2
BAT54AW R5802
1
100KOhm R5897
2
SL5897 1 2 C5804 100KOhm
3
86 1.2V_PWRGD 0201 ALL_SYSTEM_PWRGD 30,80 EM6K1-G-T2R
1UF/6.3V
2
5 Q5805B hh_c0201_h14
SL5806 1 2
1
88 +VCCIO_PWRGD
1
0201 C5802 @
4
1UF/6.3V R0.1
6
EM6K1-G-T2R 0314
follow UX432FDX, PDG V0.8 P.129
2
2 Q5805A
2
1.2V_PWRGD
EMI DPWROK_EC R5804
1
GND 1MOHM
1
@ PM_SUSB#
C5807
1
2 1000PF/25V
+3VA_DSW
1
nbs_c0201_h13_000s
@/EMI C5805
6
EM6K1-G-T2R
1UF/6.3V
2
2 Q5804A
2
GND hh_c0201_h14
PLT_RST# 25,32
R5805 @
1
R0.1
0323 100KOhm
2
Add EMI CAP C5807 reserve,
follow EMI request R5808
3
EM6K1-G-T2R
1
1MOHM PM_SUSC# 25,30,57,86
5 Q5802B @
4
6
EM6K1-G-T2R
1
2 Q5802A
1
25,30 PM_RSMRST#
C5806
3
EM6K1-G-T2R <Variant Name>
R5809 1UF/6.3V
2
5 Q5804B hh_c0201_h14
10KOhm Project Name Rev
@
4
@
UX432 R1.0
2
Title : PRO_Protect
Size
Custom
+V_DCJACK A/D_DOCK_IN
PL6001
120Ohm
1 2
PL6002 Avoid
J6001 120Ohm Spike
PIN(+)
9 1 2
7
2
SPRING(-) 8 PR6007 PR6006
1 PL6003 2.2Ohm 2.2Ohm
2 120Ohm nbs_r1206_h30_000s
3 1 2
1
PC6000 PC6001 5% 5%
1
GND
4 0.1UF/25V 1UF/25V nbs_r1206_h30_000s
5 nbs_c0603_h37_000s
2
6 PL6004 @
1
120Ohm PC6008
DC_PWR_JACK_9P 1 2 10UF/25V
12033-00034900
2
R0.1
0326 GND
J0601 12033-0032400 ==> 12033-00051600,
follow ME connector list.
0417
J0601 12033-00051600 ==> 12033-00051700,
follow ME request. GND
R1.1
J0601 12033-00051700 ==> 12033-00034900 瓦數 Bead 數量
follow ME connector list.
45W & 65W 3
Need confirm
90W 4
Battery Connector
BAT_CON
R0.1
0312
follow battery RD requirement,
BAT pin swap.
J6004
1 PT6001
1
1 1 PT6002
@ PR6004 1 2 10KOhm
SIDE1 2 BAT1_IN_OC# 30,89
9 2 @
3
3 PR6002 1 2 330Ohm
4 P_SMB0_CLK 30,89 (GPC6)
4 SMB0_DAT_CLK_CON PR6001 1 2 330Ohm
5 P_SMB0_DATA 30,89
5 SMB0_DAT_BAT_CON
6
6
SIDE2 7
10 7
1
PC6005
8
8 0.1UF/25V
1
WTOB_CON_8P nbs_c0603_h37_000s
2
D6001 D6002 GND
12017-00080400 AZ5413-01F AZ5413-01F
@/EMI @/EMI Close to EC
2
07024-01460000 07024-01460000
R0.1
0327
Follow EMI request, add D6001/D6002 = 07024-01460000
<Variant Name>
Project Name Rev
UX432 R1.0
Title : DC & BAT Connector

Size
Custom
Dept.: ASUS Engineer: SS
R0.1
0319
Change CPU/GPU NUT to 13020-03760000
CPU 13020-03760000
GPU 13020-03760000
TOP 置件
TOP 置件
H6201 H6202 H6205 H6206
CT217CB176D146 CT217CB176D146 CT217CB176D146 CT217CB176D146
13020-03760000 13020-03760000 13020-03760000 13020-03760000
GND GND GND GND
FPC
R0.1
13020-04340000 0320
Add FPC NUT 13020-04340000
Barcode for EMS
TOP 置件 TOP
R0.1
H6203 H6204 0321
H6204 GND => GND_AUDIO
0402
H6204 GND_AUDIO => NC
CT217CB156D126 CT217CB156D126
13020-04340000 13020-04340000
R2.0
GND 0717
follow EMS request, add Barcode area in TOP side
0718
follow 工程技術部advise, remove Barcode area U6215
Support NUTS
R0.1
0326
Follw DXF, add support nuts=13020-04200100 *5
H6220 H6221 H6222 H6223 H6224
C217 C217 C217 C217 C217
13020-04200100 13020-04200100 13020-04200100 13020-04200100 13020-04200100
GND GND GND GND GND
R0.1
ME Hole
0319
ADD HOLE
R2.0
0717
update J hole, follow ME DXFux433_mb_7_dxf_0713.
J M L
H6208 U6202
H6207 1
1
1 2 1
CRT1878X768CRB1878X630D110 SMD433X161
2D_D169_DO130X91
GND
GND
GND GND
C D E G H I
F H6214
1
H6215
1
H6216
RT359X585CRB324X294D150
1
H6211 H6213 H6217 CRT432X472CB276D150 S12106
1 H6212 1 RCT321x487RB313X391D150
S12107
1 1 2 S12109
CT169CB130D91 RCT520X382RCB362x329D150
CT276CB256D91 S12108
2D_DO91X130_D91
GND GND GND
GND
GND
GND GND
GND
<Variant Name>
Project Name Rev
UX432 R1.0
Title : ****
Size
Dept.: Engineer:
C
Clip
R0.1
0321
Remove un-used memory shielding clip H6301~H6306
RF request
13020-02680100 R0.1
H6311 0320 +5VSUS
Add 天線夾。 AC_BAT_SYS AC_BAT_SYS AC_BAT_SYS
1
1
2
2
3
3
1
C6361 C6362 C6363 C6365
SHIELDING_3P
10PF/25V 10PF/25V 10PF/25V 10PF/25V
2
/RF /RF /RF /RF
GND GND GND GND

GND
R1.1 R1.1
0524 0524
Place at BOT side. Place at BOT side.
RF request
R0.1
0409
C6312/C6304/C6311/C6301/C6314 10PF/50V => 10UF/6.3V, for AC PI optimization.
+1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V
1
C6307 C6301 C6302 C6303 C6304 C6305 C6306
@/RF 10UF/6.3V @/RF @/RF 10UF/6.3V @/RF @/RF
EMI request
10PF/50V hh_c0402_h28_pw 10PF/50V 10PF/50V hh_c0402_h28_pw 10PF/50V 10PF/50V
2
GND GND GND GND GND GND GND
13040-00040400 13040-00850100 13040-00850100 13040-00850100 13040-00850100 R0.1
0319
U6301 H6307 H6308 H6309 H6310 add gaskey for EMI solution
SMD134X87 SMD94X57 SMD94X57 SMD94X57 SMD94X57 +VCCST
RF request
1
/EMI /EMI /EMI /EMI /EMI
1
C6326
R0.1
0.1UF/6.3V 0214
2
nbs_c0201_h13_000s FBVDDQ --->+1.35VSG R0.1
0322 0309
GND GND GND GND GND @/EMI Add C6357 +3VSUS_WLAN --->+3V_WLAN
AC_BAT_SYS AC_BAT_SYS AC_BAT_SYS

GND +1.35VSG +1.35VSG +1.35VSG
AC_BAT_SYS +3VSUS +3VSUS +3V_WLAN +5VSUS +3V_WLAN
1
C6349 C6350 C6309 C6357 C6308 C6328 C6325
C6341 1000PF/25V 1000PF/25V @/RFVGA @/RFVGA @/RFVGA @/RF C6338 C6339 C6329 @/RF C6330
0.1UF/25V 10PF/50V 10PF/50V 10PF/50V 10PF/50V 10PF/50V 10PF/50V 10PF/50V 10PF/50V 10PF/50V
/EMI /EMI
2
@/EMI @/RF @/RF @/RF @/RF
R1.1
0528 GND GND GND GND GND GND GND GND GND
C6344、C6345、C6348、C6347、C6354、C6343改0402 size上件
GND GND GND
R0.1
0409
C6312/C6304/C6311/C6301/C6314 10PF/50V => 10UF/6.3V, for AC PI optimization.
AC_BAT_SYS AC_BAT_SYS AC_BAT_SYS AC_BAT_SYS AC_BAT_SYS AC_BAT_SYS AC_BAT_SYS AC_BAT_SYS
+1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V
1
C6343 C6344 C6345 C6346 C6347 C6348 C6327
C6342 0.1UF/25V 0.1UF/25V 1000PF/50V 1000PF/25V 1000PF/50V 1000PF/50V 1000PF/25V
1
0.1UF/25V C6313 C6310 C6311 C6312 C6314 C6315 C6316 C6317
/EMI /EMI /EMI /EMI /EMI /EMI /EMI
2
@/EMI @/RF @/RF 10UF/6.3V 10UF/6.3V 10UF/6.3V @/RF @/RF @/RF
10PF/50V 10PF/50V hh_c0402_h28_pw hh_c0402_h28_pw hh_c0402_h28_pw 10PF/50V 10PF/50V 10PF/50V
2
GND GND GND GND GND GND GND GND
R1.1
0528
Add C6366 & C6367, follow EMI request.
AC_BAT_SYS AC_BAT_SYS AC_BAT_SYS AC_BAT_SYS AC_BAT_SYS
AC_BAT_SYS
AC_BAT_SYS A/D_DOCK_IN +1.8V +1.8V +1.8V +1.8V +1.8V +1.2V +1.2V +3VS_SSD
1
1
C6351 C6352 C6353 C6354 C6355
1
C6356
1
1000PF/25V 1000PF/25V 1000PF/25V 0.1UF/25V 1000PF/25V C6366 C6367 C6321 C6318 C6319 C6320 C6322 C6323 C6324 C6331
1000PF/25V @/RF @/RF @/RF @/RF @/RF @/RF @/RF @/RF
/EMI /EMI /EMI /EMI /EMI 1000PF/25V 1000PF/25V
2
2
/EMI 10PF/50V 10PF/50V 10PF/50V 10PF/50V 10PF/50V 10PF/50V 10PF/50V 10PF/50V
2
/EMI /EMI
2
GND GND GND GND GND GND
GND GND
R0.1
0319
EMI: AC_BAT_SYS reserve 0.1uF/25V*6 on TOP side. <Variant Name>
Project Name Rev
UX432 R1.0
Title : EMI RF reserve CAP

Size
Custom
R0.1
0222
Camera USB move Camera to p.64
R0.1
3 4 RN6404B 0227
0Ohm D6403
add lid sw net & change pin define
23 USB_PP5 USB_PN5_CON_R 1 2 UX432 IO BD 0302

Remove fan net & change pin define
USB_PP5_CON_R
IECS0305C040FR
1. USB2.0 Type.A 0306
J6401 40PIN -> 60PIN
2. USB2.0 CR add TP, FP
4
@ 0315
@/EMI
90Ohm/100Mhz
L6403
3. Audio jack J6401 60PIN -> 50PIN, follow connector list.
0316
D6402 4. PWR LED J6401 Pin define change, for layout purpose.
remove p.9/12 GND, for layout purpose.
1
23 USB_PN5
1 2 RN6404A
USB_PN5_CON_R
USB_PP5_CON_R 1 2 CHG LED 0320
J6401 PIN.5 GND_AUDIO=> GND
0Ohm
IECS0305C040FR
5. PWM Fan J6401 PIN.4 SENSE_A_HP_Con=> GND_AUDIO
J6401 PIN.46 GND_AUDIO=> SENSE_A_HP_Con
@/EMI
6. IR camera 0323
J6401 50PIN -> 40PIN
7. LID SW 0323
J6401 vertical swap, for layout purpose.
0326
J6401 => 12016-00622000, follow ME connector list
J6401 pin define change, for layout purpose.
0329 Touch Panel I2C Pull High
Camera DMIC R0.1
J6401 Pin define chage for EMI request.
0330 R0.1
0222 J6401 Pin.5 add GND_AUDIO, audio vender advise. 0306
move DMIC from p.45 to p.64 move TP from p.45 to p.64
Codec DMIC 0312
remove TP
R6411 1 0Ohm 2
36 DMIC_DATA
R6410 1 0Ohm 2 DMIC_DATA_R
36 DMIC_CLK GND_AUDIO GND
DMIC_CLK_R
PCH MIC
R6409 1 0Ohm 2 @/DMIC_PCH R0.1
22 DMIC_DATA_PCH 0320
R6412 1 0Ohm 2 @/DMIC_PCH
22 DMIC_CLK_PCH NC PCH DMIC path
12016-00622000
BTOB_CON_40P
J6401
Camera POWER
41
44
AUDIO_GND AUDIO_GND
1 40
38 AC_HP_L_R 1 40 MIC2_L/RING2_Con 38
+3VS +3V_CAM 2 39
38 AC_HP_R_R 2 39
SIDE1
SIDE4
SL6403 3 38
3 HP 38 MIC2_R/SLEEVE_Con 38
4 37
1 2
30 mils 5
4 37
36
0603 5 36 SENSE_A_HP_Con 38
6 35
6 35
C6404 7 CAM 34 R0.1
1
C6405 USB_PN5_CON_R
2
7 34 0305
4.7UF/6.3V 0.1UF/6.3V DMIC_CLK_R 8 DMIC 33 USB_PP5_CON_R
8 33 Camera USB2.0 port.6=>port.5 (follow UX432FDX)
@ DMIC_DATA_R 9 32
1
9 32
2
10 U2 31 USB_PN2_X1
10 31
11 30 USB_PP2_X1
11 30
GND GND 12 29 R0.1
30,56 LID_SW# 12 29 USB_PP4 23 0305
13 CR 28
30,52,54,88 SUSC_EC# 13 28 USB_PN4 23 CR USB2.0 port.5=>port.4 (follow UX432FDX)
R1.1 14 27
USB 2.0 Typr-A R0.1 0528
follow EMI request L6401
56 POWER_LED#
15
14 LED 27
26
CHG_LED#
CHG_FULL_LED#
30
30
0221 15 26
1 2 16 25
Short-land change to 0 ohm. 09G09X090400 => 09G092090100 Camera IR LED=0.72A 40 mils +5VS
F6402 1.5A/32V
16 25 +3V_CAM
+5VS_IR 17 24 30 mils CAM=> 500mA
17 24
USB2.0+LED=1A 70 mils 18 23
+5VSUS
SIDE2
SIDE3
18 23 +3VS 40 mils CR + TP + FP=> 1A
1 2 RN6401A 19 22
0Ohm 19 22
20 21
20 21 +3VA
@ 30 mils LID=> 500mA
23 USB_PN2
42
43
/EMI
3
USB_PN2_X1
L6401
90Ohm/100Mhz
23 USB_PP2
2
USB_PP2_X1 R0.1
0306
3 4 RN6401B FP Power REFERENCE UX331 GND GND GND_AUDIO GND
0Ohm
@ +3VS
TP Reset Control
1
C6406 C6403
R0.1 4.7UF/6.3V 0.1UF/6.3V
0306 @ @/EMI
move TP from p.45 to p.64
2
0312
remove TP
R0.1
FP RST# / CS# 0322
Add Q6401 隔漏電,漏到 +3VS POWER

FP connector move FP connector to MB
0409
J6402 pin define swap for ME request.
R0.1
0312
Move gating circuit to IO BD +5VS
0322
Move gating circuit to MB, FOLLOW UX331UN
0329 +3VS
R6401 @=>N/A, R6405 N/A=>@, follow VC X705FD
Q6401B 12018-00214300
R6401 EM6K1-G-T2R FPC_CON_8P
5
0Ohm /SPI_FP
8
2 1 8
21 FP_SPI_RST# 7 10
3 4
FP_SPI_RST#_R 7 SIDE2
FP_SPI_RST#_R 6
21 FP_MOSI 6
5
R6405 21 FP_SPI_INT 5
+3VS 4
0Ohm 21 FP_MISO 4
3
2 @/SPI_FP 1 3
FP_CS#_R 2 9
21 FP_CLK 2 SIDE1
1
1
1
2
R6402 J6402
R6403
1MOhm
10KOhm
+5VS
@ @
2
1
GND GND
Q6401A
EM6K1-G-T2R
2
/SPI_FP
21 FP_CS#
FP_CS# FP_CS#_R
6 1
UX432 EMI UX433 EMI R0.1

0306
ESD-Protection REFERENCE UX331
+5VSUS +3VS +5VS_IR +3VA DMIC_CLK_R FP_SPI_RST#_R

D6401
1 6
1
C6409
1
1 6
2 5
1
1
C6407 C6408 22PF/25V FP_MISO FP_CS#_R D6404
C6401 C6402 2 5
0.1UF/25V 0.1UF/25V @/EMI 3 4 FP_SPI_INT TVL020101AB0
3 4
2
0.1UF/6.3V 0.1UF/6.3V @/EMI @/EMI FP_MOSI FP_CLK @/EMI
2
nbs_c0201_h13_000s nbs_c0201_h13_000s AZ2115-05C

@/EMI @/EMI @/EMI
2
GND GND GND GND GND
R0.1
0319
dd 0.1UF, 22PF for EMI solution reservation
<Variant Name>
Title : IO_SA
TA HDD
Engineer:
MB TO IO BD ASUS Tony1_chang
USB2.0 Port * 1, USB CR, Hall sensor , LEDs C UX432 R1.0

R0.1
0302
PWM Fan +5VS

add fan connector
0308
J6705 12G171030043==> 12G171030043
1
C6709
2.2UF/6.3V
2
+3VS
GND
2
R6711
100KOhm
12G171030043
J6705
4 6
4 SIDE2
1
3
30 FAN1_PWM 3
2
1
2
1 SIDE1
5
Check pin define
30 FAN1_TACH
WtoB_CON_4P
GND GND
<Variant Name>
Project Name Rev
UX331UA_UN R2.1
Title : Micro SD_RTL_RTS5226S

Size
Dept.: Engineer:
ASUSTeK COMPUTER INC. NB2EE1 RD1-RD3EE2
B
+1.8VSG_AON
1
R7003
10KOhm U7001 N17S-LG
/VGA +1.8VSG_AON
U7001A
2
1/14 PCI_EXPRESS
75,78 DGPU_PEX_RST#
Place Near BALLS Place Near GPU Place Between GPU and Power source.
1
R7001
10KOhm
1
R7004 /VGA AA22
PEX_DVDD1 +PEX_VDD
1MOhm AC7 AB23
2
PEX_RST_N PEX_DVDD2
AC24
1
/VGA DGPU_PEX_RST# C7001 C7002 C7003 C7004 C7005 C7006 C7007 C7008
PEX_DVDD3
AC6 AD25 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 10UF/6.3V 10UF/6.3V
2
PEX_CLKREQ_N PEX_DVDD4
CLK_REQ_VGA_GPU# AE26 /VGA /VGA /VGA /VGA /VGA @/VGA @/VGA /VGA
PEX_DVDD5
2
AE8 AE27
24 CLK_PCIE_PEG_PCH PEX_REFCLK PEX_DVDD6
AD8
24 CLK_PCIE_PEG#_PCH PEX_REFCLK_N
AC9
PEX_TX0
PCIEG_TXP0 AB9
PEX_TX0_N
PCIEG_TXN0
AG6
PEX_RX0
PCIEG_RXP0 AG7 AA10
PEX_RX0_N PEX_HVDD1 +PEX_HVDD
PCIEG_RXN0 AA12
PEX_HVDD2
AB10 AA13
1
C7010 C7011 C7012 C7013 C7014 C7015 C7016 C7017
PEX_TX1 PEX_HVDD3
CX7005 2 1 0.22UF/6.3V PCIEG_TXP1 AC10 AA16 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 10UF/6.3V 10UF/6.3V
PEX_TX1_N PEX_HVDD4
PCIENB_RXN0 CX7001 2 1 0.22UF/6.3V PCIEG_TXN0 PCIEG_TXN1 AA18 /VGA /VGA /VGA /VGA /VGA /VGA @/VGA @/VGA
PEX_HVDD5
2
PCIENB_RXP0 /VGA PCIEG_TXP0 AF7 AA19
PEX_RX1 PEX_HVDD6
CX7006 2 1 0.22UF/6.3V /VGA PCIEG_RXP1 AE7 AA20
23 PCIEG_RXP[3:0] PEX_RX1_N PEX_HVDD7
PCIENB_RXN1 CX7002 2 1 0.22UF/6.3V PCIEG_TXN1 PCIEG_RXN1 AA21
23 PCIEG_RXN[3:0] PEX_HVDD8
PCIENB_RXP1 /VGA PCIEG_TXP1 AD11 AB22
23 PCIENB_RXP[3:0] PEX_TX2 PEX_HVDD9
CX7007 2 1 0.22UF/6.3V /VGA PCIEG_TXP2 AC11 AC23
23 PCIENB_RXN[3:0] PEX_TX2_N PEX_HVDD10
PCIENB_RXN2 CX7003 2 1 0.22UF/6.3V PCIEG_TXN2 PCIEG_TXN2 AD24
PEX_HVDD11
PCIENB_RXP2 /VGA PCIEG_TXP2 AE9 AE25
PEX_RX2 PEX_HVDD12
CX7008 2 1 0.22UF/6.3V /VGA PCIEG_RXP2 AF9 AF26
PEX_RX2_N PEX_HVDD13
PCIENB_RXN3 CX7004 2 1 0.22UF/6.3V PCIEG_TXN3 PCIEG_RXN2 AF27
PEX_HVDD14
PCIENB_RXP3 /VGA PCIEG_TXP3 AC12 +1.8VSG_Main +PEX_HVDD
PEX_TX3
/VGA PCIEG_TXP3 AB12
PEX_TX3_N
PCIEG_TXN3
AG9
PEX_RX3
PCIEG_RXP3 AG10 SL7001
PEX_RX3_N
PCIEG_RXN3 1 2
AB13 0603
PEX_TX4
AC13
PEX_TX4_N Place Near GPU @/VGA
AF10
PEX_RX4
AE10 +1.8VSG_Main
PEX_RX4_N
AD14
PEX_TX5
AC14 AA8
PEX_TX5_N PEX_PLL_HVDD1
AA9
PEX_PLL_HVDD2
AE12
1
Q7001 C7020
PEX_RX5
R0.1 AF12 0.1UF/10V
S1 0126 PEX_RX5_N
1 D1 6 /VGA
PEX_CLKREQ# 24 follow UX432FN net name:
2
CLK_REQ_VGA_GPU# CLK_REQ_VGA# ==> PEX_CLKREQ# AC15
PEX_TX6
AB15
PEX_TX6_N
2 G2 5
78 DGPU_PWROK_1.8
G1 AG12
PEX_RX6
AG13
PEX_RX6_N
3 D2 4
S2 AB16
PEX_TX7
AC16
PEX_TX7_N
EM6K1-G-T2R /VGA
AF13
PEX_RX7
AE13
PEX_RX7_N
AD17
PEX_TX8
AC17
PEX_TX8_N
AE15
PEX_RX8
AF15
PEX_RX8_N
AC18
PEX_TX9
AB18
PEX_TX9_N
AG15
PEX_RX9
AG16
PEX_RX9_N
PEX LANES 15 - 4 ARE DEFEATURED

AB19
PEX_TX10
AC19
PEX_TX10_N
AF16
PEX_RX10
AE16
PEX_RX10_N
AD20
PEX_TX11
AC20
PEX_TX11_N
AE18
PEX_RX11
AF18
PEX_RX11_N
AC21
PEX_TX12
AB21
PEX_TX12_N
AG18
PEX_RX12
AG19
PEX_RX12_N
AD23
PEX_TX13
AE23
PEX_TX13_N
AF19
PEX_RX13
AE19
PEX_RX13_N
AF24
PEX_TX14
AE24
PEX_TX14_N
AE21
PEX_RX14
AF21
PEX_RX14_N
AG24
PEX_TX15
AG25
PEX_TX15_N
AG21
PEX_RX15
AG22
PEX_RX15_N
R7002
2.49KOhm
AF25 1 1% 2
PEX_TERMP
PEX_TERMP /VGA
N17S-LG-A1 /VGA
Project Name Rev
UX331UA_UN R2.1
Title : VGA PCIE

Size
Dept.: RD3_EE2 Engineer: Andy_Ceng
C
GPU MEMORY INTERFACE
U7001B
2/14 FBA
72 FBA_D[0:63]
E18
FBA_D0
FBA_D0 F18
FBA_D1
FBA_D1 E16
FBA_D2
FBA_D2 F17
FBA_D3
FBA_D3 D20
FBA_D4
FBA_D4 D21
FBA_D5
FBA_D5 F20
FBA_D6
FBA_D6 E21
FBA_D7
FBA_D7 E15
FBA_D8
FBA_D8 D15
FBA_D9
FBA_D9 F15
FBA_D10
FBA_D10 F13
FBA_D11
FBA_D11 C13
FBA_D12
FBA_D12 B13
FBA_D13
FBA_D13 E13
FBA_D14
FBA_D14 D13
FBA_D15
FBA_D15 B15
FBA_D16
FBA_D16 C16
FBA_D17
FBA_D17 A13
FBA_D18
FBA_D18 A15
FBA_D19
FBA_D19 B18
FBA_D20
FBA_D20 A18
FBA_D21
FBA_D21 A19
FBA_D22
FBA_D22 C19
FBA_D23
FBA_D23 B24
FBA_D24
FBA_D24 C23
FBA_D25
FBA_D25 A25
FBA_D26
FBA_D26 A24
FBA_D27
FBA_D27 A21
FBA_D28
FBA_D28 B21
FBA_D29
FBA_D29 C20
FBA_D30
FBA_D30 C21
FBA_D31
FBA_D31 R22
FBA_D32 FBA_CMD[0:15] 72
R24 C27
FBA_D32
FBA_D33 T22
FBA_D33 FBA_CMD0
C26 FBA_CMD0
Add for GDDR5
FBA_D34 FBA_CMD1
FBA_D34 R23 E24 FBA_CMD1
FBA_D35 FBA_CMD2
FBA_D35 N25 F24 FBA_CMD2 +1.35VSG
FBA_D36 FBA_CMD3
FBA_D36 N26 D27 FBA_CMD3
FBA_D37 FBA_CMD4
FBA_D37 N23 D26 FBA_CMD4 1 2
FBA_D38 FBA_CMD5
FBA_D38 N24 F25 FBA_CMD5 FBA_CMD14 R7101 10KOhm
FBA_D39 FBA_CMD6
FBA_D39 V23 F26 FBA_CMD6 /VGA
FBA_D40 FBA_CMD7
FBA_D40 V22 F23 FBA_CMD7 1 2
FBA_D41 FBA_CMD8
FBA_D41 T23 G22 FBA_CMD8 FBA_CMD30 R7102 10KOhm
FBA_D42 FBA_CMD9
FBA_D42 U22 G23 FBA_CMD9
FBA_D43 FBA_CMD10 /VGA
FBA_D43 Y24 G24 FBA_CMD10 1 2
FBA_D44 FBA_CMD11
FBA_D44 AA24 F27 FBA_CMD11 FBA_CMD13 R7103 10KOhm
FBA_D45 FBA_CMD12
FBA_D45 Y22 G25 FBA_CMD12
FBA_D46 AA23 G27 FBA_CMD13 1 2
FBA_D47 FBA_CMD14
FBA_D47 AD27 G26 FBA_CMD14 FBA_CMD29 R7104 10KOhm
FBA_D48 FBA_CMD15 FBA_CMD[16:31] 72
FBA_D48 AB25 M24 FBA_CMD15
FBA_D49 AD26 M23 FBA_CMD16
FBA_D50 FBA_CMD17
FBA_D50 AC25 K24 FBA_CMD17
FBA_D51 FBA_CMD18
FBA_D51 AA27 K23 FBA_CMD18
FBA_D52 FBA_CMD19
FBA_D52 AA26 M27 FBA_CMD19
FBA_D53 FBA_CMD20
FBA_D53 W26 M26 FBA_CMD20
FBA_D54 FBA_CMD21
FBA_D54 Y25 M25 FBA_CMD21
FBA_D55 FBA_CMD22
FBA_D55 R26 K26 FBA_CMD22
FBA_D56 FBA_CMD23
FBA_D56 T25 K22 FBA_CMD23
FBA_D57 FBA_CMD24
FBA_D57 N27 J23 FBA_CMD24
FBA_D58 FBA_CMD25
FBA_D58 R27 J25 FBA_CMD25
FBA_D59 FBA_CMD26
FBA_D59 V26 J24 FBA_CMD26
FBA_D60 FBA_CMD27
FBA_D60 V27 K27 FBA_CMD27
FBA_D61 FBA_CMD28
FBA_D61 W27 K25 FBA_CMD28
FBA_D62 FBA_CMD29
FBA_D62 W25 J27 FBA_CMD29
FBA_D63 FBA_CMD30
FBA_D63 J26 FBA_CMD30
FBA_CMD31
B19 FBA_CMD31
72 FBA_DBI[7..0] FBA_CMD32
D19 F22 1 T7101
FBA_DQM0 FBA_CMD34
FBA_DBI0 D14 J22 DEBUG0 1 T7102
@
FBA_DQM1 FBA_CMD35
FBA_DBI1 C17 DEBUG1 @
FBA_DQM2
FBA_DBI2 C22
FBA_DQM3
FBA_DBI3 P24
FBA_DQM4
FBA_DBI4 W24
FBA_DQM5
FBA_DBI5 AA25
FBA_DQM6
FBA_DBI6 U25
FBA_DQM7
FBA_DBI7
72 FBA_EDC[7..0]
E19
FBA_DQS_WP0
FBA_EDC0 C15
FBA_DQS_WP1
FBA_EDC1 B16 D24
FBA_DQS_WP2 FBA_CLK0 FBA_CLK0 72
FBA_EDC2 B22 D25
FBA_DQS_WP3 FBA_CLK0_N FBA_CLK0# 72
FBA_EDC3 R25 N22
FBA_DQS_WP4 FBA_CLK1 FBA_CLK1 72
FBA_EDC4 W23 M22
FBA_DQS_WP5 FBA_CLK1_N FBA_CLK1# 72
FBA_EDC5 AB26
FBA_DQS_WP6
FBA_EDC6 T26
FBA_DQS_WP7
FBA_EDC7
F19 D18
FBA_DQS_RN0 FBA_WCK01 FBA_WCK01 72
C14 C18
FBA_DQS_RN1 FBA_WCK01_N FBA_WCK01# 72
A16 D17
A22 D16
P25 T24
W22 U24
AB27 V24
T27 V25 +1.8VSG_Main
L7101
30Ohm/100Mhz
F16 1 2
FB_PLL_AVDD1
FB_PLLAVDD
P22
1
C7101 C7102 C7103 C7104 /VGA
2
FB_PLL_AVDD2
0.1UF/6.3V 0.1UF/6.3V 0.1UF/6.3V 22UF/6.3V
H22 /VGA /VGA /VGA /VGA
1
FB_REFPLL_AVDD
2
Place Near Balls Place Near GPU
T7103 1 D23
FB_VREF
@ FB_VREF
N17S-LG-A1
/VGA
Project Name Rev
UX331UA_UN R2.1
Title : VGA VRAM I/F

Size
Custom
+1.35VSG
+1.35VSG FBA_D[0:63] U7202
71
71
FBA_CLK0
FBA_CLK0#
FBA_CLK0
71 FBA_D[0:63]
FBA_D[0:63] U7201 Samsung, GDDR5, 03008-00050000 71
71
FBA_CLK1
FBA_CLK1#
M2
DQ7/DQ31 VDDQ1
B1
Micron, GDDR5, 03008-00050400

M2 B1 M4 B3
2
20161215 Byte SWAP FBA_D63 FBA_D57
DQ7/DQ31 VDDQ1 DQ6/DQ30 VDDQ2
R7231 20161216 bitd SWAP FBA_D7 FBA_D4 M4 B3 FBA_D62 FBA_D56 N2 B12
80.6Ohm 20170301 bit SWAP FBA_D6 FBA_D5 N2 B12 20170301 SWAP FBA_D61 FBA_D59 N4 B14
/VGA FBA_D5 FBA_D7 N4 B14 FBA_D60 FBA_D63 T2 D1
71 FBA_CMD[0:15] DQ4/DQ28 VDDQ4 71 FBA_CMD[16:31] DQ3/DQ27 VDDQ5
1% FBA_D4 FBA_D2 T2 D1 FBA_D59 FBA_D58 T4 D3
1
FBA_D3 FBA_D6 T4 D3 FBA_D58 FBA_D61 U2 D12
FBA_CLK0# FBA_D2 FBA_D1 U2 D12 FBA_D57 FBA_D60 U4 D14
FBA_D1 FBA_D0 U4 D14 FBA_D56 FBA_D62 M13 E5
FBA_D0 FBA_D3 M13 E5 FBA_D55 FBA_D49 M11 E10
FBA_D15 FBA_D8 M11 E10 FBA_D54 FBA_D54 N13 F1
FBA_CLK1 FBA_D14 FBA_D11 N13 F1 20170301 SWAP FBA_D53 FBA_D48 N11 F3
71 FBA_DBI[7..0] DQ13/DQ21 VDDQ11 DQ12/DQ20 VDDQ12
N11 F3 T13 F12
2
FBA_D13 FBA_D9 FBA_D52 FBA_D52
FBA_DBI0 R7232 FBA_D12 FBA_D10 T13 F12 FBA_D51 FBA_D50 T11 F14
FBA_DBI1 80.6Ohm FBA_D11 FBA_D12 T11 F14 FBA_D50 FBA_D55 U13 G2
FBA_DBI2 /VGA FBA_D10 FBA_D13 U13 G2 FBA_D49 FBA_D51 U11 G13
FBA_DBI3 1% FBA_D9 FBA_D15 U11 G13 FBA_D48 FBA_D53 F13 H3
1
FBA_DBI4 FBA_D8 FBA_D14 F13 H3 FBA_D47 FBA_D40 F11 H12
FBA_DBI5 FBA_CLK1# FBA_D23 FBA_D17 F11 H12 FBA_D46 FBA_D42 E13 K3
FBA_DBI6 FBA_D22 FBA_D23 E13 K3 20170301 SWAP FBA_D45 FBA_D45 E11 K12
FBA_DBI7 FBA_D21 FBA_D19 E11 K12 FBA_D44 FBA_D44 B13 L2
FBA_D20 FBA_D16 B13 L2 FBA_D43 FBA_D47 B11 L13
71 FBA_EDC[7..0] DQ19/DQ11 VDDQ21 DQ18/DQ10 VDDQ22
FBA_D19 FBA_D20 B11 L13 FBA_D42 FBA_D46 A13 M1
FBA_EDC0 FBA_D18 FBA_D22 A13 M1 FBA_D41 FBA_D43 A11 M3
FBA_EDC1 FBA_D17 FBA_D18 A11 M3 FBA_D40 FBA_D41 F2 M12
FBA_EDC2 FBA_D16 FBA_D21 F2 M12 FBA_D39 FBA_D38 F4 M14
FBA_EDC3 FBA_D31 FBA_D25 F4 M14 FBA_D38 FBA_D36 E2 N5
FBA_EDC4 FBA_D30 FBA_D29 E2 N5 20170301 SWAP FBA_D37 FBA_D39 E4 N10
FBA_EDC5 FBA_D29 FBA_D26 E4 N10 FBA_D36 FBA_D37 B2 P1
FBA_EDC6 FBA_D28 FBA_D31 B2 P1 FBA_D35 FBA_D32 B4 P3
FBA_EDC7 FBA_D27 FBA_D24 B4 P3 FBA_D34 FBA_D33 A2 P12
FBA_D26 FBA_D28 A2 P12 FBA_D33 FBA_D34 A4 P14
FBA_D25 FBA_D27 A4 P14 FBA_D32 FBA_D35 T1
DQ24/DQ0 VDDQ32 VDDQ33
FBA_D24 FBA_D30 T1 T3
VDDQ33 VDDQ34
T3 T12
VDDQ34 VDDQ35
T12 T14
VDDQ35 VDDQ36
T14
VDDQ36
J5
A12/A13
J5 FBA_CMD25 K4 C5
A12/A13 A0/A10/A8/A7 VDD1
FBA_CMD9 K4 C5 FBA_CMD22 K5 C10
A0/A10/A8/A7 VDD1 A1/A9/A11/A6 VDD2
FBA_CMD6 K5 C10 FBA_CMD23 K10 D11
A1/A9/A11/A6 VDD2 A3/BA3/A5/BA1 VDD3
FBA_CMD7 K10 D11 FBA_CMD20 K11 G1
A3/BA3/A5/BA1 VDD3 A2/BA0/A4/BA2 VDD4
FBA_CMD4 K11 G1 FBA_CMD19 H10 G4
FBA_CMD3 H10 G4 FBA_CMD17 H11 G11
FBA_CMD1 H11 G11 FBA_CMD18 H5 G14
A4/BA2/A2/BA0 VDD6 A6/A11/A1/A9 VDD7
FBA_CMD2 H5 G14 FBA_CMD27 H4 L1
A6/A11/A1/A9 VDD7 A7/A8/A0/A10 VDD8
FBA_CMD11 H4 L1 FBA_CMD26 L4
A7/A8/A0/A10 VDD8 VDD9
FBA_CMD10 L4 L11
VDD9 VDD10
L11 L14
VDD10 VDD11
L14 D4 P11
VDD11 71 FBA_WCK45 WCK23/WCK01 VDD12
D4 P11 D5 R5
71 FBA_WCK23 WCK23/WCK01 VDD12 71 FBA_WCK45# WCK23#/WCK01# VDD13
D5 R5 R10
71 FBA_WCK23# WCK23#/WCK01# VDD13 VDD14
R10 P4
VDD14 71 FBA_WCK67 WCK01/WCK23
P4 P5
71 FBA_WCK01 WCK01/WCK23 71 FBA_WCK67# WCK01#/WCK23#
P5 A1
71 FBA_WCK01# WCK01#/WCK23# VSSQ1
A1 R2 A3
VSSQ1 EDC0/EDC3 VSSQ2
R2 A3 FBA_EDC7 R13 A12
EDC0/EDC3 VSSQ2 EDC1/EDC2 VSSQ3
FBA_EDC0 R13 A12 FBA_EDC6 C13 A14
FBA_EDC1 C13 A14 FBA_EDC5 C2 C1
20161215 SWAP FBA_EDC2 C2 C1 FBA_EDC4 C3
EDC3/EDC0 VSSQ5 VSSQ6
FBA_EDC3 C3 P2 C4
VSSQ6 DBI0#/DBI3# VSSQ7
P2 C4 FBA_DBI7 P13 C11
DBI0#/DBI3# VSSQ7 DBI1#/DBI2# VSSQ8
FBA_DBI0 P13 C11 FBA_DBI6 D13 C12
FBA_DBI1 D13 C12 FBA_DBI5 D2 C14
20161215 SWAP FBA_DBI2 D2 C14 FBA_DBI4 E1
DBI3#/DBI0# VSSQ10 VSSQ11
FBA_DBI3 E1 E3
VSSQ11 VSSQ12
E3 E12
VSSQ12 VSSQ13
E12 G3 E14
VSSQ13 CAS#/RAS# VSSQ14
G3 E14 FBA_CMD28 L3 F5
CAS#/RAS# VSSQ14 RAS#/CAS# VSSQ15
FBA_CMD12 L3 F5 FBA_CMD31 F10
RAS#/CAS# VSSQ15 VSSQ16
FBA_CMD15 F10 H2
VSSQ16 VSSQ17
H2 J3 H13
VSSQ17 CKE# VSSQ18
J3 H13 FBA_CMD30 J11 K2
CKE# VSSQ18 CK# VSSQ19
FBA_CMD14 J11 K2 FBA_CLK1# J12 K13
CK# VSSQ19 CK VSSQ20
FBA_CLK0# J12 K13 FBA_CLK1 M5
CK VSSQ20 VSSQ21
FBA_CLK0 M5 M10
VSSQ21 VSSQ22
M10 G12 N1
VSSQ22 WE#/CS# VSSQ23
G12 N1 FBA_CMD16 L12 N3
WE#/CS# VSSQ23 CS#/WE# VSSQ24
FBA_CMD0 L12 N3 FBA_CMD21 N12
CS#/WE# VSSQ24 VSSQ25
FBA_CMD5 N12 N14
VSSQ25 VSSQ26
N14 R7206 1 /VGA 2 121Ohm J13 R1
VSSQ26 ZQ VSSQ27
R7202 1 /VGA 2 121Ohm J13 R1 FBA_GDDR5_ZQ3 J10 R3
ZQ VSSQ27 SEN VSSQ28
FBA_GDDR5_ZQ1 J10 R3 FBA_SEN3 R4
SEN VSSQ28 VSSQ29
R4 R11
VSSQ29 VSSQ30
R11 J2 R12
VSSQ30 RESET# VSSQ31
J2 R12 R7207 /VGA 1KOhm FBA_CMD29 J1 R14
RESET# VSSQ31 MF VSSQ32
R7204 /VGA 1KOhm FBA_CMD13 J1 R14 1 2 FBA_MF3 U1
1 2 FBA_MF1
MF VSSQ32
U1 MF=0 non-Mirror VSSQ33
U3
MF=0 non-Mirror VSSQ33
VSSQ34
U3
U12
VSSQ34
VSSQ35
U12
U14
VSSQ35 VSSQ36
U14 A5
VSSQ36 Vpp/NC
A5 U5
Vpp/NC Vpp/NC1
U5 B5
Vpp/NC1 VSS1
B5 A10 B10
VSS1 VREFD1 VSS2
A10 B10 U10 D10
VREFD1 VSS2 VREFD2 VSS3
U10 D10 G5
VREFD2 VSS3 VSS4
G5 G10
VSS4 VSS5
G10 H1
VSS5 VSS6
H1 H14
VSS6 VSS7
H14 K1
VSS7 VSS8
K1 1 2 J14 K14
VSS8 VREFC VSS9
1 2 J14 K14 C7202 FBA_VREFC1
820PF/50V L5
VREFC VSS9 VSS10
C7201 FBA_VREFC0
820PF/50V L5 L10
VSS10 /VGA VSS11
L10 P10
/VGA VSS11 VSS12
P10 J4 T5
VSS12 ABI# VSS13
J4 T5 FBA_CMD24 T10
ABI# VSS13 VSS14
FBA_CMD8 T10
VSS14
K4G80325FB-HC28
K4G80325FB-HC28 /VGA
/VGA
+1.35VSG +1.35VSG
2
R7210 R7212
549Ohm 549Ohm
/VGA @/VGA
1
+1.35VSG
SL7201
1 2
FBA_VREFC0
0603
FBA_VREFC1 RF 1.5PF
@
1
R7211 R7214 R7213 R7215 C7210 C7211 C7212 C7213 C7214 C7215 C7216 C7217 C7218 C7219 C7220 C7260
1.33KOhm
/VGA
931Ohm
/VGA
1.33KOhm
@/VGA
931Ohm
@/VGA
Place Under DRAM 1UF/6.3V
/VGA
1UF/6.3V
/VGA
1UF/6.3V
/VGA
1UF/6.3V
/VGA
1UF/6.3V
/VGA
1UF/6.3V
/VGA
1UF/6.3V
/VGA
1UF/6.3V
/VGA
1UF/6.3V
/VGA
1UF/6.3V
/VGA
1UF/6.3V
/VGA
1.5PF/25V
@/RF
2
1
1
Q7201A Q7201B
3
2 /VGA 5 /VGA
75 MEM_VREF_CTL
MEM_VREF_CTL
1
C7221 C7222 C7223 C7224 C7225 C7226 C7227 C7228 C7229 C7230 C7231 C7232 C7233
Ensure at least 2 GND vias
2
1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V
/VGA /VGA /VGA /VGA /VGA /VGA /VGA /VGA @/VGA /VGA /VGA /VGA @/VGA and 2 power vias
1
for each capacitor
2
1
1
C7240 C7241 C7242 C7243 C7244 C7245 C7246 C7247 C7248 C7249 C7250 C7253
2
1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 22UF/6.3V
+1.35VSG /VGA /VGA /VGA /VGA /VGA /VGA /VGA /VGA @/VGA /VGA /VGA /VGA
1
2
2
1
1
C7261
1UF/6.3V
C7264
1UF/6.3V
C7262
1UF/6.3V
C7265
1UF/6.3V
C7263
1UF/6.3V
Place Under DRAM U7201 Place Under GPU
/VGA /VGA /VGA /VGA /VGA
Place Near GPU
2
+1.35VSG
1
C7266
1UF/6.3V
C7270
1UF/6.3V
C7268
1UF/6.3V
C7269
1UF/6.3V
C7267
1UF/6.3V
Place Under DRAM U7202
/VGA /VGA /VGA /VGA /VGA
2
Project Name Rev
UX331UA_UN R2.1
Title : VGA VRAM

Size
D
U7001J
4/14 IFPAB
DVI HDMI DP
SL/DL
AC4
IFPA_L3_N
TXC/TXC AC3
IFPA_L3
AA6
IFPAB_RSET
TXD0/0 Y3
IFPA_L2_N
Y4
IFPA_L2
+1.8VSG_AON +1.8VSG_AON +1.8VSG_AON
TXD1/1 AA2
IFPA_L1_N
W7 AA3 U7001K
IFPAB_PLLVDD IFPA_L1
10/14 MISC2
AA1
2
TXD2/2
1
IFPA_L0_N
AB1 R7401 R7403 R7405 R7407 R7409 R7411 R7413 R7415 R7417
IFPA_L0
100KOhm 100KOhm 100KOhm 100KOhm 100KOhm 100KOhm 100KOhm 100KOhm 100KOhm
D12 1% 1% 1% 1% 1% 1% @/VGA @/VGA @/VGA
ROM_CS_N
AA5 @/VGA @/VGA @/VGA /VGA /VGA /VGA
2
IFPA_AUX_SDA_N
1
AA4 B12
IFPA_AUX_SCL ROM_SI
A12 ROM_SI
ROM_SO
D1 C12 ROM_SO
STRAP0 ROM_SCLK
AB4 STRAP0 D2 ROM_SCLK STRAP0 ROM_SO STRAP3
IFPB_L3_N STRAP1
TXC AB5 STRAP1 E4
IFPB_L3 STRAP2
STRAP2 E3
STRAP3
STRAP3 D3
STRAP4
W6 TXD0/3 AB2 STRAP4 C1 STRAP1 ROM_SI STRAP4
IFP_IOVDD1 IFPB_L2_N STRAP5 NC GM108
AB3 STRAP5
IFPB_L2
Y6
IFP_IOVDD2
TXD1/4 AD2 D11 STRAP2 ROM_SCLK STRAP5

IFPB_L1_N RESERVED BUFRST_N
AD3
IFPB_L1
2
1
1
R7402 R7404 R7406 R7408 R7410 R7412 R7414 R7416 R7418
TXD2/5 AD1 100KOhm 100KOhm 100KOhm 100KOhm 100KOhm 100KOhm 100KOhm 100KOhm 100KOhm
IFPB_L0_N
AE1 1% 1% 1% @/VGA @/VGA 1% 1% 1% 1%
IFPB_L0
/VGA /VGA /VGA /VGA /VGA /VGA /VGA
2
1
1
AD5
IFPB_AUX_SDA_N
AD4
IFPB_AUX_SCL
N17S-LG-A1
IFPAB (DEFEATURED 0N GM108) /VGA
N17S-LG-A1
/VGA
XTAL 27MHZ
TXC-07G010262700//HOSONIC-07G010952701
+1.8VSG_Main
L7401 1 2 30Ohm/100Mhz
+GPC_PLLVDD
/VGA
C7403 C7404 C7406
2
0.1UF/6.3V 0.1UF/6.3V 0.1UF/6.3V
/VGA /VGA /VGA
1
1
R7425
0Ohm U7001L
/VGA Near pin under GPU 9/14 XTAL_PLL
GM108
2
L6
XS_PLLVDD PLLVDD
M6
SP_PLLVDD
F11
GPCPLL_AVDD NC
L7402 1 2 30Ohm/100Mhz N6
VID_PLLVDD NC
@/VGA +VID_PLLVDD
1
C7401 C7402 C7405
2
22UF/6.3V 4.7UF/6.3V 0.1UF/6.3V
@/VGA /VGA /VGA
1
2
2
A10 C10
XTAL_SSIN XTAL_OUTBUFF
27M_SSC XTALOUT_BUF
C11 B10
1
XTAL_IN XTAL_OUT
R7419 DGPU_XIN DGPU_XOUT
1
10KOhm N17S-LG-A1 R7426
Plcae Near GPU Near pin under GPU /VGA /VGA 10KOhm
2
/VGA
2
R7427 R7421
2
0Ohm 1KOhm
/VGA
/VGA R0.1
0314
1
GPU 27MHZ XTAL add R7427=0OHM.
X7401
27MHZ W/O external SS
/VGA 07G010262700
1 3
DGPU_XIN_R XTALOUT_C
1
C7407 C7408
4
15PF/25V 15PF/25V
/VGA /VGA
2
Project Name Rev
UX331UA_UN R2.1
Title : VGA STRAP_XT

AL
Size
Custom
SL7501
1 2
0402 +1.8VSG_AON
DGPU_MOS_GATE
R7502
U7001M 1 0Ohm 2
DGPU_PEX_RST# 70,78
+1.8VSG_AON 8/14 MISC1 @/VGA
+1.8VSG_AON
1
R7501 I2C for thermal sensor
10KOhm +1.8VSG_AON
/VGA D9 R7513 1 /VGA 2 2.2KOhm Q7501
I2CS_SCL
D8 VGA_SMB1_CLK R7514 1 /VGA 2 2.2KOhm
2
I2CS_SDA S1
A6 VGA_SMB1_DAT 1 D1 6 R7504 1 2 10KOhm
OVERT SMB1_CLK_EC 28,30,79,80
OVERT# AE2 A9 R7515 1 /VGA 2 2.2KOhm VGA_SMB1_CLK GC6_GPU_EVENT# /VGA
TS_VREF I2CC_SCL
B9 I2CC_SCL R7516 1 /VGA 2 2.2KOhm R7505 1 2 10KOhm
I2CC_SDA
I2CC_SDA 2 G2 5 1.8VSG_Main_EN /VGA
DGPU_MOS_GATE G1 DGPU_MOS_GATE R7506 1 2 10KOhm
E12 VGA_ALERT#_L /VGA
THERMDN
T7501 1 C9 R7517 1 /VGA 2 2.2KOhm 3 D2 4 R0.1 R7507 1 2 100KOhm
I2CB_SCL 28,30,79,80 SMB1_DAT_EC 0129
@ F12 C8 I2CB_SCL R7518 1 /VGA 2 2.2KOhm S2 VGA_SMB1_DAT DGPU_PD# /VGA
THERMDP I2CB_SDA follow UX432FN net name:
T7502 1 I2CB_SDA SMB1_DAT ==> SMB1_DAT_S R7508 1 2 10KOhm
@ EM6K1-G-T2R /VGA SMB1_CLK ==> SMB1_CLK_S NVDD_PSI /VGA
0308
follow UX432FDX net name: R7509 1 2 10KOhm
SMB1_DAT_S ==>SMB1_DAT_EC GC6_PEX_RST_MON# @/VGA
SMB1_CLK_S ==>SMB1_CLK_EC
R7503 1 2 10KOhm
GPU_PEX_RST_HOLD# @/VGA
C6 R0.1
GPIO0 NVDD_PWM_VID 91 0129
B2
GPIO1 NV_GC6_FB_EN 78 Follow UX331UN design
D6 NV_GC6_FB_EN R0.1
GPIO2
C7 GC6_GPU_EVENT# 0308 R7522 R7510 1 2 10KOhm
GPIO3 change net name,
F9 1 0Ohm 2 NV_GC6_FB_EN /VGA
GPIO4 1.8VSG_Main_EN 78 follow pwr new circuit.
A3 1.8VSG_Main_EN 1 T7504 Q7502 @/VGA DGPU_PD# R7512 1 2 100KOhm
GPIO5
A4 FRM_CLK# @ MEM_VREF_CTL /VGA
GPIO6 NVDD_PSI 91 S1
B6 NVDD_PSI 1 D1 6
GPIO7 VGA_ALERT_P# 79
E9 1 T7503 VGA_ALERT#_L
GPIO8
F8 MEM_VDD_CTL @
GPIO9
C5 VGA_ALERT#_L 2 G2 5
GPIO10 MEM_VREF_CTL 72
E7 MEM_VREF_CTL DGPU_MOS_GATE G1 DGPU_MOS_GATE
GPIO11
D7
GPIO12 DGPU_PD# 78,89
B4 DGPU_PD# 3 D2 4
GPIO13 32 GPU_THERM#_GPU
B3 S2 OVERT#
GPIO14
C3
GPIO15
D5 EM6K1-G-T2R /VGA
GPIO16
D4 GC6_PEX_RST_MON#
GPIO17
C2
GPIO18
F7 1 T7505
GPIO19
E6 3D VISION @
GM108
GPIO20
C4
GPIO21 D7501
A7
I2CA_SDA GPIO22
B7 1
I2CA_SCL GPIO23
GPU_PEX_RST_HOLD# 3
GPU_EVENT# 21
GC6_GPU_EVENT# 2
N17S-LG-A1
/VGA BAT54CW
/VGA
U7001N
3/14 JTAG
T7507 AE5
JTAG_TCK
T7508 1 AE6
JTAG_TDI
T7509 1
@ AF6
JTAG_TDO
T7510 1
@ AD6
JTAG_TMS
1
@ AG4
JTAG_TRST_N
JTAG_TRST_VGA @ AD9
NVJTAG_SEL
NVJTAG_SEL
1
R7520 R7521
10KOhm 10KOhm
/VGA /VGA
2
N17S-LG-A1
/VGA
Project Name Rev
UX331UA_UN R2.1
Title : VGA GPIO_THERM

Size
Custom
+NVVDD +1.35VSG +NVVDD +NVVDD +NVVDD
U7001C U7001D U7001F U7001G

11/14 NVVDD 12/14 FBVDDQ 7/14 VDDS 6/14 XVDD
K10
VDD1
K12 B26
VDD2 FBVDDQ1
K14 C25 L11 G1 N4
VDD3 FBVDDQ2 VDDS1 XVDD1 XVDD36
K16 E23 L17 G2 N5
K18 E26 M14 G3 N7
L13 F14 P10 G4 P3
L15 F21 P12 G5 P4
M10 G13 P16 G6 P6
M12 G14 P18 G7 R1
M16 G15 T14 H3 R2
M18 G16 U11 H4 R3
N11 G18 U17 H6 R4
N13 G19 J1 R5
VDD13 FBVDDQ12 XVDD11 XVDD46
N15 G20 J2 R6
N17 G21 J3 R7
P14 L22 J4 T1
R11 L24 J5 T2
R13 L26 GM108 J6 T3
R15 M21 J7 T4
R17 N21 RSVD F4 K1 T5
VDD20 FBVDDQ23 VDDS_SENSE XVDD18 XVDD53
T10 R21 F3 K2 T6
VDD21 FBVDDQ24 RSVD GNDS_SENSE XVDD19 XVDD54
T12 T21 K3 T7
T16 V21 K4 U3
T18 W21 N17S-LG-A1 K5 U4
U13 H24 K6 U6
VDD25 FBVDDQ15 /VGA XVDD23 XVDD58
U15 H26 K7 V1
V10 J21 L3 V2
V12 K21 L4 V3
V14 M1 GM108 V4
VDD29 XVDD27 XVDD62
V16 M2 V5
VDD30 XVDD28 XVDD63
V18 M3 V6
VDD31 XVDD29 XVDD64
M4 RSVD
V7
XVDD30 XVDD65
M5 W1
XVDD31 XVDD66
M7 W2
XVDD32 XVDD67
F2 N1 W3
VDD_SENSE NVDD_VCCSENSE 91 XVDD33 XVDD68
F1 N2 W4
GND_SENSE NVDD_VSSSENSE 91 XVDD34 XVDD69
N3
XVDD35
R0.1
0308
change net name,
follow pwr new circuit.
N17S-LG-A1 N17S-LG-A1
/VGA /VGA
U7001H
13/14 GND +1.35VSG
A2 K11 D22 R7601 1 /VGA 2 40.2Ohm 1%

GND1 GND59 FB_CAL_PD_VDDQ
AB17 K13 FB_CAL_PD
GND6 GND60
AB20 K15
GND7 GND61
AB24 K17 C24 R7602 1 /VGA 2 40.2Ohm 1%
GND8 GND62 FB_CAL_PU_GND
AC2 L10 FB_CAL_PU
GND10 GND63
AC22 L12
GND11 GND64
AC26 L14 B25 R7603 1 /VGA 2 60.4Ohm 1%
GND12 GND65 FB_CAL_TERM_GND
AC5 L16 FB_CAL_TERM
GND13 GND66
AC8 L18
GND14 GND67
AD12 L5
GND15 GND71
AD13 M11
GND16 GND72
A26 M13
GND2 GND73
AD15 M15
GND17 GND74
AD16 M17
GND18 GND75
AD18 N10
GND19 GND76
AD19 N12
GND20 GND77
AD21 N14 N17S-LG-A1
GND21 GND78
AD22 N16
GND22 GND79 /VGA
AE11 N18
GND23 GND80
AE14 P11
GND24 GND81
AE17 P13
GND25 GND82
AE20 P15
GND26 GND83
AB11 P17
GND4 GND84
AF1 P23
GND27 GND86
AF11 P26
GND28 GND87
AF14 R10
GND29 GND89
AF17 R12
GND30 GND90
AF20 R14
GND31 GND91
AF23 R16
GND32 GND92
AF5 R18
GND33 GND93
AF8 T11
GND34 GND94
AG2 T13
GND35 GND95
AG26 T15
GND36 GND96
AB14 T17
GND5 GND97
B1 U10
GND37 GND98
B11 U12
GND38 GND99
B14 U14
GND39 GND100
B17 U16
GND40 GND101
B20 U18
B23
GND41 GND102
U23
U7001I
5/14 NC +1.8VSG_Main Place Under GPU Place Near GPU
GND42 GND104
B27 U26
GND43 GND105
B5 V11 GM108 U7001E +1.8VSG_Main
GND44 GND107
B8 V13 AA14 14/14 VDD18
+1.8VSG_AON
GND45 GND108 NC1 PEX_PLLVDD
E11 V15 AA15
GND46 GND109 NC2 PEX_PLLVDD
E14 V17 AB6 G8
GND47 GND110 NC3 VDD18_1
E17 Y2 AB8 G9
GND48 GND111 NC4 PEX_SVDD_3V3 VDD18_2
E2 Y23 AD10 G10
1
C7601 C7602 C7603 C7604
2
GND49 GND112 NC5 1V8_AON1
E20 Y26 AD7 G12 0.1UF/6.3V 0.1UF/6.3V 1UF/6.3V 4.7UF/6.3V
GND50 GND113 NC6 1V8_AON2
E22 Y5 AE22 /VGA /VGA /VGA /VGA
1
GND51 GND114 NC7 PEX_TSTCLK*
2
E25 AA7 AE3
GND52 GND3 NC8
E5 AB7 AE4
GND53 GND9 NC9
E8 AF2
GND54 NC10
AF22
NC11 PEX_TSTCLK
AF3
NC12
AF4 +1.8VSG_AON
NC13
AG3
OPTIONAL GND: NC14
D10
NC15
E10
NC16
F10
NC17
XVDD AREA F5
1
C7605 C7606 C7607 C7608
2
NC18
H2 P2 F6 0.1UF/6.3V 0.1UF/6.3V 1UF/6.3V 4.7UF/6.3V
GND55 GND85 NC19 MLS_REF0
H5 P5 W5 /VGA /VGA /VGA /VGA
1
GND58 GND88 NC20
2
L2 U2 N17S-LG-A1
GND68 GND103
U5
GND106 GM108 COMPATIBLE DESIGNS MUST /VGA
LEAVE NC PINS FLOATING EXCEPT
FOR THOSE SHOWN

PCB ADR/CMD
N17S-LG-A1
PWR REFERENCE
/VGA
H23 L23
GND56 GND69
H25 L25
GND57 GND70
N17S-LG-A1
/VGA
Project Name Rev
UX331UA_UN R2.1
Title : VGA PWR_GND

Size
C
NVVDD POWER AND DECOUPLING
Place Under GPU

+NVVDD
1
C7701 C7702 C7703 C7704 C7705 C7706 C7707 C7708 C7709 C7710 C7711
4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V
@/VGA /VGA @/VGA @/VGA @/VGA /VGA /VGA /VGA /VGA /VGA /VGA
2
Place Near GPU
1
C7714 C7715 C7716 C7713 C7718 C7719
10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V
/VGA /VGA /VGA /VGA /VGA /VGA
2
1
1
C7723 C7724
22UF/6.3V 22UF/6.3V
/VGA @/VGA
2
Place Under GPU
+NVVDD
1
C7731 C7732 C7733 C7734 C7735 C7736
4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 1UF/6.3V 1UF/6.3V
/VGA @/VGA @/VGA /VGA /VGA /VGA
2
1
1
C7737 C7738 C7739 C7712 C7741 C7742 C7743 C7744
10UF/6.3V
/VGA
10UF/6.3V
/VGA
10UF/6.3V
/VGA
10UF/6.3V
/VGA
10UF/6.3V
/VGA
10UF/6.3V
/VGA
10UF/6.3V
/VGA
22UF/6.3V
/VGA
Place Near GPU
2
2
Project Name Rev
UX331UA_UN R2.1
Title : VGA PWR_CAP

Size
B
+1.8VSG_AON +PEX_VDD
R0.1
+1.05VSUS 0129
+1.0VSUS# ==> +1.05VSUS
+1.8VSG_Main
+12VSUS +12VSUS Q7803 +PEX_VDD
NTMFS4C09NBT1G
S
+1.8VSG_Main
U7802
R1.1
D
17 R7810 R7811 3 1
GND4
16 100KOhm 100KOhm
GND3
G
15 C7801 /VGA /VGA /VGA
GND2
2
1 14
1
1000PF/50V C7802
2
+1.8VSUS VIN1_1 VOUT1_2
2 13 /VGA 22UF/6.3V
VIN1_2 VOUT1_1
3 12 /VGA
ON1 CT1
2
1.8VSG_Main_EN_3.3 4 11 1 2 +PEX_VDD_Gate
3
+5VSUS VBIAS GND1
5 10 Q7807B
ON2 CT2
6 9 1 2 5
1
DGPU_PWR_EN_3.3 EM6K1-G-T2R C7804
+1.8VSUS VIN2_1 VOUT2_2
7 8 C7803 +PEX_VDD_DSG /VGA 0.01UF/25V
4
VIN2_2 VOUT2_1
22PF/25V Q7807A /VGA
2
SN1409049DPUR /VGA EM6K1-G-T2R
/VGA 2 /VGA
PEX_VDD_EN_3.3
1
+1.8VSG_AON
1
R7812
100KOhm
/VGA R0.1
+1.8VSG_AON 0315
2
+FBVDDQ_PWRGD add pull-high, follow UX331
2
R7836
DGPU_PD#
10KOhm
/VGA
1
DGPU_PWROK 21
R0.1 +FBVDDQ_PWRGD 93
0308
remove DGPU_PD_P#, follow PWR circuit DGPU_FBVDDQ_EN 93
DGPU_PD# 75,89
+1.8VSG_AON
20
19
18
U7801
DGPU_PWROK
+1.35VSG_PGD
FBVDDQ_EN3.3
+3VSUS
2
R0.1
0129 R7835
follow UX432FN net name:
GC6_FB_EN_3.3 ==> GC6_FB_EN 10KOhm
Q7808B R0.1 /VGA
3
SL7801 EM6K1-G-T2R 0129 1 17
follow UX432FN net name: VDD GC6_FB_EN_3.3 GC6_FB_EN 21,30
1
2 1 5 /VGA DGPU_RST# ==> GPU_RST# 2 16
30 DGPU_LIMIT 0201 25,30,51 BUF_PLT_RST# BUF_PLT_RST# NV_GC6_FB_EN NV_GC6_FB_EN 75
3 15
4
21 GPU_RST# DGPU_RST# CK_REQ_VGA# DGPU_PWROK_1.8 70
@/VGA 4 14
70,75 DGPU_PEX_RST# DGPU_PEX_RST# PEX_VDD_EN_3.3
5 13 PEX_VDD_EN_3.3 R0.1
21 DGPU_PWR_EN# DGPU_PWR_EN# NVVDD_PGD NVDD_PWRGD 91
6 12 0308
30,57,88 SUSB_EC# SUSB_EC# NVDD_EN_3.3 NVVDD_EN_3.3 91 change net name,
7 11
DGPU_PWR_EN_3.3 GND follow pwr new circuit.
+1.8VSG_MAIN_PGD
DGPU_PWR_EN_3.3
+1.8VSG_MAIN_EN
+1.8VSG_MAIN_3.3
0309
change net name,
1
R7801 follow pwr(2100) new circuit.
100KOhm +1.8VSG_Main
/VGA
1
SLG4U41606V R7831
8
9
10
/VGA 10KOhm
/VGA
Power Bott on
2
(ER or PR 後移除)
75 1.8VSG_Main_EN
1.8VSG_Main_PGD
1.8VSG_Main_EN_3.3
1
R7832
1
R7804 1MOhm
+5VSUS 100KOhm /VGA
/VGA
2
Discharge
2
1
R7813
330Ohm
@
+PEX_VDD
2
1
1
LED7801 R7822
+
WHITE 22Ohm
@ /VGA
2
2
+PEX_VDD_DISCHRG
6
Q7808A
6
Q7810A 2 EM6K1-G-T2R
2 EM6K1-G-T2R +PEX_VDD_DSG /VGA
1
DGPU_PWR_EN_3.3 @
Project Name Rev
UX331UA_UN R2.1
Title : VGA_GPU_Power
Size
C
+5VSUS_TEMPSNS +5VSUS_TEMPSNS
R7905
4.3KOHM
1 2
CH3:VRAM or other,TR7902 Close to U7201&U7202
TR7902 R7907
47KOHM 0Ohm
R7901 1% 12KOHM 1 @ 2
VGA_ALERT_P# 75
2 1 2 1
R7906 @
C7902 3.6KOhm C7901 47PF/50V
1.0 ~ 3.56V 1 2 1 2
2 1
0.1UF/25V GND
GND GND SL7901 @
U7901 2 1
0402 SMB1_DAT_EC 28,30,75,80
CH2:APL/AMD CPU chip,TR7901 Close to U0301 1 8
ALT/ADD SDA
TS_ADDR_10 2 7 TS_SDA_30 SL7902 @
TM3 SCL
105C @ 5k TR7901 TS_TM3_10 3 6 TS_SCL_30 2 1
40C @ 51k TM2 GND 0402 SMB1_CLK_EC 28,30,75,80
47KOHM TS_TM2_10 4 5
TM1 VCC5 +5VSUS_TEMPSNS
R7903 2 1% 1 12KOHM
2 1 UP1905AMA8 @ R0.1
C7903 GND C7905 47PF/50V 0129
follow UX432FN net name:
0.1UF/25V 1 2 SMB1_DAT ==> SMB1_DAT_S
1.0 ~ 3.56V SMB1_CLK ==> SMB1_CLK_S
0308
2 1 GND follow UX432FDX net name:
SMB1_DAT_S ==>SMB1_DAT_EC
SMB1_CLK_S ==>SMB1_CLK_EC
GND
+5VSUS +5VSUS_TEMPSNS
R7902 2 1% 1 12KOHM R7904 1 2 2.2Ohm

91 P_GPU_VRM_TEMP_SENSOR_10
105C @ 5k C7906
40C @ 51k
1
0.1UF/25V C7908
1.0 ~ 3.56V 1UF/6.3V
2 1
2
GND
R1.1
GND 0530
Follow thermal RD request, UMA thermal sensor 上件。
Address Selection Table

Address 0x7E 0x7C 0x7A 0x78 0x76 0x74 0x72 0x70
R7905 10k 1.5k 2k 3.6k 3.9k 4.3k 5.1k 6k
R7906 Open 8.2k 6.2k 6.8k 4.7k 3.6k 2.7k 2k
<Variant Name>
Project Name Rev
UX331UA_UN R2.1
Title : VGA_sensor
Size
Dept.: RD3_EE2 Engineer: Andy_Cheng
B
WHL IMVP8 (1) Power [For CPU]
+3VS_PWR PR8031
4.7OHM
1 2
81 P_IMVP8_TEMP_10
nbs_r0603_h39_000s
1
PR8032 PC8014 PC8013
1
49.9KOhm 1UF/6.3V 4.7UF/6.3V
nbs_c0603_h37_000s
2
2
2
PR8034
89 P_IMVP8_PSYS_INFO
2MOhm
81 P_IMVP8_VINSEN_R_10
1 2 Psys FF=0.8V ER20180508
33W - 5.1K / 10G212510114030
1
45W - 5.36K / 10G 212536114030
1
PR8035 PR8005 PC8001
P_IMVP8_PWM1_10 81
65W - 5.36K / 10G 212536114030
1
133KOhm PC8015 5.36KOhm 0.01UF/50V
90W - 4.02K / 10G 2124021140300 P_IMVP8_PWM2_10 81
0.01UF/50V /ADP
120W - 4.02K / 10G 212402114030
2
2
2
P_IMVP8_PWM4_10 81
2
P_IMVP8_PWM5_10 81
PR8009
1.5KOHM PSL8012
1 2 1 2
0402 ALL_SYSTEM_PWRGD 30,58
P_IMVP8_SUMC_10
@
81 P_VCCSA_CS5_10
PR8001
1.5KOHM
1
1 2 PR8030
P_IMVP8_SUMB_10 0Ohm
2
81 P_VCCGT_CS4_10
PR8002
1.5KOHM
P_IMVP8_STB_10 81
1 2 PR8025
P_IMVP8_SUMA_10 0Ohm
1 2
SMB1_CLK_EC 28,30,75,79
P_IMVP8_VINSEN_10
1 2
P_IMVP8_VDD33_10
SMB1_DAT_EC 28,30,75,79
P_IMVP8_PWM1_10
P_IMVP8_PWM2_10
P_IMVP8_PWM4_10
P_IMVP8_PWM5_10
81 P_VCCCORE_CS2_10
P_IMVP8_TEMP_10
P_IMVP8_PSYS_10
P_VCCSA_CS5_10
PR8026 PR8027
PR8003 0Ohm 100Ohm
1.5KOHM 1 2
IMVP8_VRHOT# 8,30
1 2
P_IMVP8_SUMA_10
VCCCORE IMVP8_PWRGD 25,30
LL=1.8mohm +VCCST
81 P_VCCCORE_CS1_10
P_IMVP8_SVID_VCC_10 2 1
PU8001
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
PR8024
PJ8004 PR8060 R1.0 1Ohm 5%
GND7
GND6
GND5
GND4
GND3
GND2
GND1
CS5
VIN_SEN
PSYS
TEMP
VDD33
PWM1
PWM2
PWM3
PWM4
PWM5
+VCCCORE 0417
1
SHORT_PAD 100Ohm nbs_r0603_h24_000s
1
follow PWR request
1 2 1 2 1 34
1
PR8004 PR8022 PR8023 PC8011
CS4 EN
nbs_r0201_h12_000s PC8016 1.43KOhm P_IMVP8_CS4_10 2 33 P_IMVP8_EN_10 45.3Ohm 100Ohm 0.1UF/25V
CS3 PE
2
@ 560PF/50V 3 32 P_IMVP8_PE_10
CS2 STB
2
P_IMVP8_CS2_10 4 31 P_IMVP8_STB_10 高度ISSUE
2
CS1 SCL_P PR20180713
P_VCCCORE_VCCSENSE_L_50OHM P_IMVP8_CS1_10 5 30 P_IMVP8_SCL_10
VDIFFA SDA_P
PSL8003 P_IMVP8_VDIFFA_10 6 29 P_IMVP8_SDA_10
VFBA VRHOT#
1 2 P_IMVP8_VFBA_10 7 28 P_IMVP8_VR_HOT#_10 PSL8011 PR8021
6 P_VCCCORE_VCCSENSE_50OHM 0402 VOSENA WHL U42 Setting VRRDY
P_VCCCORE_VCCSENSE_R_50OHM 8 27 1 2 10Ohm
VORTNA ALT# 0402 P_SVID_ALERT#_50OHM_X2 6
@ P_VCCCORE_VSSSENSE_R_50OHM 9 26 P_SVID_ALERT#_50OHM_X1
VDIFFB SDIO P_SVID_DATA_50OHM_X2 6
P_IMVP8_VDIFFB_10 10 25 P_SVID_DATA_50OHM_X1 1 2
@ 1 2
1
VFBB SCLK P_SVID_CLK_50OHM_X2 6
PC8003 R1.0 P_IMVP8_VFBB_10 11 24 P_SVID_CLK_50OHM_X1
0417 VOSENB VDD18
1000PF/50V P_VCCGT_VCCSENSE_R_50OHM 12 23 P_IMVP8_VDD18_10 PR8020
1
follow PWR request VORTNB IREF
CSSUMC
CSSUMA
CSSUMB
VOSENC
VORTNC
1
VDIFFC
PR8006 P_VCCGT_VSSSENSE_R_50OHM P_IMVP8_IREF_10 49.9Ohm
IMONC
IMONA
IMONB
2
VFBC
PSL8004 PC8017 2.43KOhm
1 2 220PF/50V
1
0402
2
6 P_VCCCORE_VSSSENSE_50OHM
1
PR8017 PC8010
13
14
15
16
17
18
19
20
21
22
MP2969BGQJT-Z
@ 61.9KOhm 1UF/6.3V
P_VCCSA_VCCSENSE_R_50OHM
P_VCCSA_VSSSENSE_R_50OHM
2
PJ8005
P_VCCCORE_VSSSENSE_L_50OHM PR8061
2
SHORT_PAD 100Ohm
GT
P_IMVP8_CORE_IOUT_10
1 2 1 2
P_IMVP8_GT_IOUT_10
P_IMVP8_SA_IOUT_10
LL=3.1mohm
P_IMVP8_VDIFFC_10
nbs_r0201_h12_000s
P_IMVP8_SUMC_10
P_IMVP8_SUMA_10
P_IMVP8_SUMB_10
P_IMVP8_VFBC_10
@
PJ8006 PR8062
+VCCGT SHORT_PAD 100Ohm
1 2
1 2 nbs_r0201_h12_000s
@
P_VCCGT_VCCSENSE_L_50OHM PSL8005
1 2
6 P_VCCGT_VCCSENSE_50OHM 0402
@
1
PC8004
1000PF/50V
2
PSL8006
1 2
6 P_VCCGT_VSSSENSE_50OHM 0402
@
P_VCCGT_VSSSENSE_L_50OHM PR8063 R1.0
100Ohm 0417
follow PWR request
1 2
1
1 2
1
nbs_r0201_h12_000s PC8018 PR8038 PR8014 PC8007 PR8015 PC8008 PR8016 PC8009
PJ8007 100PF/50V 8.2KOhm 53.6KOhm 390PF/50V 120KOhm 220PF/50V 620KOhm 39PF/50V
2
SHORT_PAD
2
@
2
PJ8008 PR8064
+VCCSA SHORT_PAD 100Ohm
1 2 1 2
nbs_r0201_h12_000s
SA
@
LL=10.3mohm
IA GT SA
P_VCCSA_VCCSENSE_L_50OHM PSL8007 ICCMAX=70A ICCMAX=31A ICCMAX=6A
1 2
6 P_VCCSA_VCCSENSE_50OHM 0402
@
1
PC8006
1000PF/50V
2
PSL8008
1 2
6 P_VCCSA_VSSSENSE_50OHM 0402
@
PJ8009
P_VCCSA_VSSSENSE_L_50OHM PR8065
SHORT_PAD 100Ohm
1 2 1 2
nbs_r0201_h12_000s
@
<Variant Name>
Project Name Rev
DESIGN_IP R1.0
Title : PW_Whisky Lake IMVP8_(1)

Size
Dept.: ASUS Power Team Engineer: SS
A2
WHL IMVP8 (2) Power [For CPU]
PSP8101 @
SHORT_PAD
P_IMVP8_VINSEN_R_10 80
2 1
+3VS_PWR AC_BAT_SYS AC_BAT_SYS

+3VS_PWR
1
PCI8101 PC8101 PCI8103 PC8106
1
PC8167 + PCE8101 PC8105 + PCE8102
PC8102 10UF/25V 10UF/25V 10UF/25V 10UF/25V
1
0.1UF/25V 15UF/25V PC8107
1
0.1UF/25V 15UF/25V
1UF/6.3V nbs_c0805_h57_000s nbs_c0805_h57_000s nbs_c3528_h83_000s 1UF/6.3V nbs_c0805_h57_000s nbs_c0805_h57_000s nbs_c3528_h83_000s
2
3528_2.1mm 3528_2.1mm
2
PU8101 PU8103
14
14
MP86903-CGLT-Z MP86903-CGLT-Z
1
20
VCC
Imax = 71A 20
VCC
Imax = 31A
VIN2
VIN1
VIN2
VIN1
PWM與CS隔20mil PSL8111
PC8189
0.1UF/25V PWM與CS隔20mil PSL8104
PC8108
0.1UF/25V
80 P_IMVP8_PWM1_10
2
0402
1
P_IMVP8_CORE1_PWM1_10
15
18
PWM BST
21
P_IMVP8_CORE1_BST_30 1 2 PL8101
+VCCCORE 80 P_IMVP8_PWM4_10
2
0402
1
P_IMVP8_GT_PWM1_10
15
18
PWM BST
21
P_IMVP8_GT_BST_30 1 2 PL8103
+VCCGT
80 P_VCCCORE_CS1_10 CS 80 P_VCCGT_CS4_10 CS
@ 2 nbs_c0603_h37_000s 0.24UH @ 2 nbs_c0603_h37_000s 0.24UH
SW1 SW1
16 3 1 2 16 3 1 2
80 P_IMVP8_STB_10 SYNC SW2 SYNC SW2
17 4 P_IMVP8_CORE1_LX_S P_IMVP8_STB_10 17 4 P_IMVP8_GT_LX_S
80 P_IMVP8_TEMP_10 VTEMP/FLT SW3 VTEMP/FLT SW3
1
PC8104 CYNTEC/PEUE063T-R24MS1R195 P_IMVP8_TEMP_10 PC8109 CYNTEC/PEUE063T-R24MS1R195
19 470PF/50V 7x7x3mm 19 470PF/50V 7x7x3mm
AGND AGND
nbs_c0603_h37_000s @ nbs_c0603_h37_000s @
2
1
1
PGND1
PGND2
PGND3
PGND1
PGND2
PGND3
+ PCE8109 + PCE8105
P_IMVP8_CORE1_SNB_S 470U/2V P_IMVP8_GT_SNB_S 470U/2V
5
12
13
5
12
13
1
1
2
2
PR8103 nbs_c7343d_h83_000s PR8105 nbs_c7343d_h83_000s
1Ohm 1Ohm
nbs_r0805_h24_000s nbs_r0805_h24_000s
@ @
2
AC_BAT_SYS
AC_BAT_SYS +3VS_PWR
+3VS_PWR
1
PCI8104 PC8111
1
PC8110 + PCE8104
PCI8102 PC8191 10UF/25V 10UF/25V
1
PC8194 + PCE8108 PC8112
1
0.1UF/25V 15UF/25V
PC8193 10UF/25V 10UF/25V
1
0.1UF/25V 15UF/25V 1UF/6.3V nbs_c0805_h57_000s nbs_c0805_h57_000s nbs_c3528_h83_000s
2
1UF/6.3V nbs_c0805_h57_000s nbs_c0805_h57_000s nbs_c3528_h83_000s 3528_2.1mm
2
2
2
3528_2.1mm
2
PU8102
1
6
Imax = 6A
14
MP86903-CGLT-Z
VIN1
VIN2
20 12
VCC PWM與CS隔20mil VCC
PC8113
VIN2
VIN1
PWM與CS隔20mil PC8103 PSL8101 0.1UF/25V
PSL8102 0.1UF/25V
80 P_IMVP8_PWM5_10
2
0402
1 7
PWM BST
13 PL8104
+VCCSA
80 P_IMVP8_PWM2_10
2
0402
1
P_IMVP8_CORE1_PWM2_10
15
18
PWM BST
21
P_IMVP8_CORE2_BST_30 1 2 PL8102
+VCCCORE 80 P_VCCSA_CS5_10
@
P_IMVP8_SA_PWM1_10 10
CS
2
P_IMVP8_SA_BST_30 1 2
nbs_c0603_h37_000s
0.36UH
Irat=15A
80 P_VCCCORE_CS2_10 CS SW1
@ 2 nbs_c0603_h37_000s 0.24UH 8 1 2
SW1 SYNC
16 3 1 2 P_IMVP8_STB_10 9 3 P_IMVP8_SA_LX_S
SYNC SW2 VTEMP/FLT SW2
17 4
1
P_IMVP8_STB_10 P_IMVP8_CORE2_LX_S P_IMVP8_TEMP_10 PC8114 CYNTEC/PEUE053T-R36MS
VTEMP/FLT SW3
11
1
P_IMVP8_TEMP_10 PC8192 CYNTEC/PEUE063T-R24MS1R195 470PF/50V 5x5x3mm
PGND1
PGND2
AGND
19 470PF/50V 7x7x3mm nbs_c0603_h37_000s @
AGND
2
nbs_c0603_h37_000s @
2
PU8105
PGND1
PGND2
PGND3
4
5
MP86901-AGQT-Z P_IMVP8_SA_SNB_S
P_IMVP8_CORE2_SNB_S
1
PR8106
5
12
13
1
PR8104 1Ohm
1Ohm nbs_r0805_h24_000s
nbs_r0805_h24_000s @
2
@
2
+VCCIO +VCCSA
@
PJP8101
3MM_SHORT_PIN
1 2
1 2
Place Close to CPU
+VCCCORE 30PCS / 26PCS +VCCGT 25PCS /5PCS +VCCSA 14PCS /3PCS
1
PC8118 PC8119 PC8120 PC8121 PC8122 PC8123 PC8124 PC8125 PC8126 PC8127 PC8138 PC8139 PC8140 PC8141 PC8142 PC8144 PC8145 PC8146 22UF/6.3V PC8147 PC8158 PC8159 PC8160 PC8161 PC8162 PC8163 PC8164 PC8165 PC8170 PC8136
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V PC8143 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @
2
nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s
+VCCCORE +VCCGT +VCCSA
1
PC8128 PC8129 PC8130 PC8131 PC8132 PC8133 PC8134 PC8135 PC8156 PC8157 PC8148 PC8149 PC8150 PC8151 PC8152 PC8153 PC8154 PC8188 PC8190 PC8173 PC8183 PC8184 PC8116 PC8172
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
@ @ @ @ @ @ @ @ @ @ @ @
2
2
nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s
+VCCCORE +VCCGT
For VRTT Dummy Load

1
1
PC8171 PC8155 PC8137 PC8175 PC8180 PC8179 PC8177 PC8181 PC8178 PC8182 PC8174
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V PC8176 PC8185 PC8186 PC8187
@ 22UF/6.3V @ 22UF/6.3V @ 22UF/6.3V @ 22UF/6.3V @
+VCCGT +VCCCORE +VCCSA
2
2
nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s
2
PR8114 PR8115 PR8116
BOM
1KOhm 1KOhm 1KOhm
Project Name Rev
DESIGN_IP
1
R1.0
Title : PW_WHISKEY LAKE (2)

Size
Dept.: NB Power Team Engineer: SS
A2
+1.05VSUS [For PCH]
F=408Khz
PR8305 AC_BAT_SYS
620KOhm PJP8300
1 2 1 2
1 2
P_1.05VSUS_VIN_S @
3MM_SHORT_PIN
1
1
1
PCI8301 + PCE8301 C8301
P_1.05VSUS_VTTREF_10
1
P_1.05VSUS_VSENS_10
10UF/25V 15UF/25V 10PF/25V
PC8314 nbs_c0201_h13_000s
2
0.1UF/25V nbs_c3528_h83_000s /EMI
nbs_c0805_h57_000s
PEA16BA
PQH8301
GND GND
EMI 需求_180525
GND
5
D
PU8301
RT8248AGQW
GND 4
nbs_c0603_h39_000s,nb_c0603_h39
5
4
3
2
1
PD8300 @ G S
OCP= 11A
VDDQ
VTTREF
GND1
VTTSNS
VTTGND
BAT54CW
1 23
Imax= 8A
1
2
3
GND4
3 22
1
GND3
2 21 P_1.05VSUS_BST_R_30 PR8303
nbs_c3528_h79_000s
GND2
6 20 PR8304 PC8303 10KOhm
P_1.05VSUS_FB_10 7
FB VTT
19 0Ohm 5% 0.1UF/25V PL8301
+1.05VSUS
S3 VLDOIN
1 2 8 18 1UH
2
30,57,83,88 VSUS_ON S5 BOOT
P_1.05VSUS_EN_10 9 17 P_1.05VSUS_BST_30 1 2
nbs_r0603_h24_000s 1 2 Irat=12A
PR8308 TON UGATE
P_1.05VSUS_TON_10 10 16 P_1.05VSUS_HG_30 nbs_c0603_h37_000s 2 1 480mil
330UF/2.5V
30KOHM PGOOD PHASE
1
P_1.05VSUS_LX_30
22UF/6.3V
PC8312 [HE]CYNTEC/PEUB063T-1R0MS
PCE8302
PCO8301
0.1UF/25V 7x7x3mm
LGATE
PGND
2
SHORT_PAD
1
PC8309
VDD
VID
CS
1
1000PF/50V
PEA16BA
1
@ +
PQL8301
PSP8301
11
12
13
14
15
2
nbs_c0603_h37_000s @
58 1.0VSUS_PWRGD
1
D
2
+5VSUS
P_1.05VSUS_SNB_S
P_1.05VSUS_VDD_30
4
P_1.05VSUS_CS_10
P_1.05VSUS_LG_30
G S
2
1
1
PR8301
1
PC8308 PR8306
1
2
3
1Ohm 1000PF/50V 1Ohm 5%
nbs_r0603_h24_000s @ @
2
5% nbs_r1206_h30_000s GND
2
GND R0.1 GND
0411
1
Follow PWR request PR8302 402K ohm ==> 200K ohm
1
PC8302 (OCP: 10~15A)
200KOhm
4.7UF/6.3V
nbs_c0603_h37_000s PR8302
2
OCP= 11A
GND GND
PC8311 @
PT830* 請放置 PU8301旁;並請放置T race 上! 820PF/50V
2 1
PT8301 VFB=0.75V PRF8301 PR8307

1 @ 3.83KOhm 0Ohm @
P_1.05VSUS_HG_30 2 1
NB_TPC20T
P_1.05VSUS_FB_10 P_1.05VSUS_VSENS_10 2 1 P_1.05VSUS_LOSENS_10
PT8302
1 @
1
+1.05VSUS
1
P_1.05VSUS_LX_30 PRF8302 PC8310 PSP9303 @
NB_TPC20T
10KOhm 0.1UF/25V PSL8302 @ SHORT_PAD
@ 2 1 2 1
0402
2
PT8303 P_1.05VSUS_RESENS_10
2
1 @
P_1.05VSUS_LG_30
NB_TPC20T
GND GND
+1.8VSUS [For PCH] @ PD8302

BAT54CW
1
3
PJP8304 @
+3VA_DSW 2
1MM_OPEN_5MIL
100mil 1 2 100mil PR8311
1 2
P_+1.8VSUS_IN_S 0Ohm
1 2
VSUS_ON 30,57,83,88
1
PC8324 PC8325 P_1.8VSUS_EN_10
10UF/6.3V 10UF/6.3V
@ PC8318
1
2
2
0.1UF/25V
nbs_c0603_h37_000s nbs_c0603_h37_000s
@
2
1
PR8325
2.2Ohm GND
2
1.8VSUS_PWRGD 58 Peak =2.9A
PU8303
RT5768AGQW Conti. =2.4A
FB EN
6 5 PL8303
7
NC PGOOD
4 1UH
+1.8VSUS
SVIN LX3
P_+1.8VSUS_SVIN_20 8 3 Irat=11A
PVIN1 LX2
SHORT_PAD
9 2 1 2 100mil
PVIN2 LX1
10 1
1
PC8327 P_+1.8VSUS_LX_S +1.8VSUS
GND1
1UF/16V 11 CYNTEC/PEUE053T-1R0MS
PSP8302
GND2
nbs_c0603_h37_000s 12 5*5*3mm
GND3
2
13 PR20180713
1
PC8315 PCO8319 PC8320
47PF/50V 22UF/6.3V 22UF/6.3V
2 1 @
2
nbs_c0603_h39_000s,nb_c0603_h39
nbs_c0603_h39_000s,nb_c0603_h39
@
2
PRF8327
40.2KOhm
2 1
P_+1.8VSUS_FB_10 P_+1.8VSUS_SENSE_10 PR20180713 <Core Design>
FB=0.6V Project Name Rev
2
PRF8326 UX433 R1.0
20KOhm
Title : PW_+1.05VSUS/+1.8VSUS
1
Size
Dept.: NB Power team Engineer: SS
A2
+1.2V / +VTT [For Memory]
+VTT
1
PC8601 PC8600
10UF/6.3V 10UF/6.3V
2
nbs_c0603_h37_000s nbs_c0603_h37_000s
F=408Khz
PR8605 AC_BAT_SYS
620KOhm
1 2
1
1
PCI8601 + PCE8601
1
10UF/25V 15UF/25V
PC8614
P_DDR_VTTREF_10
2
P_DDR_VSENS_10
PR8610 PD8600 0.1UF/25V nbs_c0805_h57_000s nbs_c3528_h83_000s
2
0Ohm BAT54AW
1 2 1
25,30,57,58 PM_SUSC#
PEA16BA
PQH8601
3 GND GND
2 P_DDR_EN_10 +1.2V
30,88 1.2V_ON
GND
PSL8601
5
D
PU8601
1 2 RT8248AGQW @
4
2
OCP= 11A
5
4
3
2
1
PR8608 G S
1
PC8612
10KOhm
VDDQ
VTTREF
GND1
VTTSNS
VTTGND
0603
220NF/6.3V
23
Imax= 7.5A
1
2
3
GND4
2
22
1
GND3
1
21 P_DDR_BST_R_30 PR8603
nbs_c0603_h39_000s
nbs_c3528_h79_000s
GND2
6 20 PR8604 PC8603 10KOhm
FB VTT
P_DDR_FB_10 7 19 +VTT 0Ohm 5% 0.1UF/25V PL8601
P_DDR_LDO_EN_10 8
S3 VLDOIN
18 P_DDR_LDOIN_30 1UH
+1.2V
2
S5 BOOT
P_DDR_EN_10 9 17 P_DDR_BST_30 1 2
nbs_r0603_h24_000s 1 2 Irat=12A
TON UGATE
P_DDR_TON_10 10 16 P_DDR_HG_30 nbs_c0603_h37_000s 2 1 480mil
330UF/2.5V
58 1.2V_PWRGD PGOOD PHASE
22UF/6.3V
P_DDR_LX_30 P_DDR_VO_S
PCO8601
1
PC8604 [HE]CYNTEC/PEUB063T-1R0MS
PCE8602
PD8601 1UF/16V 7x7x3mm
LGATE
PGND
SHORT_PAD
1
BAT54CW PC8609
VDD
VID
CS
1
@ 1000PF/50V
nbs_c0603_h37_000s
PEA16BA
2 @ +
PQL8601
PSP8601
11
12
13
14
15
2
3 nbs_c0603_h37_000s @
2
1
1
D
2
PR8609 +5VSUS
0Ohm GND P_DDR_SNB_S
4
14 DDR_PG_CTRL
2 1 P_DDR_LDO_EN_10 G S
1
P_DDR_VDD_30
1
PC8613 PR8606
P_DDR_CS_10
P_DDR_LG_30
2
1
0.1UF/25V PR8601
1
PC8608 1Ohm 5%
1
2
3
@ 1Ohm 1000PF/50V @
2
nbs_r0603_h24_000s @ nbs_r1206_h30_000s GND
2
2
5%
2
GND GND
R0.1
0411
1
PC8602
1
4.7UF/6.3V (OCP: 10~15A)
200KOhm
nbs_c0603_h37_000s
2
PR8602
OCP= 11A
2
GND
GND
PC8611 @
PT860* 請放置 PU8600旁;並請放置T race 上! 820PF/50V
2 1
PT8601 VFB=0.75V PRF8601 PR8607 @

1 @ 6.19KOhm 0Ohm
P_DDR_HG_30
NB_TPC20T
P_DDR_FB_10 2 1 P_DDR_VSENS_10 2 1 P_DDR_LOSENS_10
PT8602
1 @ +1.2V
1
P_DDR_LX_30 PRF8602 PC8610 PSP8602 @
NB_TPC20T
10KOhm 0.1UF/25V PSL8602 @ SHORT_PAD
@ 2 1 2 1
0402
2
PT8603 P_DDR_RESENS_10
2
1 @
P_DDR_LG_30 Close Device & On the Cap
NB_TPC20T
GND GND
<Core Design>
Project Name Rev
UX433 R1.0
Title : PW_+1.2V/+VTT
Size
A2
+3VA_DSW / +5VSUS [System Power]
PJP8707 @
Freq 500KHz
AC_BAT_SYS 1MM_OPEN_5MIL
1 2
1 2
P_+3VADSW_VIN_S
Imax =6.6A
P_+3VADSW_+5VCC_10
1
1
PCI8707 PCI8708 PC8702
10UF/25V 10UF/25V 4.7UF/6.3V
3VA_DSW_PWRGD 25,30,58
OCP=16A
2
nbs_c0603_h37_000s PU8702
nbs_c0805_h57_000s
nbs_c0805_h57_000s
9 7
VCC PGOOD
PR8713 P_+3VADSW_BST_R_30
PC8703
10Ohm 0.1UF/25V
5
VIN BOOT
1 1 2 PL8704 +3VA_DSW
P_+3VADSW_BST_30 nbs_r0603_h24_000s 1 2 1UH
nbs_c0603_h37_000s Irat=12A
ER_180601 2 1 2
LX1
3 P_+3VADSW_LX_S
LX2
PR8715 PSL8707 @ [HE]CYNTEC/PEUB063T-1R0MS
SHORT_PAD
200KOhm SHORT_LAND 7x7x3mm
1 2 1 2 6 10
30 3VADSW_ON 0402 EN VOUT
1
P_+3VADSW_ON_10 P_+3VADSW_EN_10 P_+3VADSW_VOUT_10 PC8704 PR8714 1% PC8705 PC8706 PC8707 PC8709 PC8710
PSP8704
+3VA PSL8708 10PF/50V 1KOhm 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
1 2 @ 11 12 2 1 1 2 nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s
1
0402 LDO3 FF
2
+3VAO P_+3VADSW_FF_10 @
1
PR8716 SHORT_LAND 8 nbs_c0603_h37_000s nbs_r0603_h24_000s
AGND
1
150KOhm PC8711
4.7UF/6.3V 4
PGND
nbs_c0603_h37_000s @
2
2
P_+3VADSW_FF_R_10
ENABLE SET : 1.1V ATK1658BGQUF
ALL MLCC 需上件

ENABLE SET MODE:
Normal mode: above 2.3V
1
PC8712
USM mode : 0.8V~1.7V 0.1UF/25V

@
2
Close to PU8701
AC_BAT_SYS
PT8701
Freq 750KHz
TPC28T
1
Imax =6.33A
@
1
1
5VSUS_PWRGD
+ PCE8703 PCI8705
OCP=16A
PU8703
15UF/25V 10UF/25V
2
2
nbs_c3528_h83_000s
nbs_c0805_h57_000s 12 7
CLK PGOOD
P_+5VSUS_CLK_20 PR8711 P_+5VSUS_BST_R_30
PC8701
H=2.1mm 5 1 1
10Ohm
2
0.1UF/25V
VIN BOOT
P_+5VSUS_BST_30 1 2 PL8703 +5VSUS
nbs_r0603_h24_000s nbs_c0603_h37_000s 1UH
2 Irat=12A
LX1
3 1 2
LX2
PR8717 PSL8705 @ P_+5VSUS_LX_S
20KOhm SHORT_LAND [HE]CYNTEC/PEUB063T-1R0MS
SHORT_PAD
1 2 1 2 6 10 7x7x3mm
30 5VSUS_ON 0402 EN VOUT
1
P_+5VSUS_ON_10 P_+5VSUS_EN_10 P_+5VSUS_VOUT_10 PC8708 PR8712 1%
1
10PF/50V 1KOhm + PCE8704 PC8713 PC8714 PC8715 PC8716 PC8717
PSP8703
11 9 2 1 1 2 330UF/2.5V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
+5VSUS_PWR
LDO5 FF
P_+5VSUS_+5VA_10 P_+5VSUS_FF_10 nbs_c3528_h79_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s nbs_c0603_h39_000s
1
PSL8709
2
PR8718 8 nbs_c0603_h37_000s nbs_r0603_h24_000s @ @
AGND
15KOhm 2 1
1
4 0603
1
PC8718 PR8719
@
PGND
4.7UF/6.3V 820KOhm
2
nbs_c0603_h37_000s @ P_+5VSUS_FF_R_10 @
2
2
ENABLE SET : 1.1V
2
ATK1658CGQUF
ALL MLCC 需上件
ENABLE SET MODE:

ER20180508
PR8719
Normal mode: above 2.3V

上件則超壓100mV
1
PC8719
0.1UF/25V
USM mode : 0.8V~1.7V @
2
Close to PU8702
PC8720
0.1UF/25V PD8702
+12VSUS 2 1 6 1
P_+5VSUS_CLK_20 P_12VSUS_CP1_20 +5VSUS
@
PSL8706 1 2 5 2
0603
P_12VSUS_CP4_20 P_12VSUS_CP3_20
PC8721 4 3
1
0.1UF/25V PC8722
nbs_c0603_h37_000s BAT54SDW 0.1UF/25V
2
PC8723 nbs_c0603_h37_000s
2
0.1UF/25V
2 1
P_12VSUS_CP2_20
BOM
Project Name Rev
UX433 R1.0
Title : PW_+3VA_DSW/+5VSUS
Size
A2
Imax =0.1A
Load Switch Imax = 6A For MPS Soluction
+3VSUS +3VA_DSW +3VSUS
+3VA +3VA_EC
PSL8801 +3VS +3VS_PWR
1
1 2 +3VA_DSW PQ8811 PR8809 PR8813 PR8802
PU8803 0603 100KOhm 100KOhm
PEA28BA 100KOhm
17 @
GND4
16 PSL8802 @
2
GND3
S
15 3 1 2
GND2
D
1 14 5 2 0603
PR8820 PC8801
VIN1_1 VOUT1_2
P_LS_3VSUS_PG#_10
2 13 1
1
0Ohm +3VA_ECO 470PF/50V PC8828
VIN1_2 VOUT1_1 P_3VSUS_PWRGD 58
G
1 2 3 12 0.1UF/25V
0.01UF/50V
0.01UF/50V
ON1 CT1
4
32 PS_ON P_LS_3VA_EC_ON_10 4 11 P_LS_3VA_EC_CT_10 1 2 @
VBIAS GND1
2
1 2 5 10
P_LS_3VSUS_PG_10
3
ON2 CT2
PC8826
PC8815
30,57,83 VSUS_ON @ P_LS_3VSUS_ON_10
@ 6 9 P_LS_3VSUS_CT_10 1 2
VIN2_1 VOUT2_2 @
PR8819 7 8 PC8817 +12VS 5
VIN2_2 VOUT2_1
0Ohm 0.1UF/25V PQ8804B
4
1
1
SN1409049DPUR Imax = 2A EM6K1-G-T2R
6
P_LS_3VS_RC_10 2 1
+3VSUS 2
1
PC8827 PR8804
2
0.01UF/50V 100KOhm PQ8804A
1
1
PC8819 EM6K1-G-T2R
2
0.1UF/25V
1
PC8816
2
+3VA_DSW 0.1UF/25V
2
Imax = 2A
+1.8V
+1.8VSUS
Imax = 0.2A PQ8802
+1.8VS PEA28BA
+1.8VSUS
Imax = 3A PQ8809
S
3
+5VS +5VS_PWR
D
PEA28BA 5 2 +12V
+5VSUS PQ8801 1
G
S
3
1
PEA28BA PC8804
4
5 2 0.1UF/25V +12VSUS
1
PSL8803 @ 1 @ PR8814
2
S
3 1 2
1
PC8808 100KOhm
D
0603
4
5 2 0.1UF/25V
1
1
1
@ PR8815
2
G
2
PC8823 @ 100KOhm
4
0.1UF/25V P_LS_1.8V_RC_10
2
+12VS
2
PSL8803請放置PQ8801旁 PQ8803A
2
1
EM6K1-G-T2R
+12VS P_LS_1.8VS_RC_10 2 1 PC8805
3
P_LS_1.8_R_RC_10 PR8816
1
1
PR8808 0.01UF/50V PQ8803B 0Ohm
2
PC8807 100KOhm EM6K1-G-T2R 5 2 1
1.2V_ON 30,86
P_LS_5VS_RC_10 2 1 0.01UF/50V P_LS_1.8_EN_10
4
1
PC8822 PR8823
0.01UF/50V 100KOhm
1
PC8806
2
220NF/6.3V
@
2
Imax = 0.12A
Imax = 3.6A
Imax = 1A Imax = 0.2A
+VCCPLL_OC +3VA_DSW +3VS
+VCCIO
+1.05VSUS PQ8808A
+VCCSTG +1.05VSUS PQ8808B
+VCCST PQ8813 +1.05VSUS
+1.2V PEA28BA PQ8805
1
6 D S 1 5 D S 3 PEA28BA PR8818 PR8822
S
3 100KOhm 100KOhm
S
5 2 3
1
@
P_LS_+VCCIO_PG#_R_10
D
G G 1 5 2
PC8802 PC8803
2
G
1
1
PE532DX 0.1UF/25V PE532DX 0.1UF/25V PC8831 PR8829
G
2
4
2
1
@ @ 0.1UF/25V 0Ohm
4
@ PC8818
+VCCIO_PWRGD 58
2
PR8805 +12VS_VCCIO PR8803 +12VS @0.1UF/25V 1 2
2
1KOhm 1KOhm @
2 1 2 1 PR8824 +12VS_VCCIO
57 P_LS_VCCST_OC_RC_10
P_LS_+VCCIO_PG#_10
P_LS_VCCSTG_OC_RC_10 P_LS_VCCST_OC_RC_10 1KOhm
2 1
3
1
PR8801 +12V P_LS_VCCPLL_OC_RC_10
P_LS_+VCCIO_PG_10
5
1
PC8834 20KOhm
0.01UF/50V 2 1 PC8829 PQ8814B
4
2
0.01UF/50V EM6K1-G-T2R
2
PR8806 +12VS_VCCIO
ER20180508
1
1KOhm
6
PR8811
PC8813 2 1
0.01UF/50V P_LS_VCCIO_RC_10 2
2
20,25,30,57,58,88 PM_SUSB# 1 2
1
PQ8814A
1
1
PC8820 PC8821 EM6K1-G-T2R
100KOhm
0.01UF/50V 0.1UF/25V
2
+12VSUS PR8831
0Ohm @
1 2
+12VS PR8830 PQ8812
+12VS_VCCIO
0Ohm 20mil EMD62
TR2
20mil
1 2 +12VS_VCCIO_IN 4 3
+12V +12VS
R2 R1
+12VSUS PQ8810 +12VSUS PQ8807
1
EMD62 EMD62 P_LS_VCCIO_EN_10 5 2 PR8821
R1
20mil 20mil 20mil 20mil

R2
TR2 TR2
1MOhm
4 3 4 3
6 1
TR1
2
R2 R1 R2 R1
1
P_LS_12V_EN_10 5 2 PR8812 P_LS_12VS_EN_10 5 2 PR8810 180530_ER
R1 R1
R2 R2
1MOhm 1MOhm
P_LS_12VS_EN_R_10
6 1 6 1
TR1 TR1
2
PR8827
30,52,54,64 SUSC_EC# 30,57,78 SUSB_EC# 1 2 4.7KOhm
BOM
PR8828 1 2
0Ohm 20 VCCIO_Gate P_VCCIO_EN_10 Project Name Rev
1
20,25,30,57,58,88 PM_SUSB# 1 2 PC8835 UX433 R1.0
PR8825 PR20180713 0.01UF/50V
Title :
2
0Ohm @ PW_LOAD_SWITCH
57 P_VCCIO_EN_10 Size
ER20180508 180530_ER
A2
EE Add discharge circuit
Need to confirm timing. GND ER20180508
<=40W <=120W >=120W
PRS8901 20m 10m 5m
10125-0004B000 10125-0001B100 10G21DR00515111
PQ8901
PQ8902
QM3056M6AC
A/D_DOCK_IN P0A03BEA PRS8901 AC_BAT_SYS
3 10mOHM
S
S
480mil 2 5 1 2
D
D
3 1 P_CHG_ACMOS_S_20 1 P_CHG_PATH_19V_SHAPE
nbs_r0612_h27_001s
G
G
4
2
1
1
PR8920 PR8902
4.7MOhm PC8916 PSP8901.PSP8902 100KOhm
0.047UF/50V 請從PRS8901內側中間拉線。 @
1
2
PC8915 PSP8901 PSP8902
2
nbs_c0603_h37_000s
1000PF/50V SHORT_PAD SHORT_PAD 240mil
1 2 P_CHG_ACMOS_G_20
@ @
2
PC8902
0.1UF/25V
PQ8903
1 2 P0A03BEA
5
D
1
PR8918 PR8917 PC8903 PC8901
4.02KOHM 4.02KOHM 0.1UF/25V 0.1UF/25V
4
2
G S
2
ER20180508 PR8922
4.02KOHM
1
2
3
1 2
P_CHG_BATDRV_G_20
P_CHG_BATDRV_20
100KOhm
PR8901
PSL8904 @
1 2
1 2 0402
PQ8905B P_CHG_REGN_20 P_CHG_AC_OK_10
EM6K1-G-T2R PR20180713 AC_BAT_SYS
1 2
3
BAT A/D_DOCK_IN 200mil PC8921
5
1
@ 0.01UF/50V
PC8904
4
PQ8905A 0.1UF/25V
2
2
1
EM6K1-G-T2R PD8900
PEA28BA
PQH8901
1
PSL8900 BAT54CW PCI8901 + PCE8901
P_CHG_CMSRC_20
P_CHG_ACDRV_20
2 1 10UF/25V 15UF/25V PR8923
P_CHG_ACOK_10
30 AC_IN_OC#
P_CHG_ACN_10
P_CHG_ACP_10
0402 6 1 10OHM
5
D
2
A/D_DOCK_IN @ PR8916 nbs_c3528_h83_000s
h=2.1mm nbs_r0603_h39_000s
3
nbs_c0805_h57_000s
10Ohm 5%
1 2 4 P_CHG_BATSRC_20 1 2 240mil
P_CHG_ACDET_10 P_CHG_VCC_R_30 1 2 G S
PR8904 P_CHG_IADP_10 nbs_r1206_h28_000s
127KOhm
1
2
3
1
PU8900
PR8924
1
SN2867RUYR
1
AD : 17.8V
PR8905 PC8905 PC8906 10KOhm P_CHG_RSENS_SHAPE
7
6
5
4
3
2
1
20KOhm 0.1UF/25V 47PF/50V BAT
IADP
ACDET
ACOK
ACDRV
CMSRC
ACP
ACN
PL8901 PRS8902 PJP8901 BAT_CON
2
2
2
33
1
PC8914 3.3UH 10mOHM 3MM_OPEN_5MIL @
2
GND6
32 1UF/25V 1 2 1 2
GND5 2 1
31 nbs_c0603_h35_000s P_CHG_LX_30 2 1
GND4
2
30 7x7x3mm nbs_r1508_h39_000s
90 P_CHG_ACDET_10 GND3
29
1
PC8913 [HE]CYNTEC/PEUB063T-3R3MS CYNTEC/RL3720TT-R010-FN
GND2
8 28
1
0.047UF/50V PR20180713
IDCHG VCC
PEA28BA
9 27
1
P_CHG_IDCHG_10 P_CHG_VCC_30 PR8915 nbs_c0603_h34_000s PC8924 PC8925 PC8926 + PCE8904
PC8927 PC8931
PQL8901
PMON PHASE
2
80 P_IMVP8_PSYS_INFO 10 26 P_CHG_LX_30 0Ohm 1000PF/50V 10UF/25V 10UF/25V 10UF/25V
15UF/25V 10UF/25V
PROCHOT# HIDRV
P_CHG_PROCHOT#_10 11 25 P_CHG_HG_30 nbs_c0603_h37_000s @
5
SDA BTST D
2
P_CHG_SDA_5 12 24 P_CHG_BST_30 2 1 P_CHG_BST_R_30 nbs_c3528_h83_000s
SCL REGN nbs_c0805_h57_000s
nbs_c0805_h57_000s
nbs_c0805_h57_000s
nbs_c0805_h57_000s
13 23
3
P_CHG_SCL_5 P_CHG_REGN_20
CMPIN LODRV
14 22 4
1
PC8907 P_CHG_LG_30 P_CHG_SNB_20 h=2.1mm
CMPOUT GND1
G S
1
47PF/50V PD8901 P_CHG_LG_30
PC8912 P_CHG_REGN_20 BAT54CW
1
2
BATPRES#
PR8925 PR8926
TB_STAT#
2.2UF/16V
1
2
3
2
BATSRC
BATDRV
nbs_c0603_h35_000s 10KOhm 1Ohm 5% PSP8904.PSP8903
2
@ nbs_r1206_h30_000s 請從PRS8902內側中間拉線。
SRN
SRP
ILIM
PSL8901 @
1
1 2 PSP8904 PSP8903
15
16
17
18
19
20
21
30,60 P_SMB0_DATA 0402 +3VA
PR8913 SHORT_PAD SHORT_PAD
PSL8902 @ 180KOhm
1 2 2 1
30,60 P_SMB0_CLK 0402
P_CHG_ILIM_10 @ @
2
P_CHG_BATPRES#_10
P_CHG_TB_STAT#_10
I limit : Charge 6A
P_CHG_BATSRC_20
P_CHG_BATDRV_20
DisCharge 16.5A
1
P_CHG_SRN_10
P_CHG_SRP_10
90 P_CHG_CMPIN_10
1
PR8914 PC8911
100KOhm 0.1UF/25V
2
90 P_CHG_CMPOUT_10
2
PC8910
2
0.1UF/25V
PR8912
1
PSL8903 @ 10OHM
1 2 2 1
30,60 BAT1_IN_OC# 0402
P_CHG_SRP_L_10
nbs_r0603_h39_000s
1
PC8909
+3VS PR8910 PR8911 0.1UF/25V
10KOhm 10OHM
2
1 2 2 1
P_CHG_SRN_L_10
nbs_r0603_h39_000s
1
PC8908
0.1UF/25V
2
CLOSE TO DC_JACK
P_CHG_PATH_19V_SHAPE
P_CHG_ACMOS_S_20
A/D_DOCK_IN
3
PT8904
3
TESTPIN_6P
6
@
6
+3VA
+5VSUS
+3VA_DSW
A/D_DOCK_IN
AC_Short_Protection
HW_Throttle
PT890* 請放置 PU8900旁;並請放置T race 上!
Adaptor select
+5VS_PWR
1
PR8941 PT8901
total power = 90% ADP

8.2KOhm 1 @
nbs_r0603_h24_000s P_CHG_HG_30
NB_TPC20T
Adaptor select
PR20180713 PD8903 P_CHG_ACDET_R_10
PR8943
2
BAV99W 10KOhm AC_BAT_SYS
PR8940 1 2 1 PT8902
1
PR8927 PR8928 100Ohm 3 P_CHG_ACDET_10 1 @
1 2 PWRLIMIT#_CPU 8 2
N Series G Series 150KOhm 150KOhm P_AC_SHORT_PRO_10 P_CHG_LX_30
NB_TPC20T
PD8902 A/D_DOCK_IN
2
PRS8901 10m 5m
BAT54CW PT8903
NEW_PWRLIMIT#_CPU
3
+3VACC +3VACC PQ8904B 1 @
P_AC_SHORT_PRO_R_10
2 5 EM6K1-G-T2R P_CHG_LG_30
NB_TPC20T
3
PR8936
P_PL_AC_THROTTLE_10
4
1
1
PR8929 PR8930 PC8929
1
PR8931 PR8942 PR8944
6
14K 0.4V 30W 120W
0Ohm PQ8906A 1MOhm 2200PF/50V 1MOhm 2KOhm 300KOHM
1
PR8937 PR8935 2 EM6K1-G-T2R @
2
100KOhm 100KOhm P_CHG_PROCHOT#_10 1 2
2
31.6K 0.8V 40W 150W
@
2
PQ8906B
6
PQ8908A PR8947
30 A/D_MAX_POWER 30 MB_MAX_POWER
56K 1.2V 45W 180W
EM6K1-G-T2R
1
EM6K1-G-T2R
dGPU_PD# ---> GPIO12(EE p age 75 or 78) 1MOHM
3
PC8928 2 2 1
5 270PF/50V PSL8905 @ P_AC_SHORT_PRO_GATE_10 P_AC_SHORT_PRO_R_GATE_10 P_CHG_ACMOS_G_20
1
1
1 2
93.1K 1.6V 65W 230W
PR8938 PR8936 P_CHG_AC_OK_10
4
0402 dGPU_PD# 75,78
100KOhm 93.1KOHM P_PL_AC_THROTTLE_GPU_10
1%
3
PQ8908B
1
150K 2.0V 75W 300W
/ADP CHG PQ8904A PR20180713 PR8945 EM6K1-G-T2R
1
PC8917 PR8946
2
2 5
AC limit = 100% ADP
EM6K1-G-T2R 100KOHM 2200PF/50V 300KOHM <Variant Name>
@
2
Project Name
270K 2.4V 90W 330W Bat limit = byte 7 x 1.7
Rev
2
PR20180713 UX433 R1.0
560K 2.8V 120W 400W Title : PW_CHARGER

Size
A1
Register Address
Address Selection Table Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06
Address 0x7E 0x7C 0x7A 0x78 0x76 0x74 0x72 0x70 R/W W W W R R R R
PR9001 10k 1.5k 2k 3.6k 3.9k 4.3k 5.1k 6k bit 4 = 0

bit 5 = 0
Temp. alert
Function threshold setting Sensed temp. data bit 6 = 0
PR9002 Open 8.2k 6.2k 6.8k 4.7k 3.6k 2.7k 2k
When ALERT#
assert
PTR9001 place near PQ8901 AC FET

P_TEMPSENS_VCC_30
PTR9001 PR9003 PR9001 ALERT# pull low if sensed temp.
100kOhm 12KOhm 10KOhm is higher than setting
2 1
2 1
1% 2 1 P_TEMPSENS_VCC_30 PC9005
PC9001 PR9002 47PF/50V
0.1UF/25V 2KOhm @ @
2 1 1.0 ~ 3.56V
1 2 1 2
PR20180713
GND GND GND
PSL9006
PTR9002 place near BAT Connect PU9001
1 8 2 1
ALT/ADD SDA SMB1_DAT_P 28
105C @ 5k PTR9002 PR9004 P_TEMPSENS_ADDR_10 2 7 P_TEMPSENS_SDA_5 2 0402 1
40C @ 51k TM3 SCL 0402 SMB1_CLK_P 28
100kOhm 12KOhm P_TEMPSENS_TM3_10 3 6 P_TEMPSENS_SCL_5 @
TM2 GND
2 1 P_TEMPSENS_TM2_10 4 5 PSL9002 @
TM1 VCC5
2 1 1% P_TEMPSENS_TM1_10 P_TEMPSENS_VCC_30 Check 其他頁是否有
PC9009 UP1905AMA8 pull high 到 3.3V
0.1UF/25V GND
2 1 1.0 ~ 3.56V 1 2
+5VSUS_PWR PC9004
PR20180713 47PF/50V GND
GND 1 2 @
PTR9004 place near PL8901 or PQL8901(CHG page) PR9006 2.2Ohm 5%

nbs_r0603_h24_000s
1
105C @ 5k PTR9004 PR9005 PC9003
40C @ 51k 100kOhm 12KOhm 1UF/16V
2
2 1
nbs_c0603_h37_000s
2 1 1%
PC9002 GND
0.1UF/25V
2 1 1.0 ~ 3.56V
PR20180713
GND
DC Jack Thermal Latch
P_CHG_REGN_20 P_CHG_REGN_20 P_CHG_REGN_20
PTR9003 place near DC JACK
2
PSL9005
2
SHORT_LAND PTR9003
1
1 2 PR9014 PR9017 100kOhm
P_LATCH_ACDET_10 0402
P_LATCH_OUT_10 100KOhm 10KOhm
1
3
2
1
PQ9003B
89 P_CHG_CMPIN_10
EM6K1-G-T2R 5
2
P_LATCH_OUT#_10 PQ9003A
1
6
EM6K1-G-T2R PR9022
PC9008 7.32KOhm
2 0.1UF/25V
P_CHG_CMPOUT_10 89
2
1
1
GND
PR20180713 GND
GND
PR9018
1 2
PR9013
10KOhm
47.5KOhm
2 1
P_CHG_ACDET_10 89
<Variant Name>
Project Name Rev
UX433 R1.0
Title : PW_PROTECTION
Size
A3
+NVVDD [For DGPU]
PTR9110 place near PQL9101
Close to +NVDD L side
At Page 78
PTR9110
100kOhm PD9101
BAT54AW
P_GPU_VRM_TEMP_SENSOR_10 79
2 1
/VGA 2
3
1
@/VGA
CLOSE PCI9101
PR9102
PSP9103
0Ohm
+1.8VSG_AON
P_NVVDD_EN_10 2 1 NVVDD_EN_3.3 78 P_NVVDD_VIN_TON_10 2 1
AC_BAT_SYS
/VGA
SHORT_PAD
1
@/VGA
1
PR9101
10KOhm PC9101 PJP9101
0.015UF/16V 2 1
2
N17S Boot V oltage = 0.8V PSL9101 /VGA /VGA P_NVVDD_VIN_S 2 1
@/VGA
2
1 2
1
N16S Boot V oltage = 0.9V 75 NVDD_PSI 0402
3MM_OPEN_5MIL
1
C9101 C9102 PCI9101 + PCE9101
PWM-VID Spec @/VGA 0.1UF/25V 0.1UF/25V 10UF/25V 15UF/25V
/VGA /VGA
/EMI /EMI
2
N16 N17 PSL9102 nbs_c0805_h57_000s nbs_c3528_h83_000s
1 2
75 NVDD_PWM_VID 0402
R1 (Kohm) 20 6.19
@/VGA
R2 (Kohm) 20 20.5
PR9103 EMI 需求_180528
R3 (Kohm) 2 4.32 6.19KOhm PQH9101A
FDPC5030SG
9
R4 (Kohm) 18 16.5 P_NVVDD_REFIN_R_10 2 1
D1
R1 /VGA
1
R5 (Kohm) 0 309
1
+NVVDD
2
PR9105 PL9101
1
R3 G1
C (nF) 2.7 4.7 PR9106 PR9107 10KOhm 0.24UH
4.32KOhm R2 20.5KOhm /VGA S1 7 Irat=35A /VGA
2
2 D2/S1 6 1 2
/VGA /VGA 5 P_NVVDD_LX1_30
1
PSL9103 P_NVVDD_BST1_RC_30 [HF]CYNTEC/PEUE063T-R24MS1R195
1 2 2 1
1
7*7*3mm
P_NVVDD_BST1_30
0402
P_NVVDD_HG1_30
2 1
P_NVVDD_VID_10
P_NVVDD_REFIN_10 P_NVVDD_REFIN_L_10 5% PC9104
P_NVVDD_PSI_10
P_NVVDD_EN_10
@/VGA C PR9108 PC9103 /VGA 8 1000PF/50V
2
0Ohm 0.1UF/25V G2 nbs_c0603_h37_000s
1
R4 S2
1
nbs_r0603_h24_000s nbs_c0603_h37_000s @/VGA
PR9109 PC9105 RT:FSW=250K HZ /VGA /VGA + PCE9103
10
11
12
13
14
1
16.5KOhm 4700PF/50V PC9106 P_NVVDD_SNB1_S 330UF/2V
2
/VGA /VGA 2200PF/50V
1
PU9101
2
+5VS_PWR
1
@/VGA PR9110
/VGA
2
PC9108 P_NVVDD_VIN_TON_10 RT8820AGQW 1Ohm
5
4
3
2
1
nbs_c7343d_h83_000s
P_NVVDD_FBRTN_R_10
4700PF/50V nbs_r1206_h30_000s
VID
PSI
EN
UGATE1
BOOT1
2
PR9124 23 @/VGA
2
1
1
GND3
R5 22
1
@/VGA PR9111 PR9112 11KOhm PR9114 PR20180713
GND2
309Ohm 1% PC9109 2.2Ohm @/VGA 21 2.2Ohm
GND1
/VGA 0.1UF/25V /VGA 6 20 /VGA
2
REFADJ PHASE1
2
PR9115 P_NVVDD_REFADJ_10 7 19 P_NVVDD_LX1_30 5%
2
REFIN LGATE1
/VGA 620KOhm P_NVVDD_REFIN_10 8 18 P_NVVDD_LG1_30 nbs_r0603_h24_000s
VREF PVCC
P_NVVDD_VREF_10 9 17 P_NVVDD_PVCC_30 PQH9101B
TON LGATE2
1 2 10 16
1
P_NVVDD_FBRTN_10 P_NVVDD_OCS_10 P_NVVDD_LG2_30 FDPC5030SG
RGND PHASE2
/VGA P_NVVDD_FBRTN_10 P_NVVDD_LX2_30 PC9110 15
S2_6
16
OCSET/SS
2.2UF/16V
1
S2_7
2
UGATE2
PGOOD
17
1
PC9111 PR9125 /VGA
BOOT2
S2_8
VSNS
1UF/25V 20KOhm 18
S2_9
/VGA @/VGA 19
S2_10
2
/VGA 20
11
12
13
14
15
S2_11
Fsw RT8820A 21
S2_12
22
S2_13
PR9115 23
S2_14
495K Hz 309KOhm PR9118 P_NVVDD_BST2_RC_30 24
PSP9101 S2_15
100Ohm
P_NVVDD_COMP_10
P_NVVDD_BST2_30
P_NVVDD_HG2_30
1 2 2 1 /VGA
P_NVVDD_PG_10
P_NVVDD_FB_10
2 1 2 1
5%
250K Hz PR9115 @/VGA
1
PR9119 PC9112
SHORT_PAD
620KOhm PC9113 0Ohm 0.1UF/25V
@/VGA 1000PF/50V nbs_r0603_h24_000s nbs_c0603_h37_000s
2
P_NVVDD_FBRTN_L_10 @/VGA /VGA /VGA
PSL9104 P_NVVDD_VIN_S
1 2
1
76 NVDD_VSSSENSE 0402
1
PCI9102 + PCE9102
@/VGA 10UF/25V 15UF/25V
close to GPU /VGA /VGA
2
PC9115 PC9126 nbs_c0805_h57_000s nbs_c3528_h83_000s
2
4700PF/50V 4700PF/50V
/VGA
Imax= 53A
1
PSL9105 PQH9102A
@/VGA
1 2 FDPC5030SG
OCP= 55~60A
9
76 NVDD_VCCSENSE 0402
D1
@/VGA
1
+1.8VSG_AON
PR9122 1
G1
PL9102 +NVVDD
10KOhm 0.24UH
+NVVDD PR9123 @/VGA /VGA S1 7 Irat=35A /VGA
2
1
PSP9102 D2/S1
100Ohm 2 6 1 2
1 2 PR9131 P_NVVDD_LX2_30 5 P_NVVDD_LX2_30
2 1 10KOhm [HF]CYNTEC/PEUE063T-R24MS1R195
1
/VGA PSL9106 @/VGA 7*7*3mm
2
SHORT_PAD
@/VGA 1 2
1
PC9119
0402 NVDD_PWRGD 78
@/VGA
PC9120 8 1000PF/50V
2
P_NVVDD_FB_L_10 P_NVVDD_LG2_30 G2 nbs_c0603_h37_000s
1000PF/50V
2
S2 @/VGA
1
CO-LAY PSP9101 & +NVVDD CLOSE PCE9102 /VGA
10
11
12
13
14
1
P_NVVDD_SNB2_S + PCE9104
UP9024R RT8820A PC9122 330UF/2V
2200PF/50V
1
2
2
PR9124 @ @ @/VGA PR9126
@/VGA
RT OCL RT SS 1Ohm
nbs_c7343d_h83_000s
PR9125 @ @ nbs_r1206_h30_000s
1
算式為Per Phase
1
@/VGA
2
PC9117 @ @ PR9128 PC9125 PR20180713
ROC=Ivalley*Rds*12 /10uA 86.6KOhm 5600PF/25V
2
PC9118 @ @
2
@/VGA
RT OCL=60A /VGA
PC9121 @ @
PQH9102B
12PIN FUNCTION PR9120 0 0 FDPC5030SG
15
16
S2_6 請確認EE頁面MLCC是否有22uF電容
PR9128 @ 運算 S2_7
17
S2_8
18
S2_9
PC9125 運算運算 19
S2_10
20
S2_11
21
S2_12
PC9124 運算 @ 22
S2_13
23
S2_14
24
S2_15
PR9127 運算 @
/VGA
PR9129 10K @
PR9115 @ 620K
PR9130 10K @ PT910* 請放置 PU9101旁;並請放置T race 上!
PR9113 620KOhm @
PT9101 PT9102
1 @/VGA 1 @/VGA
PC9116 改電阻對地 @ P_NVVDD_HG1_30
NB_TPC20T
P_NVVDD_HG2_30
NB_TPC20T
9PIN FUNCTION
PC9111 @ 1UF PT9103 PT9104
1 @/VGA 1 @/VGA
<Variant Name>
P_NVVDD_LX1_30 P_NVVDD_LX2_30
NB_TPC20T NB_TPC20T
PR9112 @ 2.2Ohm Project Name Rev
PT9105 PT9106 UX433 R1.0

1 @/VGA 1 @/VGA
P_NVVDD_LG1_30 P_NVVDD_LG2_30 Title : PW_+NVVDD
NB_TPC20T NB_TPC20T
Size
Dept.: NB Power Team Engineer: SS
A2
+FBVDDQ [For VRAM]
F=408Khz
PR9305 AC_BAT_SYS
620KOhm PJP9300
1 2 2 1
2 1
P_FBVDDQ_VIN_S @/VGA
/VGA 1MM_OPEN_5MIL
1
1
PCI9301 + PCE9301
P_FBVDDQ_VTTREF_10
10UF/25V 15UF/25V
P_FBVDDQ_VSENS_10
PC9314 /VGA /VGA
2
0.1UF/25V nbs_c0805_h57_000s nbs_c3528_h83_000s
2
/VGA
3528_2.1mm
GND GND
PEA16BA
PQH9301
GND
5
D
PU9301
RT8248AGQW
GND 4
5
4
3
2
1
G S
PD9300 @/VGA
Imax= 7.2A
VDDQ
VTTREF
GND1
VTTSNS
VTTGND
BAT54CW
1 23 /VGA
1
2
3
GND4
3 22
OCP= 11A
1
GND3
2 21 P_FBVDDQ_BST_R_30 PR9303
GND2
6 20 PR9304 PC9303 10KOhm
FB VTT
P_FBVDDQ_FB_10 7 19 0Ohm 5% 0.1UF/25V /VGA PL9302
1 2 8
S3 VLDOIN
18 1UH /VGA
+1.35VSG
2
78 DGPU_FBVDDQ_EN S5 BOOT
P_FBVDDQ_EN_10 9 17 P_FBVDDQ_BST_30 1 2 nbs_c0603_h37_000s
nbs_r0603_h24_000s 1 2 Irat=12A
PR9308 TON UGATE
P_FBVDDQ_TON_10 10 16 P_FBVDDQ_HG_30 /VGA /VGA 2 1 480mil
30KOHM PGOOD PHASE
1
PC9312 P_FBVDDQ_LX_30
/VGA
0.1UF/25V [HE]CYNTEC/PEUB063T-1R0MS
PEA16BA
@/VGA 7x7x3mm
PQL9301
LGATE
PGND
2
SHORT_PAD
1
PC9309
VDD
5
VID
D
CS
1000PF/50V
/VGA @/VGA
PSP9301
11
12
13
14
15
2
4
1
nbs_c0603_h37_000s @/VGA PCO9301 PCE9302
78 +FBVDDQ_PWRGD
G S
1
22UF/6.3V + 330UF/2.5V
1
+5VSUS_PWR P_FBVDDQ_SNB_S /VGA /VGA
/VGA nbs_c0603_h39_000s,nb_c0603_h39
nbs_c3528_h79_000s
1
2
3
2
P_FBVDDQ_VDDP_20
1
PC9308 PR9306
P_FBVDDQ_CS_10
P_FBVDDQ_LG_30
1000PF/50V 1Ohm 5% 3528B H=2.1mm
@/VGA @/VGA
2
1
2
PR9301 nbs_r1206_h30_000s
2
1Ohm
nbs_r0603_h24_000s
5%
2
GND
/VGA GND GND
R0.1
/VGA 0411
1
PC9302
MOS
1
4.7UF/6.3V
nbs_c0603_h37_000s
200KOhm
(OCP: 10~15A)
1. 6A以下 PEA28BA
2. 大於6A以上 PEA16BA
2
/VGA PR9302
3. 10A以上包裝換5*6MOS
2
OCP= 11A
GND
PC9311 @/VGA GND

820PF/50V
2 1
PT930* 請放置 PU9301旁;並請放置T race 上!
VFB=0.75V PRF9301 PR9307 @/VGA

PT9301 8.06KOhm 0Ohm
1 @
P_FBVDDQ_HG_30 P_FBVDDQ_FB_10 2 1 P_FBVDDQ_VSENS_10 2 1 P_FBVDDQ_LOSENS_10
NB_TPC20T
/VGA
PRFB9301
PT9302 6.2K = 1.2V
1
1 8.06K = 1.35V +1.35VSG
1
@ PRF9302 PC9310 PSP9302 @/VGA
10K = 1.5V
P_FBVDDQ_LX_30 10KOhm 0.1UF/25V PSL9302 @/VGA SHORT_PAD
NB_TPC20T
@/VGA 2 1 2 1
0402
2
/VGA P_FBVDDQ_RSSENS_10
2
PT9303
1 @
P_FBVDDQ_LG_30
NB_TPC20T
GND GND
<Core Design>
Project Name Rev
UX433 R1.0
Title : PW_+1.35VSG
Size
A2
A/D_DOCK_IN
QM3056M6AC P0A03BEA AC_BAT_SYS
SN2867RUYR P0A03BEA
DCDRV
ACDRV
H-MOS
PEA28BA*1
SMB0_DAT L-MOS BAT
PEA28BA*1
SMB0_CLK
ACOK
AC_BAT_SYS
AC_BAT_SYS
RT8249CGQW
+3VAO
+3VA
SN1409049-1 +3VA_EC
PS_ON
H-MOS
PEA16BA*1
5VSUS_ON
L-MOS +5VSUS
PEA16BA*1
+5VSUS_PWR
Controller
Converter +5VS
SUSB#_EC PEA28BA
LDO
MOSFET +5VS_PWR
+3VA_DSW
SN1409049-2 +3VSUS
VSUS_ON
+3VS
SUSB#_EC PEA28BA
H-MOS
PEA28BA*1
L-MOS
3VADSW_ON PEA28BA*1 +1.8VSUSO
+1.8VSUS
RT5768AGQW
VSUS_ON
1.8VSUS_PWRGD
1.2V_ON PEA28BA +1.8V
SUSB#_EC PEA28BA +1.8VS
+12VSUS
EMD62
SUSC#_EC +12V
EMD62 +12VS
3VA_DSW_PWRGD SUSB#_EC
MP2969BGQJT-Z
Dr,MOS
MP86903-CGLT-Z
+VCCCORE
+3VS_PWR Dr,MOS
MP86903-CGLT-Z
+VCCGT
ALL_SYSTEM_PWRGD
Dr,MOS
P_SVID_ALERT#_X2 MP86901-AGQT-Z
+VCCSA
P_SVID_DATA_X2
P_SVID_CLK_X2 IMVP8_PWRGD
+1.05VSUS
+5VSUS
RT8248AGQW
PE532DX +VCCST
SUSC#_EC
VSUS_ON H-MOS
PEA16BA*1 1.0VSUS_PWRGD +VCCSTG
SUSC#_EC
L-MOS PE532DX
PEA16BA*1 CPU_C10_GATE#
PEA28BA
+VCCIO
SUSB_EC#
CPU_C10_GATE#
+1.2V
RT8248AGQW
+5VSUS H-MOS
PEA16BA*1
L-MOS PEA28BA
+VCCPLL_OC
PEA16BA*1 SUSC#_EC
1.2V_ON
CPU_C10_GATE#
PM_SUSC#
+VTT
DDR_PG_CTRL 1.2V_PWRGD
+NVVDD
RT8820AGQW
+5VS_PWR H-MOS
PEA16BA*2
L-MOS
PEA16BA*2
NVDD_PWR_EN
dGPU_PWRON_IO
NVDD_PWRGD
+1.35VSG
RT8248AGQW
+5VS_PWR H-MOS
PEA16BA*1
L-MOS
PEA16BA*1
<Variant Name>
DGPU_FBVDDQ_EN
Project Name Rev
UX432 R1.0
Title : PW_FLOWCHART
Size
+FBVDDQ_PWRGD Dept.: Engineer:
Custom
ASUS SS
AC-IN Mode
Power-On Sequence
Timing Diagram Rev.0.1
1 +3VA_EC
2 EC_RST#
For Detail power sequence timing spec,

please refer to #543016 chapter 43
3 3VADSW_ON
+3VADSW/+5VSUS
t200b
6 DPWROK_EC
t202
7 PM_SLP_SUS#
8 VSUS_ON
11 PM_RSMRST#
t_plt01
12 PM_SUSWARN#
(falling edge)
13 PWR_SW#
T=50ms
14 PM_PWRBTN#
15 PM_SUSC#
t204
16 PM_SUSB#
16 PM_SLP_A#
+VCCIO
(EC to power) 17 SUSC_EC#
+1.2V/+5V/+12V
(EC to power) 18 SUSB_EC#
+3VS/+5VS/+12VS
19 +1.2V_PWRGD
19
21 VCCST_PWRGD
22 ALL_SYSTEM_PWRGD
23 PM_PWROK_PCH
24 VCCIN_EN
tCPU07
+VCCIN
t_plt03
25 CORE_PWRGD
26 <Variant Name>
t_plt05=120ms Project Name Rev
UX432 R1.0
27 PM_SYSPWROK Title : AC Power Oniming
T
Size
Dept.: <OrgName> Engineer: Tony1_chang
C
28 BUF_PLT_RST# Date: Wednesday, July 18, 2018 Sheet 100 of 100
AC-IN Mode
Power On Sequence Diagram Rev.2.0
AC_BAT_SYS
RESET
(1)PS_ON +3VA_EC (2)EC_RST#
LOGIC
POWER
(15)PWR_SW#
BUTTON
+3VA
+5VA
(8)VSUS_ON
+3VSUS (16)PM_PWRBTN#
(3)ME_AC_PRESENT
(9)P_3VSUS_PWRGD (17)PM_SUSC#
(4)3VADSW_ON
SN1409049DPUR
(18)PM_SUSB#
(4)3VADSW_ON +3VA_DSW (8)VSUS_ON +1.8VSUS
(9)1.8VSUS_PWRGD
(4)5VSUS_ON
EC
(5)3VA_DSW_PWRGD
(21)1.8V_PWRGD (19)SUSC_EC#
+1.8V
(19)1.2V_ON
(6)DPWROK_EC (19)1.2V_ON
+3VS
(7)PM_SLP_SUS# (20)SUSB_EC#
(20)SUSB_EC#
(22)ALL_SYSTEM_PWRGD#
(5)3VA_DSW_PWRGD
(8)VSUS_ON
+12V
(24)PM_PWROK
(19)SUSC_EC# (11)3VSUS_PWRGD
+12VSUS
(4)5VSUS_ON (23)IMVP8_PWRGD
(13)PCH_SUSACK#
+5VSUS
+12VS
(20)SUSB_EC#
(25)PM_SYSPWROK
(12)PM_RSMRST#
(16)PM_PWRBTN#
PWRBTN#
(12)PM_RSMRST#_PCH
+5V RSMRST#
(19)SUSC_EC# (14)SUSWARN# (26)BUF_PLT_RST# (7)PM_SLP_SUS#
SLP_SUS#
+5VS
(9)P_3VSUS_PWRGD
SLP_LAN#
SKL-U
(20)SUSB_EC# (9)1.8VSUS_PWRGD
AND (11)3VSUS_PWRGD
SLP_A#
SN51285ARUKR
(10)1.0VSUS_PWRGD
(6)DPWROK_EC
P.58
(17)PM_SUSC#
(18)PM_SUSB#
SLP_S4# PCH
(5)3VA_DSW_PWRGD SLP_S3#
(22)VCCST_PWRGD_PCH
VCCST_PWRGD
(5)3VA_DSW_PWRGD
(13)PCH_SUSACK#
+1.2V AND (12)PM_RSMRST#_PCH
(14)SUSWARN#
SUSACK#
(12)PM_RSMRST# SUSPWRDNACK/SUSWARN#
(19)1.2V_ON (21)1.2V_PWRGD (6)ME_AC_PRESENT_PCH
P.25 ACPRESENT
(6)DPWROK_EC (6)DPWROK_EC
DPWROK
+VTT AND (6)ME_AC_PRESENT_PCH
(22)DDR_PG_CTRL (3)ME_AC_PRESENT (24)PM_PWROK_PCH
PCH_PWROK
P.25 (25)PM_SYSPWROK_PCH
SYS_PWROK
UP9011QQMI (18)PM_SUSB#
(22)VCCIO_PWRGD
AND (22)ALL_SYSTEM_PWRGD (26)BUF_PLT_RST#
(21)1.2V_PWRGD PLTRST#
(21)VCCST_PWRGD
P.58
+VCCST
(19)SUSC_EC# (21)VCCST_PWRGD
(24)PM_PWROK AND (24)PM_PWROK_PCH
GPP_C20
(8)VSUS_ON (23)IMVP8_PWRGD
+1.0VSUS (20)SUSB_EC# +VCCIO (22)VCCIO_PWRGD P.25 GPP_C22
(5)3VA_DSW_PWRGD
AND (25)PM_SYSPWROK_PCH
SN1409049DPUR
(25)PM_SYSPWROK
P.25
(10)1.0VSUS_PWRGD
RT8248AGQW
+VCCCORE
+VCCSA (23)IMVP8_PWRGD
+VCCGT
(22)ALL_SYSTEM_PWRGD
RT3601BCGQW
<Variant Name>
Project Name Rev
UX432 R1.0
Title : POWER-ON SEQUENCE

Size
Dept.: Engineer:
A2

Asus UX433FN - 2.0

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UX433 SCHEMATIC Revision 0.

12 TBT&TSP65982&Type_C_port1 Page 3~9

13 LPDDR3_TERMINATION Page 70~79 PCIE_9~12 TAS5766M +5VSUS_R

77 USB 2.0 USB 3.0 Page 60

1 USB 3.0 (MB) USB3_1 USB 3.0 (MB)

80_PW_IMVP8 (1) 2 USB 3.0 (I/O) USB3_2 Skew Holes

83_PW_+1.2V/ +1.8VSUS 4 Card reader USB3_4 USB 3.0 Type C (MB)

89_PW_CHARGER(ISL9237 (NVDC +HPB)) 8

90_PW_PROTECTION 9 Project Name Rev

10 SIP BT UX432 R1.0

Title : Block Diagram

GPP_C8 GPO N/A +3VS GPP_G7 Native SDIO_WP GPH5 O PM_PWROK

GPP_C21 GPO N/A GPJ2 O N/A LOW

GPP_D2 GPO N/A GPJ7 O N/A HIGH

GPP_D14 GPO N/A +3VSUS

Title : System Setting

disconnect DDC to Titan Ridge (Roger 5/5) CP4

PDG#543016 DDI1 mapping DDPB

DDI2_1 Lane1 24.9Ohm

DDPC I2C Page. 147 Size

LPDDR3 COMPENSATION SIGNALS

Project Name Rev

For Debug Code Output +3VSUS

R0505 1 2 2.2KOhm hh_r0201_h12

UX391RA add Transport Layer Security (TLS) Confidentiality

PU ESPI BUS PU Enable Project Name Rev

Disable Intel ME TLS ipher suite UX432 R1.0

C0656 C0601 C0604 C0607

CPU - VCCIO DECAPS- Place close to the package

+VCCSA System Agent power rail

+VCCGT Sliced graphics power rail

+1.05V_VCCPLL=+VCCST CPU PLL power rails

+VCCPLL_OC=+1.2V CPU digital PLL power rails

Project Name Rev

Whisky Lake Check

On Package Cache resistance Compensation

Project Name Rev

Project Name Rev

C1080 C1081 C1082 C1083 C1084 C1085

R1301 1 2 68Ohm 1% R1329 1 2 68Ohm 1% R1341 1 2 80.6Ohm 1%

+VTT R1357 1 2 37.4Ohm 1%

Project Name Rev

C1491 close to C1475 nbs_c0201_h13_000s 1%

C1402 Close to U1401

0402 size C1405 C1406 C1407 C1409 C1410 hh_c0402_h28_pw hh_c0402_h28_pw

Project Name Rev

SWAP : a300.1260a_ddr_swap.xlsx(page14,15) U1502B

Project Name Rev

VREF_CA (All close to memory)

UX432 Delete SL1905 SL1901 SL1915 DDDR DQ CA 直接short過去 P19

Project Name Rev

Title : LPDDR3 CA_DQ VOL

PD XTAL INPUT IS SINGLE ENDED

I2C1 pull high Remove to P.31 R5312 10KOhm

R2121 1 2 10KOhm R2120 1 2 10KOhm

UX305UA remove 0429 UX305UA remove 0429

Onboard Memory PCB-ID: /RAM

UX391RA add 0803