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Verilog QP - 1

The document is a test paper for a Verilog HDL module. It contains questions about Verilog concepts and syntax as well as design problems to test understanding of sequential logic design and coding in Verilog. The questions cover topics such as basic syntax, operators, modeling sequential circuits, and designing common components like counters, decoders, and ALUs.

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Mohsin Khan A
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Download as DOCX, PDF, TXT or read online on Scribd
142 views

Verilog QP - 1

The document is a test paper for a Verilog HDL module. It contains questions about Verilog concepts and syntax as well as design problems to test understanding of sequential logic design and coding in Verilog. The questions cover topics such as basic syntax, operators, modeling sequential circuits, and designing common components like counters, decoders, and ALUs.

Uploaded by

Mohsin Khan A
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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©Cranes Software International Limited, Varsity Division V1.

0 2019-20

Test Type Module Test Test Code Verilog SET 1_2019-


20

Subject Verilog HDL Duration 2 hrs Total Marks 100 Marks

INSTRUCTIONS: (Please read before answering)


1. Do not write on the question paper. Write / Answer only in the answer sheet provided
2. No additional time will be provided to complete the test
3. Your answer sheet will not be evaluated if the instructions are not followed.
I. Answer in one word (15 x 1 = 15)

1. The FPGA refers to ____________

2. In a multiplexer the output depends on its ________________

3.Most demultiplexers facilitate which type of conversion?_________________

4.The sequential circuit is also called ___________

5. How many possible outputs would a decoder have with a 6-bit binary input?_________

6.How Do You Implement The Bi-directional Ports In Verilog Hdl?

7. A decimal counter has ______ states.

8. Any signed negative binary number is recognized by its ________

9. Represent signed number -3 in bit/hex format. Consider bitwidth as 32


_______________________

10. If there is mismatch in connecting wire such as Y1[7:0] = Y2[15:0]

11. What can be Verilog statement for 6 bit register constant C3 with decimal value of 30

12. What can be the Verilog code that declares an 6-bit register, R_H36, and initially assigns it
the hexadecimal value 36

13. If A=1’b1,B=2’b01,C=2’b00 y={4{A},2{B},C} equals

14. keywords "assign" "deassign" are __________ assignment

 15. If in1 = 4’b101x and in2 = 4’b0101 then in1 + in2 equals

II. Answer the following (5 x 2 = 10)

1.What is the difference between bit wise, unary and logical operators?

2.Write a Verilog code for synchronous and asynchronous reset? 

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©Cranes Software International Limited, Varsity Division V1.0 2019-20

 3. What is $random?

4. What are different types of delay control?

5. What is rise,fall and turnoff delays?

III. Explain the following ( 5x 5 = 25)

1. What is the difference between blocking and non blocking assignment with example

2. Write any VHDL/Verilog HDL code for an Asynchronous Reset D Flip Flop.

3. Draw the combinational logic circuit with three inputs x,y, z and three output a, b and c. when
binary input is 0, 1, 2 or 3 the binary output is one greater than the input. When the binary input
is 4, 5, 6 or 7 the binary output is one less than the input.

4. Design 5 to 32 decoder. Use 2 to 4 and 3 to 8 decoder if required.

5. From the below diagram tell the equivalent logic

Circuit Gate Circuit Gate Circuit Gate

Circuit Gate Circuit Gate Circuit Gate

IV Design and write the verilog program for the following (5 x 10 = 50)

1 . Draw the MEALY FSM for following sequence detection “101011” for both overlap and non-
overlap sequence and write the HDL code.

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©Cranes Software International Limited, Varsity Division V1.0 2019-20

2. Design and write a verilog program for a counter which counts 16 states using synchronous
counter.

3. Design and write a verilog program for 4x4 multiplier.

4. Design ALU with minimum 10 functions using register and write verilog program.

5. Design the following using decoders

a) Half adder

b) F(w, x, y, z) = ∑(1, 4, 5, 6, 12, 14, 15)

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