Ina 3221
Ina 3221
Ina 3221
INA3221
SBOS576B – MAY 2012 – REVISED MARCH 2016
Typical Application
Power Supply
(0 V to 26 V) CBYPASS
0.1 µF
Load 1
VS (Supply
VIN+1 VIN±1 Voltage) 10 k
Power Supply
(0 V to 26 V) SDA
I2C-
CH 1 and SCL
Bus SMBus-
CH 2 Voltages 1-3 Compatible A0
VIN+2
Interface VPU VS
Shunt
ADC
VIN±2 Voltages 1-3
Critical Limit 10 k
Alerts 1-3 VPU
Power Valid (PV)
Load 2 CH 3 Shunt Voltage
Critical
Sum Alerts
Warning
Timing Control (TC)
GND
VIN+3 VIN±3
Power Supply
(0 V to 26 V) Load 3
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA3221
SBOS576B – MAY 2012 – REVISED MARCH 2016 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.5 Programming .......................................................... 20
2 Applications ........................................................... 1 8.6 Register Maps ......................................................... 24
3 Description ............................................................. 1 9 Application and Implementation ........................ 36
4 Revision History..................................................... 2 9.1 Application Information............................................ 36
9.2 Typical Application ................................................. 36
5 Device Comparison Table..................................... 4
6 Pin Configuration and Functions ......................... 4 10 Power Supply Recommendations ..................... 38
7 Specifications......................................................... 5 11 Layout................................................................... 38
11.1 Layout Guidelines ................................................. 38
7.1 Absolute Maximum Ratings ...................................... 5
11.2 Layout Example .................................................... 38
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5 12 Device and Documentation Support ................. 39
7.4 Thermal Information .................................................. 5 12.1 Device Support...................................................... 39
7.5 Electrical Characteristics........................................... 6 12.2 Documentation Support ....................................... 39
7.6 Typical Characteristics .............................................. 7 12.3 Community Resources.......................................... 39
12.4 Trademarks ........................................................... 39
8 Detailed Description ............................................ 10
12.5 Electrostatic Discharge Caution ............................ 39
8.1 Overview ................................................................. 10
12.6 Glossary ................................................................ 39
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11 13 Mechanical, Packaging, and Orderable
8.4 Device Functional Modes........................................ 16
Information ........................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added Device Informationand ESD Ratings tables, and Feature Description, Device Functional Modes, Application
and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and
Mechanical, Packaging, and Orderable Information sections ................................................................................................ 1
• Deleted trace from SDA to SCL, and added missing connector dot to VS in front-page diagram ........................................ 1
• Added (VIN+) + (VIN–) / 2 to common-mode analog inputs in the Absolute Maximum Ratings table ..................................... 5
• Deleted VBUS from analog inputs in Absolute Maximum Ratings table ............................................................................... 5
• Added operating temperature to Absolute Maximum Ratings table ....................................................................................... 5
• Changed all VSENSE to VSHUNT throughout data sheet for consistency.................................................................................... 6
• Changed "Status register" to "Mask/Enable register" to clarify register name in Basic ADC Functions section ................. 11
• Changed Critical Alert section text for clarity. ...................................................................................................................... 12
• Added Summation Control Function section ........................................................................................................................ 12
• Changed external "RPU" to "RPU_ext" in Figure 20 ................................................................................................................. 14
• Changed Multiple Channel Monitoring section text for clarity. ............................................................................................ 17
• Added X and Y axis labels to Figure 25 ............................................................................................................................... 18
• Changed "bidirectional" to "I/O" in second paragraph of Bus Overview section .................................................................. 20
• Changed VS+ to VS in Table 1.............................................................................................................................................. 20
• Changed references in Figure 30 to point to correct notes .................................................................................................. 22
• Changed Figure 31 ............................................................................................................................................................... 23
• Changed values in Table 2, Bus Timing Definitions............................................................................................................. 23
• Added data valid time to Table 2, Bus Timing Definitions.................................................................................................... 23
• Changed fall time to split data and clock times in Table 2, Bus Timing Definitions ............................................................. 23
• Deleted rise time for data in Table 2, Bus Timing Definitions .............................................................................................. 23
• Deleted trace from SDA to SCL, and added missing connector dot to VS in Figure 52 ...................................................... 36
• Changed Shunt voltage input range parameter values in Electrical Characteristics table..................................................... 6
• Updated Figure 19 ................................................................................................................................................................ 13
• Changed second paragraph of Serial Bus Address section................................................................................................. 20
• Updated Figure 27 and note (1) ........................................................................................................................................... 21
• Updated Figure 28 and note (1) ........................................................................................................................................... 21
• Updated Figure 29 and note (1) ........................................................................................................................................... 22
• Updated Figure 30 and note (1) ........................................................................................................................................... 22
• Changed bit D15 in Power Valid Upper Limit Register ........................................................................................................ 34
• Changed bit D15 in Power Valid Lower Limit Register ........................................................................................................ 34
DEVICE DESCRIPTION
INA226 36-V, Bidirectional, Ultrahigh Accuracy, Low- or High-Side, I2C Out, Current and Power Monitor With Alert
INA219 26-V, Bidirectional, Zero-Drift, High-Side, I2C Out, Current and Power Monitor
INA209 26-V, Bidirectional, Low- or High-Side, I2C Out, Current and Power Monitor and High-Speed Comparator
INA210, INA211, INA212,
26-V, Bidirectional, Zero-Drift, High-Accuracy, Low- or High-Side, Voltage Out, Current Shunt Monitor
INA213, INA214
RGV Package
16-Pin VQFN
Top View
IN+2
IN 2
VPU
TC
16
15
14
13
IN 3 1 12 IN+1
IN+3 2 11 IN 1
GND 3 10 PV
VS 4 9 Critical
5
8
A0
SCL
SDA
Warning
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
Address pin. Connect to GND, SCL, SDA, or VS. Table 1 shows pin settings and
A0 5 Digital input
corresponding addresses.
Critical 9 Digital output Conversion-triggered critical alert; open-drain output.
GND 3 Analog Ground
Connect to load side of the channel 1 shunt resistor. Bus voltage is the measurement
IN–1 11 Analog input
from this pin to ground.
IN+1 12 Analog input Connect to supply side of the channel 1 shunt resistor.
Connect to load side of the channel 2 shunt resistor. Bus voltage is the measurement
IN–2 14 Analog input
from this pin to ground.
IN+2 15 Analog input Connect to supply side of the channel 2 shunt resistor.
Connect to load side of the channel 3 shunt resistor. Bus voltage is the measurement
IN–3 1 Analog input
from this pin to ground.
IN+3 2 Analog input Connect to supply side of the channel 3 shunt resistor.
PV 10 Digital output Power valid alert; open-drain output.
SCL 6 Digital input Serial bus clock line; open-drain input.
SDA 7 Digital I/O Serial bus data line; open-drain input/output.
TC 13 Digital output Timing control alert; open-drain output.
VPU 16 Analog input Pull-up supply voltage used to bias power valid output circuitry.
VS 4 Analog Power supply, 2.7 V to 5.5 V.
Warning 8 Digital output Averaged measurement warning alert; open-drain output.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Voltage Supply, VS 6 V
(2)
Differential (VIN+) – (VIN–) –26 26
IN+, IN–
Analog inputs Common-mode (VIN+) + (VIN–) / 2 –0.3 26 V
VPU 26
Critical, warning, power valid 6
Digital outputs V
Timing control 26
Data line, SDA (GND – 0.3) 6
Serial bus V
Clock line, SCL (GND – 0.3) (VS + 0.3)
Input, into any pin 5
Current mA
Open-drain, digital output 10
Operating, TA –40 125
Temperature Junction, TJ 150 °C
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) VIN+ and VIN– can have a differential voltage of –26 V to +26 V; however, the voltage at these pins must not exceed the range of
–0.3 V to +26 V.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
−10
−20
Population
Gain (dB)
−30
−40
−50
−60
1 10 100 1k 10k 100k
−160
−120
−80
−40
40
80
120
160
200
Frequency (Hz) G001
Input Offset Voltage (µV)
G003
Figure 1. Frequency Response Figure 2. Shunt Input Offset Voltage Production Distribution
50 130
Common−Mode Rejection (dB)
Input Offset Voltage (µV)
45
125
40
120
35
30 115
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
Temperature (°C) G004
Temperature (°C) G005
Figure 3. Shunt Input Offset Voltage vs Temperature Figure 4. Shunt Input Common-Mode Rejection Ratio vs
Temperature
400
350
Input Gain Error (m%)
300
Population
250
200
150
100
50
0
−50 −25 0 25 50 75 100 125 150
−0.3
−0.2
−0.1
0.1
0.2
0.3
0.4
Figure 5. Shunt Input Gain Error Production Distribution Figure 6. Shunt Input Gain Error vs Temperature
150
Population
100
50
0 2 4 6 8 10 12 14 16 18 20 22 24 26
−32
32
34
−24
24
−16
16
−8
8
Common−Mode Input Voltage (V) G008
Input Offset Voltage (mV) G009
Figure 7. Shunt Input Gain Error vs Common-Mode Voltage Figure 8. Bus Input Offset Voltage Production Distribution
8
4
Input Offset Voltage (mV)
0
Population
−4
−8
−12
−16
−50 −25 0 25 50 75 100 125 150
−0.1
0.1
−0.2
0.2
0
0.4
−0.3
0.3
Temperature (°C) G010
Input Gain Error (%) G011
Figure 9. Bus Input Offset Voltage vs Temperature Figure 10. Bus Input Gain Error Production Distribution
400 50
350 45
40
Input Bias Current (µA)
Input Gain Error (m%)
300
35
250 30 IB−
200 25
150 20
15
100 IB+
10
50 5
0 0
−50 −25 0 25 50 75 100 125 150 0 4 8 12 16 20 24 28
Temperature (°C) G012
Common−Mode Input Voltage (V) G013
Figure 11. Bus Input Gain Error vs Temperature Figure 12. Input Bias Current vs Common-Mode Voltage
400
25
IB− 350
Input Bias Current (µA)
250
15
200
IB+
10 150
100
5 IB+, IB−
50
0 0
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
Temperature (°C) G014 Temperature (°C) G015
Figure 13. Input Bias Current vs Temperature Figure 14. Input Bias Current vs Temperature (Shutdown)
500 3.5
450 3
Quiescent Current (µA)
250 0.5
200 0
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
Temperature (°C) G016 Temperature (°C) G017
650 300
Quiescent Current (µA)
600
250
550
200
500
150
450
100
400
350 50
300 0
0.01 0.1 1 4 0.01 0.1 1 4
Frequency (MHz) G018
Frequency (MHz) G019
Figure 17. Active IQ vs I2C Clock Frequency Figure 18. Shutdown IQ vs I2C Clock Frequency
8 Detailed Description
8.1 Overview
The INA3221 is a current-shunt and bus voltage monitor that communicates over an I2C- and SMBus-compatible
interface. The INA3221 provides digital shunt and bus voltage readings necessary for accurate decision making
in precisely-controlled systems, and also monitors multiple rails to maintain compliance voltages. Programmable
registers offer flexible configuration for measurement precision, and continuous versus single-shot operation. The
Register Maps section provides details of the INA3221 registers, beginning with Table 3.
Bus Voltage(1) X
Bus Voltage
Channel Power Valid
Lower Limit(2)
Shunt Voltage(1) X
Critical Limit(2)
Warning Limit(2)
Channel 2 Summation(1)
Channel 3
Summation Limit(2)
(1) Read-only.
(2) Read/write.
CAUTION
Based on the fixed 8-mV bus-voltage register LSB (for any channel), a full-scale
register value results in 32.76 V. However, the actual voltage applied to the INA3221
input pins must not exceed 26 V.
There are no special power-supply sequencing considerations between the common-mode input ranges and the
device power-supply voltage because they are independent of each other; therefore, the bus voltages can be
present with the supply voltage off and vice versa.
The INA3221 takes two measurements for each channel: one for shunt voltage and one for bus voltage. Each
measurement can be independently or sequentially measured, based on the mode setting (bits 2-0 in the
Configuration register). When the INA3221 is in normal operating mode (that is, the MODE bits of the
Configuration register are set to 111), the device continuously converts a shunt-voltage reading followed by a
bus-voltage reading. This procedure converts one channel, and then continues to the shunt voltage reading of
the next enabled channel, followed by the bus-voltage reading for that channel, and so on, until all enabled
channels have been measured. The programmed Configuration register mode setting applies to all channels.
Any channels that are not enabled are bypassed in the measurement sequence, regardless of mode setting.
The INA3221 has two operating modes, continuous and single-shot, that determine the internal ADC operation
after these conversions complete. When the INA3221 is set to continuous mode (using the MODE bit settings),
the device continues to cycle through all enabled channels until a new configuration setting is programmed.
The Configuration register MODE control bits also enable modes to be selected that convert only the shunt or
bus voltage. This feature further allows the device to fit specific application requirements.
In single-shot (triggered) mode, setting any single-shot convert mode to the Configuration register (that is, the
Configuration register MODE bits set to 001, 010, or 011) triggers a single-shot conversion. This action produces
a single set of measurements for all enabled channels. To trigger another single-shot conversion, write to the
Configuration register a second time, even if the mode does not change. When a single-shot conversion is
initiated, all enabled channels are measured one time and then the device enters a power-down state. The
INA3221 registers can be read at any time, even while in power-down. The data present in these registers are
from the last completed conversion results for the corresponding register. The conversion ready flag bit
(Mask/Enable register, CVRF bit) helps coordinate single-shot conversions, and is especially helpful during
longer conversion time settings. The CVRF bit is set after all conversions are complete. The CVRF bit clears
under the following conditions:
1. Writing to the Configuration register, except when configuring the MODE bits for power-down mode; or
2. Reading the Mask/Enable register.
In addition to the two operating modes (continuous and single-shot), the INA3221 also has a separate selectable
power-down mode that reduces the quiescent current and turns off current into the INA3221 inputs. Power-down
mode reduces the impact of supply drain when the device is not used. Full recovery from power-down mode
requires 40 µs. The INA3221 registers can be written to and read from while the device is in power-down mode.
The device remains in power-down mode until one of the active MODE settings are written to the Configuration
register.
When the power-valid conditions are met, and the PV pin pulls high, the INA3221 monitors if any bus-voltage
measurements drop below 9 V. This 9-V level is the default value programmed into the Power-Valid Lower-Limit
register. This value can also be reprogrammed when the INA3221 powers up to a supply voltage of at least 2.7
V. If any bus-voltage measurement on the three channels drops below the Power-Valid Lower-Limit register
value, the PV pin goes low, indicating that the power-valid condition is no longer met. At this point, the INA3221
resumes monitoring the power rails for a power-valid condition set in the Power-Valid Upper-Limit register.
The power-valid alert function is based on the power-valid conditions requirement that all three channels reach
the intended Power-Valid Upper-Limit register value. If all three channels are not used, connect the unused-
channel IN– pin externally to one of the used channels in order to use the power-valid alert function. If the
unused channel is not connected to a valid rail, the power-valid alert function cannot detect if all three channels
reach the power-valid level. Float the unused channel IN+ pin.
The power-valid function also requires that bus-voltage measurements are monitored. To detect changes in the
power-valid state, enable bus-voltage measurements through one of the corresponding MODE-bit settings in the
Configuration register. The single-shot bus-voltage mode periodically cycles between the bus-voltage
measurements to make sure that the power-valid conditions are met.
When all three bus-voltage measurements are completed, the device compares the results to the power-valid
threshold values to determine the power-valid state. The bus-voltage measurement values remain in the
corresponding channel output registers until the bus-voltage measurements are taken again, thus updating the
output registers. When the output registers are updated, the values are again compared to the power-valid
thresholds. Without taking periodic bus-voltage measurements, the INA3221 is unable to determine if the power-
valid conditions are maintained.
INA3321
VPU
RPU_ext
PV
RPU
Power-Valid RDIV(1)
Detection
Signal SB SB SB SB SB SB SB SB SB SB SB SB SB SB SB
Channel Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch
1 2 3 1 2 3 1 2 3 1 2 3 1 2 3
2.2 ms
28.6 ms
NOTE: The signal refers to the corresponding shunt (S) and bus (B) voltage measurement for each channel.
+ +
New ÷ Output
Sample AVG # Register
± +
26
1 Average
16 Averages
25
1024 Averages
Amplitude (mV)
24
23
22
21
20
1000 2000 3000 4000 5000 6000 7000
Samples G020
40
Voltage (µV)
í40
Conversion Time: 1.1 ms
í80
í120
0 200 400 600 800 1000
Number of Conversions
Power Supply
(0 V to 26 V)
RFILTER Ch 1
” 10
Ch 2
VIN+2
CFILTER ADC
VIN 2
RFILTER
” 10
Load 2 Ch 3
CFILTER: 0.1- F to 1- F
Ceramic Capacitor
The INA3221 inputs are specified to tolerate 26 V across the inputs. However, overload conditions are another
consideration for the INA3221 inputs. For example, a large differential-input scenario might be a short to ground
on the load side of the shunt. This type of event results in the full power-supply voltage applied across the shunt,
if supported by the power supply or energy-storage capacitors. Keep in mind that removing a short to ground
may result in inductive kickbacks that can exceed the 26-V differential and common-mode rating of the INA3221.
Inductive kickback voltages are best controlled by zener-type transient-absorbing devices (commonly called
transzorbs) combined with sufficient energy-storage capacitance.
In applications that do not have large energy-storage electrolytic capacitors on one or both sides of the shunt, an
input overstress condition can result from an excessive dV/dt of the voltage applied to the input. A hard physical
short is the most likely cause of this event, particularly in applications without large electrolytic capacitors
present. This problem occurs because an excessive dV/dt can activate the INA3221 ESD protection in systems
where large currents are available. Testing has demonstrated that the addition of 10-Ω resistors in series with
each INA3221 input sufficiently protects the inputs against this dV/dt failure up to the 26-V device rating.
Selecting these resistors in the range noted has minimal effect on accuracy.
8.5 Programming
8.5.1 Bus Overview
The INA3221 offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are
essentially compatible with one another.
The I2C interface is used throughout this data sheet as the primary example, with the SMBus protocol specified
only when a difference between the two systems is discussed. Two I/O lines, the serial clock (SCL) and data
signal line (SDA), connect the INA3221 to the bus. Both SCL and SDA are open-drain connections.
The device that initiates a data transfer is called a master, and the devices controlled by the master are slaves.
The bus must be controlled by the master device that generates the SCL, controls the bus access, and
generates start and stop conditions.
To address a specific device, the master initiates a start condition by pulling SDA from a high to a low logic level
while SCL is high. All slaves on the bus shift in the slave address byte on the SCL rising edge, with the last bit
indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed
responds to the master by generating an acknowledge bit and pulling SDA low.
Data transfer is then initiated and eight bits of data are sent, followed by an acknowledge bit. During data
transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a
start or stop condition.
After all data are transferred, the master generates a stop condition by pulling SDA from low to high while SCL is
high. The INA3221 includes a 28-ms timeout on the interface to prevent locking up the bus.
SCL
SDA 1 0 0 0 0 0 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0
(1) The value of the Slave Address Byte is determined by the A0 pin setting; see Table 1.
Register writes begin with the first byte transmitted by the master. This byte is the slave address, with the R/W
bit low. The INA3221 then acknowledges receipt of a valid address. The next byte transmitted by the master is
the register address that data are written to. This register address value updates the register pointer to the
desired register. The next two bytes are written to the register addressed by the register pointer. The INA3221
acknowledges receipt of each data byte. The master terminates data transfer by generating a start or stop
condition.
When reading from the INA3221, the last value stored in the register pointer by a write operation determines
which register is read during a read operation. To change the register pointer for a read operation, write a new
value to the register pointer. This write is accomplished by issuing a slave address byte with the R/W bit low,
followed by the register pointer byte. No additional data are required. The master then generates a start condition
and sends the slave address byte with the R/W bit high to initiate the read command. The next byte is
transmitted by the slave and is the most significant byte of the register indicated by the register pointer. This byte
is followed by an acknowledge from the master; then the slave transmits the least significant byte. The master
acknowledges receipt of the data byte. The master terminates data transfer by generating a not-acknowledge
after receiving any data byte, or generating a start or stop condition. If repeated reads from the same register are
desired, it is not necessary to continually send the register pointer bytes; the INA3221 retains the register pointer
value until it is changed by the next write operation.
Figure 28 and Figure 29 show the write and read operation timing diagrams, respectively. Note that register
bytes are sent most-significant byte first, followed by the least significant byte.
1 9 1 9 1 9
SCL
Frame 1: Two-Wire Slave Address Byte (1) Frame 2: Data MSByte Frame 3: Data LSByte
(1) The value of the slave address byte is determined by the A0 pin setting; see Table 1.
1 9 1 9 1 9
SCL
Frame 1: Two-Wire Slave Address Byte(1) Frame 2: Data MSByte(2) Frame 3: Data LSByte(2)
(1) The value of the slave address byte is determined by the A0 pin setting; see Table 1.
(2) Read data are from the last register pointer location. If a new register is desired, the register pointer must be updated.
See Figure 27.
(3) The master can also send an ACK.
Figure 30 shows the timing diagram for the SMBus Alert response operation.
1 9 1 9
SCL
SDA 0 0 0 1 1 0 0 R/W 1 0 0 0 0 0 A0 0
Frame 1: SMBus ALERT Response Address Byte Frame 2: Slave Address Byte(1)
(1) The value of the Slave Address Byte is determined by the A0 pin setting; see Table 1.
t(LOW)
tr tfCL
SCL
SDA
t(BUF)
P S S P
(1) Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not production tested.
A0 = A1 = 0.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
VS (Supply
VIN+1 VIN±1 Voltage) 10 k
Power Supply
(0 V to 26 V) SDA
I2C-
CH 1 and SCL
Bus SMBus-
CH 2 Voltages 1-3 Compatible A0
VIN+2
Interface VPU VS
Shunt
ADC
VIN±2 Voltages 1-3
Critical Limit 10 k
Alerts 1-3 VPU
Power Valid (PV)
Load 2 CH 3 Shunt Voltage
Critical
Sum Alerts
Warning
Timing Control (TC)
GND
VIN+3 VIN±3
Power Supply
(0 V to 26 V) Load 3
Critical Alert
(2 V/div)
(2 V/div)
(50 mV/div)
Input/Limit
Input/Limit
Figure 53. Critical Alert Response for 1.1-ms Conversion Figure 54. Critical Alert Response for 588-µs Conversion
Time Time
11 Layout
To Load
IN 2
VPU
TC
IN 3 IN+1
IN+3 IN 1
Connect
GND PV
Supply to VPU
Bypass
Capacitor Critical
VS Critical
Output
To Bus Power
Warning
To Load
SCL
SDA
Supply
A0
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
INA3221AIRGVR ACTIVE VQFN RGV 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 INA
3221
INA3221AIRGVT ACTIVE VQFN RGV 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 INA
3221
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
• Automotive: INA3221-Q1
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
Width (mm)
H
W
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGV 16 VQFN - 1 mm max height
4 x 4, 0.65 mm pitch PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224748/A
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PACKAGE OUTLINE
RGV0016A SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4.15
B A
3.85
4.15
3.85
C
1.0
0.8
SEATING PLANE
0.08 C
0.05
0.00
2.16 0.1
2X 1.95
SYMM (0.2) TYP
5 8
EXPOSED (0.37) TYP
THERMAL PAD
4 9
2X 1.95 SYMM 17
2.16 0.1
12X 0.65
1 12
PIN 1 ID 0.38
16X
16 13 0.23
0.1 C A B
0.65
16X 0.05
0.45
4219037/A 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGV0016A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 2.16)
SYMM
16 13 SEE SOLDER MASK
DETAIL
16X (0.75)
12
16X (0.305) 1
17 SYMM
12X (0.65) (3.65)
(0.83)
4
9
(R0.05) TYP
( 0.2) TYP
VIA
5 8
(0.83)
(3.65)
0.07 MIN
0.07 MAX ALL AROUND
ALL AROUND
METAL UNDER
METAL EDGE SOLDER MASK
EXPOSED METAL
SOLDER MASK EXPOSED SOLDER MASK
OPENING METAL OPENING
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGV0016A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.58) TYP
16 13
16X (0.75)
16X (0.305) 1 12
(0.58) TYP
SYMM 17
12X (0.65) (3.65)
4X (0.96)
4
9
(R0.05) TYP
5 8
4X (0.96)
SYMM
(3.65)
EXPOSED PAD 17
79% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219037/A 06/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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