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    EC6009 Unit 5 IQ

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    shahul hameed
    The document discusses advanced computer architecture topics related to caches, memory, storage, and I/O systems. It covers cache hit and miss rates, write-through and write-back caches, average memory access time, disk mirroring techniques, bus architectures, address translation, storage devices like disks and tapes, RAID configurations, and factors for designing high-performance I/O systems. The document contains questions and answers on these topics in a question-answer format.

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    EC6009 Unit 5 IQ

    Uploaded by

    shahul hameed
    17 views3 pages
    The document discusses advanced computer architecture topics related to caches, memory, storage, and I/O systems. It covers cache hit and miss rates, write-through and write-back caches, average memory access time, disk mirroring techniques, bus architectures, address translation, storage devices like disks and tapes, RAID configurations, and factors for designing high-performance I/O systems. The document contains questions and answers on these topics in a question-answer format.

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    EC6009-Unit-5-IQ

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    The document discusses advanced computer architecture topics related to caches, memory, storage, and I/O systems. It covers cache hit and miss rates, write-through and write-back caches, average memory access time, disk mirroring techniques, bus architectures, address translation, storage devices like disks and tapes, RAID configurations, and factors for designing high-performance I/O systems. The document contains questions and answers on these topics in a question-answer format.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    17 views3 pages

    EC6009 Unit 5 IQ

    Uploaded by

    shahul hameed
    The document discusses advanced computer architecture topics related to caches, memory, storage, and I/O systems. It covers cache hit and miss rates, write-through and write-back caches, average memory access time, disk mirroring techniques, bus architectures, address translation, storage devices like disks and tapes, RAID configurations, and factors for designing high-performance I/O systems. The document contains questions and answers on these topics in a question-answer format.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 3

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    net

    DEPARTMENT OF ELECTRONICS AND COMMUNICATION


    ENGINEERING

    EC6009 - ADVANCED COMPUTER ARCHITECTURE

    UNIT-V

    PART-A
    1. What is cache miss and cache hit?
    Cache Miss: When the CPU finds a requested data item in the cache, it is called cache miss.
    Cache Hit: When the CPU finds a requested data item is available in the cache, it is called cache
    hit.

    2. What is write through and write back cache?


    Write through cache: The information is written to both the block in the cache and to the block in
    the lower level memory.
    Write Back Cache: The information is written only to the block in the cache. The modified cache
    block is written to main memory only when it is replaced.

    3. What is Miss Rate and Miss Penalty?


    Miss Rate is the fraction of cache access that results in a miss.
    Miss Penalty depends on the number of misses and clock per miss.

    4. Write the equation of Average memory access time.

    Average memory access time = hit time+miss rate X Miss Penalty

    5. What is stripping?

    Spreading multiple data over multiple disks is called stripping, which automatically forces
    accesses to several disks.

    6. What is disk mirroring? And write the drawbacks of disk mirroring.

    Disks in the configuration are mirrored or copied to another disk. With this arrangement data on
    the failed disks can be replaced by reading it from the other mirrored disks.
    Drawback: writing onto the disk is slower since the disks are not synchronized, seek time will be
    different.
    It imposes 50% space penalty hence expensive.

    7. Mention the factors that measure I/O performance ?


    Diversity capacity, response time, throughput, interference with CPU execution.

    8. What is transaction time?


    The sum of entry time, response time and think time is called transaction time.

    SANGEETHA / SNSCE / ECE / VII SEM / ACA UNIT 5 Page 1


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    9. State little law?


    Little law relates the average number of tasks in the system. It relates to Average arrival rate of
    new tasks with the average time to perform a task.

    10. What are the steps to design an I/O system?

    Naïve cost – performance design and evaluation 


    Availability of naïve design
    Response time
    Realistic cost performance, design and evaluation 
    Realistic design for availability and its evaluation 

    11. Write the classification of buses.

    I/O buses – these buses are lengthy and have any types of devices connected to it. CPU memory
    buses – They are short and generally of high speed.
    12. What is bus master?

    Bus master are devices that can initiate the read or write transaction.
    Eg. Processor – processor are always has the bus mastership.

    13. Mention the advantages of using bus master.

    It offers higher bandwidth by using packets, as opposed to holding the bus for full transaction.

    14. What is split transaction?

    The idea behind this is to split the bus into request and replies, so that the bus can be used in the
    time between request and the reply.

    15. What are the measures of latency in memory technology?


    Access Time: Is the time between when a read is required and when the desired word arrives.
    Cycle Time: Is the minimum time between requests to memory.

    SANGEETHA / SNSCE / ECE / VII SEM / ACA UNIT 5 Page 2


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    PART B
    1. Explain in detail about the vaious optimization techniques for improving the cache
    performance. (16)

    Cache performance
    There are 17 cache optimizations into four categories:
    First Miss Penalty Reduction Technique: Multi-Level Caches
    Second Miss Penalty Reduction Technique: Critical Word First and Early Restart Third Miss Penalty
    Reduction Technique: Giving Priority to Read Misses over Writes
    Fourth Miss Penalty Reduction Technique: Merging Write Buffer Fifth Miss Penalty Reduction
    Technique: Victim Caches
    First Miss Rate Reduction Technique: Larger Block Size Second Miss Rate Reduction Technique: Larger
    caches Miss Rate Reduction Technique: Higher Associativity
    Fourth Miss Rate Reduction Technique: Way Prediction and Pseudo-Associative Caches
    Fifth Miss Rate Reduction Technique: Compiler Optimizations

    2. What is virtual memory? write techniques for fast address translation


    Techniques for Fast Address Translation
    Selecting a Page Size

    3. Explain various types of storage devices (16)


    Magnetic Disks
    Optical Disks
    Magnetic Tape
    Automated Tape Libraries
    Flash Memory

    4. Explain the buses and i/o devices (16)


    Bus Design Decisions
    Bus Standards
    Interfacing Storage Devices to the CPU

    5.Briefly explain raid (or) redundant arrays of inexpensive disks (8)


    No Redundancy (RAID 0)
    Mirroring (RAID 1)
    Bit-Interleaved Parity (RAID 3)
    Block-Interleaved Parity and Distributed Block-Interleaved Parity (RAID 4 and RAID 5)
    6.Explain the design of i/o systems and its performance. (16)
    o The CPU

    o The memory system:

    o Internal and external caches, Main Memory

    o The underlying interconnection (buses)

    SANGEETHA / SNSCE / ECE / VII SEM / ACA UNIT 5 Page 3


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